Witam Jakiś czas temu, spaliło się u mnie w karcie graficznej Gigabyte Radeon R9 270 kilka elementów, ogólnie historia jest długa, a na obecną chwilę został mi do wymiany tylko tranzystor 26D41. Całość jest opisana tutaj na Pclabie (http://forum.pclab.pl/topic/1260596-Gigabyte-R9-270-spalony-element-smd), a to co jest istotne dla tego wątku opiszę tutaj. Wymieniłem kolejno uszkodzony rezystor 0 Ohm i mosfet Nokis PA102fdg i tak właściwie został mi do wymiany ten tranzystor, ale problem jest taki, że nigdzie nie da się znaleźć dokumentacji ani jakiejkolwiek informacji na temat tego tranzystora. Szukałem w różnych katalogach z elementami smd bezskutecznie. Dlatego zwracam się tutaj z prośbą o pomoc w doborze zamiennika tego elementu. To co wiem na temat tego tranzystora to właściwie to, że jest on w obudowie SOT23 i może pracować przy napięciu do 12V. Schemat zasilania wentylatorów wygląda mniej więcej tak: złącze zasilania wentylatorów->mosfet->rezystor 0 ohm->tranzystor SOT23->kontroler uP1542S. Dołączam zdjęcia pcb, jak i dokumentację kontrolera może tam będą pomocne informacje. https://obrazki.elektroda.pl/1478984300_1569156430_thumb.jpg https://obrazki.elektroda.pl/3415011300_1569156437_thumb.jpg Z góry dziękuję za pomoc
uP1542
5V/12V Synchronous-Rectified Buck Controller
Features
General Description
The uP1542 is a compact synchronous-rectified buck
controller specifically designed to operate from 5V or 12V
supply voltage and to deliver high quality output voltage
as low as 0.6V for uP1542S/U (linear OCP).
The uP1542 adopts constant frequency, voltage mode
control scheme, featuring easy-to-use, low external
component count, and fast transient response. Fixed
300kHz operation provides an optimal level of integration
to reduce size and cost of the power supply.
This controller integrates internal MOSFET drivers that
support 12V+12V bootstrapped voltage for high efficiency
power conversion. The bootstrap diode is built-in to simplify
the circuit design and minimize external part count.
Other features include internal soft start, over/under
voltage protection, over current protection and shutdown
function. With aforementioned functions, this part provides
customers a compact, high efficiency, well-protected and
cost-effective solutions. This part is available in PSOP8L and WDFN2x2-8L package.
Pin Configuration
Operates from 5V or 12V Supply Voltage
3.3V to 12V VIN Input Range
VREF with 1.0% Accuracy:
uP1542S/U: 0.6V VREF
uP1542T/Q/V: 0.8V VREF
Stand Alone Mode Operation
Simple Single-Loop Control Design
Voltage-Mode PWM Control
Fast Transient Response
Fixed 300kHz Switching Frequency
High-Bandwidth Error Amplifier
0% to 90% Duty Cycle
Lossless, Adjuatable Over Current Protection
Uses Lower MOSFET RDS(ON)
uP1542S/U: Linear OCP
uP1542T/Q/V: Fixed OCP
Internal Soft Start
BOOT
UG
2
OCS
3
LG
8
4
9
GND
PH
Integrated Boot Diode
7
COMP/EN
PSOP-8L and WDFN2x2-8L Package
6
FB
RoHS Compliant and Halogen Free
5
1
VCC
PSOP-8L (uP1542S)
BOOT
2
GND
3
LG
Power Supplies for Microprocessors or
Subsystem Power Supplies
8
4
9
GND
PH
Cable Modems, Set Top Boxes, and DSL Modems
7
COMP/EN
6
FB
Industrial Power Supplies; General Purpose
Supplies
5
1
UG
VCC
5V or 12V Input DC-DC Regulators
PSOP-8L (uP1542Q/T/V)
BOOT 1
UG 2
OCS 3
Applications
Low-Voltage Distributed Power Supplies
8 PH
GND
LG 4
7 COMP/SD
6 FB
5 VCC
WDFN2x2-8L (uP1542U)
uP1542-DS-F00A0, Apr. 2018
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1
uP1542
Ordering Information
Order Number
Package Type
uP1542TSU8
uP1542QSU8
uP1542VSU8
uP1542UDD8
WDFN2x2-8L
Top Marking
linear OCP
uP1542S
0.8V
fixed OCP@225mV
uP1542T
0.8V
fixed OCP@300mV
uP1542Q
0.8V
PSOP-8L
Remark
0.6V
uP1542SSU8
VREF
fixed OCP@375mV
uP1542V
0.6V
linear OCP
DJ
Note:
(1) Please check the sample/production availability with uPI representatives.
(2) uPI products are compatible with the current IPC/JEDEC J-STD-020 requirement. They are halogen-free,
RoHS compliant and 100% matte tin (Sn) plating that are suitable for use in SnPb or Pb-free soldering processes.
Functional Pin Description
Pin Name
Pin Function
BOOT
B ootstrap Supply for the floati ng upper gate dri ver. C onnect the bootstrap capaci tor between
BOOT pin and the PH pin to form a bootstrap circuit. The bootstrap capacitor provides the charge
to turn on the upper MOSFET.
UG
Upper Gate Driver Output. Connect this pin to the gate of upper MOSFET. This pin is monitored
by the adaptive shoot-through protection circuitry to determine when the upper MOSFET has turned
off.
GND
OCS
Over Current Protection Setting. Connect a resistor from this pin to GND to set the OCP level.
LG
Low er Gate Driver Output. Connect this pin to the gate of lower MOSFET. This pin is monitored
by the adaptive shoot-through protection circuitry to determine when the lower MOSFET has turned
off.
VC C
Supply Voltage. This pin provides the bias supply for the uP1542 and the lower gate driver. Connect
a well-decoupled 4.5V to 13.2V supply voltage to this pin. Ensure that a decoupling capacitor is
placed near the IC.
FB
Feedback Voltage. This pin is the inverting input to the error amplifier. A resistor divider from the
output to GND is used to set the regulation voltage. Use this pin in combination with the COMP/EN
pin to compensate the voltage control feedback loop of the converter.
COMP/EN
Error Amplifier Output. This is the output of the error amplifier and the non-inverting input of the
PWM comparator. Use this pin in combination with the FB pin to compensate the voltage-control
feedback loop of the converter. Pulling COMP/EN to a level below 0.3V disables the controller and
causes the oscillator to stop, the UG and LG outputs to be held low.
PH
PHASE Sw itch Node. Connect this pin to the source of the upper MOSFET and the drain of the
lower MOSFET. This pin is used as the sink for the UG driver, and to monitor the voltage drop across
the lower MOSFET for over current protection. This pin is also monitored by the adaptive shootthrough protection circuitry to determine when the upper MOSFET has turned off.
Exposed Pad
2
Ground.
Ground. The exposed pad is the dominate heat conducting path and should be well soldered to the
PCB with multiple vias for optimal thermal performance.
uP1542-DS-F00A0, Apr. 2018
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uP1542
Typical Application Circuit
VIN
VCC
UG
GND
BOOT
VOUT
PH
COMP/EN
R1
LG
Shut
Down
FB
OCS
R2
Functional Block Diagram
OCS
Soft Start
Enable
Enable
Logic
SS
Protection
0.3V
COMP/EN
POR
POR
1.0V
FB
uP1542-DS-F00A0, Apr. 2018
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Oscillator
OVP
BOOT
UG
VOCP
OCP
PWM
Comparator
VREF
0.6V/uP1542S/U
1.25xVREF
Internal
Regulator
PWM
Error
Amplifier
VFB
4.2V
VDD
VCC
Gate
Control
Logic
PH
VCC
LG
VFB
0.3xVREF
UVP
GND
3
uP1542
Functional Description
The uP1542 is a compact synchronous-rectified buck
controller specifically designed to operate from 5V or 12V
supply voltage and to deliver high quality output voltage
as low as 0.6V.
Supply Voltage
The VCC pin receives a well-decoupled 4.5V to 13.2V
supply voltage to power the control circuit, the lower gate
driver and the bootstrap circuit for the higher gate driver.
A minimum 1uF ceramic capacitor is recommended to
bypass the supply voltage. Place the bypassing capacitor
physically near the IC.
An internal linear regulator regulates the supply voltage
into a 4.2V voltage VDD for internal control logic circuit.
No external bypass capacitor is required for filtering the
VDD voltage.
The uP1542 integrates MOSFET gate drives that are
powered from the VCC pin and support 12V+12V driving
capability. A bootstrap diode is embedded to facilitate PCB
design and reduce the total BOM cost. No external
Schottky diode is required. Converters that consist of
uP1542 feature high efficiency without special
consideration on the selection of MOSFETs.
Note: The embedded bootstrap diode is not a
Schottky diode having a 0.8V forward voltage.
External Schottky diode is highly recommended if the
VCC voltage is expected to be lower than 5.0V.
Otherwise the bootstrap diode may be too low for the
device to work normally.
Power On Reset and Chip Enable
A power on reset (POR) circuitry continuously monitors
the supply voltage at VCC pin. Once the rising POR
threshold is exceeded, the uP1542 sets itself to active
state and is ready to accept chip enable command. The
rising POR threshold is typically 4.2V at VCC rising.
The COMP/EN is a multifunctional pin: control loop
compensation and chip enable as shown in Figure 1. An
Enable Comparator monitors the COMP/EN pin voltage
for chip enable. A signal level transistor is adequate to
pull this pin down to ground and shut down the uP1542.
An 80uA current source charges the external
compensation network with 1.0V ceiling when this pin is
released. If the voltage at COMP/EN pin exceeds 0.3V,
the uP1542 initiates its softstart cycle.
1V
0.3V
COMP/EN
Chip
Enable
Disable
FB
Enable
uP1542
VREF
Error
Amplifier
Figure 1. Chip Enable Function
Soft Start
A built-in Soft Start is used to prevent surge current from
power supply input during turn on (referring to the
Functional Block Diagram). The error amplifier is a threeinput device. Reference voltage VREF or the internal soft
start voltage SS whichever is smaller dominates the
behavior of the non-inverting inputs of the error amplifier.
SS internally ramps up to VCC and the output voltage will
follow the SS signal and ramp up smoothly to its target
level.
The SS signal keeps ramping up after it exceeds the
reference voltage VREF. However, the reference voltage
VREF takes over the behavior of error amplifier after SS & gt;
VREF. When the SS signal climb to 1.3 x VREF, the uP1542
claims the end of softstart cycle and enables the over and
under voltage protection of the output voltage.
Figure 2 shows a typical start up interval for uP1542 where
the COMP/SD pin has been released from a grounded
(system shutdown) state.
The internal 80uA current source starts to charge the
compensation network after the COMP/SD pin is released
from grounded at T1. The COMP/SD exceeds 0.3V and
enables the uP1542 at T2. The COMP/SD continues
ramping up and stays at 1V before the SS starts ramping
up at T3. The uP1542 initializes itself such as current limit
level setting (see the relative section) during the time
interval between T2 and T3. The output voltage follows
the internal SS and ramps up to its final level during T3
and T4. At T4, the reference voltage VREF takes over the
behavior of the error amplifier as the internal SS crosses
VREF. The internal SS keeps ramping up and reaches 1.3 x
VREF at T5, where the uP1542 asserts the end of softstart
cycle.
The 80uA current source keeps charging the COMP pin
to its ceiling until the feedback loop boosts the COMP pin
higher than 0.8V according to the feedback signal. The
current source is cut off when VCOMP is higher than 1.0V
during normal operation.
4
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uP1542
Functional Description
Ramp
COMP/EN
Figure 3. Softstart where VIN does not Present Initially.
Output Voltage Selection
0.3V
SS
VREF
VOUT
T1 T3
T2
T4
T5
COMP (1V/Div)
VOUT (1V/Div)
The output voltage can be programmed to any level
between the reference voltage VREF up to the 90% of VIN
supply. The lower limitation of output voltage is caused by
the internal reference. The upper limitation of the output
voltage is caused by the maximum available duty cycle
(90% typical). This is to leave enough time for over current
detection. Output voltage out of this range is not allowed.
An voltage divider sets the output voltage (refer to the
Typical Application Circuit on page 3 for detail). In real
applications, choose R1 in 1kΩ ~ 10kΩ range and choose
appropriate R2 according to the desired output voltage.
VOUT = VREF ×
R1 + R2
R2
Over Current Protection (OCP)
LGATE (10V/Div)
Time 2ms/Div
Figure 2. Softstart Behavior of uP1542.
Power Input Detection
The uP1542 detects PH voltage for the present of power
input when the UG turns on the first time. If the PH voltage
does not exceed 1.0V when the UG turns on, the uP1542
asserts that power input in not ready and stops the softstart
cycle. Another softstart cycle is initiate after a 6ms time
delay. Figure 4 shows the start up interval where VIN does
not present initially.
The uP1542 detects voltage drop across the lower
MOSFET (VPHASE) for over current protection when it is
turned on. If VPHASE is lower than the user-programmable
voltage VOCP, the uP1542 asserts OCP and shuts down
the converter. The OCP level can be programmed by OCS
pin (uP1542S/U) or fixed at 300mV (uP1542Q).
The uP1542 sources a 20uA current source out of OCS
pin. Connect resistor ROCS at OCS pin to create voltage
level VOCS for OCP setting. The maximum of VOCP should
not be larger than 375mV.
VOCS =
20uA × R OCS
4
VOCP = VOCS
IOCP =
VOCP
RDS( ON)
(A)
For example:
If VOCP = 375mV, and RDS(ON) = 10mΩ, the IOCP will be 37.5A.
VIN (5V/Div)
If VOCP = 225mV, and RDS(ON) = 10mΩ, the IOCP will be 22.5A.
Over Voltage and Under Voltage Protection
VOUT (1V/Div)
LGATE (10V/Div)
IL (5A/Div)
Time 4ms/Div
uP1542-DS-F00A0, Apr. 2018
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The uP1542 asserts over voltage protection if the feedback
voltage VFB is higher than 125% of reference voltage VREF.
The uP1542 asserts under voltage protection if the
feedback voltage VFB is lower than 30% of reference
voltage VREF after soft start end. The uP1542 turns off
both higher and lower gate drivers upon UVP and turns
on lower gate driver upon OVP. Both UVP and OVP are
latch-off type and can be reset by POR or toggling the
COMP/EN pin.
5
uP1542
Absolute Maximum Rating
(Note 1)
Supply Input Voltage, VCC -------------------------------------------------------------------------------------- -0.3V to +15V
BOOT to PH --------------------------------------------------------------------------------------------------------------------- -0.3V to +15V
PH to GND
DC ------------------------------------------------------------------------------------------------------------------------- -0.7V to 15V
& lt; 200ns --------------------------------------------------------------------------------------------------------------------- -8V to 30V
BOOT to GND
DC --------------------------------------------------------------------------------------------------------------- -0.3V to VCC + 15V
& lt; 200ns ------------------------------------------------------------------------------------------------------------------ -0.3V to 42V
UG to PH
DC------------------------------------------------------------------------------------------------------- -0.3V to (BOOT - PH +0.3V)
& lt; 200ns ------------------------------------------------------------------------------------------------ -5V to (BOOT - PH + 0.3V)
LG to GND
DC ---------------------------------------------------------------------------------------------------------- -0.3V to + (VCC + 0.3V)
& lt; 200ns ---------------------------------------------------------------------------------------------------------- -5V to VCC + 0.3V
Other Pins -------------------------------------------------------------------------------------------------------------------------- -0.3V to +6V
Storage Temperature Range ----------------------------------------------------------------------------------------------- -65OC to +150OC
Junction Temperature --------------------------------------------------------------------------------------------------------------------- 150OC
Lead Temperature (Soldering, 10 sec) ------------------------------------------------------------------------------------------------ 260OC
ESD Rating (Note 2)
HBM (Human Body Mode) ------------------------------------------------------------------------------------------------------- 2kV
MM (Machine Mode) --------------------------------------------------------------------------------------------------------------- 200V
Thermal Information
Package Thermal Resistance (Note 3)
PSOP-8L θJA ----------------------------------------------------------------------------------------------------------------- 47OC/W
WDFN2x2-8L θJA ---------------------------------------------------------------------------------------------------------- 155OC/W
PSOP-8L θJC ---------------------------------------------------------------------------------------------------------------- 17.9OC/W
WDFN2x2-8L θJC ------------------------------------------------------------------------------------------------------------- 20OC/W
Power Dissipation, PD @ TA = 25OC
PSOP-8L ----------------------------------------------------------------------------------------------------------------------------- 2.13W
WDFN2x2-8L ------------------------------------------------------------------------------------------------------------------------ 0.65W
Recommended Operation Conditions
(Note 4)
Operating Junction Temperature Range ------------------------------------------------------------------------------- -40OC to +125OC
Operating Ambient Temperature Range --------------------------------------------------------------------------------- -40OC to +85OC
Supply Input Voltage, VCC ----------------------------------------------------------------------------------------------------- +4.5V to 13.2V
6
uP1542-DS-F00A0, Apr. 2018
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uP1542
Electrical Characteristics
(VCC = 12V, TA = 25OC, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Units
4.5
--
13.2
V
UG and LG Open, VCC = 12V,
Switching
--
3
--
mA
VFB = VREF + 0.1V, No Switching
--
1.3
--
mA
3.0
--
13.2
V
4.0
4.2
4.4
V
Supply Input
Supply Voltage
VCC
Supply Current
ICC
Quiescent Supply Current
Power Input Voltage
ICC_Q
VIN
Pow er On Reset
POR Threshold
VCCRTH
POR Hysteresis
VCCHYS
--
0.5
--
V
fOSC
270
300
330
kHz
V C C = 12V
--
3
--
VP-P
uP1542S/U
0.594
0.60
0.606
V
uP1542T/Q/V
0.792 0.800 0.808
V
VCC rising
Sw itching Frequency
Free Running Frequency
Ramp Amplitude
∆VOSC
Reference Voltage
Internal Reference Voltage Accuracy
V FB
Error Amplifier
Open Loop DC Gain
Gain-Bandwidth Product
Slew Rate
AO
Guaranteed by Design
55
70
--
dB
GBW
Guaranteed by Design
--
10
--
MHz
SR
Guaranteed by Design
3
6
--
V/us
600
800
1000
uA/V
Transconductance
Output Source Current
VFB & lt; VREF
80
120
--
uA
Output Sink Current
VFB & gt; VREF
80
120
--
uA
-1.0
0
1.0
mV
--
0.1
1.0
nA
Input Offset Voltage
Input Leakage Current
PWM Controller Gate Drivers
Upper Gate Source
RUG_SRC IUG = 100mA Source
--
3
5
Ω
Upper Gate Sink
RUG_SNK IUG = 100mA Sink
--
1.5
3
Ω
Lower Gate Source
RLG_SRC IUG = 100mA Source
--
3
5
Ω
Lower Gate Sink
RLG_SNK IUG = 100mA Sink
--
1
2
Ω
uP1542-DS-F00A0, Apr. 2018
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7
uP1542
Electrical Characteristics
Parameter
Symbol
Test C onditions
Min
Typ
Max
U nits
PWM C ontroller Gate D rivers
PH Falli ng to LG Ri si ng D elay
VPH & lt; 1.2V to VLG & gt; 1.2V
--
30
--
ns
LG Falli ng to UG Ri si ng D elay
VLG & lt; 1.2V to (VUG - VPH ) & gt; 1.2V
--
30
--
ns
Mi ni mum D uty C ycle
--
0
--
%
Maxi mum D uty C ycle
85
90
95
%
from C OMP/EN released to VOUT i n
regulati on
--
2.5
--
ms
Soft Start
Soft Start Ti me
Protection
Under Voltage Protecti on
VFB_UVP
Percentage of VREF
--
30
--
%
Over Voltage Protecti on
VFB_OVP
Percentage of VREF
--
125
--
%
--
20
--
us
uP1542T
--
-225
--
uP1542Q
--
-300
--
uP1542V
--
-375
--
-375
--
-100
mV
--
20
--
uA
--
3.33
--
us
0.25
0.3
0.35
V
--
150
--
Over Voltage Protecti on D elay
Over C urrent Threshold
V PH
OC P Programmable Range
VOCP
OC S Source C urrent for OC P
Setti ng
uP1542S/U
IOCS
OC P D elay Ti me
D i sable Threshold
VCOMP/EN
Over Temperature Protecti on
mV
O
C
Note 1. Stresses listed as the above “ Absolute Maximum Ratings” may cause permanent damage to the device.
These are for stress ratings. Functional operation of the device at these or any other conditions beyond
those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may remain possibility to affect device reliability.
Note 2. Devices are ESD sensitive. Handling precaution recommended.
Note 3. θJA is measured in the natural convection at TA = 25°C on a low effective thermal conductivity test board of
JEDEC 51-3 thermal measurement standard.
Note 4. The device is not guaranteed to function outside its operating conditions.
8
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uP1542
Application Information
Component Selection Guidelines
The selection of external component is primarily
determined by the maximum load current and begins with
the selection of power MOSFET switches. The desired
amount of ripple current and operating frequency largely
determines the inductor value. Finally, CIN is selected for
its capability to handle the large RMS current into the
converter and COUT is chosen with low enough ESR to
meet the output voltage ripple and transient specification.
Power MOSFET Selection
The uP1542 requires two external N-channel power
MOSFETs for upper (controlled) and lower (synchronous)
switches. Important parameters for the power MOSFETs
are the breakdown voltage V(BR)DSS, on-resistance RDS(ON),
reverse transfer capacitance CRSS, maximum current
I DS(MAX) , gate supply requirements, and thermal
management requirements.
The gate drive voltage is supplied by VCC pin that receives
4.5V~13.2V supply voltage. When operating with a
7~13.2V power supply for VCC, a wide variety of
NMOSFETs can be used. Logic-level threshold MOSFET
should be used if the input voltage is expected to drop
below 7V. Caution should be exercised with devices
exhibiting very low VGS(ON) characteristics. The shootthrough protection present aboard the uP1542 may be
circumvented by these MOSFETs if they have large
parasitic impedances and/or capacitances that would
inhibit the gate of the MOSFET from being discharged
below its threshold level before the complementary
MOSFET is turned on. Also avoid MOSFETs with
excessive switching times; the circuitry is expecting
transitions to occur in under 30ns or so.
In high-current applications, the MOSFET power
dissipation, package selection and heatsink are the
dominant design factors. The power dissipation includes
two loss components: conduction loss and switching loss.
The conduction losses are the largest component of power
dissipation for both the upper and the lower MOSFETs.
These losses are distributed between the two MOSFETs
according to duty cycle. Since the uP1542 is operating in
continuous conduction mode, the duty cycles for the
MOSFETs are:
D UP =
V OUT
VIN
; DLOW =
VIN − VOUT
VIN
The resulting power dissipation in the MOSFETs at
maximum output current are:
2
PUP = IOUT × RDS( ON) × DUP + 0.5 × IOUT × VIN × TSW × fOSC
2
PLOW = IOUT × RDS( ON) × DLOW
where TSW is the combined switch ON and OFF time.
uP1542-DS-F00A0, Apr. 2018
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Both MOSFETs have I2R losses and the upper MOSFET
includes an additional term for switching losses, which
are largest at high input voltages. The lower MOSFET
losses are greatest when the bottom duty cycle is near
100%, during a short-circuit or at high input voltage. These
equations assume linear voltage current transitions and
do not adequately model power loss due the reverserecovery of the lower MOSFET’s body diode.
Ensure that both MOSFETs are within their maximum
junction temperature at high ambient temperature by
calculating the temperature rise according to package
thermal-resistance specifications. A separate heatsink may
be necessary depending upon MOSFET power, package
type, ambient temperature and air flow.
The gate-charge losses are mainly dissipated by the
uP1542 and don’t heat the MOSFETs. However, large gate
charge increases the switching interval, TSW that increases
the MOSFET switching losses. The gate-charge losses
are calculated as:
PG _ C = VCC × (VCC × (C ISS _ UP + C ISS _ LO ) + VIN × C RSS _ UP )× f OSC
where CISS_UP is the input capacitance of the upper MOSFET,
CISS_LOW is the input capacitance of the lower MOSFET, and
CRSS_UP is the reverse transfer capacitance of the upper
MOSFET. Make sure that the gate-charge loss will not
cause over temperature at uP1542, especially with large
gate capacitance and high supply voltage.
Output Inductor Selection
Output inductor selection usually is based on the
considerations of inductance, rated current, size
requirements and DC resistance (DCR).
Given the desired input and output voltages, the inductor
value and operating frequency determine the ripple
current:
∆IL =
V
1
VOUT (1 − OUT )
VIN
fOSC × L OUT
Lower ripple current reduces core losses in the inductor,
ESR losses in the output capacitors and output voltage
ripple. Highest efficiency operation is obtained at low
frequency with small ripple current. However, achieving
this requires a large inductor. There is a tradeoff between
component size, efficiency and operating frequency. A
reasonable starting point is to choose a ripple current that
is about 20% of IOUT(MAX).
There is another tradeoff between output ripple current/
voltage and response time to a transient load. Increasing
the value of inductance reduces the output ripple current
and voltage. However, the large inductance values reduce
9
uP1542
Application Information
the converter’s response time to a load transient.
Maximum current ratings of the inductor are generally
specified in two methods: permissible DC current and
saturation current. Permissible DC current is the allowable
DC current that causes 40OC temperature raise. The
saturation current is the allowable current that causes 10%
inductance loss. Make sure that the inductor will not
saturate over the operation conditions including
temperature range, input voltage range, and maximum
output current.
The size requirements refer to the area and height
requirement for a particular design. For better efficiency,
choose a low DC resistance inductor. DCR is usually
inversely proportional to size.
Input Capacitor Selection
The synchronous-rectified Buck converter draws pulsed
current with sharp edges from the input capacitor, resulting
in ripples and spikes at the input supply voltage. Use a
mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use small ceramic
capacitors for high frequency decoupling and bulk
capacitors to supply the current needed each time upper
MOSFET turns on. Place the small ceramic capacitors
physically close to the MOSFETs to avoid the stray
inductance along the connection trace.
The important parameters for the bulk input capacitor are
the voltage rating and the RMS current rating. For reliable
operation, select the bulk capacitor with voltage and current
ratings above the maximum input voltage and largest RMS
current required by the circuit. The capacitor voltage rating
should be at least 1.25 times greater than the maximum
input voltage and a voltage rating of 1.5 times is a
conservative guideline. The RMS current rating
requirement for the input capacitor of a buck converter is
calculated as:
IIN(RMS ) = IOUT(MAX )
VOUT ( VIN − VOUT )
VIN
This formula has a maximum at VIN = 2VOUT, where IIN(REMS)
= IOUT(RMS)/2. This simple worst-case condition is commonly
used for design because even significant deviations do
not offer much relief. Note that the capacitor
manufacturer’s ripple current ratings are often based on
2000 hours of life. This makes it advisable to further derate
the capacitor, or choose a capacitor rated at a higher
temperature than required. Always consult the
manufacturer if there is any question.
For a through-hole design, several electrolytic capacitors
may be needed. For surface mount designs, solid tantalum
10
capacitors can also be used, but caution must be exercised
with regard to the capacitor surge current rating. These
capacitors must be capable of handling the surge-current
at power-up. Some capacitor series available from reputable
manufacturers are surge current tested.
Output Capacitor Selection
The selection of COUT is primarily determined by the ESR
required to minimize voltage ripple and load step
transients. The equivalent ripple current into the output
capacitor is half of the inductor ripple current while the
equivalent frequency is double of phase operation
frequency due to two phase operation The output ripple
∆VOUT is approximately bounded by:
∆VOUT =
∆IL
1
(ESR +
)
2
16 × fOSC × COUT
Since ∆IL increases with input voltage, the output ripple is
highest at maximum input voltage. Typically, once the ESR
requirement is satisfied, the capacitance is adequate for
filtering and has the necessary RMS current rating. Multiple
capacitors placed in parallel may be needed to meet the
ESR and RMS current handling requirements.
The load transient requirements are a function of the slew
rate (di/dt) and the magnitude of the transient load current.
These requirements are generally met with a mix of
capacitors and careful layout. Modern components and
loads are capable of producing transient load rates above
1A/ns. High frequency capacitors initially supply the
transient and slow the current load rate seen by the bulk
capacitors. The bulk filter capacitor values are generally
determined by the ESR (Effective Series Resistance) and
voltage rating requirements rather than actual capacitance
requirements.
High frequency decoupling capacitors should be placed
as close to the power pins of the load as physically
possible. Be careful not to add inductance in the circuit
board wiring that could cancel the usefulness of these
low inductance components. Consult with the
manufacturer of the load on specific decoupling
requirements.
Use only specialized low-ESR capacitors intended for
switching-regulator applications for the bulk capacitors.
The bulk capacitor’s ESR will determine the output ripple
voltage and the initial voltage drop after a high slew-rate
transient. An aluminum electrolytic capacitor’s ESR value
is related to the case size with lower ESR available in
larger case sizes.
Bootstrap Capacitor Selection
An external bootstrap capacitor CBOOT connected to the
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uP1542
Application Information
BOOT pin supplies the gate drive voltage for the upper
MOSFET. This capacitor is charged through the internal
diode when the PH node is low. When the upper MOSFET
turns on, the PH node rises to VIN and the BOOT pin rises
to approximately VIN + VCC. The boot capacitor needs to
store about 100 times the gate charge required by the
upper MOSFET. In most applications 0.47µF to 1µF, X5R
or X7R dielectric capacitor is adequate.
filter (LOUT and COUT), with a double pole break frequency at
FLC and a zero at FESR. The DC Gain of the modulator is
simply the input voltage (VIN) divided by the peak-to-peak
oscillator voltage £ OSC.
GV
The output LC filter introduces a double pole, 40dB/decade
gain slope above its corner resonant frequency, and a total
phase lag of 180 degrees. The resonant frequency of the
LC filter expressed as:
Feedback Loop Compensation
Figure 5 highlights the voltage-mode control loop for a
synchronous-rectified buck converter consisting of
uP1542. The control loop includes a compensator and a
modulator, where the modulator consists of the PWM
comparator, the power stage amplifier and the output filter;
the compensator consists of the error amplifier and
compensating network. A well-designed feedback loop
tightly regulates the output voltage (VOUT) to the reference
voltage VREF with fast response to load/line transient and
good stability. The goal of the compensation network is to
provide and the highest 0dB crossing frequency and
adequate phase margin (greater than 45 degrees). It is
also recommended to manipulate loop frequency
response that its gain crosses over 0dB at a slope of 20dB/dec.
FLC =
FESR =
1
2π × ESR× COUT
Figure 6 illustrates frequency response of a typical
modulator using uP1542.
80
60
LC
Double
Pole
Modulator
LOUT
PH
VOUT
COUT
Gain (dB)
40
Driver
PWM
Comp.
2π L OUT × COUT
The ESR zero is contributed by the ESR associated with
the output capacitor. Note that this requires that the output
capacitor should have enough ESR to satisfy stability
requirements as described in the later sections. The ESR
zero of the output capacitor expressed as:
VIN
∠VOSC
1
20
0
ESR
Zero
-20
-40
ESR
-60
1.E+02
VREF
C3
Error
Amp.
C1
R1
Compensator
R2
VCOMP
R3
1.E+04
1.E+05
1.E+06
Frequency (Hz)
Figure 6. Frequency Response of Modulator.
2) Compensator Frequency Equations
C2
ZCOMP
ZFB
Figure 5. Voltage Control Loop Using uP1542.
Modulator Break Frequency Equations
The error amplifier output (VCOMP) is compared with the
oscillator (OSC) sawtooth waveform to provide a pulsewidth modulated (PWM) waveform with an amplitude of
VIN at the PH node. The PWM waveform is smoothed by
the output filter (LOUT and COUT). The modulator transfer
function is the small-signal transfer function of VOUT/VCOMP.
This function is dominated by a DC Gain and the output
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1.E+03
The uP1542 adopts an operational transconductance
amplifier (OTA) as the error amplifier as shown in Figure
7.
EA+
∆VM
∆IOUT= GM x ∆VM
GM
VOUT
ROUT
EA-
Figure 7. Operational Transconductance Amplifier.
11
uP1542
Application Information
The transconductance is defined as:
GM =
regulation and fast response to load/line transient with good
stability. Follow the guidelines for locating the poles and
zeros of the compensation network.
∆ IOUT
∆VM
where ∆VM = (EA+) - (EA-); ∆IOUT = E/A output current.
Figure 8 illustrates a type II compensation network using
OTA. The compensation network consists of the error
amplifier and the impedance networks ZFB and ZCOMP.
1. Pick Mid-Band Gain (R1) for desired converter bandwidth.
2. Place Zero (C1) below LC double pole (~25% FLC).
3. Place Pole (C2) at half the switching frequency.
4. Check gain against error amplifier open loop gain.
5. Estimate phase margin - repeat if necessary.
60
VOUT
VCOMP
R3
GM
40
Error
Amplifier
R2
VREF
R1
ZCOMP C1
Figure 8. Type II Compensation Network Using OTA.
The compensator transfer function is the small-signal
transfer function of VCOMP/VOUT. This function is dominated
by a Mid-Band Gain and compensation network ZCOMP, with
a pole at FP1 and a zero at FZ1. The Mid-Band Gain of the
compensation is expressed as:
Mid _ Band _ Gain =
1
C1× C2 ; FZ1 =
)
2π × R1× C1
C1 + C2
Gain (dB)
-60
1.E+02
1.E+03
1.E+04
Frequency (Hz)
1.E+05
1.E+06
As a design example, take a power supply with the
following specifications:
VIN = 10.8V to 13.2V (12V nominal), VOUT = 1.2V Ó5%,
¡
IOUT(MAX) = 20A, fOSC = 300kHz/200kHz, ∆VOUT = 20mV,
bandwidth = 50kHz.
∆IL =
Loop Gain
Compensator
Gain
20
C1
-40
First, choose the inductor for about 20% ripple current at
the maximum VIN:
40
0
-20
1.) Power Component Selection
60
R1
0
Design Example
1
2π × R1× (
Modulator
Gain
Figure 10. Frequency Response of Type II Compensation.
R2
× R1× GM
R 2 × R3
The equations below relate the compensation network’s
pole and zero to the components (R1, C1, and C2) in
Figure 9.
FP1 =
Compensator
Gain
20
Gain (dB)
C2
ZFB
Loop Gain
Modulator
Gain
FZ1
V
1
× VOUT × (1 − OUT )
VIN
fOSC × L OUT
∆IL = 20 A × 20% =
FP1
1
1 .2 V
× 1.2V × (1 −
)
300kHz × L OUT
13.2V
-20
L OUT = 0 .9 uH
-40
Selecting a standard value of 1.0uH results in a maximum
ripple current of 3.6A.
-60
1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
Frequency (Hz)
Figure 9. Frequency Response of Type II Compensation.
Figure 10 shows the DC-DC converter’s gain vs.
frequency. Careful design of ZCOMP and ZFB provides tight
12
Choose two 1000uF capacitors with 10mΩ ESR in parallel
to yield equivalent ESR = 5mΩ. The output ripple voltage
is about 18mV accordingly. An optional 22uF ceramic
output capacitor is recommended to minimize the effect
of ESL in the output ripple.
The modulator DC gain and break frequencies are
calculated as:
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uP1542
Application Information
V
12
DC Gain = 20 × log( IN ) = 20 × log(
) = 16.5dB
1. 8
∆VOSC
FLC =
1
2 π 1× 10 − 6 × 2000 × 10 − 6
FESR =
1
2π × 5 × 10 −3 × 2000 × 10 −6
= 3 .56kHz
double pole. Adding a feedforward capacitor C3 on original
type II compensation network introduces an additional
pole-zero pair ( Z2 and P2) as illustrated in Figure 13. The
new pole-zero pair are expressed as:
Z2 =
= 16kHz
2.) Compensation
1
1
; P2 =
2π × C3 × (R2 × R3) /(R2 + R3)
2π × R3 × C3
VOUT
Select R2 = 10kΩ and R3 = 5kΩ to set output voltage as
1.2V. R2 and R3 do not affect the compensation, 1kΩ ~
10kΩ is adequate for the application.
Select C1 = 10nF to place FZ1 = 0.9kHz, about one forth of
the LC double pole.
Select C2 = 68pF to place FP1 = 133kHz, about half of the
switching frequency.
R2
VREF
ZCOMP C1
80
60
Loop
Gain
Loop Gain
Compensator
Gain
40
Gain (dB)
Compensator
Gain
20
R1
While the Mid-Band Gain remains unchanged, the
additional pole-zero pair causes a gain boost at the flat
gain region. The gain-boost is limited by the ratio (R1 +R2)/
R2. Figures 14 shows the DC-DC converter’s gain vs.
frequency.
60
Gain (dB)
C2
ZFB
Figure 11 shows the result loop gain vs. frequency relation.
0
Error
Amplifier
Figure 12. Type III Compensation Network.
10(19.5 / 20) × VOUT
= 17.7kΩ
GM× VREF
40
GM
C3
The modulator gain at zero-crossing frequency (50kHz)
is calculated as -19.5dB. This demands a compensator
with mid-band gain as 19.5dB. Select R1 as:
R1 =
VCOMP
R3
Modulator
Gain
20
0
P2
Modulator
Gain
Z1
P1
Z2
-20
-20
-40
-40
-60
1.E+01
-60
1.E+02
1.E+03
1.E+04
Frequency (Hz)
1.E+05
1.E+06
1.E+02
1.E+03
1.E+04
Frequency (Hz)
1.E+05
1.E+06
Figure 13. Loop Gain of Type III Compensation Network.
Figure 11. Gain vs. Frequency for the Design Example.
Type III Compensation
The ESR zero plays an important role in type II
compensation. Output capacitors with low ESR and small
capacitance push the ESR zero to high frequency band. If
the ESR zero is ten times higher than the LC double pole,
the double pole may cause the loop phase close to 180O
and make the control loop unstable. A type II compensation
cannot stabilize the loop since it has only one zero.
A type III compensation network as shown in Figure 12
that features 2 poles and 2 zeros is necessary for such
applications where ESR zero is far away from the LC
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13
uP1542
Application Information
connection the top layer with wide, copper filled areas.
80
60
2.1 Place the input capacitors, especially the high
frequency ceramic decoupling capacitors, directly
to the drain of upper MOSFET ad the source of
the lower MOSFET. To reduce the ESR replace
the single input capacitor with two parallel units
Compensator
Gain
40
Gain (dB)
2 Place the power components as physically close as
possible.
Loop Gain
20
0
Modulator
Gain
-20
2.2 Place the output capacitor between the converter
and load.
-40
-60
1.E+01
1.E+02
1.E+03
1.E+04
Frequency (Hz)
1.E+05
1.E+06
Figure 14. Frequency Response of Type III Compensation.
Checking Transient Response
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, VOUT immediately shifts by an amount
equal to ∆ILOADx(ESR), where ESR is the effective series
resistance of C OUT. ∆I LOAD also begins to charge or
discharge COUT generating a feedback error signal used
by the regulator to return VOUT to its steady-state value.
During this recovery time, VOUT can be monitored for
overshoot or ringing that would indicate a stability problem.
PCB Layout Considerations
High speed switching and relatively large peak currents
in a synchronous-rectified buck converter make the PCB
layout a very important part of design. Fast current
switching from one device to another in a synchronousrectified buck converter causes voltage spikes across the
interconnecting impedances and parasitic circuit elements.
The voltage spikes can degrade efficiency and radiate
noise that result in overvoltage stress on devices. Careful
component placement layout and printed circuit board
design minimizes the voltage spikes induced in the
converter.
Follow the layout guidelines for optimal performance of
uP1542.
1 The upper and lower MOSFETs turn on/off and conduct
pulsed current alternatively with high slew rate
transition. Any inductance in the switched current path
generates a large voltage spike during the switching.
The interconnecting wires indicated by red heavy lines
conduct pulsed current with sharp transient and should
be part of a ground or power plane in a printed circuit
board to minimize the voltage spike. Make all the
14
3 Place the uP1542 near the upper and lower MOSFETs
with UG and LG facing the power components. Keep
the components connected to noise sensitive pins near
the uP1542 and away from the inductor and other noise
sources.
4 Use a dedicated grounding plane and use vias to ground
all critical components to this layer. The ground plane
layer should not have any traces and should be as close
as possible to the layer with power MOSFETs. Use an
immediate via to connect the components to ground
plane including GND of uP1542. Use several bigger
vias for power components.
5 Apply another solid layer as a power plane and cut this
plane into smaller islands of common voltage levels.
The power plane should support the input power and
output power nodes to maintain good voltage filtering
and to keep power losses low. Also, for higher currents,
it is recommended to use a multilayer board to help
with heat sinking power components.
6 The PH node is subject to very high dV/dt voltages.
Stray capacitance between this island and the
surrounding circuitry tend to induce current spike and
capacitive noise coupling. Keep the sensitive circuit
away from the PH node and keep the PCB area small
to limit the capacitive coupling. However, the PCB area
should be kept moderate since it also acts as main
heat convection path of the lower MOSFET.
7 The uP1542 sources/sinks impulse current with 2A peak
to turn on/off the upper and lower MOSFETs. The
connecting trance between the controller and gate/
source of the MOSFET should be wide and short to
minimize the parasitic inductance along the traces.
8 Flood all unused areas on all layers with copper.
Flooding with copper will reduce the temperature rise
of power component.
9 Provide local VCC decoupling between VCC and GND
pins. Locate the capacitor, CBOOT as close as possible
to the BOOT and PH pins.
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uP1542
Package Information
4.80 - 5.00
1.80 - 2.40
1.80 - 2.40
3.80 - 4.00
5.79 - 6.20
0.40 - 1.27
0.10 - 0.25
PSOP - 8L
1
1.27 BSC
0.31 - 0.51
1.7 MAX
0.00 - 0.15
Note
1.Package Outline Unit Description:
BSC: Basic. Represents theoretical exact dimension or dimension target
MIN: Minimum dimension specified.
MAX: Maximum dimension specified.
REF: Reference. Represents dimension for reference use only. This value is not a device specification.
TYP. Typical. Provided as a general value. This value is not a device specification.
2.Dimensions in Millimeters.
3.Drawing not to scale.
4.These dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm.
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15
uP1542
Package Information
WDFN2x2 - 8L
1.90 - 2.10
1.10 - 1.40
0.20 - 0.50
1
0.50 - 0.80
8
4
1.90 - 2.10
5
0.50 BSC
0.18 - 0.30
0.70 - 0.80
0.20 REF
0.00 - 0.05
Note
1.Package Outline Unit Description:
BSC: Basic. Represents theoretical exact dimension or dimension target
MIN: Minimum dimension specified.
MAX: Maximum dimension specified.
REF: Reference. Represents dimension for reference use only. This value is not a device specification.
TYP. Typical. Provided as a general value. This value is not a device specification.
2.Dimensions in Millimeters.
3.Drawing not to scale.
4.These dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm.
16
uP1542-DS-F00A0, Apr. 2018
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uP1542
Important Notice
uPI and its subsidiaries reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products
and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information
before placing orders and should verify that such information is current and complete.
uPI products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment. However, no responsibility is
assumed by uPI or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use.
No license is granted by implication or otherwise under any patent or patent rights of uPI or its subsidiaries.
COPYRIGHT (C) 2011, UPI SEMICONDUCTOR CORP.
uPI Semiconductor Corp.
Headquarter
9F.,No.5, Taiyuan 1st St. Zhubei City,
Hsinchu Taiwan, R.O.C.
TEL : 886.3.560.1666 FAX : 886.3.560.1888
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uPI Semiconductor Corp.
Sales Branch Office
12F-5, No. 408, Ruiguang Rd. Neihu District,
Taipei Taiwan, R.O.C.
TEL : 886.2.8751.2062 FAX : 886.2.8751.5064
17