To model z 2014r Link -matryca z serii WRGB) ,FHD :?: Raczej serwisy w Szwajcarii nie należą do tanich ( o ile jeszcze egzystują ), a ten 55" calowy model z zakrzywionym ekranem (curved) nie należy do łatwych w naprawie. Main i nazwę chassis odczytasz z foto https://obrazki.elektroda.pl/7660165000_1557305055_thumb.jpg - cięzki do zakupu (ebay, picclick) i cena ponad >250.$/Eur * był też main EBT63359602 (na druku pcb: Eax65612206 (1.1)) * ( był main EAX: 65612209, EBT: 63304002) https://obrazki.elektroda.pl/3259374300_1557299402_thumb.jpg https://obrazki.elektroda.pl/7649436100_1557300302_thumb.jpg Zasilacz PSU to EAY63348801 / LGP55F-14OP - daje 2x 24V/ 12V/ 3.5V stby https://obrazki.elektroda.pl/3418062700_1557299737_thumb.jpg https://obrazki.elektroda.pl/2346983100_1557304280_thumb.jpg T-con Oled TV 6871L-3963E (na pcb: 6870C-0555A) https://obrazki.elektroda.pl/1665944500_1557299871_thumb.jpg Był też T-con (inna matryca) 6871L-4007J (pcb: 6870C-0477C) https://obrazki.elektroda.pl/9681622700_1557300103_thumb.jpg Jak masz pojęcie o serwisie , przyrządy , znajomośc pomiarów -rozejrzyj sie za SM pod te chassis (mało popularne) lub pózniejszych modeli OLED TV -poczytaj Manual Treningowy dla LED TV LG , był na forum - oceń możliwości i ...? (Twoja wola i TV) p.s Obecne SM od LG są ubogie , ale zawsze coś można wyczytać…. W zał SM pod 33" OLED LG na chassis EA34D - jest jeszcze pod chassis EA51E - pod EA64B Link Problemy z OLED TV opisano pod Link
Internal Use Only
North/Latin America
Europe/Africa
Asia/Oceania
http://aic.lgservice.com
http://eic.lgservice.com
http://biz.lgservice.com
OLED TV
SERVICE MANUAL
CHASSIS : EA34D
MODEL : 55EA8800
55EA8800-UC
CAUTION
BEFORE SERVICING THE CHASSIS,
READ THE SAFETY PRECAUTIONS IN THIS MANUAL.
P/NO : MFL67840105(1312-REV00)
Printed in Korea
CONTENTS
CONTENTS . ............................................................................................. 2
PRODUCT SAFETY ................................................................................. 3
SPECIFICATION........................................................................................ 4
ADJUSTMENT INSTRUCTION............................................................... 11
EXPLODED VIEW .................................................................................. 23
SCHEMATIC CIRCUIT DIAGRAM ..............................................................
Copyright ©
LG Electronics. Inc. All rights reserved.
Only for training and service purposes
-2-
LGE Internal Use Only
SAFETY PRECAUTIONS
IMPORTANT SAFETY NOTICE
Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by
in the
Schematic Diagram and Exploded View.
It is essential that these special safety parts should be replaced with the same components as recommended in this manual to prevent
Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.
General Guidance
Leakage Current Hot Check (See below Figure)
Plug the AC cord directly into the AC outlet.
An isolation Transformer should always be used during the
servicing of a receiver whose chassis is not isolated from the AC
power line. Use a transformer of adequate power rating as this
protects the technician from accidents resulting in personal injury
from electrical shocks.
It will also protect the receiver and it's components from being
damaged by accidental shorts of the circuitry that may be
inadvertently introduced during the service operation.
If any fuse (or Fusible Resistor) in this TV receiver is blown,
replace it with the specified.
When replacing a high wattage resistor (Oxide Metal Film Resistor,
over 1 W), keep the resistor 10 mm away from PCB.
Keep wires away from high voltage or high temperature parts.
Do not use a line Isolation Transformer during this check.
Connect 1.5 K / 10 watt resistor in parallel with a 0.15 uF capacitor
between a known good earth ground (Water Pipe, Conduit, etc.)
and the exposed metallic parts.
Measure the AC voltage across the resistor using AC voltmeter
with 1000 ohms/volt or more sensitivity.
Reverse plug the AC cord into the AC outlet and repeat AC voltage
measurements for each exposed metallic part. Any voltage
measured must not exceed 0.75 volt RMS which is corresponds to
0.5 mA.
In case any measurement is out of the limits specified, there is
possibility of shock hazard and the set must be checked and
repaired before it is returned to the customer.
Leakage Current Hot Check circuit
Before returning the receiver to the customer,
always perform an AC leakage current check on the exposed
metallic parts of the cabinet, such as antennas, terminals, etc., to
be sure the set is safe to operate without damage of electrical
shock.
Leakage Current Cold Check(Antenna Cold Check)
With the instrument AC plug removed from AC source, connect an
electrical jumper across the two AC plug prongs. Place the AC
switch in the on position, connect one lead of ohm-meter to the AC
plug prongs tied together and touch other ohm-meter lead in turn to
each exposed metallic parts such as antenna terminals, phone
jacks, etc.
If the exposed metallic part has a return path to the chassis, the
measured resistance should be between 1 MΩ and 5.2 MΩ.
When the exposed metal has no return path to the chassis the
reading must be infinite.
An other abnormality exists that must be corrected before the
receiver is returned to the customer.
Copyright ©
LG Electronics. Inc. All rights reserved.
Only for training and service purposes
-3-
LGE Internal Use Only
SERVICING PRECAUTIONS
CAUTION: Before servicing receivers covered by this service
manual and its supplements and addenda, read and follow the
SAFETY PRECAUTIONS on page 3 of this publication.
NOTE: If unforeseen circumstances create conflict between the
following servicing precautions and any of the safety precautions
on page 3 of this publication, always follow the safety precautions.
Remember: Safety First.
General Servicing Precautions
1. lways unplug the receiver AC power cord from the AC power
A
source before;
a. emoving or reinstalling any component, circuit board modR
ule or any other receiver assembly.
b. isconnecting or reconnecting any receiver electrical plug or
D
other electrical connection.
c. onnecting a test substitute in parallel with an electrolytic
C
capacitor in the receiver.
CAUTION: A wrong part substitution or incorrect polarity
installation of electrolytic capacitors may result in an explosion hazard.
2. est high voltage only by measuring it with an appropriate
T
high voltage meter or other voltage measuring device (DVM,
FETVOM, etc) equipped with a suitable high voltage probe.
Do not test high voltage by " drawing an arc " .
3. o not spray chemicals on or near this receiver or any of its
D
assemblies.
4. nless specified otherwise in this service manual, clean
U
electrical contacts only by applying the following mixture to the
contacts with a pipe cleaner, cotton-tipped stick or comparable
non-abrasive applicator; 10 % (by volume) Acetone and 90 %
(by volume) isopropyl alcohol (90 % - 99 % strength)
CAUTION: This is a flammable mixture.
Unless specified otherwise in this service manual, lubrication of
contacts in not required.
5. o not defeat any plug/socket B+ voltage interlocks with which
D
receivers covered by this service manual might be equipped.
6. o not apply AC power to this instrument and/or any of its
D
electrical assemblies unless all solid-state device heat sinks are
correctly installed.
7. lways connect the test receiver ground lead to the receiver
A
chassis ground before connecting the test receiver positive
lead.
Always remove the test receiver ground lead last.
8. se with this receiver only the test fixtures specified in this
U
service manual.
CAUTION: Do not connect the test fixture ground strap to any
heat sink in this receiver.
Electrostatically Sensitive (ES) Devices
Some semiconductor (solid-state) devices can be damaged easily by static electricity. Such components commonly are called
Electrostatically Sensitive (ES) Devices. Examples of typical ES
devices are integrated circuits and some field-effect transistors
and semiconductor “chip” components. The following techniques
should be used to help reduce the incidence of component damage caused by static by static electricity.
1. mmediately before handling any semiconductor component or
I
semiconductor-equipped assembly, drain off any electrostatic
charge on your body by touching a known earth ground. Alternatively, obtain and wear a commercially available discharging
wrist strap device, which should be removed to prevent potential shock reasons prior to applying power to the unit under test.
Copyright ©
LG Electronics. Inc. All rights reserved.
Only for training and service purposes
2. fter removing an electrical assembly equipped with ES
A
devices, place the assembly on a conductive surface such as
aluminum foil, to prevent electrostatic charge buildup or exposure of the assembly.
3. se only a grounded-tip soldering iron to solder or unsolder ES
U
devices.
4. se only an anti-static type solder removal device. Some solder
U
removal devices not classified as “anti-static” can generate
electrical charges sufficient to damage ES devices.
5. o not use freon-propelled chemicals. These can generate
D
electrical charges sufficient to damage ES devices.
6. o not remove a replacement ES device from its protective
D
package until immediately before you are ready to install it.
(Most replacement ES devices are packaged with leads electrically shorted together by conductive foam, aluminum foil or
comparable conductive material).
7. mmediately before removing the protective material from the
I
leads of a replacement ES device, touch the protective material
to the chassis or circuit assembly into which the device will be
installed.
CAUTION: Be sure no power is applied to the chassis or circuit,
and observe all other safety precautions.
8. inimize bodily motions when handling unpackaged replaceM
ment ES devices. (Otherwise harmless motion such as the
brushing together of your clothes fabric or the lifting of your
foot from a carpeted floor can generate static electricity sufficient to damage an ES device.)
General Soldering Guidelines
1. se a grounded-tip, low-wattage soldering iron and appropriate
U
tip size and shape that will maintain tip temperature within the
range or 500 °F to 600 °F.
2. se an appropriate gauge of RMA resin-core solder composed
U
of 60 parts tin/40 parts lead.
3. Keep the soldering iron tip clean and well tinned.
4. horoughly clean the surfaces to be soldered. Use a mall wireT
bristle (0.5 inch, or 1.25 cm) brush with a metal handle.
Do not use freon-propelled spray-on cleaners.
5. se the following unsoldering technique
U
a. llow the soldering iron tip to reach normal temperature.
A
(500 °F to 600 °F)
b. Heat the component lead until the solder melts.
c. uickly draw the melted solder with an anti-static, suctionQ
type solder removal device or with solder braid.
CAUTION: Work quickly to avoid overheating the circuit
board printed foil.
6. se the following soldering technique.
U
a. llow the soldering iron tip to reach a normal temperature
A
(500 °F to 600 °F)
b. irst, hold the soldering iron tip and solder the strand against
F
the component lead until the solder melts.
c. uickly move the soldering iron tip to the junction of the
Q
component lead and the printed circuit foil, and hold it there
only until the solder flows onto and around both the component lead and the foil.
CAUTION: Work quickly to avoid overheating the circuit
board printed foil.
d. losely inspect the solder area and remove any excess or
C
splashed solder with a small wire-bristle brush.
-4-
LGE Internal Use Only
IC Remove/Replacement
Some chassis circuit boards have slotted holes (oblong) through
which the IC leads are inserted and then bent flat against the circuit foil. When holes are the slotted type, the following technique
should be used to remove and replace the IC. When working with
boards using the familiar round hole, use the standard technique
as outlined in paragraphs 5 and 6 above.
3. older the connections.
S
CAUTION: Maintain original spacing between the replaced
component and adjacent components and the circuit board to
prevent excessive component temperatures.
Circuit Board Foil Repair
Excessive heat applied to the copper foil of any printed circuit
board will weaken the adhesive that bonds the foil to the circuit
board causing the foil to separate from or " lift-off " the board. The
following guidelines and procedures should be followed whenever
this condition is encountered.
Removal
1. esolder and straighten each IC lead in one operation by
D
gently prying up on the lead with the soldering iron tip as the
solder melts.
2. raw away the melted solder with an anti-static suction-type
D
solder removal device (or with solder braid) before removing
the IC.
Replacement
1. arefully insert the replacement IC in the circuit board.
C
2. arefully bend each IC lead against the circuit foil pad and
C
solder it.
3. lean the soldered areas with a small wire-bristle brush.
C
(It is not necessary to reapply acrylic coating to the areas).
At IC Connections
To repair a defective copper pattern at IC connections use the
following procedure to install a jumper wire on the copper pattern
side of the circuit board. (Use this technique only on IC connections).
" Small-Signal " Discrete Transistor
Removal/Replacement
1. emove the defective transistor by clipping its leads as close
R
as possible to the component body.
2. end into a " U " shape the end of each of three leads remaining
B
on the circuit board.
3. end into a " U " shape the replacement transistor leads.
B
4. onnect the replacement transistor leads to the corresponding
C
leads extending from the circuit board and crimp the " U " with
long nose pliers to insure metal to metal contact then solder
each connection.
Power Output, Transistor Device
Removal/Replacement
1. Heat and remove all solder from around the transistor leads.
2. Remove the heat sink mounting screw (if so equipped).
3. arefully remove the transistor from the heat sink of the circuit
C
board.
4. nsert new transistor in the circuit board.
I
5. older each transistor lead, and clip off excess lead.
S
6. eplace heat sink.
R
Diode Removal/Replacement
1. emove defective diode by clipping its leads as close as posR
sible to diode body.
2. end the two remaining leads perpendicular y to the circuit
B
board.
3. bserving diode polarity, wrap each lead of the new diode
O
around the corresponding lead on the circuit board.
4. ecurely crimp each connection and solder it.
S
5. nspect (on the circuit board copper side) the solder joints of
I
the two " original " leads. If they are not shiny, reheat them and if
necessary, apply additional solder.
1. arefully remove the damaged copper pattern with a sharp
C
knife. (Remove only as much copper as absolutely necessary).
2. arefully scratch away the solder resist and acrylic coating (if
c
used) from the end of the remaining copper pattern.
3. end a small " U " in one end of a small gauge jumper wire and
B
carefully crimp it around the IC pin. Solder the IC connection.
4. oute the jumper wire along the path of the out-away copper
R
pattern and let it overlap the previously scraped end of the
good copper pattern. Solder the overlapped area and clip off
any excess jumper wire.
At Other Connections
Use the following technique to repair the defective copper pattern
at connections other than IC Pins. This technique involves the
installation of a jumper wire on the component side of the circuit
board.
1. emove the defective copper pattern with a sharp knife.
R
Remove at least 1/4 inch of copper, to ensure that a hazardous
condition will not exist if the jumper wire opens.
2. race along the copper pattern from both sides of the pattern
T
break and locate the nearest component that is directly connected to the affected copper pattern.
3. onnect insulated 20-gauge jumper wire from the lead of the
C
nearest component on one side of the pattern break to the lead
of the nearest component on the other side.
Carefully crimp and solder the connections.
CAUTION: Be sure the insulated jumper wire is dressed so the
it does not touch components or sharp edges.
Fuse and Conventional Resistor
Removal/Replacement
1. lip each fuse or resistor lead at top of the circuit board hollow
C
stake.
2. ecurely crimp the leads of replacement component around
S
notch at stake top.
Copyright ©
LG Electronics. Inc. All rights reserved.
Only for training and service purposes
-5-
LGE Internal Use Only
SPECIFICATION
NOTE : Specifications and others are subject to change without notice for improvement.
1. Application range
This spec sheet is applied LED TV with (LA34N) chassis
2. Test condition
Each part is tested as below without special notice.
1) Temperature : 25 ºC ± 5 ºC(77 ± 9 ºF) , CST : 40 ºC±5 ºC
2) Relative Humidity: 65 % ± 10 %
3) Power Voltage
Market
Input voltage
Frequency
USA
110~240V
50/60Hz
Remark
Standard Voltage of each
product is marked by
models
4) pecification and performance of each parts are followed
S
each drawing and specification by part number in
accordance with BOM
5) he receiver must be operated for about 20 minutes prior to
T
the adjustment
3. Test method
1) Performance: LGE TV test method followed
2) Demanded other specification
Safety : UL, CSA, CE, IEC specification
EMC: FCC, ICES, CE, IEC specification
Wireless : Wireless HD Specification (Option)
4. General Specification
No
Item
Specification
1
Market
1) North America
2
Broad casting System
1) ATSC / NTSC-M
3
Receiving System
1) ATSC / NTSC-M
4
Input Voltage
AC 100 - 240V ~ 60Hz
5
Available Channel
1) VHF : 02~13
2) UHF : 14~69
3) DTV : 02-69
4) CATV : 01~135
5) CADTV : 01~135
7
Aspect Ratio
16:9
8
Tuning System
FS
9
LCD Module
LC550LUD-MFP2
10
Operating Environment
1) Temp : 0 ~ 40 deg
2) Humidity : ~ 80 %
11
Storage Environment
Remark
1) Temp : -20 ~ 60 deg
2) Humidity : ~ 85 %
Copyright ©
LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGD
-6-
LGE Internal Use Only
5. External input format
5.1. 2D mode
5.1.1. Component input (Y, CB/PB, CR/PR)
No.
Resolution
H-freq(kHz)
V-freq.(kHz)
Pixel clock
Proposed
1.
720*480
15.73
60.00
13.5135
SDTV ,DVD 480I
2.
720*480
15.73
59.94
13.50
SDTV ,DVD 480I
3.
720*480
31.50
60.00
27.027
SDTV 480P
4.
720*480
31.47
59.94
27.00
SDTV 480P
5.
1280*720
45.00
60.00
74.25
HDTV 720P
6.
1280*720
44.96
59.94
74.176
HDTV 720P
7.
1920*1080
33.75
60.00
74.25
HDTV 1080I
8.
1920*1080
33.72
59.94
74.176
HDTV 1080I
9.
1920*1080
67.50
60.00
148.50
HDTV 1080P
10.
1920*1080
67.432
59.94
148.352
HDTV 1080P
11.
1920*1080
27.00
24.00
74.25
HDTV 1080P
12.
1920*1080
26.97
23.94
74.176
HDTV 1080P
13.
1920*1080
33.75
30.00
74.25
HDTV 1080P
14.
1920*1080
33.71
29.97
74.176
HDTV 1080P
5.1.2. HDMI Input 1 (PC/DTV)
No.
Resolution
H-freq(kHz)
V-freq.(kHz)
Pixel clock(MHz)
HDMI-PC
1
640*350
Proposed
DDC
31.468
70.09
25.17
EGA
Х
2
720*400
31.469
70.08
28.32
DOS
O
3
640*480
31.469
59.94
25.17
VESA(VGA)
O
4
800*600
37.879
60.31
40.00
VESA(SVGA)
O
5
1024*768
48.363
60.00
65.00
VESA(XGA)
O
6
1152*864
54.348
60.053
80.00
VESA
O
7
1280*1024
63.981
60.020
108.00
VESA (SXGA)
O
8
1360*768
47.712
60.015
85.50
VESA (WXGA)
O
9
1920*1080
67.5
60
148.5
WUXGA(Reduced Blanking)
O
HDMI-DTV
1
720*480
31.47
60
27.027
SDTV 480P
2
720*480
31.47
59.94
27.00
SDTV 480P
3
1280*720
45.00
60.00
74.25
HDTV 720P
4
1280*720
44.96
59.94
74.176
HDTV 720P
5
1920*1080
33.75
60.00
74.25
HDTV 1080I
6
1920*1080
33.72
59.94
74.176
HDTV 1080I
7
1920*1080
67.500
60
148.50
HDTV 1080P
8
1920*1080
67.432
59.939
148.352
HDTV 1080P
9
1920*1080
27.000
24.000
74.25
HDTV 1080P
10
1920*1080
26.97
23.976
74.176
HDTV 1080P
11
1920*1080
33.75
30.000
74.25
HDTV 1080P
12
1920*1080
33.71
29.97
74.176
HDTV 1080P
Copyright ©
LG Electronics. Inc. All rights reserved.
Only for training and service purposes
-7-
LGE Internal Use Only
5.2. 3D Mode
5.2.1. RF Input
No.
Resolution
H-freq(kHz)
V-freq.(Hz)
Pixel clock(MHz)
Proposed
Remark
1
1920*1080
45.00
60
74.25
HDTV 1080I
Side by Side, Top & Bottom
2
1280*720
45.00
60
74.25
HDTV 720P
Side by Side, Top & Bottom
5.2.2. HDMI Input
5.2.2.1. HDMI 1.3 - DTV (3D supported mode manually)
No.
Resolution
H-freq(kHz)
V-freq.(Hz)
Pixel clock(MHz)
Proposed
Remark
1
1280*720p
45.00
60.00
74.25
Side by Side , Top & Bottom,
Single Frame Sequential
2
1920*1080i
33.75
60.00
74.25
Side by Side, Top & Bottom
3
1920*1080p
67.50
60.00
148.50
Side by Side , Top & Bottom
Checkerboard, Single Frame Sequential
Row Interleaving, Column Interleaving
4
1920*1080p
27.00
24.000
74.25
Side by Side , Top & Bottom
Checkerboard
5
1920*1080p
33.75
30.000
74.25
Side by Side, Top & Bottom
Checkerboard
5.2.2.2. HDMI 1.3 - DTV (3D supported mode manually)
No.
Resolution
H-freq(kHz)
V-freq.(Hz)
Pixel clock(MHz)
Proposed
Remark
1
1280*720p
89.91 / 90.00
59.94 / 60.00
148.35 / 148.50
Mandatory
Frame Packing,
2
1280*720p
44.96 / 45.00
59.94 / 60.00
74.18 / 74.25
Mandatory
Top & Bottom
3
1920*1080i
33.72 / 33.75
59.94 / 60.00
74.18 / 74.25
Mandatory
Side by Side (Half)
4
1920*1080p
43.94 / 54.00
23.97 / 24.00
148.35 / 148.50
Mandatory
Frame Packing,
5
1920*1080p
26.97 / 27.00
23.97 / 24.00
74.18 / 74.25
Mandatory
Top & Bottom
6
1280*720p
44.96 / 45.00
59.94 / 60.00
74.18 / 74.25
Primary
Side by Side (Half)
7
1920*1080i
67.432 / 67.50
59.94 / 60.00
148.35 / 148.50
Primary
Frame Packing
8
1920*1080p
67.43 / 67.50
59.94 / 60.00
148.35 / 148.50
Primary
Top & Bottom
9
1920*1080p
26.97 / 27.00
23.97 / 24.00
74.18 / 74.25
Primary
Side by Side (Half)
10
1920*1080p
67.432 / 67.50
29.976 / 30.00
148.35 / 148.50
Primary
Frame Packing,
11
1920*1080p
33.716 / 33.75
29.976 / 30.00
74.18 / 74.25
Primary
Top & Bottom
12
1920*1080i
33.72 / 33.75
59.94 / 60.00
74.18 / 74.25
Secondary
Top & Bottom
13
1920*1080p
67.43 / 67.50
59.94 / 60.00
148.35 / 148.50
Secondary
Side by Side (Half)
14
1920*1080p
33.716 / 33.75
29.976 / 30.00
74.18 / 74.25
Secondary
Side by Side (Half)
15
720*480p
62.938 / 63.00
59.94 / 60.00
54.00 / 54.054
Secondary (16:9)
Frame Packing,
16
720*480p
31.469 / 31.50
59.94 / 60.00
27.00 / 27.027
Secondary (16:9)
Top & Bottom
17
720*480p
31.469 / 31.50
59.94 / 60.00
27.00 / 27.027
Secondary (16:9)
Side by Side (Half)
Copyright ©
LG Electronics. Inc. All rights reserved.
Only for training and service purposes
-8-
LGE Internal Use Only
No.
Resolution
H-freq(kHz)
V-freq.(Hz)
Pixel clock(MHz)
Proposed
Remark
18
720*480p
62.938 / 63.00
59.94 / 60.00
54.00 / 54.054
Secondary (4:3)
Frame Packing,
19
720*480p
31.469 / 31.50
59.94 / 60.00
27.00 / 27.027
Secondary (4:3)
Top & Bottom
20
720*480p
31.469 / 31.50
59.94 / 60.00
27.00 / 27.027
Secondary (4:3)
Side by Side (Half)
21
640*480p
62.938 / 63.00
59.94 / 60.00
50.35 / 50.40
Secondary
Frame Packing,
22
640*480p
31.469 / 31.50
59.94 / 60.00
25.175 / 25.20
Secondary
Top & Bottom
23
640*480p
31.469 / 31.50
59.94 / 60.00
25.175 / 25.20
Secondary
Side by Side (Half)
24
1280*720p
89.91 / 90.00
59.94 / 60.00
148.35 / 148.50
Line Alternative
25
1280*720p
44.96 / 45.00
59.94 / 60.00
148.35 / 148.50
Side by Side (Full)
26
1920*1080i
67.432 / 67.50
59.94 / 60.00
148.35 / 148.50
Field Alternative
27
1920*1080i
33.72 / 33.75
59.94 / 60.00
148.35 / 148.50
Side by Side (Full)
28
1920*1080p
43.94 / 54.00
23.97 / 24.000
148.35 / 148.50
Line Alternative
29
1920*1080p
26.97 / 27.00
23.97 / 24.000
148.35 / 148.50
Side by Side (Full)
30
1920*1080p
67.432 / 67.50
29.976 / 30.00
148.35 / 148.50
Line Alternative
31
1920*1080p
33.716 / 33.75
29.976 / 30.00
148.35 / 148.50
32
720*480p
62.938 / 63.00
59.94 / 60.00
54.00 / 54.054
Side by Side (Full)
16:9
Line Alternative
33
720*480p
31.469 / 31.50
59.94 / 60.00
54.00 / 54.054
16:9
Side by Side (Full)
34
720*480p
62.938 / 63.00
59.94 / 60.00
54.00 / 54.054
4:3
Line Alternative
4:3
35
720*480p
31.469 / 31.50
59.94 / 60.00
54.00 / 54.054
36
640*480p
62.938 / 63.00
59.94 / 60.00
50.35 / 50.40
Line Alternative
Side by Side (Full)
37
640*480p
31.469 / 31.50
59.94 / 60.00
50.35 / 50.40
Side by Side (Full)
5.2.3. HDMI-PC Input (3D supported mode manually)
No.
Resolution
H-freq(kHz)
V-freq.(Hz)
Pixel clock(MHz)
Proposed
Remark
1
1024*768
48.363
60.004
65.000
Side by Side, Top & Bottom
2
1360*768
47.712
60.015
85.500
Side by Side, Top & Bottom
3
1920*1080
67.50
60.00
148.50
Side by Side, Top & Bottom
Checkerboard, Single Frame Sequential
Row Interleaving, Column Interleaving
5.2.4. USB Input
5.2.4.1. USB Input (3D supported mode automatically)
No.
1
Resolution
1920*1080
H-freq(kHz)
33.75
V-freq.(Hz)
30.000
Pixel clock(MHz)
74.25
Proposed
HDTV 1080p
Remark
Side by Side, Top & Bottom,
Checkerboard, MPO (Photo)
5.2.4.2. USB Input (3D supported mode manually)
No.
1
Resolution
1920*1080
H-freq(kHz)
33.75
V-freq.(Hz)
30.000
Copyright ©
LG Electronics. Inc. All rights reserved.
Only for training and service purposes
Pixel clock(MHz)
74.25
Proposed
HDTV 1080p
-9-
Remark
Side by Side, Top & Bottom
Checkerboard, Single Frame Sequential,
Row Interleaving, Column Interleaving
(Photo : Side by Side, Top & Bottom)
LGE Internal Use Only
5.2.5. DLNA Input
5.2.5.1. DLNA Input (3D supported mode automatically)
No.
1
Resolution
1920*1080
H-freq(kHz)
33.75
V-freq.(Hz)
30.000
Pixel clock(MHz)
74.25
Proposed
HDTV 1080p
Remark
Side by Side, Top & Bottom,
Checkerboard, MPO (Photo)
5.2.5.2. DLNA Input (3D supported mode manually)
No.
1
Resolution
1920*1080
H-freq(kHz)
33.75
V-freq.(Hz)
30.000
Pixel clock(MHz)
74.25
Proposed
HDTV 1080p
Remark
Side by Side, Top & Bottom
Checkerboard, Single Frame Sequential,
Row Interleaving, Column Interleaving
(Photo : Side by Side, Top & Bottom)
5.2.6. Component Input
No.
Resolution
H-freq(kHz)
V-freq.(Hz)
Pixel clock(MHz)
Proposed
Remark
1
1280*720
44.96
59.94
74.176
HDTV 720P
Side by Side, Top & Bottom
2
1920*1080
33.75
60.00
74.25
HDTV 1080I
Side by Side, Top & Bottom
3
1920*1080
33.72
59.94
74.176
HDTV 1080I
Side by Side, Top & Bottom
4
1920*1080
67.500
60
148.50
HDTV 1080P
Side by Side, Top & Bottom
5
1920*1080
67.432
59.94
148.352
HDTV 1080P
Side by Side, Top & Bottom
6
1920*1080
27.000
24.000
74.25
HDTV 1080P
Side by Side, Top & Bottom
7
1920*1080
26.97
23.976
74.176
HDTV 1080P
Side by Side, Top & Bottom
8
1920*1080
33.75
30.000
74.25
HDTV 1080P
Side by Side, Top & Bottom
9
1920*1080
33.71
29.97
74.176
HDTV 1080P
Side by Side, Top & Bottom
● Remark: 3D Input mode
No
1
Side by Side
L
R
Top & Bottom
Checkerboard
LLLLL
R
L
Copyright ©
LG Electronics. Inc. All rights reserved.
Only for training and service purposes
Single Frame
Sequential
R
- 10 -
Frame Packing
Line Interleaving
Column Interleaving
L
LGE Internal Use Only
ADJUSTMENT INSTRUCTION
1. Application
This spec. sheet applies to EA34D Chassis applied LED TV all
models manufactured in TV factory
2. Specification
(1) ecause this is not a hot chassis, it is not necessary to use
B
an isolation transformer. However, the use of isolation
transformer will help protect test instrument.
(2) Adjustment must be done in the correct order.
(3) he adjustment must be performed in the circumstance of
T
25 ±5 ºC of temperature and 65±10% of relative humidity if
there is no specific designation
(4) he input voltage of the receiver must keep 100~240V,
T
50/60Hz
(5) he receiver must be operated for about 5 minutes prior to
T
the adjustment when module is in the circumstance of over
15 ºC
n case of keeping module is in the circumstance of 0°C, it
I
should be placed in the circumstance of above 15°C for 2
hours
n case of keeping module is in the circumstance of below
I
-20°C, it should be placed in the circumstance of above
15°C for 3 hours.
※ Caution
When still image is displayed for a period of 20 minutes or
longer (especially where W/B scale is strong.
Digital pattern 13ch and/or Cross hatch pattern 09ch), there
can some afterimage in the black level area
4. MAIN PCBA Adjustments
4.1. DC Calibration
A
- n ADC calibration is not necessary because MAIN SoC
A
(LGExxxx) is already calibrated from IC Maker
- If it needs to adjust manually, refer to appendix.
4.2. AC Address, ESN Key and Widevine
M
Key download
4.2.1. Equipment & Condition
1) Play file: keydownload.exe
4.2.2. Communication Port connection
1) Key Write: Com 1,2,3,4 and 115200 (Baudrate)
2) Barcode: Com 1,2,3,4 and 9600 (Baudrate)
4.2.3. Download process
1) Select the download items.
2) Mode check: Online Only
3) Check the test process
- S, Canada models: DETECT - & gt; MAC_WRITE - & gt;
U
WIDEVINE_WRITE
- orea, Mexico models: DETECT - & gt; MAC_WRITE - & gt;
K
WIDEVINE_WRITE
4) Play : START
5) Check of result: Ready, Test, OK or NG
6) Printer out (MAC Address Label)
4.2.4. Communication Port connection
1) onnect: PCBA Jig - & gt; RS-232C Port == PC - & gt; RS-232C
C
Port
3. Adjustment items
3.1. Main PCBA Adjustments
(1) ADC adjustment: Component 480i, 1080p
(2) EDID downloads for HDMI
※ Remark
- bove adjustment items can be also performed in Final
A
Assembly if needed. Adjustment items in both PCBA and
final assembly tages can be checked by using the INSTART
Menu - & gt; 1.ADJUST CHECK
4.2.5. Download
1) S, Canada models (13Y LCD TV + MAC + Widevine +
U
ESN Key + DTCP Key + HDCP1.4 and HDCP2.0)
3.2. Final assembly adjustment
(1) White Balance adjustment
(2) RS-232C functionality check
(3) Factory Option setting per destination
(4) Shipment mode setting (In-Stop)
(5) GND and HI-POT test
3.3. Appendix
(1) ool option menu, USB Download (S/W Update, Option and
T
Service only)
(2) Manual adjustment for ADC calibration and White balance.
(3) Shipment conditions, Channel pre-set
4.2.6. Inspection
- In INSTART menu, check these keys.
Copyright ©
LG Electronics. Inc. All rights reserved.
Only for training and service purposes
- 11 -
LGE Internal Use Only
4.3. LAN port Inspection (Ping Test)
4.4.4. EDID DATA(PCM)
(1)DTS
# HDMI 1(C/S : E8 36)
EDID Block 0, Bytes 0-127 [00H-7FH]
4.3.1. Equipment setting
1) Play the LAN Port Test PROGRAM.
2) Input IP set up for an inspection to Test Program.
- IP number: 12.12.2.2
0 1 2 3 4 5 6 7 8 9 A B C D E F
--------------------------------------------------------------------------------0 | 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01
10 | 01 17 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26
20 | 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80
30 | 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C
40 | 45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30
50 | 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A
60 | 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC
70 | 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 E8
4.3.2. LAN PORT inspection (PING TEST)
1) Play the LAN Port Test Program.
2) Connect each other LAN Port Jack.
3) Play Test (F9) button and confirm OK Message.
4) Remove LAN CABLE
EDID Block 1, Bytes 128-255 [80H-FFH]
0 1 2 3 4 5 6 7 8 9 A B C D E F
--------------------------------------------------------------------------------0 | 02 03 34 F1 48 90 22 20 05 04 03 02 01 29 3d 06
10 | C0 15 07 50 09 57 07 78 03 0C 00 10 00 B8 2D 20
20 | C0 0E 01 4F 00 FE 08 10 06 10 18 10 28 10 38 10
30 | E3 05 03 01 02 3A 80 18 71 38 2D 40 58 2C 45 00
40 | 40 84 63 00 00 1E 01 1D 80 18 71 1C 16 20 58 2C
50 | 25 00 40 84 63 00 00 9E 01 1D 00 72 51 D0 1E 20
60 | 6E 28 55 00 40 84 63 00 00 1E 00 00 00 00 00 00
70 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 36
# HDMI 2(C/S : E8 26)
EDID Block 0, Bytes 0-127 [00H-7FH]
0 1 2 3 4 5 6 7 8 9 A B C D E F
--------------------------------------------------------------------------------0 | 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01
10 | 01 17 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26
20 | 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80
30 | 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C
40 | 45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30
50 | 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A
60 | 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC
70 | 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 E8
4.4. EDID Download
4.4.1 Overview
▪ t is a VESA regulation. A PC or a MNT will display an
I
optimal resolution through information sharing without any
necessity of user input. It is a realization of “Plug and Play”.
4.4.2 Equipment
▪ ince embedded EDID data is used, EDID download JIG,
S
HDMI cable and D-sub cable are not need.
▪ Adjust remocon
4.4.3 Download method
1) Press Adj. key on the Adj. R/C,
2) Select EDID D/L menu.
3) By pressing Enter key, EDID download will begin
4) f Download is successful, OK is display, but If Download is
I
failure, NG is displayed.
5) If Download is failure, Re-try downloads.
EDID Block 1, Bytes 128-255 [80H-FFH]
0 1 2 3 4 5 6 7 8 9 A B C D E F
--------------------------------------------------------------------------------0 | 02 03 34 F1 48 90 22 20 05 04 03 02 01 29 3D 06
10 | C0 15 07 50 09 57 07 78 03 0C 00 20 00 B8 2D 20
20 | C0 0E 01 4F 00 FE 08 10 06 10 18 10 28 10 38 10
30 | E3 05 03 01 02 3A 80 18 71 38 2D 40 58 2C 45 00
40 | 40 84 63 00 00 1E 01 1D 80 18 71 1C 16 20 58 2C
50 | 25 00 40 84 63 00 00 9E 01 1D 00 72 51 D0 1E 20
60 | 6E 28 55 00 40 84 63 00 00 1E 00 00 00 00 00 00
70 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 26
W
※ Caution) hen EDID Download, must remove RGB/HDMI
Cable.
Copyright ©
LG Electronics. Inc. All rights reserved.
Only for training and service purposes
- 12 -
LGE Internal Use Only
# HDMI 3(C/S : E8 16)
EDID Block 0, Bytes 0-127 [00H-7FH]
0 1 2 3 4 5 6 7 8 9 A B C D E F
--------------------------------------------------------------------------------0 | 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01
10 | 01 17 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26
20 | 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80
30 | 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C
40 | 45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30
50 | 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A
60 | 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC
70 | 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 E8
EDID Block 1, Bytes 128-255 [80H-FFH]
0 1 2 3 4 5 6 7 8 9 A B C D E F
--------------------------------------------------------------------------------0 | 02 03 34 F1 48 90 22 20 05 04 03 02 01 29 3D 06
10 | C0 15 07 50 09 57 07 78 03 0C 00 30 00 B8 2D 20
20 | C0 0E 01 4F 00 FE 08 10 06 10 18 10 28 10 38 10
30 | E3 05 03 01 02 3A 80 18 71 38 2D 40 58 2C 45 00
40 | 40 84 63 00 00 1E 01 1D 80 18 71 1C 16 20 58 2C
50 | 25 00 40 84 63 00 00 9E 01 1D 00 72 51 D0 1E 20
60 | 6E 28 55 00 40 84 63 00 00 1E 00 00 00 00 00 00
70 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 16
# HDMI 4(C/S : E8 06)
EDID Block 0, Bytes 0-127 [00H-7FH]
0 1 2 3 4 5 6 7 8 9 A B C D E F
--------------------------------------------------------------------------------0 | 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01
10 | 01 17 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26
20 | 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80
30 | 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C
40 | 45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30
50 | 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A
60 | 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC
70 | 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 E8
EDID Block 1, Bytes 128-255 [80H-FFH]
0 1 2 3 4 5 6 7 8 9 A B C D E F
--------------------------------------------------------------------------------0 | 02 03 34 F1 48 90 22 20 05 04 03 02 01 29 3D 06
10 | C0 15 07 50 09 57 07 78 03 0C 00 40 00 B8 2D 20
20 | C0 0E 01 4F 00 FE 08 10 06 10 18 10 28 10 38 10
30 | E3 05 03 01 02 3A 80 18 71 38 2D 40 58 2C 45 00
40 | 40 84 63 00 00 1E 01 1D 80 18 71 1C 16 20 58 2C
50 | 25 00 40 84 63 00 00 9E 01 1D 00 72 51 D0 1E 20
60 | 6E 28 55 00 40 84 63 00 00 1E 00 00 00 00 00 00
70 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 06
Copyright ©
LG Electronics. Inc. All rights reserved.
Only for training and service purposes
(2)AC3
# HDMI 1(C/S : E8 3F)
EDID Block 0, Bytes 0-127 [00H-7FH]
0 1 2 3 4 5 6 7 8 9 A B C D E F
--------------------------------------------------------------------------------0 | 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01
10 | 01 17 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26
20 | 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80
30 | 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C
40 | 45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30
50 | 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A
60 | 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC
70 | 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 E8
EDID Block 1, Bytes 128-255 [80H-FFH]
0 1 2 3 4 5 6 7 8 9 A B C D E F
--------------------------------------------------------------------------------0 | 02 03 31 f1 48 90 22 20 05 04 03 02 01 26 15 07
10 | 50 09 57 07 78 03 0c 00 10 00 b8 2d 20 c0 0e 01
20 | 4f 00 fe 08 10 06 10 18 10 28 10 38 10 e3 05 03
30 | 01 02 3a 80 18 71 38 2d 40 58 2c 45 00 40 84 63
40 | 00 00 1e 01 1d 80 18 71 1c 16 20 58 2c 25 00 40
50 | 84 63 00 00 9e 01 1d 00 72 51 d0 1e 20 6e 28 55
60 | 00 40 84 63 00 00 1e 00 00 00 00 00 00 00 00 00
70 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 3f
# HDMI 2(C/S : E8 2F)
EDID Block 0, Bytes 0-127 [00H-7FH]
0 1 2 3 4 5 6 7 8 9 A B C D E F
--------------------------------------------------------------------------------0 | 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01
10 | 01 17 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26
20 | 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80
30 | 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C
40 | 45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30
50 | 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A
60 | 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC
70 | 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 E8
EDID Block 1, Bytes 128-255 [80H-FFH]
0 1 2 3 4 5 6 7 8 9 A B C D E F
--------------------------------------------------------------------------------0 | 02 03 31 f1 48 90 22 20 05 04 03 02 01 26 15 07
10 | 50 09 57 07 78 03 0c 00 20 00 b8 2d 20 c0 0e 01
20 | 4f 00 fe 08 10 06 10 18 10 28 10 38 10 e3 05 03
30 | 01 02 3a 80 18 71 38 2d 40 58 2c 45 00 40 84 63
40 | 00 00 1e 01 1d 80 18 71 1c 16 20 58 2c 25 00 40
50 | 84 63 00 00 9e 01 1d 00 72 51 d0 1e 20 6e 28 55
60 | 00 40 84 63 00 00 1e 00 00 00 00 00 00 00 00 00
70 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 2f
- 13 -
LGE Internal Use Only
# HDMI 3(C/S : E8 1F)
EDID Block 0, Bytes 0-127 [00H-7FH]
0 1 2 3 4 5 6 7 8 9 A B C D E F
--------------------------------------------------------------------------------0 | 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01
10 | 01 17 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26
20 | 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80
30 | 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C
40 | 45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30
50 | 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A
60 | 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC
70 | 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 E8
EDID Block 1, Bytes 128-255 [80H-FFH]
0 1 2 3 4 5 6 7 8 9 A B C D E F
--------------------------------------------------------------------------------0 | 02 03 2e f1 48 90 22 20 05 04 03 02 01 23 09 57
10 | 07 78 03 0c 00 10 00 b8 2d 20 c0 0e 01 4f 00 fe
20 | 08 10 06 10 18 10 28 10 38 10 e3 05 03 01 02 3a
30 | 80 18 71 38 2d 40 58 2c 45 00 40 84 63 00 00 1e
40 | 01 1d 80 18 71 1c 16 20 58 2c 25 00 40 84 63 00
50 | 00 9e 01 1d 00 72 51 d0 1e 20 6e 28 55 00 40 84
60 | 63 00 00 1e 00 00 00 00 00 00 00 00 00 00 00 00
70 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b1
# HDMI 4(C/S : E8 0F)
EDID Block 0, Bytes 0-127 [00H-7FH]
0 1 2 3 4 5 6 7 8 9 A B C D E F
--------------------------------------------------------------------------------0 | 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01
10 | 01 17 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26
20 | 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80
30 | 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C
40 | 45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30
50 | 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A
60 | 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC
70 | 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 E8
0 1 2 3 4 5 6 7 8 9 A B C D E F
--------------------------------------------------------------------------------0 | 02 03 31 f1 48 90 22 20 05 04 03 02 01 26 15 07
10 | 50 09 57 07 78 03 0c 00 40 00 b8 2d 20 c0 0e 01
20 | 4f 00 fe 08 10 06 10 18 10 28 10 38 10 e3 05 03
30 | 01 02 3a 80 18 71 38 2d 40 58 2c 45 00 40 84 63
40 | 00 00 1e 01 1d 80 18 71 1c 16 20 58 2c 25 00 40
50 | 84 63 00 00 9e 01 1d 00 72 51 d0 1e 20 6e 28 55
60 | 00 40 84 63 00 00 1e 00 00 00 00 00 00 00 00 00
70 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0f
Copyright ©
LG Electronics. Inc. All rights reserved.
Only for training and service purposes
0 1 2 3 4 5 6 7 8 9 A B C D E F
--------------------------------------------------------------------------------0 | 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01
10 | 01 17 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26
20 | 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80
30 | 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C
40 | 45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30
50 | 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A
60 | 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC
70 | 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 E8
EDID Block 1, Bytes 128-255 [80H-FFH]
0 1 2 3 4 5 6 7 8 9 A B C D E F
--------------------------------------------------------------------------------0 | 02 03 31 f1 48 90 22 20 05 04 03 02 01 26 15 07
10 | 50 09 57 07 78 03 0c 00 30 00 b8 2d 20 c0 0e 01
20 | 4f 00 fe 08 10 06 10 18 10 28 10 38 10 e3 05 03
30 | 01 02 3a 80 18 71 38 2d 40 58 2c 45 00 40 84 63
40 | 00 00 1e 01 1d 80 18 71 1c 16 20 58 2c 25 00 40
50 | 84 63 00 00 9e 01 1d 00 72 51 d0 1e 20 6e 28 55
60 | 00 40 84 63 00 00 1e 00 00 00 00 00 00 00 00 00
70 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 1f
EDID Block 1, Bytes 128-255 [80H-FFH]
(3)PCM
# HDMI 1(C/S : E8 B1)
EDID Block 0, Bytes 0-127 [00H-7FH]
# HDMI 2(C/S : E8 A1)
EDID Block 0, Bytes 0-127 [00H-7FH]
0 1 2 3 4 5 6 7 8 9 A B C D E F
--------------------------------------------------------------------------------0 | 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01
10 | 01 17 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26
20 | 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80
30 | 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C
40 | 45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30
50 | 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A
60 | 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC
70 | 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 E8
EDID Block 1, Bytes 128-255 [80H-FFH]
0 1 2 3 4 5 6 7 8 9 A B C D E F
--------------------------------------------------------------------------------0 | 02 03 2e f1 48 90 22 20 05 04 03 02 01 23 09 57
10 | 07 78 03 0c 00 20 00 b8 2d 20 c0 0e 01 4f 00 fe
20 | 08 10 06 10 18 10 28 10 38 10 e3 05 03 01 02 3a
30 | 80 18 71 38 2d 40 58 2c 45 00 40 84 63 00 00 1e
40 | 01 1d 80 18 71 1c 16 20 58 2c 25 00 40 84 63 00
50 | 00 9e 01 1d 00 72 51 d0 1e 20 6e 28 55 00 40 84
60 | 63 00 00 1e 00 00 00 00 00 00 00 00 00 00 00 00
70 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 A1
- 14 -
LGE Internal Use Only
5. Final Assembly Adjustment
# HDMI 3(C/S : E8 91)
EDID Block 0, Bytes 0-127 [00H-7FH]
0 1 2 3 4 5 6 7 8 9 A B C D E F
--------------------------------------------------------------------------------0 | 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01
10 | 01 17 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26
20 | 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80
30 | 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C
40 | 45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30
50 | 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A
60 | 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC
70 | 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 E8
5.1. White Balance Adjustment
5.1.1. Overview
5.1.1.1. W/B adj. Objective & How-it-works
(1) Objective: To reduce each Panel’s W/B deviation
(2) ow-it-works: When R/G/B gain in the OSD is at 192, it
H
means the panel is at its Full Dynamic Range. In order to
prevent saturation of Full Dynamic range and data, one of
R/G/B is fixed at 192, and the other two is lowered to find
the desired value.
(3) Adj. condition: normal temperature
- Surrounding Temperature: 25±5 °C
- Warm-up time: About 5 Min
- Surrounding Humidity: 20% ~ 80%
- efore White balance adjustment, Keep power on status,
B
don’t power off
5.1.1.2. Adj. condition and cautionary items
(1) ighting condition in surrounding area surrounding lighting
L
should be lower 10 lux. Try to isolate adj. area into dark
surrounding.
(2) robe location: Color Analyzer (CA-210) probe should be
P
within 10cm and perpendicular of the module surface
(80°~ 100°)
(3) Aging time
- fter Aging Start, Keep the Power ON status during 5
A
Minutes.
- n case of LCD, Back-light on should be checked using no
I
signal or Full-white pattern.
EDID Block 1, Bytes 128-255 [80H-FFH]
0 1 2 3 4 5 6 7 8 9 A B C D E F
--------------------------------------------------------------------------------0 | 02 03 2e f1 48 90 22 20 05 04 03 02 01 23 09 57
10 | 07 78 03 0c 00 30 00 b8 2d 20 c0 0e 01 4f 00 fe
20 | 08 10 06 10 18 10 28 10 38 10 e3 05 03 01 02 3a
30 | 80 18 71 38 2d 40 58 2c 45 00 40 84 63 00 00 1e
40 | 01 1d 80 18 71 1c 16 20 58 2c 25 00 40 84 63 00
50 | 00 9e 01 1d 00 72 51 d0 1e 20 6e 28 55 00 40 84
60 | 63 00 00 1e 00 00 00 00 00 00 00 00 00 00 00 00
70 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 91
# HDMI 4(C/S : E8 81)
EDID Block 0, Bytes 0-127 [00H-7FH]
0 1 2 3 4 5 6 7 8 9 A B C D E F
--------------------------------------------------------------------------------0 | 00 FF FF FF FF FF FF 00 1E 6D 01 00 01 01 01 01
10 | 01 17 01 03 80 A0 5A 78 0A EE 91 A3 54 4C 99 26
20 | 0F 50 54 A1 08 00 31 40 45 40 61 40 71 40 81 80
30 | 01 01 01 01 01 01 02 3A 80 18 71 38 2D 40 58 2C
40 | 45 00 40 84 63 00 00 1E 66 21 50 B0 51 00 1B 30
50 | 40 70 36 00 40 84 63 00 00 1E 00 00 00 FD 00 3A
60 | 3E 1E 53 10 00 0A 20 20 20 20 20 20 00 00 00 FC
70 | 00 4C 47 20 54 56 0A 20 20 20 20 20 20 20 01 E8
5.1.2. Equipment
(1) olor Analyzer: CA-210 (NCG: CH 9 / WCG: CH12 / LED:
C
CH14 / OLED : CH : 17)
(2) dj. Computer (During auto adj., RS-232C protocol is
A
needed)
(3) Adjust Remocon
(4) ideo Signal Generator MSPG-925F 720p/204-Gray
V
(Model: 217, Pattern: 49)
※ Color Analyzer Matrix should be calibrated using CS-1000
EDID Block 1, Bytes 128-255 [80H-FFH]
0 1 2 3 4 5 6 7 8 9 A B C D E F
--------------------------------------------------------------------------------0 | 02 03 2e f1 48 90 22 20 05 04 03 02 01 23 09 57
10 | 07 78 03 0c 00 40 00 b8 2d 20 c0 0e 01 4f 00 fe
20 | 08 10 06 10 18 10 28 10 38 10 e3 05 03 01 02 3a
30 | 80 18 71 38 2d 40 58 2c 45 00 40 84 63 00 00 1e
40 | 01 1d 80 18 71 1c 16 20 58 2c 25 00 40 84 63 00
50 | 00 9e 01 1d 00 72 51 d0 1e 20 6e 28 55 00 40 84
60 | 63 00 00 1e 00 00 00 00 00 00 00 00 00 00 00 00
70 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 81
Copyright ©
LG Electronics. Inc. All rights reserved.
Only for training and service purposes
- 15 -
LGE Internal Use Only
5.1.3. Equipment connection
5.1.5.2. OLED White balance table
(1) Cool Mode
- P urpose : Especially B-gain fix adjust leads to the
luminance enhancement. Adjust the color temperature to
reduce the deviation of the module color temperature.
- P rinciple : To adjust the white balance without the
saturation, Adjust the B gain more than 192 ( If R gain or G
gain is more than 255 , G gain can adjust less than 192 )
and change the others ( R/G Gain ).
- Adjustment mode : mode – Cool
(2) Medium / Warm Mode
- P urpose : Adjust the color temperature to reduce the
deviation of the module color temperature
- P rinciple : To adjust the white balance without the
saturation, Fix the B gain to 192 (default data) and
decrease the others
- Adjustment mode : mode – Medium
5.1.4. Adjustment Command (Protocol)
(1) RS-232C Command used during auto-adj.
RS-232C COMMAND
Explanation
CMD
DATA
ID
Wb
00
00
Begin White Balance adj.
Wb
00
ff
End White Balance adj.
(internal pattern disappears )
(3) Warm
- P urpose : Adjust the color temperature to reduce the
deviation of the module color temperature.
- P rinciple : To adjust the white balance without the
saturation, Fix the W gain to 192 (default data) and
decrease the others.
- Adjustment mode : mode – Warm
(2) Adjustment Map
Adj. item
Command
(lower caseASCII)
Data Range
(Hex.)
CMD1
MAX
g
00
C0
j
h
00
C0
j
i
00
C0
R Gain
j
a
00
C0
G Gain
j
b
00
C0
B Gain
j
c
00
C0
R Gain
j
d
00
C0
G Gain
j
e
00
C0
B Gain
Warm
MIN
j
B Gain
Medium
CMD2
R Gain
G Gain
Cool
j
f
00
C0
(4) THX(Warm)
- P urpose : Adjust the color temperature to reduce the
deviation of the module color temperature.
- P rinciple : To adjust the white balance without the
saturation, Fix the W gain to 192 (default data) and
decrease the others.
- Adjustment mode : mode – Warm
- Auto White balance 4 point
- Adjust 100 IRE White Balance
- djust Gamam 2.2 each IRE (60, 40, 20). Using max
A
luminance
- Complete 4 point gamma, W/B.
5.1.5. Adjustment method
5.1.5.1. Auto WB calibration
(1) et TV in ADJ mode using P-ONLY key (or POWER ON
S
key)
(2) Place optical probe on the center of the display
- It need to check probe condition of zero calibration before
adjustment.
(3) Connect RS-232C Cable
(4) Select mode in ADJ Program and begin a adjustment.
(5) hen WB adjustment is completed with OK message,
W
check adjustment status of pre-set mode (Cool, Medium,
Warm)
(6) Remove probe and RS-232C cable.
▪ /B Adj. must begin as start command “wb 00 00” , and
W
finish as end command “wb 00 ff”, and Adj. offset if need
Copyright ©
LG Electronics. Inc. All rights reserved.
Only for training and service purposes
- 16 -
Picture is H 1/3, V 1/3
fixed Center Window size
Outer Black Picture do not need change Contrast / Brightness
Center Level can change Contrast / Bright
Window pattern of Center 0~255 level
LGE Internal Use Only
5.1.6. eference (White Balance Adj. coordinate and
R
color temperature)
(1) Luminance: 204 Gray, 80IRE
(2) tandard color coordinate and temperature using CS-1000
S
(over 26 inch)
5.1.7. eference (White Balance Adj. coordinate and
R
color temperature)
5.3. Magic Motion remote controller Check
5.3.1. Test equipment
▪ F-remote controller for check, IR-KEY-CODE remote
R
controller.
▪ heck AA battery before test. A recommendation is that a
C
tester change battery every lots.
5.3.2. Test
(1) ake pairing with TV set by pressing “Start key(Wheel
M
key)” on RCU.
(2) Check a cursor on screen by pressing ‘Wheel key” of RCU
(3) top paring with TV set by pressing “Back+ Home” key of
S
RCU
▪ Luminance: 204 Gray
▪ tandard color coordinate and temperature using CS-1000
S
(over 26 inch)
Coordinate
Mode
X
Temp
Y
△uv
5.3.3. Applied models
Cool
0.271
0.270
13,000K
0.0000
Medium
0.285
0.293
9,300K
0.0000
Chassis
Model Name
Magic RF receiver
Warm
0.313
0.329
6,500K
0.0000
EA34D
55EA8800-UA
Built-in
▪ tandard color coordinate and temperature using
S
CA-210(CH-14)
Coordinate
Mode
Temp
13,000K
0.0000
0.285±0.002
0.293±0.002
9,300K
0.0000
0.313±0.002
0.329±0.002
6,500K
5.4. Wi-Fi MAC Address Check
5.4.1. Using RS232 Command
△uv
0.270±0.002
55EA9800-UA
0.0000
X
Y
Cool
0.271±0.002
Medium
Warm
Command
Transmission
Set ACK
[A][l][][Set ID][][20][Cr]
[O][K][x] or [N][G]
5.4.2. Check the menu on in-start
▪ tandard color coordinate and temperature using
S
CA-210(CH-14) – by aging time
5.2. ool Option setting & Inspection per
T
countries
5.2.1. Overview
(1) ool option selection is only done for models in Non-USA
T
North America due to rating
(2) pplied model: EA34D Chassis applied to CANADA and
A
MEXICO
5.2.2. Country Group selection
(1) ress ADJ key on the Adj. R/C, and then select Country
P
Group Menu
(2) epending on destination, select US, then on the lower
D
Country option, select US, CA, MX.
Selection is done using +, - KEY
5.2.3. Tool Option inspection
▪ Press Adj. key on the Adj. R/C, then select Tool option
Model
Tool 1
Tool 2
Tool 3
Tool 4
Tool 5
Tool 6
Tool 7
55EA9800-UA
32791
21777
5085
61837
55446
1432
47147
※ Tool option can be reconstructed by Software
Copyright ©
LG Electronics. Inc. All rights reserved.
Only for training and service purposes
- 17 -
LGE Internal Use Only
5.5. 3D pattern test (Only for 3D models)
5.6. HDMI ARC Function Inspection
5.5.1. Test equipment
(1) attern Generator MSHG-600 or MSPG-6100 (HDMI 1.4
P
support)
(2) Pattern: HDMI mode (model No. 872, pattern No. 83)
5.5.2. Test method
5.6.1. Test equipment
- Optic Receiver Speaker
- MSHG-600 (SW: 1220 ↑)
- HDMI Cable (for 1.4 version)
5.6.2. Test method
(1) Input 3D test signal as Fig.1.
(1) nsert the HDMI Cable to the HDMI ARC port from the
I
master equipment (HDMI1)
(2) Press ‘OK” key as a 3D input OSD is shown.
(3) heck pattern as Fig2 without 3D glasses. (3D mode
C
without 3D glasses)
(3) heck the Sound from the Speaker or using AV & Optic
C
TEST program (It’s connected to MSHG-600)
Fig.2
& lt; OK in 3D mode without 3D glasses & gt;
* Remark: nspect in Power Only Mode and check SW version
I
in a master equipment
Fig.3
& lt; NG in 3D mode without 3D glasses & gt;
Copyright ©
LG Electronics. Inc. All rights reserved.
Only for training and service purposes
(2) Check the sound from the TV Set
- 18 -
LGE Internal Use Only
5.7. PIP/ W & R Function Inspection
6.3. Audio Output Inspection
(1) N P U T C H E C K – S K E Y O F A D J U S T R E M O T E
I
CONTROLLER TO INSPECT SPEAKER
(2) hen you click the first, the output volume of left & right
W
main speakers must be 50
(3) hen you click the second, the output volume of left & right
W
main speakers must be 80.
(1) Objective : o check the connection between sub tuner and
T
PCBA, and their Function
(2) Test Method : his Inspection is available only Power-Only
T
Status.
1) Press exit key of the Adj. R/C and Press PIP key.
2) Check that the SUB TUNER pop up window on the TV
Set.
3) Check that the normal operation (picture, sound) of DTV
on the TV Set.
5.8. Ship-out mode check (In-stop)
▪ After final inspection, press In-Stop key of the Adj. R/C and
check that the unit goes to Stand-by mode
(4) hen you click the third, the output volume of left & right
W
main speakers must be 100.
(5) hen you click the fourth, the output volume of left main
W
speaker must be 50.
6. AUDIO output check
6.1. Audio input condition
(6) hen you click the fifth, the output volume of right main
W
speaker must be 50.
(1) RF input: Mono, 1KHz sine wave signal, 100% Modulation
(2) CVBS, Component: 1KHz sine wave signal (0.4Vrms)
(3) RGB PC: 1KHz sine wave signal (0.7Vrms)
6.2. Specification
No
Item
Min
Typ
Max
Unit
Remark
1
Audio
practical
max Output,
L/R
(Distortion=10%
max Output)
9.0
8.5
10.0
8.9
12.0
9.9
W
(1) easurement
M
Vrms
condition
- EQ/AVL/Clear
Voice: Off
(2) peaker (8Ω
S
Impedance)
(7) hen you click the sixth, the output volume of left sub
W
speaker must be 100.
(8) hen you click the seventh, the output volume of right sub
W
speaker must be 100.
(9) hen you click the eighth, the output volume of all
W
speakers (left & right main speaker and left & right sub
speaker) must be 30.
Copyright ©
LG Electronics. Inc. All rights reserved.
Only for training and service purposes
- 19 -
LGE Internal Use Only
7. Soft Touch Key Check
- Before you start a test, you must run a ‘Power Only Mode’.
A
FTER Touch SOFT TOUCH KEY OF SET, LOCAL KEY
CHECK DISPLAY WILL START
8. EYE Q Green Inspection
(1) Turn on TV
(2) Press EYE key of Adj. R/C
(1) Tab Test : Touch SOFT TOUCH KEY OF SET quickly
(3) over the Eye Q sensor on the front of the using your hand
C
and wait for 6 seconds
(2) Left Test : ouch SOFT TOUCH KEY OF SET to the left
T
side.
(4) onfirm that value is lower than 100 of the “Raw Data
C
(Sensor data, Back light )” If after 6 seconds, value is not
lower than 100, replace Eye Q sensor
(3) Right Test : ouch SOFT TOUCH KEY OF SET to the right
T
side
(5) emove your hand from the Eye Q sensor and wait for 6
R
seconds
(4) Long Tab Test : Touch SOFT TOUCH KEY OF SET long.
(6) onfirm that “ok” pop up. If change is not seen, replace
C
Eye Q sensor
- on’t need to run a test with this sequence. For example, the
D
sequence such as ‘Right → Tab → Long Tab → Left’ is
allowed.
Copyright ©
LG Electronics. Inc. All rights reserved.
Only for training and service purposes
- 20 -
LGE Internal Use Only
9. GND and HI-POT Test
9.1. GND & HI-POT auto-check preparation
(1) heck the POWER CABLE and SIGNAL CABE insertion
C
condition
10. USB S/W Download
(optional, Service only)
9.2. GND & HI-POT auto-check
(1) allet moves in the station. (POWER CORD / AV CORD is
P
tightly inserted)
(2) Connect the AV JACK Tester.
(3) Controller (GWS103-4) on.
(4) GND Test (Auto)
- If Test is failed, Buzzer operates.
- If Test is passed, execute next process (Hi-pot test).
(Remove A/V CORD from A/V JACK BOX)
(5) HI-POT test (Auto)
- If Test is failed, Buzzer operates.
- f Test is passed, GOOD Lamp on and move to next process
I
automatically.
(1) Put the USB Stick to the USB socket
(2) Automatically detecting update file in USB Stick
- f your downloaded program version in USB Stick is lower
I
than that of TV set, it didn’t work. Otherwise USB data is
automatically detected.
(3) Show the message “Copying files from memory”
9.3. Checkpoint
(1) Test voltage
- GND: 1.5KV/min at 100mA
- SIGNAL: 3KV/min at 100mA
(2) TEST time: 1 second
(3) TEST POINT
- GND Test = POWER CORD GND and SIGNAL CABLE GND.
- Hi-pot Test = POWER CORD GND and LIVE & NEUTRAL.
(4) LEAKAGE CURRENT: At 0.5mArms
(4) Updating is staring
(5) Updating Completed, The TV will restart automatically
(6) f your TV is turned on, check your updated version and
I
Tool option.
* f downloading version is more high than your TV have, TV
I
can lost all channel data. In this case, you have to channel
recover. If all channel data is cleared, you didn’t have a DTV/
ATV test on production line.
* After downloading, TOOL OPTION setting is needed again.
(1) Push " IN-START " key in service remote controller.
(2) Select " Tool Option 1 " and Push “OK” button.
(3) Punch in the number. (Each model has their number.)
Copyright ©
LG Electronics. Inc. All rights reserved.
Only for training and service purposes
- 21 -
LGE Internal Use Only
11. Optional adjustments
11.2. Manual White balance Adjustment
11.2.1. Adj. condition and cautionary items
11.1. Manual ADC Calibration
(1) ighting condition in surrounding area surrounding lighting
L
should be lower 10 lux. Try to isolate adj. area into dark
surrounding.
(2) robe location: Color Analyzer (CA-210) probe should be
P
within 10cm and perpendicular of the module surface
(80°~ 100°)
(3) Aging time
- fter Aging Start, Keep the Power ON status during 5
A
Minutes.
- n case of LCD, Back-light on should be checked using no
I
signal or Full-white pattern
11.1.1. Equipment & Condition
(1) Adjustment Remocon
(2) 01GF (802B, 802F, 802R) or MSPG925FA Pattern
8
Generator
- R esolution: 480i Comp1 (MSPG-925FA: model-209,
pattern-65)
- esolution: 1080p Comp1 (MSPG-925FA: model-225,
R
pattern-65)
- esolution : 1080p RGB (MSPG-925FA: model-225,
R
pattern-65)
- Pattern : Horizontal 100% Color Bar Pattern
- Pattern level: 0.7±0.1 Vp-p
11.2.2. Equipment
(1) olor Analyzer: CA-210 (NCG: CH 9 / WCG: CH12 / LED:
C
CH14/ OLED : CH17)
(2) dj. Computer (During auto adj., RS-232C protocol is
A
needed)
(3) Adjust Remocon
(4) ideo Signal Generator MSPG-925F 720p/216-Gray
V
(Model: 217, Pattern: 78)
11.1.2. Equipment & Condition
11.1.2.1. ADC 480i/1080p Comp
(1) heck connected condition of Comp cable to the
C
equipment
(2) ive a 480i Mode, Horizontal 100% Color Bar Pattern to
G
Comp1. (MSPG-925FA → Model: 209, Pattern: 65)
(3) hange input mode as Component1 and picture mode as
C
“Standard”
(4) ress the In-start Key on the ADJ remote after at least 1
P
min of signal reception. Then, select 7.External ADC. And
Press OK or Right Button for going to sub menu.
(5) Press OK in Comp 480i menu
(6) ive a 1080p Mode, Horizontal 100% Color Bar Pattern to
G
Comp1. (MSPG-925FA → Model: 225, Pattern: 65)
(7) Press OK in Comp 1080p menu
(8) f ADC Comp is successful, “ADC Component Success” is
I
displayed. If ADC calibration is failure, “ADC Component
Fail” is displayed.
(10) f ADC calibration is failure, after rechecking ADC pattern
I
or condition, retry calibration
(11) f ADC calibration is failure, after recheck ADC pattern or
I
condition, retry calibration
Copyright ©
LG Electronics. Inc. All rights reserved.
Only for training and service purposes
11.2.3. Adjustment
- 22 -
(1) Set TV in Adj. mode using POWER ON
(2) ero Calibrate the probe of Color Analyzer, then place it on
Z
the center of LCD module within 10cm of the surface.
(3) ress ADJ key → EZ adjust using adj. R/C → 6. WhiteP
Balance then press the cursor to the right (KEY►).
When KEY(►) is pressed 216 Gray internal pattern will be
displayed.
(4) ne of R Gain / G Gain / B Gain should be fixed at 192,
O
and the rest will be lowered to meet the desired value.
(5) dj. is performed in COOL, MEDIUM, WARM 3 modes of
A
color temperature.
▪ f internal pattern is not available, use RF input. In EZ Adj.
I
menu 6.White Balance, you can select one of 2 Test-pattern:
O
N, OFF. Default is inner(ON). By selecting OFF, you can
adjust using RF signal in 216 Gray pattern.
LGE Internal Use Only
EXPLODED VIEW
IMPORTANT SAFETY NOTICE
Option
CAM1
AT1
AG1
A22
A2
501
512
510
500
580
200
300
Option
120
511
561
810
820
530
590
560
540
Option
522
521
571
570
121
830
400
710
700
Many electrical and mechanical parts in this chassis have special safety-related characteristics. These
parts are identified by
in the Schematic Diagram and EXPLODED VIEW.
It is essential that these special safety parts should be replaced with the same components as
recommended in this manual to prevent X-RADIATION, Shock, Fire, or other Hazards.
Do not modify the original design without permission of manufacturer.
Copyright ©
LG Electronics. Inc. All rights reserved.
Only for training and service purposes
- 23 -
LGE Internal Use Only
System Configuration
Clock for LG1154D
NVRAM
EEPROM_ST
IC102-*1
M24256-BRMN6TP
+3.3V_NORMAL
E0
MAIN Clock(24Mhz)
E1
X-TAL_1
C101
E2
1
8
8
2
7
3
6
4
5
VCC
WC
SCL
SDA
- Low : Normal Operation
- High : Write Protection
VCC
1M
A0
1
Write Protection
VSS
R108
1
GND_1
10pF
C103
0.1uF
IC102
R1EX24256BSAS0A
XIN_MAIN
2
7
WP
4
A1
GND_2
X-TAL_2
3
2
C100
EEPROM_RENESAS
24MHz
X100
10pF
A2
XO_MAIN
VSS
3
A0’h
4
6
5
SCL
R139
33
I2C_SCL5
R140
SDA
33
I2C_SDA5
System Clock for Analog block(24Mhz)
OPT
R100
EPHY_RXD1
EPHY_TXD0
EPHY_RXD0
EPHY_TXD1
EPHY_MDIO
EPHY_EN
EPHY_MDC
EPHY_REFCLK
EMMC_DATA[1]
EMMC_DATA[0]
EMMC_DATA[2]
EMMC_DATA[5]
EMMC_DATA[3]
EMMC_DATA[4]
EMMC_DATA[6]
EMMC_DATA[7]
EMMC_CLK
EMMC_RST
EB_DATA[2]
EB_DATA[0]
EB_DATA[3]
EB_DATA[1]
EB_DATA[4]
EB_DATA[5]
EB_DATA[6]
EB_ADDR[0]
EB_DATA[7]
EB_ADDR[1]
EB_ADDR[2]
EB_ADDR[3]
EB_ADDR[4]
EB_ADDR[5]
EB_ADDR[8]
EB_ADDR[6]
EB_ADDR[7]
EB_ADDR[9]
EB_ADDR[10]
EB_ADDR[11]
EB_ADDR[12]
EB_BE_N0
EB_ADDR[14]
EB_ADDR[13]
EB_BE_N1
EB_OE_N
USB_CTL3
EB_WE_N
Mhz)
Mhz)
Mhz)
Mhz)
33
R101
/USB_OCD2
USB_CTL2
/USB_OCD3
PLL SET[1:0] : internal pull up
" 00 " : CPU(1200Mhz),M0 / M1 DDR(792,792
" 01 " : CPU(1056Mhz),M0 / M1 DDR(672,672
" 10 " : CPU(1056Mhz),M0 / M1 DDR(792,792
" 11 " : CPU( 960Mhz),M0 / M1 DDR(792,792
EMMC_CMD
EMMC_DATA[0-7]
EB_DATA[0-7]
EPHY_CRS_DV
EB_ADDR[0-14]
33
AL34
GPIO29
GPIO28
B27
XTAL_BYPASS
GPIO27
H13DA_XTAL
AT37
GPIO26
+3.3V_NORMAL
+3.3V_NORMAL
GPIO25
PORES_N
OPM1
AN9
AP11
AN11
AN10
TDO0
AM10
AM9
Jtag I/F For Main
AM11
AM12
AL11
AL9
PLLSET1
AL10
PLLSET0
AE34
BOOT_MODE
TCK0
W34
AT13
AP12
M_REMOTE_RTS
M_REMOTE_CTS
AR12
TP109
IRB_SPI_SS
IRB_SPI_MOSI
IRB_SPI_MISO
IRB_SPI_CK
IRB_SPI_SS
AE36
IRB_SPI_MOSI
AF36
IRB_SPI_MISO
AF35
IRB_SPI_CK
AG34
LOW
non Taiwan
AG33
AG32
For ISP
AL32
AR9
SW100
JTP-1127WEM
UART2_TX
AM5
2
UART2_RX
AM6
AMP_RESET_N
AM7
AL6
1
4
3
INSTANT_BOOT
AK7
DEBUG
AK6
SC_DET
AK5
local dimming
AV1_CVBS_DET
AJ5
AJ6
I2C port
COMP1_DET
AJ7
M_RFModule_RESET
AH6
HP_DET
AG7
FRC_RESET
AG6
/TU_RESET1
/S2_RESET
AG5
AF5
VCOM_DYN
AH30
PMIC_RESET
AG30
/RST_HUB
AN33
FE_LNA_Ctrl2
AK33
/TU_RESET2
AE30
HDMI_S/W_RESET
AD30
AN32
FE_LNA_Ctrl1
AK32
HDMI_INT
R169
3.3K
AC33
R170
3.3K
AB33
HPD0
AE37
UART1_RTS
PHY0_RX1N_0
PHY0_RX1P_0
PHY0_RX2N_0
SPI_CS0/GPIO36
PHY0_RX2P_0
SPI_DO0/GPIO38
PHY0_RXCN_0
SPI_DI0/GPIO39
AC36
AC37
AB36
AB37
AA36
AA37
PHY0_RXCP_0
SPI_SCLK0/GPIO37
AD36
AD37
SPDIF_OUT_ARC
HDMI_RX0HDMI_RX0+
HDMI_RX1HDMI_RX1+
HDMI_RX2HDMI_RX2+
HDMI_CLKHDMI_CLK+
R32
SPI_CS1
HUB_PORT_OVER0
SPI_DO1
/USB_OCD1
R33
SPI_DI1
HUB_VBUS_CTRL0
USB_CTL1
GPIO139
GPIO138
GPIO137
GPIO136
NC_4
NC_3
NC_2
NC_1
USB3_REFPADCLKP
USB3_REFPADCLKM
USB3_RESREF
USB3_TX0M
USB3_TX0P
USB3_RX0M
Not Support
HW_OPT_4
USB3_RX0P
SDA5
USB3_DM0
SCL5
non AJ_JA
USB3_DP0
SDA4
USB2_0_TXRTUNE
I2C_SDA6
SCL4
USB2_0_DM
AH33
USB2_0_DP
I2C_SCL6
Not Support
SDA3
USB2_1_TXRTUNE
AH34
SCL3
USB2_1_DM0
AJ33
I2C_SDA5
SDA2/GPIO77
USB2_1_DP0
Not Support
SCL2/GPIO78
USB2_2_TXRTUNE
AH32
SDA1/GPIO79
USB2_2_DM0
I2C_SDA4
Disable
SCL1/GPIO64
USB2_2_DP0
AR6
SDA0/GPIO65
SD_DATA0/GPIO134
AP6
SCL0/GPIO66
SD_DATA1/GPIO135
Support
RF_SWITCH_CTL
AL33
+3.3V_NORMAL
DDCD0_DA
PHY0_RX0P_0
SD_DATA2/GPIO120
EPI
+3.3V_NORMAL
/RST_PHY
AK34
AC32
PHY0_RX0N_0
SD_DATA3/GPIO121
AJ_JA
MODEL_OPT_10
OLED option
Area2
AN34
GPIO0
DDCD0_CK
PHY0_ARC_OUT_0
CAM_CE1_N
MODEL_OPT_9
HW_OPT_3
AR17
I2C_SCL4
FRC option
Pannel Resol
GPIO1
UART1_TXD
SD_WP_N/GPIO122
Support
S Tuner
GPIO2
UART1_RXD
SD_CD_N/GPIO123
Support
GPIO3
UART0_TXD
SD_CMD/GPIO124
T2 Tuner
MODEL_OPT_8
HW_OPT_2
AP17
I2C_SCL2_SOC
AREA option1
HW_OPT_1
AP16
I2C_SCL5
MODEL_OPT_7
HW_OPT_0
Enable
GPIO4
UART0_RXD
SD_CLK/GPIO125
AR16
I2C_SDA_MICOM_SOC
Default
CP BOX
MODEL_OPT_6
EXT_INTR1/GPIO68
SC_DATA/GPIO132
AP15
I2C_SDA2_SOC
Reserved
EXT_INTR2/GPIO69
SC_RST/GPIO131
V12
MODEL_OPT_5
EXT_INTR3/GPIO70
SC_VCC_SEL/GPIO128
V13
IC100
LG1154D_H13D
PLLSET0
SC_VCCEN/GPIO129
Module
GPIO5
PLLSET1
SC_DETECT/GPIO133
I2C_SCL1
I2C_SDA1
NON OLED
MODEL_OPT_4
TDO1
SC_CLK/GPIO130
EPI
10K
R131
AJ_JA
R129
10K
DVB_S_TUNER
R128
10K
CP_BOX
R124
10K
DVB_T2_TUNER
R126
10K
OPT
10K
R122
V13_MODULE
R120
10K
OLED
R116
10K
FHD
10K
R114
INTERNAL_FRC
R112
10K
TAIWAN
R110
10K
OLED
GPIO6
AF30
AR15
I2C_SCL_MICOM_SOC
OLED
GPIO7
TDI1
CAM_IOIS16_N/GPIO83
UD
MODEL_OPT_3
GPIO8
TCK1
AM32
SPI_SCLK1
No FRC(60Hz)
FHD
TMS1
CAM_REG_N/GPIO72
FRC(120Hz)
Panel
GPIO9
CAM_WAIT_N/GPIO84
FRC
MODEL_OPT_2
TRST_N1
CAM_VCCEN_N/GPIO87
MODEL_OPT_1
GPIO10
CAM_INPACK/GPIO74
Model Option
+3.3V_NORMAL
TDO0
CAM_RESET
HIGH
Taiwan
Area1
GPIO11
AE35
AF33
MODEL_OPT_0
GPIO12
TDI0
CAM_IREQ_N/GPIO73
TP111
GPIO13
TCK0
CAM_VS2_N/GPIO85
TP110
TMS0
CAM_VS1_N/GPIO86
TP107
GPIO14
UART1_CTS
AU13
M_REMOTE_TX
TP100
TRST_N0
EXT_INTR0/GPIO67
AT12
M_REMOTE_RX
TP108
GPIO15
AU12
SOC_RX
C106
33pF
50V
+3.3V_NORMAL
33
SOC_TX
SOC_RESET
TP106
W33
R174
1/16W
5%
TMS0
TP105
33
W32
R164
33
TP104
GPIO16
Y33
33
R151
EPHY_INT
TDO0
TP103
GPIO17
BOOT_MODE
R149
TDI0
GPIO18
H13DA_SCL
CAM_CD2_N/GPIO75
R118
3.3K
TCK0
TRST_N0
GPIO19
AP9
TDI0
TP102
GPIO20
H13DA_SDA
AU26
TMS0
TP101
OPM1
AT26
H13A_SCL
H13A_SDA
BOOT_MODE0
GPIO21
OPM0
AD33
TRST_N0
INSTANT_MODE0
GPIO22/UART2_RX
AD34
OPM0
BOOT_MODE
INSTANT_BOOT
GPIO23/UART2_TX
AU16
SOC_RESET
CAM_CD1_N/GPIO76
3.3K
BOOT MODE
" 0 : EMMC
" 1 : TEST MODE
CAM_CE2_N
(internal pull down)
R117
OPT
3.3K
OPT
R150
GPIO24
INSTANT boot MODE
" 1 : Instant boot
" 0 : normal
CAM_SLIDE_DET
AM33
3.3K
GPIO30
R103
GPIO31
DEBUG
RMII_RXD0
AR11
AU10
AT10
AT11
RMII_RXD1
RMII_TXD0
RMII_TXD1
RMII_TXEN
AR10
RMII_MDC
AT8
AR8
RMII_MDIO
RMII_CRS_DV
RMII_REF_CLK
AU11
U36
U37
EMMC_DATA0
EMMC_DATA1
EMMC_DATA2
U35
EMMC_DATA3
V36
V35
W36
V37
EMMC_DATA4
EMMC_DATA5
EMMC_DATA7
EMMC_DATA6
T36
Y36
Y37
W35
EMMC_RESETN
EMMC_CMD
EMMC_CLK
A36
EB_DATA0/GPIO114
EB_DATA1/GPIO115
C34
EB_DATA2/GPIO116
B34
A34
EB_DATA3/GPIO117
EB_DATA4/GPIO118
A33
B33
C33
EB_DATA5/GPIO119
EB_DATA6/GPIO104
EB_DATA7/GPIO105
C32
EB_ADDR0/GPIO106
B35
EB_ADDR1/GPIO107
B37
B36
EB_ADDR2/GPIO108
EB_ADDR3/GPIO109
C35
C36
D35
EB_ADDR6/GPIO96
EB_ADDR4/GPIO110
EB_ADDR5/GPIO111
D37
D36
EB_ADDR7/GPIO97
EB_ADDR8/GPIO98
E35
EB_ADDR9/GPIO99
E37
F35
F36
G35
G36
G37
H37
J36
J35
H36
H35
L35
K37
K36
E36
EB_ADDR10/GPIO100
EB_ADDR11/GPIO101
XOUT
EB_ADDR14/GPIO88
XIN
EB_ADDR12/GPIO102
B26
EB_ADDR13/GPIO103
560
EB_BE_N0/GPIO80
R152
EB_ADDR15/GPIO89
XO_MAIN
EB_OE_N/GPIO82
A26
XIN_MAIN
EB_WAIT/GPIO94
OPM1
OPM0
EB_CS0/GPIO90
33
OPT
EB_WE_N/GPIO95
33
R134
EB_BE_N1/GPIO81
OPT
R133
EB_CS1/GPIO91
K35
EB_CS3/GPIO93
+3.3V_NORMAL
EB_CS2/GPIO92
OP MODE[1:0]
" 00 " : Normal Mode
" 01/10/11 " : Internal Test mode
AU8
PLLSET1
PLLSET0
OPT
J34
K32
J33
J32
M31
L33
AJ31
L32
P32
P33
N34
R37
R36
N37
N36
P36
P37
AP7
AT7
AU7
K33
M36
M37
K34
L36
L37
C24
D24
E24
D25
E25
B25
C25
A25
V34
V33
V32
T32
U33
T33
H33
D34
H32
D33
G34
F32
G33
G32
E32
E33
TP112
200 1%
Debug
R162
R165
3.3K
12507WS-04L
IR_B_RESET
USB3_TX0M
USB3_TX0P
USB3_RX0M
USB3_RX0P
USB3_DM
USB3_DP
P101
+3.3V_NORMAL
IR_B_RESET
0.1uF
C105
0.1uF
C104
WIFI_DM
R161
200 1%
WIFI_DP
USB_DM2
R159 200 1%
USB_DP2
USB2_HUB_IC_IN_DM
R157 200 1%
USB2_HUB_IC_IN_DP
Only SMART CARD
interface
SMARTCARD_DATA/SD_EMMC_CLK
SMARTCARD_RST/SD_EMMC_DATA[2]
SMARTCARD_VCC/SD_EMMC_CMD
SMARTCARD_DET/SD_EMMC_DATA[3]
CAM_REG_N
CAM_WAIT_N
SMARTCARD_PWR_SEL/SD_EMMC_DATA[1]
I2C for tuner
CI
I2C for tuner
I2C_SDA5
SMARTCARD_CLK/SD_EMMC_DATA[0]
I2C_SDA4
I2C_SCL4
+3.3V_NORMAL
R155
10K
I2C_SDA2_SOC
I2C_SCL2_SOC
PCM_RESET
I2C_SCL1
I2C_SDA_MICOM_SOC
I2C_SCL_MICOM_SOC
I2C_SCL5
Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
Only for training and service purposes
I2C_SCL2_SOC
I2C_SDA1
I2C_SDA6
I2C_SCL6
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
I2C_SDA2_SOC
PCM_5V_CTL
R104
CAM_INPACK_N
I2C_SCL2
I2C_SCL_MICOM_SOC
CAM_IREQ_N
I2C_SDA2
I2C_SDA_MICOM_SOC
R148
3.3K
R147
3.3K
R145
3.3K
R144
3.3K
R143
3.3K
R141
3.3K
R142
3.3K
R137
3.3K
R138
3.3K
R102
R106
R154
10K
CI
NON_EPI
R132
10K
NON_AJ_JA
R130
10K
NON_DVB_S_TUNER
R127
10K
NON_CP_BOX
R123
10K
NON_DVB_T2_TUNER
R125
10K
10K
R121
V12_MODULE
R119
10K
NON_OLED
R115
10K
10K
UD
R113
NO_FRC
R111
10K
NON_TAIWAN
R109
10K
EPI selection
KR_PIP
R136-*1 1.5K
KR_PIP_NOT
R135
3.3K
KR_PIP_NOT
R136
3.3K
AREA option2
KR_PIP
R135-*1 1.5K
HW_OPT_9
R146
3.3K
I2C PULL UP
HW_OPT_10
33
33
CAM_CD2_N
+3.3V_NORMAL
HW_OPT_8
satellite support
R105
/PCM_CE1
+3.3V_NORMAL
T2 support
33
33
I2C_SCL_MICOM
/PCM_CE2
HW_OPT_7
+3.3V_TU
CAM_CD1_N
I2C_SDA_MICOM
+3.3V_TU
CI
R153
10K
reserved
CP BOX
D32
HW_OPT_5
HW_OPT_6
F34
F33
EPI PANEL version
1
DEBUG
UART2_RX
2
3
AC-coupling CAP
Place near by LG1154D
UART2_TX
4
5
BSD-NC4_H001-HD
2012-11-14
H13 D CHIP
LGE Internal Use Only
LG1154A
LG1154D
LG1154A
IC100
LG1154D_H13D
H13A_NON_BRAZIL
+3.3V_Bypass Cap
IC101
LG1154AN_H13A
VREF_M0_0
VREF_M0_1
T18
AVDD10_VSB
M8
AVDD10_LLPLL
G10
DVDD10_APLL_1
G11
DVDD10_APLL_2
G12
LTX_VDD
GND_79
GND_80
GND_81
GND_82
GND_83
GND_84
GND_85
GND_86
V5
VSS25_REF
VSS25_REF
C3
GND_1
D3
GND_2
D4
GND_87
GND_88
GND_89
GND_3
GND_4
D17
E4
GND_90
GND_91
GND_5
F4
GND_6
F7
GND_7
F8
GND_8
F9
GND_9
F10
GND_10
F12
GND_11
F13
GND_12
F17
GND_13
F18
GND_14
G4
GND_15
G6
GND_16
G13
GND_17
G14
GND_18
G15
GND_19
G16
GND_20
G17
GND_21
G18
GND_22
H4
GND_23
H5
GND_24
H6
GND_25
H8
GND_26
H9
GND_27
H10
GND_28
H11
GND_29
GND_92
GND_93
GND_94
GND_95
GND_96
GND_97
GND_98
GND_99
GND_100
GND_101
GND_102
GND_103
GND_104
GND_105
GND_106
GND_107
GND_108
GND_109
GND_110
GND_111
GND_112
GND_113
GND_114
GND_115
0.1uF
C297
4.7uF
C300
C279
4.7uF
C255
4.7uF
C351
4.7uF
VDDC11_12
VDD33_5
VDDC11_13
VDD33_6
VDDC11_14
VDD33_7
VDDC11_15
VDDC11_16
VDDC11_17
AVDD33_USB_1
VDDC11_18
AVDD33_USB_2
VDDC11_19
AVDD33_BT_USB_1
VDDC11_20
AVDD33_BT_USB_2
VDDC11_21
0.1uF
AVDD33_HDMI_1
VDDC11_22
VDDC11_23
VDDC11_25
C301
VDDC11_26
VDDC11_27
VDD25_LVRX_1
VDDC11_28
VDD25_LVRX_2
VDDC11_29
VTXPHY_VDD25_1
VDDC11_30
VTXPHY_VDD25_2
VDDC11_31
VDD25_DR3PLL
VDDC11_32
M10
M11
M14
M15
M16
N4
VDDC11_33
VDDC11_34
OPT
H15
H16
H17
H18
H19
H20
H21
H22
H23
H24
N5
H25
VDD15_M0_1
C5
+1.1V
C26
C27
D5
N23
D26
E5
P15
E6
E7
P16
E8
E22
P17
E23
E26
P18
F7
F8
R15
T15
F22
F23
+1.1V_VDD
F24
F25
T22
F26
F27
T23
F31
T24
G8
G7
G9
U15
G10
G11
U22
G12
U23
G14
G13
G15
U24
G16
G17
V15
G18
V22
G20
G19
G21
V23
G22
V24
G24
G23
G25
W22
G26
G27
W23
G28
W24
G30
G29
G31
AB15
H9
H26
AB24
H27
AC15
H29
H28
H30
AC24
H31
J7
AD15
J30
J31
AD16
K7
K30
AD17
K31
AD18
L31
L30
M7
AD21
M12
M13
AD22
M14
AD23
M16
M15
M17
AD24
M18
M19
VDDC11_35
M20
M24
VDD15_M0_2
M25
M26
VDD15_M0_3
VDD15_M0_4
M32
M33
M34
VDD15_M0_5
VDD15_M0_6
M30
VDD11_VTXPHY
AB14
VTXPHY_VDD11_1
VDD15_M0_7
VTXPHY_VDD11_2
VDD15_M0_8
N12
N13
AC14
N14
AD14
N16
N15
VTXPHY_VDD11_3
VDDC11_XTAL
N17
N18
N19
VDD15_M0_9
P25
VDD15_M0_10
AVDD11_DR3PLL
VDD15_M0_11
AVDD11_DCO
VDD15_M0_12
GPLL_VDD11
N20
AA15
N30
N24
AC26
+1.1V_VDD
N31
N32
N33
P7
VDD15_M0_13
P12
VDD15_M0_14
P14
P13
P19
P20
VDD15_M0_15
P21
P22
VDD15_M0_16
N14
N22
P23
P24
N15
H7
N17
H8
P4
J8
P5
K8
P6
L7
P7
L8
P8
VDDC15_M1
P9
M8
N7
P10
N8
P11
P8
+1.5V_Bypass Cap
P14
P15
R7
R8
P16
T8
R4
U8
R7
+1.5V_DDR
+1.0V_Bypass Cap
VDDC15_M0
VDDC15_M0
V8
VDDC15_M0
P30
P31
VDD15_M1_1
R12
VDD15_M1_2
R13
VDD15_M1_3
R16
VDD15_M1_4
R18
VDD15_M1_5
R20
R14
R17
R19
R21
R22
VDD15_M1_6
R23
VDD15_M1_7
R24
VDD15_M1_8
R26
R25
R30
VDD15_M1_9
R34
VDD15_M1_10
T12
VDD15_M1_11
T14
T7
T13
T16
T17
VDD15_M1_12
T18
T19
VDD15_M1_13
T20
T21
VDD15_M1_14
T25
W8
R9
+1.0V_VDD
R10
VDD10_XTAL
R11
R12
L230
L211
BLM18PG121SN1D
R13
R16
R17
T4
T26
T31
T30
T34
VREF_M0_1
U7
U12
U13
U14
U16
U17
U18
R14
R15
VREF_M0_0
VDD15_M1_15
VDD15_M1_16
R8
T7
BLM18PG121SN1D
OPT
OPT
U19
0.1uF
AVDD10_CVBS
GND_78
VDD33_4
U20
U21
U25
U26
U30
U31
V7
V12
V13
V14
V16
V17
V18
T8
V19
V20
T9
V21
V25
T10
V26
V30
T11
V31
+1.0V_VDD
W5
T12
W6
VDDC10
T15
+1.5V_DDR
VDDC15_M1
W7
VDDC15_M1
VDDC15_M1
W12
W13
L206
BLM18PG121SN1D
T16
U4
W14
W15
VREF_M1_0
U6
U18
V4
V16
GND_116
L228
W16
VREF_M1_1
H13A_BRAZIL
IC101-*1
LG1154AN_H13A_ISDB-T (LG1154AN-IT)
W17
W18
W19
W20
W21
W25
BLM18PG121SN1D
OPT
OPT
P17
0.1uF
VDDC10_13
T17
M9
L200
BLM18PG121SN1D
VDDC15_M0
R202
M12
GND_77
VDDC11_11
1K 1%
VDDC10_12
L207
BLM18PG121SN1D
VDD25_AUD
1%
M7
GND_76
M4
M5
+2.5V_Normal
VDD25_LTX
R203
VDDC10_11
GND_75
+2.5V_Normal
1K
VDDC10_10
L12
VDD33_3
C344
L7
GND_74
M3
H14
R302
VDDC10_9
GND_73
M2
1K 1%
VDDC10_8
K12
H12
H13
1%
GND_72
M1
R303
VDDC10_7
K7
GND_71
+1.5V
L201
BLM18PG121SN1D
P18
J17
H18
XIN_SUB
XO_SUB
AAD_ADC_SIF
D18
XTAL_BYPASS
AUDA_OUTL
CLK_24M
AUDA_OUTR
XTAL_SEL0
AUD_SCART_OUTL
XTAL_SEL1
M17
H17
W30
Y3
N1
Y4
N2
GND_1
GND_185
GND_2
GND_186
GND_3
GND_187
GND_4
GND_188
GND_5
GND_189
GND_6
GND_190
GND_7
GND_191
GND_8
GND_192
GND_9
GND_193
GND_10
GND_194
GND_11
GND_195
GND_12
GND_196
GND_13
GND_197
GND_14
GND_198
GND_15
GND_199
GND_16
GND_200
GND_17
GND_201
GND_18
GND_202
GND_19
GND_203
GND_20
GND_204
GND_21
GND_205
GND_22
GND_206
GND_23
GND_207
GND_24
GND_208
GND_25
GND_209
GND_26
GND_210
GND_27
GND_211
GND_28
GND_212
GND_29
GND_213
GND_30
GND_214
GND_31
GND_215
GND_32
GND_216
GND_33
GND_217
GND_34
GND_218
GND_35
GND_219
GND_36
GND_220
GND_37
GND_221
GND_38
GND_222
GND_39
GND_223
GND_40
GND_224
GND_41
GND_225
GND_42
GND_226
GND_43
GND_227
GND_44
GND_228
GND_45
GND_229
GND_46
GND_230
GND_47
GND_231
GND_48
GND_232
GND_49
GND_233
GND_50
GND_234
GND_51
GND_235
GND_52
GND_236
GND_53
GND_237
GND_54
GND_238
GND_55
GND_239
GND_56
GND_240
GND_57
GND_241
GND_58
GND_242
GND_59
GND_243
GND_60
GND_244
GND_61
GND_245
GND_62
GND_246
GND_63
GND_247
GND_64
GND_248
GND_65
GND_249
GND_66
GND_250
GND_67
GND_251
GND_68
GND_252
GND_69
GND_253
GND_70
GND_254
GND_71
GND_255
GND_72
GND_256
GND_73
GND_257
GND_74
GND_258
GND_75
GND_259
GND_76
GND_260
GND_77
GND_261
GND_78
GND_262
GND_79
GND_263
GND_80
GND_264
GND_81
GND_265
GND_82
GND_266
GND_83
GND_267
GND_84
GND_268
GND_85
GND_269
GND_86
GND_270
GND_87
GND_271
GND_88
GND_272
GND_89
GND_273
GND_90
GND_274
GND_91
GND_275
GND_92
GND_276
GND_93
GND_277
GND_94
GND_278
GND_95
GND_279
GND_96
GND_280
GND_97
GND_281
GND_98
GND_282
GND_99
GND_283
GND_100
GND_284
GND_101
GND_285
GND_102
GND_286
GND_103
GND_287
GND_104
GND_288
GND_105
GND_289
GND_106
GND_290
GND_107
GND_291
GND_108
GND_292
GND_109
GND_293
GND_110
GND_294
GND_111
GND_295
GND_112
GND_296
GND_113
GND_297
GND_114
GND_298
GND_115
GND_299
GND_116
GND_300
GND_117
GND_301
GND_118
GND_302
GND_119
GND_303
GND_120
GND_304
GND_121
GND_305
GND_122
GND_306
GND_123
GND_307
GND_124
GND_308
GND_125
GND_309
GND_126
GND_310
GND_127
GND_311
GND_128
GND_312
GND_129
GND_313
GND_130
GND_314
GND_131
GND_315
GND_132
GND_316
GND_133
GND_317
GND_134
GND_318
GND_135
GND_319
GND_136
GND_320
GND_137
GND_321
GND_138
GND_322
GND_139
GND_323
GND_140
GND_324
GND_141
GND_325
GND_142
GND_326
GND_143
GND_327
GND_144
GND_328
GND_145
GND_329
GND_146
GND_330
GND_147
GND_331
GND_148
GND_332
GND_149
GND_333
GND_150
GND_334
GND_151
GND_335
GND_152
GND_336
GND_153
GND_337
GND_154
GND_338
GND_155
GND_339
GND_156
GND_340
GND_157
GND_341
GND_158
GND_342
GND_159
GND_343
GND_160
GND_344
GND_161
GND_345
GND_162
GND_346
GND_163
GND_347
GND_164
GND_348
GND_165
GND_349
GND_166
GND_350
GND_167
GND_351
GND_168
GND_352
GND_169
GND_353
GND_170
GND_354
GND_171
GND_355
GND_172
GND_356
GND_173
GND_357
GND_174
GND_358
GND_175
GND_359
GND_176
GND_360
GND_177
GND_361
GND_178
GND_362
GND_179
GND_363
GND_180
GND_364
GND_181
GND_365
GND_182
GND_366
GND_183
GND_367
GND_184
W31
P2
AUDA_VBG_EXT
N18
W26
AAD_ADC_SIFM
VSB_AUX_XIN
M18
1K
VDDC10_6
J12
VDD10_XTAL
GND_70
L18
C310
VDDC10_5
J7
H11
VDD11_VTXPHY
0.1uF
H12
GND_69
L17
0.1uF
VDDC10_4
VDDC11_10
H10
+1.1V_VDD
1K 1%
H7
GND_68
L16
C296
VDDC10_3
GND_67
1005 size bead
Bottom side of chip
1K 1%
VDDC10_2
G9
VDD33_2
GPLL_AVDD25
L15
C304
G8
GND_66
AD26
OPT
VDDC10_1
GND_65
VSS25_REF
0.1uF
VDD10_XTAL
G7
L14
C208
GND_64
R18
VDDC10
GND_63
AF14
N25
R200
SDRAM_VDDQ_5
VDD10_XTAL
GND_62
L13
1%
SDRAM_VDDQ_4
K16
VDD25_XTAL
R201
K15
GND_61
AE14
1K
SDRAM_VDDQ_3
L11
L226
BLM15BD121SN1
R300
J16
GND_60
L10
1%
SDRAM_VDDQ_2
GND_59
VDDC11_9
SP_VQPS
AF23
R301
SDRAM_VDDQ_1
J15
L9
1K
H15
GND_58
VDD33_1
AE23
0.1uF
LTX_LVDD_2
GND_57
L8
0.1uF
LTX_LVDD_1
F16
GND_56
VDDC11_8
VDDC11_24
VDD25_LVDS
C206
VDD25_AAD
F15
VDDC11_7
R31
C207
M13
GND_55
VDDC11_6
+2.5V
0.1uF
VDD25_AUD_2
L6
0.1uF
VDD25_LTX
GND_54
L5
C308
VDD25_AUD_1
N6
L220
BLM18PG121SN1D
L4
C298 4.7uF
M6
GND_53
L225
BLM15BD121SN1
OPT
VDD25_APLL
XTAL_VDD
AVDD33_HDMI_2
AF26
C205 4.7uF
F14
GND_52
L3
L227
BLM18PG121SN1D
VDD25_REF
AVDD25
C209 4.7uF
VDD25_COMP_3
+2.5V_Normal
L2
0.1uF
VDD25_AUD
GND_51
AF25
C306
VDD25_COMP_2
N9
L1
0.1uF
VDD25_LTX
AK12
VDDC11_XTAL
C303 22uF
N8
GND_50
AFE 3CH Power
C302
VDD25_COMP_1
+1.1V_VDD
K14
C299 22uF
N7
GND_49
AK11
C307
VDD25_REF
GND_48
K13
M23
0.1uF
VDD25_VSB_2
U5
+2.5V_Bypass Cap
K11
4.7uF
N13
GND_47
VDDC11_5
M22
C204
VDD25_VSB_1
GND_46
K10
C202
VDD25_CVBS_2
N12
VDDC11_4
VDD33_8
0.1uF
N11
GND_45
AF8
K9
C288
VDD25_CVBS_1
AE8
AK25
C200 4.7uF
GND_44
N10
VDD25_REF
GND_43
Y30
AA30
K8
0.1uF
AVDD33_CVBS_2
VDDC11_3
P26
AK24
C270
4.7uF
T14
GND_42
VDDC11_2
M1_DDR_VREF1
M21
K6
C274
AVDD33_CVBS_1
M0_DDR_VREF2
M1_DDR_VREF2
A2
AK13
0.1uF
T13
GND_41
VDDC11_1
+3.3V
K5
C246
VDD33_XTAL
GND_40
N21
M0_DDR_VREF1
XTAL_VDDP
0.1uF
VDD33_11
N16
A4
N26
C251
R6
GND_39
B5
A24
Y1
VDD33
Y5
A27
VDDC11_XTAL
VDD25_XTAL
K4
C242
4.7uF
VDD33_10
GND_38
J14
0.1uF
VDD33_9
R5
GND_37
C223
VDD33_8
P13
J11
C239
4.7uF
P12
GND_36
J10
C214
4.7uF
VDD33_7
GND_35
J9
C211
4.7uF
VDD33_6
J13
J8
C216
4.7uF
H13
GND_34
0.1uF
VDD33_5
C218
G5
GND_33
VREF_M1_1
+1.1V_VDD
L222
BLM18PG121SN1D
J5
J6
VREF_M1_0
AVDD33_CVBS(2)
L216
BLM18PG121SN1D
C275
4.7uF
VDD33_4
GND_32
L209
BLM18PG121SN1D
J4
C241
4.7uF
GND_31
VDD33_3
F11
AVDD25
GND_30
VDD33_2
F6
AVDD33_XTAL
AVDD33_CVBS
AVDD33_XTAL
(1)
H14
VDD33_1
F5
0.1uF
E11
+1.1V_Bypass Cap
+3.3V_NORMAL
+3.3V_NORMAL
(2)
0.1uF
AVDD33
C283
+3.3V_NORMAL
C259
AVDD33
IC100
LG1154D_H13D
+0.75V
Y8
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
Y23
Y24
Y25
Y26
Y31
Y35
AA8
AA12
AA13
AA14
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AA23
AA24
AA25
AA26
AA31
AB6
AB8
AB12
AB13
AB16
AB17
AB18
AB19
AB20
AB21
AB22
AB23
AB25
AB26
AB30
AB31
AC8
AC12
AC13
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
AC25
AC30
AC31
AD8
AD12
AD13
AD19
AD20
AD25
AD31
AE12
AE13
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE24
AE25
AE26
AE31
AF12
AF13
AF15
AF16
AF17
AF18
AF19
AF20
AF21
AF22
AF24
AF31
AG8
AG31
AH8
AH31
AJ8
AJ30
AK8
AK9
AK10
AK14
AK15
AK16
AK17
AK18
AK19
AK20
AK21
AK22
AK23
AK26
AK27
AK28
AK29
AK30
AK31
AL8
AL12
AL13
AL14
AL15
AL16
AL17
AL18
AL19
AL20
AL21
AL22
AL23
AL24
AL25
AL26
AL27
AL28
AL29
AL30
AL31
AM8
AM13
AM14
AM15
AM16
AM17
AM18
AM19
AM20
AM21
AM22
AM23
AM24
AM25
AM26
AM27
AM28
AM29
AM30
AM31
AN6
AN12
AN13
AN15
AN16
AN17
AN18
AN19
AN20
AN21
AN22
AN23
AN24
AN25
AN26
AN27
GND_368
AN28
AN29
AN30
AN31
N3
AUD_SCART_OUTR
P1
P3
AUAD_L_CH4_IN
AUAD_R_CH4_IN
E3
PORES_N
AUAD_L_CH3_IN
AUAD_R_CH3_IN
K3
OPM0
AUAD_L_CH2_IN
OPM1
K2
AUAD_R_CH2_IN
AUAD_L_CH1_IN
A8
H13A_SCL
AUAD_R_CH1_IN
H13A_SDA
B8
AUAD_R_REF
AUAD_M_REF
AUAD_L_REF
V15
CVBS_IN3
CVBS_IN2
CVBS_IN1
U3
V2
V3
U1
T3
T2
RFAGC
R3
BUF_OUT1
ADC_I_INCOM
BUF_OUT2
ADC_I_INP
K18
IFAGC
J18
U16
U15
U14
T1
U2
K17
ANTCON
CVBS_VCM
V13
R2
AUAD_REF_PO
U13
V14
R1
U17
V17
ADC_I_INN
F3
GPIO0
U7
V6
V7
U10
V12
T5
GND JIG POINT
SMD TOP for EMI
+3.3V_Bypass Cap
+2.5V_Bypass Cap
+3.3V_NORMAL
V8
V9
+2.5V_Normal
+2.5V_Normal
VDD33
T6
U8
VDD25_XTAL
(1)
U9
VDD25_LVDS(4)
V10
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
REFB
GPIO2
ADC1_COM
GPIO3
ADC2_COM
GPIO4
ADC3_COM
GPIO5
SC1_SID
GPIO6
SC1_FB
GPIO7
PB1_IN
GPIO8
Y1_IN
GPIO9
SOY1_IN
GPIO10
PR1_IN
GPIO11
GPIO12
GPIO13
SOY2_IN
GPIO14
G3
G2
G1
H3
H2
H1
J3
E18
E17
H16
GPIO15
J2
J1
K1
0.1uF
C378
4.7uF
PB2_IN
Y2_IN
F2
F1
C381
0.1uF
C368
0.1uF
U12
L238
BLM18PG121SN1D
C364
4.7uF
MDS62110209
C203
NON_LA8600
GASKET_8.0X6.0X8.5H
M200
C201
4.7uF
JP205
JP204
JP203
JP202
L234
BLM18PG121SN1D
GPIO1
PR2_IN
U11
V11
L203
BLM18PG121SN1D
REFT
BSD-NC4_H002-HD
2012-12-24
MAIN POWER
11/05/31
Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
IC101
LG1154AN_H13A
+3.3V_NORMAL
OP MODE Setting
& Select XTAL Input
Clock for H13A
CLK_54M_VTT
IC100
LG1154D_H13D
H13A_NON_BRAZIL
E1
INTR_GBB
INTR_AFE3CH
+3.3V_NORMAL
AT16
E2
AU17
D1
AT17
1M
R460
R461
R462
10K
10K
AUD_FS21CLK
R484 OPT
R441
10K
10K
R459
XTAL SEL[1:0] : SW[4:3]
00 = & gt; Xtal Input
01 = & gt; CLK 24M from H13D
10 = & gt; XTAL Bypass from H13D
XOUT_SUB
R482 OPT
OPT
R483
R481 OPT
X-TAL_1
GND_1
1
2
C427
OP MODE[0:1] : SW[2:1]
00 = & gt; Normal Operaiton Mode
/T32 Debug Mode
01 = & gt; Internal Test Purpose
10 = & gt; Internal Test Purpose
11 = & gt; Internal Test Purpose
4
3
10pF
1/16W
1%
R466
82
X-TAL_2
DAC_START_PULLDOWN
XIN_SUB
24MHz
X400
10pF
C426
GND_2
R464
1K
1/16W
1%
1/16W
1%
R465
390
MAIN Clock(24Mhz)
C404
0.01uF
50V
A6
AUD_FS20CLK
AUD_FS23CLK
AUD_FS24CLK
AUD_FS25CLK
100
XTAL_SEL[0]
100
AUD_DAC1_SCK
XTAL_SEL[1]
AUD_DAC1_LRCH
AUD_ADC_LRCK
AV1_CVBS_IN
100 C424
IC101 H13A_NON_BRAZIL
LG1154AN_H13A
AUD_ADC_SCK
0.047uF
L409 1uH
R433
100 C425
H18
XIN_SUB
330P18
J17
R453
0.047uF
AAD_ADC_SIF
XO_SUB
VSB_AUX_XIN
C462
150pF
EU
R411
75
1%
C423
10K EU
SCART_FB_DIRECT
EU
R436
2.7K
R422
0.047uF
33 C419
BB_TP_DATA6
R479
SCART_Lout_SOC
BB_TP_DATA5
R480
EU 100
EU 100
P1
SCART_Rout_SOC
BB_TP_DATA4
R447
R429
COMP1_Y
33 C420
33 C421
1000pF
33 C422
R431
R417 1% 75
R415 1% 75
R413 1% 75
50V 10pF
C431
ADC_I_INCOM
BUF_OUT2
0.047uF
0.047uF
ADC_I_INP
REFT
0.047uF
GPIO7
PB1_IN
GPIO8
Y1_IN
V9
COMP1_Y_IN_SOC_SOY
GPIO6
SC1_FB
V8
GPIO5
SC1_SID
U8
GPIO4
ADC3_COM
T6
COMP1_Y_IN_SOC
GPIO3
ADC2_COM
T5
GPIO2
ADC1_COM
V12
GPIO1
REFB
V7
COMP1_PB_IN_SOC
GPIO9
SOY1_IN
U12
COMP2_PR_IN_SOC
GPIO14
PR2_IN
COMP2_Y_IN_SOC_SOY
GPIO13
SOY2_IN
V11
GPIO12
Y2_IN
U11
COMP2_Y_IN_SOC
GPIO11
PB2_IN
V10
COMP2_PB_IN_SOC
GPIO10
PR1_IN
U9
COMP1_PR_IN_SOC
Near Place Scart AMP
GPIO0
U10
SC_FB_SOC
COMP2_PR_IN_SOC
C458
EU
C460
EU R442
22K
AUAD_L_CH2_IN
U3
BB_TP_DATA2
BB_TP_DATA1
CVBS_GC2
CVBS_GC1
CVBS_GC0
AUAD_R_REF
T3
CVBS_UP
AUAD_M_REF
T2
Close to IC4300
AUAD_REF_PO
FS00CLK
AUDCLK_OUT
NON_TU_W_BR/TW/CO
R487
K18
J18
C454
DAC_DATA4
C459
0.1uF
TU_W_BR/TW/CO
0.1uF
ADC_I_INP
V17
DAC_DATA3
DAC_DATA2
DAC_DATA1
ADC_I_INN
DAC_DATA0
AAD_GC4
TU_W_BR/TW/CO
HW_OPT_1
F1
R487-*1
HW_OPT_2
G3
AAD_GC3
AAD_GC2
HW_OPT_3
G2
AAD_GC1
10K
HW_OPT_4
EU
G1
HW_OPT_5
H3
HW_OPT_6
H2
AAD_DATA9
HW_OPT_7
J3
E18
AAD_DATA8
HW_OPT_8
AAD_DATA7
HW_OPT_9
H1
AAD_DATA6
HW_OPT_10
E17
H16
AAD_DATA5
MHL_ON_OFF
GPIO15
AAD_DATA4
AAD_DATA3
J2
AAD_DATA2
J1
AAD_DATA1
K1
SC_FB_BUF
AAD_DATA0
STPI1_SOP/GPIO41
AUD_FS24CLK
STPI1_VAL/GPIO40
STPI1_ERR/GPIO55
AU19
C1
AT18
D2
AU18
B4
AU22
A3
AT21
B3
AU21
TP_DVB_SOP
TP_DVB_VAL
AUD_DAC1_SCK
TP_DVB_ERR
AUD_DAC1_LRCH
TP_DVB_DATA0
AUD_DAC0_LRCK
TP_DVB_DATA1
AUD_DAC0_SCK
TP_DVB_DATA2
AUD_DAC0_LRCH
TP_DVB_DATA3
AUD_ADC_LRCK
TP_DVB_DATA4
AUD_ADC_SCK
TP_DVB_DATA5
AUD_ADC_LRCH
TP_DVB_DATA6
AU25
B7
E8
AP23
D8
AR23
C8
AP22
E7
AR22
D7
AP21
C7
AR21
E6
AP20
D6
AR20
C6
AP19
E5
AR19
D5
AP18
C5
AR18
CLK_54M_VTT
R467 82
BB_SCL
1/16W 1%
TPI_CLK
BB_TPI_CLK
TPI_SOP
BB_TPI_ERR
TPI_VAL
BB_TPI_SOP
TPI_ERR
BB_TPI_VAL
TPI_DATA0
BB_TPI_DATA7
TPI_DATA1
BB_TPI_DATA6
TPI_DATA2
BB_TPI_DATA5
TPI_DATA3
BB_TPI_DATA4
TPI_DATA4
BB_TPI_DATA3
TPI_DATA5
BB_TPI_DATA2
TPI_DATA6
BB_TPI_DATA1
HSR_AM0
Placed as close as possible to IC4300
HSR_BP0
+3.3V_NORMAL
HSR_BM0
L407
HSR_CM0
OPT
C447
1uF
25V
1%
IC400
MM1756DURE
10K 1%
C412
0.1uF
4.7uF
1%
R421
5
2
4
3
GND
AR24
B9
AU27
A9
AT27
D9
AP24
4.7uF
AUAD_L_CH2_IN
10K 1%
C435
27K
4.7uF
R440
AR25
Close to LG1154A
B11 R492
330
A11 R407
330
TPIO_CLK/GPIO53
CLK_54M
TPIO_SOP/GPIO52
CVBS_GC2
TPIO_VAL/GPIO51
CVBS_GC1
TPIO_ERR/GPIO50
CVBS_GC0
TPIO_DATA0/GPIO58
CVBS_UP
TPIO_DATA1/GPIO59
TPIO_DATA2/GPIO60
AU29
AT29
DAC_START_PULLDOWN
AR27
E10
AP26
D10
AR26
C10
AP25
A10 R451
AT28
TPIO_DATA3/GPIO61
FS00CLK
TPIO_DATA4/GPIO62
H13A_AUDCLK_OUT
TPIO_DATA5/GPIO63
TPIO_DATA6/GPIO48
AP27
C11
DAC_START
C455
10uF
HSR_DP0
1%
R457
51K
HSR_DM0
HSR_EP0
DAC_DATA3
AUDCLK_OUT
AP29
DAC_DATA2
DACLRCH
DAC_DATA1
DACSLRCH/GPIO127
PCMI3SCK/GPIO112
DACSCK
E12
AR29
D12
AP28
C12
AR28
AAD_GC4
DACLRCK
AAD_GC3
PCMI3LRCK/GPIO113
AAD_GC2
PCMI3LRCH
AAD_GC1
DACCLFCH/GPIO126
AAD_GC0
IEC958OUT
DACSUBMCLK
AP35
E16
AR35
D16
AP34
C16
AR34
AP33
E15
D15
AR33
C15
AP32
E14
AR32
D14
AP31
AAD_DATA9
DACSUBLRCH
AAD_DATA8
DACSUBSCK
AAD_DATA7
DACSUBLRCK
AAD_DATA6
TEST1
AAD_DATA5
AAD_DATA4
AR31
E13
AP30
TX0N
AAD_DATA2
TX0P
AAD_DATA1
TX1N
AAD_DATA0
TX1P
TX2N
TX2P
AT36
AT30
ADCO_OUT_CLK
SCART_Rout_SOC
2.2uF
10V
SCART_FB_BUFFER
R401
SC_FB
470
B
AUDA_OUTL
0.01uF
C401
0.01uF
R6451
100
AUDA_OUTR
HP_ROUT_MAIN
Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
Only for training and service purposes
AU33
A16
AT34
B16
AU34
A17
AT35
B17
AU35
HSR_BP
TX5N
HSR_BM
TX5P
HSR_CP
TX6N
HSR_CM
TX6P
HSR_CLKP
TX7N
HSR_CLKM
TX7P
HSR_DP
TX8N
HSR_DM
TX8P
HSR_EP
TX9N
TX9P
TX10N
AUD_HPDRV_LRCH
TX10P
AUD_HPDRV_LRCK
TX11N
AUD_HPDRV_SCK
AU15
33
AN5
33
AR14
R400
33
AP14
TX11P
TX12N
FRC_LR_O_SYNC_FLAG
AP13
DPM
AF7
AD7
BPL_IN
L_VSOUT_LD
GST_SOC
DPM
AFE 3CH REF Setting
L406
OPT
MCLK_SOC
GCLK_SOC
TX13N
DIM0_MOSI
TX13P
DIM1_SCLK
TX14N
TX14P
TX15N
PWM0
TX15P
PWM1
TX16N
PWM2
TX16P
TX17N
TX17P
AP8
AR7
AN7
EPI_EO
TX18N
EPI_VST
TX18P
EPI_DPM
TX19N
EPI_MCLK
TX19P
EPI_GCLK
AN8
TX20N
TX20P
C438
TX21N
Placed as close as possible to IC4300
TX21P
TX22N
C444
Placed as close as possible to IC100
REFT
TX22P
0.1uF
HP_OUT
L400
BLM18PG121SN1D
HP_LOUT_AMP
TX23N
C446
0.1uF
HP_OUT
L401
BLM18PG121SN1D
HP_OUT
C407
0.22uF
10V
HP_LOUT
HP_ROUT_AMP
FE_DEMOD1_TS_ERROR
FE_DEMOD1_TS_DATA[0]
AN36
FE_DEMOD1_TS_DATA[1]
AN37
FE_DEMOD1_TS_DATA[2]
AN35
FE_DEMOD1_TS_DATA[3]
AP37
FE_DEMOD1_TS_DATA[4]
AP36
FE_DEMOD1_TS_DATA[5]
AR37
FE_DEMOD1_TS_DATA[6]
AR36
FE_DEMOD1_TS_DATA[7]
B29
B28
C28
B32
FE_DEMOD1_TS_DATA[0-7]
TPI_CLK
TPI_SOP
TPI_ERR
TP402
TPI_VAL
TPI_ERR
TPI_DATA[0-7]
TPI_DATA[0]
C31
TPI_DATA[1]
B31
TPI_DATA[2]
A31
TPI_DATA[3]
C30
TPI_DATA[4]
A30
TPI_DATA[5]
B30
TPI_DATA[6]
C29
TPI_DATA[7]
TPO_CLK
D31
TPO_SOP
F30
TPO_VAL
TPO_ERR
TP400
TPO_ERR
E31
E30
TPO_DATA[1]
E29
TPO_DATA[0-7]
TPO_DATA[0]
F29
TPO_DATA[2]
TPO_DATA[3]
F28
E28
TPO_DATA[4]
D28
TPO_DATA[5]
E27
TPO_DATA[6]
TPO_DATA[7]
D27
R495
100
AD6
R496
100
Y7
AC6
R497
R498
FRC_FLASH_WP
100
AC5
100
AUD_SCK
AUD_LRCK
AA6
C411
10pF
50V
OPT
AB7
AB5
AU14
SPDIF_OUT
AA32
AA34
AA33
AB34
AE32
33
33
+3.3V_NORMAL
R493
AE33
R494
AU6
AT5
TXB4N/TX0N
TXB4P/TX0P
TXB3N/TX1N
AU5
AT4
AU4
AU3
AU2
AT2
AT1
AR4
AR3
AP1
TXB3P/TX1P
TXBCLKN/TX2N
TXBCLKP/TX2P
TXB2N/TX3N
TXB2P/TX3P
TXB1N/TX4N
TXB1P/TX4P
TXB0N/TX5N
TXB0P/TX5P
TXA4N/TX6N
AP2
AP4
AP3
AN4
AN3
TXA4P/TX6P
TXA3N/TX7N
TXA3P/TX7P
TXACLKN/TX8N
TXACLKP/TX8P
AM4
AM3
AL4
AL3
AK1
AK2
AK4
AK3
AJ3
AH4
AH3
AG4
AG3
AF1
AF2
AF4
AF3
AE4
AE3
AD4
AD3
AC4
AC3
AB1
AB2
AB4
AB3
AA4
AA3
AR5
TX_LOCKN
REFB
AUD_MASTER_CLK
AUD_LRCH
Y6
TX23P
Must be used
C445
HP_OUT
C409
0.22uF
10V
FE_DEMOD1_TS_SYNC
FE_DEMOD1_TS_VAL
AM35
AJ4
DIM0_SCLK
PWM_IN
AE6
AL37
TX12P
DIM1_MOSI
AN14
PWM1
TXA2N/TX9N
TXA2P/TX9P
TXA1N/TX10N
TXA1P/TX10P
TXA0N/TX11N
H13 Ball Name
TXA0P/TX11P
EPI Output
TXB2N
TXD4N/TX12N
TXB2P
TXD4P/TX12P
TXB1N
TXD3N/TX13N
TXB1P
TXB0N
TXD3P/TX13P
TXB0P
TXDCLKP/TX14P
TXA4N
TXA4P
TXACLKN
TXD2N/TX15N
TXACLKP
TXD1P/TX16P
TXA1N
TXD0N/TX17N
TXA1P
TXD0P/TX17P
TXDCLKN/TX14N
TXD2P/TX15P
TXD1N/TX16N
TXC4N
TXC4P
TXC3N
TXC3P
TXCCLKN
TXCCLKP
TXC2N
TXC2P
TXC1N
TXC1P
TXC0N
TXC0P
EPI_LOCK6
0.1uF
HP_ROUT
DIMMING
Place at JACK SIDE
PWM_DIM2
R490
R489
100
LG1154A
100
PWM_DIM
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
B15
PWM2
SC_FB_BUF
MMBT3904(NXP)
Q400
E SCART_FB_BUFFER
AT33
TX4P
IF_P
Tuner IF Filter
1/16W
1%
R430
22K
C400
0.01uF
R445
22K
1/16W
5%
SCART_FB_BUFFER
1K R406
R6450
100
HP_LOUT_MAIN
A15
EO_SOC
ADC_I_INP
C
AU32
HSR_AM
AF6
0.01uF
51
SCART_FB_BUFFER
R446
4.7K
100K
R409
EU
C406
AT32
B14
R405
L/DIM0_MOSI
C437
51
NON_TU_W_BR/TW
C436
22pF
NON_TU_BR/TW
R444
100K
R408
EU
2.2uF
10V
AU31
A14
C456
4.7uF
10V
IF_N
+3.3V_NORMAL
SCART_Lout_SOC
EU
B13
TX4N
AP5
To ADC
EU
AT31
R402
L/DIM0_VS
L/DIM0_SCLK
10K 1%
ADC_I_INN
C403
TX3P
AC7
TU_W_BR/TW TU_W_BR/TW TU_W_BR/TW
R444-*1
R443-*1
C436-*1
100pF
220
220
SCART_Lout
AU30
A13
AT15
1%
R458
47K
TX3N
HSR_AP
HSR_EM
B12
FE_DEMOD1_TS_CLK
AL35
AT6
AAD_DATA3
AAD_DATAEN
C14
NC
AUAD_M_REF
FE_DEMOD3_TS_DATA
AL36
TEST2
AT14
EU
FE_DEMOD3_TS_ERROR
AG36
AD5
AR30
HSR_EM0
C448 OPT
4.7uF
10V
NON_TU_BR/TW
R443
HSR_CLKM0
FE_DEMOD3_TS_VAL
AG35
TPIO_DATA7/GPIO49
DAC_DATA4
DAC_DATA0
330
C13
AUAD_R_REF
AUAD_R_CH2_IN
+12V
HSR_CLKP0
FE_DEMOD3_TS_SYNC
AH36
D30
CVBS_DN
E9
BIAS
C413
C434
R439
1%
COMP1/AV1/DVI_R_IN
EU
DTV/MNT_V_OUT
27K
AUAD_L_REF
DTV/MNT_V_OUT_SOC
OUT
R420
1
10K 1%
PS
COMP1/AV1/DVI_L_IN
6
IN
4.7uF
R438
VCC
AUAD_R_CH3_IN
OPT
R454
2
C433
27K
EU
1%
R419
SC_R_IN
1%
R455
51K
47K R456 1%
R437
AUAD_L_CH3_IN
EU
1/10W
5%
4.7uF
C414
0.1uF
SC_L_IN
C432
27K
4.7uF C449
AUAD_REF_PO
R418
HSR_CP0
FE_DEMOD3_TS_CLK
AH37
TPI_DATA7
AU28
C9
A12
HSR_AP0
FE_DEMOD2_TS_DATA
AH35
A28
BB_SDA
BB_TPI_DATA0
ADCO_OUT_CLK
+2.5V_Normal
FE_DEMOD2_TS_ERROR
AJ36
TP_DVB_DATA7
AT25
B18
10K
FE_DEMOD2_TS_VAL
AJ35
AM36
TP_DVB_CLK
AUD_DAC1_LRCK
R6006
EU
AUDIO IN
100K
R403
EU
C2
AAD_DATAEN
SCART_AMP_L_FB
100K
R404
EU
AT19
C17
EU
1uF 25V 10K
R6005
C6001
SCART_Rout
AU20
B1
AAD_GC0
SCART_AMP_R_FB
25V 1uF
C6006
B2
D13
HW_OPT_0
F2
STPI1_CLK/GPIO42
AUD_FS23CLK
AUD_HDMI_MCLK
D11
DAC_START
IF_AGC
U17
AUD_FS21CLK
AT20
CVBS_DN
AUAD_L_REF
R3
STPI0_DATA/GPIO43
AU36
B10
CLK_F54M
V3
U1
AUD_FS20CLK
FE_DEMOD2_TS_SYNC
AK37
STPI1_DATA/GPIO54
BB_TP_DATA0
AUAD_R_CH2_IN
V2
F3
0.047uF
SC_ID_SOC
COMP2_Y_IN_SOC_SOY
AUAD_R_CH3_IN
U2
ADC_I_INN
68 C441
68 C442
AUAD_L_CH3_IN
T1
U16
BUF_OUT1
U14
68 C440
R449
COMP2_PB_IN_SOC
COMP2_Y_IN_SOC
0.047uF
C429
50V 10pF
C470
U15
V6
REFB
R2
BB_TP_DATA3
IFAGC
U7
R448
0.047uF
R1
0
REFT
COMP1_Pb
C430
RFAGC
CVBS_VCM
C439
100pF
50V
OPT
COMP1_PR_IN_SOC
ANTCON
CVBS_IN1
Placed as close as possible to SOC
R428
50V 10pF
BB_TP_DATA7
K17
CVBS_IN2
V15
0.047uF V13
DTV/MNT_V_OUT_SOC
COMP1_Y_IN_SOC_SOY
EU
EU
1% 75
R412
R414 1% 75
EU
R416 1% 75
OPT 50V 10pF
C473
OPT 50V 10pF
C474
C472
1000pF
0.047uF
CVBS_IN3
BB_TP_SOP
AUDA_OUTR
N3
AUAD_REF_PO
V14
C443
R450 68
COMP1_PB_IN_SOC
COMP1_Y_IN_SOC
0.047uF
C428
OPT 50V 10pF
AUAD_R_REF
BB_TP_ERR
AUDA_OUTL
N2
STPI0_ERR/GPIO44
FE_DEMOD2_TS_CLK
AK36
I2S_I/F
33 C417
33 C418
R427
D406
AUAD_R_CH1_IN
U13
TU_CVBS_SOC
D403
AUAD_L_CH1_IN
H13A_SDA
SC_CVBS_IN_SOC
5.5V
AUAD_R_CH2_IN
H13A_SCL
AUAD_L_REF
R425
D401
OPM1
B8
AUAD_M_REF
SC_G
SC_CVBS_IN_SOY
5.5V
AUAD_L_CH2_IN
A8
H13A_SDA
R424
5.5V
AUAD_R_CH3_IN
OPM0
K2
AV1_CVBS_IN_SOC
EU
AUAD_L_CH3_IN
K3
H13A_SCL
NON_EU
R436-*1
0
SC_B
COMP1_Pr
PORES_N
OPM[1]
SC_ID_SOC
75
SC_R
2.2uF
EU R426
22K
E3
OPM[0]
SC_FB_SOC
AUAD_R_CH4_IN
BB_TP_CLK
BB_TP_VAL
N1
AUD_SCART_OUTR
AUAD_L_CH4_IN
SCART_FB_DIRECT
R423
100
0
C453
TUNER_SIF
C457
1000pF
OPT
P3
SC_FB
NON_EU
R422-*1
AUD_SCART_OUTL
XTAL_SEL1
SOC_RESET
R435
0.1uF
10uF
TU_CVBS_SOC
C402
150pF
50V
OPT
SC_ID
AUDA_OUTR
XTAL_SEL0
M17
XTAL_SEL[1]
0.047uF
AUDA_OUTL
CLK_24M
M18
XTAL_SEL[0]
100
XTAL_BYPASS
D18
SC_CVBS_IN_SOY
R432
TU_CVBS
AUDA_VBG_EXT
N18
EU
EU
0.1uF
C451
C452
P2
SC_CVBS_IN_SOC
C408
150pF
50V
EU
C450
H17
AAD_ADC_SIFM
0.01uF
P17
XIN_SUB
XOUT_SUB
BB_SDA
EU
R410
75
1%
SC_CVBS_IN
C4
A7
BB_SCL
0.01uF
C410
150pF
STPI0_VAL/GPIO45
AUD_FS25CLK
AT22
A4
AUD_ADC_LRCH
AV1_CVBS_IN_SOC
C405
150pF
50V
5.5V
D404
AU23
A2
AUD_DAC1_LRCK
AUD_DAC0_LRCH
R434
AT23
B5
C18
OPM[1]
AUD_DAC0_SCK
L408 1uH
A5
AUD_HDMI_MCLK
OPM[0]
100
100
AUD_DAC0_LRCK
Place SOC Side
AU24
STPI0_SOP/GPIO46
AT24
B6
STPI0_CLK/GPIO47
INTR_AFE3CH
AUDCLK_OUT_SUB
FOR EMI
Place JACK Side
AK35
INTR_GBB
INTR_AGPIO
INTR_AGPIO
LG1154D
PWM1
PWM2
BSD-NC4_H004-HD
2012-11-13
MAIN AUDIO/VIDEO
LGE Internal Use Only
IC100
LG1154D_H13D
F15
M0_DDR_A[0]
M0_DDR_A[1]
M0_DDR_A[2]
M0_DDR_A[3]
M0_DDR_A[4]
M0_DDR_A[5]
M0_DDR_A[6]
M0_DDR_A[7]
M0_DDR_A[8]
M0_DDR_A[9]
M0_DDR_A[10]
M0_DDR_A[11]
M0_DDR_A[12]
M0_DDR_A[13]
M0_DDR_A[14]
M0_DDR_A0
F13
M0_DDR_A1
F17
M0_DDR_A2
F19
M0_DDR_A3
E10
M0_DDR_A4
E18
M0_DDR_A5
E11
M0_DDR_A6
F18
DDR_SAMSUNG
IC500
K4B4G1646B-HCK0
M0_DDR_A7
F11
M0_DDR_A8
F16
M0_DDR_A9
E9
VDDC15_M0
M0_DDR_CKE
M0_DDR_A10
E12
N2
P8
M0_DDR_A12
E16
F14
R541
R520
M0_DDR_A13
M0_DDR_A14
F12
M0_DDR_A0
10K
10K
M0_DDR_A1
M0_DDR_A2
M0_DDR_RESET_N
M0_DDR_A15
M0_DDR_A3
E19
M0_DDR_BA[1]
M0_DDR_BA0
E15
M0_DDR_A4
M0_DDR_BA1
F10
M0_DDR_A5
M0_DDR_A6
M0_U_CLK
M0_D_CLK
M0_DDR_BA2
M0_DDR_BA[2]
M0_DDR_U_CLKN
M0_DDR_D_CLK
M0_DDR_D_CLKN
M0_U_CLK
A10
M0_U_CLKN
A19
100
R535
B10
100
R519
M0_DDR_A7
M0_DDR_U_CLK
M0_D_CLK
M0_D_CLKN
B19
E14
M0_DDR_A8
M0_DDR_A9
M0_DDR_A10
M0_U_CLKN
M0_D_CLKN
M0_DDR_A11
M0_DDR_A12
M0_DDR_CKE
M0_DDR_CKE
M0_DDR_A13
F21
M0_DDR_ODT
M0_DDR_RASN
M0_DDR_CASN
M0_DDR_ODT
E20
M0_DDR_A14
M0_DDR_RASN
E21
M0_DDR_A15
M0_DDR_CASN
F20
M0_DDR_BA0
M0_DDR_WEN
M0_DDR_WEN
M0_DDR_BA1
E17
F9
M0_DDR_ZQCAL
VDDC15_M0
M0_DDR_RESET_N
M0_DDR_RESET_N
R500
240
M0_DDR_BA2
VDDC15_M0
M0_1_DDR_VREFCA
M0_DDR_VREFCA
1%
M0_DDR_DQ[10]
M0_DDR_DQ[11]
M0_DDR_DQ[12]
M0_DDR_DQ[13]
M0_DDR_DQ[14]
M0_DDR_DQ[15]
M0_DDR_DQ[16]
M0_DDR_DQ[17]
M0_DDR_DQ[18]
M0_DDR_DQ[19]
M0_DDR_DQ[20]
M0_DDR_DQ[21]
M0_DDR_DQ[22]
M0_DDR_DQ[23]
M0_DDR_DQ[24]
M0_DDR_DQ[25]
M0_DDR_DQ[26]
M0_DDR_DQ[27]
M0_DDR_DQ[28]
M0_DDR_DQ[29]
M0_DDR_DQ[30]
R536
1K 1%
0.1uF
1%
R537
1K
C512
M0_DDR_DQS1
M0_DDR_DQ0
C15
M0_DDR_DQS_N1
M0_DDR_DQ1
C23
VDDC15_M0
M0_DDR_DQ2
D16
VDDC15_M0
M0_DDR_DM0
M0_DDR_DQ3
B24
M0_DDR_DQ4
B15
M0_DDR_DQ5
D23
M0_DDR_DQ6
A15
M0_DDR_DQ7
C16
M0_1_DDR_VREFDQ
M0_DDR_VREFDQ
M0_DDR_DM1
M0_DDR_DQ0
M0_DDR_DQ1
M0_DDR_DQ8
M0_DDR_DQ9
D21
D17
M0_DDR_DQ2
M0_DDR_DQ3
M0_DDR_DQ10
C22
M0_DDR_DQ11
C18
M0_DDR_DQ12
C21
M0_DDR_DQ13
C17
0.1uF
M0_DDR_DQ[8]
M0_DDR_DQ[9]
N2
P8
P2
R8
R2
T8
R3
A1
R7
N7
T3
T7
M7
M3
A2
H1
A3
VREFDQ
J3
K3
L3
M0_DDR_DQ4
M0_DDR_DQ5
M0_DDR_DQ6
M0_DDR_DQ7
M0_DDR_DQ14
D20
M0_DDR_DQ15
C14
A5
M0_DDR_DQ14
M0_DDR_DQ22
D6
M0_DDR_DQ13
M0_DDR_DQ21
D14
M0_DDR_DQ12
M0_DDR_DQ20
C6
M0_DDR_DQ11
M0_DDR_DQ19
D13
M0_DDR_DQ10
M0_DDR_DQ18
D7
M0_DDR_DQ8
M0_DDR_DQ16
M0_DDR_DQ17
C13
VDD_1
VDD_2
VDD_3
VDD_4
A13
VDD_5
A14
VDD_6
VDD_7
BA0
J3
VDDC15_M0
A5
L8
A6
K3
L3
R542
VDD_8
VDDQ_2
VDDQ_3
VDDQ_4
CS
VDDQ_6
VDDQ_5
VDDQ_7
ODT
RAS
VDDQ_8
CAS
NC_1
NC_2
A10/AP
VDD_2
A11
VDD_3
A12/BC
VDD_4
A13
VDD_5
A14
VDD_6
VDD_7
VDD_8
BA0
D2
M0_DDR_A3
E9
F1
H2
H9
M0_DDR_A4
J9
M0_DDR_A5
L1
L9
DQSL
M0_DDR_A6
A9
C7
B7
B2
VDD_1
M0_DDR_A2
DQSL
VSS_1
DQSU
VSS_2
VSS_3
E7
A9
A8
C1
C9
NC_4
F3
DQSU
A8
M0_DDR_A1
J1
RESET
G3
R9
VDDQ_9
T2
240
1%
M0_DDR_A0
N9
R1
A1
VDDQ_1
CK
CK
NC_3
A7
K8
N1
VDD_9
WE
ZQ
D9
G7
K2
BA1
CKE
A4
D3
VSS_4
DML
DMU
VSS_5
DQL0
VSS_7
VSS_6
E3
D9
F7
F2
F8
H3
G7
H8
G2
H7
K2
VSS_8
DQL1
DQL2
VSS_9
DQL3
VSS_10
DQL4
VSS_11
DQL5
K8
N1
A2
C2
A7
B8
M0_DDR_A8
M9
M0_DDR_A9
P1
P9
T1
T9
M0_DDR_A10
B1
VSSQ_1
DQU0
VSSQ_2
DQU1
VSSQ_3
VSSQ_4
DQU2
DQU3
VSSQ_5
DQU4
VSSQ_6
VSSQ_7
DQU5
DQU6
VSSQ_8
DQU7
A3
J2
J8
M1
VSS_12
D7
C3
M0_DDR_A7
DQL6
DQL7
C8
B3
E1
G8
M0_DDR_A11
B9
D1
D8
M0_DDR_A12
E2
E8
F9
G1
M0_DDR_A13
VSSQ_9
G9
N9
M0_DDR_A14
R1
M0_DDR_A15
M0_DDR_BA0
BA1
M0_DDR_BA1
A1
VDDQ_1
CK
VDDQ_2
CK
VDDQ_3
VDDQ_4
VDDQ_5
CS
VDDQ_6
ODT
VDDQ_7
RAS
VDDQ_8
CAS
M0_DDR_BA2
C1
M0_U_CLK
C9
M0_U_CLKN
D2
M0_DDR_CKE
NC_2
H2
C534
0.1uF
M0_DDR_ODT
H9
C535
0.1uF
M0_DDR_RASN
M0_DDR_WEN
L1
M0_DDR_RESET_N
M0_DDR_DQ15
M0_DDR_DQ9
DQSU
VSS_1
DQSU
VSS_2
VSS_3
DML
VSS_4
DMU
VSS_5
VSS_6
E3
F2
F8
H3
H8
G2
H7
DQL0
VSS_7
DQL1
VSS_8
DQL2
VSS_9
DQL3
VSS_10
DQL4
VSS_11
DQL5
A7
A2
B8
A3
M0_DDR_DQS_N3
J2
M0_DDR_DM2
J8
M0_DDR_DM3
M8
N2
H1
A3
P8
A0
A3
M3
A6
A10/AP
R8
R2
A13
A14
L8
R3
BA0
VDD_2
VDD_3
A12/BC
T3
VDD_4
A13
T7
VDD_5
VDD_6
A14
M7
A15
VDD_7
VDD_8
M2
BA0
N8
N1
N9
R1
R9
A1
VDDQ_1
CK
VDDQ_2
CK
VDDQ_3
VDDQ_4
VDDQ_5
CS
VDDQ_6
ODT
VDDQ_7
RAS
VDDQ_8
CAS
A8
C1
C9
D2
E9
F1
H2
VDDQ_9
WE
T2
RESET
H9
J1
NC_1
NC_2
NC_3
J9
L1
L9
NC_4
F3
B2
VDD_1
A11
N7
D9
G7
K2
K8
VDD_9
BA1
DQSL
DQSL
A10/AP
R7
K3
L3
G3
A9
L7
K1
J3
240
1%
A8
VDD_5
VDD_6
VDD_7
VDD_8
L2
R544
ZQ
A7
T8
VDD_2
VDD_3
VDD_4
CKE
K9
VDDC15_M0
A6
B2
VDD_1
A11
A12/BC
J7
K7
A5
L8
ZQ
A7
A8
A9
BA2
A4
P2
H1
VREFDQ
A4
A5
M2
N8
VREFDQ
VREFCA
A1
A2
A15
C7
D9
E7
B7
A9
DQSU
VSS_1
DQSU
D3
VSS_2
DML
VSS_4
VSS_3
DMU
VSS_5
DQL0
VSS_7
VSS_6
E3
G7
F7
F2
F8
K2
H3
K8
H7
H8
G2
DQL1
DQL2
VSS_8
VSS_9
DQL3
VSS_10
DQL4
VSS_11
DQL5
C8
C2
A7
N9
A2
B8
DQU0
VSSQ_2
DQU1
VSSQ_3
DQU2
VSSQ_4
DQU3
VSSQ_5
DQU4
VSSQ_6
DQU5
VSSQ_7
DQU6
VSSQ_8
DQU7
A3
J2
J8
M1
M9
P1
P9
T1
T9
B1
VSSQ_1
D7
C3
N1
B3
E1
G8
VSS_12
DQL6
DQL7
B9
D1
D8
E2
E8
F9
G1
VSSQ_9
G9
R1
R9
VDD_9
BA1
M3
BA2
A1
VDDQ_1
J7
CK
VDDQ_3
CKE
K9
VDDQ_2
CK
K7
VDDQ_4
VDDQ_5
CS
L3
VDDQ_8
CAS
K3
VDDQ_7
RAS
J3
VDDQ_6
ODT
K1
A8
C1
C9
D2
E9
VDDQ_9
WE
F1
H2
C566
0.1uF
H9
C567
0.1uF
J1
NC_1
T2
RESET
NC_2
J9
L1
L9
NC_4
F3
DQSL
G3
DQSL
M9
M0_DDR_DQ16
P1
M0_DDR_DQ17
P9
M0_DDR_DQ18
T1
M0_DDR_DQ19
T9
M0_DDR_DQ20
M0_DDR_DQ22
B1
VSSQ_1
DQU0
VSSQ_2
DQU1
VSSQ_3
DQU2
VSSQ_4
DQU3
VSSQ_5
DQU4
VSSQ_6
DQU5
VSSQ_7
DQU6
VSSQ_8
C7
A9
DQSU
VSS_1
DQSU
B7
VSS_2
VSS_3
E7
DML
DMU
D3
VSS_4
VSS_5
M1
M0_DDR_DQ23
VSS_6
E3
DQL0
G2
VSS_11
DQL5
H8
VSS_10
DQL4
H3
VSS_9
DQL3
F8
VSS_8
DQL2
F2
VSS_7
DQL1
F7
VSSQ_9
D1
M0_DDR_DQ24
D8
M0_DDR_DQ25
E2
M0_DDR_DQ26
E8
M0_DDR_DQ27
F9
M0_DDR_DQ28
G1
M0_DDR_DQ29
G9
M0_DDR_DQ30
M0_DDR_DQ31
B3
E1
G8
J2
J8
M1
VSS_12
M9
P1
P9
T1
T9
DQL6
H7
DQL7
B1
B9
M0_DDR_DQ23
C7
M7
G8
M0_DDR_DQ21
DQU7
C2
M0_DDR_DQS3
E1
DQL6
D7
C8
B3
VSS_12
DQL7
C3
L7
R7
N7
A9
E7
F7
R2
T8
R3
T3
NC_3
M0_DDR_DQS2
C7
P8
P2
T7
L9
DQSL
P3
N2
R8
M8
VREFCA
A2
J9
DQSL
D3
P3
NC_4
F3
B7
A1
L2
F1
J1
RESET
P7
E9
M0_DDR_CASN
NC_1
A0
A8
VDDQ_9
T2
N3
DDR3
4Gbit
(x16)
R9
VDD_9
WE
G3
A9
A10/AP
A11
A12/BC
L2
K1
H5TQ4G63AFR-PBC
N3
P7
M0_1_DDR_VREFDQ
B2
J7
K7
K9
DDR_HYNIX
IC502-*1
M0_1_DDR_VREFCA
L8
ZQ
BA2
CKE
K1
H1
VREFDQ
A6
A7
A8
M2
N8
J7
K9
VREFCA
A2
A3
A4
A5
A15
M7
BA2
K7
T3
T7
M3
M2
N8
L7
R7
N7
VREFCA
A15
L7
M0_DDR_VREFDQ
M8
DDR_SAMSUNG
IC502
K4B4G1646B-HCK0
M8
A0
A1
M0_DDR_DQS_N2
R538
M0_DDR_DQ[7]
M0_DDR_DQS_N0
M0_DDR_DM3
1K 1%
M0_DDR_DQ[6]
P3
A0
R8
R2
T8
R3
NC_3
1%
M0_DDR_DQ[5]
M0_DDR_CASN
M0_DDR_DQS0
R539
M0_DDR_DQ[4]
M0_DDR_RASN
M0_DDR_RESET_N
M0_DDR_DM2
C11
1K
M0_DDR_DQ[3]
M0_DDR_ODT
M0_DDR_WEN
C513
M0_DDR_DQ[2]
P7
L2
M0_DDR_DM1
D9
D22
M0_DDR_DQ[1]
N3
DDR3
4Gbit
(x16)
M0_DDR_DM0
C20
M0_DDR_DM[3]
M0_DDR_DQ[0]
1K 1%
M0_DDR_DQS_N3
0.1uF
M0_DDR_DM[2]
R514
M0_DDR_DQS3
D10
D18
M0_DDR_DM[1]
R515
M0_DDR_DQS_N2
C10
1K
M0_DDR_DQS2
C504
A11
B11
1%
M0_DDR_DQS_N1
M0_DDR_DQS_N[3]
M0_DDR_DM[0]
0.1uF
D19
R516
M0_DDR_DQS[3]
M0_DDR_CKE
M0_DDR_DQS1
1K 1%
M0_DDR_DQS_N[2]
C19
1%
M0_DDR_DQS[2]
M0_DDR_DQS_N0
R517
M0_DDR_DQS_N[1]
A20
1K
M0_DDR_DQS[1]
M0_DDR_DQS0
C505
M0_DDR_DQS_N[0]
M0_D_CLK
M0_D_CLKN
B20
M0_DDR_DQS[0]
N3
P7
P3
P2
M0_DDR_A11
E13
M0_DDR_A[15]
M0_DDR_BA[0]
DDR_HYNIX
IC500-*1
H5TQ4G63AFR-PBC
M0_DDR_VREFCA
VSSQ_1
D7
DQU0
VSSQ_8
DQU7
A3
VSSQ_7
DQU6
B8
VSSQ_6
DQU5
A2
VSSQ_5
DQU4
A7
VSSQ_4
DQU3
C2
VSSQ_3
DQU2
C8
VSSQ_2
DQU1
C3
B9
VSSQ_9
D1
D8
E2
E8
F9
G1
G9
M0_DDR_DQ24
D12
M0_DDR_DQ25
D8
M0_DDR_DQ26
B13
M0_DDR_DQ27
C9
M0_DDR_DQ28
C12
M0_DDR_DQ29
C8
M0_DDR_DQ30
D11
M0_DDR_DQ31
M0_DDR_DQ[31]
Real USE : 1Gbit
H5TQ1G63DFR-PBC(x16)
IC100
LG1154D_H13D
1Gbit : T7(NC_6)
N6
M6
M1_DDR_A14
P6
M1_DDR_BA0
V6
M1_DDR_BA1
M1_D_CLK
F2
M1_D_CLKN
N5
VDDC15_M1
1%
M1_DDR_DQS_N[2]
M1_DDR_DQS[3]
E1
F3
F4
P1
P2
R3
R4
M1_DDR_DQS_N[3]
G4
M1_DDR_DM[0]
M1_DDR_DM[1]
M1_DDR_DM[2]
E3
T4
P3
M1_DDR_DM[3]
C4
M1_DDR_DQ[0]
M1_DDR_DQ[1]
M1_DDR_DQ[2]
M1_DDR_DQ[3]
M1_DDR_DQ[4]
M1_DDR_DQ[5]
M1_DDR_DQ[6]
M1_DDR_DQ[7]
M1_DDR_DQ[8]
M1_DDR_DQ[9]
M1_DDR_DQ[10]
M1_DDR_DQ[11]
M1_DDR_DQ[12]
M1_DDR_DQ[13]
M1_DDR_DQ[14]
M1_DDR_DQ[15]
M1_DDR_DQ[16]
M1_DDR_DQ[17]
M1_DDR_DQ[18]
M1_DDR_DQ[19]
M1_DDR_DQ[20]
M1_DDR_DQ[21]
M1_DDR_DQ[22]
M1_DDR_DQ[23]
M1_DDR_DQ[24]
M1_DDR_DQ[25]
M1_DDR_DQ[26]
M1_DDR_DQ[27]
M1_DDR_DQ[28]
M1_DDR_DQ[29]
M1_DDR_DQ[30]
M1_DDR_DQ[31]
K3
B3
J4
A3
K2
B4
K1
J3
D4
H4
C3
G3
D3
H3
E4
M3
V4
M4
W3
L4
W4
L3
Y2
V3
N4
U4
M2
T3
N3
U3
P4
0.1uF
1%
M1_DDR_RASN
M1_DDR_CASN
M1_DDR_WEN
M1_DDR_RESET_N
P8
P2
R8
R2
T8
R3
A2
A3
R7
N7
T3
T7
M7
M3
R531
M1_DDR_DQS0
M1_DDR_DQS_N1
M1_DDR_DQS_N0
M1_DDR_DQS2
M1_DDR_DQS_N2
M1_DDR_DQS1
M1_DDR_DQS3
M1_DDR_DQS_N1
M1_DDR_DQS_N3
VDDC15_M1
VDDC15_M1
M1_DDR_DM0
M1_DDR_DM0
M1_DDR_DM1
M1_1_DDR_VREFDQ
M1_DDR_VREFDQ
M1_DDR_DM2
M1_DDR_DQ0
M1_DDR_DQ2
M1_DDR_DQ4
M1_DDR_DQ5
M1_DDR_DQ6
M1_DDR_DM1
M1_DDR_DQ0
M1_DDR_DQ1
M1_DDR_DQ2
M1_DDR_DQ3
M1_DDR_DQ1
M1_DDR_DQ3
R7
N7
T3
T7
H1
H5TQ4G63AFR-PBC
J3
K3
L3
M1_DDR_DQ7
M1_DDR_DQ8
M1_DDR_DQ9
M1_DDR_DQ10
M1_DDR_DQ11
M1_DDR_DQ12
M1_DDR_DQ13
M1_DDR_DQ14
M1_DDR_DQ4
M1_DDR_DQ5
M1_DDR_DQ6
M1_DDR_DQ7
M1_DDR_DQ8
M1_DDR_DQ9
M1_DDR_DQ10
M1_DDR_DQ11
M1_DDR_DQ12
M1_DDR_DQ13
M1_DDR_DQ14
M1_DDR_DQ15
N8
A10/AP
A11
VDD_2
VDD_3
A12/BC
VDD_4
VDD_5
A14
VDD_6
VDD_7
VDD_8
BA0
ZQ
K1
J3
K3
VDDC15_M1
A7
L3
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
CS
VDDQ_6
ODT
VDDQ_7
RAS
VDDQ_8
CAS
B2
A10/AP
VDD_2
A11
VDD_3
A12/BC
VDD_4
A13
VDD_5
A14
VDD_6
VDD_7
VDD_8
BA0
G3
NC_2
B7
K2
K8
N1
N9
R1
R9
BA1
A1
VDDQ_1
VDDQ_2
CK
VDDQ_3
VDDQ_4
VDDQ_5
CS
VDDQ_6
ODT
VDDQ_7
RAS
CAS
VDDQ_8
WE
RESET
C9
D2
E9
F1
H2
C529
0.1uF
H9
C530
0.1uF
J1
NC_1
T2
A8
C1
VDDQ_9
NC_2
J9
L1
L9
NC_4
F3
E9
H9
VSS_2
DML
VSS_4
VSS_3
DMU
F2
F8
H3
H8
G2
H7
VSS_5
VSS_6
E3
F7
DQL0
VSS_7
DQL1
VSS_8
DQL2
VSS_9
DQL3
VSS_10
DQL4
VSS_11
DQL5
J9
L1
C2
A7
A2
B8
A3
M1_DDR_A7
M1_DDR_A8
B3
M1_DDR_A9
E1
G8
J2
J8
M1_DDR_A10
M1
M9
P1
M1_DDR_A11
P9
VSS_12
T1
T9
M1_DDR_A12
B1
VSSQ_1
D7
C3
M1_DDR_A6
M1_DDR_A13
DQL6
DQL7
C8
M1_DDR_A5
L9
A9
VSS_1
DQSU
G7
M1_DDR_A4
F1
H2
DQSL
E7
D3
VDD_9
CK
A8
C1
DQSL
C7
D9
M1_DDR_A3
C9
D2
NC_4
DQSU
M1_DDR_A2
J1
NC_1
NC_3
VDD_1
N1
N9
R1
R9
VDDQ_9
WE
RESET
M1_DDR_A1
A1
VDDQ_1
CK
F3
A9
G7
K2
K8
VDD_9
CK
T2
A8
D9
BA1
L2
240
P8
M1_DDR_A0
B2
VDD_1
CKE
R543
N2
L8
ZQ
A13
J7
L8
P7
P3
H1
VREFDQ
A7
DQU0
VSSQ_2
DQU1
VSSQ_3
DQU2
VSSQ_4
DQU3
VSSQ_5
DQU4
VSSQ_6
DQU5
VSSQ_7
DQU6
VSSQ_8
DQU7
B9
D1
D8
E2
M1_DDR_A14
E8
F9
G1
M1_DDR_A15
M1_DDR_BA0
M1_DDR_BA1
M1_DDR_BA2
M1_U_CLK
M1_U_CLKN
M1_DDR_CKE
M1_DDR_ODT
M1_DDR_RASN
M1_DDR_CASN
M1_DDR_WEN
M1_DDR_RESET_N
A9
DQSU
VSS_1
VSS_2
DML
VSS_4
DMU
VSS_5
VSS_3
D3
VSS_6
E3
F7
F2
F8
H3
H8
G2
DQL0
VSS_7
DQL1
VSS_8
DQL2
VSS_9
DQL3
VSS_10
DQL4
VSS_11
DQL5
B3
M1_DDR_DQS3
E1
M1_DDR_DQS_N3
G8
J2
M1_DDR_DM2
J8
M1_DDR_DM3
M1
VSS_12
M9
M1_DDR_DQ16
P1
M1_DDR_DQ17
P9
M1_DDR_DQ18
T1
M1_DDR_DQ19
T9
M1_DDR_DQ20
M1_DDR_DQ21
DQL6
M1_DDR_DQ22
DQL7
H7
M1_DDR_DQ23
D7
C3
C8
C2
A7
A2
B8
A3
B1
VSSQ_1
DQU0
VSSQ_2
DQU1
VSSQ_3
DQU2
VSSQ_4
DQU3
VSSQ_5
DQU4
VSSQ_6
DQU5
VSSQ_7
DQU6
VSSQ_8
DQU7
VSSQ_9
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
A1
A2
A3
DDR3
4Gbit
(x16)
M8
M3
R7
N7
T3
T7
M7
H1
J3
K3
L3
B9
D1
M1_DDR_DQ24
D8
M1_DDR_DQ25
E2
M1_DDR_DQ26
E8
M1_DDR_DQ27
F9
M1_DDR_DQ28
G1
M1_DDR_DQ29
G9
M1_DDR_DQ30
M1_DDR_DQ31
VREFCA
H1
VREFDQ
L8
ZQ
A7
A8
A9
A10/AP
A11
B2
VDD_1
VDD_2
VDD_3
A12/BC
VDD_4
VDD_5
A14
VDD_6
VDD_7
VDD_8
BA0
VDDQ_2
A6
VDDQ_3
VDDQ_4
VDDQ_5
L2
L8
R545
ZQ
K1
240
J3
K3
L3
CS
VDDQ_6
ODT
VDDQ_7
RAS
VDDQ_8
CAS
G3
VDD_1
A10/AP
VDD_2
A11
VDD_3
A12/BC
VDD_4
VDD_5
A14
VDD_6
VDD_7
VDD_8
BA0
B7
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
CS
VDDQ_6
ODT
VDDQ_7
RAS
VDDQ_8
CAS
RESET
NC_2
K2
K8
N1
N9
R1
R9
A8
C1
C9
D2
E9
F1
H2
C561
0.1uF
H9
C562
0.1uF
J9
L1
L9
NC_4
F3
VSS_2
VSS_4
VSS_3
DMU
G7
J1
NC_1
T2
VSS_1
DML
E7
D3
VDDQ_9
J9
L1
L9
A9
DQSU
DQSU
D9
A1
VDDQ_1
H9
DQSL
DQSL
BA1
CK
E9
F1
H2
NC_4
C7
VDD_9
CK
NC_2
NC_3
B2
A9
A13
RESET
F3
A8
A8
C1
C9
D2
J1
NC_1
T2
VDDC15_M1
N1
N9
R1
R9
VDDQ_9
WE
A7
G7
K2
K8
A1
VDDQ_1
CK
CK
CKE
A5
D9
VDD_9
BA1
J7
K7
WE
G3
N8
M3
K9
CKE
K1
A3
A4
A5
A6
A15
A4
J7
K9
A0
A1
A2
A13
M2
VREFDQ
BA2
K7
R2
T8
R3
BA2
M2
N8
P2
R8
L7
A15
M7
M1_1_DDR_VREFDQ
VREFCA
NC_3
M1_DDR_DQS2
E7
P3
A0
L2
M1_DDR_DQS_N2
DQSU
B7
P7
G9
DQSL
C7
N3
VSSQ_9
DQSL
G3
M8
N3
VREFCA
A8
A9
A15
K9
CKE
K1
A3
A4
A5
A6
BA2
A5
A6
A0
A1
A2
M2
K7
J7
K9
M7
VREFDQ
BA2
K7
R2
T8
R3
A4
M2
N8
P8
P2
R8
L7
A15
L7
N2
M1_DDR_VREFDQ
VREFCA
NC_3
M1_DDR_DQS1
M1_DDR_DM3
M8
M3
M1_DDR_DQS_N0
0.1uF
M1_DDR_DQS[2]
R512
M1_DDR_DQS[1]
M1_DDR_DQS_N[1]
R513
M1_DDR_DQS_N[0]
M1_DDR_DQS0
R532
R501
240
1K
M1_DDR_RESET_N
N2
A1
L2
M1_DDR_ODT
R533
K5
1K 1%
M1_DDR_WEN
M1_DDR_RESET_N
M1_D_CLK
M1_D_CLKN
M1_DDR_CKE
C508
M1_DDR_CASN
H6
E2
M1_1_DDR_VREFCA
1K 1%
G5
P3
A0
VDDC15_M1
M1_DDR_VREFCA
M1_DDR_ODT
M1_DDR_RASN
M1_DDR_WEN
M1_DDR_DQS[0]
M1_DDR_BA2
M1_DDR_CKE
F5
F6
M1_DDR_BA0
M1_U_CLKN
F1
M1_DDR_ZQCAL
M1_DDR_A14
M1_DDR_A15
1%
M1_DDR_CASN
M1_U_CLKN
M1_U_CLK
R1
G6
M1_DDR_ODT
M1_D_CLKN
M1_DDR_BA2
M1_DDR_CKE
M1_DDR_RASN
M1_DDR_A12
R534
M1_DDR_D_CLKN
M1_DDR_A11
1K
M1_DDR_D_CLK
M1_DDR_A10
M1_DDR_A13
M1_DDR_BA1
M5
M1_DDR_A9
M1_U_CLK
M1_D_CLK
M1_DDR_A15
R2
M1_DDR_U_CLKN
M1_DDR_A8
M1_DDR_A13
T6
M1_DDR_BA[2]
M1_DDR_U_CLK
M1_DDR_A7
M1_DDR_A12
L5
H5
M1_DDR_BA[1]
M1_DDR_A6
M1_DDR_RESET_N
M1_DDR_A11
P5
M1_DDR_A4
M1_DDR_A5
M1_DDR_A10
R5
M1_DDR_A3
10K
M1_DDR_A9
V5
10K
R521
M1_DDR_A8
M1_DDR_A2
P7
DDR3
4Gbit
(x16)
DDR3 1.5V bypass Cap - Place these caps near Memory
U6
M1_DDR_A[15]
M1_DDR_BA[0]
R540
M1_DDR_A7
N3
DDR3 1.5V bypass Cap - Place these caps near Memory
K6
C509
M1_DDR_A[14]
M1_DDR_A1
100
R530
M1_DDR_A[13]
M1_DDR_A0
M1_DDR_A6
100
R518
M1_DDR_A[12]
T5
0.1uF
M1_DDR_A[11]
M1_DDR_CKE
M1_DDR_A5
0.1uF
M1_DDR_A[10]
J5
VDDC15_M1
R510
M1_DDR_A[9]
P3
M1_DDR_A4
1K 1%
M1_DDR_A[8]
DDR_HYNIX
IC503-*1
M1_1_DDR_VREFCA
M8
N3
P7
M1_DDR_A3
U5
1%
M1_DDR_A[7]
J6
R511
M1_DDR_A[6]
H5TQ4G63AFR-PBC
1K
M1_DDR_A[5]
DDR_SAMSUNG
IC503
K4B4G1646B-HCK0
4Gbit : T7(A14)
DDR_HYNIX
IC501-*1
M1_DDR_VREFCA
M1_DDR_A2
C500
M1_DDR_A[4]
L6
1K 1%
M1_DDR_A[3]
M1_DDR_A1
1%
M1_DDR_A[2]
DDR_SAMSUNG
IC501
K4B4G1646B-HCK0
M1_DDR_A0
R6
1K
M1_DDR_A[1]
C501
M1_DDR_A[0]
F2
F8
H3
H8
G2
H7
VSS_5
VSS_6
E3
F7
DQL0
VSS_7
DQL1
VSS_8
DQL2
VSS_9
DQL3
VSS_10
DQL4
VSS_11
DQL5
C2
A7
A2
B8
A3
J8
M1
M9
P1
P9
T1
T9
B1
VSSQ_1
D7
C3
C8
B3
E1
G8
J2
VSS_12
DQL6
DQL7
DQU0
VSSQ_2
DQU1
VSSQ_3
DQU2
VSSQ_4
DQU3
VSSQ_5
DQU4
VSSQ_6
DQU5
VSSQ_7
DQU6
VSSQ_8
DQU7
B9
D1
D8
E2
E8
F9
G1
VSSQ_9
G9
DQSL
DQSL
C7
A9
DQSU
VSS_1
DQSU
B7
VSS_2
VSS_3
E7
DML
VSS_4
DMU
D3
VSS_5
VSS_6
E3
F7
F2
F8
H3
H8
G2
H7
DQL0
VSS_7
DQL1
VSS_8
DQL2
VSS_9
DQL3
VSS_10
DQL4
VSS_11
DQL5
C2
A7
A2
B8
A3
G8
J2
J8
M1
M9
P1
P9
T1
T9
DQL6
B1
VSSQ_1
D7
C8
E1
VSS_12
DQL7
C3
B3
DQU0
VSSQ_2
DQU1
VSSQ_3
DQU2
VSSQ_4
DQU3
VSSQ_5
DQU4
VSSQ_6
DQU5
VSSQ_7
DQU6
VSSQ_8
DQU7
B9
VSSQ_9
D1
D8
E2
E8
F9
G1
G9
M1_DDR_DQ15
M1_DDR_DQ16
M1_DDR_DQ17
M1_DDR_DQ18
M1_DDR_DQ19
M1_DDR_DQ20
M1_DDR_DQ21
M1_DDR_DQ22
M1_DDR_DQ23
M1_DDR_DQ24
M1_DDR_DQ25
M1_DDR_DQ26
M1_DDR_DQ27
M1_DDR_DQ28
M1_DDR_DQ29
M1_DDR_DQ30
M1_DDR_DQ31
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
Only for training and service purposes
BSD-NC4_H005-HD
2012-09-14
MAIN DDR
LGE Internal Use Only
+5V_CI_ON
R711
10K
OPT
R712
10K
OPT
CI_DATA[0-7]
CI
JK700
10120698-015LF
R720
10K
OPT
/PCM_CE1
35
+5V_CI_ON
R716
/CI_CD1
CI_TS_DATA[3]
1
36
2
CI_DATA[3]
37
100
CI
3
CI_DATA[4]
CI_DATA[5]
CI_TS_DATA[4]
R706
10K
OPT
R708
10K
OPT
38
4
CI_TS_DATA[5]
39
5
CI_DATA[6]
CI_TS_DATA[6]
CI_TS_DATA[7]
40
6
CI_DATA[7]
CI R721
41
7
+5V_CI_ON
CI_ADDR[10]
42
8
43
9
44
10
CI_ADDR[11]
45
11
CI_ADDR[9]
46
12
CI_IN_TS_DATA[0]
47
13
CI_IN_TS_DATA[1]
48
14
CI_IN_TS_DATA[2]
49
15
CI_IN_TS_DATA[3]
50
16
51
17
52
18
/PCM_CE2
CI_VS1
/PCM_IORD
/PCM_IOWR
R710
0
OPT
CI_IN_TS_DATA[0-7]
R715
+5V_CI_ON
CI_IN_TS_DATA[4]
0
OPT
/PCM_WAIT
PCM_INPACK
R701
R702
C706
0
R718
0.1uF
CI
55
21
56
22
57
23
58
24
59
25
60
26
61
27
62
28
63
29
64
30
65
CI_DATA[1]
66
32
67
33
68
34
R714
/PCM_REG
0 CI
CI_TS_VAL
CI_TS_SYNC
CI_TS_DATA[0]
CI_TS_DATA[1]
PCM_INPACK
EB_DATA[2]
EB_DATA[3]
CI_DATA[3]
R723
10K
CI
CI_ADDR[13]
CI_ADDR[14]
R725
10K
OPT
CI_DATA[4]
EB_DATA[4]
CI_DATA[5]
EB_DATA[6]
CI_DATA[7]
/PCM_IRQA
EB_DATA[5]
CI_DATA[6]
/PCM_WE
33
OPT
33
CI
AR713
EB_DATA[7]
EB_DATA[0-7]
CI_DATA[0]
31
33 OPT
CI_VS1
C707
0.1uF
16V
EB_DATA[0]
EB_DATA[1]
CI_DATA[2]
33
20
CI_IN_TS_DATA[7]
R707
10K
OPT
CI
CI
AR712
CI_DATA[1]
OPT
19
54
33 CI
33 CI
R700
CI_ADDR[8]
CI_ADDR[13]
R722
+5V_CI_ON
CI_DATA[0]
CI_ADDR[9]
CI_ADDR[14]
53
CI_TS_CLK
PCM_RESET
CI_ADDR[11]
CI_ADDR[8]
CI_IN_TS_DATA[6]
R709
10K
CI
CI_ADDR[10]
/PCM_OE
CI_IN_TS_DATA[5]
R704
10K
OPT
R724
10K
OPT
33
EB_DATA[0-7]
C703
4.7uF
10V
CI
CI_DATA[0-7]
C702
0.1uF
CI
CI_TS_DATA[2]
/CI_CD2
R717 CI 100
/PCM_CE2
R713
0
G2
69
CI_DATA[0-7]
CI_ADDR[12]
CI_ADDR[7]
CI_ADDR[6]
CI_ADDR[5]
CI_ADDR[3]
CI_ADDR[2]
CI_ADDR[0]
CI_ADDR[7]
CI_ADDR[5]
CI_ADDR[4]
CI_ADDR[1]
CI_ADDR[12]
CI_ADDR[6]
CI_ADDR[4]
CI_ADDR[3]
CI_ADDR[2]
CI_ADDR[1]
CI_ADDR[0]
+5V_CI_ON
CI_DATA[2]
R719
10K
OPT
G1
OPT
CI_IN_TS_VAL
CI_IN_TS_CLK
CI_IN_TS_SYNC
C705
12pF
50V
OPT
TPO_DATA[0-7]
CI
AR701
TPO_DATA[0]
33
CI_IN_TS_DATA[0]
TPO_DATA[1]
CI_IN_TS_DATA[1]
TPO_DATA[2]
CI_IN_TS_DATA[2]
TPO_DATA[3]
CI_IN_TS_DATA[3]
TPO_DATA[4]
CI_IN_TS_DATA[4]
TPO_DATA[5]
CI_IN_TS_DATA[5]
TPO_DATA[6]
CI_IN_TS_DATA[6]
TPO_DATA[7]
CI_IN_TS_DATA[7]
AR706 CI
33
33
TPO_CLK
CI
AR705
33
CI
AR707
33
CI
AR711
EB_ADDR[12]
EB_ADDR[0]
CI_ADDR[12]
CI_ADDR[1]
EB_ADDR[1]
CI_ADDR[13]
EB_ADDR[13]
CI_ADDR[2]
EB_ADDR[2]
EB_ADDR[14]
CI_ADDR[3]
EB_ADDR[3]
CI_ADDR[14]
/PCM_REG
CI_ADDR[0]
CI_IN_TS_CLK
TPO_SOP
CI_IN_TS_SYNC
CI_IN_TS_VAL
TPO_VAL
CI_ADDR[4]
33
CAM_REG_N
CI
AR708
EB_ADDR[4]
CI_ADDR[5]
EB_ADDR[5]
/PCM_OE
CI_ADDR[6]
EB_ADDR[6]
/PCM_WE
CI_ADDR[7]
EB_ADDR[7]
/PCM_IORD
/PCM_IOWR
33
CI
AR710
EB_OE_N
EB_WE_N
EB_BE_N1
EB_BE_N0
+5V_NORMAL
CI_ADDR[8]
CI_ADDR[9]
33
CI
AR709
EB_ADDR[8]
EB_ADDR[9]
/PCM_WAIT
EB_ADDR[11]
CAM_WAIT_N
CAM_IREQ_N
/PCM_IRQA
/CI_CD2
/CI_CD1
EB_ADDR[10]
CI_ADDR[11]
AR702
10K
10K
R705
R703
CI_ADDR[10]
100
CAM_CD2_N
CAM_CD1_N
CI
C700
0.1uF
16V
CI
C701
0.1uF
16V
AR703 CI
PCM_INPACK
CAM_INPACK_N
TPI_CLK
CI_TS_CLK
CI_TS_VAL
100
CI_TS_SYNC
TPI_VAL
TPI_SOP
C704
12pF
50V
OPT
AR704 CI
CI_TS_DATA[7]
CI_TS_DATA[6]
TPI_DATA[7]
TPI_DATA[6]
CI_TS_DATA[5]
TPI_DATA[5]
CI_TS_DATA[4]
100
TPI_DATA[4]
AR700 CI
CI_TS_DATA[3]
TPI_DATA[3]
TPI_DATA[2]
CI_TS_DATA[2]
CI_TS_DATA[1]
CI_TS_DATA[0]
100
TPI_DATA[1]
TPI_DATA[0]
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
Only for training and service purposes
BSD-NC4_H007-HD
2012-10-20
PCMCIA
LGE Internal Use Only
+12V
L2313
UBW2012-121F
6
PDIM#2
GND
8
10
12
GND
12V
13
14
12V
12V
15
16
17
18
+24V
C2316
0.1uF
50V
24V
GND
L2303
C2306
0.1uF
50V
S
24V
11
PANEL_20V
PWM_DIM2 L2306
UBW2012-121F
GND
9
GND
UBW2012-121F
7
24V
+12V
5
INV_CTL
C2333
10uF
16V
R2346
5.6K
4
PDIM#1
3.5V
C2307
0.1uF
16V
R2309
100
INV ON
G
C
GND
B
PANEL_CTL
3
2
POWER_DET
RESET
1
C2355
0.1uF
16V
GND
C2365
0.1uF
16V
C2347
0.1uF
50V
R2336
100K
PANEL_20V
not to RESET at 8kV ESD
Q2301
MMBT3904(NXP)
R2314
10K
R2338
10K
OPT
IC2307
PD_+12V
R2326
1.2K
1%
LVDS_DISCHARGE
2
LVDS_DISCHARGE
R2347
5.6K
PWR ON 1
3.5V
3
+3.5V_ST
NCP803SN293
VCC
R2317
33K
L2304
UBW2012-121F
R2337
100K
PD_+3.5V
R2330
0
5%
Q2302
AO3407A
R2310
1K
D
P2300
SMAW200-H18S1
+3.5V_ST
PD_+12V
R2325
2.7K
1%
PANEL_VCC
C2331
0.1uF
50V
+3.3V_NORMAL
R2318
5.6K
1
MMBT3906(NXP)
+12V
3
+3.5V_ST
Power_DET
PANEL_POWER
Q2300
R2300
10K
2
RL_ON
10K
R2301
+3.5V_ST
IC2308
NCP803SN293
R2327
5.6K
1%
E
19
VCC
2
OLED : 20V DET = POWER_ON/OFF2_4
POWER_ON/OFF2_4
R2348
0
RESET
1
C2356
0.1uF
16V
R2328
1.3K
1%
3
GND
24V-- & gt; 3.48V
20V-- & gt; 3.51V
12V-- & gt; 3.58V
ST_3.5V-- & gt; 3.5V
PWM_DIM
L/DIM0_MOSI
L/DIM0_MOSI
JP2308
L/DIM0_VS
JP2309
L/DIM0_VS
L/DIM0_SCLK
JP2310
+2.5V
L/DIM0_SCLK
DDR MAIN 1.5V
+2.5V_Normal
IC2302
AP7173-SPG-13 HF(DIODES)
ZD2304
5V
[EP]
0.1uF
16V
PH_1
VSENSE
8A
R2316
8
COMP
C2313
4.7uF
16V
+3.3V_NORMAL
C2315
4700pF
+3.3V_NORMAL
1K
+12V
NC_2
+24V
POWER_ON/OFF2_2
FB
L2314
OLED
L2311
BOOT
PGOOD
EN
9
6
7
SW_1
SS/TR
8
RT/SYNC
AGND
5
C2309
10uF
35V
4
6
5A
5
VIN
C2330
22uF
10V
C2334
22uF
10V
C2336
10uF
10V
C2338
0.1uF
50V
GND
EN
POWER_ON/OFF1
C2311
0.1uF
50V
R2345
10K
1%
BLM18PG121SN1D
Vout=0.6*(1+R1/R2)
3
7
BLM18PG121SN1D
NON_OLED
Vout(1.24V)=0.6*(1+16k/15k)
L2305
2
SS/TR
50V
1/16W
1%
R2305
15K
R2
4
SW_2
L2310
4.7uH
40V
9
L2312
4.7uH
SW
D2300
B540C
10
6
7
10
DCDC_RT
[EP]GND
8
1
9
5
NC_1
VIN
IC2304
RT8289GSP
THERMAL
R1
3
SW_3
R2
51K
R2344
C2335
0.1uF
16V
R1
1%
C2302
180pF
50V
EN
R2343
16K
GND
PVIN_2
C2324
0.01uF
50V
BOOT
ZD2302
2.5V
C2303
10uF
16V
SW
Vout=0.765*(1+R1/R2)
+12V
C2323
22uF
10V
BOOT
R2
Switching freq: 700K
C2341
22uF
10V
OPT
5
C2322
22uF
10V
PH_1
50V
6
4
11
C2321
3
4
22000pF
SS
7
PVIN_1
11
+5V_NORMAL
L2308
1uH
0.1uF
16V
PH_2
1/16W
5%
C2312
3300pF
50V
2
12
R2315 0
FB
PVCC
3
[EP]GND
VIN
12
C2318
BOOT
50V
1%
C2319
22uF
10V
8
1
13
C2320
C2310
1uF
10V
33K
C2317
22uF
10V
13
14
IC2305-*1
RT8079AGQW
+5.0V normal & USB
PWRGD
47pF
3A
R2306
GND
5
GND_2
15
THERMAL
17
2
+1.1V_VDD
15
ZD2300
2.5V
IC2300-*1
RT7266ZSP
2
14
1.3K
6
4
GND_2
+1.1V_VDD
DCDC_RT
EN
SS
GND_1
1
[EP]GND
R2313
3
NR5040T2R2N
L2307
2.2uH
SW
GND_1
1
THERMAL
VBST
7
RT/CLK
1/16W
1%
L2301
1/16W
1%
C2308
100pF
50V
DCDC_TI
2
16V
0.1uF
C2314
R2303
16K
VREG5
R2307
120K
9
11K
9
VFB
R2302
ZD2303
2.5V
OPT
VIN_2
IC2303
TPS54821RHL
+12V
THERMAL
R1
VIN
8
THERMAL
1%
OPT
TPS54327DDAR [EP]GND
1
16
VIN_1
3A $ 0.145
Vout=0.827*(1+R1/R2)=1.521V
DCDC_TI IC2300
EN
R2
R2340
56K
1/16W
1%
+1.0V_VDD
BLM18PG121SN1D
POWER_ON/OFF2_3
50V
+1.23V_CORE
L2300
DCDC_TI
C2364
100pF
50V
C2360
4700pF
5%
LG1154A
+1.0V_VDD
R2304
10K
R1
R2335
1/16W 330K 5%
R2334
15K
C2301
10uF
16V
C2362
22uF
10V
0.01uF
50V
1/16W
+12V
C2361
22uF
10V
VIN_3
C2359
SS/TR
COMP
AGND
5
3A
NR5040T3R3N
[EP]GND
2
GND_2
Vout=0.8*(1+R1/R2)
THERMAL
17
FB
11
PH_2
3 IC2305 DCDC_TI10
TPS54319TRE
4
9
L2320
3.3uH
PH_3
GND_1
C2350
10uF
10V
BOOT
12
1
VIN_2
R2339
C2300
22uF
10V
16V
47K 1%
VIN_1
C2305
0.1uF
16V
+1.5V_DDR
C2358
0.1uF
13
L2318
R2321
2K
1% R2
14
C2337
2200pF
50V
GND
7
5
C2348
0.1uF
16V
8
4
C2346
10uF
10V
COMP
1.5A
OPT
C2343
22uF
10V
RT/CLK
R2322
R1
4.3K
1%
SS
EN
6
PWRGD
+3.5V_ST
VIN_3
EN
C2354
FB
15
R2312
10K
POWER_ON/OFF2_1
L2302
BLM18PG121SN1D
C2327
10uF
10V
3
POWER_ON/OFF2_2
6
VCC
LG1154D
VSENSE
+5V_NORMAL
3.3V_EMMC
7
OUT
EP[GND]
+3.3V_NORMAL
2
8
16
PG
1
9
IN
THERMAL
eMMC POWER
10K
R2331
+3.3V_NORMAL
C2329
150pF
50V
C2304
10uF
16V
POWER_ON/OFF1
1%
R1
VFB
VREG5
C2325
100pF
50V
3
7
6
VIN
VBST
SW
16V
0.1uF
C2332
L2309
3.6uH
SM-8040
SS
R2319
15K
1%
Switching freq: 700K
2
R2308
51K
OPT
8
1
9
EN
THERMAL
R2311
10K
ZD2301
5V
IC2301
TPS54327DDAR [EP]GND
C2326
1uF
10V
4
3A
5
GND
C2339
22uF
10V
C2340
22uF
10V
Vout=1.222*(1+R1/R2)
POWER UP SEQUENCE
5V/3.3V- & gt; 2.5V- & gt; 1.5V/1.1V- & gt; 1.0V
LG1154D
: 3.3V- & gt; 2.5V- & gt; 1.5V- & gt; 1.1V
LG1154AN : 3.3V- & gt; 2.5V- & gt; 1.0V
C2328
3300pF
50V
R2
Vout=0.765*(1+R1/R2)
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
Only for training and service purposes
BSD-NC4_H039-HD
NC4_H13
POWER_BLOCK(OLED)
2013.03.05
23
LGE Internal Use Only
Renesas MICOM
For Debug
For CEC
+3.5V_ST
4.7M
OPT
MHL_DET
MICOM_RESET_SW
SW3000
JTP-1127WEM
2
1
4
270K
OPT
P124/XT2/EXCLKS
41
P120/ANI19
P123/XT1
42
37
P137/INTP0
43
P41/TI07/TO07
P122/X2/EXCLK
44
C3001
+3.5V_ST
P40/TOOL0
P121/X1
45
C3000
0.1uF
C3004
0.1uF
16V
38
REGC
46
Commercial
RESET
VSS
47
0.47uF
VDD
48
Ready For
+3.5V_ST
39
10K
GND
R3030
10K
MHL_DET
R3031
Q3001-*1
SI1012CR-T1-GE3
HDMI_CEC_FET_VISHAY
R3032
S
D
5
R3028
MICOM_RESET_22OHM
R3029
22
MICOM_RESET
HDMI_WAUP:HDMI_INIT
MICOM_DEBUG
32.768KHz
Q3001
RUE003N02
HDMI_CEC_FET_ROHM
LOGO_LIGHT
HDMI_CEC
S
G
3
4
8pF
X3000
BAT54_SUZHO
MICOM_DEBUG
LOGO_LIGHT
40
2
D
CEC_REMOTE
1
C3003
G
D3000
MICOM_RESET
8pF
R3034
120K
R3033
27K
Don’t remove R3014,
not making float P40
C3002
+3.5V_ST
R3016 1K
P3000
12507WS-04L
R3014 10K
MICOM_DEBUG
MICOM_DEBUG
+3.5V_ST
3
ST_BY_DET_CAM
ST_BY_DET_CAM
MICOM_RESET_33OHM
R3029-*1 33
R3021
10K
GP4 High/MID Power SEQUENCE
P60/SCLA0
1
36
P140/PCLBUZ0/INTP6
P61/SDAA0
2
35
P00/TI00/TXD1
P62
3
34
P01/TO00/RXD1
33
P130
IC3000
32
P20/ANI0/AVREFP
R5F100GEAFB
31
P21/ANI1/AVREFM
30
P22/ANI2
29
P23/ANI3
I2C_SDA_MICOM
EDID_WP
SCART_MUTE
P63
4
P31/TI03/TO03/INTP4
5
P75/KR5/INTP9/SCK01/SCL01
POWER_ON/OFF2_1
6
PANEL_CTL
WOL/WIFI_POWER_ON
IR
POWER_ON/OFF2_2
P74/KR4/INTP8/SI01/SDA01
HDMI_CEC
7
MICOM_LEAD_Au
KEY2
KEY1
MODEL1_OPT_1
8
P72/KR2/SO21
9
28
P24/ANI4
10
27
P25/ANI5
P70/KR0/SCK21/SCL21
11
26
P26/ANI6
P30/INTP3/RTC1HZ/SCK11/SCL11
12
25
P27/ANI7
POWER_ON/OFF2_2
POWER_ON/OFF2_3
P71/KR1/SI21/SDA21
EYE_SDA
POWER_ON/OFF2_4
EYE_SCL
CAM_PWR_ON_CMD
CAM_PWR_ON_CMD
POWER_ON/OFF2_4
POWER_ON/OFF2_1
P73/KR3/SO01
POWER_ON/OFF2_3
SCART_MUTE
POWER_ON/OFF2_4
EDID_WP
RL_ON
I2C_SCL_MICOM
POWER_ON/OFF!
MODEL1_OPT_4
MODEL1_OPT_0
SIDE_HP_MUTE
MODEL1_OPT_3
MODEL1_OPT_2
REGC
P121/X1
P122/X2/EXCLK
P137/INTP0
P123/XT1
P124/XT2/EXCLKS
RESET
P40/TOOL0
P41/TI07/TO07
P120/ANI19
46
45
44
43
42
41
40
39
38
37
P147/ANI18
24
23
22
P146
P13/TXD2/SO20
21
20
19
18
17
16
15
14
13
P60/SCLA0
Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
Only for training and service purposes
P130
P31/TI03/TO03/INTP4
5
IC3000-*1
33
32
P20/ANI0/AVREFP
6
R5F100GEAFB#30
31
P21/ANI1/AVREFM
7
30
P22/ANI2
8
29
P23/ANI3
9
28
P24/ANI4
10
27
P25/ANI5
11
26
P26/ANI6
P30/INTP3/RTC1HZ/SCK11/SCL11
12
25
P27/ANI7
NetCast4.0
MICOM (RENESAS)
24
P147/ANI18
23
22
P146
P10/SCK00/SCL00
21
P11/SI00/RXD0/TOOLRXD/SDA00
20
P12/SO00/TXD0/TOOLTXD
19
P13/TXD2/SO20
18
P14/RXD2/SI20/SDA20
17
16
15
P17/TI02/TO02
P16/TI01/TO01/INTP5
13
MICOM_LEAD_Cu
P50/INTP1/SI11/SDA11
CAM_CTL
4
P74/KR4/INTP8/SI01/SDA01
CAM_CTL
MODEL1_OPT_5
AMP_MUTE
SOC_RX
SOC_TX
INV_CTL
P01/TO00/RXD1
P63
P70/KR0/SCK21/SCL21
SOC_RESET
P00/TI00/TXD1
34
P71/KR1/SI21/SDA21
WOL_CTL
P140/PCLBUZ0/INTP6
35
3
P72/KR2/SO21
LED_R
36
2
P62
P73/KR3/SO01
LED_R
POWER_DET
POWER_ON/OFF1
WOL/ETH_POWER_ON
MICOM_NON_LOGO_LIGHT
R3012
10K
MICOM_TACT_KEY
R3008
10K
MICOM_LCD/OLED
R3005
10K
MICOM_GP3_12/15PIN
R3004
10K
MICOM_M13
R3001
10K
MICOM_NON_GED
R3000
10K
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
1
P61/SDAA0
P75/KR5/INTP9/SCK01/SCL01
MODEL1_OPT_4
MODEL1_OPT_5
P15/PCLBUZ1/SCK20/SCL20
EYE_Q
GED
MODEL1_OPT_3
14
NON_GED
MODEL1_OPT_2
VSS
MODEL_OPT_5
R3036
3.3K
Ready for sample set
H13
VDD
IR_wafer(10pin)
M13
47
IR_wafer(12/15)
MODEL_OPT_4
48
Need to Assign ADC port
P51/INTP2/SO11
PDP
P10/SCK00/SCL00
LCD / OLED
P12/SO00/TXD0/TOOLTXD
MODEL_OPT_2
P14/RXD2/SI20/SDA20
For LOGO LIGHT
Ready for sample set
P15/PCLBUZ1/SCK20/SCL20
LOGO
TOUCH_KEY
P11/SI00/RXD0/TOOLRXD/SDA00
MODEL1_OPT_0
NON LOGO
TACT_KEY
MODEL_OPT_3
MODEL1_OPT_1
MODEL_OPT_0
MODEL_OPT_1
P16/TI01/TO01/INTP5
1
P17/TI02/TO02
MICOM_OLED_FRC
R3007-*2
22K
MICOM_OLED_MAIN
R3007-*1
56K
MICOM_LOGO_LIGHT
R3013
10K
MICOM_TOUCH_KEY
R3010
10K
MICOM_PDP
R3007
10K
MICOM_H13
R3003
10K
MICOM_NC4_8PIN
R3006
10K
MICOM_GED
R3002
10K
0
P51/INTP2/SO11
MICOM MODEL OPTION
+3.5V_ST
P50/INTP1/SI11/SDA11
MICOM MODEL OPTION
R3035
3.3K
+3.5V_ST
EYE_Q
SOC_RESET
2013.02.05
30
LGE Internal Use Only
CK_GND
D3215
RCLAMP0524PA
1
10
CK+
2
CK-
12
8
D0+_HDMI1
5
3
D1-_HDMI1
2
D2_GND
2
9
3
TMDS_CH1+
D1+_HDMI1
GND_1
8
4
D2+
1
TMDS_CH1-
7
TMDS_CH2-
TMDS_CH2+
1
8
4
7
5
6
NC_3
5
9
8
4
7
5
6
ARC
TX2P
TX2N
TX1P
TX1N
TX0P
TX0N
TXCP
TXCN
TCVDD12
TPVDD12
R0XCN
R0XCP
R0X0N
R0X0P
R0X1N
R0X1P
R0X2N
R0X2P
VDD33_2
[EP]GND
VDD12_3
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
44
CBUS_HPD4
42
41
43
DSCL4
DSDA4
R3PWR5V
40
CBUS_HPD3
39
38
DSDA3
DSCL3
37
R1PWR5V
36
35
DSCL1
CBUS_HPD1
34
DSDA1
32
33
R0PWR5V
31
DSCL0
29
30
DSDA0
28
R4X2P
VDD12_2
26
25
23
24
27
R4X2N
NC_3
GND_2
NC_2
NC_1
TMDS_CH1+
GND_1
TMDS_CH2-
9
3
10
2
9
3
8
4
7
5
6
NC_4
NC_3
GND_2
NC_2
NC_1
8
4
TMDS_CH2+
1
7
D1+_HDMI4
D2_GND
5
D2+
1
1/16W
5%
D2+_HDMI4
6
C
B
MHL_DET
Q3200
D3207
JK3203
C
C3223
0.047uF
25V
HDMI_ESD_SEMTEK
51U019S-312HFN-E-R-B-LG
HDMI1
HDMI S/W OUTPUT
B
6
D2+_HDMI1
E MMBT3906(NXP)
Q3201
R3247
10K
R3243
1K
D2-_HDMI4
NC_1
51U019S-312HFN-E-R-B-LG
R4PWR5V
D3214-*1
IP4283CZ10-TBA
D1-_HDMI4
2
2
HDMI_ESD_SEMTEK
45
+3.5V_ST
D2-_HDMI1
JK3202
DSDA5[VGA]
22
HDMI_ESD_NXP
TMDS_CH1-
GND_2
NC_2
DSCL5[VGA]
46
NC_4
10
3
NC_4
9
3
47
D0+_HDMI4
D3214
RCLAMP0524PA
1
10
D2-
3
10
2
6
D1+
HDMI_ESD_NXP
D3211-*1
IP4283CZ10-TBA
5
TMDS_CH2+
HDMI_ESD_SEMTEK
4
D3211
RCLAMP0524PA
1
10
D2-
D0-_HDMI4
D1_GND
5
D1+
4
GND_1
TMDS_CH2-
D1-
6
HDMI_ESD_SEMTEK
R5PWR5V[VGA]
20
21
HDMI4 With MHL
MMBT3904(NXP) E
HDMI_RX2+
7
D1_GND
48
D0+
NC_1
6
7
2
HDMI_RX1+
5
8
4
1
HDMI_RX2-
7
3
TMDS_CH1+
HDMI_RX1-
D1-
6
6
4
TMDS_CH2+
NC_2
SBVCC5
19
HDMI_ESD_NXP
TMDS_CH1-
CK+_HDMI4
D0_GND
PWRMUX_OUT
49
R4XCP
HDMI_RX0+
5
8
3
TMDS_CH2-
D0-_HDMI1
D0+
7
7
GND_2
50
D3215-*1
IP4283CZ10-TBA
CK-_HDMI4
9
D0-
9
LPSBV
17
R4XCN
HDMI_RX0-
4
NC_3
9
2
GND_1
D0_GND
8
8
NC_4
10
1
TMDS_CH1+
51
18
A2
HDMI_CLK-
3
TMDS_CH1-
WKUP
16
AVDD12_2
MHL_DET
HDMI_CLK+
CK+_HDMI1
11
10
CD_SENSE0
52
R3X2P
CK+_HDMI1
9
D3210-*1
IP4283CZ10-TBA
53
VDD33_1
C
10K
R3245
CK-_HDMI1
2
D0-
9
HDMI_ESD_NXP
CK-_HDMI1
CD_SENSE1
14
15
R3X1P
D0-_HDMI1
CK+
54
R3X1N
A1
13
CBUS_HPD0
13
D3210
RCLAMP0524PA
1
10
GPIO2
R3X0N
R4X1N
CE_REMOTE
CD_SENSE3
55
R4X0N
14
56
VA3211
ESD_HDMI
VA3210
ESD_HDMI
CEC_REMOTE
CD-SENSE4
11
12
R4X1P
DDC_SCL_4
NC
EAG62611204
11
10
22
15
CEC_REMOTE
CK_GND
DDC_SDA_4
R3223
GPIO0
57
R3X2N
22
R3222
DDC_CLK
CK-
12
EAG62611204
16
OPT
C3226
0.1uF
16V
CE_REMOTE
13
DDC_DATA
4
3
GPIO1
58
R3X0P
5%
1/16W
EN
TPWR
59
R3XCP
D0+_HDMI1
VA3213
ESD_HDMI
ARC
14
OPT
R3249
3.9K
15
10V
OC
10
RESET_N
60
R3XCN
D1-_HDMI1
DDC_CLK
SPDIF_OUT_ARC
VA3216
ESD_HDMI
2
VDD12_1
D1+_HDMI1
16
17
C3202
1uF
DDC_DATA
GND
VA3212
ESD_HDMI
GND
CSDA
61
IC3201-*1
SII9587CNUC-3
CSCL
62
9
INT
63
8
AVDD12_1
SPDIF_IN
64
7
RSVDL
65
6
R1X2P
D2-_HDMI1
17
18
C3205
10uF
10V
C3208
0.1uF
66
THERMAL
89
4
5
R1X2N
1/16W
5%
D2+_HDMI1
GND
5V
HDMI_HPD_4
3
R1X0P
R1X1N
D3204
VA3206
ESD_HDMI
ARC
30V
5%
1/16W
VA3207
ESD_HDMI
OPT
R3248
1K
5V
19
1
2
R1X0N
R1X1P
5
MHL_ON_OFF
R3246
10K
DDC_SCL_1
HDMI_FREEPORT HP_DET
R3253
33
1
UD
R1XCN
R3254
100
IN
220K
R3206
20
HDMI_FREEPORT HP_DET
OUT
R3215
100K
22
5.6V
20
18
D3206
MBR230LSFT1G
DDC_SDA_1
R3208
19
5V_HDMI_4
GND
22
84
OPT
R1XCP
R3207
BODY_SHIELD
85
IC3202
TPS2051BDBVR
86
5V_HDMI_4
BODY_SHIELD
88
+5V_NORMAL
VA3215
ESD_HDMI
VA3208
ESD_HDMI
87
HDMI_HPD_1
R4X0P
33
AVDD12_3
5V_HDMI_1
R3250
HDMI1 With ARC
+5V_NORMAL
5V_HDMI_1
+5V_NORMAL
SDA
DDC/CEC_GND
8
7
6
5
4
3
2
1
9
3
8
D0_GND
4
TMDS_CH1+
6
TMDS_CH2-
D0-_HDMI3
TMDS_CH2+
1
10
2
NC_4
9
3
6
TMDS_DATA2+
TMDS_DATA2_SHIELD
TMDS_DATA2-
D0+_HDMI3
TMDS_DATA1+
HDMI_ESD_SEMTEK
TMDS_DATA1TMDS_DATA0+
TMDS_DATA0_SHIELD
TMDS_DATA0-
D1+
D2-
D3208
RCLAMP0524PA
1
10
2
3
D2_GND
D2+
TMDS_CLK+
TMDS_CLK_SHIELD
D3208-*1
IP4283CZ10-TBA
CEC
9
D1+_HDMI3
8
TMDS_CH1-
TMDS_CH1+
GND_1
4
7
5
TMDS_CLK-
HDMI_ESD_NXP
D1-_HDMI3
6
TMDS_CH2-
D2-_HDMI3
D2+_HDMI3
HDMI_ESD_SEMTEK
TMDS_CH2+
TMDS_DATA2+
2
TMDS_DATA2_SHIELD
3
TMDS_DATA2-
NC_1
D1D1_GND
1
NC_2
TMDS_DATA1_SHIELD
D0+
1
10
2
9
3
8
4
7
5
6
NC_4
NC_3
GND_2
NC_2
NC_1
RESERVED
SCL
SDA
DDC/CEC_GND
VDD[+5V]
HOT_PLUG_DETECT
4
TMDS_DATA1+
5
TMDS_DATA1_SHIELD
TMDS_DATA1-
6
7
TMDS_DATA0+
8
TMDS_DATA0_SHIELD
9
TMDS_DATA0-
10
TMDS_CLK+
11
TMDS_CLK_SHIELD
12
TMDS_CLK-
13
CEC
14
RESERVED
15
SCL
16
SDA
17
DDC/CEC_GND
VDD[+5V]
18
HOT_PLUG_DETECT
19
20
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
Only for training and service purposes
VDD12_3
10K
R3202
67
68
ARC
TX2P
69
70
TX2N
71
TX1P
72
TX1N
TX0P
73
74
TX0N
TXCP
75
TCVDD12
TXCN
76
77
78
TPVDD12
R0XCN
79
R0X0N
R0XCP
80
81
R0X0P
82
R0X1N
83
R0X1P
84
R0X2P
AVDD12_3
R0X2N
85
86
88
44
43
42
41
40
39
38
37
36
23
CBUS_HPD4
DSCL4
DSDA4
R3PWR5V
CBUS_HPD3
DSCL3
DSDA3
R1PWR5V
10K
R3244
C3207
0.1uF
16V
C3201
10uF
10V
1
2
3
4
C3203
10uF
10V
C3217
0.1uF
16V
5
6
7
8
9
10
11
Vout=0.8*(1+R1/R2)
12
13
HDMI4
14
15
16
17
18
5V_HDMI_1
19
BODY_SHIELD
5V_HDMI_2
R3231
10
51U019S-312HFN-E-R-B-LG
HDMI3
35
D
C3206
0.1uF
16V
C3213
1uF
1/16W
R3233
5.1K
5%
R3240
10
R3232
10
C3214
1uF
1/16W
R3234
5.1K
5%
5V_HDMI_4
5V_HDMI_3
20
BODY_SHIELD
JK3201
C3204
0.1uF
16V
DAADR019A
GND_2
7
5
HDMI_FOOSUNG
JK3203-*1
NC_3
8
4
HDMI_FOOSUNG
JK3202-*1
DAADR019A
TMDS_CH1-
7
5
BODY_SHIELD
BODY_SHIELD
GND_1
D0-
20
20
D3209-*1
IP4283CZ10-TBA
CK+_HDMI3
CK+
OUT
GND/ADJ
HDMI_ESD_NXP
CK-_HDMI3
2
2
1uF
10V
C3222
10uF
10V
C3218
10uF
10V
HDMI_HPD_4
9
CK_GND
3
C3215
0.1uF
16V
C3212
1
19
DDC_SCL_4
11
10
ESD_HDMI
D3209
RCLAMP0524PA
1
10
IN
18
HOT_PLUG_DETECT
19
DDC_SDA_4
ESD_HDMI
CK-
VDD[+5V]
18
C3209
0.1uF
16V
17
HDMI_HPD_3
EAG62611204
12
VDD[+5V]
HOT_PLUG_DETECT
CE_REMOTE
CEC_REMOTE
13
DDC/CEC_GND
DDC_SCL_3
14
VA3201
VA3200
NC
16
DDC_SDA_3
15
R4PWR5V
13
15
SDA
17
45
14
SCL
16
DSDA5[VGA]
22
HDMI_HPD_2
DDC_CLK
RESERVED
15
DSCL5[VGA]
46
12
CEC
13
14
SCL
47
21
11
TMDS_CLK-
12
CEC
RESERVED
48
20
CBUS_HPD1
TMDS_CLK-
DDC_SCL_3
10
TMDS_CLK_SHIELD
11
19
IC3200
AZ1117BH-1.2TRE1
9
TMDS_CLK+
10
R3216
10
R5PWR5V[VGA]
R4X0N
R3205 22
VA3214
ESD_HDMI
DDC_DATA
8
TMDS_DATA0-
9
TMDS_CLK+
TMDS_CLK_SHIELD
SBVCC5
7
TMDS_DATA0_SHIELD
8
TMDS_DATA0-
DDC_SDA_3
49
R4XCP
C3211
0.1uF
16V
1/16W
5%
TMDS_DATA0_SHIELD
R3203 22
PWRMUX_OUT
18
6
TMDS_DATA0+
7
C3210
0.1uF
16V
R3212
1
TMDS_DATA0+
LPSBV
50
5
TMDS_DATA1-
6
51
17
AVDD12_2
G
TMDS_DATA1-
4
TMDS_DATA1_SHIELD
5
C3200
10uF
10V
3
TMDS_DATA1+
4
52
16
R4XCN
2
TMDS_DATA2-
3
TMDS_DATA1+
15
VDD33_1
AO3438
Q3202
1
TMDS_DATA2_SHIELD
2
TMDS_DATA1_SHIELD
20
TMDS_DATA2+
1
TMDS_DATA2-
BODY_SHIELD
16
DAADR019A
1/16W
R3213
5.1K
5%
WKUP
R3X2P
HDMI_FOOSUNG
JK3201-*1
DAADR019A
TMDS_DATA2+
GND
CD_SENSE0
Device Address : 0XB0
R3X2N
D2-_HDMI3
S
HDMI_FOOSUNG
JK3200-*1
HDMI_HPD_3
TMDS_DATA2_SHIELD
17
CD_SENSE1
53
MHL_DET
+3.5V_ST
+5V_NORMAL
R3X1P
D1+_HDMI3
D2+_HDMI3
HDMI_FREEPORT HP_DET
19
5V
54
14
FHD
R3X1N
D1-_HDMI3
R3204
10K
HDMI2
VA3202
ESD_HDMI
L3203
L3202
+3.3V_NORMAL
JK3200
87
[EP]GND
D0+_HDMI3
5V_HDMI_3
13
R3X0P
D0-_HDMI3
R3252
33
12
R3X0N
CK+_HDMI3
D2+_HDMI2
51U019S-312HFN-E-R-B-LG
GPIO2
R3XCP
NC_1
D2-_HDMI2
D2+
CD_SENSE3
55
11
34
6
CK-_HDMI3
33
5
NC_2
DSCL1
7
6
TMDS_CH2+
CD-SENSE4
56
10
R3XCN
HDMI3
GND_2
8
4
GPIO0
57
HDMI_S/W_RESET
VDD12_1
NC_3
DSDA1
5
3
DDC_SCL_3
GPIO1
58
IC3201
SII9587CNUC
DDC_SCL_2
7
9
59
9
DDC_SDA_2
4
TMDS_CH2-
10
2
8
R0PWR5V
8
1
TPWR
32
3
D2_GND
GND_1
60
CBUS_HPD0
TMDS_CH1+
D1+_HDMI2
7
R1X2P
D2+_HDMI2
DDC_SCL_4
RESET_N
AVDD12_1
47K
DDC_SDA_4
I2C_SDA5
61
HDMI_HPD_1
9
NC_4
I2C_SCL5
6
DSCL0
D1-_HDMI2
2
D2-
DDC_SDA_3
HDMI_ESD_NXP
33
HDMI_INT
R1X2N
D2-_HDMI2
D3213-*1
IP4283CZ10-TBA
TMDS_CH1-
R3214
5
DSDA0
D1+
R3229
CSDA
33
DDC_SCL_1
D3213
RCLAMP0524PA
1
10
D1_GND
R3226
47K
47K
62
R3237
VDD12_2
D1-
33
R1X1P
D1+_HDMI2
R3220
R3218
47K
R3236
R1X1N
D1-_HDMI2
HDMI_ESD_SEMTEK
D0+
CSCL
31
D0+_HDMI2
D0_GND
D0+_HDMI2
D3205
33
63
30
D3203
R3211
4
DDC_SDA_1
NC_1
INT
R1X0P
D0-_HDMI2
29
D3201
28
6
NC_2
R4X2P
5
GND_2
D2+_HDMI4
7
64
THERMAL
89
27
6
8
4
SPDIF_IN
3
R4X2N
5
TMDS_CH2+
3
NC_3
D2-_HDMI4
D0-_HDMI2
D0-
9
R1X0N
CK+_HDMI2
NC_4
10
2
26
GND_1
TMDS_CH2-
1
RSVDL
65
R4X1P
7
TMDS_CH1+
66
2
D1+_HDMI4
4
TMDS_CH1-
CK+_HDMI2
1
25
CK+
8
A2
9
3
A1
2
+3.3V_NORMAL
R1XCP
CK-_HDMI2
+3.5V_ST
16V
0.1uF
C3225
C3224
0.1uF
16V
R1XCN
HDMI2
+5V_NORMAL
5V_HDMI_4
HDMI_ESD_SEMTEK
18
VDD33_2
C
C
CK_GND
+5V_NORMAL
5V_HDMI_3
HDMI_ESD_NXP
D3212-*1
IP4283CZ10-TBA
CK-_HDMI2
24
1
D3212
RCLAMP0524PA
1
10
CEC_REMOTE
R4X1N
2
CE_REMOTE
CK-
R4X0P
3
DDC_SCL_2
D1-_HDMI4
4
DDC_SDA_2
NC
D0+_HDMI4
6
5
47K
D0-_HDMI4
7
R3228
47K
DDC_SCL_1
CK+_HDMI4
8
R3225
DDC_SDA_1
VA3204
ESD_HDMI
CK-_HDMI4
9
DDC_CLK
C
11
10
47K
A2
EAG62611204
12
22
DDC_SCL_2
VA3203
ESD_HDMI
A1
13
R3210
DDC_DATA
R3219
R3217
47K
C
14
D3202
DDC_SDA_2
A2
15
VA3209
ESD_HDMI
22
A1
16
R3209
C
17
GND
A2
D3200
HDMI_FREEPORT HP_DET
19
5V
18
A1
VA3205
ESD_HDMI
20
+5V_NORMAL
5V_HDMI_2
HDMI_HPD_2
5V_HDMI_2
A1
BODY_SHIELD
A2
R3251
33
C3220
1uF
1/16W
R3241
5.1K
5%
R3238
10
C3219
1uF
1/16W
R3239
5.1K
5%
GP4
HDMI
32
LGE Internal Use Only
JK3401
JSTIB15
VIN
VCC
B
GND
R3400
33
C
SPDIF_OUT
C3400
0.1uF
16V
1/10W
5%
5
JACK_KSD
JK3403-*1
KJA-PH-0-0177
GND
5
R3406
HP_OUT
R3409
100
4
OPT
JACK_PARK
JK3403
PEJ038-3B6
+3.3V_NORMAL
GND
L
L
4
3
DETECT
3
R
1/16W
5%
4
DETECT
10K
HP_OUT
HP_DET
SHIELD
C3402
47pF
50V
VA3400
5.5V
R3404
150
HP_LOUT
A
Fiber Optic
+3.3V_NORMAL
SPDIF OUT
1
R
1
R3405
150
HP_ROUT
ADUC 5S 02 0R5L
EAG61030009
1/10W
5%
COMPONENT 1 PHONE JACK
EAG61030001
VA3405
5.6V
CVBS 1 PHONE JACK
+3.3V_NORMAL
OPT
+3.3V_NORMAL
C3401
18pF
R3402
10K
R3407
100
R3403
330K
R3408
100
COMP1_DET
AV1_CVBS_DET
1/16W
5%
VA3401
5.6V
VA3402
5.6V
JACK_PARK
JK3400
PEJ038-4G6
JACK_PARK
JK3402
PEJ038-4Y6
5
M5_GND
4
M4
3
1
6
M6
C3403
0.1uF
16V
1/16W
5%
for audio Hum noise (L)
5
M5_GND
4
M4
M3_DETECT
3
M3_DETECT
M1
1
M1
6
M6
COMP1_Y
COMP1/AV1/DVI_L_IN
VA3403
5.6V
EAG61030012
EAG61030011
COMP1_Pb
COMP1/AV1/DVI_R_IN
JACK_KSD
JACK_KSD
JK3400-*1
KJA-PH-1-0177-2
JK3402-*1
KJA-PH-1-0177-1
5
M5_GND
4
M4
3
M3_DETECT
1
M1
6
M6
VA3404
5.6V
5
M5_GND
4
M4
3
M3_DETECT
1
M1
6
M6
COMP1_Pr
AV1_CVBS_IN
EAG61030007
EAG61030006
SOC_RX
SOC_TX
P3400
+3.5V_ST
12507WS-04L
R3401
10K
1
2
3
4
5
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
Only for training and service purposes
BSD-NC4_H034-HD
JACK HIGH/MID
2012.10.09
LGE Internal Use Only
EPI_LOCK6
VCOM_DYN
PMIC_RESET
I2C_SDA2
I2C_SCL2
GST_SOC
GCLK_SOC
EO_SOC
MCLK_SOC
SMD TOP for EMI
GASKET_8.0X6.0X8.5H
M201
MDS62110209
EA98
GASKET_8.0X6.0X8.5H
M202
MDS62110209
GASKET_8.0X6.0X8.5H
M203
MDS62110209
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
Only for training and service purposes
BSD-NC4_H036-HD
NC4_H13
NON_EPI(OLED)
2013.02.22
36
LGE Internal Use Only
+3.5V_ST
Place Near Micom
+3.5V_ST
10K
R4000
OPT
LOGO_LIGHT
R4004
33
LOGO_LIGHT
LOGO_LIGHT
R4009
10K
5%
R4006
100
KEY1
LOGO_LIGHT_WAFER
VA4001
5.6V
AMOTECH CO., LTD.
R4007
100
LOGO_LIGHT
B
LOGO_LIGHT
R4001
10K
R4008
10K
5%
LOGO_LIGHT
R4003
33
C4000
0.1uF
16V
C
KEY2
C4001
0.1uF
1K Q4000
R4002
MMBT3904(NXP) E
LOGO_LIGHT
C4002
0.1uF
IR_WAFER_8P
VA4000
5.6V
AMOTECH CO., LTD.
P4002
12507WR-08L
KEY2
+3.5V_ST
L4001
BLM18PG121SN1D
+3.5V_ST
1
2
+3.5V_ST
C4005
1000pF
50V
R4005
10K
5%
GND
LOGO
LOGO_LIGHT_WAFER
NON_OLED
IR
NON_OLED
IR
C4006
100pF
50V
VA4002
5.6V
GND
AMOTECH CO., LTD.
R4011
100
EYE_SCL
EYE_SCL
VA4004
ADMC 5M 02 200L
OPT
EYE_SDA
3
4
5
6
7
8
R4010
100
9
EYE_SDA
GND
OLED_EYE_SDA
OLED_EYE_SCL
VA4003
ADMC 5M 02 200L
OPT
+3.3V_NORMAL
+3.5V_WOL
L4000
120-ohm
BLM18PG121SN1D
MAX 0.4A
L4002
120-ohm
P4003
SMAW200-H18S1
C4004
22uF
10V
C4007
0.1uF
R4012
100
+3.5V_WOL
1
2
3.3V
USB_DM
3
4
RST
USB_DP
5
6
RX
GND
7
8
TX
M_REMOTE_RX
WOL
10
RESET
M_REMOTE_TX
9
12
CTS
14
+3.5V_ST
WIFI_DP
C4016
5pF
50V
C4015
5pF
50V
WOL/WIFI_POWER_ON
For EMI
AR4000
100
1/16W
+3.3V_NORMAL
R4014
10K
WIFI_DM
M_REMOTE_RTS
C4012
1000pF
50V
M_RFModule_RESET
GND
NC
11
13
M_REMOTE_CTS
15
16
GND
EYE_SCL
17
18
EYE_SDA
IR
C4010
100pF
50V
OPT
VA4005
5.6V
AMOTECH CO., LTD.
OPT
OPT
C4008 C4009 C4013
47pF 47pF 47pF
50V
50V
50V
C4011
1000pF
50V
IR
R4013
22
L4003 +3.5V_ST
BLM18PG121SN1D
OPT
C4014
47pF
50V
For EMI
OLED_EYE_SDA
OLED_EYE_SCL
19 GND
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
Only for training and service purposes
BSD-NC4_H037-HD
NC4_H13
IR/KEY_OLED
2013.02.25
40
LGE Internal Use Only
+3.3V_NORMAL
CAMERA
C4202
4.7uF
OVCUR3
19
OVCUR4
IC4200
GL852G-31
18
TEST/SCL
3
0.1uF
DM4
DP3
/RST_HUB
C4209
0.1uF
CAMERA
AVDD_3
DM3
AVDD_2
CAMERA
R4214
1% 680
RREF
C4205
14
15
13
7
DP2
12
DP4
11
RESET
16
10
USB_CAMERA_DP
17
6
X2
0.1uF
CAMERA
5
DM2
9
USB_CAMERA_DM
4
X1
C4201
DP1
AVDD_1
USB_DP3
CAMERA
C4208
1/16W
5%
DM1
100K CAMERA
R4216
PSELF R4215100K CAMERA
PGANG
23
22
10K R4219
OPT
24
25
26
V5
27
20
CAMERA
2
8
BLM18PG121SN1D C4200
CAMERA
1uF
25V
0 R4210 CAMERA
DVDD
THERMAL
29
CAMERA
R4217
10K
0 R4206 CAMERA
USB_DM3
+3.3V_NORMAL
21
1
DP0
USB2_HUB_IC_IN_DP
SDA
10K R4218
0 R4205 CAMERA
CAMERA
L4200
120-ohm
28
DM0
USB2_HUB_IC_IN_DM
+3.3V_NORMAL
V33
[EP]GND
0 R4204
CAMERA
OVCUR1
0.1uF
OVCUR2
CAMERA
C4203
From HUB
USB_Camera
C4206
0.1uF
CAMERA
CAMERA
P4200
12507WR-12L
0.1uF
CAMERA
CAM_SLIDE_DET
OPT
X4200
12MHZ
X-TAL_1
GND_2
4
C4213
4.7uF
10V
CAMERA
ZD4200
5V
2
R4211
33 CAMERA
R4212
33 CAMERA CAMERA
AUD_LRCK
+5V_NORMAL
CAMERA POWER ENABLE CONTROL
AUD_SCK
NON_CAMERA
CAM_CTL
R4207
3.3K
R4208
22K
CAM_PWR_ON_CMD
7
ST_BY_DET_CAM
8
R4220
10K
CAMERA
USB_CAMERA_DP
Q4200
MMBT3904(NXP)
CAMERA_NON_OLED
E
Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
Only for training and service purposes
9
10
11
USB_CAMERA_DM
C
B
6
C4210
4.7uF
10V
CAMERA_NON_OLED
R4209
2.2K
CAMERA_NON_OLED
CAMERA_NON_OLED
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
5
33pF
50V C4211
CAMERA
0 R4203
USB_DP3
NON_CAMERA
CAMERA
CAMERA
VA4201
0 R4201
USB2_HUB_IC_IN_DP
4
33pF
R4213
50V C4212
33
CAMERA
RCLAMP0502BA
OPT D4200
USB_DM3
D
S
NON_CAMERA
0 R4202
G
CAMERA_NON_OLED
NON_CAMERA
0 R4200
+3.5V_CAM
3
33pF
50V C4214
L4201
CAMERA_NON_OLED
Q4201 UBW2012-121F
OLED
PMV48XP
+3.5V_ST
USB2_HUB_IC_IN_DM
CAMERA
AUD_LRCH
VA4200
X-TAL_2
OPT
3
CAMERA
C4207
22pF
CAMERA
2
GND_1
C4204
22pF
CAMERA
1
1
33pF
50V C4215
+3.5V_CAM
12
13
BSD-NC4_H042-HD
NC4_H13
2012.03.04
USB_HUB
42
LGE Internal Use Only
+5V_USB_1
USB1 (3.0)
MAX 1.2A
C4400
10uF
10V
JK4400
SJ113262
+3.3V_NORMAL
VBUS
OCP USB1
R4500
10K
OPT
DUSB3_DM
R4501
10K
D+
USB3_DP
IC4500
BD82020FVJ
GND
+5V_USB_1
1
2
3
4
+5V_NORMAL
7
3
6
4
5
USB3_RX0M
STDA_SSRX+
OUT_2
USB3_RX0P
OUT_1
C4501
GND_DRAIN
10uF
10V
STDA_SSTX-
OC
USB3_TX0M
STDA_SSTX+
USB_CTL1
OCP USB2/3
+5V_USB_2
3
6
4
5
FLT2
D4402
RCLAMP0502BA
D4401
RCLAMP0502BA
8
9
USB3 (2.0)
MAX 1.0A
3AU04S-305-ZC-(LG)
JK4300
1
2
1
C4322
10uF
10V
C4337
10uF
10V
USB_DM3
USB_DP3
C4310
10uF
10V
/USB_OCD2
C4301
10uF
10V
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
Only for training and service purposes
2
USB_DP2
+5V_USB_2
OUT2
3
OUT1
4
7
+5V_USB_3
RCLAMP0502BA
D4300
EN2
USB_CTL2
USB_DM2
/USB_OCD3
+5V_USB_3
5
USB_CTL3
FLT1
RCLAMP0502BA
D4302
EN1
2
8
9
IN
1
THERMAL
GND
C4302
0.1uF
16V
7
SHIELD
3AU04S-305-ZC-(LG)
JK4302
USB DOWN STREAM
10K
+5V_NORMAL
R4302
IC4306
TPS2066CDGNR [EP]GND
6
10
USB2 (2.0)
MAX 1.0A
10K
R4301
+3.3V_NORMAL
D4400
RCLAMP0502BA
USB3_TX0P
5
3
EN
/USB_OCD1
2
STDA_SSRX-
OUT_3
USB DOWN STREAM
IN_2
8
4
IN_1
C4500
0.1uF
16V
1
5
GND
BSD-NC4_H044-HD
2012-11-09
USB JACK
LGE Internal Use Only
+3.3V_NORMAL
Full Scart(18 Pin Gender)
EU
R4801
10K
CLOSE TO JUNCTION
EU
R4802
100
EU
C4804
0.1uF
VA4801
5.6V
EU
SC_DET
1/16W
5%
SC_CVBS_IN
VA4807
5.5V
EU
SHIELD
19
AV_DET
18
17
16
15
14
13
12
11
75
COM_GND
R4800
EU
VA4808
5.5V
OPT
SYNC_IN
DTV/MNT_V_OUT
SYNC_OUT
SYNC_GND
RGB_IO
SC_FB
R_OUT
VA4802
5.6V
EU
R_GND
G_OUT
10
G_GND
9
SC_R
ID
8
VA4803
5.5V
EU
B_OUT
7
AUDIO_L_IN
6
B_GND
5
SC_G
AUDIO_GND
4
VA4804
5.5V
EU
AUDIO_L_OUT
3
AUDIO_R_IN
2
AUDIO_R_OUT
1
SC_B
VA4805
5.5V
EU
DA1R018H91E
JK4800
EU
SC_ID
SC_L_IN
VA4809
5.6V
EU
VA4800
20V
EU
SC_R_IN
VA4806
5.6V
EU
BLM18PG121SN1D
L4800
EU
EU
C4800
1000pF
50V
DTV/MNT_L_OUT
EU
C4802
4700pF
BLM18PG121SN1D
L4801
EU
EU
C4801
1000pF
50V
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
Only for training and service purposes
EU
C4803
4700pF
DTV/MNT_R_OUT
BSD-NC4_H048-HD
2012.10.31
SCART GENDER
LGE Internal Use Only
Ethernet Block
LAN_JACK_POWER
C5100
0.1uF
16V
C5101
0.01uF
50V
C5102
0.1uF
16V
C5103
0.01uF
50V
JK5100
XRJH-01A-4-DA7-180-LG(B)
LAN_XML
1
2
3
4
5
6
P1[CT]
P2[TD+]
EPHY_TDP
P3[TD-]
EPHY_TDN
P4[RD+]
EPHY_RDP
P5[RD-]
EPHY_RDN
P6[CT]
VA5100
5.5V
7
8
9
10
11
D1
D2
D3
D4
VA5101
5.5V
VA5102
5.5V
VA5103
5.5V
P7
P8
P9
P10[GND]
P11
YL_C
YL_A
GN_C
GN_A
12
SHIELD
JK5100-*1
TLA-6T764
LAN_TDK
1
2
3
4
5
6
7
8
9
10
11
D1
D2
D3
D4
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10[GND]
R11
YL_C
YL_A
GN_C
GN_A
12
SHIELD
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LAN_VERTICAL
2011.12.09
50
LGE Internal Use Only
Ethernet Block
R5215
3.3K
+3.3V_WOL
EPHY_ACTIVITY
R5217 3.3K
ET_RXER
LAN_JACK_POWER
+3.3V_WOL
Place this cap. near IC
+3.5V_WOL
C5203
0.1uF
16V
EPHY_CRS_DV
ET_RXER
33
24
IC5200
RTL8201F-VB-CG
TXD[2]
RXDV
8
17
TXD[1]
TXD[0]
TXC
DVDD33
1/16W
5%
R5219
10K
C5212
0.1uF
OPT
OPT
33 R5221
EDID_WP (PHY reset from MICOM)
EPHY_TXD1
+3.3V_WOL
5pF
51
EPHY_TXD0
C5202
R5209
C5211
0.1uF
16V
EPHY_REFCLK
RXC
RXD[3]/CLK_CTL
OPT
EPHY_INT
R5208
3.3K
EPHY_RXD0
D
EPHY_EN
G
S
/RST_PHY (from SOC)
Place near IC
+3.5V_WOL
EPHY_RXD1
33pF
C5209
RXD[1]
33
33 RXD[2]/INTB
R5207
R5206
3.3K
R5200
+3.3V_WOL
RXD[0]
33
9
3.3K
R5201
R5203
Q4301
PMV48XP
EPHY_MDC
33 R5220
16
18
15
7
14
AVDD33_1
EPHY_MDIO
TXD[3]
13
TXEN
19
12
20
6
11
5
MDI-[1]
10
MDI+[1]
+3.3V_WOL
EPHY_RDN
1/16W
1%
PHYRSTB
4
EPHY_RDP
+3.5V_ST
3.3K
MDC
MDI-[0]
EPHY_TDN
WOL POWER ENABLE CONTROL
WOL/ETH_POWER_ON
MDIO
21
3
Route Single 50 Ohm, Differential 100 Ohm
EPHY_TDP
THERMAL
33
LED0/PHYAD[0]/PMEB
23
22
2
R5212
1.5K
CRS/CRS_DV
COL
26
DVDD10OUT
RXER/FXEN
27
28
AVDD33_2
CKXTAL1
+3.3V_WOL
1
MDI+[0]
29
RSET
AVDD10OUT
30
R5204
2.49K 1%
32
[EP]
50V
Place this Res. near IC
31
CKXTAL2
C5207
20pF
Place this cap. near IC
C5205
0.1uF
16V
R5210
R5218
0
1M R5202
GND_1
X-TAL_1
OPT
25MHz
X5200
1
X-TAL_2
3
4
2
+3.3V_WOL
GND_2
C5206
20pF
50V
ET_COL/SNI
Place 0.1uF close to each power pins
R5205
C5201
0.1uF
16V
LED1/PHYAD[1]
C5200
4.7uF
10V
25
BLM18PG121SN1D
EPHY_ACTIVITY
C5208
0.1uF
16V
ET_COL/SNI
L5200 120-ohm
R4317
22K
C4325
4.7uF
10V
R4318
2.2K
WOL_CTL
R4316
3.3K
C
Q4300
MMBT3904(NXP)
B
E
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
Only for training and service purposes
BSD-NC4_H052-HD
2012-09-12
ETHERNET
LGE Internal Use Only
R5602
0
Separate DGND AND AVSS
R5608 15K
C5613 2200pF
50V
OUT_A
1
PVDD_AB_2
BST_A
PVDD_AB_1
2
3
4
NC_1
PBTL
AVSS
PLL_FLTM
NC_2
7
8
9
PLL_FLTP
C5616
0.033uF
50V
NC_6
44
NC_5
43
BST_B
42
41
NC_4
40
NC_3
19
20
SCLK
21
SDIN
22
39
23
38
PGND_CD_2
SCL
24
37
R5612
18
OUT_C
PGND_CD_1
SPK_L50V
0.033uF
C5624
L5606
10.0uH
NRS6045T100MMGK
NRS6045T100MMGK
50V
0.033uF
C5625
36
35
34
33
32
31
30
AUD_LRCK
29
25
TAS5733
IC5600
49
18
SDA
E
17
LRCLK
C5605
4.7uF C5607
0.1uF
10V
L5604
10.0uH
SPK_R+
SPEAKER_R
C5631
0.47uF
50V
WOOFER_MUTE
+3.3V_NORMAL
C5606
L5602
0.1uF BLM18PG121SN1D
16V
C5617
C5610
0.1uF
16V
OUT_D
PVDD_CD_2
BST_D
PVDD_CD_1
GVDD_OUT
VREG
GND
AGND
DVSS
C5614
0.1uF
R5604
C5619
0.1uF
50V
0.033uF
50V
C5621
10uF
35V
C5623
10uF
35V
C5638
2200pF
50V
C5634
0.1uF
50V
C5639
2200pF
50V
C5635
0.1uF
50V
C5629
330pF
50V
1/16W
33
C5628
330pF
50V
+24V_AMP
R5614
18
AMP_RESET_N
C56151uF 25V
WOOFER_MUTE
I2C_SCL1
R5605
R5606
DVDD
33
33
I2C_SDA1
STEST
RESET
AUD_SCK
AUD_LRCH
SPEAKER_L
BST_C
DVSSO
PDN
100 C5602
1000pF
Q5600
50V
MMBT3904(NXP)
C5637
2200pF
50V
C5633
0.1uF
50V
OUT_B
45
16
28
10K
46
15
27
B
PGND_AB_1
OSC_RES
26
AMP_MUTE
PGND_AB_2
47
VR_DIG
AUD_MASTER_CLK
R5603
C
14
MCLK
18K
R5607 1%
R5601
10K
R5600
48
13
A_SEL_FAULT
C5630
0.47uF
50V
C5627
330pF
50V
[EP]
C5636
2200pF
50V
C5632
0.1uF
50V
1/16W
C5604
0.1uF
16V
C5618
0.1uF
50V
C5626
330pF
50V
C5620 C5622
10uF
10uF
35V
35V
R5613
18
C5603
10uF
10V
SPK_L+
R5611
18
+24V_AMP
THERMAL
AVDD
+3.3V_NORMAL
10
L5601
BLM18PG121SN1D
11
VR_ANA
470
12
OPT
ZD5601
5V
R5609
SSTIMER
C5608
0.047uF
5
C5609 4700pF
+3.3V_NORMAL
Close to Speaker
NRS6045T100MMGK
L5605
10.0uH
6
C5601
0.1uF
50V
0.047uF
C5611 4700pF
L5600
UBW2012-121F
R5610
470
This parts are Located
on AVSS area.
+24V_AMP
C5612
+24V
SPK_RL5603
10.0uH
NRS6045T100MMGK
WAFER-ANGLE
SPK_L+
SPK_L-
SPK_R+
SPK_R-
4
3
2
1
P5600
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
Only for training and service purposes
GP4_MT5369
AUDIO[ST]
2011.11.21
58
LGE Internal Use Only
WAFER-ANGLE
FILM_SPK
R5700
0
SPK_WOOFER_L+
4
SPK_WOOFER_L-
GND-4
3
SPK_WOOFER_R+
2
Separate DGND AND AVSS
SPK_WOOFER_R-
1
P5700
+24V_AMP_WOOFER
+12V
FILM_SPK
L5707
UBW2012-121F
FILM_SPK
C5701
0.1uF
50V
PVDD_AB_1
OUT_A
1
3
4
5
2
FILM_SPK
C5713 2200pF
50V
NC_1
FILM_SPK
BST_A
C5716
0.033uF
PVDD_AB_2
50V
SSTIMER
NC_2
AVSS
PBTL
7
8
9
PLL_FLTP
10
TAS5733
IC5700
PGND_AB_1
46
OUT_B
45
NC_6
44
NC_5
43
BST_B
42
NC_4
40
NC_3
FILM_SPK
SPK_WOOFER_LFILM_SPK
50V
0.033uF
C5724
22
39
OUT_C
SDA
23
38
24
37
PGND_CD_1
FILM_SPK
50V
0.033uF
C5725
FILM_SPK
L5702
BLM18PG121SN1D
C5710
0.1uF
16V
WOOFER
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
C5721
10uF
35V
C5723
10uF
35V
FILM_SPK
0.033uF
50V
FILM_SPK
1/16W
10K
OPT
R5710
FILM_SPK
R5711
18
OUT_D
PVDD_CD_2
PVDD_CD_1
BST_D
GVDD_OUT
VREG
C5717
C5719
0.1uF
50V
FILM_SPK
SPK_WOOFER_R+
FILM_SPK
C5734
0.1uF
50V
FILM_SPK
C5726
330pF
50V
FILM_SPK
C5731
0.47uF
50V
FILM_SPK
C5727
330pF
50V
1/16W
+3.3V_NORMAL
FILM_SPK
FILM_SPK
R5712
18
C5714
0.1uF
FILM_SPK
+24V_AMP_WOOFER
FILM_SPK
C5738
2200pF
50V
FILM_SPK
C5735
0.1uF
50V
FILM_SPK
C5739
2200pF
50V
WOOFER_R
SPK_WOOFER_RL5705
10K
FILM_SPK
33 R5702
AGND
GND
DVSS
R5704FILM_SPK
FILM_SPK
C5706
0.1uF
16V
Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
Only for training and service purposes
DVDD
R5703
FILM_SPK
33
OPT
R5709
AMP_RESET_N
33
C57151uF 25V
FILM_SPK
I2C_SCL1
STEST
RESET
AUD_SCK
AUD_LRCH
NRS6045T100MMGK
L5703
10.0uH
FILM_SPK
36
30
25
FILM_SPK
AUD_LRCK
I2C_SDA1
L5706
10.0uH
NRS6045T100MMGK
PGND_CD_2
SCL
35
SDIN
C5707
0.1uF
34
21
33
20
32
19
31
18
WOOFER
17
VR_DIG
SCLK
C5705
FILM_SPK
4.7uF
10V
DVSSO
LRCLK
AUD_MASTER_CLK
WOOFER_L
FILM_SPK
C5737
2200pF
50V
BST_C
41
49
16
FILM_SPK
C5733
0.1uF
50V
FILM_SPK
C5736
2200pF
50V
R5714
18
FILM_SPK
PGND_AB_2
47
FILM_SPK
C5732
0.1uF
50V
FILM_SPK
C5730
0.47uF
50V
FILM_SPK
C5729
330pF
50V
[EP]
PDN
R5705 1%
FILM_SPK
FILM_SPK
100 C5702
1000pF
50V
15
29
WOOFER_MUTE
MCLK
OSC_RES
28
FILM_SPK
R5701
FILM_SPK
18K
14
FILM_SPK
R5713
18
FILM_SPK
C5728
330pF
50V
FILM_SPK
FILM_SPK C5720 C5722
C5718
10uF
10uF
0.1uF
35V
35V
50V
FILM_SPK
48
13
A_SEL_FAULT
27
FILM_SPK
R5706 15K
C5704
0.1uF
16V
FILM_SPK
Close to Speaker
SPK_WOOFER_L+
+24V_AMP_WOOFER
THERMAL
AVDD
C5703
10uF
10V
11
VR_ANA
12
L5701
470
FILM_SPK
OPT
ZD5701
5V
0.047uF
BLM18PG121SN1D
R5708
470
FILM_SPK
R5707
PLL_FLTM
FILM_SPK
C5708
+3.3V_NORMAL
FILM_SPK
NRS6045T100MMGK
L5704
10.0uH
6
FILM_SPK
C5709 4700pF
C5712
GND-4
FILM_SPK
0.047uFFILM_SPK
This parts are Located
on AVSS area.
26
OPT
L5700
UBW2012-121F
FILM_SPK
4700pF
C5711
+24V
FILM_SPK
10.0uH
NRS6045T100MMGK
FILM_SPK
BSD-NC4_H038-HD
NC4_H13
TI_AMP_FILM_SPK
2013.02.01
57
LGE Internal Use Only
+12V
EU
AUD_OUT & gt; & gt; EU/CHINA_HOTEL_OPT
IC6000
AZ4580MTR-E1
L6000
EU
EU
OUT1
R6000
C6000
1uF
25V
EU
OPT
C6002
6800pF
OPT
R6002
33K
EU
R6004
IN1-
470K
C6003
33pF
EU
IN1+
VEE
SCART_AMP_L_FB
1
8
2
7
4
C6004
EU
0.1uF
OUT2
R6011
2.2K
50V
SIGN600002
[SCART AUDIO MUTE]
EU
C6008
DTV/MNT_R_OUT
EU
3
VCC
6
IN2-
R6008
EU
33K
OPT
R6010
470K
5
OPT
1uF
C6007
DTV/MNT_L_OUT
25V
6800pF
EU
IN2+
C
C6005 EU
33pF
Q6000
MMBT3904(NXP)
SCART_AMP_R_FB
B
EU_SCART_MUTE_ISAHAYA
Q6002
RT1P141C-T112
EU
SCART_Lout
SCART_MUTE
B
C
E
R6013
1K
E
2.2K
DTV/MNT_L_OUT
SCART_Rout
DTV/MNT_R_OUT
Q6001
MMBT3904(NXP)
E
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
Only for training and service purposes
E
R6014
1K
B
B
PDTA114ET
Q6002-*1
C
EU
C
EU
EU_SCART_MUTE_NXP
SCART AUDIO AMP
2011.11.21
60
LGE Internal Use Only
HP_OUT_H13
HP_OUT_H13
C6109-*1
18pF
C6104-*1
18pF
EARPHONE AMP
IC6100
TPA6138A2
HP_OUT
C6100
R6100
1uF
10V
HP_OUT 10K
+INR
HP_OUT_MTK
C6104
180pF
HP_OUT
R6106
43K
HP_OUT
-INR
HP_ROUT_MAIN
1%
R6103
33K
HP_OUT_MTK
HP_OUT_H13
R6103-*1
43K
C6108
10pF
50V
OUTR
1
14
13
2
12
3
+INL
HP_OUT_MTK
HP_OUT
R6104
-INL HP_OUT
43K
C6109
180pF
HP_OUT
R6101
10K
C6101
1uF
10V
HP_OUT
HP_LOUT_MAIN
OUTL
C6106
10pF
50V
1%
R6102
33K
HP_OUT_MTK
HP_LOUT_AMP
HP_ROUT_AMP
GND_1
+3.3V_NORMAL
11
4
UVP
+3.3V_NORMAL
HP_OUT_H13
R6102-*1
43K
1%
MUTE
SIDE_HP_MUTE
HP_OUT
4.7K
R6105
VSS
5
10
6
9
GND_2
VDD
HP_OUT
C6102
1uF
10V
HP_OUT
1%
HP_OUT
CN
7
8
CP
L6100
120-ohm
BLM18PG121SN1D
C6105
1uF
10V
HP_OUT
C6107
0.1uF
16V
C6103
1uF
10V
HP_OUT
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
Only for training and service purposes
HEADPHONE AMP
2011.09.29
61
LGE Internal Use Only
CI POWER ENABLE CONTROL
IC6200
AP2151WG-7
+5V_NORMAL
IN
5
+5V_CI_ON
1
OUT
CI
2
CI
R6217
100
PCM_5V_CTL
EN
4
3
GND
FLG
C6210
1uF
25V
CI
R6219
10K
CI
R6218
10K
CI
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
Only for training and service purposes
CI SLOT
2011.10.31
62
LGE Internal Use Only
B-CAS (SMART CARD) INTERFACE
+3.3V_NORMAL
INT
CMDVCC :
STATUS
--------------------------------HIGH
HIGH
CARD PRESENT
LOW
HIGH
CARD not PRESENT
+3.3V_NORMAL
IC6300
TDA8024TT
OPT
OPT
R6304
2.7K
JAPAN
R6306
5V/3V
R6300 22
R6302
SMARTCARD_PWR_SEL/SD_EMMC_DATA[1]
PGND
+5V_NORMAL
S2
JAPAN
28
2
27
3
26
4
25
5
24
6
23
AUX2UC
AUX1UC
JAPAN
R6316
1.2K
JAPAN
1
OPT
R6319
1.2K
CLKDIV2
JAPAN
R6315
1.2K
CLKDIV1
OPT
R6318
1.2K
CLKDIV1 CLKDIV2 : F_CRD_CLK
----------------------------1
0
CLKIN
JAPAN
R6317
1.2K
2.7K
JAPAN
OPT
R6305
R6301
2.7K
JAPAN
R6303
SIGN630028
I/OUC
JAPAN
R6307
22
SMARTCARD_DATA/SD_EMMC_CLK
XTAL2
JAPAN
R6308
22
SMARTCARD_CLK/SD_EMMC_DATA[0]
XTAL1
JAPAN
R6309
22
SMARTCARD_DET/SD_EMMC_DATA[3]
OFF
JAPAN
R6310
22
SMARTCARD_RST/SD_EMMC_DATA[2]
L6300
VDDP
JAPAN
C6300
0.1uF
16V
JAPAN
C6301
10uF
10V
JAPAN
C6303
0.1uF
16V
S1
22
7
JAPAN
R6311
22
GND
VUP
JAPAN
C6302
0.1uF
16V
PRES
PRES
I/O
AUX2
AUX1
CGND
8
21
9
20
10
19
11
18
12
17
13
16
14
15
SMARTCARD_VCC/SD_EMMC_CMD
L6301 JAPAN
BLM18PG121SN1D
JAPAN
VDD
RSTIN
JAPAN
C6305
0.1uF
16V
JAPAN
C6306
0.1uF
16V
CMDVCC
+3.3V_NORMAL
BLM18PG121SN1D
B-CAS SLOT
P6300
10057542-1311FLF(B CAS Slot)
PORADJ
VCC
VCC
JAPAN
C6307
0.33uF
16V
RST
RST
Place CLK C3 far from C2,C7,C4 and C8
CLK
CLK
JAPAN
C6304
0.1uF
16V
RESERVED_1
GND
VPP
JAPAN
R6313
75
I/O
C1
C2
C3
C4
C5
JAPAN
C6
C7
75 ohm in I/O is for short circuit Protection
RESERVED
JAPAN
+3.3V_NORMAL
R6314
1K
JAPAN
ZD6300
5V
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
Only for training and service purposes
SW2
JAPAN
10K
R6312
JAPAN
SW1
C8
S1
S2
ZD6301
5V
CI SLOT
2011.04.17
62
LGE Internal Use Only
/TU_RESET2
RF_SWITCH_CTL_50
FE_DEMOD1_TS_ERROR
TU_W_BR/TW/CO
L6508-*1
0
+3.3V_TU
TU_Q/W_KR/JP/AU
L6508
BLM18PG121SN1D
TU_S/N/Q/W
/TU_RESET1
C6520
0.1uF
16V
TU_N/M/W_CN/TW/BR/CO
R6508-*1
1
I2C_SCL6_TU
1K
5%
RF_SWITCH_CTL_50
C6502
TU_S/N/Q/W
0.1uF
R6508
TU_N/Q_KR/TW/BR/CO/AU
4
I2C_SDA6_TU
5
+3.3V_TU
6
7
NON_TU_W_BR/TW/CO
R6509
I2C_SCL6
33
NON_TU_W_BR/TW/CO
R6510
I2C_SDA6
33
R6534
TU_CVBS_TU
OPT
R6516
470
0.1uF
10
IF_P
11
IF_N
12
C
Power_D_Demod_TU
IF_AGC
C6503-*1
0.1uF
16V
14
CN_RESET_TU
IF_P
should be guarded by ground
IF_N
+3.3V_TU
TU_N/M_CN/BR
L6502
BLM18PG121SN1D
R6506-*1
TU_W_BR/TW
TU_N/M
R6502
10
TU_N_BR
R6502-*1
/S2_RESET
1K
100
TU_Q/W_KR/BR/TW/CO/JP/AU
L6507
TU_A_GLOBAL_6/7
Q6501
MMBT3906(NXP)
C6530
0.1uF
16V
T2 : Max 1.0A
else : Max 0.7A
output : 1.1V_D_Demod
for DVB-T2(V1.3.1) Sony Demod
TU_W_CO_T2
R6528-*1
6.8K
TU_Q/N/M/W
1. should be guarded by ground
2. No via on both of them
3. Signal Width & gt; = 12mils
Signal to Signal Width = 12mils
Ground Width & gt; = 24mils
+3.3V_TU
IC6501
AP2132MP-2.5TRG1
1
2
+1.8V_TU
16
FE_DEMOD1_TS_ERROR
17
FE_DEMOD1_TS_SYNC
18
FE_DEMOD1_TS_VAL
FE_DEMOD1_TS_CLK
EN
GND
7
ADJ
3
6
TU_Q/N/M/W
VOUT
VIN
C6533
10uF
16V
FE_DEMOD1_TS_VAL
19
C6516-*1
0.1uF
16V
TU_W_BR/TW/CO/JP
TU_Q/N/M/W
R6527
R2
20K
1%
TU_Q/N/M/W
R6528
11K
1%
R6529 R1
10K
1%
8
PG
TU_Q/N/M/W
R6523
10K
+1.23V_D_Demod
1%
[EP]
TU_Q/N/M/W
C6540
0.1uF
+1.23V_D_Demod
C6516
BLM18PG121SN1D
0.1uF
16V
TU_N/M/Q/W_KR/CN/BR/JP/AU
5%
C6529
22uF
10V
85C
C6526
0.1uF
16V
TU_W_BR/TW
+3.3V_TU
13
R6506
100
TU_S/N/Q_T/US/KR/TW/AU
TU_A_GLOBAL_6/7
R6521
200
B
+1.8V_TU
C6550
0.1uF
16V
L6503
BLM18PG121SN1D
E
OPT
Q6500
C
MMBT3906(NXP)
OPT
R6515
4.7K
+3.3V_TU
1608 perallel
because of derating
TU_CVBS
B
16V
close to Tuner
TU_S/N/Q_T/US/KR/TW/AU
close to Tuner
TU_A_GLOBAL_6/7
R6520
200
TUNER_SIF
E
OPT
C6522
L6500
TU_W_BR/TW/CO/JP/_Q_AU BLM18PG121SN1D
C6503
0.1uF
16V
+3.3V_TU
OPT
R6518
82
close to TUNER
+3.3V_TU
IF_AGC_TU
+3.3V_NORMAL
0
+3.3V_TU
TU_W_BR/TW/CO/JP/_Q_AU
C6554
100pF
50V
mA(MAX)
TU_A_GLOBAL_6/7
C6514
0.1uF
16V
TU_+1.8V_TU
8
C6506
47pF
50V
C6508
47pF
50V
TUNER_SIF_TU
9
R6501 1K
TU_M/W_BR/TW/CO/CN
100 TU_M/W_BR/TW/CO/CN
TU_N/Q_KR/TW/BR/CO/AU
TU_W_BR/TW/CO/JP TU_W_BR/TW/CO/JP
TU_W_BR/TW/CO TU_W_BR/TW/CO TU_W_BR/TW/CO
C6508-*1
R6509-*1
R6534-*1
R6510-*1
C6506-*1
18pF
18pF
150
300
220
RF_SWITCH_CTL
R6505
10K
/TU_RESET1_TU
3
R6500 1K
TU_N/M_TW/BR
TU_N/M_TW/BR
C6501
0.1uF
RF_SWITCH_CTL_TU
2
TU_N_TW/BR
9
TU_W_BR/TW/CO
C6501-*1
1000pF
THERMAL
close to TUNER
2A
4
+5V_NORMAL
5
NC
VCTRL
FE_DEMOD1_TS_CLK
FE_DEMOD1_TS_ERROR
EAN61387601
Global F/E Option Name
1. TU
2. Tuner Name = TDS’S’,TDS’Q’...
3. Country Name = T,T2,S2,KR,US,BR ...
TU_Q/N/M/W
C6535
1uF
Vout=0.6*(1+R1/R2)
20 FE_DEMOD1_TS_DATA[0]
FE_DEMOD1_TS_DATA[0-7]
21 FE_DEMOD1_TS_DATA[1]
FE_DEMOD1_TS_DATA[0]
Example of Option name
TU_Q_T2 = apply TDSQ type tuner and T2 country
TU_M/W = apply TDSM & TDSW Type Tuner
13’ Tuner Type
TDS’S’-G501D :
TDS’Q’-G501D :
TDS’Q’-G601D :
TDS’Q’-G651D :
TDS’M’-C601D :
TDS’W’-J551F :
TDS’W’-B651F :
TDS’W’-A651F :
TDS’W’-K651F :
FE_DEMOD1_TS_DATA[1]
22 FE_DEMOD1_TS_DATA[2]
24 FE_DEMOD1_TS_DATA[4]
CHB : Max mA
else : Max mA
FE_DEMOD1_TS_DATA[2]
FE_DEMOD1_TS_DATA[3]
23 FE_DEMOD1_TS_DATA[3]
+3.3V_TU
FE_DEMOD1_TS_DATA[4]
for Global
T/C Half NIM Horizontal Type
T/C/S2 Combo Horizontal type
T2/C/S2 Combo Horizontal Type
T2/C/S2 Combo Vertical Type
China NIM with Isolater Type
Japan Dual NIM
Brazil 2Tuner
Taiwan 2Tuner
Colombia DVB-T2 2Tuner
C6549
10uF
16V
FE_DEMOD1_TS_SYNC
+1.8V_TU
FE_DEMOD1_TS_DATA[5]
IC6503
FE_DEMOD1_TS_DATA[6]
25 FE_DEMOD1_TS_DATA[5]
AZ1117BH-1.8TRE1
FE_DEMOD1_TS_DATA[7]
IN
26 FE_DEMOD1_TS_DATA[6]
3
2
OUT
1
ADJ/GND
27 FE_DEMOD1_TS_DATA[7]
TU_Q/W
+1.23V_D_Demod
L6501
BLM18PG121SN1D
30
31
+1.23V_D_Demod_TU
C6515
0.1uF
TU_Q/W
/S2_RESET_TU
32
+3.3V_TU
33
I2C_SCL4_TU
35
C6546
10uF
10V
C6548
10uF
10V
TU_W
R6513-*1
1K
5%
TU_Q
R6513
LNB_TX
34
R6531
1
I2C_SDA4_TU
10
/S2_RESET
+3.3V_TU
+3.3V_TU
LNB_TX
TU_Q/W_KR/BR/CO/TW/JP/AU R6503
36
22
C6521
0.1uF
OPT
I2C_SCL4
TU_Q/W
LNB_OUT
C6531
0.1uF
C6504
18pF
50V
TU_Q/W_KR/BR/CO/TW/JP/AU
R6504
22
C6538
10uF
10V
C6542
0.1uF
I2C_SDA4
TU_Q/W
LNB_OUT
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
Only for training and service purposes
C6500
18pF
50V
Close to the tuner
TUNER
2012.07.10
65
LGE Internal Use Only
4
5
6
7
8
9
10
11
A1
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
SCL
SCL
SDA
SDA
I2C_SCL6_TU
+B1[3.3V]
SIF
+B1[3.3V]
I2C_SDA6_TU
+3.3V_TU
+B2[1.8V]
CVBS
TU6701
TDSM-C651D(B)
SIF
+B2[1.8V]
TUNER_SIF_TU
TU_M_CN
TU_+1.8V_TU
8
IF_AGC
9
DIF[P]
10
DIF[N]
11
A1
12
13
12
14
SHIELD
15
16
17
18
RF_S/W_CTL
RF_SWITCH_CTL_50
RESET
TU_PIN2
SCL
I2C_SCL6_TU
SDA
I2C_SDA6_TU
+B1[3.3V]
+3.3V_TU
SIF
TUNER_SIF_TU
+B2[1.8V]
TU_+1.8V_TU
50
19
51
20
52
21
53
22
54
23
55
24
56
25
26
27
CVBS
CVBS
NC_2
NC_1
NC_3
NC_2
NC_4
NC_3
+B3[3.3V]
+B3[3.3V]
+B4[1.23V]
+B4[1.23V]
NC_5
DEMOD_RESET
GND
GND
NC_4
ERROR
SYNC
SYNC
D6
D6
D7
D7
B1
A1
25
26
27
28
A1
A1
29
28
A2
30
A2
SHIELD
31
TU_GND_B
32
TU_GND_A
TU_GND_B
B2
59
SHIELD
B2
B1
A1
24
27
D5
D5
23
26
D4
D4
22
25
D3
D3
21
24
D2
D2
20
23
D1
D1
19
22
D0
D0
B1
B1
19
MCLK
18
21
MCLK
18
VALID
17
20
VALID
17
33
34
35
B1
B1
A1
1
RESET
2
TU_SCL
3
TU_SDA
4
+B2[3.3V_M]
5
S_SIF
6
+B3[1.8V_M]
7
S_CVBS
8
M_IF_AGC
9
M_DIF[P]
10
M_DIF[N]
11
+B4[3.3V_S]
12
+B5[1.8V_S]
13
NC_1
14
GND
15
SD_ERROR
16
SD_SYNC
17
SD_VALID
18
SD_MCLK
19
SD_SERIAL_D0
20
NC_2
21
NC_3
22
NC_4
23
NC_5
24
NC_6
25
NC_7
26
NC_8
27
GND_1
28
GND_2
29
+B6[1.23V_SD]
30
SD_RESET
31
+B7[3.3V_SD]
32
NC_9
33
SD_SCL
34
SD_SDA
35
36
A1
TU_M_CN
C6706
1000pF
630V
B1
TU_GND_B
SHIELD
OPT
ZD6501
2.5V
0 R6703
NON_CHINA
NON_CHINA
0 R6702
NON_CHINA
TU_GND_B
+1.8V_TU
TU_GND_A
TU_GND_B
0 R6701
C6707
630V
NON_CHINA
0 R6700
TU_M_CN
1000pF
EOS for Tuner 1.8V LDO
2
SCL
3
SDA
4
+B1[3.3V]
5
B1
38
A1
TU6702-*1
TDSQ-A651D(B)
TU6704-*4
TDSN-T751F
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
LNA_CTRL1
LNA_CTRL2
R6704
100
TU_PIN2
B1
57
26
58
27
B1
A1
RF_S/W_CTL
1
RESET
2
SCL
3
SDA
4
+B1[3.3V]
5
SIF
6
+B2[1.8V]
7
CVBS
8
IF_AGC
9
DIF[P]
10
DIF[N]
11
NC_1
12
NC_2
13
NC_3
14
GND
15
NC_4
16
NC_5
17
NC_6
18
NC_7
19
NC_8
20
NC_9
21
NC_10
22
NC_11
23
NC_12
24
NC_13
25
NC_14
26
NC_15
27
A1
28
59
29
30
SHIELD
TU_M/W
C6700
0.1uF
TU6704-*1
TDSW-B652F(B)
TU_AJJA
1
2
31
TU_M/W
32
33
34
35
B1
B1
A1
TU_BR
+B1[+3.3V_S/P]
1
RESET
2
TU_SCL
3
TU_SDA
4
+B2[3.3V_M]
5
S_SIF
6
+B3[1.8V_M]
7
S_CVBS
8
M_IF_AGC
9
M_DIF[P]
10
M_DIF[N]
11
+B4[3.3V_S]
12
+B5[1.8V_S]
13
TU_CO
1
2
TU_SCL
3
TU_SDA
4
+B2[3.3V_M]
5
S_SIF
6
+B3[1.8V_M]
7
S_CVBS
8
M_IF_AGC
9
M_DIF[P]
10
M_DIF[N]
11
+B4[3.3V_S]
12
+B5[1.8V_S]
13
+B1(3.3V)_S/P
1
T_RESET
2
TU_SCL
3
TU_SDA
4
+B2[3.3V_M]
5
S_SIF
6
+B3[1.8V_M]
7
S_CVBS
8
M_IF_AGC
9
M_DIF[P]
10
M_DIF[N]
11
+B4[3.3V_S]
12
+B5[1.8V_S]
13
+B1(3.3V)_S/P
T_RESET
NC_6
13
TU_W_JP
10K
NC_3
NC_4
58
NC_5
NC_6
NC_7
NC_8
GND_1
28
GND_2
29
+B6[1.23V_SD]
30
SD_RESET
31
+B7[3.3V_SD]
32
NC_9
33
SD_SCL
34
SD_SDA
35
GND_1
28
GND_2
29
+B6[1.23V_D]
30
D_RESET
31
+B7[3.3V_D]
32
NC_1
33
D_SCL
34
D_SDA
35
GND_1
28
GND_2
29
+B6[1.23V_D]
30
D_RESET
31
+B7[3.3V_D]
32
NC_1
33
SD_SCL
34
SD_SDA
35
GND_1
GND_2
28
GND_3
29
+B3[1.23V]
30
DEMOD_RESET
31
F22_OUTPUT
32
DEMOD_SCL
33
DEMOD_SDA
34
LNB
35
GND_4
TU_Q_T2/S2
GND_2
38
39
40
RF_S/W_CTRL
NC_2
50
41
51
42
43
44
45
46
47
48
49
B1
B1
A1
59
38
GND_4
39
MD_ERROR
40
MD_SYNC RF_S/W_CTRL
MD_VALID
NC_7
50
41
51
42
MD_MCLK
43
MD_DATA
44
SD_ERROR
45
SD_SYNC
46
SD_VALID
47
SD_MCLK
48
SD_DATA
A1
49
B1
B1
A1
GND_3
38
GND_4
39
NC_2
NC_3
40
RF_S/W_CTRL
NC_4
NC_2
50
41
51
42
NC_5
43
NC_6
44
SD_ERROR
45
SD_SYNC
46
SD_VALID
47
SD_MCLK
48
SD_DATA
A1
49
B1
B1
A1
R6706
+1.23V_D_Demod_TU
MD_VALID
MD_MCLK
MD_DATA
SD_ERROR
SD_SYNC
SD_VALID
SD_MCLK
SHIELD
33
I2C_SCL4_TU
34
I2C_SDA4_TU
35
LNB_OUT
36
A1
38
40
NC_7
FE_DEMOD2_TS_ERROR
40
FE_DEMOD2_TS_SYNC
41
FE_DEMOD2_TS_VAL
42
FE_DEMOD2_TS_CLK
43
FE_DEMOD2_TS_DATA
44
FE_DEMOD3_TS_ERROR
45
FE_DEMOD3_TS_SYNC
46
FE_DEMOD3_TS_VAL
TU_W_JP
C6701
0.1uF
16V
LNA_CTR1
47
FE_DEMOD3_TS_CLK
LNA_CTR2
48
FE_DEMOD3_TS_DATA
TU_QW
L6701
BLM18PG121SN1D
49
NC_6
D_SCL
D_SDA
LNB
50
41
51
42
52
43
53
44
54
45
55
46
56
47
57
48
58
49
GND_4
GND_5
GND_6
TS1_ERROR
TS1_SYNC
TS1_VALID
TS1_MCLK
TS1_DATA
TS2_ERROR
TS2_SYNC
TS2_VALID
TS2_MCLK
TS2_DATA
TU_W_JP
B1
C6702
0.1uF
16V
B1
A1
A1
+3.3V_D_Demod2
59
+3.3V_TU
TU_QW
C6708
0.1uF
D_SCL
MD_ERROR
32
LNB_TX
+B6[3.3V]
D_SDA
MD_SYNC
31
+3.3V_D_Demod2
D_RESET
+B7[3.3V_D]
GND_4
30
/S2_RESET_TU
+B5[1.23V]
NC_1
GND_3
27
GND_3
SHIELD
TU_QW
C6709
10uF
10V
TU_MNQW
L6700
BLM18PG121SN1D
+3.3V_D_Demod
+3.3V_TU
TU_MNQW
C6703
0.1uF
SD_DATA
A1
59
59
SHIELD
Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
Only for training and service purposes
GND_3
36
37
D_RESET
A1
SHIELD
FE_LNA_Ctrl2
26
GND_2
0
SHIELD
+B6[1.1V_D]
36
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
R6705
25
D7
NC_9
NC_2
24
D6
SCL_S
SD_MCLK
23
D5
RESET_T2
SD_SERIAL_D0
22
D4
+B5[1.8V_S]
SD_SYNC
21
D3
+B4[3.3V]
SD_VALID
20
D2
39
TU_W_JP
10K
19
+1.8V_T2
D1
TU_+1.8V_TU
FE_LNA_Ctrl1
18
+3.3V_T2
D0
M_DIF[P]
57
17
NC_5
MCLK
S_CVBS
SD_ERROR
16
NC_4
VALID
NC_8
NC_1
14
NC_3
SYNC
+3.3V_S_TUNER
GND
13
NC_2
ERROR
TUNER_SIF_TU
56
12
Power_D_Demod_TU
+1.8V_T1
GND
M_IF_AGC
M_DIF[N]
11
+3.3V_D_Demod
NC_1
NC_7
+B2[3.3V_M]
+B4[3.3V_S]
10
IF_N
FE_DEMOD1_TS_DATA[7]
12
9
IF_P
FE_DEMOD1_TS_DATA[6]
NC_5
8
IF_AGC_TU
FE_DEMOD1_TS_DATA[5]
11
7
TU_CVBS_TU
FE_DEMOD1_TS_DATA[4]
NC_4
6
TU_+1.8V_TU
FE_DEMOD1_TS_DATA[3]
10
5
FE_DEMOD1_TS_DATA[2]
NC_3
+3.3V_TU
TUNER_SIF_TU
FE_DEMOD1_TS_DATA[1]
9
+3.3V_TU
55
4
+3.3V_T1
FE_DEMOD1_TS_DATA[0]
8
NC_2
TU_SCL
S_SIF
3
I2C_SDA6_TU
SDA_T
FE_DEMOD1_TS_CLK
CVBS
TU_SDA
+B3[1.8V_M]
2
I2C_SCL6_TU
SCL_T
FE_DEMOD1_TS_VAL
7
I2C_SDA6_TU
54
/TU_RESET1_TU
FE_DEMOD1_TS_SYNC
+B2[1.8V]
TU6704-*3
TDSW-K651F(B)
TU6704-*2
TDSW-A652F(B)
TU_TW
+B1(3.3V)_S/P
T_RESET
1
RESET_T1
FE_DEMOD1_TS_ERROR
6
SDA_S
TU_TW_SINGLE
C6705
10uF
10V
+5V_OR_+3.3V_SPLITTER
CN_RESET_TU
SIF
50 RF_SWITCH_CTL_50
51
TU_PIN2
I2C_SCL6_TU
52
53
/TU_RESET2
1
RESET
R6707
37
36
GND seperation for CHINA tuner
N.C_1
TU_GND_B
TU_GND_B
B1
RESET
TU_W_JP
TU_Q_T2/S2
+B1[+3.3V_S/P]
R6708 0
3
RESET
TU_Korea_PIP
NC_1
TU_W_JP
2
TU6704
TDSW-J551F(B)
TU_GND_A
1
NC
TU6703
TDSQ-G651D(B)
RF_SWITCH_CTL_TU
TU_T2/C
TU_S_US
B1
TU6702
TDSQ-H651F(B)
TU6705
TDSN-G351D
TU6700
TDSS-H651F(B)
SHIELD
TU_MNQW
C6704
10uF
10V
BSD-NC4_H067-HD
TU_SYMBOL
2012.09.14
LGE Internal Use Only
DVB-S2 LNB Part Allegro
(Option:LNB)
Input trace widths should be sized to conduct at least 3A
3A
Ouput trace widths should be sized to conduct at least 2A
+12V
2A
D6904-*1
Max 1.3A
40V
LNB_SX34
A_GND
GNDLX
LX
16
NC_3
BOOST
NC_2
17
18
19
VREG
12
ISET
11
TCAP
LNB
5
A_GND
A_GND
LNB
R6903
39K
C6912
Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LNB
LNB_TX
I2C_SDA4
I2C_SCL4
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
1/16W
1%
LNB
0.1uF
C6911
Close to Tuner
Surge protectioin
13
LNB
0.22uF
TDO
D6903-*1
LNB_SX34
40V
3
IC6900
4
A8303SESTR-T
R6904
0
GND
10
C6902
0.22uF
25V
TDI
TONECTRL
LNB
C6904
0.1uF
50V
VIN
14
9
LNB
2
ADD
D6900
LNB
R6900
2.2K
1W
LNB
NC_1
LNB
R6901 33
C6901
33pF
LNB
D6903
LNB_SMAB34
40V
8
30V
LNB
7
LNB_OUT
THERMAL
21
Caution!! need isolated GND
C6910
0.1uF
50V
15
1
SDA
LNB
R6902 33
VCP
D6901
MBR230LSFT1G
close to VIN pin(#15)
20
A_GND
C6909
10uF
25V
LNB
A_GND
A_GND
6
close to Boost pin(#1)
SCL
C6907
10uF
25V
LNB
[EP]GND
C6906
10uF
25V
LNB
IRQ
C6905
10uF
25V
LNB
LNB
C6903
0.01uF
50V
LNB
SP-7850_15
15uH
L6900
LNB
40V
LNB_SMAB34
C6908 0.1uF
30V
C6900
18pF
LNB
3.5A
D6904
LNB
D6902
LNB
LNB
2012.03.08
69
LGE Internal Use Only
LVDS
[51Pin LVDS OUTPUT Connector]
[41Pin LVDS OUTPUT Connector]
P7202
FI-RE41S-HF-J-R1500
LVDS
P7201
FI-RE51S-HF-J-R1500
LVDS
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
NC
OLED R7209
0
OLED R7208
0
NC
I2C_SDA1
UD_CPBOX R7201 0
3
I2C_SDA1
UD_CPBOX R7200 0
OLED : FRC_RESET = LVDS_VAL
INV_CTL = ELVDD_ON
I2C_SCL1
I2C_SCL1
NC
NC
1
2
FRC_RESET
NC
LVDS_SEL
R7204
0
OLED
4
5
6
UD
INV_CTL
7
R7217
0
8
FRC_FLASH_WP
NC
NC
R7213
0
ALEF
BPL_IN
9
10K
R7215
10
TXC0N
L/DIM_ENABLE
11
TXC0P
GND
12
TXC1N
RA0N
13
TXC1P
14
TXC2N
15
TXC2P
TXA0N/TX11N
RA0P
TXA0P/TX11P
RA1N
TXA1N/TX10N
16
RA1P
TXA1P/TX10P
17
TXCCLKN
18
RA2N
TXCCLKP
TXA2N/TX9N
RA2P
TXA2P/TX9P
19
GND
20
TXC3N
21
TXC3P
22
TXC4N
23
RACLKN
TXC4P
TXACLKN/TX8N
RACLKP
TXACLKP/TX8P
GND
RA3N
TXA3N/TX7N
24
RA3P
TXA3P/TX7P
25
RA4N
TXA4N/TX6N
26
TXA1N
TXD0N/TX17N
27
TXA1P
TXD0P/TX17P
28
TXACLKN
TXD1N/TX16N
29
TXACLKP
TXD1P/TX16P
30
TXA4N
TXD2N/TX15N
31
TXA4P
TXD2P/TX15P
33
TXB0N
TXDCLKN/TX14N
34
TXB0P
TXDCLKP/TX14P
36
TXB1N
TXD3N/TX13N
37
TXB1P
TXD3P/TX13P
38
TXB2N
TXD4N/TX12N
39
RA4P
TXB2P
TXD4P/TX12P
TXA4P/TX6P
GND
BIT_SEL
BIT_SEL
RB0N
TXB0N/TX5N
RB0P
TXB0P/TX5P
R7214
10K
LVDS_BIT_SEL_LOW
RB1N
TXB1N/TX4N
32
RB1P
TXB1P/TX4P
RB2N
TXB2N/TX3N
RB2P
TXB2P/TX3P
H13 BALL NAME
2
UD_OLED
R7210
33
NC
OLED
1
35
GND
RBCLKN
TXBCLKN/TX2N
RBCLKP
TXBCLKP/TX2P
GND
RB3N
TXB3N/TX1N
40
RB3P
TXB3P/TX1P
41
RB4N
TXB4N/TX0N
RB4P
42
TXB4P/TX0P
GND
PANEL_VCC
GND
GND
GND
L7201
120-ohm
LVDS
T_CON_SYS_POWER_OFF
GND
C7201
10uF
16V
OPT
NC
VLCD
C7203
0.1uF
16V
LVDS
VLCD
VLCD
VLCD
52
GND
R7216
100
T_CON_SYS_POWER_OFF
LED_R
OLED
VA7201
ADMC 5M 02 200L
OPT
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
Only for training and service purposes
C7204
0.1uF
OPT
BSD-NC4_H072-HD
2012-10-15
LVDS INTERFACE
LGE Internal Use Only
A5
B2
B3
3.3V_EMMC
B4
B5
47K
B6
NC_24
DAT2
NC_25
DAT3
NC_26
DAT4
NC_27
DAT5
NC_28
DAT6
NC_29
NC_30
R8116
10K
M6
A5
EMMC_DATA[3]
EMMC_DATA[4]
B2
EMMC_DATA[5]
B4
EMMC_DATA[6]
B5
EMMC_SERIAL_22
AR8101
22
1/16W
EMMC_DATA[7]
B6
NC_26
DAT2
NC_27
DAT3
NC_28
DAT4
NC_29
DAT5
NC_30
DAT6
NC_31
DAT7
B3
DAT1
NC_32
NC_33
NC_34
M6
CLK
NC_35
CMD
M5
NC_36
NC_37
NC_38
A6
C5
E5
E8
EMMC_SERIAL_22
22
E10
EMMC_CMD
F10
EMMC_RST
G3
G10
H5
OPT
J5
C8107
10pF
50V
K6
K7
K10
EMMC_SERIAL_100
AR8100-*1 AR8101-*1 AR8102-*1
100
100
100
1/16W
1/16W
1/16W
EMMC_SERIAL_100
EMMC_SERIAL_100
eMMC serial 100 ohm option
P7
P10
NC_39
NC_4
NC_40
NC_23
NC_41
NC_42
NC_46
NC_43
NC_47
NC_44
NC_48
NC_45
NC_49
NC_52
NC_50
NC_58
NC_51
NC_59
NC_53
NC_66
NC_54
NC_73
NC_55
NC_80
NC_56
NC_81
NC_57
NC_82
NC_60
NC_116
NC_61
NC_62
NC_63
NC_64
K5
RESET
OPT
C8100
0.1uF
16V
NC_65
NC_67
NC_68
C6
3.3V_EMMC
M4
3.3V_EMMC
N4
P3
EMMC_RESET_BALL
EMMC_CMD_BALL
EMMC_CLK_BALL
DAT6
DAT5
DAT4
DAT3
P5
VCCQ_1
VCCQ_2
VCCQ_3
VCCQ_4
VCCQ_5
C8105
0.1uF
16V
C8106
2.2uF
10V
E6
F5
J10
K9
VCC_1
VCC_2
VCC_3
VCC_4
EMMC_VDDI
C2
VDDI
C8104
1uF
10V
E7
G5
H10
K8
C8102
0.1uF
16V
C8103
2.2uF
10V
C4
VSS_1
VSS_2
VSS_3
VSS_4
NC_69
HYNIX_EMMC_4GB
AR8102
EMMC_CLK
E9
NC_3
NC_119
A7
NC_70
NC_71
NC_72
NC_74
NC_75
NC_76
NC_77
NC_78
NC_79
NC_83
NC_84
NC_85
NC_86
NC_87
NC_88
NC_89
NC_90
NC_91
NC_92
N5
P4
P6
VSSQ_1
NC_93
VSSQ_2
NC_94
VSSQ_3
NC_95
VSSQ_4
NC_96
VSSQ_5
N2
NC_97
NC_98
NC_99
DAT3
DAT4
A2
A8
A9
A10
A11
A12
A13
A14
B1
B7
B8
B9
B10
B11
B12
Don’t Connect Power At VDDI
B13
EMMC_VDDI
B14
C1
(Just Interal LDO Capacitor)
DAT5
NC_100
A1
C3
C7
NC_1
NC_101
NC_2
NC_102
NC_5
NC_103
NC_6
NC_104
NC_7
NC_105
NC_8
NC_106
NC_9
NC_107
NC_10
NC_108
NC_11
NC_109
NC_12
NC_110
NC_13
NC_111
NC_14
NC_112
NC_15
NC_113
NC_16
NC_114
NC_17
NC_115
NC_18
NC_117
NC_19
NC_118
NC_20
NC_120
NC_21
NC_121
NC_22
NC_24
NC_122
C9
E8
C10
E9
C11
E10
C12
F10
C13
G3
G10
C14
D1
D2
DAT5
H5
J5
D3
K6
D4
K7
K10
D12
D13
P7
D14
P10
E1
NC_37
RFU_2
NC_38
NC_21
NC_39
RFU_3
NC_40
RFU_4
NC_41
RFU_5
NC_42
RFU_6
NC_43
RFU_7
NC_44
RFU_8
NC_45
RFU_9
NC_46
RFU_10
NC_47
RFU_11
NC_48
RFU_12
NC_49
RFU_13
NC_50
RFU_14
NC_51
RFU_15
NC_52
NC_53
E2
K5
E3
RST_N
E12
E13
C6
E14
F1
F2
DAT6
M4
N4
P3
F3
P5
F12
VCCQ_1
VCCQ_2
VCCQ_3
VCCQ_4
VCCQ_5
F13
F14
G1
E6
G2
F5
G12
J10
G13
K9
VCC_1
VCC_2
VCC_3
VCC_4
G14
H1
C2
H2
VDDI
H3
H12
E7
H13
G5
H14
H10
J2
K8
J3
C4
J12
N2
N5
J13
EMMC_RESET_BALL
P4
P6
K1
K2
DU7
DU8
DUMMY_6
DUMMY_7
DUMMY_8
DUMMY_13
DUMMY_14
DUMMY_15
DUMMY_16
NC_70
NC_71
NC_72
NC_73
NC_74
NC_75
NC_82
NC_83
NC_84
NC_85
K12
K13
A2
L1
A8
NC_86
A1
K14
L2
A9
L3
A10
L12
A11
L13
A12
L14
A13
M1
A14
M2
B1
M3
B7
M7
B8
M8
B9
M9
B10
M10
B11
M11
B12
M12
B13
M13
B14
M14
C1
C3
N1
N3
EMMC_CMD_BALL
N6
C7
NC_1
NC_87
NC_2
NC_88
NC_3
NC_89
NC_4
NC_90
NC_5
NC_91
NC_6
NC_92
NC_7
NC_93
NC_8
NC_94
NC_9
NC_95
NC_10
NC_96
NC_11
NC_97
NC_12
NC_98
NC_13
NC_99
NC_14
NC_100
NC_15
NC_101
NC_16
NC_102
NC_17
NC_103
NC_18
NC_104
NC_19
NC_105
NC_20
NC_106
NC_22
A5
C11
B2
C12
B3
C13
B4
C14
B5
B6
D1
D2
NC_26
DAT2
NC_27
DAT3
NC_28
DAT4
NC_29
DAT5
NC_30
DAT6
NC_31
DAT7
C10
NC_25
DAT1
NC_32
NC_33
D3
D4
M6
D12
M5
NC_34
NC_35
CMD
D13
CLK
NC_36
NC_37
D14
NC_38
A6
E1
A7
E3
C5
E12
E5
E13
E8
E14
E9
E10
F1
F2
F10
F3
G3
F12
G10
F13
H5
F14
J5
G1
K6
G2
K7
K10
G12
G13
P7
G14
P10
H1
NC_39
NC_4
NC_40
NC_23
NC_41
NC_42
NC_46
NC_43
NC_47
NC_44
NC_48
NC_45
NC_49
NC_52
NC_50
NC_58
NC_51
NC_59
NC_53
NC_66
NC_54
NC_73
NC_55
NC_80
NC_56
NC_81
NC_57
NC_82
NC_60
NC_116
NC_61
NC_119
E2
NC_3
NC_62
H2
K5
H3
RESET
H12
H13
C6
H14
J1
M4
J2
N4
P3
J3
P5
J12
VCCQ_1
VCCQ_2
VCCQ_3
VCCQ_4
VCCQ_5
J13
J14
K1
E6
K2
F5
J10
K3
K9
K12
VCC_1
VCC_2
VCC_3
VCC_4
K13
K14
C2
L1
VDDI
L2
L3
E7
L12
L13
G5
L14
H10
K8
M1
M2
C4
M3
N2
VSS_1
VSS_2
VSS_3
VSS_4
NC_63
NC_64
NC_65
NC_67
NC_68
NC_69
NC_70
NC_71
NC_72
NC_74
NC_75
NC_76
NC_77
NC_78
NC_79
NC_83
NC_84
NC_85
NC_86
NC_87
NC_88
NC_89
NC_90
NC_91
NC_92
M8
P4
M9
P6
M10
NC_93
VSSQ_2
NC_94
VSSQ_3
NC_95
VSSQ_4
NC_96
VSSQ_5
N5
M7
VSSQ_1
NC_97
NC_98
M11
NC_99
M12
M13
A1
M14
A2
N1
A8
NC_100
NC_107
A9
N6
A10
N7
A11
N8
A12
N9
A13
N10
A14
N11
B1
N12
B7
N13
B8
N14
B9
P1
B10
P2
B11
P8
B12
P9
B13
P11
B14
P12
C1
P13
C3
P14
C7
NC_101
NC_2
NC_102
NC_5
NC_103
NC_6
NC_104
NC_7
NC_105
NC_8
NC_106
NC_9
NC_107
NC_10
NC_108
NC_11
NC_109
NC_12
NC_110
NC_13
NC_111
NC_14
NC_112
NC_15
NC_113
NC_16
NC_114
NC_17
NC_115
NC_18
NC_117
NC_19
NC_118
NC_20
NC_120
NC_21
NC_121
NC_22
NC_122
NC_24
N3
NC_1
A3
C9
A4
C12
C14
B6
D1
D2
NC_30
DAT6
B5
NC_29
DAT5
B4
NC_28
DAT4
B3
C13
NC_27
DAT3
B2
NC_31
NC_32
NC_33
D3
D4
M6
D12
NC_34
M5
CLK
CMD
D13
NC_35
NC_36
NC_37
D14
NC_38
A6
E1
E13
F2
F12
F14
G1
G13
P10
H1
NC_60
NC_116
P7
G14
NC_57
NC_82
K10
G12
NC_56
NC_81
K7
NC_55
NC_80
K6
G2
NC_54
NC_73
J5
NC_53
NC_66
H5
NC_51
NC_59
G10
F13
NC_50
NC_58
G3
NC_49
NC_52
F10
F3
NC_48
NC_45
E10
F1
NC_47
NC_44
E9
NC_46
NC_43
E8
E14
NC_41
NC_42
E5
NC_40
NC_23
C5
E12
NC_4
A7
E3
NC_39
NC_61
NC_119
E2
NC_3
NC_62
NC_63
H2
NC_64
K5
H3
RSTN
H12
H13
C6
H14
J1
M4
J2
VDD_1
N4
VDD_2
VDD_3
P3
J3
VDD_4
P5
J12
VDD_5
J13
J14
K1
E6
K2
F5
VDDF_1
VDDF_2
J10
K3
VDDF_3
K9
K12
VDDF_4
K13
K14
C2
L1
VDDI
L2
L3
C4
L12
L13
E7
L14
VSS_1
G5
VSS_2
VSS_3
H10
M1
NC_65
NC_67
NC_68
NC_69
NC_70
NC_71
NC_72
NC_74
NC_75
NC_76
NC_77
NC_78
NC_79
NC_83
NC_84
NC_85
NC_86
NC_87
NC_88
NC_89
NC_90
NC_91
VSS_5
M8
P4
M9
P6
M10
NC_95
VSS_8
N5
M7
NC_94
VSS_7
N2
NC_93
VSS_6
K8
M3
NC_92
NC_96
VSS_9
M2
VSS_4
NC_97
NC_98
M11
NC_99
M12
M13
A1
M14
A2
N1
NC_100
A8
NC_123
NC_2
N7
N9
N10
N12
N13
P1
P8
P9
P12
P13
NC_121
NC_22
C7
NC_120
NC_21
C3
P14
NC_118
NC_20
C1
NC_117
NC_19
B14
NC_115
NC_18
B13
P11
NC_114
NC_17
B12
NC_113
NC_16
B11
NC_112
NC_15
B10
P2
NC_111
NC_14
B9
NC_110
NC_13
B8
N14
NC_109
NC_12
B7
NC_108
NC_11
B1
NC_107
NC_10
A14
N11
NC_106
NC_9
A13
NC_105
NC_8
A12
NC_104
NC_7
A11
N8
NC_103
NC_6
A10
NC_102
NC_5
A9
N6
NC_101
NC_122
NC_24
N3
NC_1
NC_123
C9
C10
C11
C12
C13
C14
D1
A3
A5
C8
B2
B3
B4
B5
B6
DAT0
NC_23
DAT1
NC_24
DAT2
NC_25
DAT3
NC_26
DAT4
NC_27
DAT5
NC_28
DAT6
NC_29
DAT7
A4
NC_30
D2
D3
D4
D12
NC_31
NC_32
M6
CLK
NC_33
CMD
M5
NC_34
D13
D14
E1
E2
E3
E12
E13
E14
F1
F2
F3
F12
F13
F14
G1
G2
G12
G13
G14
NC_35
NC_36
A6
C5
E5
E8
E9
E10
F10
G3
G10
H5
J5
K6
K7
K10
P7
P10
NC_37
RFU_2
NC_38
NC_21
NC_39
RFU_3
NC_40
RFU_4
NC_41
RFU_5
NC_42
RFU_6
NC_43
RFU_7
NC_44
RFU_8
NC_45
RFU_9
NC_46
RFU_10
NC_47
RFU_11
NC_48
RFU_12
NC_49
RFU_13
NC_50
RFU_14
NC_51
RFU_15
NC_52
RFU_16
A7
RFU_1
NC_53
H1
NC_54
H2
NC_55
H3
K5
RSTN
H12
H13
H14
J1
J2
J3
J12
C6
M4
N4
P3
P5
VCCQ_1
VCCQ_2
VCCQ_3
VCCQ_4
VCCQ_5
J13
J14
K1
K2
K3
K12
E6
F5
J10
K9
VCC_1
VCC_2
VCC_3
VCC_4
K13
K14
L1
C2
VDDI
L2
L3
L12
L13
L14
M1
M2
M3
M7
M8
M9
E7
G5
H10
K8
C4
N2
N5
P4
P6
VSS_1
VSS_2
VSS_3
VSS_4
VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
M10
M11
M12
M13
M14
N1
N3
N6
N7
N8
N9
N10
N11
N12
N13
N14
P1
P2
P8
P9
P11
P12
P13
P14
A1
A2
A8
A9
A10
A11
A12
A13
A14
B1
B7
B8
B9
B10
B11
B12
B13
B14
C1
C3
C7
NC_1
NC_56
NC_57
NC_58
NC_59
NC_60
NC_61
NC_62
NC_63
NC_64
NC_65
NC_66
NC_67
NC_68
NC_69
NC_70
NC_71
NC_72
NC_73
NC_74
NC_75
NC_76
NC_77
NC_78
NC_79
NC_80
NC_81
NC_82
NC_83
NC_84
NC_85
NC_86
NC_87
NC_2
NC_88
NC_3
NC_89
NC_4
NC_90
NC_5
NC_91
NC_6
NC_92
NC_7
NC_93
NC_8
NC_94
NC_9
NC_95
NC_10
NC_96
NC_11
NC_97
NC_12
NC_98
NC_13
NC_99
NC_14
NC_100
NC_15
NC_101
NC_16
NC_102
NC_17
NC_103
NC_18
NC_104
NC_19
NC_105
NC_20
NC_106
NC_22
C9
C10
C11
C12
C13
C14
D1
D2
D3
D4
D12
D13
D14
E1
E2
E3
E12
E13
E14
F1
F2
F3
F12
F13
F14
G1
G2
G12
G13
G14
H1
H2
H3
H12
H13
H14
J1
J2
J3
J12
J13
J14
K1
K2
K3
K12
K13
K14
L1
L2
L3
L12
L13
L14
M1
M2
M3
M7
M8
M9
M10
M11
M12
M13
M14
NC_107
N1
N3
N6
N7
N8
N9
N10
N11
N12
N13
N14
P1
P2
P8
P9
P11
P12
P13
P14
N9
N10
N11
N12
N13
N14
P1
P2
P8
IC8100-*8
H26M42002GMR
IC8100-*5
KLM4G1FE3B-B001
EMMC_CLK_BALL
P9
A5
B2
B4
B5
B6
C8
DAT0
NC_25
DAT1
NC_26
DAT2
NC_27
DAT3
NC_28
DAT4
DAT5
DAT6
DAT7
P12
M6
M5
CLK
CMD
P13
A6
P14
A7
C5
E5
E8
NC_3
NC_4
NC_23
NC_42
NC_43
NC_44
NC_45
NC_52
NC_58
NC_59
NC_66
NC_73
NC_80
NC_81
NC_82
NC_116
K5
RSTN
DU10
C6
M4
DU11
N4
P3
P5
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
DU12
E6
F5
DU13
DU14
DU15
J10
K9
VDDF_1
VDDF_2
VDDF_3
VDDF_4
C2
VDDI
E7
G5
H10
DU16
IC8100-*7
KLMAG2GE4A-A001
A4
B3
P11
IC8100-*6
THGBM5G6A2JBAIR
A3
A3
A4
K8
C4
N2
N5
P4
VSS_2
VSS_3
VSS_4
VSS_5
VSS_1
VSS_6
VSS_7
VSS_8
VSS_9
A1
A2
A8
A9
A10
A11
A12
A13
A14
B1
B7
B8
B9
B10
B11
B12
B13
B14
C1
NC_1
NC_2
NC_5
NC_6
NC_7
NC_8
NC_29
NC_30
NC_31
NC_32
NC_33
NC_34
NC_35
NC_36
NC_37
NC_38
NC_39
NC_40
NC_41
NC_46
NC_47
NC_48
NC_49
NC_50
NC_51
NC_53
NC_54
NC_55
NC_56
NC_57
NC_60
NC_61
NC_62
NC_63
NC_64
NC_65
NC_67
NC_68
NC_69
NC_70
NC_71
NC_72
NC_74
NC_75
NC_76
NC_77
NC_78
NC_79
NC_83
NC_84
NC_85
NC_86
NC_87
NC_88
NC_89
NC_90
NC_91
NC_92
NC_93
NC_94
NC_95
NC_96
NC_97
NC_98
NC_99
NC_100
NC_101
NC_102
NC_103
NC_104
NC_105
NC_106
NC_9
NC_107
NC_10
NC_108
NC_11
NC_109
NC_12
NC_110
NC_13
NC_111
NC_14
NC_112
NC_15
NC_113
NC_16
NC_114
NC_17
NC_115
NC_18
NC_117
NC_19
NC_118
NC_20
NC_120
NC_21
NC_121
NC_22
NC_122
NC_24
C3
C7
NC_123
A3
C9
A4
C10
A5
C11
B2
C12
B3
C13
B4
C14
B5
D1
B6
C8
DAT0
NC_23
DAT1
NC_24
DAT2
NC_25
DAT3
NC_26
DAT4
DAT5
DAT6
DAT7
D2
D3
D4
M6
D12
M5
CLK
CMD
D13
D14
E1
A6
E2
A7
E3
C5
E12
E5
E13
E8
E14
E9
F1
E10
F2
F10
F3
F12
F13
G3
G10
H5
F14
J5
G1
K6
G2
G12
K7
K10
G13
P7
G14
P10
RFU_1
RFU_2
NC_21
RFU_3
RFU_4
RFU_5
RFU_6
RFU_7
RFU_8
RFU_9
RFU_10
RFU_11
RFU_12
RFU_13
RFU_14
RFU_15
RFU_16
H1
H2
H3
K5
RSTN
H12
H13
H14
C6
J1
M4
J2
N4
J3
P3
J12
P5
VCCQ_1
VCCQ_2
VCCQ_3
VCCQ_4
VCCQ_5
J13
J14
K1
E6
K2
F5
K3
J10
K12
K9
VCC_1
VCC_2
VCC_3
VCC_4
K13
K14
L1
C2
VDDI
L2
L3
L12
E7
L13
G5
L14
H10
M1
K8
M2
C4
M3
N2
M7
N5
M8
P4
M9
P6
VSS_1
VSS_2
VSS_3
VSS_4
VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
M10
M11
M12
M13
M14
A1
A2
N1
A8
N3
A9
N6
A10
N7
A11
N8
A12
N9
A13
N10
A14
N11
B1
N12
B7
N13
N14
P1
B8
B9
B10
P2
B11
P8
B12
P9
B13
P11
B14
P12
C1
P13
C3
P14
C7
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_27
NC_28
NC_29
NC_30
NC_31
NC_32
NC_33
NC_34
NC_35
NC_36
NC_37
NC_38
NC_39
NC_40
NC_41
NC_42
NC_43
NC_44
NC_45
NC_46
NC_47
NC_48
NC_49
NC_50
NC_51
NC_52
NC_53
NC_54
NC_55
NC_56
NC_57
NC_58
NC_59
NC_60
NC_61
NC_62
NC_63
NC_64
NC_65
NC_66
NC_67
NC_68
NC_69
NC_70
NC_71
NC_72
NC_73
NC_74
NC_75
NC_76
NC_77
NC_78
NC_79
NC_80
NC_81
NC_82
NC_83
NC_84
NC_85
NC_86
NC_87
NC_88
NC_89
NC_90
NC_91
NC_92
NC_7
NC_93
NC_8
NC_94
NC_9
NC_95
NC_10
NC_96
NC_11
NC_97
NC_12
NC_98
NC_13
NC_99
NC_14
NC_100
NC_15
NC_101
NC_16
NC_102
NC_17
NC_103
NC_18
NC_104
NC_19
NC_105
NC_20
NC_106
NC_22
A3
C9
A4
C10
A5
C11
B2
C12
B3
C13
B4
C14
B5
D1
B6
C8
DAT0
DAT1
DAT2
DAT3
DAT4
DAT5
DAT6
DAT7
D2
D3
D4
M6
D12
M5
CLK
CMD
D13
D14
E1
A6
E2
A7
E3
C5
E12
E5
E13
E8
E14
E9
F1
E10
F2
F10
F3
F12
F13
G3
G10
H5
F14
J5
G1
K6
G2
G12
K7
K10
G13
P7
G14
P10
RFU_1
RFU_2
RFU_3
RFU_4
RFU_5
RFU_6
NC_39
RFU_7
RFU_8
RFU_9
RFU_10
RFU_11
RFU_12
RFU_13
RFU_14
RFU_15
NC_104
H1
H2
H3
K5
RESET
H12
H13
H14
C6
J1
M4
J2
N4
J3
P3
J12
P5
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
J13
J14
K1
E6
K2
F5
K3
J10
K12
K9
VDDF_1
VDDF_2
VDDF_3
VDDF_4
K13
K14
L1
C2
VDDI
L2
L3
L12
E7
L13
G5
L14
H10
M1
K8
M2
C4
M3
N2
M7
N5
M8
P4
M9
P6
VSS_2
VSS_3
VSS_4
VSS_9
VSS_1
VSS_5
VSS_6
VSS_7
VSS_8
M10
M11
M12
M13
M14
A1
A2
N1
A8
N3
A9
N6
A10
N7
A11
N8
A12
N9
A13
N10
A14
N11
B1
N12
B7
N13
N14
P1
B8
B9
B10
P2
B11
P8
B12
P9
B13
P11
B14
P12
C1
NC_107
NC_1
NC_2
NC_3
NC_4
NC_22
NC_23
NC_24
NC_25
NC_26
NC_27
NC_28
NC_29
NC_30
NC_31
NC_32
NC_33
NC_34
NC_35
NC_36
NC_37
NC_38
NC_40
NC_41
NC_42
NC_43
NC_44
NC_45
NC_46
NC_47
NC_48
NC_49
NC_50
NC_51
NC_52
NC_53
NC_54
NC_55
NC_56
NC_57
NC_58
NC_59
NC_60
NC_61
NC_62
NC_63
NC_64
NC_65
NC_66
NC_67
NC_68
NC_69
NC_70
NC_71
NC_72
NC_73
NC_74
NC_75
NC_76
NC_77
NC_78
NC_79
NC_80
NC_81
NC_82
NC_83
NC_84
NC_85
NC_86
NC_87
NC_88
NC_89
NC_90
NC_5
NC_91
NC_6
NC_92
NC_7
NC_93
NC_8
NC_94
NC_9
NC_95
NC_10
NC_96
NC_11
NC_97
NC_12
NC_98
NC_13
NC_99
NC_14
NC_100
NC_15
NC_101
NC_16
NC_102
NC_17
NC_103
NC_18
RFU_16
C3
C7
NC_19
NC_105
NC_20
NC_106
NC_21
P13
P14
C9
A5
C10
B2
C11
B3
C12
C13
C14
B4
B5
B6
D1
CMD
D13
E1
E2
E3
A6
A7
E12
C5
E13
E5
E14
F1
E8
E9
F2
F3
F12
E10
F10
F13
G3
F14
G10
G1
G2
H5
J5
G12
G13
G14
H1
K6
K7
K10
H2
P7
H3
P10
DU4
DU5
DU6
DU7
DU8
DUMMY_1
DUMMY_9
DUMMY_2
DUMMY_10
DUMMY_11
DUMMY_4
DUMMY_12
DUMMY_5
DUMMY_13
DUMMY_6
DUMMY_14
DUMMY_7
DUMMY_15
DUMMY_8
DUMMY_16
NC_3
NC_4
NC_23
NC_42
NC_43
NC_44
NC_45
NC_52
NC_58
NC_59
NC_66
NC_73
NC_80
NC_81
NC_82
NC_116
NC_119
H12
H13
H14
J1
K5
RESET
J2
J3
J12
J13
C6
M4
J14
K1
N4
K2
P3
K3
P5
VCCQ_1
VCCQ_2
VCCQ_3
VCCQ_4
VCCQ_5
K12
K13
K14
E6
L1
L2
L3
L12
F5
J10
K9
VCC_1
VCC_2
VCC_3
VCC_4
L13
L14
M1
C2
M2
VDDI
M3
M7
M8
M9
M10
M11
E7
G5
H10
K8
M12
M13
M14
C4
N2
N1
N5
N3
P4
N6
P6
VSS_1
VSS_2
VSS_3
NC_28
NC_29
NC_30
NC_31
NC_32
NC_33
NC_34
NC_35
NC_36
NC_37
NC_38
NC_39
NC_40
NC_41
NC_46
NC_47
NC_48
NC_49
NC_50
NC_51
NC_53
NC_54
NC_55
NC_56
NC_57
NC_60
NC_61
NC_62
NC_63
NC_64
NC_65
NC_67
NC_68
NC_69
NC_70
NC_71
NC_72
NC_74
NC_75
NC_76
NC_77
NC_78
NC_79
NC_83
NC_84
NC_85
NC_86
NC_87
NC_88
NC_89
NC_90
NC_91
VSS_4
NC_92
VSSQ_1
NC_93
VSSQ_2
NC_94
VSSQ_3
NC_95
VSSQ_4
NC_96
VSSQ_5
N7
NC_97
N8
NC_98
N9
NC_99
N10
N11
A2
NC_100
A1
N12
N13
N14
A8
A9
P1
P2
P8
A10
A11
P9
A12
P11
A13
P12
P13
A14
B1
P14
B7
DU9
DUMMY_3
CLK
D14
B9
DU2
DAT5
DAT6
M6
M5
B10
DU3
NC_26
NC_27
DAT3
DAT4
D3
D4
NC_25
DAT1
DAT2
DAT7
D12
NC_107
DU1
C8
DAT0
D2
B8
Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
Only for training and service purposes
DAT2
A5
C11
NC_26
DAT7
C10
NC_25
DAT1
N8
P6
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
C8
DAT0
N7
DU9
DUMMY_5
NC_69
VSSQ_4
NC_119
DU6
NC_68
NC_81
P7
DU5
NC_67
VSSQ_3
P10
DUMMY_12
NC_66
NC_80
K7
DUMMY_4
NC_65
VSSQ_2
K10
DUMMY_11
NC_64
NC_79
H5
DUMMY_3
NC_63
VSSQ_1
J5
DU4
NC_62
NC_78
K6
DU3
NC_61
VSS_4
G3
DUMMY_10
NC_60
NC_77
G10
DUMMY_2
NC_59
VSS_3
E9
DU2
NC_58
NC_76
E10
DUMMY_9
NC_57
VSS_2
F10
DUMMY_1
NC_56
K3
NC_123
DU1
NC_55
VSSQ_5
J1
J14
VSS_1
NC_54
C8
DAT0
HYNIX_EMMC_8GB
A4
EMMC_DATA[2]
RFU_1
A4
SAMSUNG_EMMC_16G
EMMC_DATA[1]
E5
C8
NC_25
NC_36
RFU_16
C5
DAT0
NC_34
A6
A7
EMMC_DATA[0]
NC_33
NC_35
IC8100
H26M31002GPR
A3
CLK
CMD
M5
TOSHIBA_EMMC_4GB
R8117
10K
10K
R8107
10K
10K
10K
R8104
R8106
R8105
10K
10K
10K
10K
R8103
R8102
EMMC DATA LINE
10K PULL/UP
FOR M13
NC_32
SAMSUNG_EMMC_4GB
EMMC_DATA[0-7]
R8100
EMMC_SERIAL_22
AR8100
22
1/16W
R8101
R8107-*1
R8104-*1
R8106-*1
R8105-*1
R8103-*1
R8102-*1
R8101-*1
R8100-*1
NC_31
A3
C9
TOSHIBA_EMMC_8GB
47K
47K
47K
47K
47K
47K
EMMC DATA LINE 47K PULL/UP
NC_23
DAT1
IC8100-*4
THGBM5G7A2JBAIR
IC8100-*3
KLM2G1HE3F-B001
TOSHIBA_EMMC_16GB
eMMC I/F
47K
C8
DAT0
DAT7
A4
HYNIX_EMMC_2GB
A3
IC8100-*2
H26M21001ECR
SAMSUNG_EMMC_2GB
IC8100-*1
THGBM5G5A1JBAIR
DU10
B11
B12
DU11
DU12
B13
DU13
B14
DU14
C1
DU15
C3
DU16
C7
NC_1
NC_101
NC_2
NC_102
NC_5
NC_103
NC_6
NC_104
NC_7
NC_105
NC_8
NC_106
NC_9
NC_107
NC_10
NC_108
NC_11
NC_109
NC_12
NC_110
NC_13
NC_111
NC_14
NC_112
NC_15
NC_113
NC_16
NC_114
NC_17
NC_115
NC_18
NC_117
NC_19
NC_118
NC_20
NC_120
NC_21
NC_121
NC_22
NC_122
NC_24
C9
C10
C11
C12
C13
C14
D1
D2
D3
D4
D12
D13
D14
E1
E2
E3
E12
E13
E14
F1
F2
F3
F12
F13
F14
G1
G2
G12
G13
G14
H1
H2
H3
H12
H13
H14
J1
J2
J3
J12
J13
J14
K1
K2
K3
K12
K13
K14
L1
L2
L3
L12
L13
L14
M1
M2
M3
M7
M8
M9
M10
M11
M12
M13
M14
N1
N3
N6
N7
N8
N9
N10
N11
N12
N13
N14
P1
P2
P8
P9
P11
P12
NC_123
P13
P14
eMMC
11.09.29
81
LGE Internal Use Only
OLED vs. LED
OLED is next generation display which is simple, thin and light. OLED can achieve natural and vivid colors due to self-emitting
characteristics
OLED
LCD
Polarizing plate
BLU
+Prism
+Diffuser
TFT
Cell
CF Polarizing plate
Indirect light source display, which is
complex and consists of many
components.
Light is supplied from BLU and goes
through many layers
Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
Only for training and service purposes
TFT & OLED
Polarizing plate
Simple structure with not many
components (without BLU) Paper
slim & light
Self-emitting display
Better response time / contrast
ratio compared to LCD
LGE Internal Use Only
Main PCB for Broadband
55EA9800
Clear S
Cl
Speaker
k
CAM USB
Local Dim.
To PSU
Module
1
1
Main processor_Digital(LG1152D),
DDR Memory
Flash Memory
2
wifi
Motion assy
IR + Digital Eye
Front Spk
3
Micom for Key/IR sensing
4
2
3
Main processor_analog(LG1152A)
Audio AMP (Max 12W)
5
HDMI switch (4:1)
5
4
Local Key
Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
H13 Block diagram
DIF(P/N)
CVBS
Tuner
M-Remote_Rx/Tx
SIF
AUD
Motion-R
SPDIF
BB_TP_DATA
OPTIC
LNB
SC_CVBS, RGB, Audio L/R
SCART
DTV/MNT_LR/V_OUT
H13
LG1154A
H13
LG1154D
DAC_DATA
H/P Audio L/R
I2S
AV1_CVBS
AV1_Audio L/R
AV1
IR_B
Micom
H/P AMP
IR_Blaster
H/P
AAD_DATA
PC_Audio_L/R
PC_AUDIO
IRB_SPI
CVBS
HSR_P/M
Audio
A di
AMP
SPK/
Clear Speaker
Comp1 Y,Pb,Pr
COMP1
CI
CI
HDMI
Switch
HDMI1~4
HDMI_CEC
HDMI CEC
OLED Module
Logo Light
WOL / WOW
LAN
RMII
PHY
FRC
TCON
LVDS : Quad
USB 2.0
USB_W-iFi
USB 3.0
USB1(USB3.0)
USB 2.0
USB2(USB2.0)
USB3(USB2.0)
USB_CAM
USB
HUB
USB 2.0
16
DDR3
16
16
DDR3
DDR3
16
DDR3
8
eMMC
4Gb×4 (1600)
Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
H13 Block diagram
DVB-CI/CI+
I2S(External)
Audio DAC
(48KHz )
Video Encoder
TrustZone
Clear Voice II
I2S
Perceptual
Volume Control
HDMI
I2Cx1
GPIOIx16
Audio PLL
w/ DCO
HDMI
(1-Link)
SCI
USB3.0 x1
eMMC
DMAC(8ch)
Timer
WDT
SRAM 16KB
BE
TCO
ON
LED
PE
E1
OS
SD
CPLL
HDMI-Rx 1.4
(1-port PHY)
3D, ARC, 4kx2k
DDR3 Controller
16
DDR3 Controller
DDR3 PHY
Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
Only for training and service purposes
EMAC
MCU
H3D
LVDS
Rx
UART
Output fo
ormatter
I2Cx1
LVDS
Tx
GPIOx136
Timer
DE
Main/Sub Scaler
b
10x3ch
Capture
Block
(3CH)
OTP
32KBD$
MCU
TNR
3ch Video
AFE
10b@148.5MHz
w/ LLPLL
Mux
SW
SW
CVBS AFE(2-ch)
12b@54MHz
CVBS
Encoder
CVD
Y/C
CVBS
48KB ROM
64KB SRAM
1MB L2 $
Bluetooth
De-inte
erlacer
5x1ch (1ch)
CVBS DAC
DivX
Source Mux
e
SPDIF
Digital
Audio
Output
Mux
Digital AMP
Secure Engine
CPU
ARMCA9 Core
Dual 1.2GHz
32KBI$
UARTx3
UART 3
I2Cx10
CPU
I2S
USB2.0x3
SPIx2
1080p@30fps
Slim SPK
Component(2ch)
JPG/PNG Decoder
JPG Encoder
Multi-STD
Audio Decoder
LX4 HiFi EP
Audio
Sound DSP
I2S(HPD)
CVBS-Out
2D GFX
I2S
Audio DAC (48KHz)
CVBS(3ch)
GPU Rogue Han
Audio DSP
SR
RE
VC
CR
Line Out
AAD
(THAT)
1ch L/R
Audio-ADC
24b@48KHz
Video Decoder
Multi STD
Multi-STD
HD Decoder
(Boda950)
FR
RC
SCART out
SW
Audio L/R(4-ch)
BTSC AFE
10b@18.432MHz
w/ PLL
SW
SIF
Mux
Tuner
H13D
TS(S)
TS(S)
System
Demux
D
TS (P)
Global Baseband
V/Q, DVB-T/C ISDB-T
TS(P)
DDR3 PHY
16
PHY
GBB AFE
1ch@30MHz
w/ PLL
DIF
TS(P)
SDRAM
(MCP)
Vx1/
/EPI/LVDS Combo
(120Hz)
H13A
16
DCO
x2
SPLL
DPLL
DDR
PLL
DDR
PLL
16
LGE Internal Use Only
H13 Block diagram
Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
H13 Block diagram
[+3.3V_S2_DEMOD] 32
+3.3V_D_Demod
+3.3V_TU
+1.8_TU
+1.23V_D_Demod
+3.3V_NORMAL
[+3.3V_TUNER] 5
[+.1.8V_TUNER] 7
[+1.23V_S2_DEMOD] 30
[S2_F22_OUTPUT] 33
[LNB] 36
3.3K
3 3K Ω
LNB_TX
10 [TONECTRL]
LNB_OUT
2 [LNB]
[S2_SCL] 34
[S2_SDA] 35
22 Ω
I2C_SCL4
I2C_SDA4
33 Ω
TU6503
TDSQ-H651F
[RESET] 2
[T/C_DIF[N]] 11
[SLC] 3
[SDA] 4
[ERROR] 16
[SYNC] 17
[VALID] 18
[MCLK] 19
[D0] 20
[D1] 21
[D2] 22
[D3] 23
[D4] 24
[D5] 25
[D6] 26
[D7] 27
[S2_RESET] 31
/TU_RESET1
AH33 [SDA5]
AM35 [TP_DVB_DATA0]
AN36 [TP_DVB_DATA1]
AN37 [TP_DVB_DATA2]
AN35 [TP_DVB_DATA3]
AP37 [TP_DVB_DATA4]
AP36 [TP_DVB_DATA5]
AR37 [TP_DVB_DATA6]
AR37 [TP_DVB_DATA7]
[TP DVB DATA7]
FE_DEMOD1_TS_DATA [0-7]
/S2_RESET
AG5 [GPIO9]
IF_P
TUNER_SIF
TU_CVBS
H13
LG1154D
AL37 [TP_DVB_ERR]
AL36 [TP_DVB_SOP]
AL35 [TP_DVB_VAL]
AM36 [TP_DVB_CLK]
FE_DEMOD1_TS_ERROR
FE_DEMOD1_TS_SYNC
FE_DEMOD1_TS_VAL
FE_DEMOD1_TS_CLK
[T/C_DIF[N]] 11
AP6 [SCL3]
AR6 [SDA3]
AH34 [SCL5]
IC2_SDA6
IC2 SDA6
IF_N
8 [SDA]
LNB
IC6900
A8303SESTR-TB
AG6 [GPIO10]
IC2_SCL6
[T/C_DIF[P]] 10
7 [SCL]
ADC_I_INP
FILTER
ADC_I_INN
U17 [ADC_I_INP]
V17 [ADC_I_INN]
H13
LG1154A
IF_AGC
Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
H13 Block diagram
Jack Side
AV1
Phone JACK
AV1_CVBS_IN
SOC Side
AV1_CVBS_IN_SOC
[CVBS_IN3]
[CVBS IN3]
AV_L/R_IN
AUAD_L/R_CH2_IN
[AUAD_L/R_CH2_IN]
FULL
SCART
(18P)
SC_CVBS_IN
SC_CVBS_IN_SOC
[CVBS_IN2]
[CVBS IN2]
SC_R/G/B
/CVBS_IN_SOY
[PR1/Y1/PB1/SOY1_IN]
COMP1_PR_IN_SOC
COMP1_Y_IN_SOC
COMP1_PB_IN_SOC
COMP1 PB IN SOC
COMP1_Y_IN_SOC_SOY
SC_L/R_IN
H13
(LG1154A)
AUAD_L/R_CH3_IN
[AUAD_L/R_CH3_IN]
Component 1
Phone JACK
COMP1_Y/Pb/Pr
[PB2/Y2/SOY2/PR2_IN]
COMP2_PB_IN_SOC
COMP2_Y_IN_SOC
COMP2_Y_IN_SOC_SOY
COMP2_PR_IN_SOC
Tuner
TU_CVBS_IN
SIF
DIF[P/N]
Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
Only for training and service purposes
TU_CVBS_IN_SOC
TUNER_SIF
ADC_I_INP/INN
[CVBS_IN1]
[AAD_ADC_SIF]
[
[ADC_I_INP/INN]
]
LGE Internal Use Only
H13 Block diagram
MICOM
SC_L/R_IN
[AUAD_L_CH3_IN]
[AUD_SCART_OUTL/OUTR]
AV_L/R_IN
SC
CART_MUTE
Mute
CTRL
[TR]
[
[AUAD_L_CH1_IN]
]
SCART_Lout/Rout
[AUAD_L_CH2_IN]
[
[DACSCK]
]
[DACLRCK]
[DACLRCH]
AZ4580MTR
OP AMP
DTV/MNT_L/R_OUT
pi filter
MAIN
AUD_SCK/LRCK/LRCH
[SCL0/SDA0]
AUDIO L/R OUT
4P wafer
TAS5733
I2C_SCL1/SDA1
SCART
[GPIO21]
LPF
LPF
AMP_RESET_N
H13
LG1154
WOOFER
2P wafer
TAS5733
LPF
LPF
Tuner
AMP_MUTE
MICOM
TUNER_SIF
TUNER SIF
SIDE_HP_MUTE
_ _
[AAD_ADC_SIF]
[AUDA_OUTL]
[PHY0_ARC_OUT_0]
HP_L/ROUT_MAIN
[IEC958OUT]
TPA6138A2
Headphone
AMP
LPF
HEAD PHONE
& line out
SPDIF_OUT
SPDIF_OUT_ARC
Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
H13 Block diagram
HDMI1
SPDIF_OUT_ARC
TMDS Link 8bits
CEC_REMOTE
HDMI_S/W_RESET
HDMI S/W RESET
DDC_I2C 2bits
HDMI_INT
SPDIF_OUT_ARC
H13
LG1154D
HDMI
Switch
(IC3201 / SII9587CNUC)
HDMI2
TMDS Link 8bits
CEC_REMOTE
HDMI Out put 8bits
DDC_I2C 2bit
DDC I2C 2bits
I2C_SCL/SDA 5 2bits
HDMI3
TMDS Link 8bits
CEC_REMOTE
CEC_REMOTE
DDC_I2C 2bits
MICOM
(IC3000 /
R5F100GEAFB)
HDMI4
TMDS Link 8bits
DDC_I2C 2bits
OCP
(IC3202 /
TPS2051)
Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
Only for training and service purposes
CEC_REMOTE
MHL_DET
LGE Internal Use Only
H13 Block diagram
USB_CAMERA_DP
USB CAMERA DP / DM
USB2_HUB_IC_IN_DP / DM
[USB2_2_DP0 / DM0]
USB HUB
USB2512B-AEZG
USB_Camera
(구주7600 - Ready)
USB_DP3 / DM3
USB_CTL3
USB_CTL2
_
[EB_CS2/GPIO92]
OCP USB2/3
TPS2062C
USB3
USB2_ DP2 / DM2
[USB3_DP0/DM0]
[USB3_RX0P / M]
[USB3_TX0P / M]
[HUB_VBUS_CTRL0]
[HUB_PORT_OVER0/1]
[UART1_RXD / TXD]
[GPIO15 / GPIO18]
[GPIO13]
MICOM
(R5F100GEAFB)
+5V_USB3
+5V_USB2
+5V USB2
USB2
[USB2_1_DP0 / DM0]
[USB2_0_DP / DM]
CAM_DET
CAM DET
WIFI_DP / DM
USB_WIFI
USB3_DP / DM
WOL/WOW_POWER_ON
USB1
(USB3.0, PVR Ready)
USB3_RX0P/RX0M
USB3_TX0P/TX0M
USB_CTL2
OCP USB1
TPS2554
/USB_OCD1
/USB OCD1
+5V_USB1
M_REMOTE_RX / TX
Motion Remote
M_REMOTE_CTS / RTS
Receiver
M_REMOTE_RESET
H13
LG1154D
[UART0_RXD]
[UART0_TXD]
SOC_TX
SOC_RX
MICOM
(R5F100GEAFB)
SOC_TX
SOC_RX
4Pin debugging
Wafer
P3800
Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
Interconnection - 1
55EA9800
[PCBs]
1
5
Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
Only for training and service purposes
3
PSU
WIFI ASSY
BT MOTION ASSY
5
4
2
4
1
Main PCB
3
2
IR PCB
6
Touch Key / Logo
6
LGE Internal Use Only
Contents of LCD TV Standard Repair Process
No.
Error symptom (High category)
Error symptom (Mid category)
Page
1
No video/Normal audio
1
2
No video/No audio
2
Picture broken/ Freezing
3
4
Color error
4
5
Vertical/Horizontal bar residual image
bar,
image,
light spot, external device color error
5
6
No power
6
Off when on, off while viewing, power
h
ff hil i i
auto on/off
7
No audio/Normal video
8
9
Wrecked audio/discontinuation/noise
9
10
Remote control & Local switch checking
10
11
MR13 operating checking
i
h ki
11
Wifi operating checking
12
13
Camera operating checking
13
14
External device recognition error
Remarks
14
3
A. Video error
B.
B Power error
7
8
C. Audio error
12
D. Function error
15
E. Noise
Circuit noise, mechanical noise
15
16
F. Exterior error
Exterior defect
16
First of all, Check whether there is SVC Bulletin in GCSC System for these model.
Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
Standard Repair Process
A. Video error
LCD TV
Established
date
No video/ Normal audio
Error
symptom
Revised date
2013.01.31
1/16
First of all, Check whether all of cables between board is inserted properly or not.
(Main B/D↔ Power B/D, EPI Cable,Speaker Cable,IR B/D Cable,,,)
☞A1
No video
Normal audio
Normal
audio
Y
☞A18
Check OLED Light
On with naked eye
N
Move to No
video/No audio
Y
On
Check Power
Board
24V, 12V,3.5V etc.
N
☞A18
Y
Replace T-con
Board or module
And Adjust VCOM
N
Repair Power
Board or parts
Check Power Board 24V output
Normal
voltage
Normal
voltage
Y
Replace Inverter
or module
End
N
Repair Power
Board or parts
※Precaution
☞A4 & A2
Always check & record S/W Version and White
Balance value before replacing the Main Board
Replace Main Board
Re-enter White Balance value
1
Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
Standard Repair Process
LCD TV
A. Video error
Established
date
No video/ No audio
Error
symptom
Revised date
2013.01.31
2/16
☞A18
No Video/
No audio
Check various
voltages of Power
Board ( 3.5V,12V,20V
or 24V…)
Normal
voltage?
Y
N
Check and
replace
MAIN B/D
End
Replace Power
Board and repair
parts
2
Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
Standard Repair Process
LCD TV
☞ A3
Check RF Signal level
Normal
Signal?
A. Video error
Y
Established
date
Picture broken/ Freezing
Error
symptom
Revised date
2013.01.31
3/16
. By using Digital signal level meter
. By using Diagnostics menu on OSD
( Setting→ Set up→ Manual Tuning → Check the Signal )
- Signal strength (Normal : over 50%)
- Signal Quality (Normal: over 50%)
Check whether other equipments have problem or not.
(By connecting RF Cable at other equipment)
,Set Top Box,
etc
→ DVD Player ,Set-Top-Box, Different maker TV etc`
N
☞ A4
Check RF Cable
Connection
1. Reconnection
2. Install Booster
Normal
Picture?
Y
Check
S/W Version
N
N
Y
Check
Tuner soldering
T
ld i
Close
N
Y
N
Normal
Picture?
SVC
Bulletin?
S/W Upgrade
Contact with signal distributor
or broadcaster (Cable or Air)
Normal
Picture?
Y
N
Replace
Main B/D
Y
Close
Close
3
Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
Standard Repair Process
LCD TV
A. Video error
Revised date
Color
error?
N
Y
※ Check
and replace
Link Cable
(EPI) and
contact
condition
Check Test tt
Ch k T t pattern
4/16
Y
Color
error?
Y
Color
error?
Replace Main B/D
Replace module
N
N
End
Check error
color input
mode
☞A8
2013.01.31
☞ A7
☞A6
Check color by input
-External Input
-COMPONENT
COMPONENT
-AV
-HDMI
Established
date
Color error
Error
symptom
External Input/
Component
C
t
error
Check
external
device and
cable
External device Y
/Cable
/C bl
normal
Replace M i B/D
R l
Main
N
Request repair
for external
device/cable
N
HDMI
error
Check external
device and
cable
External device Y
/Cable
normal
Replace Main B/D
4
Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
Standard Repair Process
LCD TV
A. Video error
Established
date
Vertical / Horizontal bar, residual image,
light spot, external device color error
Error
symptom
Revised date
2013.01.31
5/16
Vertical/Horizontal bar, residual image, light spot
Replace
Module
☞A6
☞ A7
Check color condition by input
-External Input
-Component
-HDMI
HDMI
Screen Y
normal?
Check external
device
connection
condition
Normal?
Check and
replace Link
Cable
N
N
Check Test pattern
Screen N
normal?
Y
Request repair
for external
device
Replace
module
☞A8
A8
Y
N
End
Replace Main B/D
(adjust VCOM)
Screen
normal?
For LGD panel
Y
Replace Main B/D
End
For other panel
External device screen error-Color error
Check S/W Version
Check N
version
Y
External
Input
error
Component
error
S/W Upgrade
Normal
screen?
Check screen
condition by input
-External Input
-Component
-HDMI/DVI
HDMI/
DVI
N
Y
End
Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
Only for training and service purposes
Connect other external
device and cable
(Check normal operation of
External Input, Component,
RGB and HDMI/DVI by
connecting Jig, pattern
Generator ,Set-top Box etc.
Connect other external
device and cable
(Check normal operation of
External Input, Component,
E t
lI
t C
t
RGB and HDMI/DVI by
connecting Jig, pattern
Generator ,Set-top Box etc.
Screen
normal?
N
Replace
Main B/D
Y
Request repair for
external device
Y
Screen
normal?
N
Replace
Main B/D
5
LGE Internal Use Only
Standard Repair Process
LCD TV
B. Power error
Established
date
No power
Error
symptom
Revised date
☞A17
Check
Logo LED
2013.01.31
6/16
☞A18
DC Power on
by pressing Power Key
On Remote control
Y
Power LED
On?
. Stand-By: Red or Turn Off
N
. Operating: Turn Off
Normal N
operation?
Check Power
On ‘”High”
OK?
Y
Replace
R l
Power
B/D
Y
Check Power cord
was inserted properly
Replace Main B/D
☞A18
Normal?
Measure voltage of each output of Power B/D
N
Y
Close
Y
※
Check ST-BY 3.5V
Normal
Y
voltage?
☞A18
Normal
voltage?
g
Y
Replace Main B/D
N
Replace Power B/D
N
Replace Power
B/D
6
Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
Standard Repair Process
LCD TV
B. Power error
Established
date
Off when on off while viewing, power auto on/off
on,
viewing
Error
symptom
Revised date
2013.01.31
7/16
Check outlet
☞A19
Check A/C cord
Error?
N
Check Power Off
Mode
CPU
Abnormal
Normal?
Replace Main B/D
Y
End
N
Check for all 3- phase
power out
Y
Abnormal
1
☞A18
Fix A/C cord & Outlet
and check each 3
phase out
(If Power Off mode
is not displayed)
Check Power B/D
voltage
※ Caution
Check d fi
Ch k and fix exterior
i
of Power B/D Part
* Please refer to the all cases which
can be displayed on power off mode.
Replace Power B/D
Normal
voltage?
Y
Replace Main B/D
N
Replace Power B/D
Status
Power off List
" POWEROFF_REMOTEKEY "
" POWEROFF REMOTEKEY "
" POWEROFF_OFFTIMER "
" POWEROFF_SLEEPTIMER "
" POWEROFF_INSTOP "
" POWEROFF_AUTOOFF "
Normal " POWEROFF ONTIMER "
N
l " POWEROFF_ONTIMER "
" POWEROFF_20V_DET "
" POWEROFF_RESREC "
" POWEROFF_RECEND "
" POWEROFF_SWDOWN "
" POWEROFF_UNKNOWN "
" POWEROFF UNKNOWN "
" POWEROFF_ABNORMAL1 "
Abnormal
" POWEROFF_CPUABNORMAL "
Power
P
Power
Power
Power
Power
Power
P
Power
Power
Power
Power
Power
P
Power
Power
off
ff
off
off
off
off
off
ff
off
off
off
off
off
ff
off
off
Explanation
b REMOTE CONTROL
by
by OFF TIMER
by SLEEP TIMER
by INSTOP KEY
by AUTO OFF
b ON TIMER
by
by AC OFF
by Reservated Record
by End of Recording
by S/W Download
b unknown status except li t d case
by k
t t
t listed
by abnormal status except CPU trouble
by CPU Abnormal
7
Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
Standard Repair Process
LCD TV
Error
symptom
C. Audio error
Established
date
No audio/ Normal video
Revised date
☞A20
No audio
Screen normal
Check user
menu & gt;
Speaker off
2013.01.31
8/16
☞A21+A18
Off
N
Check audio B+ 24
of Power Board
Normal
voltage
Y
N
Cancel OFF
Check
Speaker
disconnection
Y
Replace Power Board and repair parts
Disconnection
N
Replace MAIN Board
End
Y
Replace Speaker
8
Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
Standard Repair Process
LCD TV
Error
symptom
C. Audio error
Established
date
Wrecked audio/ discontinuation/noise
Revised date
2013.01.31
9/16
→ abnormal audio/discontinuation/noise is same after “Check input signal” compared to No audio
Check input
signal
-RF
-External Input
signal
Wrecked audio/
Discontinuation/
Noise for
all audio
Signal
normal?
☞A21+A18
Check and replace
speaker and
connector
Check audio
B+ Voltage (24V)
Y
Y
Wrecked audio/
Discontinuation/
Noise only
for D-TV
N
N
Wrecked audio/
Discontinuation/
Noise only
for Analog
(When RF signal is not
received)
Request repair to external
cable/ANT provider
(In case of
External Input
signal error)
Check and fix
external device
Normal
voltage?
Replace Main B/D
Replace Power B/D
Replace Main B/D
Wrecked audio/
Discontinuation/
Noise only
for External Input
Connect and check
other external
device
Normal
audio?
End
N
Y
Check and fix external device
9
Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
Standard Repair Process
D. Function error
Error
symptom
LCD TV
Established
date
Remote control & Local switch checking
2013.01.31
Revised date
10/16
1. Remote control(R/C) operating error
☞A22
Check R/C itself
Operation
☞A22
Check & Repair
Cable connection
Connector solder
Normal Y
operating?
N
Normal
operating?
N
Y
Check R/C Operating
When turn off light
in room
Y
Normal
operating?
Check B+
3.5V
On Main B/D
☞A18
Close
Check & Replace
Baterry of R/C
If R/C operate,
Explain the customer
cause is interference
from light in room.
Replace
Main B/D
Normal
Voltage?
Y
☞A22
A22
Check IR
Output signal
N
Check 3.5v on Power B/D
Replace Power B/D or
Replace Main B/D
(Power B/D don’t have problem)
Normal
Signal?
Y
N
Repair/Replace
IR B/D
Close
N
Replace R/C
10
Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
Standard Repair Process
D. Function error
Error
symptom
LCD TV
Established
date
MR13/P operating checking
2013.01.31
Revised date
11/16
2. MR13/P (Magic Remocon) operating error
☞A4
Check the
INSTART menu
RF Receiver ver
is “00.00”?
N
Check MR13/P
itself Operation
Normal Y
operating?
Press the
wheel
N
☞A23
Y
Y
Check & Replace
Battery of MR13/P
Check & Repair
RF assy
connection
Y
Normal
operating?
☞A4
RF Receiver ver
is “00.00”?
N
Y
Close
Cl
Turn off/on the
set and press
the wheel
Is show ok N
message?
N
Close
Close
Is show ok
message?
N
Press the back
y
key about 5sec
Y
Replace
MR13
Close
Down load the Firmware
•If you conduct the loop at 3times, change the
MR13/P.
* INSTART MENU 02.11
Remocon Test 3. Firmware
download
11
Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
Standard Repair Process
LCD TV
D. Function error
Error
symptom
Established
date
Wifi operating checking
2013.01.31
Revised date
12/16
3.Wifi operating error
☞A4
Check the
INSTART menu
☞A24
Wi-Fi Mac value
is “NG”?
☞A24
N
Check the Wifi wafer
1pin
Normal
Voltage?
N
Replace
Main B/D
Y
Y
Close
Check & Repair
Wifi cable
connection
☞A4
Wi-Fi Mac value
is “NG”?
N
Close
Y
Change the Wifi
assy
12
Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
Standard Repair Process
LCD TV
D. Function error
Error
symptom
Established
date
Camera operating checking
2013.01.31
Revised date
13/16
4.Camera operating error
☞A4
Check the
INSTART menu
☞A25
Camera Ver.
is “NG”?
☞A25
N
Check the Camera wafer
P4200 2pin
Normal
Voltage?
N
Replace
Camera B/D
Y
Y
Close
Check & Repair
Camera cable
connection
☞A4
Camera Ver.
is “NG”?
N
Close
Y
Change the
Camera assy
13
Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
Standard Repair Process
LCD TV
Check
input
signal
D. Function error
Signal
input?
N
Y
Established
date
External device recognition error
Error
symptom
Revised date
Check technical
information
- Fix information
- S/W Version
Check and fix
external device/cable
Technical
information?
N
External Input and
Component
Recognition error
2013.01.31
14/16
Replace Main B/D
Y
Fix in
accordance
with technical
information
HDMI/
DVI, Optical
Recognition error
Replace Main B/D
14
Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
Standard Repair Process
LCD TV
Identify
nose
type
Error
symptom
Circuit
noise
Mechanical
noise
E. Noise
Established
date
Circuit noise mechanical noise
noise,
Revised date
Check
location of
noise
2013.01.31
15/16
Replace PSU
Check location of
noise
※ M h i l noise i a natural
Mechanical i is
t l
phenomenon, and apply the 1st level
description. When the customer does not
agree, apply the process by stage.
※ Describe the basis of the description
in “Part l t d to
i “P t related t nose” i th O
” in the Owner’s
’
Manual.
OR
OR
※ When the nose is severe, replace the module
(For models with fix information, upgrade the
p
p
)
S/W or provide the description)
※ If there is a “Tak Tak” noise from the
cabinet, refer to the KMS fix information and
then proceed as shown in the solution manual
(
(For models without any fix information,
y
,
provide the description)
15
Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
Standard Repair Process
LCD TV
F. Exterior defect
Error
symptom
Zoom part with
Z
ih
exterior damage
Exterior defect
Module
damage
Revised date
2013.01.31
16/16
Replace module
Cabinet
damage
Established
date
Replace cabinet
Remote
controller
damage
Stand
dent
Replace remote controller
Replace sta d
ep ace stand
16
Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
Contents of LCD TV Standard Repair Process Detail Technical Manual
No.
1
Error symptom
Content
Page
Check LCD back light with naked eye
A1
Check White Balance value
A2
TUNER input signal strength checking
method
A3
LCD-TV Version checking method
A4
Tuner Checking Part
A5
LCD TV connection di
ti
diagram
A6
Check Link Cable (EPI) reconnection
condition
A7
9
Adjustment Test pattern - A J K
Adj
ADJ Key
A8
10
Exchange Main Board (1)
A-1/5
Exchange Main Board (2)
A-2/5
Exchange Power Board (PSU)
A-3/5
Exchange Module (1)
A-4/5
Exchange Module (2)
Remarks
A 5/5
A-5/5
2
A.
A Video error No video/Normal
error_
audio
4
5
A.
A Video error video error /Video
error_
lag/stop
6
7
8
11
12
13
A. Video error _Vertical/Horizontal bar,
Vertical/Horizontal
residual image, light spot
A. Video error_ Color error
& lt; Appendix & gt;
Appendix
Defected Type caused by T-Con/
Inverter/ Module
14
Continue to the next page
Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
Contents of LCD TV Standard Repair Process Detail Technical Manual
Continued from previous page
No.
16
Error symptom
Content
Page
Check front display LED
A17
Check power input Voltage & ST-BY 3.5V
A18
POW R
POWER OFF MO
MODE checking method
A19
Checking method in menu when there is
no audio
A20
Voltage and speaker checking method
when there is no audio
A21
Remote controller operation checking
method
A22
Motion Remote operation checking
method
A23
23
Wifi operation checking method
A24
24
Camera operation checking method
A25
Tool option changing method
Remarks
A26
17
18
19
20
B. Power error_ No power
B. Power error_Off when on, off
while viewing
hil i i
C. Audio error_ No audio/Normal
video
21
22
25
D. Function error
E. Etc
Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
Standard Repair Process Detail Technical Manual
A. Video error_No video/Normal audio
Content
LCD TV
Error
symptom
Check LCD back light with naked eye
Established
date
Revised
date
2013.01.31
A1
After Remove the Rear Cover, turning on the power and disassembling the case,
check with the naked eye.
A1
Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
Standard Repair Process Detail Technical Manual
LCD TV
Error
symptom
A. Video error_No video/Normal audio
Content
Check White Balance value
Established
date
Revised
date
2013.01.31
A2
Entry method
Entry method
1.1. Press the ADJ button on the remote controller for adjustment.
Press the ADJ button on the remote controller for adjustment.
2.2. Enter into White Balance of item 9.
Enter into White Balance of item 6.
3. Aft recording the R, G B (GAIN, C t) value of C l T
3 3. After recording the R, G, B (GAIN, Cut) value fof Color Temp
After
di th R G, (GAIN Cut) l
Color Temp
(Cool/Medium/Warm), re-enter the value after replacing the MAIN BOARD.
(Cool/Medium/Warm), re-enter the value after replacing the MAIN BOARD.
A2
Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
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Standard Repair Process Detail Technical Manual
A. Video error_Video error, video lag/stop
Content
LCD TV
Error
symptom
TUNER input signal strength checking method
Established
date
Revised
date
Settings
Channel
select channel
2013.01.31
A3
Manual Tuning
When the signal is strong, use the
attenuator (-10dB -15dB -20dB etc.)
( 10dB, 15dB, 20dB etc )
A3
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LGE Internal Use Only
Standard Repair Process Detail Technical Manual
A. Video error_Video error, video lag/stop
Content
LCD TV
Error
symptom
LCD-TV
LCD TV Version checking method
Established
date
Revised
date
2013.01.31
A4
1. Checking method for remote controller for adjustment
Version
Press the IN-START with the remote
controller for adjustment
t ll f
dj t
t
A4
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Only for training and service purposes
LGE Internal Use Only
Standard Repair Process Detail Technical Manual
A. Video error_Video error, video lag/stop
Content
LCD TV
Error
symptom
TUNER checking part
Established
date
Revised
date
2013.01.31
A5
Checking method:
1. Check the signal strength or check whether the screen is normal when the external device is connected.
g
g
power supply, finally replace the MAIN BOARD.
pp y,
y p
2. After measuring each voltage from p
A5
Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
Standard Repair Process Detail Technical Manual
LCD TV
Error
symptom
Content
A. Video error _Vertical/Horizontal bar,
residual image, light spot
LCD TV connection di
ti diagram (1)
Established
date
Revised
date
2013.01.31
A6
As the part connecting to the external input, check
the screen condition by signal
A6
Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
Standard Repair Process Detail Technical Manual
LCD TV
Error
symptom
Content
A. Video error_Color error
Check Link Cable
Ch k Li k C bl (EPI) reconnection condition
ti
diti
Established
date
Revised
date
2013.01.31
A7
Check the contact condition of the Link Cable, especially dust or mis insertion.
A7
Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
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LGE Internal Use Only
Standard Repair Process Detail Technical Manual
A. Video error_Color error
Content
LCD TV
Error
symptom
Adjustment Test pattern - ADJ Key
Established
date
Revised
date
2013.01.31
A8
You can view 6 types of patterns using the ADJ Key
Checking item : 1. Defective pixel 2. Residual image 3. MODULE error (ADD-BAR,SCAN BAR..)
4.Video error (Classification of MODULE or Main-B/D!)
A8
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Only for training and service purposes
LGE Internal Use Only
Appendix : Exchange the Module (1)
수직 비내림
Crosstalk
Brightness difference
Press damage
Line Dim
Crosstalk
Un-repairable Cases
In this case please exchange the module.
p
g
Burnt
A – 1/2
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Only for training and service purposes
LGE Internal Use Only
Appendix : Exchange the Module (2)
Angle view Color difference
Brightness difference
Brightness dot noise
Green Noise on power on/off time
Half dead
Line Defect
Un-repairable Cases
In this case please exchange the module.
p
g
Mura
A – 2/2
Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
Standard Repair Process Detail Technical Manual
LCD TV
Error
symptom
Content
B. Power error _No power
Check front di l Logo
Ch k f
t display L
Front LED control :
Menu
Option
Standby Light
ON/ Off
Established
date
Revised
date
2013.01.31
A17
ST-BY condition: On or Off
Power ON condition: Turn Off
A17
Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
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LGE Internal Use Only
Standard Repair Process Detail Technical Manual
LCD TV
Error
symptom
Content
B. Power error _No power
Check power input voltage and ST-BY 3 5V
ST BY 3.5V
Established
date
Revised
date
2013.01.31
A18
Check the DC 24V 12V 3 5V
24V, 12V, 3.5V.
18 Pin (Power Board ↔ Main Board)
1
Power on
2
DRV ON
3
3.5V
4
20V
5
3.5V
3 5V
6
N.C
NC
7
GND
8
GND
9
24V
10
24V
11
GND
12
GND
13
12V
14
12V
15
12V
16
24V
17
GND
18
GND
A18
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LGE Internal Use Only
Standard Repair Process Detail Technical Manual
LCD TV
Error
symptom
Content
B. Power error _Off when on, off whiling viewing Established
date
POWER OFF MODE checking method
h ki
th d
Revised
date
2013.01.31
A19
Entry method
1. Press the IN-START button of the remote
controller for adjustment
2. Check the entry into adjustment item 3
A19
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LGE Internal Use Only
Standard Repair Process Detail Technical Manual
C. Audio error_No audio/Normal video
Content
LCD TV
Error
symptom
Checking
Ch ki method in menu when there is no audio
th d i
h th
i
di
Established
date
Revised
date
2013.01.31
A20
Checking method
1. Press the Setting button on the remote controller
g
2. Select the Sound function of the Menu
3. Select the Sound Setting
p
4. Select TV Speaker
A20
Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
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LGE Internal Use Only
Standard Repair Process Detail Technical Manual
C. Audio error_No audio/Normal video
Content
LCD TV
Error
symptom
Voltage and speaker checking method
when there is no audio
Established
date
Revised
date
2013.01.31
A21
③
①
②
Checking order when there is no audio
24 Pin (Power Board ↔ Main Board)
1
2
Power on
INV ON
3
4
3.5V
PDIM#1
5
6
3.5V
PDIM#2
7
8
GND
GND
9
10
24V
24V
11
12
GND
GND
13
12V
14
12V
15
12V
16
24V
17
GND
18
GND
19
GND
20
GND
21
GND
22 L/DIM0_V8
23 L/DIM0_MOSI 24 L/DIM0_SCLK
③
① Check the contact condition of or 24V connector of Main Board
② Measure the 24V input voltage supplied from Power Board
(If there is no input voltage, remove and check the connector)
③ Connect the tester RX1 to the speaker terminal and if you hear the Chik Chik sound when you touch the
GND and output terminal, the speaker is normal.
A21
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LGE Internal Use Only
Standard Repair Process Detail Technical Manual
Error
symptom
Content
LCD TV
D. Function error
Remote controller operation checking method
Established
date
Revised
date
2013.01.31
A22
③
①
1
2
3
4
5
6
7
8
P4002
KEY2
+3.5V_ST
GND
LOGO Light Wafer
IR
GND
EYE SCL
EYE SDA
②
Checking order
g
1, 2. Check Touch cable condition between Touch & Main board.
3.
Check the st-by 3.5V on the terminal 4,7.
4. When checking the Pre-Amp when the power is in ON condition, it is normal when the
Analog Tester needle moves slowly and defective when it does not move at all
slowly,
all.
A22
Copyright ⓒ 2013 LG Electronics. Inc. All right reserved.
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LGE Internal Use Only
Standard Repair Process Detail Technical Manual
LCD TV
Error
symptom
Content
D. Function error
Motion R
M ti
Remote operation checking method
t
ti
h ki
th d
Established
date
Revised
date
2013.01.31
A23
③
1
2
3
4
5
6
7
8
9
P4003
+3.5V_WOL
3 5V WOL
+3.3V
USB_DM
RTS
USB_DP
USB DP
RX
GND
TX
WOL
10
11
CTS
13
NC
14
+3.5V_ST(OLED)
15
IR(OLED)
16
GND
17
EYE_SCL
18
①
GND
12
②
RESET
EYE_SDA
Checking order
1, 2. Check Motion cable condition between Motion assy & Main board.
3.
Check the 3.3V on the terminal 2.
A23
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LGE Internal Use Only
Standard Repair Process Detail Technical Manual
LCD TV
Error
symptom
Content
D. Function error
Wifi operation checking method
Established
date
Revised
date
2013.01.31
A24
③
1
2
3
4
5
6
7
8
9
P4003
+3.5V_WOL
3 5V WOL
+3.3V
USB_DM
RTS
USB_DP
USB DP
RX
GND
TX
WOL
10
11
CTS
13
NC
14
+3.5V_ST(OLED)
15
IR(OLED)
16
GND
17
EYE_SCL
18
①
GND
12
②
RESET
EYE_SDA
Checking order
1, 2. Check Wifi cable condition between Wifi assy & Main board.
3.
Check the 3.3V on the terminal 2.
A24
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Standard Repair Process Detail Technical Manual
Error
symptom
LCD TV
Content
D. Function error
Camera operation checking method
Established
date
Revised
date
2013.01.31
A25
1
2
3
4
5
6
7
8
9
10
USB_CAMERA_DM
12
②
USB_CAMERA_DP
11
①
P4200
CAM_SLIDE_DET
CAM SLIDE DET
+3.5V_CAM
AUD_LRCH
AUD_LRCK
AUD_SCK
AUD SCK
GND
CAM_PWR_ON_CMD
ST_BY_DET_CAM
GND
GND
Checking order
1, 2. Check Camera cable condition between Camera assy & Main board.
3.
Check the 3.5V on the terminal 2.
A25
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LGE Internal Use Only
Standard Repair Process Detail Technical Manual
LCD TV
Error
symptom
Content
E. Etc
Tool ti
T l option changing method
h
i
th d
Established
date
Revised
date
2013.01.31
A26
②
①
Changing method
1.
Contact the USB memory. (USB 1,2,3 jack)
2.
Enter the password. (ex. 000000)
* Access USB Memory has each password.
A26
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LGE Internal Use Only