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Revised May 1999
CD4047BC
Low Power Monostable/Astable Multivibrator
s True and complemented buffered outputs
General Description
The CD4047B is capable of operating in either the
monostable or astable mode. It requires an external capacitor (between pins 1 and 3) and an external resistor
(between pins 2 and 3) to determine the output pulse width
in the monostable mode, and the output frequency in the
astable mode.
Astable operation is enabled by a high level on the astable
input or low level on the astable input. The output frequency (at 50% duty cycle) at Q and Q outputs is determined by the timing components. A frequency twice that of
Q is available at the Oscillator Output; a 50% duty cycle is
not guaranteed.
Monostable operation is obtained when the device is triggered by LOW-to-HIGH transition at + trigger input or
HIGH-to-LOW transition at − trigger input. The device can
be retriggered by applying a simultaneous LOW-to-HIGH
transition to both the + trigger and retrigger inputs.
A high level on Reset input resets the outputs Q to LOW, Q
to HIGH.
s Only one external R and C required
MONOSTABLE MULTIVIBRATOR FEATURES
s Positive- or negative-edge trigger
s Output pulse width independent of trigger pulse duration
s Retriggerable option for pulse width expansion
s Long pulse widths possible using small RC components
by means of external counter provision
s Fast recovery time essentially independent of pulse
width
s Pulse-width accuracy
approaching 100%
maintained
at
duty
cycles
ASTABLE MULTIVIBRATOR FEATURES
s Free-running or gatable operating modes
s 50% duty cycle
s Oscillator output available
s Good astable frequency stability
typical= ±2% + 0.03%/°C @ 100 kHz
Features
frequency= ±0.5% + 0.015%/°C @ 10 kHz
s Wide supply voltage range:
3.0V to 15V
s High noise immunity: 0.45 VDD (typ.)
s Low power TTL compatibility: Fan out of 2 driving 74L
or 1 driving 74LS
deviation (circuits trimmed to frequency VDD = 10V
±10%)
Applications
• Frequency discriminators
• Timing circuits
SPECIAL FEATURES
s Low power consumption: special CMOS oscillator
configuration
• Time-delay applications
s Monostable (one-shot) or astable (free-running)
operation
• Frequency multiplication
• Envelope detection
• Frequency division
Ordering Code:
Order Number
Package Number
Package Description
CD4047BCM
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
CD4047BCN
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 1999 Fairchild Semiconductor Corporation
DS005969.prf
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CD4047BC Low Power Monostable/Astable Multivibrator
October 1987
CD4047BC
Connection Diagram
Pin Assignments for SOIC and DIP
Top View
Function Table
Terminal Connections
To VDD
Function
Output Pulse
To VSS
From
Input Pulse
To
Typical Output
Period or
Pulse Width
Astable Multivibrator
Free-Running
4, 5, 6, 14
7, 8, 9, 12
10, 11, 13
tA(10, 11) = 4.40 RC
True Gating
4, 6, 14
7, 8, 9, 12
5
10, 11, 13
tA (13) = 2.20 RC
Complement Gating
6, 14
5, 7, 8, 9, 12
4
10, 11, 13
Positive-Edge Trigger
4, 14
5, 6, 7, 9, 12
8
10, 11
Negative-Edge Trigger
4, 8, 14
5, 7, 9, 12
6
10, 11
Retriggerable
4, 14
5, 6, 7, 9
8, 12
10, 11
Monostable Multivibrator
External Countdown (Note 1) 14
5, 6, 7, 8, 9, 12
Figure 1
Figure 1
Note 1: External resistor between terminals 2 and 3. External capacitor between terminals 1 and 3.
Typical Implementation of External Countdown Option
tEXT = (N − 1) tA + (tM + tA/2)
FIGURE 1.
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2
tM (10, 11) = 2.48 RC
Figure 1
CD4047BC
Block Diagram
Logic Diagram
*Special input protection circuit to permit larger input-voltage swings.
3
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CD4047BC
Absolute Maximum Ratings(Note 2)
Recommended Operating
Conditions (Note 3)
(Note 3)
−0.5V to +18VDC
DC Supply Voltage (VDD)
Input Voltage (VIN)
DC Supply Voltage (VDD)
−0.5V to VDD +0.5VDC
−65°C to +150°C
Storage Temperature Range (TS)
500 mW
Lead Temperature (TL)
(Soldering, 10 seconds)
−40°C to +85°C
Note 2: “Absolute Maximum Ratings” are those values beyond which the
safety of the device cannot be guaranteed. They are not meant to imply
that the devices should be operated at these limits. The table of “Recommended Operating Conditions” and “Electrical Characteristics” provides
conditions for actual device operation.
700 mW
Small Outline
0 to VDD VDC
Operating Temperature Range (TA)
Power Dissipation (PD)
Dual-In-Line
3V to 15VDC
Input Voltage (VIN)
Note 3: VSS = 0V unless otherwise specified.
260°C
DC Electrical Characteristics (Note 3)
Symbol
Parameter
−40°C
Conditions
Min
Max
25°C
Min
Typ
85°C
Max
Min
Max
Units
VOL
LOW Level Output Voltage
20
20
150
µA
40
40
300
µA
VDD = 15V
Quiescent Device Current
VDD = 5V
VDD = 10V
IDD
80
80
600
µA
|IO| & lt; 1 µA
VDD = 5V
HIGH Level Output Voltage
0
0.05
0.05
V
0.05
0
0.05
0.05
V
VDD = 15V
VOH
0.05
VDD = 10V
0.05
0
0.05
0.05
V
|IO| & lt; 1 µA
VDD = 5V
4.95
4.95
5
4.95
V
VDD = 10V
9.95
9.95
10
9.95
V
VDD = 15V
LOW Level Input Voltage
14.95
14.95
15
14.95
V
VDD = 5V, VO = 0.5V or 4.5V
1.5
2.25
1.5
1.5
V
VDD = 10V, VO = 1V or 9V
VIL
3.0
4.5
3.0
3.0
V
6.75
4.0
4.0
V
VDD = 15V, VO = 1.5V or 13.5V
HIGH Level Input Voltage
4.0
VDD = 5V, VO = 0.5V or 4.5V
3.5
3.5
2.75
3.5
V
VDD = 10V, VO = 1V or 9V
VIH
7.0
7.0
5.5
7.0
V
VDD = 15V, VO = 1.5V or 13.5V
IOL
LOW Level Output Current
11.0
11.0
8.25
11.0
V
VDD = 5V, VO = 0.4V
0.52
0.44
0.88
0.36
mA
mA
HIGH Level Output Current
(Note 4)
1.3
1.1
2.25
0.9
3.6
3.0
8.8
2.4
mA
VDD = 5V, VO = 4.6V
−0.52
−0.44
−0.88
−0.36
mA
VDD = 10V, VO = 9.5V
−1.3
−1.1
−2.25
−0.9
mA
VDD = 15V, VO = 13.5V
IOH
VDD = 10V, VO = 0.5V
VDD = 15V, VO = 1.5V
(Note 4)
−3.6
−3.0
−8.8
−2.4
Input Current
mA
VDD = 15V, VIN = 0V
−0.3
−10−5
−0.3
−1.0
µA
VDD = 15V, VIN = 15V
IIN
0.3
10−5
0.3
1.0
µA
Note 4: IOH and IOL are tested one output at a time.
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4
(Note 5)
Symbol
Typ
Max
Units
Propagation Delay Time Astable,
VDD = 5V
200
400
ns
Astable to Osc Out
VDD = 10V
100
200
ns
VDD = 15V
tPHL, tPLH
Parameter
Conditions
Min
80
160
ns
tWL, tWH
Minimum Input Pulse Duration
ns
300
600
ns
240
480
ns
VDD = 5V
300
600
ns
175
300
ns
150
250
ns
VDD = 5V
300
600
ns
125
250
ns
100
200
ns
VDD = 5V
100
200
ns
50
100
ns
VDD = 15V
Transition Time Q, Q, Osc Out
1200
VDD = 10V
tTHL, tTLH
700
VDD = 15V
Reset to Q, Q
ns
VDD = 5V
VDD = 10V
tPHL, tPLH
400
VDD = 15V
+ Trigger, Retrigger to Q
ns
200
VDD = 10V
tPHL, tPLH
ns
500
VDD = 15V
+ Trigger, − Trigger to Q
900
250
VDD = 10V
tPHL, tPLH
550
VDD = 15V
Astable, Astable to Q, Q
VDD = 5V
VDD = 10V
tPHL, tPLH
40
80
ns
Any Input
VDD = 5V
500
1000
ns
VDD = 10V
200
400
ns
VDD = 15V
160
320
ns
VDD = 5V
15
µs
VDD = 10V
5
µs
VDD = 15V
CIN
+ Trigger, Retrigger, Rise and
Fall Time
tRCL, tFCL
5
µs
7.5
pF
Average Input Capacitance
Any Input
5
Note 5: AC Parameters are guaranteed by DC correlated testing.
5
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CD4047BC
AC Electrical Characteristics
TA = 25°C, CL = 50 pF, RL = 200k, input tr = tf = 20 ns, unless otherwise specified.
CD4047BC
Typical Performance Characteristics
Typical Q, Q, Osc Out Period Accuracy vs
Supply Voltage (Astable Mode Operation)
f Q, Q
A
1000 kHz
B
C
R
Typical Q, Q, Pulse Width Accuracy vs
Supply Voltage Monostable Mode Operation
C
22k
100 kHz
22k
220k
1 kHz
220k
100 Hz
2.2M
7 µs
22k
100 pF
60 µs
220k
100 pF
550 µs
220k
1000 pF
E
1000 pF
10 pF
D
1000 pF
E
5.5 ms
2.2M
1000 pF
A
Typical Q, Q and Osc Out Period Accuracy
vs Temperature Astable Mode Operation
f Q, Q
A
1000 kHz
B
C
D
R
Typical Q and Q Pulse Width Accuracy vs
Temperature Monostable Mode Operation
C
tM
R
C
2 µs
22k
10 pF
B
7 µs
22k
100 pF
C
60 µs
220k
100 pF
550 µs
220k
1000 pF
22k
10 pF
100 kHz
22k
100 pF
10 kHz
220k
100 pF
1 kHz
220k
1000 pF
D
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C
22k
B
100 pF
D
R
2 µs
C
100 pF
10 kHz
tM
10 pF
A
6
CD4047BC
Timing Diagrams
Astable Mode
Monostable Mode
Retrigger Mode
7
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CD4047BC
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
Package Number M14A
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8
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N14A
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
1. Life support devices or systems are devices or systems
device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the
sonably expected to cause the failure of the life support
body, or (b) support or sustain life, and (c) whose failure
device or system, or to affect its safety or effectiveness.
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
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user.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
CD4047BC Low Power Monostable/Astable Multivibrator
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
This datasheet has been downloaded from:
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Datasheets for electronic components.