Masz raczej problem w sekcji na polowych (jak pisza koledzy) Scalak uP1608PK (Link) sam w sobie tani , w Chinach (partia 5szt. to ok. 9.$)/ ebay już 13.$) datasheet na ten IC dostępny , gorzej z układem pracy - np na kartach grafiki, zasilanie CPU :?: Powiadają , że to NCP5395t Problem jest w fazach zasilania (3+1) 3-fazy to zasilanie GPU 1-faza to zasilanie pamieci i PLL opartych o polowe np. MOSFET， M3014M(30V 50A 12mΩ), M3016M(30V 108A 4mΩ) * lub para SINOPOWER ([url=http://www.sinopowersemi.com/Form2) SM4370 + para SM4373. lub https://obrazki.elektroda.pl/7785575100_1505071586_thumb.jpg - zasilanie Vmem i PLL ... na np. ANPEC APW7165/ uPi1529P Kontroler zasilania GPU – CHiL CHL8228G - poniżej z AMD R7750/ HD7970/ R5670/R7850 czy GTX 680/ GF550ti -zasilanie 4+1 fazowe https://obrazki.elektroda.pl/6206005000_1505069677_thumb.jpg https://obrazki.elektroda.pl/1695472300_1505070045_thumb.jpg Jest SM pod MSI MS-7592(G41TM-P33) Opisano tam układ uP6206. * Układ uP1608PQ ma tyle samo pin., ale jest róznica № - uP6206AQGK - uP1608PQGK pin.11 - OFS - TP pin.19 - TB - NC Trzeba popatrzec po płycie (co z tym pin.) , ponadto w karcie z ((6206) nie ma diód w linii BOOT) * jest ? miejsce przeznaczone pod nie
APW7165
5V to 12V Synchronous Buck Controller
Features
General Description
•
Wide Operation Supply Voltage from 5V to 12V
•
Power-On-Reset Monitoring on VCC
The APW7165 is a voltage mode, fixed 300kHz-switching
frequency, and synchronous buck controller. The
•
Excellent Reference Voltage Regulations
APW7165 allows wide input voltage that is either a single
5~12V or two supply voltages for various applications. A
- 0.8V Internal Reference
- ±1% Over Temperature Range
power-on-reset (POR) circuit monitors the VCC supply
voltage to prevent wrong logic controls. A built-in digital
•
Integrated Soft-Start
•
Automatic PSM/PWM Modes
•
Voltage Mode PWM Operation with 90% (Max.)
soft-start circuit prevents the output voltages from overshoot as well as limits the input current. An internal 0.8V
temperature-compensated reference voltage with high
accuracy is designed to meet the requirement of low out-
Duty Cycle
•
Under-Voltage Protection
•
Adjustable Over-Current Protection Threshold
•
Over-Voltage Protection
•
Under-Voltage Protection
•
Simple SOP-8 Package
•
Lead Free and Green Devices Available
put voltage applications. The APW7165 provides excellent output voltage regulations against load current
variation.
The controller’ over-current protection monitors the outs
- Sensing the RDS(ON) of Low-Side MOSFET
put current by using the voltage drop across the RDS(ON) of
low-side MOSFET, eliminating the need for a current sensing resistor that features high efficiency and low cost.
The APW7165 also integrates over-voltage protection
(RoHS Compliant)
(OVP) and under-voltage protection circuit which monitors the FB voltage to prevent the PWM output from over
Applications
and under voltage.
The APW7165 is available in a simple SOP-8 package.
•
Graphic Cards
•
DSL, Switch HUB
•
Wireless Lan
•
Notebook Computer
•
Mother Board
•
LCD Monitor/TV
Simplified Application Circuit
VVCC
APW7165
BOOT 1
UGATE 2
7 COMP
PHASE 8
5
OFF
ON
Pin Configuration
BOOT 1
VCC
VOUT
LGATE 4
6 FB
GND
3
8 PHASE
UGATE 2
VIN
7 COMP
GND 3
6 FB
LGATE 4
5 VCC
SOP-8
(Top View)
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright © ANPEC Electronics Corp.
Rev. A.3 - Jan., 2011
1
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APW7165
Ordering and Marking Information
Package Code
K : SOP-8
Operating Ambient Temperature Range
E : -20 to 70oC
Handling Code
TR : Tape & Reel
Assembly Material
G : Halogen and Lead Free Device
APW7165
Assembly Material
Handling Code
Temperature Range
Package Code
APW7165 K:
APW7165
XXXXX
XXXXX - Date Code
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Absolute Maximum Ratings
(Note 1)
Rating
Unit
VVCC
VCC Supply Voltage (VCC to GND)
Parameter
-0.3 ~ 16
V
VBOOT
BOOT to PHASE Voltage
-0.3 ~ 16
V
VUGATE
UGATE to PHASE Voltage
& gt; 400ns
-0.3 ~ VBOOT+0.3
V
& lt; 400ns
-5 ~ VBOOT+5
V
VLGATE
LGATE to GND Voltage
& gt; 400ns
-0.3 ~ VVCC+0.3
V
& lt; 400ns
-5 ~ VVCC+5
V
& gt; 200ns
-0.3 ~ 16
V
& lt; 200ns
-10 ~ 30
V
Symbol
VPHASE
PHASE to GND Voltage
FB and COMP to GND ( & lt; VVCC + 0.3V)
TJ
-0.3 ~ 7
TSDR
Maximum Lead Soldering Temperature, 10 Seconds
°C
260
Storage Temperature
°C
-65 ~ 150
TSTG
V
150
Maximum Junction Temperature
°C
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Thermal Characteristics
Symbol
Parameter
θJA
Thermal Resistance - Junction to Ambient
θJC
Typical Value
Unit
150
°C/W
28
°C/W
(Note 2)
Thermal Resistance - Junction to Case
SOP-8
SOP-8
Note 2 : θJA is measured with the component mounted on a high effective thermal conductivity test board in free air.
Copyright © ANPEC Electronics Corp.
Rev. A.3 - Jan., 2011
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APW7165
Recommended Operating Conditions (Note 3)
Symbol
VVCC
VOUT
Parameter
Range
4.5 ~ 13.2
VCC Supply Voltage (VCC to GND)
Converter Output Voltage
Unit
V
0.9 ~ 5
V
2.9 ~ VVCC
V
0 ~ 20
A
Ambient Temperature
-20 ~ 70
°C
Junction Temperature
-20 ~ 125
°C
VIN
Converter Input Voltage
IOUT
Converter Output Current
TA
TJ
Note 3 : Refer to the application circuit for further information.
Electrical Characteristics
Refer to the typical application circuit. These specifications apply over VVCC = 12V, TA = -20°C to 70°C, unless otherwise
noted. Typical values are at TA = 25°C.
Symbol
Parameter
APW7165
Test Conditions
Unit
Min.
Typ.
Max.
INPUT SUPPLY VOLTAGE AND CURRENT
VCC Supply Current (Shutdown Mode)
UGATE and LGATE open;
COMP=GND
-
4
6
VCC Supply Current
UGATE and LGATE open
-
16
24
Rising VCC POR Threshold
3.7
4.1
4.4
V
VCC POR Hysteresis
IVCC
0.3
0.45
0.6
V
270
300
330
kHz
-
1.5
-
V
85
-
90
%
0.792
0.8
0.808
V
-
-
0.2
%
-
667
-
µA/V
1
µA
mA
POWER-ON-RESET(POR)
OSCILLATOR
FOSC
Oscillator Frequency
∆VOSC
Oscillator Sawtooth Amplitude
DMAX
Maximum Duty Cycle
(Note 4)
ERROR AMPLIFIER
VREF
Reference Voltage
Converter Load Regulation
gm
TA = -20 ~ 70°C
(Note 4)
IOUT = 2 ~ 12A
Transconductance
FB Input Leakage Current
VFB = 0.8V
-
0.1
COMP High Voltage
RL = 10kΩ to GND
-
2.5
-
COMP Low Voltage
RL = 10kΩ to GND
-
1
-
Maximum COMP Source Current
VCOMP = 2V
-
200
-
Maximum COMP Sink Current
VCOMP = 2V
-
200
-
High-Side Gate Driver Source Current
VBOOT= 12V, VUGATE-PHASE = 2V
-
1.8
-
A
High-Side Gate Driver Sink Impedance
BOOT=12V, IUGATE = 0.1A
-
2.3
-
Ω
Low-Side Gate Driver Source Current
VVCC = 12V, VLGATE = 2V
-
1.8
-
A
Low-Side Gate Driver Sink Impedance
VVCC =12V, IUGATE = 0.1A
-
1.3
-
Ω
-
30
-
ns
V
µA
GATE DRIVERS
TD
Dead-Time
(Note 4)
Copyright © ANPEC Electronics Corp.
Rev. A.3 - Jan., 2011
3
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APW7165
Electrical Characteristics (Cont.)
Refer to the typical application circuit. These specifications apply over VVCC = 12V, TA = -20°C to 70°C, unless otherwise
noted. Typical values are at TA = 25°C.
Symbol
Parameter
APW7165
Test Conditions
Unit
Min.
Typ.
Max.
PROTECTIONS
VFB_UV
FB Under-Voltage Protection Trip Point
Percentage of VREF
45
50
55
%
VFB_OV
FB Over-Voltage Protection Trip Point
VFB rising
115
120
125
%
FB Over-Voltage Protection Hysteresis
VOCP_MAX
IOCSET
-
5
-
%
Built-in Maximum OCP Voltage
300
-
-
mV
OCSET Current Source
19.5
21.5
23.5
µA
-
-
0.6
V
-
1.7
-
ms
SOFT-START
VDISABLE
TSS
Shutdown Threshold of VCOMP
Internal Soft-Start Interval
(Note 4)
Note 4 : Guaranteed by design, not production tested.
Copyright © ANPEC Electronics Corp.
Rev. A.3 - Jan., 2011
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APW7165
Operating Waveforms
Refer to the typical application circuit. The test condition is VIN=12V, TA= 25oC unless otherwise specified.
Power On
Power Off
VIN
V IN
1
1
V OUT
VOUT
2
2
VUGATE
V UGATE
3
3
CH1: VIN, 5V/Div
CH2: VOUT, 500mV/Div
CH3: VUGATE, 10V/Div
Time: 1ms/Div
CH1: VIN, 5V/Div
CH2: VOUT, 500mV/Div
CH3: VUGATE, 10V/Div
Time: 200ms/Div
Enable
Shutdown
RLOAD=10Ω
VCOMP
VCOMP
1
1
VOUT
VOUT
2
2
VP H A S E
VP H A S E
3
3
CH1: VCOMP, 1V/Div
CH2: VOUT, 500mV/Div
CH3: VPHASE, 10V/Div
Time: 500µs/Div
Copyright © ANPEC Electronics Corp.
Rev. A.3 - Jan., 2011
CH1: VCOMP, 1V/Div
CH2: VOUT, 500mV/Div
CH3: VPHASE, 10V/Div
Time: 1ms/Div
5
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APW7165
Operating Waveforms (Cont.)
Refer to the typical application circuit. The test condition is VIN=12V, TA= 25oC unless otherwise specified.
PSM to PWM
PWM to PSM
IOUT =10mA to 2A
IOUT= 2A to 10mA
VOUT
VOUT
VP H A S E
1
1
2
2
VP H A S E
IL
3
3
IL
CH1: VOUT, 1V/Div
CH2: VPHASE, 10V/Div
CH3: IL, 2A/Div
Time: 500µs/Div
CH1: VOUT, 500mV/Div
CH2: VPHASE, 10V/Div
CH3: IL, 2A/Div
Time: 500µs/Div
UGATE Falling
UGATE Rising
VUGATE2
V UGATE
1
V LGATE
1,2
2
VLGATE2
VPHASE2
3
3
CH1: VUGATE, 20V/Div
CH2: VLGATE, 10V/Div
CH3: VPHASE, 10V/Div
Time: 20ns/Div
Copyright © ANPEC Electronics Corp.
Rev. A.3 - Jan., 2011
VPHASE
CH1: VUGATE, 20V/Div
CH2: VLGATE, 10V/Div
CH3: VPHASE, 10V/Div
Time: 20ns/Div
6
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APW7165
Operating Waveforms (Cont.)
Refer to the typical application circuit. The test condition is VIN=12V, TA= 25oC unless otherwise specified.
Over Current Protection
Over Current Protection
ROCSET=5.1k Ω,RDS (low-side)=10mΩ
V OUT
VOUT
1
1
VP H A S E
2
2
VPHASE
IL
3
3
IL
CH1: VOUT, 500mV/Div
CH1: VOUT, 500mV/Div
CH2: VPHASE, 20A/Div
CH3: IL, 10A/Div
CH2: VPHASE, 20A/Div
CH3: IL, 10A/Div
Time: 5µs/Div
Time: 50µs/Div
Load Transient Response
IOUT Slew rate=10A /µs
IOUT=10mA- & gt; 10A- & gt; 10mA
1
V OUT
2
IOUT
CH1: VOUT, 50mV/Div
CH2: IOUT, 5A/Div
Time: 200µs/Div
Copyright © ANPEC Electronics Corp.
Rev. A.3 - Jan., 2011
7
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APW7165
Pin Description
PIN
FUNCTION
NO.
NAME
1
BOOT
2
UGATE
3
GND
4
LGATE
Low-side Gate Driver Output and Over-Current Setting Input. This pin is the gate driver for low-side
MOSFET. It also used to set the maximum inductor current. Refer to the section in “Function
Description” for detail.
5
VCC
Power Supply Input for Control Circuitry. Connect a nominal 5V to 12V power supply voltage to this
pin. A power-on-reset function monitors the input voltage at this pin. It is recommended that a
decoupling capacitor (1 to 10µF) be connected to GND for noise decoupling.
6
FB
Feedback Input of Converter. The converter senses feedback voltage via FB and regulates the FB
voltage at 0.8V. Connecting FB with a resistor-divider from the output sets the output voltage of the
converter.
7
COMP
This is a multiplexed pin. During the soft-start and normal converter operation, this pin represents the
output of the error amplifier. It is used to compensate the regulation control loop in combination with
the FB pin.
Pulling COMP low (VDISABLE = 0.6V typical) will shut down the controller. When the pull-down device is
released, the COMP pin will start to rise. When the COMP pin rises above the VDISABLE trip point, the
APW7165 will begin a new initialization and soft-start cycle.
8
PHASE
This pin is the return path for the high-side gate driver. Connecting this pin to the high-side MOSFET
source and connecting a capacitor to BOOT for the bootstrap voltage. This pin is also used to monitor
the voltage drop across the low-side MOSFET for over-current protection.
This pin provides the bootstrap voltage to the high-side gate driver for driving the N-channel MOSFET.
An external capacitor from PHASE to BOOT, an internal diode, and the power supply voltage VCC,
generates the bootstrap voltage for the high-side gate driver (UGATE).
High-side Gate Driver Output. This pin is the gate driver for high-side MOSFET.
Signal and Power ground. Connecting this pin to system ground.
Typical Application Circuit
VCC Supply
(5~12V)
C5
1µF
R5
2R2
7
ON
Q3
2N7002
BOOT
VCC
COMP UGATE
C1
15nF
C2
15pF
PHASE
R3
15kΩ
6
R2
CIN1
APW7165
5
OFF
VIN
LGATE
FB
GND
3
1
C4
0.1µF
CIN2
1µF
470µF x 2
Q1
APM2510
L1
2
8
VOUT
1µH
Q2
APM2556
4
ROCSET
COUT
470µF x 2
R1
1kΩ
2kΩ
Copyright © ANPEC Electronics Corp.
Rev. A.3 - Jan., 2011
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APW7165
Block Diagram
VCC
IOCSET
Sample
Regulator (21.5µA typical) and
Hold
BOOT
Power-On-Reset
UGATE
Sense Low Side
VREF 3V
(0.8V typical)
VROCSET
To
LGATE
PHASE
UVP Comparator
1/2
2xVROCSET
Soft-Start
and
Fault Logic
IZCMP
VCC
Inhibit
OVP Comparator
1.2
Gate
Control
LGATE
Soft-Start
Error Amplifier
PWM
Comparator
VREF 0.8V
Oscillator
0.6V
FB
Disable
GND
COMP
Copyright © ANPEC Electronics Corp.
Rev. A.3 - Jan., 2011
9
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APW7165
Function Description
Power-On-Reset (POR)
A resistor (ROCSET), connected from the LGATE to the GND,
programs the over-current trip level. Before the IC ini-
The Power-On-Reset (POR) function of APW7165 continually monitors the input supply voltage (VCC) and en-
tiates a soft-start process, an internal current source, IOCSET
(21.5µA typical), flowing through the ROCSET develops a
sures that the IC has sufficient supply voltage and can
work well. The POR function initiates a soft-start process
voltage (VROCSET) across the ROCSET. During the normal
operation, the device holds VROCSET and stops the current
while the VCC voltage exceeds the POR threshold; the
POR function also inhibits the operations of the IC while
the VCC voltage falls below the POR threshold.
source, IOCSET. When the voltage across the low-side
MOSFET exceeds the double VROCSET (2 x VROCSET), the IC
Soft-Start
shuts off the converter and then initiates a new soft-start
process. After 2 over-current events are counted, the de-
The APW7165 builds in a 40-steps digital soft-start to
control the output voltage rise as well as limit the current
vice is shut down and all the gate drivers (UGATE, LGATE,
and DRIVE) are off. Both the output of the PWM converter
surge at the start-up. During the soft-start, the internal
step voltage connected to the one of the positive inputs of
and linear controller are latched to be floating.
The APW7165 has an internal OCP voltage, VOCP_MAX, and
the error amplifier replaces the reference voltage (0.8V
typical) until the step voltage reaches the reference
the value is 0.3V minimum. When the ROCSET x IOCSET exceeds 0.3V or the ROCSET is floating or not connected, the
voltage. The digital soft-start circuit interval (shown as
figure 1) depends on the switching frequency.
VROCSET will be the default value 0.3V. The over current
threshold would be 0.7V across low-side MOSFET. The
TSS = (t 3 − t 2 ) =
1
FOSC
threshold of the valley inductor current-limit is therefore
given by:
x 512
ILIMIT =
Voltage(V)
2 × IOCSET × ROCSET
RDS(ON) (low − side)
For the over-current is never occurred in the normal operating load range; the variation of all parameters in the
VVCC
above equation should be considered:
- The RDS(ON) of low-side MOSFET is varied by temperature and gates to source voltage. Users should deter-
OCSET count completed
POR
OCSET count start
mine the maximum RDS(ON) by using the manufacturer’
s
datasheet.
(OCSET duration, t2 - t1, less than 0.9ms)
VOUT
t0
t1 t2
t3
- The minimum I OCSET (19.5µA) and minimum R OCSET
should be used in the above equation.
Time
- Note that the ILIMIT is the current flow through the lowside MOSFET; ILIMIT must be greater than valley inductor
Figure 1. Soft-Start Interval
current which is output current minus the half of inductor ripple current.
Over-Current Protection
The over-current function protects the switching converter
against over-current or short-circuit conditions. The con-
ILIMIT & gt; IOUT (MAX ) −
troller senses the inductor current by detecting the drainto-source voltage which is the product of the inductor’
s
Where Δ I = output inductor ripple current
- The overshoot and transient peak current also should
current and the on-resistance of the low-side MOSFET
during it’ on-state.
s
Copyright © ANPEC Electronics Corp.
Rev. A.3 - Jan., 2011
∆I
2
be considered.
10
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APW7165
Function Description (Cont.)
Under-Voltage Protection
Adaptive Shoot-Through Protection
The under-voltage function monitors the voltage on FB
(VFB) by Under-Voltage (UV) comparator to protect the PWM
The gate drivers incorporate an adaptive shoot-through
protection to prevent high-side and low-side MOSFETs
converter against short-circuit conditions. When the VFB
falls below the falling UVP threshold (50% VREF), a fault
from conducting simultaneously and shorting the input
supply. This is accomplished by ensuring the falling gate
signal is internally generated and the device turns off
high-side and low-side MOSFETs. The converter is shut-
has turned off one MOSFET before the other is allowed to
rise.
down and the output is latched to be floating.
During turn-off of the low-side MOSFET, the LGATE voltage is monitored until it is below 1.5V threshold, at which
Over-Voltage Protection (OVP)
time the UGATE is released to rise after a constant delay.
During turn-off of the high-side OCSFET, the UGATE-to-
The over-voltage protection monitors the FB voltage to
prevent the output from over-voltage condition. When the
PHASE voltage is also monitored until it is below 1.5V
threshold, at which time the LGATE is released to rise
output voltage rises above 120% of the nominal output
voltage, the APW7165 turns off the high-side MOSFET
after a constant delay.
and turns on the low-side MOSFET until the output voltage falls below the falling OVP threshold, regulating the
output voltage around the OVP threshold.
Shutdown and Enable
The APW7165 can be shut down or enabled by pulling
low the voltage on COMP. The COMP is a dual-function
pin. During normal operation, this pin represents the
output of the error amplifier. It is used to compensate the
regulation control loop in combination with the FB pin.
Pulling the COMP low (VDISABLE = 0.6V typical) places the
controller into shutdown mode which UGATE and LGATE
are pulled to PHASE and GND respectively.
When the pull-down device is released, the COMP voltage will start to rise. When the COMP voltage rises above
the VDISABLE threshold, the APW7165 will begin a new initialization and soft-start process.
Pulse Skipping Mode (PSM)
At light loads, the inductor current may reach zero or reverse on each pulse. The low-side MOSFET is turned off
by the current reversal comparator, IZCMP, to block the
negative inductor current. In this condition, the converter
enters discontinuous current mode operation.
At very light loads, the APW7165 will automatically skip
pulses in pulse skipping mode operation to reduce
switching losses as well as maintain output regulation
for efficient applications.
Copyright © ANPEC Electronics Corp.
Rev. A.3 - Jan., 2011
11
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APW7165
Application Information
Output Voltage Selection
IRIPPLE =
The output voltage can be programmed with a resistive
divider. Use 1% or better resistors for the resistive divider
VIN − VOUT VOUT
×
FSW × L
VIN
where Fs is the switching frequency of the regulator.
∆VOUT = IRIPPLE x ESR
is recommended. The FB pin is the inverter input of the
error amplifier, and the reference voltage is 0.8V. The
A tradeoff exists between the inductor’ ripple current and
s
the regulator load transient response time. A smaller in-
output voltage is determined by:
R
VOUT = 0.8 × 1 + 1
R2
ductor will give the regulator a faster load transient response at the expense of higher ripple current and vice
Where R1 is the resistor connected from VOUT to FB and
R2 is the resistor connected from FB to the GND.
versa. The maximum ripple current occurs at the maximum input voltage. A good starting point is to choose the
Output Capacitor Selection
ripple current to be approximately 30% of the maximum
output current.
The selection of COUT is determined by the required effective series resistance (ESR) and voltage rating rather than
Once the inductance value has been chosen, selecting
an inductor is capable of carrying the required peak cur-
the actual capacitance requirement. Therefore, selecting
high performance low ESR capacitors is intended for
rent without going into saturation. In some types of
inductors, especially core that is make of ferrite, the ripple
switching regulator applications. In some applications,
multiple capacitors have to be paralleled to achieve the
current will increase abruptly when it saturates. This will
result in a larger output ripple voltage.
desired ESR value. If tantalum capacitors are used, make
sure they are surge tested by the manufactures. If in doubt,
Compensation
consult the capacitors manufacturer.
The output LC filter of a step down converter introduces a
Input Capacitor Selection
double pole, which contributes with –40dB/decade gain
slope and 180 degrees phase shift in the control loop. A
The input capacitor is chosen based on the voltage rating
compensation network between COMP pin and ground
should be added. The simplest loop compensation net-
and the RMS current rating. For reliable operation, select
the capacitor voltage rating to be at least 1.3 times higher
work is shown in Figure 5.
The output LC filter consists of the output inductor and
than the maximum input voltage. The maximum RMS
current rating requirement is approximately IOUT/2 where
output capacitors. The transfer function of the LC filter is
given by:
IOUT is the load current. During power up, the input capacitors have to handle large amount of surge current. If tantalum capacitors are used, make sure they are surge tested
by the manufactures. If in doubt, consult the capacitors
GAINLC =
manufacturer.
For high frequency decoupling, a ceramic capacitor be-
1 + s × ESR × COUT
s2 × L × COUT + s × ESR × COUT + 1
The poles and zero of this transfer function are:
1
2 × π × L × COUT
tween 0.1µF to 1µF can connect between VCC and ground
pin.
FLC =
Inductor Selection
FESR =
The inductance of the inductor is determined by the output voltage requirement. The larger the inductance, the
1
2 × π × ESR × COUT
The FLC is the double poles of the LC filter, and FESR is
the zero introduced by the ESR of the output capacitor.
lower the inductor’ current ripple. This will translate into
s
lower output ripple voltage. The ripple current and ripple
voltage can be approximated by:
Copyright © ANPEC Electronics Corp.
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APW7165
Application Information (Cont.)
Compensation (Cont.)
The compensation circuit is shown in Figure 5. R3 and
C1 introduce a zero and C2 introduces a pole to reduce
L
the switching noise. The transfer function of error ampli-
Output
PHASE
fier is given by:
COUT
1 1
//
GAIN AMP = gm × ZO = gm × R3 +
sC1 sC2
ESR
= gm ×
1
s +
R3 × C1
s × s +
Figure 2. The Output LC Filter
C1 + C2
× C2
R3 × C1× C2
The pole and zero of the compensation network are:
FLC
FP =
-40dB/dec
FESR
FZ =
Gain
1
2 × π × R3 ×
C1× C2
C1 + C2
1
2 × π × R3 × C1
VOUT
-20dB/dec
Error
Amplifier
R1
FB
Frequency
-
COMP
Figure 3. The LC Filter Gain & Frequency
R2
The PWM modulator is shown in Figure 4. The input is
the output of the error amplifier and the output is the PHASE
+
R3
VREF
C2
C1
node. The transfer function of the PWM modulator is given
by:
GAINPWM =
VIN
∆VOSC
Figure 5. Compensation Network
VIN
The closed loop gain of the converter can be written as:
Driver
GAINLG × GAINPWM ×
PWM
Comparator
R2
× GAINAMP
R1 + R2
Figure 6 shows the converter gain and the following guideVOSC
lines will help to design the compensation network.
1.Select the desired zero crossover frequency FO:
Output of
Error
Amplifier
PHASE
(1/5 ~ 1/10) x FSW & gt; FO & gt; FZ
Use the following equation to calculate R3:
R3 =
Driver
∆VOSC FESR R1 + R2 FO
×
×
×
VIN
R2
gm
FLC2
Where:
gm = 667µA/V
Figure 4. The PWM Modulator
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APW7165
Application Information (Cont.)
Compensation (Cont.)
Note that both MOSFETs have conduction losses while
2. Place the zero FZ before the LC filter double poles FLC:
the upper MOSFET include an additional transition loss.
The switching internal, tsw, is the function of the reverse
FZ = 0.75 x FLC
transfer capacitance CRSS. Figure 7 illustrates the switching waveform internal of the MOSFET.
Calculate the C1 by the equation:
C1 =
1
2 × π × R1× 0.75 × FLC
The (1+TC) term factors in the temperature dependency
of the RDS(ON) and can be extracted from the “RDS(ON) vs.
Temperature” curve of the power MOSFET.
3. Set the pole at the half the switching frequency:
FP = 0.5xFSW
VDS
C1
π × R3 × C1× FSW − 1
Voltage across
C2 =
FZ=0.75FLC
20 . log(gm . R3)
FP=0.5FSW
Compensation
Gain
Gain
FLC
V
20.log IN
∆VOSC
drain and source of MOSFET
Calculate the C2 by the equation:
FO
tsw
FESR
PWM &
Filter Gain
Converter
Gain
Time
Figure 7. Switching Waveform Across MOSFET
Layout Consideration
Frequency
In any high switching frequency converter, a correct lay-
Figure 6. Converter Gain & Frequency
out is important to ensure proper operation of the
regulator. With power devices switching at 300kHz, the
MOSFET Selection
The selection of the N-channel power MOSFETs is deter-
resulting current transient will cause voltage spike across
the interconnecting impedance and parasitic circuit
mined by the RDS(ON), reverse transfer capacitance (CRSS),
and maximum output current requirement.The losses in
elements. As an example, consider the turn-off transition
of the PWM MOSFET. Before turn-off, the MOSFET is car-
the MOSFETs have two components: conduction loss and
transition loss. For the upper and lower MOSFET, the
rying the full load current. During turn-off, current stops
flowing in the MOSFET and is free-wheeling by the lower
losses are approximately given by the following equations:
MOSFET and parasitic diode. Any parasitic inductance of
the circuit generates a large voltage spike during the
PUPPER = IOUT2 (1+ TC)(RDS(ON))D + (0.5)(Iout)(VIN)(tsw)FSW
switching interval. In general, using short and wide printed
circuit traces should minimize interconnecting imped-
PLOWER = IOUT2 (1+ TC)(RDS(ON))(1-D)
where IOUT is the load current
TC is the temperature dependency of RDS(ON)
ances and the magnitude of voltage spike. And signal
and power grounds are to be kept separating till com-
FSW is the switching frequency
tsw is the switching interval
bined using the ground plane construction or single point
grounding. Figure 8. illustrates the layout, with bold lines
D is the duty cycle
indicating high current paths; these traces must be short
Copyright © ANPEC Electronics Corp.
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APW7165
Application Information (Cont.)
Layout Consideration (Cont.)
and wide. Components along the bold lines should be
placed lose together. Below is a checklist for your layout:
- Keep the switching nodes (UGATE, LGATE, and PHASE)
away from sensitive small signal nodes since these
nodes are fast moving signals. Therefore, keep traces
to these nodes as short as possible.
- The traces from the gate drivers to the MOSFETs (UG
and LG) should be short and wide.
- Place the source of the high-side MOSFET and the drain
of the low-side MOSFET as close as possible. Minimizing the impedance with wide layout plane between the
two pads reduces the voltage bounce of the node.
- Decoupling capacitor, compensation component, the
resistor dividers, and boot capacitors should be close
their pins. (For example, place the decoupling ceramic
capacitor near the drain of the high-side MOSFET as
close as possible. The bulk capacitors are also placed
near the drain).
- The input capacitor should be near the drain of the upper MOSFET; the output capacitor should be near the
loads. The input capacitor GND should be close to the
output capacitor GND and the lower MOSFET GND.
- The drain of the MOSFETs (VIN and PHASE nodes) should
be a large plane for heat sinking.
- The ROCSET resistance should be placed near the IC as
close as possible.
APW7165
VIN
VCC
BOOT
L
O
A
D
UGATE
PHASE
LGATE
ROCSET
VOUT
Close to IC
Figure 8. Layout Guidelines
Copyright © ANPEC Electronics Corp.
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APW7165
Package Information
SOP-8
D
h X 45o
E
E1
SEE VIEW A
c
0.25
A
b
A2
e
aaa
GAUGE PLANE
SEATING PLANE
A1
NX
c
L
VIEW A
S
Y
M
B
O
L
SOP-8
MILLIMETERS
MIN.
INCHES
MAX.
A
MIN.
MAX.
1.75
A1
1.25
b
0.004
0.25
0.10
A2
0.069
0.31
0.010
0.049
0.51
0.012
0.020
0.010
c
0.17
0.25
0.007
D
4.80
5.00
0.189
0.197
E
5.80
6.20
0.228
0.244
E1
3.80
4.00
0.150
0.157
h
0.25
0.50
0.010
0.020
L
0.40
1.27
0.016
0.050
0o
8o
e
θ
1.27 BSC
0o
aaa
0.050 BSC
8o
0.10
0.004
Note: 1. Followed from JEDEC MS-012 AA.
2. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion or gate burrs shall not exceed 6 mil per side.
3. Dimension “E” does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 10 mil per side.
Copyright © ANPEC Electronics Corp.
Rev. A.3 - Jan., 2011
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APW7165
Carrier Tape & Reel Dimensions
P0
P2
P1
A
B0
W
F
E1
OD0
K0
A0
A
OD1 B
B
T
SECTION A-A
SECTION B-B
H
A
d
T1
Application
A
H
T1
C
d
D
W
E1
F
330.0±
2.00
50 MIN.
12.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
12.0±
0.30
1.75±
0.10
5.5±
0.05
P0
P1
P2
D0
D1
T
A0
B0
K0
4.0±
0.10
8.0±
0.10
2.0±
0.05
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.40
6.40±
0.20
5.20±
0.20
2.10±
0.20
SOP-8
(mm)
Devices Per Unit
Package Type
Unit
Quantity
SOP-8
Tape & Reel
2500
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APW7165
Taping Direction Information
SOP-8
USER DIRECTION OF FEED
Classification Profile
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APW7165
Classification Reflow Profiles
Profile Feature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
3 °C/second max.
3 °C/second max.
183 °C
60-150 seconds
217 °C
60-150 seconds
See Classification Temp in table 1
See Classification Temp in table 2
Time (tP)** within 5°C of the specified
classification temperature (Tc)
20** seconds
30** seconds
Average ramp-down rate (Tp to Tsmax)
6 °C/second max.
6 °C/second max.
6 minutes max.
8 minutes max.
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
Average ramp-up rate
(Tsmax to TP)
Liquidous temperature (TL)
Time at liquidous (tL)
Peak package body Temperature
(Tp)*
Time 25°C to peak temperature
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Package
Thickness
& lt; 2.5 mm
≥2.5 mm
Volume mm
& lt; 350
235 °C
220 °C
3
Volume mm
≥350
220 °C
220 °C
3
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness
& lt; 1.6 mm
1.6 mm – 2.5 mm
≥2.5 mm
Volume mm
& lt; 350
260 °C
260 °C
250 °C
3
Volume mm
350-2000
260 °C
250 °C
245 °C
3
Volume mm
& gt; 2000
260 °C
245 °C
245 °C
3
Reliability Test Program
Test item
SOLDERABILITY
HOLT
PCT
TCT
HBM
MM
Latch-Up
Method
JESD-22, B102
JESD-22, A108
JESD-22, A102
JESD-22, A104
MIL-STD-883-3015.7
JESD-22, A115
JESD 78
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Rev. A.3 - Jan., 2011
19
Description
5 Sec, 245°C
1000 Hrs, Bias @ Tj=125°C
168 Hrs, 100%RH, 2atm, 121°C
500 Cycles, -65°C~150°C
VHBM≧2KV
VMM≧200V
10ms, 1tr≧100mA
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APW7165
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
Copyright © ANPEC Electronics Corp.
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