As I wrote , there is no schematic of this power supply or similar. Is Not even in the Service manual for 42LE5500. http://obrazki.elektroda.pl/9784593700_1489245416_thumb.jpg Only after the apps out there, applied IC Model: 42LE5500-xx LG LED TV 42LE5500 Chassis/Version: LD03E Panel: LC420EUH (SC)(A1) LED driver (backlight): integrated into PSU; / **118V 660mA (42 inch LG) PWM LED driver: AS3693B, MEGA48PA Power Supply (PSU): PLDF-L903A EAY60803101/ 3PCGC10008A-R PWM Power: VIPER27H (Standby), ICE2PCS04 (PFC) and L6599D
austriamicrosystems AG
is now
ams AG
The technical content of this austriamicrosystems datasheet is still valid.
Contact information:
Headquarters:
ams AG
Tobelbaderstrasse 30
8141 Unterpremstaetten, Austria
Tel: +43 (0) 3136 500 0
e-Mail: ams_sales@ams.com
Please visit our website at www.ams.com
AS3693B
austriamicrosystems
Product Specification, Confidential
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AS3693B–16 Channel high precision LED driver for
LCD Backlight
lv
1 General Description
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The AS3693B is a 16 channels high precision LED
controller with build in PWM generators for driving
external FETs in LCD-backlight panels.
External clock and synchronizing inputs allow the
synchronization of the LCD backlight with the TV
picture. Local dimming and scan dimming is
supported by 16 independent PWM generators with
programmable delay, period and duty cycle. Three
free configurable dynamic power feedback circuits
make the device usable for white LED as well as
RGB backlights. Build in safety features include
thermal shutdown as well as open and short LED
detection. All circuit parameters are programmable
via I2C or SPI interface.
Free programmable 12 bit resolution ( period,
high time and delay )
Overvoltage detection ( short LED )
Undervoltage detection ( open LED )
Temperature shutdown
Fault interrupt output
H-Sync, V-Sync inputs to synchronize with TVset
Internal or external PWM – clock
I2C interface
SPI interface
5 bit device - address (sets device address
and interface mode)
Automatic supply regulation feedback
Each output can be assigned to red, green or
blue feedback.
Package epTQFP64 and QFN64
2 Key Features
3 Applications
•
LED backlighting for LCD – TV sets and
monitors
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16 Channel LED driver
Output current only limited by external
transistor
Output voltage 0.4V to 50V
Absolute current accuracy +/- 0.5%
Output slew rate programmable
Current programmable with external resistor
Linear current control with 8 - bit DAC
Linear current control with external analog
voltage
Digital current control with 16 independent
PWM generators
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AS3693B
austriamicrosystems
4 Block Diagram
V2_5
REF
Vreg
FBB
FBG
FBR
Vsupply
Reference,
DAC
PWM
PWM
Fault detectors
PWM
SMPS
feedback
PWM
PWM
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PWM
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PWM
PWM
AS3693B
PWM
PWM
PWM
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PWM
86 byte
registers
PWM
PWM
PWM
Addr2
Addr1
SDA
SCL
CS
SDO
Vsync
Hsync
SPI / I2C
Interface
Fault
PWM
V2_5
Typical application
Vdcdc
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Power Supply
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16 output
channels
100k
10k
Curr1
Rfb1
Gate1
Curr2
Rfb2
Rfb15 Curr16
Gate15
Vsync
Hsync
100k
Curr15
Gate2
Rfb16
Gate16
Rfb
10k
Vreg
SDI
SCLK
xCS
AS3693B
V2_5
FBR
FBG
FBB
10k
Micro
controller
2.2uF
10k
Te
10k
ch
Rvreg
SDO
Fault
Ref(EXT)
V2_5
AGND
GND
ADDR2
ADDR1
Cfb
10uF
Cfb
10uF
Cfb
10uF
( Exposed Pad )
2.2uF
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2.2uF
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AS3693B
austriamicrosystems
Table of Contents
General Description ....................................................................................................................................... 1
Key Features.................................................................................................................................................. 1
Applications.................................................................................................................................................... 1
Block Diagram................................................................................................................................................ 2
Characteristics ............................................................................................................................................... 4
5.1
Absolute Maximum Ratings .................................................................................................................... 4
5.2
Operating Conditions .............................................................................................................................. 5
5.3
Electrical Characteristics......................................................................................................................... 6
6 Typical Operation Characteristics .................................................................................................................. 8
6.1
Output current vs Output Voltage ........................................................................................................... 8
6.2
Vsupply vs VREG and V2.5 at startup .................................................................................................... 8
6.3
9us Slew Rate ......................................................................................................................................... 9
6.4
Supply Regulation ................................................................................................................................... 9
7 Block Description ......................................................................................................................................... 10
7.1
Feedback Circuit ................................................................................................................................... 10
7.1.1
Feedback Selection ....................................................................................................................... 11
7.1.2
Voltage fault registers .................................................................................................................... 12
7.2
Curreg 1-16........................................................................................................................................... 12
7.3
PWM – modes ...................................................................................................................................... 14
7.3.1
SYNC mode (PWM_MODE = 00) .................................................................................................. 14
7.3.2
ASYNC – mode (PWM_MODE = 01) ............................................................................................ 16
7.4
PWM – high time, period and delay registers ....................................................................................... 17
7.5
Shunt Regulator .................................................................................................................................... 18
7.5.1
Undervoltage lockout ..................................................................................................................... 18
7.6
Over temperature control ...................................................................................................................... 18
7.7
Device address setup ........................................................................................................................... 19
7.7.1
I2C Device Address setup ............................................................................................................. 19
7.7.2
SPI Device Address setup ............................................................................................................. 19
7.8
Digital interface ..................................................................................................................................... 20
7.8.1
I2C interface .................................................................................................................................. 20
7.8.2
SPI interface .................................................................................................................................. 22
8 Register map................................................................................................................................................ 24
9 Pinout and Packaging .................................................................................................................................. 27
9.1
Pinout.................................................................................................................................................... 27
9.2
Package drawing epTQFP64 ............................................................................................................... 29
9.3
Package drawing QFN64 ...................................................................................................................... 30
10 Ordering Information .................................................................................................................................... 31
Copyright............................................................................................................................................................. 32
Disclaimer ........................................................................................................................................................... 32
Contact Information ............................................................................................................................................. 32
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1
2
3
4
5
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AS3693B
austriamicrosystems
5 Characteristics
5.1 Absolute Maximum Ratings
Stresses beyond those listed in Table 1 may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated in Section 5
Electrical Characteristics is not implied.
Table 1 – Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Unit
Note
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Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
VDDMAX
Supply for LED’s
-0.3
& gt; 50
V
See notes
VINVREG
VREG supply voltage
-0.3
7.0
V
Applicable for pin VREG
IINVREG
Maximum Vreg current
100
mA
VIN2.5V
2.5 V Pins
-0.3
V2_5+0.3V
V
Applicable for 2.5V pins
VIN5V
5V Pins
-0.3
VREG+
0.3V
V
Applicable for 5V pins
50V Pins
-0.3
55
V
Applicable for CURR1, CURR2,
CURR3 up to CURR16
IIN
Input Pin Current
-25
+25
mA At 25ºC, Norm: Jedec 17
TSTRG
Storage Temperature Range
-55
150
°C
Humidity
5
85
%
Non condensing
-4000
4000
V
Norm: MIL 883 E Method 3015
-2000
2000
V
Norm: MIL 883 E Method 3015
W
At Ta = 25ºC, no airflow for
ePTQFP64 on two layer FR4-Cu
3
PCB
lv
4
2
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VIN50V
VESD
Maximum Current flowing into
Vreg
Electrostatic Discharge on Pins
Curr1 – Curr16
VESD
Electrostatic Discharge on all Pins
PT
Total Power Dissipation
3.8W
PDERATE
PT Derating Factor
40
TBODY
Body Temperature during
Soldering
260
°C
according to IPC/JEDEC J-STD020C
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Notes:
mW/
3
See notes
°C
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1, As the AS3693B is not directly connected to this supply. Only the parameters VINVREG, VIN5V and
VIN50V have to be guaranteed by the application
2, All pins except CURR1 to CURR16 and 2.5V
3, Copper area & gt; 9 cm², thermal vias
4, 2.5V Pins are Fault, SDO, ADDR1 and ADDR2
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AS3693B
austriamicrosystems
5.2 Operating Conditions
Test circuit
Vcurr
Vreg
Curr1
Rfb1
Curr2
Gate1
Rfb2
Curr15
Gate2
Rfb15 Curr16
Gate15
Rfb16
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Vreg
Gate16
SDI
SCLK
xCS
AS3693B
FBR
FBG
FBB
10k
10k
V2_5
SDO
Fault
Ref(EXT)
V2_5
AGND
GND
ADDR2
ADDR1
( Exposed Pad )
2.2uF
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2.2uF
lv
Vsync
Hsync
Table 2 – Operating Conditions
Symbol
Parameter
VDD
Min
Main Supply
Supply (shunt regulated by
AS3693B)
Note
V
Supply is not directly connected to
the AS3693B – see section ‘Shunt
Regulator’
%
Applies only for supply VREG is
connected via Rvdd
VREGEXT
5.0
5.4
V
If internally (shunt-)regulated by
ZD1
4.5
4.9
V
If externally supplied
2.4
Untervoltage lockout voltage
5.2
3
VREGINT
VUVL
Unit
+20
-20
Max
Not
Limited
VDDTOL Main Supply Voltage Tolerance
Typ
2.7
3
V
If Vreg & lt; UVUL current sources
are turned off
( Addr 0x01,Addr 0x02 = 0x00 )
IVREG_M
Gate driving capability
uA
Condition: externally supplied
0.5
1
2
Curr_reg1-16 off (register 01h =
00h, register 02h = 00h)
mA Gate1 – Gate16 output current
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Maximum Current Into VREG –
mA PIN (Supply current + shunt
regulator current).
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EXT_OFF
30
Maximum Supply current
AX
IVREG
20
Supply Current (Chip current
consumption)
ca
IVREG
Excluding current through shunt
regulator (ZD1) – see section
mA ‘Shunt Regulator’. Note: Take care
of the Power dissipation of the
external Resistor.
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AS3693B
austriamicrosystems
5.3 Electrical Characteristics
Table 3 – Analog Electrical Characteristics
Symbol
Parameter
VCURR
Min
Typ
Voltage at CURR1 to CURR16
Max
Unit
50.0
V
+0.5
%
Note
Using 250mV reference
-0.5
@25C TJUNCTION, excluding
variation of external resistors
(1)
ICURR,
-1.5
Current Source Tolerance
TOL
+1.5
%
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Using 250mV reference
-20° to +100°
C
C TJUNCTION,
-20° to +85° TAMB, excluding
C
C
variation of external resistors;
V(CURRx) & lt; = 4.0V
-1.6
+1.6
%
lv
Using DAC reference
VDAC =250mV ( Data = 0x80 )
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@25C TJUNCTION, excluding
variation of external resistors
DAC INL
-4
+4
VC
Automatic Supply Regulation trip
point
0.5
1
VC,GAIN
Automatic Supply Regulation
gain
TOVTEMP
Over temperature Limit
Thyst
Over temperature hysteresis
CLK
Internal Clock for PWM
DAC_INL
Notes:
140
150
10
400
500
V
See section ‘Feedback Circuit
(DCDC_Regulation_Trip_Point)’.
mA/V
2.0
130
LSB DAC integral nonlinearity
Voltage to current ratio; output
current range typ. 0 to 200uA
°C
Maximum junction temperature
(2)
°C
600
KHz Clock for internal PWM generation
1, Accuracy at +100° guaranteed by design and verified by laboratory characterization
C
2, If the temperature exceeds the over temperature limit, the PWM will be turned off. If the temperature
decreases, the PWM is activated again. The register settings are not reset.
Table 4 – Digital Input pins characteristics (SDI,VSYNC,HSYNC,SCL,CS)
Parameter
Min
VIH
High Level Input voltage
VIL
Low Level Input voltage
1.3
VREG
V
-0.3
0.4
V
Maximum SCL Frequency
10
MHz
Maximum HSYNC Frequency
10
MHz
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f_HSYNC
Unit
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f_SCL
Max
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Symbol
Te
ts_VH
Vsync setup time before rising
edge of Hsync
Typ
Note
Output driver is slew rate limited
( Register: Curreg_Control 0x0D )
SYNC-mode:
15
ns
PWM values are updated with first
rising edge of Hsync while Vsync = 1
( see 7.3.1.1 )
th_VH
Vsync hold time after rising edge
of Hsync
15
ns
ts_SCISCL
Setup time SDI,SCL
15
ns
SPI interface mode
th_SCLSCI
Hold time SCL,SDI
15
ns
SPI interface mode
ts_CSSCL
Setup time CS,SCL
15
ns
SPI interface mode
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AS3693B
austriamicrosystems
Parameter
Min
th_SCLCS
Hold time SCL, CS
15
ns
SPI interface mode
1.3
us
I2C interface mode
100
ns
I2C interface mode
160
ns
I2C interface mode
160
ns
I2C interface mode
Bus free time between
tBUF
Stop and Start conditions
Setup time for repeated
Tsetupstart
Start condition
Hold time for repeated
Tholdstart
Start condition
Setup time for
Tsetupstop
Stop condition
Typ
Max
Unit
Note
Table 5 – Digital output pins characteristics (SDO)
Min
VOH
High Level Output voltage
VOL
Low Level Output voltage
Typ
Max
Unit
2.4
2.5
V
-0.3
0.4
V
Note
lv
Parameter
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Symbol
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Symbol
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AS3693B
austriamicrosystems
6 Typical Operation Characteristics
6.1 Output current vs Output Voltage
0,16
0,12
0,1
150mA
0,08
75mA
lv
25mA
0,06
0
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0,02
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0,14
0
5
10
15
20
25
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6.2 Vsupply vs VREG and V2.5 at startup
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Channel 1 = VREG
Channel 2 = V2_5
Channel3 = Vsupply
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AS3693B
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6.3 9us Slew Rate
Channel 1 = Voltage on Current Source
Channel 2 + Voltage on RES Pin
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6.4 Supply Regulation
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Channel 1 = DCDC VOUT (30V)
Channel 2 = Voltage on RES Pin
Channel 3 = Voltage on Curr Pin
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AS3693B
7
austriamicrosystems
Block Description
7.1 Feedback Circuit
The AS3693B supports a flexible feedback selection for external DCDC – supplies. Beside the default setup for
RGGB lighting, each channel can be assigned to an external DCDC feedback loop. This feedback circuit is
important to reduce power dissipation of the device.
Table 6 – Feedback Control
Addr: 04h
Enables and Disables the Different Feedback modes
Default
Access
0
Feedback on
1
R/W
1
Feedback on PWM
0
R/W
2
Open_Led_Det_on
0
R/W
3
Short_det_on
5:4
Short Led Detect
Voltage(VSL)
7:6
DCDC_Regulation_tri
p Point (VC)
Description
1 = Feedback Circuit is active
0 = The entire Feedback Loop is disabled
0 = The Feedback Regulator is always active
1 = The Feedback Regulator is only active, if PWM = 1
Enables open Led Detection Comparators
0 = Open Led Detection Disabled
1 = Open Led Detection Enabled, Level: Ucurrx = 50mV
Enables Short detection
0 = Short detection off
1 = Sort detection on.
Short led Detection Trip Voltage ( debounced 3mS )
00 = 2V
01 = 3V
Trip Point voltage of the DCDC-Feedback Regulation
Circuit. (NOTE: This value has to be adjusted if Analog
Ref select Bit is changed.)
00 = 0.5V (Note use for Currents up to 70 mA)
01 = 0.6V (Note use for Currents up to 80 mA)
10 = 0.8V (Note use for Currents up to 110 mA)
11 = 1.0V (Note use for Currents up to 150 mA)
lv
Bit Name
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Feedback control
0
R/W
R/W
00
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R/W
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AS3693B
7.1.1
austriamicrosystems
Feedback Selection
In the AS3693B, each led – string feedback can be assigned to the specific led-supply, to minimize the power
consumption in the system. It can be chosen in between FBR, FBG and FBB.
DCDC Converter
for VDD
(Internal or externa)l
From main
supply
R1
R3
Vfb
R2
C1
Feedback resistor divider
(part of DCDC converter circuit)
AS3693B
lv
ANALOG REGULATION
CIRCUIT
16 REGULATORS
3...16
2
1
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Voltage Feedback
input for DCDC
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FB R
FB G
FB B
NOFB
VC
SHORTLED
VSL
OPENLED
VOL
REF
R5
Table 7 – Feedback Selection
Addr: 05h,06h,07h,08h
Feedback Select 1-4
This register controls the Feedback of the Automatic feedback loop
Bit Name
Default
Access
1:0
FB1_Select
FB5_Select
FB9_Select
FB13_Select
00
R/W
FB2_Select
FB6_Select
FB10_Select
FB14_Select
01
R/W
5:4
FB3_Select
FB7_Select
FB11_Select
FB15_Select
01
R/W
7:6
FB4_Select
FB8_Select
FB12_Select
FB16_Select
10
R/W
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Bit
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Description
Selects the feedback of the voltage regulators
00= regulator on FBR
01= regulator on FBG
10= regulator on FBB
11= regulator not connected to FB
Selects the feedback of the voltage regulators
00= regulator on FBR
01= regulator on FBG
10= regulator on FBB
11= regulator not connected to FB
Selects the feedback of the voltage regulators
00= regulator on FBR
01= regulator on FBG
10= regulator on FBB
11= regulator not connected to FB
Selects the feedback of the voltage regulators
00= regulator on FBR
01= regulator on FBG
10= regulator on FBB
11= regulator not connected to FB
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AS3693B
austriamicrosystems
7.1.2 Voltage fault registers
In this registers an open or short led fault can be detected. If an open or short led error occurs, pin fault is pulled
to 0 (3 ms debounced ).
Remark: At 100% PWM duty cycle, short led fault detection is not available. Please set PWM to 99% duty cycle.
Open led fault detection is available at 100% PWM duty cycle.
Table 8 – Fault Registers
Addr: 09h-0ch
Voltage Fault 1,2,3,4
Bit Name
Access
00
R
Shows a error on any led string
00 = no fault
01 = open led
10 = short led
R
Shows a error on any led string
00 = no fault
01 = open led
10 = short led
Fault_Reg 1
Fault_Reg 5
Fault_Reg 9
Fault_Reg 13
Fault_Reg 2
1:0
Fault_Reg 6
Fault_Reg 10
Fault_Reg 14
Fault_Reg 3
Fault_Reg 7
Fault_Reg 11
Fault_Reg 15
Fault_Reg 4
5:4
00
00
R
Shows a error on any led string
00 = no fault
01 = open led
10 = short led
00
Fault_Reg 8
Fault_Reg 12
Fault_Reg 16
7:6
Description
R
Shows a error on any Led string
00 = no Fault
01 = open Led
10 = short Led
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3:2
7.2
Default
lv
Bit
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This register shows a fault on any led string
Curreg 1-16
Each current source can be turned on and off separately.
Table 9 –Reg. Control 1
Addr: 01h
Reg. Control1
Bit Name
7:0
Default
Access
Curreg 1-8_ON
R/W
Description
Enables or disables the current regulators
0 = regulator off
1 = regulator on
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Bit
00000000
This register enables or disables the curreg 1 - 8
Table 10– Reg.Control 2
Reg. Control2
This Register enables or disables the curreg 9-16
Bit
Bit Name
Default
Access
7:0
Curreg 9 -16_ON
00000000
Te
Addr: 02h
R/W
www.austriamicrosystems.com
Description
Enables or disables the current regulators
0 = regulator off
1 = regulator on
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AS3693B
austriamicrosystems
Table 11 –CURREG_CONTROL
Addr: 0dh
Curreg Control
Controls Rise, Fall times and References of the Curreg.
Bit
Bit Name
Default
Access
R/W
3:2
SLEW_RATE_CONT
ROL
00
R/W
5:4
PWM_LOW_LEVEL
00
R/W
7
boost mode
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lv
Analog Ref Select
Voltage reference for the current regulators can be
chosen with these options.
00 = 250mV reference
01 = external reference
10 = DAC reference
11 = do not use
SLEW – RATE – Control. Adjusts the rise and fall time of
the current switching
00 = typ. 9us
01 = typ. 6us
10 = typ. 3us
11 = typ. 1us
Note: Test bits for internal use only
Gives +30% current.
only available in internal reference mode.
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Description
0
R/W
AS3693B
Reference Sources
Analog Ref Select
3-16
2
0,5% VREF 250mV
1
PWM
8Bit DAC
0...500mV
External Reference
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Curreg
Table 12 – Ref_DAC_Voltage
ch
Addr: 0eh
Bit Name
Te
Bit
7…0
Ref_DAC_Voltage
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Ref_DAC_Voltage
The Regulation Voltage can be chosen in this register
Default
00
Access
Description
R/W
Reference voltage for current regulators. (Note: If Analog
Ref Select = 10, the regulation voltage can be adjusted
here.
00000000 = 0mV
00000001
…
01111111 = 250 mV
..
11111111= 500mV
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AS3693B
austriamicrosystems
7.3
PWM – modes
Table 14– PWM CONTROL
Addr: 0fh
PWM_MODE
Controls the different PWM modes and Internal or external PWM
Default
Access
PWM_MODE
01
R/W
2
PWM INT/EXT
1
R/W
3
VSYNC_INVERT
0
R/W
4
PWMINVERT
00 Sync mode
01 Async - mode
10 not used
11 not used
NOTE: Sync mode can only be used with
PWM INT = 0.
0 PWM generator uses external H and Vsync clock
1 PWM generator uses internal 500kHz clock.
0 VSYNC active high (PWM triggers on rising edge)
1 VSYNC active low (PWM triggers on falling edge)
0 PWM normal (PWM starts with “1” after delay)
1 PWM inverted(PWM starts with “0” after delay)
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te G
nt
st
il
1:0
Description
al
id
Bit Name
lv
Bit
0
R/W
Note: If Vsync or Hsync is not used, connect it to GND.
7.3.1
SYNC mode (PWM_MODE = 00)
In this mode the PWM is synchronized with VSYNC and HSYNC.
Reg: N
Vsync
Delay
Reset
Or
R
Hsync
Counter
Reg: P
Compare
Compare
PWMINVERT( Register 0x0F )
ca
Reg: M
PWM
Te
ch
ni
Setup options:
Delay (N) = registers 0h32 to 0h51
High Time (M) = registers 0h12 to 0h31
PWM Period (P) = register 0h10
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Revision 1.21 / 2011-09-30
14 - 32
AS3693B
austriamicrosystems
P WM duration = t
vsyn
c
V sync
Hs ync
P WM
Reset
P*t & gt; t
reset with Vsync
h c
syn
vs c
yn
Delay =N * t
h yn
s c
P WM
P WM s ignal: High time = M * t
h c
syn
h c
syn
v c
syn
P WM
P WM s ignal: High time = M * t
h c
syn
am
lc s
on A
te G
nt
st
il
Example: Two PWM output channels with fixed delays and variable high times (HT)
PWMINVERT = 0
PWMINVERT = 1
Restart
P WM P eriode = P * t hsync
h c
syn
lv
P*t & lt; t
Repetitive PWM
reset with P * t
al
id
P WM P eriode = t vsyunc
ca
7.3.1.1 SYNC – mode PWM – generator update cycle.
ch
ni
-Store new values from serial interface
-Update delay immediately
VSYNC
-no new data
-new data
Update HighTime, Period
Te
Delayed
VSYNC
(internal)
PWM
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Revision 1.21 / 2011-09-30
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AS3693B
austriamicrosystems
Shift new data
in PWM – State
maschine
Restart PWM
VSYNC
al
id
HSYNC
lv
7.3.2 ASYNC – mode (PWM_MODE = 01)
This PWM is synchronized with Hsync or internal 500KHz clock. The registers are updated with each serial data.
am
lc s
on A
te G
nt
st
il
Reset
Vsync
R
Hsync
Reg: P
Counter
Compare
Compare
Reg: M
PWM
PWMINVERT( Register 0x0F )
High time (M) = registers 0h12 to 0h 31
PWM period (P) = register 0h10
Hs ync
AsyncMode
ca
Repetitive PWM
no Reset
Syncronized on Hsync or
internal
Clock
P WM
P WM s ignal: High time = M * t
h
sync
Te
ch
ni
P WM P eriode = P * t hsync
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Revision 1.21 / 2011-09-30
16 - 32
AS3693B
austriamicrosystems
7.4 PWM – high time, period and delay registers
Table 15 – Curreg1-16_DELAY_LSB
Addr: 32h – 50h
CURREGX_DELAY_LSB
7:0
Bit Name
Default
Access
R/W
CurregX_DELAY_LSB
Description
Defines the delay time of the PWM
lv
Table 16 – Curreg1-16_DELAY_MSB
Addr: 32h-51h
CURREGX_DELAY_LSB
am
lc s
on A
te G
nt
st
il
Defines delay of the different PWM’s
Bit
3:0
al
id
Bit
00000000
Defines delay of the different PWM’s
Bit Name
Default
Access
CurregX_DELAY_MSB
0000
R/W
Description
Defines the delay time of the PWM
Table 17– PWM_PERIOD_LSB
Addr: 10h
PWM – Period – LSB
Bit
Bit Name
Default
Access
7:0
PWM_PERIOD_LSB
11111111
Defines PWM – Periode
R/W
Description
Defines the period of the PWM
Table 18– PWM_PERIOD_MSB
Addr: 11h
PWM – Period – MSB
ca
Defines PWM – Periode
Bit Name
Default
Access
3:0
PWM_PERIOD_MSB
0000
R/W
Description
Defines the period of the PWM
ni
Bit
ch
Table 19– Curreg1-16_HT_LSB
Addr: 12h-30h
CURREGX_HT_LSB
Defines High Time of PWM
Bit Name
Default
Access
7:0
Curreg1_HT_LSB
0
R/W
Te
Bit
www.austriamicrosystems.com
Description
Defines PWM high time
Revision 1.21 / 2011-09-30
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AS3693B
austriamicrosystems
Table 20– Curreg1-16_HT_MSB
Addr: 13h-31h
CURREGX_HT_MSB
Defines High Time of PWM
Bit
Bit Name
Default
Access
3:0
Curreg1_HT_MSB
0000
R/W
Description
Defines PWM high time
al
id
7.5 Shunt Regulator
The supply of the AS3693B is generated from the high voltage supply. To obtain a 5V regulated supply, a series
resistor Rvdd is used together with an internal zener diode (ZD1). An external capacitor Cvdd is used to filter the
supply on the pin VREG.
VDDMIN is the minimum voltage of the
supply, where Rvdd is connected
VDDMIN − 5,4V
20mA
am
lc s
on A
te G
nt
st
il
Rvdd =
lv
The external resistor Rvdd has to be choosen according to the following formula:
This ensures enough supply current (IVREGMAX) for the AS3693B under minimum supply voltage VDDMIN.
If a stable 5V supply within the operating conditions limits of VREGEXT is already existing in the system it is
possible to supply the AS3693B directly. In this case remove the resistor Rvdd and connected this supply
directly to VREG.
7.5.1 Undervoltage lockout
The undervoltage lockout is an additional safety feature to prevent LED-current under abnormal Vreg conditions.
If the supply voltage Vreg is below 2.7V (e.g. device is supplied only by the voltage of the serial interface ) the
registers Reg.Control1 and RegControl2 (0x01 and 0x02) are reset. This turns off all current sinks.
Vreg
3V to 5.4V
Reset
Register 0x01
Reset
Register 0x02
ni
ca
2.7V
ch
7.6 Over temperature control
Table 14– Overtemp Control
Te
Addr:55h
Over temperature Control
Controls the temperature functions
Bit
Bit Name
Default
Access
0
overtemp_on
1
R/W
1
ov_temp
0
R/W
www.austriamicrosystems.com
Description
Enables the over temperature protection
0 = Protection off
1 = Protection on
Displays temperature status
0 = Normal operation
1 = Over temperature shutdown
Revision 1.21 / 2011-09-30
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AS3693B
austriamicrosystems
7.7 Device address setup
The I2C and SPI – Device address can be set via PIN ADDR1 and ADDR2. The AS3693B offers 31 I2C or 32
SPI addresses, which can be set via external resistor. ADDR2 bit 2 decides if I2C or SPI interface is used.
AS3693
Flexible 6- Bit Address Programming
with 2 external resistors.
al
id
Digital
Digital Registers
PWM - Generator
6 Bit I2C ADDRESS
ADDR1
ADDR2
R2
am
lc s
on A
te G
nt
st
il
R1
lv
ADC
Table 13– Device Address
Device Adress Setup:
I2C ADDRESS
I2C ADDRESS Options
Bit
Bit Name
Default
Device ADDR1
5:3
000
Device ADDR2
000
R
ni
ch
Description
Lower 3 bits of device address
Note: don’t use address 00h
000 open
001 320k
010 160k
011 80k
100 40k
101 20k
110 10k
111 0
Upper 3 bits of device address
000 open Note: activates I2C - mode
001 320k Note: activates I2C - mode
010 160k Note: activates I2C - mode
011 80k Note: activates I2C - mode
100 40k Note: activates SPI - mode
101 20k Note: activates SPI - mode
110 10k Note: activates SPI - mode
111 0
Note: activates SPI – mode
R
ca
2:0
Access
7.7.1 I2C Device Address setup
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0 (ADDR2 & lt; 2 & gt; )
ADDR2 & lt; 1 & gt;
ADDR2 & lt; 0 & gt;
ADDR1 & lt; 2 & gt;
ADDR1 & lt; 1 & gt;
ADDR1 & lt; 0 & gt;
R/W
Te
BIT 7
0
7.7.2 SPI Device Address setup
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0
0
1 (ADDR2 & lt; 2 & gt; )
ADDR2 & lt; 1 & gt;
ADDR2 & lt; 0 & gt;
ADDR1 & lt; 2 & gt;
ADDR1 & lt; 1 & gt;
ADDR1 & lt; 0 & gt;
www.austriamicrosystems.com
Revision 1.21 / 2011-09-30
19 - 32
AS3693B
7.8
austriamicrosystems
Digital interface
The AS3693B can be controlled with two types of interfaces.
7.8.1 I2C interface
7.8.1.1 Feature List
al
id
Fast-mode capability (max. SCL-frequency is 400 kHz)
Write formats:
Single-Byte-Write, Page-Write
Read formats:
Current-Address-Read, Random-Read, Sequential-Read
SDA input delay and SCL spike filtering by integrated RC-components
•
•
•
•
7.8.1.2 Transfer Formats
2
DW
A
WA
A
reg_data
S
Sr
DW
DR
WA
A
N
P
white field
grey field
WA++
A P
write register,
WA++
2
START condition after STOP
repeated START
device address for write
device address for read
word address
acknowledge
no acknowledge
stop condition
slave as receiver
slave as transmitter
increment word address internally
am
lc s
on A
te G
nt
st
il
S
lv
Figure 1 – I C Byte-Write:
Figure 2 – I C Page-Write:
S
DW
A
WA
A
reg_data 1
A
reg_data 2
…
A
reg_data n
write register
WA++
write register
WA++
A P
write register
WA++
Byte-Write and Page-Write are used to write data to the slave.
The transmission begins with the START condition, which is generated by the master when the bus is in IDLE
state (the bus is free). The device-write address is followed by the word address. After the word address any
number of data bytes can be send to the slave. The word address is incremented internally, in order to write
subsequent data bytes on subsequent address locations.
ni
ca
For reading data from the slave device, the master has to change the transfer direction. This can be done either
with a repeated START condition followed by the device-read address, or simply with a new transmission START
followed by the device-read address, when the bus is in IDLE state. The device-read address is always followed
st
by the 1 register byte transmitted from the slave. In Read-Mode any number of subsequent register bytes can
be read from the slave. The word address is incremented internally.
ch
The diagrams below show various read formats available:
2
Figure 3 – I C Random-Read:
DW
A
Te
S
WA
A Sr
DR
A
data
read register
WA++
N P
WA++
Random-Read and Sequential-Read are combined formats. The repeated START condition is used to change
the direction after the data transfer from the master.
The word address transfer is initiated with a START condition issued by the master while the bus is idle. The
START condition is followed by the device-write address and the word address.
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Revision 1.21 / 2011-09-30
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AS3693B
austriamicrosystems
st
In order to change the data direction a repeated START condition is issued on the 1 SCL pulse after the
acknowledge bit of the word address transfer. After the reception of the device-read address, the slave becomes
the transmitter. In this state the slave transmits register data located by the previous received word address
vector. The master responds to the data byte with a not-acknowledge, and issues a STOP condition on the bus.
2
Figure 4 – I C Sequential-Read:
A
WA
A Sr
DR
A
A
data 2
A
data n
read register
WA++
al
id
DW
data 1
…
S
N P
WA++
2
am
lc s
on A
te G
nt
st
il
lv
Sequential-Read is the extended form of Random-Read, as more than one register-data bytes are transferred
subsequently. In difference to the Random-Read, for a sequential read the transferred register-data bytes are
responded by an acknowledge from the master. The number of data bytes transferred in one sequence is
unlimited (consider the behavior of the word-address counter). To terminate the transmission the master has to
send a not-acknowledge following the last data byte and generate the STOP condition subsequently.
Figure 5 – I C Current-Address-Read:
S
DR
A
data 1
read register
WA++
A
data 2
…
read register
WA++
A
data n
read register
WA++
N P
WA++
Te
ch
ni
ca
To keep the access time as small as possible, this format allows a read access without the word address transfer
in advance to the data transfer. The bus is idle and the master issues a START condition followed by the DeviceRead address. Analogous to Random-Read, a single byte transfer is terminated with a not-acknowledge after the
st
1 register byte. Analogous to Sequential-Read an unlimited number of data bytes can be transferred, where the
data bytes has to be responded with an acknowledge from the master. For termination of the transmission the
master sends a not-acknowledge following the last data byte and a subsequent STOP condition.
www.austriamicrosystems.com
Revision 1.21 / 2011-09-30
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AS3693B
7.8.2
austriamicrosystems
SPI interface
SPI – Interface Pins
OUTPUT
Digital
SDI
Control -Registers
PWM - Generator
SCL
CS
FAULT
SDO
al
id
VSYNC
HSYNC
lv
ADDR1 ADDR2
am
lc s
on A
te G
nt
st
il
SPI Mode – Digital Interface Pins:
CS(N)
Chip Select input
SDO
Serial Data output
SDI
Serial Data input
SCL
Serial Clock input
VSYNC
Video Sync signal input
HSYNC
Video Sync signal input
ADDR1
Device Address pins (can be
ADDR2
set via resistor).
7.8.2.1 Read Sequence
CS1
0
1
SCK
2
3
4
5
6
7
8
9
7
6
5
4
3
2
11
12
13
14
1
0
7 Bit Register Address
1
6
0
5
4
3
2
15
16
17
18
7
8 Bit Device Address
SDI
(SDA)
10
6
5
19
20
21
22
23
2
1
0
R/W
1
Data Out
High Impedance
4
3
ca
SDO
Te
ch
ni
7.8.2.2 Page Read Sequence
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Revision 1.21 / 2011-09-30
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AS3693B
austriamicrosystems
7.8.2.3 Write Sequence
CS1
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
TWC
SCL
8 Bit Device Address
SDI
(SDA)
7
6
5
4
3
R/W
7 Bit Address
2
0
1
5
6
4
3
10
11
2
1
12
13
0
Data Byte
0
7
6
5
4
3
2
1
0
al
id
High Impedance
SDO
CS1
1
2
3
4
5
6
7
8
9
8 Bit Device Address
SDI
(SDA)
7
6
5
CS1
24
25
7
6
SCK
4
26
3
27
7 Bit Register Address
2
28
1
6
0
5
4
3
29
30
31
32
33
34
2
1
0
7
6
5
Data Byte 2
15
16
17
18
19
20
21
22
23
5
4
3
35
R/W
1
2
36
0
0
Data Byte 1
7
37
38
1
0
5
Data Byte 3
4
3
4
3
2
1
0
39
2
6
Data Byte n (32 max)
7
6
5
4
3
2
1
0
Te
ch
ni
ca
SD
(SDA)
14
am
lc s
on A
te G
nt
st
il
0
SCK
lv
7.8.2.4 Page Write Sequence
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Revision 1.21 / 2011-09-30
23 - 32
AS3693B
austriamicrosystems
8 Register map
Name
Def
ault
B7
b6
b5
B4
b3
b2
b1
b0
Reg. Control1
01h
00h
Curreg
8_ON
Curreg7
_ON
Curreg6
_ON
Curreg5
_ON
Curreg4
_ON
Curreg
3_ON
Curreg
2_ON
Curreg1
_ON
Reg Control 2
02h
00h
Curreg
16_ON
Curreg1
5_ON
Curreg1
4_ON
Curreg1
3_ON
Curreg1
2_ON
Curreg
11_ON
Curreg
10_ON
Curreg9
_ON
Short_Led Detect
Voltage
SHORT
_DET_
ON
OPEN_
LED
_DET
_ON
Feedba
ck_on_
PWM
FEEDB
ACK_O
N
al
id
Addr
Feedback Control
04h
01h
DCDC_REGULATI
ON_TRIP_POINT
Fedback Select 1
05h
94h
FB4_ Select
FB3_ Select
FB2_ Select
Fedback Select 2
06h
94h
FB8_ Select
FB7_ Select
FB6_ Select
FB5_ Select
Fedback Select 3
07h
94h
FB12_ Select
FB11_ Select
FB10_ Select
FB9_ Select
Fedback Select 4
08h
94h
FB16_ Select
FB15_ Select
FB14_ Select
FB13_ Select
Voltage_Fault 1
09h
00h
Fault_Reg4
Fault_Reg3
Fault_Reg2
Fault_Reg1
Voltage_Fault 2
0Ah
00h
Fault_Reg8
Fault_Reg7
Fault_Reg6
Fault_Reg5
Voltage_Fault 3
0Bh
00h
Fault_Reg12
Fault_Reg11
Fault_Reg10
Fault_Reg9
Voltage_Fault 4
0Ch
00h
Fault_Reg16
Fault_Reg15
Fault_Reg14
Fault_Reg13
CURREG_CONTR
OL
0Dh
00h
PWM_LOW_LEVE
L
RC_SEL
Select Ref
Ref_DAC_Voltage
0Eh
00h
PWM –CONTROL
0Fh
04h
PWMPERIOD_LSB
10h
FFh
PWM-PERIODMSB
11h
00h
Curreg1_HT_LSB
12h
00h
Curreg1_HT_MSB
13h
00h
Curreg2_HT_LSB
14h
00h
Curreg2_HT_MSB
15h
00h
lv
am
lc s
on A
te G
nt
st
il
switch_
output_
driver
boost
mode
Vref_DAC
PWM
INVER
T
00h
Curreg3_HT_MSB
17h
18h
00h
Curreg4_HT_MSB
19h
1Ah
00h
Curreg5_HT_MSB
1Bh
1Ch
00h
Curreg6_HT_MSB
1Dh
1Eh
00h
Curreg7_HT_MSB
1Fh
20h
00h
Curreg2_HT_MSB
00h
Curreg8_HT_LSB
Curreg2_HT_LSB
00h
Curreg7_HT_LSB
Curreg1_HT_MSB
00h
Curreg6_HT_LSB
www.austriamicrosystems.com
PWM - MODE
Curreg1_HT_LSB
00h
Curreg5_HT_LSB
PWMINT/EX
T
PWM – period - MSB
00h
Curreg4_HT_LSB
VSYNC
_INVER
T
PWM –PERIOD - LSB
ca
ni
16h
ch
Curreg3_HT_LSB
Te
FB1_Select
Curreg3_HT_LSB
Curreg3_HT_ MSB
Curreg4_HT_LSB
Curreg4_HT_ MSB
Curreg5_HT_LSB
Curreg5_HT_ MSB
Curreg6_HT_LSB
Curreg6_HT_ MSB
Curreg7_HT_LSB
Curreg7_HT_ MSB
Curreg8_HT_LSB
Revision 1.21 / 2011-09-30
24 - 32
AS3693B
austriamicrosystems
Name
Curreg8_HT_MSB
21h
00h
Curreg9_HT_LSB
22h
00h
Curreg9_HT_MSB
23h
00h
Curreg10_HT_LSB
24h
00h
Curreg10_HT_MSB
25h
00h
Curreg11_HT_LSB
26h
00h
Curreg11_HT_MSB
27h
00h
Curreg12_HT_LSB
28h
00h
Curreg12_HT_MSB
29h
00h
Curreg13_HT_LSB
2Ah
00h
Curreg13_HT_MSB
2Bh
00h
Curreg14_HT_LSB
2Ch
00h
Curreg14_HT_MSB
2Dh
00h
Curreg15_HT_LSB
2Eh
Curreg15_HT_MSB
2Fh
00h
Curreg16_HT_LSB
30h
00h
Curreg16_HT_MSB
31h
00h
Curreg1_DELAY_L
SB
32h
00h
Curreg1_ DELAY
_MSB
33h
00h
Curreg2_ DELAY
_LSB
34h
00h
Curreg2_ DELAY
_MSB
35h
00h
Curreg3_ DELAY
_LSB
36h
00h
Curreg3_ DELAY
_MSB
37h
00h
Curreg4_ DELAY
_LSB
38h
00h
Curreg4_ DELAY
_MSB
39h
00h
Curreg5_DELAY_L
SB
3Ah
00h
Curreg5_DELAY_M
SB
3Bh
Curreg6_DELAY_L
SB
3Ch
00h
Curreg6_DELAY_M
SB
3Dh
00h
Curreg7_DELAY_L
SB
3Eh
00h
Curreg7_DELAY_M
SB
3Fh
00h
Curreg8_DELAY_L
SB
40h
00h
B7
b6
b5
B4
b2
b1
b0
Curreg8_HT_ MSB
Curreg9_HT_LSB
Curreg9_HT_ MSB
Curreg10_HT_LSB
Curreg10_HT_ MSB
Curreg11_HT_LSB
Curreg11_HT_ MSB
Curreg12_HT_LSB
Curreg12_HT_MSB
Curreg13_HT_LSB
Curreg13_HT_MSB
Curreg14_HT_LSB
Curreg14_HT_MSB
Curreg15_HT_LSB
am
lc s
on A
te G
nt
st
il
00h
Curreg15_HT_MSB
Curreg16_HT_LSB
Curreg16_HT_MSB
Curreg1_DELAY_LSB
Curreg1_DELAY_MSB
Curreg2_DELAY_LSB
Curreg2_DELAY_MSB
Curreg3_DELAY_LSB
Curreg3_DELAY_ MSB
ca
Curreg4_DELAY_LSB
Curreg4_DELAY_ MSB
Curreg5_DELAY_LSB
ni
ch
Te
b3
al
id
Def
ault
lv
Addr
00h
www.austriamicrosystems.com
Curreg5_DELAY_ MSB
Curreg6_DELAY_LSB
Curreg6_DELAY_ MSB
Curreg7_DELAY_LSB
Curreg7_DELAY_ MSB
Curreg8_DELAY_LSB
Revision 1.21 / 2011-09-30
25 - 32
AS3693B
austriamicrosystems
Curreg8_DELAY_M
SB
41h
00h
Curreg9_DELAY_L
SB
42h
00h
Curreg9_DELAY_M
SB
43h
00h
Curreg10_DELAY_
LSB
44h
00h
Curreg10_DELAY_
MSB
45h
00h
Curreg11_DELAY_
LSB
46h
00h
Curreg11_DELAY_
MSB
47h
00h
Curreg12_DELAY_
LSB
48h
00h
Curreg12_DELAY_
MSB
49h
00h
Curreg13_DELAY_
LSB
4Ah
00h
Curreg13_DELAY_
MSB
4Bh
00h
Curreg14_DELAY_
LSB
4Ch
00h
Curreg14_DELAY_
MSB
4Dh
00h
Curreg15_DELAY_
LSB
4Eh
00h
Curreg15_DELAY_
MSB
4Fh
00h
Curreg16_DELAY_
LSB
50h
00h
Curreg16_DELAY_
MSB
51h
00h
Overtemp control
55h
b5
B4
b3
b2
b1
b0
Curreg8_DELAY_ MSB
Curreg9_DELAY_LSB
Curreg9_DELAY_ MSB
Curreg10_DELAY_LSB
Curreg10_DELAY_ MSB
Curreg11_DELAY_LSB
Curreg11_DELAY_ MSB
Curreg12_DELAY_LSB
Curreg12_DELAY_MSB
Curreg13_DELAY_LSB
Curreg13_DELAY_MSB
Curreg14_DELAY_LSB
Curreg14_DELAY_MSB
Curreg15_DELAY_LSB
Curreg15_DELAY_MSB
Curreg16_DELAY_LSB
Curreg16_DELAY_LSB
ca
ASIC ID2
b6
5Ch
5Dh
ov_temp
01h
CAh
1
1
0
0
5Xh
0
1
0
1
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ASIC ID1
B7
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Def
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Addr
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Name
1
0
ov_temp
_on
1
0
REVISION
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Revision code:
0x8… initial version November 2008
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AS3693B
austriamicrosystems
9 Pinout and Packaging
9.1 Pinout
Table 5 – Pinlist
Name
Type
Description
1
GATE16
AIO
Connect to Gate of External Transistor
2
RFB1
AIO
Connect to Source of External Transistor and to Resistor RSET
3
GATE1
AIO
Connect to Gate of External Transistor
4
CURR_sense1
AIO
Connect to Drain of external Transistor (input for Open and Short led detection)
5
FBG
AIO
Automatic supply regulation for GREEN led strings; if not
used, leave open
6
FBB
AIO
Automatic supply regulation for BLUE led strings; if not
used, leave open
7
REF(EXT)
AI
8
GND(SENSE)
AIO
9
VREG
AIO
10
V2_5
11
ADDR2
12
ADDR1
13
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Reference pin for PWM = 1 voltage, if not used leave open
GND supply connection (sense)
Shunt regulator supply; connect to Rvdd and
Cvdd
Digital supply, connect 1uF blocking capacitor
AIO
Connect to external resistor for serial interface address selection,
AIO
Connect to external resistor for serial interface address selection.
CURR_sense2
AIO
Connect to Drain of external Transistor (input for Open and Short led detection)
14
GATE2
AIO
Connect to Gate of External Transistor
15
RFB2
AIO
Connect to Source of External Transistor and to Resistor RSET
16
GATE3
AIO
Connect to Gate of External Transistor
17
RFB3
AIO
Connect to Source of External Transistor and to Resistor RSET
18
CURR_sense3
AIO
Connect to Drain of external Transistor (input for Open and Short led detection)
19
GATE4
AIO
Connect to Gate of External Transistor
20
RFB4
AIO
Connect to Source of External Transistor and to Resistor RSET
21
CURR_sense4
AIO
Connect to Drain of external Transistor (input for Open and Short led detection)
22
GATE5
23
RFB5
24
ca
AIO
Connect to Gate of External Transistor
AIO
Connect to Source of External Transistor and to Resistor RSET
CURR_sense5
AIO
Connect to Drain of external Transistor (input for Open and Short led detection)
25
CURR_sense6
AIO
Connect to Drain of external Transistor (input for Open and Short led detection)
26
RFB6
AIO
Connect to Source of External Transistor and to Resistor RSET
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ni
AIO
GATE6
AIO
Connect to Gate of External Transistor
28
CURR_sense7
AIO
Connect to Drain of external Transistor (input for Open and Short led detection)
29
RFB7
AIO
Connect to Source of External Transistor and to Resistor RSET
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27
30
GATE7
AIO
Connect to Gate of External Transistor
31
CURR_sense8
AIO
Connect to Drain of external Transistor (input for Open and Short led detection)
32
RFB8
AIO
Connect to Source of External Transistor and to Resistor RSET
33
GATE8
AIO
Connect to Gate of External Transistor
34
RFB9
AIO
Connect to Source of External Transistor and to Resistor RSET
35
GATE9
AIO
Connect to Gate of External Transistor
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Revision 1.21 / 2011-09-30
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AS3693B
austriamicrosystems
Table 5 – Pinlist
Pin
Name
Type
36
CURR_sense9
AIO
37
FBR
AIO
38
VSYNC
DI
Video sync signal , NOTE: Connect to GND in ASYNC MODE
39
HSYNC
DI
Video sync signal or external clock input in ASYNC mode
40
CS
DI
SPI : CS – function, I2C: connect to GND
41
SCL
DI
SPI/ I2C: Serial interface clock input.
42
SDA
DI
SPI/ I2C: Serial interface data I/O.
43
SDO
DO
SPI: digital data output, I2C: leave open
44
FAULT
DO
FAULT PIN, open drain output. Connect pull up resistor to V2_5
45
CURR_sense10
AIO
Connect to Drain of external Transistor (input for Open and Short led detection)
46
GATE10
AIO
Connect to Gate of External Transistor
47
RFB10
AIO
Connect to Source of External Transistor and to Resistor RSET
48
GATE11
AIO
Connect to Gate of External Transistor
49
RFB11
AIO
Connect to Source of External Transistor and to Resistor RSET
50
CURR_sense11
AIO
Connect to Drain of external Transistor (input for Open and Short led detection)
51
GATE12
AIO
Connect to Gate of External Transistor
52
RFB12
AIO
Connect to Source of External Transistor and to Resistor RSET
53
CURR_sense12
AIO
Connect to Drain of external Transistor (input for Open and Short led detection)
54
GATE13
AIO
Connect to Gate of External Transistor
55
RFB13
AIO
Connect to Source of External Transistor and to Resistor RSET
56
CURR_sense13
AIO
Connect to Drain of external Transistor (input for Open and Short led detection)
57
CURR_sense14
AIO
Connect to Drain of external Transistor (input for Open and Short led detection)
58
RFB14
AIO
Connect to Source of External Transistor and to Resistor RSET
59
GATE14
AIO
Connect to Gate of External Transistor
60
CURR_sense15
AIO
Connect to Drain of external Transistor (input for Open and Short led detection)
61
RFB15
AIO
Connect to Source of External Transistor and to Resistor RSET
62
GATE15
AIO
Connect to Gate of External Transistor
63
CURR_sense16
AIO
Connect to Drain of external Transistor (input for Open and Short led detection)
64
RFB16
AIO
Connect to Source of External Transistor and to Resistor RSET
VSS Supply connection; add as many vias to
ground plane as possible.
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Connect to Drain of external Transistor (input for Open and Short led detection)
Automatic supply regulation for RED led strings; if not
used, leave open
ni
65
(EP)
Description
GND
S
Te
ch
AIO…Analog pin
DI…Digital input. Protected with clamp to 2.5V
DO…Digital output. Protected with clamp to 2.5V
S… VSS supply
Note: Connect any unused output channel as follows:
- GATEx = open, RFbx = CURR_senseX = GND
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Revision 1.21 / 2011-09-30
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AS3693B
austriamicrosystems
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9.2 Package drawing epTQFP64
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AS3693B
austriamicrosystems
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9.3 Package drawing QFN64
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AS3693B
austriamicrosystems
10 Ordering Information
Table 6 – Ordering Information
Marking
Package Type
Delivery Form
Description
AS3693B-ZTQT
AS3693B
epTQFP64
Tape and Reel
in Dry Pack
Package size = 10x10mm, Exposed pad
size = 4.5x4.5mm, Pitch = 0.5mm, Pb-free;
AS3693B-ZQFT
AS3693B
QFN64
Tape and Reel
in Dry Pack
Package size = 9x9mm, Pitch = 0.5mm,
Pb-free;
AS3693B-ZMFT
AS3693B
MLF64
Tape and Reel
in Dry Pack
Package size = 9x9mm, Pitch = 0.5mm,
Pb-free;
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Part Number
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AS3693B
austriamicrosystems
Copyright
Copyright © 1997-2006, austriamicrosystems AG, Schloss Premstaetten, 8141 Unterpremstaetten, AustriaEurope. Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted,
merged, translated, stored, or used without the prior written consent of the copyright owner.
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All products and companies mentioned are trademarks of their respective companies.
Disclaimer
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Devices sold by austriamicrosystems AG are covered by the warranty and patent identification provisions
appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by
description regarding the information set forth herein or regarding the freedom of the described devices from
patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at any time
and without notice. Therefore, prior to designing this product into a system, it is necessary to check with
austriamicrosystems AG for current information. This product is intended for use in normal commercial
applications. Applications requiring extended temperature range, unusual environmental requirements, or high
reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not
recommended without additional processing by austriamicrosystems AG for each application.
The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However,
austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not
limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect,
special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing,
performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise
or flow out of austriamicrosystems AG rendering of technical or other services.
Contact Information
Headquarters:
ca
austriamicrosystems AG
Business Unit Communications
A 8141 Schloss Premstätten, Austria
T. +43 (0) 3136 500 0
F. +43 (0) 3136 5692
info@austriamicrosystems.com
ni
For Sales Offices, Distributors and Representatives, please visit:
Te
ch
www.austriamicrosystems.com
austriamicrosystems
www.austriamicrosystems.com
– a leap ahead
Revision 1.21 / 2011-09-30
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