( BKP , BKX) - BKX to MAX9650 - BKP to MAX15032ATA iML7822 Link i7822 = iML7822 2-ch VCOM; Supply Voltage: 5V～20V; Ipeak= 400mA, Irms=45mA, SR=20V/us czyli dwa operacyjne i7822 = LM8262 =HX8902 = EL5211 iML7975 (iML7975 7bit DVR with I2C interface; logic voltage: 2.25V(R)/2.6V(W)～4V; Analog voltage: 4.5V～18V; 10-TDFN) http://obrazki.elektroda.pl/3894807800_1485995874_thumb.jpg Tcon MODEL: SYNC60C4LV0.3 for Toshiba 40LV655PR Main Board - PE0772 / V28A001020A1 (Cpu - MST 6B885GL-LF ) PSU DPS - 276AP A ICT1 - THF930I LMU4142TI ICM1 - W9864G2GH-6 OP1,PO2 - I7814HS ICE - 24C64WP ICV1 - I7975 IC20 - XC95144XL TQG100AWN0925 D3648512A ICT4 - KECYWB66 ICC1 - MAX9591 ICS1 - +1181L ICD2 - KA1718 ICD1 - TPS65167 VIN +12.05V AVDD +15.1V TEMP +1.79V VON +19.45V VOFF -7.49V 3.3V - OK VON_P +22.7V 1.8V - OK DEO +2.32V T_RD +3.32V SSCLK0 +1.43V SSCLK1 +1.55V KB +2.2V RST +3.2V DSW +2.21V VREF_L-L +0.31V VREF_L-H +6.12V VREF_U-L +8.91V VREF_U-H +14.77V CLKM +1.48V VSTL +6.04V VCOM_L +6.53V VCOMG2L +6.35V VCOMG1 +6.41V VDDQ +3.31V WP1 0V VR +8.27V DRN +11.12V CV0 +8.25V TD0 +2.3V TD1 +3.3V TMS +3.3V TCK +2.4V DQM 0V WE +3.3V CAS +3.3V RAS +3.3V CS +3.28V CLKM +1.47V T-CON Samsung S100FAPC2LV0-3 (BN98-03131A ) IC590 S524A40X20-RC70 IC1 LPFC041T0A-Q1 IC2 INAISL24835IRTZ-T13 IC4 SM4109 IC6 IML7975 ICD2 FDC658AP http://obrazki.elektroda.pl/3747119000_1485996650_thumb.jpg SM T-con t370xw02-vf-bn07-00642a Link
EL5111, EL5211, EL5411
®
Data Sheet
May 7, 2007
FN7119.7
60MHz Rail-to-Rail Input-Output Op Amps
Features
The EL5111, EL5211, and EL5411 are low power, high
voltage rail-to-rail input-output amplifiers. The EL5111
represents a single amplifier, the EL5211 contains two
amplifiers, and the EL5411 contains four amplifiers.
Operating on supplies ranging from 5V to 15V, while
consuming only 2.5mA per amplifier, the EL5111, EL5211,
and EL5411 have a bandwidth of 60MHz (-3dB). They also
provide common mode input ability beyond the supply rails,
as well as rail-to-rail output capability. This enables these
amplifiers to offer maximum dynamic range at any supply
voltage.
• Pb-free plus anneal available (RoHS compliant)
The EL5111, EL5211, and EL5411 also feature fast slewing
and settling times, as well as a high output drive capability of
65mA (sink and source). These features make these
amplifiers ideal for high speed filtering and signal
conditioning application. Other applications include battery
power, portable devices, and anywhere low power
consumption is important.
• ±180mA output short current
The EL5111 is available in 5 Ld TSOT and 8 Ld HMSOP
packages. The EL5211 is available in the 8 Ld HMSOP
package. The EL5411 is available in space-saving 14 Ld
HTSSOP packages. All feature a standard operational
amplifier pinout. These amplifiers operate over a temperature
range of -40°C to +85°C.
• Data acquisition
• 60MHz (-3dB) bandwidth
• Supply voltage = 4.5V to 16.5V
• Low supply current (per amplifier) = 2.5mA
• High slew rate = 75V/µs
• Unity-gain stable
• Beyond the rails input capability
• Rail-to-rail output swing
Applications
• TFT-LCD panels
• VCOM amplifiers
• Drivers for A/D converters
• Video processing
• Audio processing
• Active filters
• Test equipment
• Battery-powered applications
• Portable equipment
Pinouts
EL5111
(8 LD HMSOP)
TOP VIEW
NC 1
VIN- 2
VIN+ 3
VS- 4
EL5111
(5 LD TSOT)
TOP VIEW
8 NC
+
VOUT 1
7 VS+
VS- 2
6 VOUT
VIN+ 3
5 NC
EL5211
(8 LD HMSOP)
TOP VIEW
5 VS+
VOUTA 1
VINA- 2
+ 4 VIN-
VINA+ 3
VS- 4
EL5411
(14 LD HTSSOP)
TOP VIEW
8 VS+
7 VOUTB
+
+
VOUTA 1
14 VOUTD
VINA- 2
6 VINB-
VINA+ 3
5 VINB+
13 VIND+
+
VS+ 4
11 VS-
VINB+ 5
VINB- 6
VOUTB 7
1
12 VIND+
10 VINC+
+
-
+
-
9 VINC8 VOUTC
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2004, 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
EL5111, EL5211, EL5411
Ordering Information
PART NUMBER
PART MARKING
TAPE & REEL
PACKAGE
PKG. DWG. #
EL5111IWT-T7
8
7” (3k pcs)
5 Ld TSOT
MDP0049
EL5111IWT-T7A
8
7” (250 pcs)
5 Ld TSOT
MDP0049
EL5111IWTZ-T7 (Note)
BAAG
7” (3k pcs)
5 Ld TSOT (Pb-free)
MDP0049
EL5111IWTZ-T7A (Note)
BAAG
7” (250 pcs)
5 Ld TSOT (Pb-free)
MDP0049
EL5111IYE
7
-
8 Ld HMSOP (3.0mm)
MDP0050
EL5111IYE-T7
7
7”
8 Ld HMSOP (3.0mm)
MDP0050
EL5111IYE-T13
7
13”
8 Ld HMSOP (3.0mm)
MDP0050
EL5111IYEZ (Note)
BAAJA
-
8 Ld HMSOP (Pb-free) (3.0mm)
MDP0050
EL5111IYEZ-T7 (Note)
BAAJA
7”
8 Ld HMSOP (Pb-free) (3.0mm)
MDP0050
EL5111IYEZ-T13 (Note)
BAAJA
13”
8 Ld HMSOP (Pb-free) (3.0mm)
MDP0050
EL5111AIYEZ (Note)
BBLAA
-
8 Ld HMSOP (Pb-free) (3.0mm)
MDP0050
EL5111AIYEZ-T13 (Note)
BBLAA
13”
8 Ld HMSOP (Pb-free) (3.0mm)
MDP0050
EL5111AIYEZ-T7 (Note)
BBLAA
7”
8 Ld HMSOP (Pb-free) (3.0mm)
MDP0050
EL5211IYE
9
-
8 Ld HMSOP (3.0mm)
MDP0050
EL5211IYE-T7
9
7”
8 Ld HMSOP (3.0mm)
MDP0050
EL5211IYE-T13
9
13”
8 Ld HMSOP (3.0mm)
MDP0050
EL5211IYEZ (Note)
BAATA
-
8 Ld HMSOP (Pb-free) (3.0mm)
MDP0050
EL5211IYEZ-T7 (Note)
BAATA
7”
8 Ld HMSOP (Pb-free) (3.0mm)
MDP0050
EL5211IYEZ-T13 (Note)
BAATA
13”
8 Ld HMSOP (Pb-free) (3.0mm)
MDP0050
EL5411IRE
5411IRE
-
14 Ld HTSSOP (4.4mm)
MDP0048
EL5411IRE-T7
5411IRE
7”
14 Ld HTSSOP (4.4mm)
MDP0048
EL5411IRE-T13
5411IRE
13”
14 Ld HTSSOP (4.4mm)
MDP0048
EL5411IREZ (Note)
5411IREZ
-
14 Ld HTSSOP (Pb-free) (4.4mm) MDP0048
EL5411IREZ-T7 (Note)
5411IREZ
7”
14 Ld HTSSOP (Pb-free) (4.4mm) MDP0048
EL5411IREZ-T13 (Note)
5411IREZ
13”
14 Ld HTSSOP (Pb-free) (4.4mm) MDP0048
EL5411IR
5411IR
-
14 Ld TSSOP (4.4mm)
MDP0044
EL5411IR-T7
5411IR
7”
14 Ld TSSOP (4.4mm)
MDP0044
EL5411IR-T13
5411IR
13”
14 Ld TSSOP (4.4mm)
MDP0044
EL5411IRZ (Note)
5411IRZ
-
14 Ld TSSOP (Pb-free) (4.4mm)
M14.173
EL5411IRZ-T7 (Note)
5411IRZ
7”
14 Ld TSSOP (Pb-free) (4.4mm)
M14.173
EL5411IRZ-T13 (Note)
5411IRZ
13”
14 Ld TSSOP (Pb-free) (4.4mm)
M14.173
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2
FN7119.7
May 7, 2007
EL5111, EL5211, EL5411
Absolute Maximum Ratings (TA = +25°C)
Thermal Information
Supply Voltage between VS+ and VS- . . . . . . . . . . . . . . . . . . . .+18V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . VS- - 0.5V, VS +0.5V
Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 65mA
Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER
VS+ = +5V, VS- = -5V, RL = 1kΩ to 0V, TA = +25°C, Unless Otherwise Specified
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
3
15
mV
INPUT CHARACTERISTICS
VOS
Input Offset Voltage
VCM = 0V
TCVOS
Average Offset Voltage Drift (Note 1)
IB
Input Bias Current
RIN
Input Impedance
1
GΩ
CIN
Input Capacitance
2
pF
CMIR
Common-Mode Input Range
CMRR
Common-Mode Rejection Ratio
for VIN from -5.5V to 5.5V
50
70
dB
AVOL
Open-Loop Gain
-4.5V ≤ VOUT ≤ 4.5V
62
70
dB
7
VCM = 0V
2
-5.5
µV/°C
60
+5.5
nA
V
OUTPUT CHARACTERISTICS
VOL
Output Swing Low
IL = -5mA
VOH
Output Swing High
IL = 5mA
ISC
IOUT
-4.92
4.85
-4.85
V
4.92
V
Short-Circuit Current
±180
mA
Output Current
±65
mA
80
dB
POWER SUPPLY PERFORMANCE
PSRR
Power Supply Rejection Ratio
VS is moved from ±2.25V to ±7.75V
60
IS
Supply Current
No load (EL5111)
2.5
4.5
mA
No load (EL5211)
5
7.5
mA
No load (EL5411)
10
15
mA
DYNAMIC PERFORMANCE
SR
Slew Rate (Note 2)
-4.0V ≤ VOUT ≤ 4.0V, 20% to 80%
75
V/µs
tS
Settling to +0.1% (AV = +1)
(AV = +1), VO = 2V step
80
ns
BW
-3dB Bandwidth
60
MHz
GBWP
Gain-Bandwidth Product
32
MHz
PM
Phase Margin
50
°
CS
Channel Separation
f = 5MHz (EL5211 and EL5411 only)
110
dB
dG
Differential Gain (Note 3)
RF = RG = 1kΩ and VOUT = 1.4V
0.17
%
dP
Differential Phase (Note 3)
RF = RG = 1kΩ and VOUT = 1.4V
0.24
°
NOTES:
1. Measured over operating temperature range.
2. Slew rate is measured on rising and falling edges.
3. NTSC signal generator used.
3
FN7119.7
May 7, 2007
EL5111, EL5211, EL5411
Electrical Specifications
PARAMETER
VS+ = +5V, VS- = 0V, RL = 1kΩ to 2.5V, TA = +25°C, Unless Otherwise Specified
DESCRIPTION
CONDITION
MIN
TYP
MAX
UNIT
3
15
mV
INPUT CHARACTERISTICS
VOS
Input Offset Voltage
VCM = 2.5V
TCVOS
Average Offset Voltage Drift (Note 4)
IB
Input Bias Current
RIN
Input Impedance
1
GΩ
CIN
Input Capacitance
2
pF
CMIR
Common-Mode Input Range
CMRR
Common-Mode Rejection Ratio
for VIN from -0.5V to 5.5V
45
66
dB
AVOL
Open-Loop Gain
0.5V ≤ VOUT ≤ 4.5V
62
70
dB
7
VCM = 2.5V
2
-0.5
µV/°C
60
+5.5
nA
V
OUTPUT CHARACTERISTICS
VOL
Output Swing Low
IL = -5mA
VOH
Output Swing High
IL = 5mA
ISC
IOUT
80
4.85
150
mV
4.92
V
Short-circuit Current
±180
mA
Output Current
±65
mA
80
dB
POWER SUPPLY PERFORMANCE
PSRR
Power Supply Rejection Ratio
VS is moved from 4.5V to 15.5V
60
IS
Supply Current
No load (EL5111)
2.5
4.5
mA
No load (EL5211)
5
7.5
mA
No load (EL5411)
10
15
mA
DYNAMIC PERFORMANCE
SR
Slew Rate (Note 5)
1V ≤ VOUT ≤ 4V, 20% to 80%
75
V/µs
tS
Settling to +0.1% (AV = +1)
(AV = +1), VO = 2V step
80
ns
BW
-3dB Bandwidth
60
MHz
GBWP
Gain-Bandwidth Product
32
MHz
PM
Phase Margin
50
°
CS
Channel Separation
f = 5MHz (EL5211 and EL5411 only)
110
dB
dG
Differential Gain (Note 6)
RF = RG = 1kΩ and VOUT = 1.4V
0.17
%
dP
Differential Phase (Note 6)
RF = RG = 1kΩ and VOUT = 1.4V
0.24
°
NOTES:
4. Measured over operating temperature range.
5. Slew rate is measured on rising and falling edges.
6. NTSC signal generator used.
4
FN7119.7
May 7, 2007
EL5111, EL5211, EL5411
Electrical Specifications
PARAMETER
VS+ = +15V, VS- = 0V, RL = 1kΩ to 7.5V, TA = +25°C, Unless Otherwise Specified
DESCRIPTION
CONDITION
MIN
TYP
MAX
UNIT
3
15
mV
INPUT CHARACTERISTICS
VOS
Input Offset Voltage
VCM = 7.5V
TCVOS
Average Offset Voltage Drift (Note 7)
IB
Input Bias Current
RIN
Input Impedance
1
GΩ
CIN
Input Capacitance
2
pF
CMIR
Common-Mode Input Range
CMRR
Common-Mode Rejection Ratio
for VIN from -0.5V to 15.5V
53
72
dB
AVOL
Open-Loop Gain
0.5V ≤ VOUT ≤ 14.5V
62
70
dB
7
VCM = 7.5V
2
-0.5
µV/°C
60
+15.5
nA
V
OUTPUT CHARACTERISTICS
VOL
Output Swing Low
IL = -5mA
VOH
Output Swing High
IL = 5mA
ISC
IOUT
80
14.85
150
mV
14.92
V
Short-circuit Current
±180
mA
Output Current
±65
mA
80
dB
POWER SUPPLY PERFORMANCE
PSRR
Power Supply Rejection Ratio
VS is moved from 4.5V to 15.5V
60
IS
Supply Current
No load (EL5111)
2.5
4.5
mA
No load (EL5211)
5
7.5
mA
No load (EL5411)
10
15
mA
DYNAMIC PERFORMANCE
SR
Slew Rate (Note 8)
1V ≤ VOUT ≤ 14V, 20% to 80%
75
V/µs
tS
Settling to +0.1% (AV = +1)
(AV = +1), VO = 2V step
80
ns
BW
-3dB Bandwidth
60
MHz
GBWP
Gain-Bandwidth Product
32
MHz
PM
Phase Margin
50
°
CS
Channel Separation
f = 5MHz (EL5211 and EL5411 only)
110
dB
dG
Differential Gain (Note 9)
RF = RG = 1kΩ and VOUT = 1.4V
0.16
%
dP
Differential Phase (Note 9)
RF = RG = 1kΩ and VOUT = 1.4V
0.22
°
NOTES:
7. Measured over operating temperature range
8. Slew rate is measured on rising and falling edges
9. NTSC signal generator used
5
FN7119.7
May 7, 2007
EL5111, EL5211, EL5411
Typical Performance Curves
25
VS = ±5V
TA = +25°C
TYPICAL
PRODUCTION
DISTRIBUTION
400
300
200
100
VS = ±5V
QUANTITY (AMPLIFIERS)
15
10
5
21
19
17
15
11
13
9
INPUT OFFSET VOLTAGE DRIFT, TCVOS (µV/°C)
FIGURE 1. INPUT OFFSET VOLTAGE DISTRIBUTION
FIGURE 2. INPUT OFFSET VOLTAGE DRIFT
0.008
2.0
VS = ±5V
INPUT BIAS CURRENT (µA)
INPUT OFFSET VOLTAGE (mV)
7
1
12
8
10
6
4
2
-0
-2
-4
-6
-8
-10
-12
INPUT OFFSET VOLTAGE (mV)
5
0
0
1.5
1.0
0.5
0.0
-0.5
-50
-10
30
70
110
0.004
0.000
-0.004
-0.008
-0.012
-50
150
-10
TEMPERATURE (°C)
70
110
150
FIGURE 4. INPUT BIAS CURRENT vs TEMPERATURE
4.96
4.94
4.92
4.90
4.88
-10
30
70
110
150
TEMPERATURE (°C)
FIGURE 5. OUTPUT HIGH VOLTAGE vs TEMPERATURE
6
OUTPUT LOW VOLTAGE (V)
-4.85
VS = ±5V
IOUT = 5mA
4.86
-50
30
TEMPERATURE (°C)
FIGURE 3. INPUT OFFSET VOLTAGE vs TEMPERATURE
OUTPUT HIGH VOLTAGE (V)
TYPICAL
PRODUCTION
DISTRIBUTION
20
3
QUANTITY (AMPLIFIERS)
500
VS = ±5V
IOUT = 5mA
-4.87
-4.89
-4.91
-4.93
-4.95
-50
-10
30
70
110
150
TEMPERATURE (°C)
FIGURE 6. OUTPUT LOW VOLTAGE vs TEMPERATURE
FN7119.7
May 7, 2007
EL5111, EL5211, EL5411
Typical Performance Curves (Continued)
78
75
VS = ±5V
77
SLEW RATE (V/µs)
OPEN-LOOP GAIN (dB)
VS = ±5V
RL = 1kΩ
70
65
76
75
74
73
60
-50
-10
30
70
110
72
-50
150
-10
TEMPERATURE (°C)
110
150
FIGURE 8. SLEW RATE vs TEMPERATURE
2.70
2.9
TA = +25°C
VS = ±5V
2.7
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
70
TEMPERATURE (°C)
FIGURE 7. OPEN-LOOP GAIN vs TEMPERATURE
2.5
2.3
2.1
1.9
1.7
4
8
12
16
2.65
2.60
2.55
2.50
2.45
2.40
-50
1.5
20
SUPPLY VOLTAGE (V)
-10
30
70
110
150
TEMPERATURE (°C)
FIGURE 9. SUPPLY CURRENT PER AMPLIFIER vs SUPPLY
VOLTAGE
FIGURE 10. SUPPLY CURRENT PER AMPLIFIER vs
TEMPERATURE
0.00
0.30
DIFFERENTIAL PHASE (°)
-0.02
DIFFERENTIAL GAIN (%)
30
-0.04
-0.06
-0.08
-0.10
-0.12
VS = ±5V
AV = 2
RL = 1kΩ
-0.14
-0.16
-0.18
0.25
0.20
0.15
0.10
0.05
0.00
0
100
IRE
FIGURE 11. DIFFERENTIAL GAIN
7
200
0
100
200
IRE
FIGURE 12. DIFFERENTIAL PHASE
FN7119.7
May 7, 2007
EL5111, EL5211, EL5411
Typical Performance Curves (Continued)
-30
80
VS = ±5V
AV = 2
RL = 1kΩ
FREQ = 1MHz
-60
2nd HD
-70
-80
40
PHASE
4
8
6
10
-20
1k
10
10k
100k
VOP-P (V)
VS = ±5V
AV = 1
CLOAD = 0pF
1kΩ
1
560Ω
-3
150Ω
-5
100k
1M
10M
1000pF
15
47pF
10pF
-5
-15
VS = ±5V
AV = 1
RL = 1kΩ
1M
100M
FIGURE 16. FREQUENCY RESPONSE FOR VARIOUS CL
MAXIMUM OUTPUT SWING (VP-P)
OUTPUT IMPEDANCE (Ω)
350
300
250
200
150
100
50
10M
100M
FREQUENCY (Hz)
FIGURE 17. CLOSED LOOP OUTPUT IMPEDANCE
8
10M
FREQUENCY (Hz)
400
1M
100pF
5
FREQUENCY (Hz)
100k
-50
100M
25
-25
100k
100M
FIGURE 15. FREQUENCY RESPONSE FOR VARIOUS RL
0
10k
10M
FIGURE 14. OPEN LOOP GAIN AND PHASE
MAGNITUDE (NORMALIZED) (dB)
MAGNITUDE (NORMALIZED) (dB)
5
-1
1M
FREQUENCY (Hz)
FIGURE 13. HARMONIC DISTORTION vs VOP-P
3
70
0
-90
2
130
20
3rd HD
0
190
GAIN
PHASE (°)
-50
60
GAIN (dB)
DISTORTION (dB)
-40
250
12
10
8
6
4
2
VS = ±5V
AV = 1
RL = 1kΩ
DISTORTION & lt; 1%
0
10k
100k
1M
10M
100M
FREQUENCY (kHz)
FIGURE 18. MAXIMUM OUTPUT SWING vs FREQUENCY
FN7119.7
May 7, 2007
EL5111, EL5211, EL5411
Typical Performance Curves (Continued)
-15
-80
PSRR+
-25
PSRR-
PSRR (dB)
CMRR (dB)
-60
-35
-45
-40
-20
-55
VS = ±5V
TA = +25°C
-65
1k
10k
100k
1M
10M
0
100
100M
1k
FREQUENCY (Hz)
100
XTALK (dB)
VOLTAGE NOISE (nV/√Hz)
10M
-60
DUAL MEASURED CH A TO B
QUAD MEASURED CH A TO D OR B TO C
OTHER COMBINATIONS YIELD
IMPROVED REJECTION
-80
10
-100
-120
VS = ±5V
RL = 1kΩ
AV = 1
VIN = 110mVRMS
-140
1k
10k
100k
1M
10M
-160
1k
100M
10k
100k
1M
10M 30M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 21. INPUT VOLTAGE NOISE SPECTRAL DENSITY
FIGURE 22. CHANNEL SEPARATION
5
100
VS = ±5V
AV = 1
RL = 1kΩ
VIN = ±50mV
TA = +25°C
4
3
STEP SIZE (V)
80
1M
FIGURE 20. PSRR
1K
1
100
100k
FREQUENCY (Hz)
FIGURE 19. CMRR
OVERSHOOT (%)
10k
60
40
VS = ±5V
AV = 1
RL = 1kΩ
0.1%
2
1
0
-1
-2
0.1%
-3
20
-4
0
10
100
LOAD CAPACITANCE (pF)
FIGURE 23. SMALL-SIGNAL OVERSHOOT vs LOAD
CAPACITANCE
9
1k
-5
55
65
75
85
95
105
SETTLING TIME (ns)
FIGURE 24. SETTLING TIME vs STEP SIZE
FN7119.7
May 7, 2007
EL5111, EL5211, EL5411
Typical Performance Curves (Continued)
VS = ±5V
TA = +25°C
AV = 1
RL = 1kΩ
VS = ±5V
TA = +25°C
AV = 1
RL = 1kΩ
100mV STEP
1V STEP
50ns/DIV
50ns/DIV
FIGURE 25. LARGE SIGNAL TRANSIENT RESPONSE
FIGURE 26. SMALL SIGNAL TRANSIENT RESPONSE
Pin Descriptions
EL5111
(TSOT-5)
EL5111
(HMSOP8)
EL5211
(HMSOP8)
EL5411
(HTSSOP14)
NAME
1
6
1
1
VOUTA
FUNCTION
EQUIVALENT CIRCUIT
Amplifier A output
VS+
GND
VS-
CIRCUIT 1
4
2
2
2
VINA-
Amplifier A inverting input
VS+
VS-
CIRCUIT 2
3
3
3
3
VINA+
5
7
8
4
VS+
5
5
VINB+
Amplifier B non-inverting input
(Reference Circuit 2)
6
6
VINB-
Amplifier B inverting input
(Reference Circuit 2)
7
7
VOUTB
Amplifier B output
(Reference Circuit 1)
8
VOUTC
Amplifier C output
(Reference Circuit 1)
9
VINC-
Amplifier C inverting input
(Reference Circuit 2)
10
VINC+
Amplifier C non-inverting input
(Reference Circuit 2)
11
VS-
12
VIND+
Amplifier D non-inverting input
(Reference Circuit 2)
13
VIND-
Amplifier D inverting input
(Reference Circuit 2)
14
VOUTD
Amplifier D output
(Reference Circuit 1)
2
4
4
1, 5, 8
NC
10
Amplifier A non-inverting input
(Reference Circuit 2)
Positive power supply
Negative power supply
Not connected
FN7119.7
May 7, 2007
EL5111, EL5211, EL5411
Applications Information
Short Circuit Current Limit
Product Description
The EL5111, EL5211, and EL5411 voltage feedback
amplifiers are fabricated using a high voltage CMOS
process. They exhibit rail-to-rail input and output capability,
are unity gain stable and have low power consumption
(2.5mA per amplifier). These features make the EL5111,
EL5211, and EL5411 ideal for a wide range of generalpurpose applications. Connected in voltage follower mode
and driving a load of 1kΩ, the EL5111, EL5211, and EL5411
have a -3dB bandwidth of 60MHz while maintaining a 75V/µs
slew rate. The EL5111 is a single amplifier, the EL5211 a
dual amplifier, and the EL5411 a quad amplifier.
Operating Voltage, Input, and Output
The EL5111, EL5211, and EL5411 are specified with a single
nominal supply voltage from 5V to 15V or a split supply with
its total range from 5V to 15V. Correct operation is
guaranteed for a supply range of 4.5V to 16.5V. Most
EL5111, EL5211, and EL5411 specifications are stable over
both the full supply range and operating temperatures of
-40°C to +85°C. Parameter variations with operating voltage
and/or temperature are shown in the typical performance
curves.
The input common-mode voltage range of the EL5111,
EL5211, and EL5411 extends 500mV beyond the supply
rails. The output swings of the EL5111, EL5211, and EL5411
typically extend to within 100mV of positive and negative
supply rails with load currents of 5mA. Decreasing load
currents will extend the output voltage range even closer to
the supply rails. Figure 27 shows the input and output
waveforms for the device in the unity-gain configuration.
Operation is from ±5V supply with a 1kΩ load connected to
GND. The input is a 10VP-P sinusoid. The output voltage is
approximately 9.8VP-P.
VS = ±5V, TA = +25°C, AV = 1, VIN = 10VP-P
10µs
OUTPUT
INPUT
5V
5V
FIGURE 27. OPERATION WITH RAIL-TO-RAIL INPUT AND
OUTPUT
The EL5111, EL5211, and EL5411 will limit the short circuit
current to ±180mA if the output is directly shorted to the
positive or the negative supply. If an output is shorted
indefinitely, the power dissipation could easily increase such
that the device may be damaged. Maximum reliability is
maintained if the output continuous current never exceeds
±65mA. This limit is set by the design of the internal metal
interconnects.
Output Phase Reversal
The EL5111, EL5211, and EL5411 are immune to phase
reversal as long as the input voltage is limited from VS- -0.5V
to VS+ +0.5V. Figure 28 shows a photo of the output of the
device with the input voltage driven beyond the supply rails.
Although the device's output will not change phase, the
input's overvoltage should be avoided. If an input voltage
exceeds supply voltage by more than 0.6V, electrostatic
protection diodes placed in the input stage of the device
begin to conduct and overvoltage damage could occur.
VS = ±2.5V, TA = +25°C, AV = 1, VIN = 6VP-P
1V
10µs
1V
FIGURE 28. OPERATION WITH BEYOND-THE-RAILS INPUT
Power Dissipation
With the high-output drive capability of the EL5111, EL5211,
and EL5411 amplifiers, it is possible to exceed the +125°C
'absolute-maximum junction temperature' under certain load
current conditions. Therefore, it is important to calculate the
maximum junction temperature for the application to
determine if load conditions need to be modified for the
amplifier to remain in the safe operating area.
The maximum power dissipation allowed in a package is
determined according to:
T JMAX – T AMAX
P DMAX = -------------------------------------------θ JA
(EQ. 1)
where:
• TJMAX = Maximum junction temperature
• TAMAX = Maximum ambient temperature
• ΘJA = Thermal resistance of the package
• PDMAX = Maximum power dissipation in the package
11
FN7119.7
May 7, 2007
EL5111, EL5211, EL5411
The maximum power dissipation actually produced by an IC
is the total quiescent supply current times the total power
supply voltage, plus the power in the IC due to the loads, or:
P DMAX = Σi [ V S × I SMAX + ( V S + – V OUT i ) × I LOAD i ]
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY (4-LAYER) TEST BOARD HTSSOP EXPOSED DIEPAD SOLDERED TO
PCB PER JESD51-5
(EQ. 2)
when sourcing, and:
P DMAX = Σi [ V S × I SMAX + ( V OUT i – V S - ) × I LOAD i ]
(EQ. 3)
when sinking,
where:
POWER DISSIPATION (W)
3.5
• i = 1 to 2 for dual and 1 to 4 for quad
3.0
2.632W
2.5
HTSSOP14
θJA = +38°C/W
2.0
1.5
1.0
0.5
0.0
0
• VS = Total supply voltage
25
50
75 85
100
125
AMBIENT TEMPERATURE (°C)
• ISMAX = Maximum supply current per amplifier
• VOUTi = Maximum output voltage of the application
FIGURE 30. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
• ILOADi = Load current
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1.2
TSSOP28
POWER DISSIPATION (W)
If we set the two PDMAX equations equal to each other, we
can solve for RLOADi to avoid device overheat. Figures 29
through 36 provide a convenient way to see if the device will
overheat. The maximum safe power dissipation can be
found graphically, based on the package type and the
ambient temperature. By using the previous equation, it is a
simple matter to see if PDMAX exceeds the device's power
derating curves. To ensure proper operation, it is important
to observe the recommended derating curves shown in
Figures 29 through 36.
θJA = +120°C/W
TSSOP24
1.0
0.8
0.6
θJA = +140°C/W
TSSOP16
977mW
893mW
0.4
θJA = +148°C/W
845mW
0.2
TSSOP14
758mW
0.9
θJA = +165°C/W
0.0
0.8
POWER DISSIPATION (W)
θJA = +128°C/W
TSSOP20
1.042W
0
694mW
0.7
HTSSOP14
θJA = +144°C/W
0.6
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 31. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
0.5
0.4
0.3
0.2
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
0.1
1.8
0
25
50
75 85
100
125
AMBIENT TEMPERATURE (°C)
FIGURE 29. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
POWER DISSIPATION (W)
0.0
TSSOP28
1.6
θJA=+75°C/W
TSSOP24
1.4
1.2
1.0
0.8
1.471W
0.6
1.389W
0.4
1.289W
0.2
θJA=+85°C/W
TSSOP20
1.667W
1.250W
θJA=+90°C/W
TSSOP16
θJA=+97°C/W
TSSOP14
θJA=+100°C/W
0.0
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 32. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
12
FN7119.7
May 7, 2007
EL5111, EL5211, EL5411
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY (SINGLE LAYER) TEST BOARD
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY (4-LAYER) TEST BOARD
0.6
290mW
0.300
0.250
POWER DISSIPATION (W)
POWER DISSIPATION (W)
0.350
TSOT5
θJA = +345°C/W
0.200
0.150
0.100
0.050
0.5 483mW
0.3
0.2
0.1
0.0
0.000
0
25
50
75 85 100
125
AMBIENT TEMPERATURE (°C)
0
150
FIGURE 33. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
25
50
75 85 100
125
AMBIENT TEMPERATURE (°C)
150
FIGURE 34. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
0.6
1
486mW
0.5
0.4
θ
JA
=
0.3
POWER DISSIPATION (W)
POWER DISSIPATION (W)
TSOT5
θJA = +207°C/W
0.4
HM
SO
P8
+2
06
°C
/W
0.2
0.1
870mW
0.9
0.8
θ
0.7
JA
=
0.6
0.5
HM
SO
P8
+1
15
°C
/W
0.4
0.3
0.2
0.1
0
0
0
25
50
75 85
100
125
AMBIENT TEMPERATURE (°C)
FIGURE 35. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
Unused Amplifiers
It is recommended that any unused amplifiers in a dual and
a quad package be configured as a unity gain follower. The
inverting input should be directly connected to the output
and the non-inverting input tied to the ground plane.
13
0
25
50
75 85
100
125
AMBIENT TEMPERATURE (°C)
FIGURE 36. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
Power Supply Bypassing and Printed Circuit
Board Layout
The EL5111, EL5211, and EL5411 can provide gain at high
frequency. As with any high-frequency device, good printed
circuit board layout is necessary for optimum performance.
Ground plane construction is highly recommended, lead
lengths should be as short as possible and the power supply
pins must be well bypassed to reduce the risk of oscillation.
For normal single supply operation, where the VS- pin is
connected to ground, a 0.1µF ceramic capacitor should be
placed from VS+ to pin to VS- pin. A 4.7µF tantalum
capacitor should then be connected in parallel, placed in the
region of the amplifier. One 4.7µF capacitor may be used for
multiple devices. This same capacitor combination should be
placed at each supply pin to ground if split supplies are to be
used.
FN7119.7
May 7, 2007
EL5111, EL5211, EL5411
Thin Shrink Small Outline Package Family (TSSOP)
MDP0044
0.25 M C A B
D
THIN SHRINK SMALL OUTLINE PACKAGE FAMILY
A
(N/2)+1
N
MILLIMETERS
SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE
A
1
(N/2)
B
0.20 C B A
2X
N/2 LEAD TIPS
TOP VIEW
1.20
1.20
1.20
1.20
Max
0.10
0.10
0.10
0.10
0.10
±0.05
A2
E1
1.20
A1
PIN #1 I.D.
E
0.90
0.90
0.90
0.90
0.90
±0.05
b
0.25
0.25
0.25
0.25
0.25
+0.05/-0.06
c
0.15
0.15
0.15
0.15
0.15
+0.05/-0.06
D
5.00
5.00
6.50
7.80
9.70
±0.10
E
C
SEATING
PLANE
6.40
6.40
6.40
Basic
4.40
4.40
4.40
4.40
±0.10
e
H
6.40
4.40
0.65
0.65
0.65
0.65
0.65
Basic
L
0.60
0.60
0.60
0.60
0.60
±0.15
L1
0.05
e
6.40
E1
1.00
1.00
1.00
1.00
1.00
Reference
Rev. F 2/07
0.10 M C A B
b
0.10 C
N LEADS
SIDE VIEW
NOTES:
1. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed
0.15mm per side.
2. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm per
side.
SEE DETAIL “X”
3. Dimensions “D” and “E1” are measured at dAtum Plane H.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
c
END VIEW
L1
A
A2
GAUGE
PLANE
0.25
L
A1
0° - 8°
DETAIL X
14
FN7119.7
May 7, 2007
EL5111, EL5211, EL5411
HTSSOP (Heat-Sink TSSOP) Family
MDP0048
0.25 M C A B
D
HTSSOP (HEAT-SINK TSSOP) FAMILY
A
(N/2)+1
N
MILLIMETERS
SYMBOL 14 LD 20 LD 24 LD 28 LD 38 LD TOLERANCE
A
0.20 C B A
2X
N/2 LEAD TIPS
(N/2)
TOP VIEW
B
1.20
1.20
1.20
Max
0.075
0.075
0.075
0.075
±0.075
0.90
0.90
0.90
0.90
0.90
+0.15/-0.10
b
1
1.20
0.075
A2
E1
1.20
A1
PIN #1 I.D.
E
0.25
0.25
0.25
0.25
0.22
+0.05/-0.06
c
0.15
0.15
0.15
0.15
0.15
+0.05/-0.06
D
5.00
6.50
7.80
9.70
9.70
±0.10
D1
7.25
Reference
6.40
6.40
Basic
4.40
4.40
4.40
4.40
4.40
±0.10
3.0
3.0
3.0
3.0
3.0
Reference
0.65
0.65
0.65
0.65
0.50
Basic
L
0.60
0.60
0.60
0.60
0.60
±0.15
L1
1.00
1.00
1.00
1.00
1.00
Reference
N
14
20
24
28
38
Reference
Rev. 3 2/07
BOTTOM VIEW
NOTES:
0.05
e
5.0
6.40
e
C
4.3
6.40
E2
E2
4.2
6.40
E1
D1
EXPOSED
THERMAL PAD
3.2
E
H
1. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed
0.15mm per side.
2. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm per
side.
SEATING
PLANE
0.10 C
N LEADS
3. Dimensions “D” and “E1” are measured at Datum Plane H.
0.10 M C A B
b
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
SIDE VIEW
SEE DETAIL “X”
c
END VIEW
L1
A A2
GAUGE
PLANE
0.25
L
A1
0° - 8°
DETAIL X
15
FN7119.7
May 7, 2007
EL5111, EL5211, EL5411
TSOT Package Family
MDP0049
e1
D
TSOT PACKAGE FAMILY
A
MILLIMETERS
6
N
SYMBOL
4
TSOT5
TSOT6
TSOT8
TOLERANCE
A
2X
1
5
2
(N/2)
0.25 C
2X N/2 TIPS
e
ddd M
B
C A-B D
b
NX
Max
0.05
±0.05
0.87
0.87
0.87
±0.03
0.38
0.38
0.29
±0.07
c
0.15 C D
1.00
0.05
A2
E
3
1.00
0.05
b
E1
2
1.00
A1
0.127
0.127
0.127
+0.07/-0.007
D
2.90
2.90
2.90
Basic
E
2.80
2.80
2.80
Basic
E1
1.60
1.60
1.60
Basic
e
0.95
0.95
0.65
Basic
e1
1.90
1.90
1.95
Basic
L
0.15 C A-B
0.40
±0.10
0.60
0.60
Reference
ddd
3
0.40
0.60
0.20
0.20
0.13
-
N
1
D
2X
0.40
L1
5
6
8
Reference
Rev. B 2/07
C
A2
SEATING
PLANE
1. Plastic or metal protrusions of 0.15mm maximum per side are
not included.
2. Plastic interlead protrusions of 0.15mm maximum per side are
not included.
A1
0.10 C
NOTES:
NX
3. This dimension is measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
(L1)
5. Index area - Pin #1 I.D. will be located within the indicated zone
(TSOT6 AND TSOT8 only).
H
A
GAUGE
PLANE
c
L
16
6. TSOT5 version has no center lead (shown as a dashed line).
0.25
4° ±4°
FN7119.7
May 7, 2007
EL5111, EL5211, EL5411
HMSOP (Heat-Sink MSOP) Package Family
E
B
0.25 M C A B
E1
MDP0050
HMSOP (HEAT-SINK MSOP) PACKAGE FAMILY
MILLIMETERS
1
N
SYMBOL
HMSOP8 HMSOP10
TOLERANCE
NOTES
A
A1
0.075
0.075
+0.025/-0.050
-
0.86
0.86
±0.09
-
0.30
0.20
+0.07/-0.08
-
0.15
0.15
±0.05
-
3.00
3.00
±0.10
1, 3
D1
1.85
1.85
Reference
-
E
4.90
4.90
±0.15
-
E1
3.00
3.00
±0.10
2, 3
E2
1.73
1.73
Reference
-
e
0.65
0.50
Basic
-
L
0.55
0.55
±0.15
-
L1
0.95
0.95
Basic
-
N
A
-
D
PIN #1
I.D.
Max.
c
(N/2)
1.00
b
(N/2)+1
1.00
A2
D
8
10
Reference
-
TOP VIEW
E2
EXPOSED
THERMAL PAD
D1
BOTTOM VIEW
Rev. 1 2/07
e
NOTES:
H
1. Plastic or metal protrusions of 0.15mm maximum per side are not
included.
C
SEATING
PLANE
2. Plastic interlead protrusions of 0.25mm maximum per side are
not included.
0.08 M C A B
b
0.10 C
N LEADS
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
SIDE VIEW
L1
A
c
END VIEW
SEE DETAIL " X "
A2
GAUGE
0.25 PLANE
L
3° ±3°
A1
DETAIL X
17
FN7119.7
May 7, 2007
EL5111, EL5211, EL5411
Thin Shrink Small Outline Plastic Packages (TSSOP)
M14.173
N
INDEX
AREA
E
0.25(0.010) M
E1
2
SYMBOL
MIN
MAX
MILLIMETERS
MIN
MAX
NOTES
A
0.25
0.010
SEATING PLANE
-
0.15
-
0.031
0.041
0.80
1.05
-
0.0075
0.0118
0.19
0.30
9
c
α
e
A1
b
c
B S
0.0035
0.0079
0.09
0.20
-
0.195
0.199
4.95
5.05
3
E1
A2
0.10(0.004)
C A M
1.20
0.05
D
-C-
0.10(0.004) M
-
0.006
b
A
D
0.047
0.002
A2
L
-
A1
3
0.05(0.002)
-A-
INCHES
GAUGE
PLANE
-B1
14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE
B M
0.169
0.177
4.30
4.50
4
e
0.026 BSC
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E.
-
E
0.246
0.256
6.25
6.50
-
L
0.0177
0.0295
0.45
0.75
6
8o
0o
N
NOTES:
0.65 BSC
α
14
0o
14
7
8o
Rev. 2 4/06
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
18
FN7119.7
May 7, 2007