Raczej nie ? Strona Fujitsu milczy o tym układzie Link Jak potrafisz znależć gdzie jaki pin. np. to: Vcc , masa GND, to na zwarcie http://obrazki.elektroda.pl/8975241300_1485890917_thumb.jpg na wej. masz chyba dwa polowe (P-ch 30V,13A, 12 mOhm)/ patrz zał. W Toshinbach stawiali też Si4835BDY (P-ch., 30V,10A, 0.014 ohm) P.s Może to coś"na wzór" MB39A119 QFN28, patrz zał.
FUJITSU SEMICONDUCTOR
DATA SHEET
DS04-27247-2E
ASSP for Power Supply Applications (Secondary battery)
DC/DC Converter IC of Synchronous
Rectification for charging Li-ion battery
MB39A119
■ DESCRIPTION
The MB39A119 is the N-ch MOS drive of the synchronous rectification type DC/DC converter IC using pulsewidth modulation (PWM) type that can charge Li-ion battery from 1 cell to 4 cells and suitable for down-conversion.
This IC integrates built-in comparator for the voltage detection of the AC adapter and switches the power supply
to the AC adapter or battery automatically, enabling supply it to system. In addition, the constant voltage control
state detection function is built in, which prevents mis-detecting the full charge. The MB39A119 provides a wide
range of power supply voltage and low standby current, high efficiency, making it ideal for use as a built-in charge
device in products such as notebook PC.
■ FEATURES
•
•
•
•
•
High efficiency : 97 % (Max)
High-frequency operation : 1 MHz (Max)
Built-in off time control function
Built-in voltage detection function of AC adapter (ACOK, XACOK terminal)
Preventing mis-detection for the full charge by the constant voltage control state detection function (CVM
terminal)
(Continued)
■ PACKAGE
28-pin plastic QFN
(LCC-28P-M10)
Copyright©2005-2006 FUJITSU LIMITED All rights reserved
MB39A119
(Continued)
• Built-in two constant current control circuits
• Analog control of constant current value is possible ( + INE1, + INE2 terminal)
• Built-in output stage for N-ch MOS FET synchronous rectification
• Built-in charge stop function at low input voltage
• Output voltage setting accuracy : 4.2 V ± 0.74 % (Ta= − 10 °C to + 85 °C)
• Built-in high accuracy charge current detection amplifier : ± 4 %
(At input voltage difference 100 mV with Voltage gain 24.5 (V/V)
• Built-in high accuracy input current detection amplifier : ± 3 %
(At input voltage difference 100 mV with Voltage gain 25 (V/V)
• Arbitrary output voltage can be set by external resistor
• In IC standby mode, output voltage setting resistor is made to be open to prevent inefficient current loss
• Quiescent current : 1.9 mA (Typ)
• Standby current : 0 µA (Typ)
• Package : QFN28
2
MB39A119
■ PIN ASSIGNMENT
CB
OUT-1
VS
VB
OUT-2
PGND
XACOK
(TOP VIEW)
28
27
26
25
24
23
22
GND
+INC1
3
19
VREF
ACIN
4
18
RT
ACOK
5
17
CS
CVM
6
16
OUTD
+INE1
7
15
−INE3
8
9
10
11
12
13
14
FB123
20
−INE2
2
+INE2
−INC1
−INC2
CTL
+INC2
21
OUTC2
1
−INE1
VCC
(LCC-28P-M10)
Note : Connect IC’s radiation board at bottom side to potential of GND.
3
MB39A119
■ PIN DESCRIPTION
Pin No.
Pin Name
I/O
Description
1
VCC
⎯
Power supply terminal for reference voltage and control circuit.
2
−INC1
I
Input current detection amplifier (Current Amp1) input terminal.
3
+ INC1
I
Input current detection amplifier (Current Amp1) input terminal.
4
ACIN
I
AC adapter voltage detection block (AC Comp.) input terminal.
5
ACOK
O
AC adapter voltage detection block (AC Comp.) output terminal.
ACOK = L when ACIN = H, ACOK = Hi-Z when ACIN = L,
ACOK = Hi-Z when CTL = L
6
CVM
O
Constant voltage control state detection block (CV Comp.) output terminal.
7
+ INE1
I
Error amplifier (Error Amp1) non-inverted input terminal.
8
−INE1
I
Error amplifier (Error Amp1) inverted input terminal.
9
OUTC2
O
Charge current detection amplifier (Current Amp2) output terminal.
10
+ INC2
I
Charge current detection amplifier (Current Amp2) input terminal.
11
−INC2
I
Charge current detection amplifier (Current Amp2) and low input voltage
detection comparator (UV Comp.) input terminal.
12
+ INE2
I
Error amplifier (Error Amp2) non-inverted input terminal.
13
− INE2
I
Error amplifier (Error Amp2) inverted input terminal.
14
FB123
O
Error amplifier (Error Amp1, 2, 3) output terminal.
15
−INE3
I
Error amplifier (Error Amp3) inverted input terminal.
16
O
17
CS
⎯
Soft-start capacitor connection terminal.
18
RT
⎯
Triangular wave oscillation frequency setting resistor connection terminal.
19
VREF
O
Reference voltage output terminal.
20
GND
⎯
Ground terminal.
21
CTL
I
Power supply control terminal for DC/DC converter block.
22
XACOK
O
AC adapter voltage detection block (AC Comp.) output terminal.
XACOK = Hi-Z when ACIN = H, XACOK = L when ACIN = L,
XACOK = Hi-Z when CTL = L
23
PGND
⎯
Ground terminal.
24
OUT-2
O
External synchronous rectification side FET gate drive output terminal.
25
VB
O
Bias output terminal for output circuit.
26
VS
⎯
External main side FET source conneciton terminal.
27
OUT-1
O
External main side FET gate drive output terminal.
28
4
OUTD
This terminal is set to Hi-Z to prevent loss of current through the output
voltage setting resistor when IC is standby mode.
OUTD = Hi-Z when CTL = L
OUTD = L when CTL = H
CB
⎯
Boot strap capacitor connection terminal.
The capacitor is connected between the CB terminal and the VS terminal.
MB39A119
■ BLOCK DIAGRAM
ACIN
4
ACOK
5
XACOK
22
CVM
6
& lt; CV Comp. & gt;
−
& lt; AC Comp. & gt;
+
+
−
2.0 V
+INC1 3
−INC1 2
2.6 V
0.1 V & lt; UV Comp. & gt;
+
& lt; Current Amp1 & gt;
+
×25
−
100 kΩ
3.1 V
5
28 CB
+
−
−INE2 13
−2.5 V
−1.5 V
OUTC2 9
& lt; Current Amp2 & gt;
+
+INC2 10
−INC2 11
×24.5
−
+INE2 12
25 VB
& lt; PWM Comp. & gt;
−
+
+INE1 7
5.0 V
−INC2
(VO)
& lt; Error Amp1 & gt;
−INE1 8
VB Reg.
−
Drv-1
Drive logic
Hi Side Only
VCC
1
26 VS
Drv-2
& lt; Error Amp2 & gt;
27 OUT-1
24 OUT-2
Off time
Control
−
+
23 PGND
H: UVLO, UV
release
FB123 14
& lt; UVLO & gt;
VCCUVLO
& lt; Error Amp3 & gt;
−
−INE3 15
+
4.2 V
OUTD 16
VBUVLO
Slope
Control
VREFUVLO
+
−
& lt; SOFT & gt;
VREF
2.6 V
OUTC2
10 µA
−
& lt; Over Current Det. & gt;
CS 17
+
+
0.3 V
+INC2
−
0.2 V
+
−INC2
(Vo)
& lt; OSC & gt;
CT
VCC
& lt; Synchronous Cnt. & gt;
4.2 V
bias
& lt; REF & gt;
& lt; CTL & gt;
VREF
5.0 V
18
RT
19
VREF
DC/DC
ON/OFF
21 CTL
20
GND
5
MB39A119
■ ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Condition
Power supply voltage
VCC
CB terminal input voltage
Control input voltage
Rating
Unit
Max
Unit
VCC terminal
⎯
27
V
VCB
CB terminal
⎯
32
V
VCTL
CTL terminal
⎯
27
V
VINE
+ INE1, + INE2, − INE1, − INE2,
− INE3 terminal
⎯
VCC + 0.3
V
VINC1
+ INC1, − INC1 terminal
⎯
VCC + 0.3
V
VINC2
Input voltage
Min
+ INC2, − INC2 terminal
⎯
20
V
OUTD terminal output voltage
VOUTD
OUTD terminal
⎯
20
V
ACIN input voltage
VACIN
ACIN terminal
⎯
VCC
V
ACOK terminal output voltage
VACOK
ACOK terminal
⎯
27
V
XACOK terminal output voltage
VXACOK
XACOK terminal
⎯
27
V
CVM terminal output voltage
VCVM
CVM terminal
⎯
27
V
Output current
IOUT
⎯
⎯
60
mA
Power dissipation
PD
⎯
4400*1,*2
⎯
1900*1,*3
mW
−55
+ 125
°C
Storage temperature
Ta ≤ +25 °C
TSTG
⎯
*1 : The packages are mounted on the dual-sided epoxy board (10 cm × 10cm) .
*2 : With connection of exposed pad and with thermal via.
*3 : With connection of exposed pad and without thermal via.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
6
MB39A119
■ RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Condition
Power supply voltage
VCC
CB terminal input voltage
Value
Unit
Min
Typ
Max
VCC terminal
8
⎯
25
V
VCB
CB terminal
⎯
⎯
30
V
Reference voltage output
current
IREF
VREF terminal
−1
⎯
0
mA
Bias output current
IVB
VB terminal
−1
⎯
0
mA
VINE
+ INE1, + INE2, − INE1,
− INE2, − INE3 terminal
0
⎯
5
V
VINC1
+ INC1, −INC1 terminal
7
⎯
VCC
V
VINC2
+ INC2, −INC2 terminal
0
⎯
19
V
Input voltage difference
DVINC
Current detection voltage range
0
⎯
140
mV
OUTD terminal output voltage
VOUTD
OUTD terminal
0
⎯
19
V
OUTD terminal output current
IOUTD
OUTD terminal
0
⎯
2
mA
CTL terminal input voltage
VCTL
CTL terminal
0
⎯
25
V
ACIN input voltage
VACIN
ACIN terminal
0
⎯
VCC
V
ACOK terminal output voltage
VACOK
ACOK terminal
0
⎯
25
V
XACOK terminal output
voltage
VXACOK
XACOK terminal
0
⎯
25
V
CVM terminal output voltage
VCVM
CVM terminal
0
⎯
25
V
Peak output current
IOUT
−1200
⎯
+1200
mA
Oscillation frequency
fOSC
⎯
200
500
1000
kHz
Timing resistor
RT
RT terminal
⎯
39
⎯
kΩ
Soft-start capacitor
CS
CS terminal
⎯
0.22
⎯
µF
CB terminal capacitor
CB
CB terminal
⎯
0.1
⎯
µF
Bias output capacitor
CVB
VB terminal
⎯
1.0
⎯
µF
Reference voltage output
capacitor
CREF
VREF terminal
⎯
0.1
1.0
µF
Ta
⎯
−30
+25
+85
°C
Input voltage
Operating ambient
temperature
Duty ≤ 5 % (t=1/fOSC × Duty)
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
7
MB39A119
■ ELECTRICAL CHARACTERISTICS
(VCC = 19 V, VB = 0 mA, VREF = 0 mA, Ta = +25 °C)
Parameter
Symbol
Pin No.
VREF1
19
VREF2
Input stability
Conditions
Value
Unit
Min
Typ
Max
Ta = +25 °C
4.963
5.000
5.037
V
19
Ta = −10 °C to + 85 °C
4.95
5.00
5.05
V
Line
19
VCC = 8 V to 25 V
⎯
1
10
mV
Load stability
Load
19
VREF = 0 mA to −1 mA
⎯
1
10
mV
Short-circuit
output current
Ios
19
VREF = 1 V
−60
−30
−15
mA
VTLH
1
VCC
⎯
7.5
7.9
V
VTHL
1
VCC
7.0
7.4
⎯
V
VH
1
VCC
⎯
0.1
⎯
V
VTLH
25
VB
3.8
4.0
4.2
V
VTHL
25
VB
3.1
3.3
3.5
V
VH
25
VB
⎯
0.7
⎯
V
VTLH
19
VREF
2.5
2.7
2.9
V
VTHL
19
VREF
2.3
2.5
2.7
V
Hysteresis width
VH
19
VREF
⎯
0.2
⎯
V
Charge current
ICs
17
−14
−10
−6
µA
Oscillation
frequency
fosc
27
RT = 39 kΩ
450
500
550
kHz
Frequency
temperature
stability
∆f/fdt
27
Ta = −30 °C to + 85 °C
⎯
1*
⎯
%
Input offset
voltage
VIO
7, 8
⎯
⎯
1
5
mV
Input bias current
IB
7, 8
⎯
−50
−15
⎯
nA
Voltage gain
AV
7, 8, 14
DC
⎯
100*
⎯
dB
Frequency
bandwidth
BW
7, 8, 14
AV = 0 dB
⎯
1.2*
⎯
MHz
VFBH
14
⎯
2.9
3.1
⎯
V
VFBL
14
⎯
⎯
0.8
0.9
V
ISOURCE
14
FB123 = 2 V
⎯
−60
−30
µA
ISINK
14
FB123 = 2 V
2.0
4.0
⎯
mA
Output voltage
Reference
voltage
block
[REF]
Threshold voltage
Hysteresis width
Under
voltage
Threshold voltage
lockout
protection
circuit block Hysteresis width
[UVLO]
Threshold voltage
Soft-start
block
[SOFT]
Triangular
wave
oscillator
block
[OSC]
Error
amplifier
block
[Error
Amp1]
Output voltage
Output source
current
Output sink
current
⎯
* : Standard design value
(Continued)
8
MB39A119
(VCC = 19 V, VB = 0 mA, VREF = 0 mA, Ta = +25 °C)
Parameter
Symbol Pin No.
Conditions
Value
Min
Typ
Max
Unit
VIO
12, 13
⎯
⎯
1
5
mV
Input bias current
IB
12, 13
⎯
−50
−15
⎯
nA
Voltage gain
AV
12, 13,
DC
14
⎯
100*
⎯
dB
Frequency bandwidth
BW
12, 13,
AV = 0dB
14
⎯
1.2*
⎯
MHz
Input offset voltage
Error
amplifier
block
[Error
Amp2]
Output voltage
Output source current
Output sink current
VFBH
14
⎯
2.9
3.1
⎯
V
VFBL
14
⎯
⎯
0.8
0.9
V
ISOURCE
14
FB123 = 2 V
⎯
−60
−30
µA
ISINK
14
FB123 = 2 V
2.0
4.0
⎯
mA
VTH1
Threshold voltage
14, 15 FB123 = 2 V
VTH2
14, 15
4.179 4.200 4.221
FB123 = 2 V,
Ta = −10 °C to + 85 °C
V
4.169 4.200 4.231
V
Voltage gain
Error
amplifier
block
[Error
Amp3]
AV
14, 15 DC
⎯
100*
⎯
dB
Frequency bandwidth
BW
14, 15 AV = 0 dB
⎯
1.2*
⎯
MHz
VFBH
14
⎯
2.9
3.1
⎯
V
VFBL
14
⎯
⎯
0.8
0.9
V
ISOURCE
14
FB123 = 2 V
⎯
−60
−30
µA
Output sink current
ISINK
14
FB123 = 2 V
2.0
4.0
⎯
mA
OUTD terminal leak
current
ILEAK
16
OUTD = 19 V
⎯
0
1
µA
OUTD terminal output
ON resistance
RON
16
OUTD = 1 mA
⎯
35
50
Ω
VOUTC1
8
+ INC1 = − INC1 = 7 V to 19 V,
2.425
∆VIN = 100 mV
2.5
2.575
V
VOUTC2
8
+ INC1 = − INC1 = 7 V to 19 V,
0.425
∆VIN = 20 mV
0.5
0.575
V
Voltage gain
AV
2, 3, 8
+ INC1 = − INC1 = 7 V to 19 V,
24.25
∆VIN = 100 mV
25
25.75 V/V
Input offset voltage
VIO
2, 3, 8
+ INC1 = − INC1 = 7 V to 19 V
−3
⎯
+3
mV
IINC1
2, 3
+ INC1 = − INC1 = 7 V to 19 V
⎯
20
30
µA
IINC2
2, 3
+ INC1 = − INC1 = 7 V to 19 V,
CTL = 0 V
⎯
0
1
µA
⎯
3.0*
⎯
MHz
Output voltage
Output source current
Current detection
voltage
Current
detection
amplifier
block
[Current
Amp1]
Input current
Frequency bandwidth
Output voltage
Output source current
Output sink current
BW
2, 3, 8 AV = 0 dB
VOUTCH
8
⎯
3.7
4.0
⎯
V
VOUTCL
8
⎯
⎯
0.04
0.2
V
ISOURCE
8
-INE1 = 2 V
⎯
−1.2
−0.6
mA
ISINK
8
-INE1 = 2 V
100
200
⎯
µA
* : Standard design value
(Continued)
9
MB39A119
(VCC = 19 V, VB = 0 mA, VREF = 0 mA, Ta = +25 °C)
Parameter
Symbol Pin No.
Conditions
Value
Min
Typ
Max
Unit
VOUTC1
9
+ INC2 = − INC2 = 3 V to 19 V,
∆VIN = 100 mV
2.38
2.48
2.58
V
VOUTC2
9
+ INC2 = − INC2 = 3 V to 19 V,
∆VIN = 20 mV
0.44
0.52
0.60
V
VOUTC3
9
+ INC2 = − INC2 = 0 V to 3 V,
∆VIN = 100 mV
2.24
2.45
2.66
V
VOUTC4
9
+ INC2 = − INC2 = 0 V to 3 V,
∆VIN = 20 mV
0.30
0.5
0.70
V
Voltage gain
AV
9, 10, 11
+ INC2 = − INC2 = 3 V to 19 V,
23.76
∆VIN = 100 mV
24.5
25.24 V/V
Input offset voltage
VIO
9, 10, 11 + INC2 = − INC2 = 3 V to 19 V −1.5
+1.5
+4.5
mV
Current detection
voltage
Current
detection
amplifier
block
[Current
Amp2]
I+INCH
Frequency
bandwidth
⎯
30
45
µA
I−INCH
11
+ INC2 = − INC2 = 3 V to 19 V,
∆VIN = 100 mV
⎯
0.1*
⎯
µA
10, 11
−300
−200
⎯
µA
⎯
3.0*
⎯
MHz
BW
+ INC2 = − INC2 = 0 V
9, 10, 11 AV = 0 dB
Output source
current
Output sink current
PWM
comparator block
[PWM
Comp.]
Threshold voltage
Output
block
[Drv-1, 2]
Output ON
resistance
Threshold voltage
Hysteresis width
VOUTCH
9
⎯
3.9
4.2
⎯
V
VOUTCL
9
⎯
⎯
0.04
0.2
V
ISOURCE
9
OUTC2 = 2 V
⎯
−1.2
−0.6
mA
ISINK
9
OUTC2 = 2 V
100
200
⎯
µA
VTL
Output voltage
Under
input
voltage
detection
comparator block
[UV
Comp.]
+ INC2 = − INC2 = 3 V to 19 V,
∆VIN = 100 mV
IINCL
Input current
10
14
Duty cycle = 0%
⎯
1.5
⎯
V
VTH
14
Duty cycle = 100%
⎯
2.5
⎯
V
ROH
24, 27 OUT-1, OUT-2 = −100 mA
⎯
4
7
Ω
ROL
24, 27 OUT-1, OUT-2 = 100 mA
⎯
1
3.5
Ω
VTLH
11
−INC2 = 12.6 V
12.6
12.8
13.0
V
VTHL
11
−INC2 = 12.6 V
12.5
12.7
12.9
V
VH
11
⎯
0.1
⎯
V
⎯
* : Standard design value
(Continued)
10
MB39A119
(Continued)
(VCC = 19 V, VB = 0 mA, VREF = 0 mA, Ta = +25 °C)
Parameter
Overcurrent
detection
block
[Over
Current Det.]
Symbol Pin No.
Conditions
−INC2 = 12.6 V
Value
Unit
Min
Typ
Max
12.75
12.8
12.85
V
VTLH
11
VTLH
4
⎯
2.056
2.12
2.184
V
VTHL
4
⎯
1.959
2.02
2.081
V
VH
4
⎯
⎯
0.1
⎯
V
ACOK terminal
output leak current
ILEAK
5
ACOK = 25 V
⎯
0
1
µA
ACOK terminal
output ON resistance
RON
5
ACOK = 1 mA
⎯
200
400
Ω
XACOK terminal
output leak current
ILEAK
22
XACOK = 25 V
⎯
0
1
µA
XACOK terminal
output ON resistance
RON
22
XACOK = 1 mA
⎯
200
400
Ω
VTLH
14
⎯
⎯
2.7*
⎯
V
VTHL
14
⎯
⎯
2.6*
⎯
V
VH
14
⎯
⎯
0.1*
⎯
V
CVM terminal
output leak current
ILEAK
6
CVM = 25 V
⎯
0
1
µA
CVM terminal
output ON resistance
RON
6
CVM = 1 mA
⎯
200
400
Ω
VTLH
17
⎯
2.55
2.6
2.65
V
VTHL
17
⎯
2.50
2.55
2.60
V
VH
17
⎯
⎯
0.05
⎯
V
VTLH
9
⎯
0.35
0.4
0.45
V
VTHL
9
⎯
0.25
0.3
0.35
V
Hysteresis width
VH
9
⎯
⎯
0.1
⎯
V
Output voltage
VB
25
⎯
4.9
5.0
5.1
V
Load stability
Load
25
VB = 0 mA to − 10 mA
⎯
10
50
mV
CTL
input voltage
VON
21
IC operating state
2
⎯
25
V
VOFF
21
IC standby state
0
⎯
0.8
V
ICTLH
21
CTL = 5 V
⎯
25
40
µA
ICTLL
21
CTL = 0 V
⎯
0
1
µA
Standby current
ICCS
1
CTL = 0 V
⎯
0
10
µA
Power supply current
ICC
1
CTL = 5 V
⎯
1.9
2.9
mA
Threshold voltage
Threshold voltage
Hysteresis width
AC adapter
voltage
detection
block
[AC Comp.]
Constant
voltage
control state
detection
block
[CV Comp.]
Threshold voltage
Hysteresis width
CS threshold
voltage
Synchronous
rectification
Hysteresis width
control block
[Synchronous Light load detection
threshold voltage
Cnt.]
Bias voltage
block
[VB]
Control block
[CTL]
Input current
General
* : Standard design value
11
MB39A119
■ TYPICAL CHARACTERISTICS
Power supply current ICC (mA)
Power Supply Current vs. Power Supply Voltage
Reference Voltage vs. Power Supply Voltage
Reference voltage VREF (V)
6
5
4
3
2
Ta = +25 °C
CTL = 5 V
1
0
0
5
10
15
20
25
6
5
4
3
2
Ta = +25 °C
CTL = 5 V
VREF = 0 mA
1
0
0
5
Power supply voltage VCC (V)
Reference voltage VREF (V)
Reference voltage VREF (V)
3
2
1
0
5
10
15
20
25
30
35
5.04
5.02
5.00
4.98
4.96
4.94
4.92
−40
700
9
8
7
600
6
VREF
500
5
400
4
300
3
ICTL
200
2
100
1
0
0
25
0
5
10
15
20
CTL terminal voltage VCTL (V)
Error amplifier threshold voltage
VTH (V)
800
10
Reference voltage VREF (V)
CTL terminal current ICTL (µA)
Ta = +25 °C
VCC = 19 V
VREF = 0 mA
−20
0
20
40
60
80
100
Error Amplifier Threshold Voltage vs.
Operating Ambient Temperature
CTL Terminal Current, Reference Voltage vs.
CTL Terminal Voltage
900
VCC = 19 V
CTL = 5 V
5.06
Operating ambient temperature Ta ( °C)
Load current IREF (mA)
1000
25
5.08
4
0
20
Reference Voltage vs. Operating Ambient Temperature
Ta = +25 °C
VCC = 19 V
CTL = 5 V
5
15
Power supply voltage VCC (V)
Reference Voltage vs. Load Current
6
10
4.25
VCC = 19 V
CTL = 5 V
4.24
4.23
4.22
4.21
4.20
4.19
4.18
4.17
4.16
4.15
−40
−20
0
20
40
60
80
100
Operating ambient temperature Ta ( °C)
(Continued)
12
MB39A119
Triangular Wave Oscillation Frequency vs.
Timing Resistor
580
10000
Triangular wave oscillation
frequency fOSC (kHz)
Triangular wave oscillation
frequency fOSC (kHz)
Triangular Wave Oscillation Frequency vs.
Operating Ambient Temperature
VCC = 19 V
CTL = 5 V
RT = 39 kΩ
560
540
520
500
480
460
440
420
−40
−20
0
20
40
60
80
100
Ta = +25 °C
VCC = 15 V
CTL = 5 V
1000
100
10
1
Operating ambient temperature Ta ( °C)
100
1000
Timing Resistor RT (kΩ)
50
40
30
20
10
0
−10
−20
−30
−40
−50
100
225
180
135
90
45
0
−45
−90
−135
−180
−225
10M
VCC = 19 V
Ta = +25 °C
φ
Av
1k
10k
100k
1M
Phase φ (degree)
Gain AV (dB)
Error Amplifier Gain, Phase vs. Frequency (ERR1, 2)
4.2 V
240 kΩ
10 kΩ 10 kΩ
IN
1 µF 2.4 kΩ
+
10 kΩ
8
(13)
7
(12)
−
OUT
14
+
10 kΩ
Error Amp1
(Error Amp2)
Frequency f (Hz)
50
40
30
20
10
0
−10
−20
−30
−40
−50
100
225
180
135
90
45
0
−45
−90
−135
−180
−225
10M
VCC = 19 V
Ta = +25 °C
φ
Av
1k
10k
100k
1M
Phase φ (degree)
Gain AV (dB)
Error Amplifier Gain, Phase vs. Frequency (ERR3)
240 kΩ
10 kΩ
IN
1 µF 2.4 kΩ
+
15
−
+
10 kΩ
OUT
14
4.2 V
Error Amp3
Frequency f (Hz)
(Continued)
13
MB39A119
(Continued)
Current Detection Amplifier Gain, Phase vs. Frequency
225
50.0
180
135
90
45
0
−45
−90
−135
−180
−225
10M
Av
φ
1k
100k
10k
1M
Phase φ (degree)
Gain AV (dB)
40.0
30.0
20.0
10.0
0.0
−10.0
−20.0
−30.0
−40.0
−50.0
Ta = +25 °C
VCC = 19 V
+INC1
−INC1
3
2
+
× 25
−
−INE1
8
OUT
Current Amp1
19 V
18.95 V
Frequency f (Hz)
Current Detection Amplifier Gain, Phase vs. Frequency
225
40.0
30.0
20.0
10.0
0.0
−10.0
−20.0
−30.0
−40.0
−50.0
Ta = +25 °C
180
135
90
45
0
−45
−90
−135
−180
−225
10M
Av
φ
1k
100k
10k
1M
VCC = 19 V
Phase φ (degree)
Gain AV (dB)
50.0
Frequency f (Hz)
Power Dissipation vs. Operating Ambient Temperature
Power dissipation PD (mW)
5000
QFN-24 (with thermal via)
4500
4400
4000
3500
3000
QFN-24
(without thermal via)
2500
2000
1900
1500
1000
500
0
−50
−25
0
25
50
75
100
125
Operating ambient temperature Ta ( °C)
14
+INC2
10
−INC2
11
+
× 24.5
−
OUTC2
9
OUT
Current Amp2
12.6 V
12.55 V
MB39A119
■ FUNCTION DESCRIPTION
1. DC/DC Converter Block
(1) Reference voltage block (REF)
The reference voltage circuit uses the voltage supplied from the VCC terminal (pin 1) to generate a temperature
compensated, stable voltage (5.0 V Typ) used as the reference power supply voltage for the IC’s internal circuitry.
This block can also be used to obtain a load current to a maximum of 1 mA from the reference voltage VREF
terminal (pin 19) .
(2) Triangular wave oscillator block (OSC)
The triangular wave oscillator block has built-in capacitor for frequency setting and generates the triangular wave
oscillation waveform by connecting the triangular wave oscillation frequency setting resistor with the RT terminal
(pin 17) .
The triangular wave is input to the PWM comparator circuits on the IC.
(3) Error amplifier block (Error Amp1)
This amplifier detects the output signal from the current detection amplifier (Current Amp1) , compares this to
the +INE1 terminal (pin 7) , and outputs a PWM control signal to be used in controlling the charge current.
In addition, an arbitrary loop gain can be set up by connecting a feedback resistor and capacitor between the
FB123 terminal (pin 14) and -INE1 terminal (pin 8) , providing stable phase compensation to the system.
(4) Error amplifier block (Error Amp2)
This amplifier detects the output signal from the current detection amplifier (Current Amp2) , compares this to
the +INE2 terminal (pin 12) , and outputs a PWM control signal to be used in controlling the charge current.
In addition, an arbitrary loop gain can be set up by connecting a feedback resistor and capacitor between the
FB123 terminal (pin 14) and -INE2 terminal (pin 13) , providing stable phase compensation to the system.
(5) Error amplifier block (Error Amp3)
This error amplifier (Error Amp3) detects the output voltage from the DC/DC converter and outputs the PWM
control signal. External output voltage setting resistors can be connected to the error amplifier inverted input
terminal to set the desired level of output voltage from 1 cell to 4 cells.
In addition, an arbitrary loop gain can be set by connecting a feedback resistor and capacitor from the FB123
terminal (pin 14) to the -INE3 terminal (pin 15) of the error amplifier, enabling stable phase compensation to the
system.
(6) Current detection amplifier block (Current Amp1)
The current detection amplifier (Current Amp1) detects a voltage drop which occurs between both ends of the
output sense resistor (RS2) due to the flow of the AC adapter current, using the +INC1 terminal (pin 3) and -INC1
terminal (pin 2) . The AC adapter current control signal is amplified to 25 times and output to the inverse input
terminal of Error Amp1 through the internal 100 kΩ.
This amplifier cannot use for detecting the charge current.
(7) Current detection amplifier block (Current Amp2)
The current detection amplifier (Current Amp2) detects a voltage drop which occurs between both ends of the
output sense resistor (RS1) due to the flow of the charge current, using the +INC2 terminal (pin 10) and -INC2
terminal (pin 11) . The signal amplified to 24.5 times is output to the OUTC2 terminal (pin 9) .
(8) PWM comparator block (PWM Comp.)
The PWM comparator circuit is a voltage-pulse width converter for controlling the output duty of the error
amplifiers (Error Amp1 to Error Amp3) depending on their output voltage.
The PWM comparator circuit compares with either of low voltages between the triangular wave voltage generated
by the triangular wave oscillator and the error amplifier output voltage, turns on the main side output transistor
15
MB39A119
and turns off on the synchronous rectification side output transistor, during the interval in which the triangular
wave voltage is lower than the error amplifier output voltage.
(9) Output block (Drv-1, 2)
The output circuit uses a CMOS configuration capable of driving an external N-ch MOS FET both main side and
synchronous rectification side.
(10) Control block (CTL)
Setting the CTL terminal (pin 21) “L” level places in the standby mode.
CTL function table
CTL
Power
OUTD
L
OFF (Standby)
Hi-Z
H
ON (Active)
L
(11) Bias voltage block (VB)
Bias voltage block outputs 5 V (Typ) for the power supply of the output circuit and for setting the bootstrap voltage.
(12) Off time control block (Off time Control)
When MB39A119 operates by high on-duty, voltage difference of both ends of boot strap capacitor CB is
decreasing gradually. In such the case, off time control block charges with CB by compulsorily generating off
time (0.3 µs Typ) .
(13) Overcurrent detection block (Over Current Det.)
Overcurrent detection block detects the 0.2 V (Typ) or more potential difference between +INC2 terminal (pin
10) and -INC2 terminal (pin 11) . When excessive current flows to the charge direction due to load-sudden
change, it determines the overcurrent, makes CS terminal (pin 17) “L” level, and makes the on duty 0 %. After
finishing the overcurrent, MB39A119 restarts with the soft-start operation.
(14) Synchronous rectification control block (Synchronous Cnt.)
CS terminal (pin 17) and 2.6 V (Typ) are compared. Output OUT-2 terminal (pin 24) for synchronous rectification
side FET drive in the soft-start is fixed at “L” level.
Output OUTC2 terminal of current detection amplifier block (Current Amp2) (pin 9) and 0.3 V (Typ) are compared,
and output OUT-2 terminal (pin 24) for synchronous rectification side FET drive is fixed at “L” level at light-load.
16
MB39A119
2. Protection Function
(1) Under voltage lockout protection circuit block (VREF-UVLO)
A momentary decrease in internal reference voltage (VREF) may cause malfunctions in the control IC, resulting
in breakdown or degradation of the system.
To prevent such malfunction, the under voltage lockout protection circuit detects internal reference voltage drop
and fixes the OUT-1 terminal (pin 27) and the OUT-2 terminal (pin 24) to the “L” level. The system restores voltage
supply when the internal reference voltage reaches the threshold voltage of the under voltage lockout protection
circuit.
Protection circuit (VREF-UVLO) operation function table
When UVLO is operating (VREF voltage is lower than UVLO threshold voltage) , the logic of the following terminal
is fixed.
OUTD
OUT-1
OUT-2
CS
VB
Hi-Z
L
L
L
L
(2) Under voltage lockout protection circuit block (VCC-UVLO, VB-UVLO)
The transient state or a momentary decrease in power supply voltage, which occurs when the bias voltage (VB)
for output circuit is turned on, may cause malfunctions in the control IC, resulting in breakdown or degradation
of the system.
To prevent such malfunction, the under voltage lockout protection circuit detects a bias voltage drop and fixes
the OUT-1 terminal (pin 27) and the OUT-2 terminal (pin 24) to the “L” level. The system restores voltage supply
when the power supply voltage or internal reference voltage reaches the threshold voltage of the under voltage
lockout protection circuit.
Protection circuit (VCC-UVLO, VB-UVLO) operation function table
When UVLO is operating (VCC voltage or VB voltage is lower than UVLO threshold voltage) , the logic of the
following terminal is fixed.
OUT-1
OUT-2
CS
L
L
L
(3) Under input voltage detection comparator block (UV Comp.)
VCC terminal (pin 1) voltage and -INC2 terminal (pin 11) voltage are compared, and VCC voltage is lower than
the battery voltage +0.1 V (Typ) and fixes the OUT-1 terminal (pin 27) and OUT-2 terminal (pin 24) to the “L” level.
The system restores voltage supply when the input voltage reaches the threshold voltage of the under input
voltage detection comparator.
Protection circuit (UV Comp.) operation function table
When under input voltage is detected (Input voltage is lower than UV Comp. threshold voltage) , the logic of the
following terminal is fixed.
OUT-1
OUT-2
CS
L
L
L
17
MB39A119
3. Detection Functions
(1) AC adapter voltage detection block (AC Comp.)
When ACIN terminal (pin 4) voltage is lower than 2.0 V (Typ) , AC adapter voltage detection block (AC Comp.)
outputs “Hi-Z” level to the ACOK terminal (pin 5) and outputs “L” level to the XACOK terminal (pin 22) . When
CTL terminal (pin 21) is set to “L” level, ACOK terminal (pin 5) and XACOK terminal (pin 22) are fixed to “Hi-Z” level.
AC adapter detection function table
The logic of the following terminal is fixed according to the connection state of the AC adapter.
ACIN
ACOK
XACOK
H
L
Hi-Z
L
Hi-Z
L
(2) Constant voltage control state detection block (CV Comp.)
When CV Comp. detects that the FB123 terminal (pin 14) voltage of the error amplifier (Error Amp3) output
terminal becomes 2.6 V (Typ) or less, “L” level is output to constant voltage control state detection block output
terminal CVM terminal (pin 6) .
Charge control state function table
Error Amp3 output (FB123)
Status
& gt; 2.6 V
Hi-Z
Constant current control
≤ 2.6 V
18
CVM
L
Constant voltage control
MB39A119
■ CONSTANT CHARGING VOLTAGE AND CURRENT OPERATION
The MB39A119 is DC/DC converter IC with the pulse width modulation method (PWM method) .
In the output voltage control loop, the output voltage of the DC/DC converter is detected, and the Error Amp3
compares internal reference voltage 4.2 V and DC/DC converter output to output the PWM controlled signal.
In the charging current control loop, the voltage drop generated at both ends of charging current sense resistor
(RS1) is sensed by +INC2 terminal (pin 10) , -INC2 terminal (pin 11) of Current Amp2, and the signal is output
to OUTC2 terminal (pin 9) , which is amplified by 24.5 times. Error Amp2 compares the OUTC2 terminal (pin 9)
voltage, which is the output of Current Amp2, and +INE2 terminal (pin 12) to output the PWM control signal,
and it regulates the charging current.
In AC adapter current control loop, the voltage drop generated at both ends of AC adapter current sense resistor
(RS2) is sensed by +INC1 terminal (pin 3) , -INC1 terminal (pin 2) of Current Amp1, and the signal is output to
-INE1 terminal (pin 8) , which is amplified by 25 times. Error Amp1 compares -INE1 terminal (pin 8) voltage,
which is output of Current Amp1, and +INE1 terminal (pin 7) to output PWM controlled signal, and it limits the
charging current due to the AC adapter current not to exceed the setting value.
The PWM comparator compares the triangular wave to the smallest terminal voltage among the Error Amplifier
output voltage (Error Amp1 to Error Amp3) . And the triangular wave voltage generated by the triangular wave
oscillator. When the triangular wave voltage is smaller than the error amplifier output voltage, the main side
output transistor is turned on and the synchronous rectification side output transistor is turned off.
19
MB39A119
■ SETTING THE CHARGE VOLTAGE
The charge voltage (DC/DC output voltage) can be set by connecting external output voltage setting resistors
(R1 and R2) to the -INE3 terminal (pin 15) . Be sure to select a resistor value that allows you to ignore the onresistance (35 Ω at 1 mA) of internal FET connected to the OUTD terminal (pin 16).
Battery charge voltage : VO
VO (V) =
R1 + R2
× − INE3 (V)
R2
B VO
R1
& lt; Error Amp3 & gt;
−INE3
−
15
+
R2
4.2 V
16
OUTD
■ SETTING THE CHARGE CURRENT
The charge current value can be set at the analog voltage value of the +INE2 terminal (pin 12) .
Charge current formula : Ichg (A) =
+ INE2 (V)
24.5 × RS1 (Ω)
Battery charge current setting voltage : + INE2
+ INE2 (V) = 24.5 × Ichg (A) × RS1 (Ω)
It is recommended that the filter should be connected to an input terminal of Current Amp2 as shown below in order
to reduce the switching noise and increase the charge current accuracy.
Ichg
RS1
10 Ω
10 Ω
0.22
µF
0.22
µF
+INC2
−INC2
20
& lt; Current Amp2 & gt;
10
11
+
× 24.5
−
MB39A119
■ SETTING THE INPUT CURRENT
The input limit current value can be set at the analog voltage value of the +INE1 terminal (pin 7) .
Input current formula : IIN (A) =
+ INE1 (V)
25 × RS2 (Ω)
Input current setting voltage : + INE1
+ INE1 (V) = 25 × IIN (A) × RS2 (Ω)
■ SETTING THE OVERCURRENT DETECTION VALUE
The overcurrent is detected when the voltage difference is more than 0.2 V (Typ) between +INE2 terminal (pin
10) voltage and -INE2 terminal (pin 11) voltage.
Charge overcurrent detection value : Iocdet (A) =
0.2 (V)
RS1 (Ω)
Charge current and overcurrent detection value by RS1 value (example)
RS1
+INE2
Ichg
OCDet
33 mΩ
0.5 V to 3.5 V
0.6 A to 4.2 A
6A
15 mΩ
0.5 V to 3.5 V
1.3 A to 9.3 A
13 A
■ SETTING THE TRIANGULAR WAVE OSCILLATION FREQUENCY
The triangular wave oscillation frequency can be set by the timing resistor (RT) connected to the RT terminal
(pin 18) .
Triangular wave oscillation frequency : fOSC
19500
fosc (kHz) =
:
RT (kΩ)
21
MB39A119
■ SETTING THE SOFT-START TIME
To prevent rush current at start-up of IC, the soft-start time can be set by connecting soft-start capacitor (CS) to
the CS terminal (pin 17) .
When the CTL terminal (pin 21) is set to “H” level and IC is started (VCC ≥ UVLO threshold voltage) , external
soft-start capacitor (CS) connected to the CS terminal (pin 17) is charged at 10 µA.
ON duty depends PWN comparator output, which compares the FB123 terminal (pin 14) voltage and the triangular wave oscillator output voltage.
During soft-start, FB123 terminal (pin14) voltage increases with sum voltage of CS terminal (pin 17) and diode
voltage. Therefore, the output voltage of the DC/DC converter and current increase can be set by output ON
duty in proportion to rise of the CS terminal (pin 17) voltage. The ON duty is affected by the ramp voltage of
FB123 terminal (pin 14) until an output voltage of one Error Amp reaches the DC/DC converter loop controlled
voltage.
Soft-start time is obtained from the following formula. :
Soft-start time : tS (time to output on duty 80 %)
ts (s) = 0.13 × CS (µF)
:
• Soft-start timing chart
CS
CT
FB123
CS
FB123
CT
0v
OUT-1
OUT-1
0v
VO
Error Amp3 threshold voltage
VO
0v
IO
0A
22
IO
MB39A119
■ TRANSIENT RESPONSE AT LOAD-STEP
The constant voltage control loop and the constant current control loop are independent. With the load-step,
these two control loops change.
The battery voltage and current overshoot are generated by the delay time of the control loop when the mode
changes. The delay time is determined by phase compensation constant. When the battery is removed if the
charge control is switched from the constant current control to the constant voltage control, and the charging
voltage does overshoot by generating the period controlled with high duty by output setting voltage. The excessive
voltage is not applied to the battery because the battery is not connected.
When the battery is connected if the charge control is switched from the constant voltage control to the constant
current control, and the charging current does overshoot by generating the period controlled with high duty by
output setting voltage.
The battery pack manufacturer in Japan thinks not the problem the current overshoot of 10ms or less.
• Operation at step-load
Error Amp3 Output
Error Amp2 Output
Constant Current
Battery Voltage
Battery Current
Error Amp2 Output
Error Amp3 Output
Constant Voltage
When charge control switches from the
constant current control to the constant
voltage control, the voltage does
overshoot by generating the period
controlled with high duty by output
setting voltage.
Constant Current
The battery pack manufacturer in
Japan thinks not the problem the
current overshoot of 10ms or
less.
23
MB39A119
■ AC ADAPTER DETECTION FUNCTION
When ACIN terminal (pin 4) voltage is lower than 2.0 V (Typ) , AC adapter voltage detection block (AC Comp.)
outputs “Hi-Z” level to the ACOK terminal (pin 5) and outputs “L” level to the XACOK terminal (pin 22) . When
CTL terminal (pin 21) is set to “L” level, ACOK terminal (pin 5) and XACOK terminal (pin 22) are fixed to
“Hi-Z” level.
(1) AC adapter presence
The presence of AC adapter can be easily detected because the signal is output from the ACOK terminal (pin
5) to microcomputer etc.
In this case, if CTL terminal (pin 21) is set in “L” level, IC become the standby state (ICC = 0 µA Typ) .
• Connection example of detecting AC adapter presence
Micon
AC adapter
ACIN
& lt; AC Comp. & gt;
+
−
24
ACOK
5
4
XACOK
22
MB39A119
(2) Automatic changing system power supply between AC adapter and battery
The AC adapter voltage is detected, and the external switch at input side and battery side is changed automatically with the connection as follows. Connect CTL terminal (pin 21) to VCC terminal (pin 1) for this function.
OFF duty cycle becomes 100 % when CS terminal (pin 17) voltage is made to be 0 V, if it is needed after full
charge.
• Connection example of automatic changing system power supply between AC adapter and battery
System
AC adapter
ACIN
ACOK
4
5
Battery
XACOK
22
& lt; AC Comp. & gt;
+
−
VCC
1
CTL
21
& lt; SOFT & gt;
VREF
10 µA
CS
17
Micon
Micon
(3) Battery selector function
When control signal from microcomputer etc. is input to ACIN terminal (pin 4) below, ACOK terminal (pin 5)
output voltage and XACOK terminal (pin 22) output voltage are controlled to select one of the two batteries for
charge. Connect CTL terminal (pin 21) to VCC terminal (pin 1) for this function. OFF duty cycle becomes 100
% when CS terminal (pin 17) voltage is made to be 0 V, if it is needed after full charge.
• Connection example of battery selector function
System
AC
adapter
4
ACIN
& lt; AC Comp. & gt;
+
−
VCC
CTL
1
21
5
ACOK
22
XACOK
A
B
Ichg
RS1
Battery1
Battery2
& lt; SOFT & gt;
VREF
10 µA
Micon
CS
17
25
MB39A119
■ PHASE COMPENSATION
Circuit example of phase compensation is shown below.
• Circuit example of phase compensation
VIN
RS2
15 mΩ
VCC
−INE3
& lt; Error Amp3 & gt;
& lt; PWM Comp. & gt;
−
+
Cc
+
−
& lt; OUT & gt;
OUT
Drive
Lo
l1
RL
VBATT
RS1
33 mΩ
4.2 V
−2.5 V
Rc
−1.5 V
FB123
Ro
Co
Rin1
ESR
Rin2
VH
(VCC-6V)
VH
Bias
Voltage
OSC
Lo : Inductance
RL : Equivalent series resistance of inductance
Co : Capacity of condenser
ESR : Equivalent series resistance of condenser
Ro : Load resistance
• Method to obtain frequency characteristic of LC filter
90
80
70
60
50
40
30
20
10
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
1
180
160
gain
phase 140
120
Gain
Phase
10
100
1k
10k
Frequency [Hz]
26
Cut-off frequency
100k
1M
100
80
60
40
20
0
−20
−40
−60
−80
−100
−120
−140
−160
−180
10M
1
f1 (Hz) =
2π
Phase [deg]
Gain [dB]
Frequency characteristic of power output LC filter
(DC gain is included.)
Lo = 15 µH
Co = 14.1 µF
Ro = 4.2 Ω
RL = 30 mΩ
ESR = 100 mΩ
Lo × Co ×
(Ro + ESR)
(Ro + RL)
MB39A119
• Method to obtain frequency characteristic of Error Amp
total gain
AMP Open
Loop Gain
total phase
Gain
Phase
1
10
100
1k
10k
100k
180
160
140
120
100
80
60
40
20
0
−20
−40
−60
−80
−100
−120
−140
−160
−180
Cut-off frequency
f2 (Hz) =
Phase [deg]
Gain [dB]
Total frequency characteristic
90
80
70
60
50
40
30
20
10
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
1
2π × Rc × Cc
Rc = 150 kΩ
Cc = 3300 pF
1M
Frequency [Hz]
• Method to obtain frequency characteristic of DC/DC converter
total gain
AMP Open Loop
Gain
total phase
Gain
Phase
1
10
100
1k
10k
100k
180
160
140
120
100
80
60
40
20
0
−20
−40
−60
−80
−100
−120
−140
−160
−180
Phase [deg]
Gain [dB]
Total frequency characteristic
90
80
70
60
50
40
30
20
10
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
1M
The overview of frequency characteristic
for DC/DC converter can be obtained in
combination between LC filter and frequency characteristic of Error Amp as
mentioned above.
Note the following point in order to stabilize frequency characteristic of DC/DC
converter.
Cut-off frequency of DC/DC converter
should be set to half or less of the triangular wave oscillator frequency.
Frequency [Hz]
Triangular wave oscillation frequency.
Note1) Review frequency characteristic of Error Amp when LC filter constant is changed.
Note2) When the ceramic capacitor is used as smoothing capacitor CO, phase margin is reduced because ESR
of the ceramic capacitor is extremely small as frequency characteristic of LC filter at low ESR.
Therefore, change phase compensation of Error Amp or create resistance equivalent to ESR using pattern.
• Method to obtain frequency characteristic of LC filter at low ESR
90
80
70
60
50
40
30
20
10
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
1
gain
phase
Gain
Phase
10
100
1k
10k
100k
1M
180
160
140
120
100
80
60
40
20
0
−20
−40
−60
−80
−100
−120
−140
−160
−180
Cut-off frequency
1
f1 (Hz) =
2π
Phase [deg]
Gain [dB]
Frequency characteristic of power output LC filter
(DC gain is included.)
Lo × Co ×
(Ro + ESR)
(Ro + RL)
Lo = 15 µH
Co = 14.1 µF
Ro = 4.2 Ω
RL = 30 mΩ
ESR = 100 mΩ
10M
Frequency [Hz]
27
MB39A119
• Additional ESR
• 3Pole2Zero
DC/DC output
−
+
28
Board Pattern
or connected
resistor
MB39A119
■ PROCESSING WITHOUT USING OF THE CURRENT AMP1 AND AMP2
When Current Amp is not used, connect +INC1 terminal (pin 3) and −INC1 terminal (pin 2) to VCC terminal (pin
1) , connect +INC2 terminal (pin 10) and −INC2 terminal (pin 11) to VREF terminal (pin 19) , and then leave
OUTC2 terminal (pin 9) open.
• Connection when Current Amp is not used
2
+INC1
3
11
−INC2
+INC2
10
1
VCC
19
“Open”
−INC1
VREF
9
OUTC2
■ PROCESSING WITHOUT USING OF THE ERROR AMP1 AND AMP2
When Error Amp1 and Amp2 are not used, connect −INE1 terminal (pin 8) and −INE2 terminal (pin 13) to GND
(pin 20) , and connect +INE1 terminal (pin 7) and +INE2 terminal (pin 12) to VREF terminal (pin 19) .
• Connection when Error Amp is not used
7
+INE1
GND
20
12 +INE2
8
−INE1
13 −INE2
19 VREF
29
MB39A119
■ PROCESSING WITHOUT USING OF THE CS TERMINAL
When soft-start function is not used, leave the CS terminal (pin 17) open.
• Connection when no soft-start time is specified
“Open”
CS
30
17
MB39A119
■ I/O EQUIVALENT CIRCUIT
• Control block
• Reference voltage block
VCC 1
CTL 21
1.25 V
+
−
132.4
kΩ
19 VREF
124.53
kΩ
ESD protection
element
41.47
kΩ
204
kΩ
ESD protection
element
GND 20
GND
• Soft-start block
• Bias voltage block
VCC
VCC
VREF
(5.0 V)
25 VB
200 kΩ
2.5 V
17 CS
200 kΩ
GND
GND
• Error amplifier block (Error Amp1)
• Triangular wave oscillator block
VCC
VCC
VREF
(5.0 V)
1.08 V
(3.1 V)
CS
+
−
−INE1 8
14 FB123
18 RT
1MΩ
GND
GND
7 +INE1
• Error amplifier block (Error Amp3)
• Error amplifier block (Error Amp2)
VCC
VCC
(3.1 V)
(3.1 V)
−INE2 13
FB123
−INE3 15
4.2 V
FB123
GND
GND
12 +INE2
(Continued)
31
MB39A119
(Continued)
• Current detection amplifier block (Current Amp1)
• Current detection amplifier block (Current Amp2)
VCC
VCC
VREF
VREF
+INC1 3
100 kΩ
+INC2 10
−INE1
9 OUTC2
80 kΩ
80 kΩ
20 kΩ
20 kΩ
GND
GND
2 −INC1
• PWM comparator
block
11 −INC2
• Output block (synchronous
rectification side)
• Output block
(Main side)
VB
28 CB
VREF
• Invalidity current
prevention block
16 OUTD
27 OUT-1
24 OUT-2
26 VS
23 PGND
FB123
CTL
GND
GND
GND
• Constant voltage control state detection
block
VREF
(5.0 V)
FB123
GND
32
GND
• AC adapter voltage detection block
VREF
(5.0 V)
6 CVM
ACIN 4
GND
5 ACOK
22 XACOK
MB39A119
■ APPLICATION EXAMPLE
R6
Q2-1 51kΩ Q2-2 RS2
System
C21
0.1µF
15mΩ
R39
16kΩ
R40
75kΩ
R15
24kΩ
Q5
ACIN
4
ACOK
5
6
22
& lt; AC Comp. & gt;
−INC1
2
0.1V & lt; UV Comp. & gt;
+
×25
−
+
−
3.1V
A
B
−INE1
8
+INE1
7
C11 6800pF
R20
R17
20kΩ
10kΩ −INE2
13
R32
100kΩ
OUTC2
9
C18 1500pF
R51
R33
10Ω
10kΩ +INC2
10
C22 0.22µF
−INC2
11
R25 R26
R52
+INE2
12
10Ω 9.1kΩ15kΩ
C23
0.22µF
14
FB123
& lt; Error Amp1 & gt;
R21
24kΩ
−
+
+
−
Drv-1
VS
R28 R27 R24
2kΩ 16kΩ 47kΩ
R18
33kΩ
C12 330pF
SW3
OFF
ON
ON
SW4
OFF
OFF
ON
lchg
4A
2A
0.4A
R10
100kΩ
OUTD
C1
4.7µF
23
C3 C4 C5
4.7µF 4.7µF 4.7µF Battery
PGND
Output voltage (Battery
voltage) is adjustable.
& lt; UVLO & gt;
& lt; Error Amp3 & gt;
−
+
15
16
VREF
UVLO
+
−
2.6V
OUTC2
+
−
0.2V
+
−
0.3V
& lt; Over Current Det. & gt;
17
VCC
UVLO
VB
UVLO
Slope
Control
4.2V
10µA
C9
0.22µF
Q1-2 D1
C2
4.7µF
H: ULVO,UV
release
& lt; SOFT & gt;
VREF
CS
VO
15Ω
OUT-2
SW4 SW3
C13 22pF
C14 22pF
R8
300kΩ
−INE3
lchg
5.2µH RS1
33mΩ
R2
24
Off time
Control
−
+
L1
Q1-1
27
26
Drv-2
B
A
C6
0.1µF
OUT-1
& lt; PWM Comp. & gt;
& lt; Error Amp2 & gt;
D4
28
−1.5 V
+
×24.5
−
C7
VB 1.0µF
25
CB
−2.5 V
& lt; Current
Amp2 & gt;
5.0V
VB Reg.
−INC2
(VO)
100kΩ
8V
~
25V
C8
0.1µF
2.6V
& lt; Current Amp1 & gt;
3
1
−
+
2.0V
+INC1
R46 56kΩ
VCC
& lt; CV Comp. & gt;
+
−
Hi Side only
R34
100kΩ
CVM
XACOK
Drive Logic
R41
16kΩ
VIN
R45
100kΩ
& lt; Sync Cnt. & gt;
VCC
+INC2
−INC2
(VO)
& lt; OSC & gt;
CT
4.2V
bias
& lt; REF & gt;
& lt; CTL & gt;
VREF
5.0V
R19
39kΩ
VREF
21 CTL
20
19
18
RT
DC/DC
ON/OFF
GND
C10
0.1µF
33
MB39A119
■ PARTS LIST
Component
M1
Q1-1, Q1-2
Q2-1, Q2-2
Q5
D1
D4
L1
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C18
C21
C22
C23
RS1
RS2
R2
R6
R8
R10
R15
R17
R18
R19
R20
R21
R24
R25
R26
R27
Item
IC
N-ch FET
P-ch FET
P-ch FET
Diode
Diode
Inductor
Ceramic condenser
Ceramic condenser
Ceramic condenser
Ceramic condenser
Ceramic condenser
Ceramic condenser
Ceramic condenser
Ceramic condenser
Ceramic condenser
Ceramic condenser
Ceramic condenser
Ceramic condenser
Ceramic condenser
Ceramic condenser
Ceramic condenser
Ceramic condenser
Ceramic condenser
Ceramic condenser
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Specification
MB39A119
VDS = − 30 V, ID = 8 A (Max)
VDS = − 30 V, ID = 8 A (Max)
VDS = − 30 V, ID = 6 A (Max)
VF = 0.35 V (Max) at IF = 0.5 A
VF = 0.4 V (Max) at IF = 0.3 A
5.2 µH, 22 mΩ, 5.5 A
4.7 µF (25 V)
4.7 µF (25 V)
4.7 µF (25 V)
4.7 µF (25 V)
4.7 µF (25 V)
0.1 µF (50 V)
1.0 µF (25 V)
0.1 µF (50 V)
0.22 µF (25 V)
0.1 µF (50 V)
6800 pF (50 V)
330 pF (50 V)
22 pF (50 V)
22 pF (50 V)
1500 pF (50 V)
0.1 µF (50 V)
0.22 µF (25 V)
0.22 µF (25 V)
33 mΩ
15 mΩ
15 Ω
51 kΩ
300 kΩ
100 kΩ
24 kΩ
10 kΩ
33 kΩ
39 kΩ
20 kΩ
24 kΩ
47 kΩ
9.1 kΩ
15 kΩ
16 kΩ
Vendor
Fujitsu
NEC
NEC
TOSHIBA
ROHM
SANYO
SUMIDA
TDK
TDK
TDK
TDK
TDK
TDK
TDK
TDK
TDK
TDK
TDK
TDK
TDK
TDK
TDK
TDK
TDK
TDK
KOA
KOA
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
Package
QFN-28P
SO-8
SO-8
SO-8
TUMD2
1197A
SMD
3216
3216
3216
3216
3216
1608
3216
1608
1608
1608
1608
1608
1608
1608
1608
1608
1608
1608
SL1
SL1
1608
1608
1608
1608
1608
1608
1608
1608
1608
1608
1608
1608
1608
1608
Parts No.
MB39A119QN-G
µPA2752
µPA1772
TPC8102
RSX051VA-30
SBS006
CDRH104R-5R2
C3216JB1E475K
C3216JB1E475K
C3216JB1E475K
C3216JB1E475K
C3216JB1E475K
C1608JB1H104K
C3216JB1E105K
C1608JB1H104K
C1608JB1E224K
C1608JB1H104K
C1608JB1H682K
C1608CH1H331J
C1608CH1H220J
C1608CH1H220J
C1608CH1H152J
C1608JB1H104K
C1608JB1E224K
C1608JB1E224K
SL1TTE33L0D
SL1TTE15L0D
RR0816P150D
RR0816P513D
RR0816P304D
RR0816P104D
RR0816P243D
RR0816P103D
RR0816P333D
RR0816P393D
RR0816P203D
RR0816P243D
RR0816P473D
RR0816P912D
RR0816P153D
RR0816P163D
(Continued)
34
MB39A119
(Continued)
Component
R28
R32
R33
R34
R39
R40
R41
R45
R46
R51
R52
Item
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Specification
2 kΩ
100 kΩ
10 kΩ
100 kΩ
16 kΩ
75 kΩ
16 kΩ
100 kΩ
56 kΩ
10 Ω
10 Ω
Vendor
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
Package
1608
1608
1608
1608
1608
1608
1608
1608
1608
1608
1608
Parts No.
RR0816P202D
RR0816P104D
RR0816P103D
RR0816P104D
RR0816P163D
RR0816P753D
RR0816P163D
RR0816P104D
RR0816P563D
RR0816P100D
RR0816P100D
Note : NEC
: NEC corporation
TOSHIBA : TOSHIBA CORPORATION
ROHM
: ROHM CO., LTD.
SUMIDA : Sumida Corporation
TDK
: TDK Corporation
KOA
: KOA Corporation
ssm
: SUSUMU CO., LTD.
SANYO : SANYO Electric Co., Ltd.
35
MB39A119
■ SELECTION OF COMPONENTS
• N-ch MOS FET
The N-ch MOS FET for switching use should be rated for at least +20% more than the input voltage. To minimize
continuity loss, use a FET with low RDS (ON) between the drain and source. For high input voltage and high
frequency operation, on-cycle switching loss will be higher so that power dissipation must be considered. In this
application, the NEC µPA2752 is used. Continuity loss, on/off switching loss and total loss are determined by
the following formulas. The selection must ensure that peak drain current does not exceed rated values.
Continuity loss : Pc
PC = ID2 × RDS (ON) × Duty
On-cycle switching loss : PS (ON)
PS (ON) =
VD (Max) × ID × tr × fosc
6
Off-cycle switching loss : PS (OFF)
PS (OFF) =
VD (Max) × ID (Max) × tf × fosc
6
Total loss : PT
PT = PC + PS (ON) + PS (OFF)
• Inductor
In selecting inductors, it is of course essential not to apply more current than the rated capacity of the inductor,
but also to note that the lower limit for ripple current is a critical point that if reached will cause discontinuous
operation and a considerable drop in efficiency. This can be prevented by choosing a higher inductance value,
which will enable continuous operation under light loads. Note that if the inductance value is too high, however,
direct current resistance (DCR) is increased and this will also reduce efficiency. The inductance must be set at
the point where efficiency is greatest.
Note also that the DC superimposition characteristics become worse as the load current value approaches the
rated current value of the inductor, so that the inductance value is reduced and ripple current increases, causing
loss of efficiency. The selection of rated current value and inductance value will vary depending on where the
point of peak efficiency lies with respect to load current. Inductance values are determined by the following
formulas.
The L value for all load current conditions is set so that the peak to peak value of the ripple current is 1/2 the
load current or less.
36
MB39A119
16.8 V output
VIN = 24 V (Max) , VO = 16.8 V, IO = 4.0 A, fosc = 500 kHz
1. N-ch MOS FET (µPA2752 : NEC product)
Main side
VDS = 30 V, VGS = ± 20 V, ID = 8 A, RDS (ON) = 25 mΩ (Typ) , Qg = 10 nC (Typ)
Synchronous rectification side
VDS = 30 V, VGS = ± 20 V, ID = 8 A, RDS (ON) = 25 mΩ (Typ) , Qg = 10 nC (Typ)
Drain current : Peak value
The peak drain current of this FET must be within its rated current.
If the FET’s peak drain current is ID, it is obtained by the following formula.
Main side
VIN−Vo
ID ≥ Io +
tON
2L
24−16.8
≥ 4.0 +
2 × 5.2 × 10
×
−6
1
×
500 × 103
0.7
≥ 4.97 A
Synchronous rectification side
Vo
ID ≥ Io +
tOFF
2L
16.8
≥ 4.0 +
2 × 5.2 × 10−6
1
×
500 × 103
×
(1 − 0.7)
≥ 4.97 A
2. Inductor (CDRH104R-5R2 : SUMIDA product)
5.2 µH (tolerance ± 30%) , rated current = 5.5 A
L≥
≥
2 (VIN−Vo)
Io
tON
2 × (24−16.8)
4.0
×
1
500 × 103
×
0.7
≥ 5.04 µH
37
MB39A119
The load current satisfying the continuous current condition
Vo
Io ≥
≥
tOFF
2L
16.8
2 × 5.2 × 10
−6
×
1
×
500 × 10−3
(1−0.7)
≥ 0.97 A
Ripple current : Peak value
The peak ripple current must be within the rated current of the inductor.
If the peak ripple current is IL, it is obtained by the following formula.
VIN−Vo
tON
IL ≥ IO
2L
≥ 4.0 +
24−16.8
2 × 5.2 × 10−6
×
1
500 × 103
×
0.7
≥ 4.97 A
Ripple current : peak-to-peak value
If the peak-to-peak ripple current is ∆IL, it is obtained by the following formula.
VIN−Vo
∆IL =
tON
L
=
24−16.8
5.2 × 10
= 1.94 A
:
38
−6
×
1
500 × 103
×
0.7
MB39A119
12.6 V output
VIN = 20 V (Max) , VO = 12.6 V, IO = 4.0 A, fosc = 500 kHz
1. N-ch MOS FET (µPA2752 : NEC product)
Main side
VDS = 30 V, VGS = ± 20 V, ID = 8 A, RDS (ON) = 25 mΩ (Typ) , Qg = 10 nC (Typ)
Synchronous rectification side
VDS = 30 V, VGS = ± 20 V, ID = 8 A, RDS (ON) = 25 mΩ (Typ) , Qg = 10 nC (Typ)
Drain current : Peak value
The peak drain current of this FET must be within its rated current.
If the FET’s peak drain current is ID, it is obtained by the following formula.
Main side
ID ≥ Io +
VIN−Vo
2L
tON
20−12.6
≥ 4.0 +
2 × 5.2 × 10
×
−6
1
500 × 103
× 0.63
≥ 4.90 A
Synchronous rectification side
ID ≥ Io +
≥ 4.0 +
≥
Vo
2L
tOFF
12.6
2 × 5.2 × 10−6
×
1
500 × 103
×
(1 − 0.63)
4.90 A
39
MB39A119
2. Inductor (CDRH104R-5R2 : SUMIDA product)
5.2 µH (tolerance ± 30%) , rated current = 5.5 A
2 (VIN−Vo)
L≥
tON
Io
2 × (24−12.6)
≥
×
4.0
1
500 × 103
× 0.63
≥ 4.67 µH
The load current satisfying the continuous current condition
Vo
Io ≥
2L
12.6
≥
×
2 × 5.2 × 10
−6
≥
IL ≥
tOFF
1
500 × 103
×
(1−0.63)
897.0 mA
VIN−Vo
IO
tON
2L
≥ 4.0 +
20−12.6
2 × 5.2 × 10−6
×
1
500 × 103
× 0.63
≥ 4.90 A
Ripple current : Peak-to-peak value
If the peak-to-peak ripple current is ∆IL, it is obtained by the following formula.
VIN−Vo
tON
∆IL =
L
=
20−12.6
5.2 × −6
×
1
500 × 103
× 0.63
= 1.79 A
:
3. Diode for bootstrap (SBS006 : SANYO product)
VR (DC reverse voltage) = 30 V, Average output current = 500 mA, peak surge current = 10 A
VF (forward voltage) = 0.35 V, at IF = 300 mA
VR : value that satisfies input voltage
Efficiency is somewhat rising in low leak Schottky diode by the use but even if the signal diode is used, it
is enough. It is recommended to use low VF. Also, capacitor for bootstrap must be very large than gate
capacity of FET at main side. It is recommended to use the capacity of approximately 0.1 µF to 1.0 µF.
40
MB39A119
4. Charging current setting sense resistor (SL1TTE33L0F : KOA product)
33 mΩ
When + INE2 terminal (pin 12) voltage is 3.3 V, and the charging current (IO) is 4.0 A, R4 is obtained by the
following formula.
+ INE2
R4 =
24.5 × IO
=
=
:
3.3
24.5 × 4.0
33.0 mΩ
5. Input current setting sense resistor (SL1TTE15L0F : KOA product)
15 mΩ
When + INE1 terminal (pin 7) voltage is 2.25 V, and the input current is 6.0 A, R1 is obtained by the following
formula.
+ INE1
R1 =
25 × I1
=
2.25
25 × 6.0
= 15.0 mΩ
:
6. Switching P-ch FET (µPA1772 : NEC product, TPC8102 : TOSHIBA product)
Q2-1, Q2-2, and Q5 must select an appropriate device according to the input current.
41
MB39A119
■ REFERENCE DATA
Conversion efficiency vs. Charging current (constant voltage mode)
Conversion efficiency η (%)
100
95
VIN = 19 V
VO = 16.8 V setting
90
85
80
75
70
65
60
55
50
0.01
0.1
1
10
Charging current IO (A)
Conversion efficiency η (%)
Conversion efficiency vs. Charging current (constant voltage mode)
100
95
90
VIN = 16 V
VO = 12.6 V setting
85
80
75
70
65
60
55
50
0.01
0.1
1
10
Charging current IO (A)
Conversion efficiency vs. Charging voltage (constant current mode)
Conversion efficiency η (%)
100
95
90
VIN = 19 V
IO = 4 A setting
85
80
75
70
65
60
55
50
0
2
4
6
8
10
12
14
16
18
20
Charging voltage VO (V)
(Continued)
42
MB39A119
Conversion efficiency vs. Charging voltage (constant current mode)
Conversion efficiency η (%)
100
95
90
VIN = 16 V
IO = 4 A setting
85
80
75
70
65
60
55
50
0
2
4
6
8
10
12
14
16
18
20
Charging voltage VO (V)
Charging voltage vs. Charging current
Charging voltage VO (V)
18
16
VIN = 19 V
VO = 16.8 V setting
14
12
SW3 = ON
SW4 = ON
10
SW3 = ON
SW4 = OFF
SW3 = OFF
SW4 = OFF
8
6
4
2
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Charging current IO (A)
Charging voltage vs. Charging current
Charging voltage VO (V)
18
VIN = 16 V
VO = 12.6 V setting
16
14
12
SW3 = ON
SW4 = ON
10
SW3 = ON
SW4 = OFF
SW3 = OFF
SW4 = OFF
8
6
4
2
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Charging current IO (A)
(Continued)
43
MB39A119
Switching waveform (constant voltage mode)
OUT-1 (V)
OUT-1
20
15
10
5
VIN = 19 V
VO = 16.8 V setting
IO = 2 A
SW3 = OFF
SW4 = OFF
0
OUT-2 (V)
5
OUT-2
0
−5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0(µs)
Switching waveform (constant current mode)
OUT-1 (V)
OUT-1
20
15
10
5
VIN = 19 V
VO = 12 V
IO = 4 A setting
SW3 = OFF
SW4 = OFF
0
OUT-2 (V)
5
OUT-2
0
−5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0(µs)
Switching waveform (constant voltage mode)
VS
(V)
20
VS
15
10
5
VIN = 19 V
VO = 16.8 V setting
IO = 2.0 A
SW3 = OFF
SW4 = OFF
0
−5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0(µs)
(Continued)
44
MB39A119
Switching waveform (constant current mode)
VS
(V)
VIN = 19 V
VO = 12 V
IO = 4.0 A setting
SW3 = OFF
SW4 = OFF
20
VS
15
10
5
0
−5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0(µs)
Oscillation frequency vs. Charging current
Oscillation frequency fOSC (kHz)
600
550
OUT-1
500
450
VIN = 19 V
VO = 16.8 V setting
400
350
OUT-2
300
250
200
150
100
50
0
0.000
1.000
2.000
3.000
4.000
5.000
Charging current IO (A)
Oscillation frequency charging voltage vs. Input voltage
24.0
fosc
550
22.0
20.0
500
VO
450
18.0
400
16.0
350
14.0
300
12.0
250
VO = 16.8 V setting
RL = 10 Ω
200
10.0
8.0
150
6.0
100
4.0
50
Charging voltage VO (V)
Oscillation frequency fOSC (kHz)
600
2.0
0
17
18
19
20
21
22
23
24
0.0
25
Input voltage VIN (V)
(Continued)
45
MB39A119
Soft-start operating waveform (constant current mode)
Vo (V)
18
Io (A)
5
Vo
16
14
4
CVM (V)
5
CVM
3
2
0
VIN = 19 V
IO = 4 A setting
SW3 = OFF
SW4 = OFF
1
Io
CTL (V)
10
0
CTL
4
0
0
8
12
16
20
24
28
32
36
40 (ms)
Soft-start operating waveform (constant current mode)
Vo (V)
18
Vo
Io (A)
5
16
VIN = 19 V
IO = 4 A setting
SW3 = OFF
SW4 = OFF
Io
4
14
CVM (V)
5
3
CVM
2
0
1
CTL (V)
0
10
CTL
0
0
4
8
12
16
20
24
28
32
36
40 (ms)
(Continued)
46
MB39A119
Soft-start operating waveform (constant voltage mode)
Vo (V)
18
Vo
Io (A)
5
16
14
CVM (V)
5
4
CVM
3
2
0
VIN = 19 V
VO = 16.8 V setting
SW3 = OFF
SW4 = OFF
1
CTL (V)
Io
10
0
CTL
0
4
0
8
12
16
20
24
28
32
36
40 (ms)
Soft-start operating waveform (constant voltage mode)
Vo (V)
18
Vo
Io (A)
5
16
VIN = 19 V
VO = 16.8 V setting
SW3 = OFF
SW4 = OFF
4
3
14
CVM (V)
5
CVM
0
2
Io
1
0
CTL (V)
10
CTL
0
0
4
8
12
16
20
24
28
32
36
40 (ms)
(Continued)
47
MB39A119
Load-step response operation waveform (C.V mode→C.C mode)
6
Vo
(V)
18
5
16
Io (A)
Vo
14
4
3
VIN = 19 V
IO = 4 A setting
SW3 = OFF
SW4 = OFF
2
1
Io
0
0
2
4
6
8
10
12
14
16
18
20 (ms)
Load-step response operation waveform (C.C mode→C.V mode)
Vo
(V)
18
Io (A)
Vo
6
16
5
Io
14
4
3
VIN = 19 V
IO = 4 A setting
SW3 = OFF
SW4 = OFF
2
1
0
0
2
4
6
8
10
12
14
16
18
20 (ms)
(Continued)
48
MB39A119
(Continued)
Load-step response operation waveform (C.V mode→C.V mode)
Vo
(V)
18
Io (A)
Vo
6
16
5
VIN = 19 V
VO = 16.8 V setting
SW3 = OFF
SW4 = OFF
4
14
3
2
1
Io
0
0
2
4
6
8
10
12
14
16
18
20 (ms)
Load-step response operation waveform (C.V mode→C.V mode)
Vo
(V)
18
Io (A)
Vo
6
16
5
14
4
3
VIN = 19 V
VO = 16.8V setting
SW3 = OFF
SW4 = OFF
2
Io
1
0
0
2
4
6
8
10
12
14
16
18
20 (ms)
49
MB39A119
■ LOOP CHARACTERISTICS
& lt; Voltage mode & gt;
VIN = 19 V
Setting VO = 16.8 V
VO = 16.8 V (C.V mode)
RL = 10
1.E+02
1.E+03
1.E+04
1.E+05
200
180
160
140
120
100
80
60
40
20
0
20
40
60
80
100
120
140
160
180
200
1.E+06
Phase (deg)
50
45
40
35
30
25
20
15
10
5
0
5
10
15
20
25
30
35
40
45
50
1.E+01
200
180
160
140
120
100
80
60
40
20
0
20
40
60
80
100
120
140
160
180
200
1.E+06
Phase (deg)
Gain (dB)
Gain, phase vs. Frequency
Frequency (Hz)
& lt; Current mode & gt;
Gain (dB)
Gain, phase vs. Frequency
50
45
40
35
30
25
20
15
10
5
0
5
10
15
20
25
30
35
40
45
50
1.E+01
VIN = 16 V
Setting VO = 8.4 V
VO = 6 V (C.C mode)
RL = 1.5
1.E+02
1.E+03
1.E+04
Frequency (Hz)
50
1.E+05
MB39A119
■ USAGE PRECAUTIONS
• Printed circuit board ground lines should be set up with consideration for common impedance.
• Take appropriate static electricity measures.
• Containers for semiconductor materials should have anti-static protection or be made of conductive material.
• After mounting, printed circuit boards should be stored and shipped in conductive bags or containers.
• Work platforms, tools, and instruments should be properly grounded.
• Working personnel should be grounded with resistance of 250 kΩ to 1 MΩ between body and ground.
• Do not apply negative voltages.
• The use of negative voltages below −0.3 V may create parasitic transistors on LSI lines, which can cause
abnormal operation.
■ ORDERING INFORMATION
Part number
MB39A119QN
Package
Remarks
28-pin plastic QFN
(LCC-28P-M10)
51
MB39A119
■ PACKAGE DIMENSION
28-pin plastic QFN
(LCC-28P-M10)
3.50±0.10
(.138±.004)
5.00±0.10
(.197±.004)
5.00±0.10
(.197±.004)
INDEX AREA
3.50±0.10
(.138±.004)
0.25±0.10
(.010±.004)
0.40±0.10
(.016±.004)
0.50(.020)
TYP
1PIN CORNER
(C0.30(C.012))
0.08(.003)
0.02
.0008
C
+0.05
–0.02
+.002
–.0008
1.00(.039)
MAX
0.20(.008)
2004 FUJITSU LIMITED C28067Sc-2-1
Dimensions in mm (inches) .
Note : The values in parentheses are reference values.
52
MB39A119
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information, such as descriptions of function and application
circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of
Fujitsu semiconductor device; Fujitsu does not warrant proper
operation of the device with respect to use based on such
information. When you develop equipment incorporating the
device based on such information, you must assume any
responsibility arising out of such use of the information. Fujitsu
assumes no liability for any damages whatsoever arising out of
the use of the information.
Any information in this document, including descriptions of
function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as
patent right or copyright, or any other right of Fujitsu or any third
party or does Fujitsu warrant non-infringement of any third-party’s
intellectual property right or other right by using such information.
Fujitsu assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result
from the use of information contained herein.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
Edited
Business Promotion Dept.
F0604