Chyba problem w LP8550 LED Backlight Driver - sam z siebie U7701 (zobacz zasilanie + LDO) - pady pod nim - syg,EN.>> na Q7706 > jego zaś otwiera go Q7707> ten zaś potrzebuje do otwarcia dwa syg. 1. BKLT_PLT_RST_L (tworzy go logika "I" /U2071) i 2. EDP_BKLT_EN (z procesora) * brak jednego Q7706 zamkniety * na próbę > pinceta i zewrzyj 2 z 5 Q7707. - przemyj_przeczyść złącza (czasem pomaga) (':D') * Driver IC U7701 LP8550 (mark as D68b) LCD Backlight Driver for Macbook Air 13" A1466 2013 820-3437-A/B Coś było na tym forum i np. Link_Elvikom Masz w zał. SM , pomierz i myśl ? Może pomocne Link_ * w pole Search (prawa _góra, przed pomarańcz. _go) wpisz frazę : LP8550 http://obrazki.elektroda.pl/1927499200_1479329581_thumb.jpg
8
7
6
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
5
4
3
2
1
REV
ECN
& lt; REV & gt;
& lt; ECN & gt;
DESCRIPTION OF REVISION
CK
APPD
DATE
J43 MLB SCHEMATIC DVT
REV 6.5.0
& lt; ECO_DESCRIPTION & gt;
& lt; ECODATE & gt;
4/09/13
D
(.csa)
Date
Page
TABLE_TABLEOFCONTENTS_HEAD
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
C
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
B
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
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Contents
Sync
(.csa)
MASTER
TABLE_TABLEOFCONTENTS_ITEM
11/16/2010
TABLE_TABLEOFCONTENTS_ITEM
MASTER
TABLE_TABLEOFCONTENTS_ITEM
02/06/2013
TABLE_TABLEOFCONTENTS_ITEM
04/02/2013
TABLE_TABLEOFCONTENTS_ITEM
02/06/2013
TABLE_TABLEOFCONTENTS_ITEM
04/09/2013
TABLE_TABLEOFCONTENTS_ITEM
02/06/2013
TABLE_TABLEOFCONTENTS_ITEM
01/08/2013
TABLE_TABLEOFCONTENTS_ITEM
02/07/2013
Table of Contents
TABLE_TABLEOFCONTENTS_HEAD
04/09/2013
1
TABLE_TABLEOFCONTENTS_ITEM
MASTER
2
BOM Configuration
J41_MLB
3
BOM Variants
K21_MLB
PD PARTS
MASTER
4
5
CPU GFX/NCTF/RSVD
J41_MLB
6
CPU Misc/JTAG/CFG/RSVD
J41_MLB
7
CPU DDR3/LPDDR3 Interfaces
J41_MLB
8
CPU/PCH POWER
J41_MLB
9
CPU/PCH GROUNDS
J41_MLB
10
CPU Decoupling
WILL_J43
PCH Decoupling
J41_MLB
12
02/06/2013
TABLE_TABLEOFCONTENTS_ITEM
04/02/2013
TABLE_TABLEOFCONTENTS_ITEM
02/06/2013
TABLE_TABLEOFCONTENTS_ITEM
02/06/2013
TABLE_TABLEOFCONTENTS_ITEM
02/15/2013
TABLE_TABLEOFCONTENTS_ITEM
J41_MLB
14
PCH PM/PCI/GFX
TABLE_TABLEOFCONTENTS_ITEM
02/06/2013
PCH Audio/JTAG/SATA/CLK
TABLE_TABLEOFCONTENTS_ITEM
02/06/2013
13
J41_MLB
15
PCH PCIe/USB/LPC/SPI/SMBus
J41_MLB
16
PCH GPIO/MISC/LPIO
J41_MLB
18
CPU/PCH Merged XDP
J41_MLB
19
Chipset Support
J41_MLB
Project Chipset Support
J41_MLB
DDR3 VREF MARGINING
J41_MLB
20
02/12/2013
02/06/2013
02/06/2013
TABLE_TABLEOFCONTENTS_ITEM
02/06/2013
TABLE_TABLEOFCONTENTS_ITEM
J41_MLB
26
LPDDR3 DRAM Channel B (32-63)
TABLE_TABLEOFCONTENTS_ITEM
J41_MLB
25
LPDDR3 DRAM Channel B (0-31)
TABLE_TABLEOFCONTENTS_ITEM
J41_MLB
24
LPDDR3 DRAM Channel A (32-63)
TABLE_TABLEOFCONTENTS_ITEM
02/06/2013
LPDDR3 DRAM Channel A (0-31)
TABLE_TABLEOFCONTENTS_ITEM
02/06/2013
23
TABLE_TABLEOFCONTENTS_ITEM
02/06/2013
22
J41_MLB
27
LPDDR3 DRAM Termination
J41_MLB
Thunderbolt Host (1 of 2)
J41_MLB
28
02/06/2013
TABLE_TABLEOFCONTENTS_ITEM
02/06/2013
TABLE_TABLEOFCONTENTS_ITEM
04/09/2013
TABLE_TABLEOFCONTENTS_ITEM
04/02/2013
TABLE_TABLEOFCONTENTS_ITEM
03/20/2013
J41_MLB
32
Thunderbolt Connector A
J41_MLB
35
Wireless Connector
J41_MLB
37
SSD Connector
J41_MLB
39
Camera 1 of 2
J41_MLB
Camera 2 of 2
CPU VR12.6 VCC Regulator IC
J41_MLB
CPU VR12.5 VCC Power Stage
J41_MLB
LPDDR3 Supply
J41_MLB
5V S4RS3 / 3.3V S5 Power Supply
J41_MLB
1.05V S0 Power Supply
J41_MLB
LCD/KBD Backlight Driver
J41_MLB
Misc Power Supplies
J41_MLB
Power FETs
J41_MLB
Power Control
J41_MLB
Internal DisplayPort Connector
J41_MLB
Left I/O (LIO) Connector
CLEAN_J43
02/09/2013
04/09/2013
73
04/09/2013
74
02/09/2013
75
09/17/2012
76
03/28/2013
77
02/06/2013
78
02/06/2013
80
02/06/2013
81
02/06/2013
83
02/06/2013
95
11/13/2012
100
C
01/30/2013
Power Aliases
J41_MLB
Signal Aliases
J41_MLB
Func Test / No Test
J41_MLB
Project FCT/NC/Aliases
J41_MLB
PCB Rule Definitions
CONSTRAINTS
CPU Constraints
CONSTRAINTS
PCH Constraints 1
CLEAN_J43
102
08/30/2012
104
02/01/2013
105
09/13/2012
110
10/24/2012
111
09/25/2012
112
11/13/2012
113
12/14/2012
PCH Constraints 2
J41_MLB
Memory Constraints
CONSTRAINTS
Thunderbolt Constraints
CONSTRAINTS
Camera Constraints
J41_MLB
SMC Constraints
CONSTRAINTS
Project Specific Constraints
J41_MLB
Project Specific Constraints
CONSTRAINTS
Reference
J41_MLB
114
09/25/2012
115
09/25/2012
116
01/30/2013
117
09/25/2012
118
12/07/2012
119
09/25/2012
121
07/03/2012
J41_MLB
Fan
J41_MLB
72
J41_MLB
Thermal Sensors
PBus Supply & Battery Charger
02/06/2013
J41_MLB
Debug Sensors 1
J41_MLB
71
J41_MLB
Voltage & Load Side Current Sensing
MASTER
J41_MLB
High Side Current Sensing
Battery Connector
DC-In & G3H Supply
70
J41_MLB
SMBus Connections
02/06/2013
MASTER
J41_MLB
SMC Project Support
J41_MLB
J41_MLB
SMC Shared Support
Audio: Speaker Amp
69
J41_MLB
SMC
J41_MLB
J41_MLB
IPD Connector
04/02/2013
LPC+SPI Debug Connector
64
MASTER
External A USB3 Connector
61
MASTER
SD CONTROLLER (GL3219)
Sync
J41_MLB
SD READER CONNECTOR
Contents
TABLE_TABLEOFCONTENTS_ITEM
J41_MLB
30
TBT Power Support
TABLE_TABLEOFCONTENTS_ITEM
02/07/2013
Thunderbolt Host (2 of 2)
TABLE_TABLEOFCONTENTS_ITEM
02/06/2013
29
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
D
Date
Page
J41_MLB
40
44
07/01/2011
45
10/11/2010
46
B
02/07/2013
48
02/12/2013
50
02/06/2013
51
02/06/2013
52
02/06/2013
53
02/06/2013
54
03/28/2013
55
03/28/2013
56
03/28/2013
58
02/06/2013
60
02/06/2013
TABLE_TABLEOFCONTENTS_ITEM
ALIASES RESOLVED
A
Schematic / PCB #’s
PART NUMBER
DESCRIPTION
REFERENCE DES
CRITICAL
051-9800
QTY
1
SCHEM,MLB,J43
SCH
1
PCBF,MLB,J43
PCB
CRITICAL
TITLE=MLB
9 20:06:04 2013
7
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
R
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
ABBREV=DRAWING
8
DRAWING NUMBER
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
DRAWING
LAST_MODIFIED=Tue Apr
& lt; PART_DESCRIPTION & gt;
PRODUCT SAFETY REQUIREMENTS:
PCB, UL RECOGNIZED, MIN. 130-C TEMP. RATING AND V-0 FLAME RATING PER UL 796 & UL 94.
PCB TO BE SILK-SCREENED WITH UL/CUL RECOGNITION MARK, MANUFACTURER’S UL FILE
NUMBER, UL PCB MATERIAL DESIGNATION, 130-C TEMP. RATING AND V-0 FLAME RATING.
CRITICAL
820-3437
BOM OPTION
A
DRAWING TITLE
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
1 OF 121
SHEET
1 OF 76
1
8
7
6
5
4
3
BOM Groups
1
Alternate Parts
TABLE_BOMGROUP_HEAD
BOM GROUP
2
BOM OPTIONS
TABLE_ALT_HEAD
PART NUMBER
ALTERNATE FOR
PART NUMBER
REF DES
COMMENTS:
376S1032
376S0855
ALL
Toshiba alt for Diodes dual
376S1129
376S0855
ALL
NXP alt for Diodes dual
376S1089
376S1128
ALL
NXP alt for Diodes single
138S0684
138S0660
ALL
Murata alt to Taiyo Yuden
138S0703
138S0648
ALL
Murata alt to Taiyo Yuden
152S0586
152S1301
ALL
Dale/Vishay alt to Cyntec
372S0186
372S0185
ALL
NXP alt to Diodes
197S0479
197S0478
ALL
200uW Epson alt to NDK
376S1053
376S0604
ALL
Diodes alt to Fairchild
371S0713
371S0558
ALL
Diodes alt to ST Micro
128S0371
128S0376
ALL
Kemet alt to Sanyo
128S0394
128S0415
ALL
NEC alt to Sanyo
152S1821
152S1757
ALL
Cyntec alt to NEC
197S0480
197S0343
ALL
NDK crystal alt to TXC
197S0481
197S0343
ALL
Epson crystal alt to TXC
107S0254
107S0241
ALL
Cyntec sense R alt to TFT
353S3452
353S1286
ALL
Maxim alt to Microchip
128S0386
128S0284
ALL
Kemet alt to Sanyo
128S0397
128S0325
ALL
Kemet alt to Sanyo
377S0155
377S0104
ALL
OnSemi alt to Infineon
128S0398
128S0220
ALL
Kemet alt to Sanyo
197S0542
197S0544
ALL
NDK alt to TXC
197S0545
197S0544
ALL
Epson alt to TXC
138S0681
138S0638
ALL
Taiyo alt to Samsung
138S0841
138S0638
ALL
Murata alt to Samsung
376S1180
376S0761
ALL
Renesas alt to Vishay
152S1876
152S1804
ALL
TDK alt to Toko
107S0255
107S0240
ALL
Cyntec alt to TFT
107S0250
107S0248
ALL
Cyntec alt to TFT
TABLE_BOMGROUP_ITEM
MLB_COMMON
ALTERNATE,COMMON,MLB_MISC,MLB_DEBUG:ENG,MLB_PROGPARTS
MLB_MISC
MLB_DEVEL:ENG
PP5V5_DCIN:NO,TBTHV:P15V,EDP,CAM_XTAL:NO,CAM_WAKE:NO,APCLKRQ:ISOL,TPAD_INTWAKE:SHARED,USB_PWR:S3,SD_ON_MLB,VCORE_FETS
BOM OPTION
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
ALTERNATE,BKLT:ENG,XDP_CONN,DDRVREF_DAC,S0PGOOD_ISL,DBGLED,ISNS:ENG
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
MLB_DEVEL:PVT
XDP_CONN
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
MLB_DEBUG:ENG
DEVEL_BOM,XDP,LPCPLUS
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
MLB_DEBUG:PVT
D
DEVEL_BOM,BKLT:PROD,XDP,LPCPLUS,ISNS:PROD
D
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
MLB_DEBUG:PROD
BKLT:PROD,LPCPLUS,XDP,ISNS:PROD
TABLE_ALT_ITEM
TABLE_ALT_ITEM
Current Sensor Configuration
CPU DRAM CFG Chart
TABLE_BOMGROUP_HEAD
BOM GROUP
BOM OPTIONS
ISNS:ENG
CPU_HS_ISNS:YES,CPUVR_ISNS:YES,DRAM_ISNS:YES,P1V05_ISNS:YES,AIRPORT_ISNS:YES,SSD_ISNS:YES,LCDBKLT_ISNS:YES,P3V3S5_ISNS:YES,3V3S0_ISNS:YES,OTHER_HS_ISNS:YES,CAM_ISNS:YES,CPUDDR_ISNS:YES,PANEL_ISNS:YES
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
VENDOR
CFG 1
CFG 0
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
ISNS:PROD
HYNIX
CPU_HS_ISNS:YES,CPUVR_ISNS:YES,DRAM_ISNS:YES,P1V05_ISNS:NO,AIRPORT_ISNS:NO,SSD_ISNS:YES,LCDBKLT_ISNS:NO,P3V3S5_ISNS:NO,3V3S0_ISNS:NO,OTHER_HS_ISNS:NO,CAM_ISNS:NO,CPUDDR_ISNS:NO,PANEL_ISNS:NO
0
0
TABLE_ALT_ITEM
SAMSUNG
1
0
MICRON
0
1
ELPIDA
1
1
TABLE_ALT_ITEM
CPU DRAM SPD Straps
TABLE_ALT_ITEM
TABLE_BOMGROUP_HEAD
BOM GROUP
BOM OPTIONS
DDR3:HYNIX_4GB
RAMCFG0:L,RAMCFG1:L,RAMCFG2:L,RAMCFG3:L,DRAM_TYPE:HYNIX_4GB
DDR3:HYNIX_8GB
RAMCFG0:L,RAMCFG1:L,RAMCFG2:H,RAMCFG3:L,DRAM_TYPE:HYNIX_8GB
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
SIZE
CFG 2
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
RAMCFG0:H,RAMCFG1:H,RAMCFG2:H,RAMCFG3:L,DRAM_TYPE:ELPIDA_8GB
DDR3:MICRON_4GB
1
RAMCFG0:H,RAMCFG1:H,RAMCFG2:L,RAMCFG3:L,DRAM_TYPE:ELPIDA_4GB
DDR3:ELPIDA_8GB
8GB
RAMCFG0:L,RAMCFG1:H,RAMCFG2:H,RAMCFG3:L,DRAM_TYPE:SAMSUNG_8GB
DDR3:ELPIDA_4GB
0
RAMCFG0:L,RAMCFG1:H,RAMCFG2:L,RAMCFG3:L,DRAM_TYPE:SAMSUNG_4GB
DDR3:SAMSUNG_8GB
4GB
TABLE_BOMGROUP_ITEM
DDR3:SAMSUNG_4GB
RAMCFG0:H,RAMCFG1:L,RAMCFG2:L,RAMCFG3:L,DRAM_TYPE:MICRON_4GB
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
TABLE_ALT_ITEM
DIE REV
TABLE_BOMGROUP_ITEM
CFG 3
TABLE_ALT_ITEM
A
0
B
TABLE_BOMGROUP_ITEM
1
TABLE_ALT_ITEM
TABLE_ALT_ITEM
C
Programmable Parts
PART NUMBER
QTY
C
TABLE_ALT_ITEM
DESCRIPTION
REFERENCE DES
CRITICAL
BOM OPTION
TABLE_ALT_ITEM
335S0865
1
EEPROM,256KBIT,SPI,5MHZ,1.8V,2X3QFN
U2890
CRITICAL
TBTROM:BLANK
341S3802
1
IC,EEPROM,C/R (V23.4) EVT,J41/J41
U2890
CRITICAL
TBTROM:PROG
338S1159
1
IC,SMC12-A3,40MHZ/50DMIPS MCU,9X9,157BGA
U5000
CRITICAL
SMC:BLANK
335S0809
1
64 MBIT SPI SERIAL DUAL I/O FLASH,8X6X0.8
U6100
CRITICAL
BOOTROM_MAC:BLANK
335S0803
1
64 MBIT SPI SERIAL DUAL I/O FLASH,8X6X0.8
U6100
CRITICAL
BOOTROM_NUM:BLANK
341S3809
1
IC,EFI ROM (V0071) DVT,J41/J43
U6100
CRITICAL
BOOTROM:PROG
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
Module Parts
PART NUMBER
QTY
REFERENCE DES
CRITICAL
337S4525
1
HSW,SR16M,PRQ,C0,1.3,15W,2+3,1.0,3M,BGA
DESCRIPTION
U0500
CRITICAL
CPU:1.3GHZ
337S4526
1
HSW,SR16L,PRQ,C0,1.4,15W,2+3,1.1,3M,BGA
U0500
CRITICAL
CPU:1.4GHZ
337S4528
1
HSW,SR16H,PRQ,C0,1.7,15W,2+3,1.1,4M,BGA
U0500
CRITICAL
CPU:1.7GHZ
338S1113
1
IC,TBT,CR-4C,B1,PRQ,CIO,288,12X12 FC-CSP
U2800
CRITICAL
338S1186
IC,BCM15700A2,S2 PCIE CAMERA PROCESSOR
U3900
CRITICAL
1
ASSEMBLY,SUBASSY,PCBA,HALL EFFECT,K99
J6955
CRITICAL
946-3892
B
1
607-6811
1
J11/J13 MLB DYMAX ADHESIVE 29993-SC 0.4G
GLUE
BOM OPTION
CRITICAL
J41_MLB
B
825-7670
1
LABEL,TEXT,MLB,K21/K78
LABEL
376S0964
2
MOSFET,N-CH,25V,30A,9.6M,8P 3.3X3.3 DFN
Q7310,Q7320
CRITICAL
376S1104
2
MOSFET,N-CH,25V,30A,6.1M,8P 3.3X3.3 DFN
Q7311,Q7321
CRITICAL
VCORE_FET:REN
376S1173
2
MOSFET,N-CH,30V,15.3A,12M,8P 3.3X3.3 DFN
Q7310,Q7320
CRITICAL
VCORE_FET:VSHY
376S1174
2
MOSFET,N-CH,30V,22A,6.0M,8P 3.3X3.3 DFN
VCORE_FET:VSHY
900-0090
1
Q7311,Q7321
CRITICAL
SOLDERPASTE
CRITICAL
REFERENCE DES
CRITICAL
VCORE_FET:REN
DRAM Parts
PART NUMBER
4
IC,SDRAM,8Gb,LPDDR3-1600,178P FBGA
U2300,U2400,U2500,U2600
CRITICAL
333S0681
4
IC,SDRAM,16Gb,LPDDR3-1600,178P FBGA
U2300,U2400,U2500,U2600
CRITICAL
DRAM_TYPE:HYNIX_8GB
333S0676
4
IC,SDRAM,8Gb,LPDDR3-1600,178P FBGA
U2300,U2400,U2500,U2600
CRITICAL
DRAM_TYPE:SAMSUNG_4GB
333S0680
4
IC,SDRAM,16Gb,LPDDR3-1600,178P FBGA
U2300,U2400,U2500,U2600
CRITICAL
DRAM_TYPE:SAMSUNG_8GB
333S0678
A
QTY
333S0677
DESCRIPTION
BOM OPTION
4
IC,SDRAM,8Gb,LPDDR3-1600,178P FBGA
U2300,U2400,U2500,U2600
CRITICAL
DRAM_TYPE:ELPIDA_4GB
333S0666
4
IC,SDRAM,16Gb,LPDDR3-1600,178P FBGA
U2300,U2400,U2500,U2600
CRITICAL
DRAM_TYPE:ELPIDA_8GB
333S0679
4
IC,SDRAM,8Gb,LPDDR3-1600,178P FBGA
U2300,U2400,U2500,U2600
CRITICAL
DRAM_TYPE:MICRON_4GB
DRAM_TYPE:HYNIX_4GB
SYNC_MASTER=J41_MLB
SYNC_DATE=04/09/2013
PAGE TITLE
BOM Configuration
DRAWING NUMBER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
2 OF 121
SHEET
2 OF 76
1
A
8
7
BOM Variants
6
5
4
3
2
1
NOTE: All the " GOOD " BOM Configs have been de-activated
TABLE_BOMGROUP_HEAD
BOM NUMBER
BOM NAME
BOM OPTIONS
639-4146
PCBA,MLB,GOOD,HY-4GB,J43
MLB_CMNPTS,CPU:1.3GHZ,DDR3:HYNIX_4GB
639-4293
PCBA,MLB,GOOD,HY-8GB,J43
MLB_CMNPTS,CPU:1.3GHZ,DDR3:HYNIX_8GB
TABLE_BOMGROUP_ITEM
Alternate Parts
TABLE_BOMGROUP_ITEM
TABLE_ALT_HEAD
PART NUMBER
ALTERNATE FOR
PART NUMBER
685-0064
333S0704
TABLE_BOMGROUP_ITEM
639-4294
PCBA,MLB,GOOD,EL-4GB,J43
639-4295
PCBA,MLB,GOOD,EL-8GB,J43
PCBA,MLB,GOOD,MI-4GB,J43
PCBA,MLB,BETTER,HY-4GB,J43
PCBA,MLB,BETTER,HY-8GB,J43
685-0065
ALL
Renesas alt for Vishay
333S0700
ALL
Elpida CAM DRAM alt to Hynix
MLB_CMNPTS,CPU:1.3GHZ,DDR3:HYNIX_4GB
639-4446
COMMENTS:
MLB_CMNPTS,CPU:1.3GHZ,DDR3:MICRON_4GB
639-4445
REF DES
MLB_CMNPTS,CPU:1.3GHZ,DDR3:ELPIDA_8GB
639-4745
BOM OPTION
MLB_CMNPTS,CPU:1.3GHZ,DDR3:ELPIDA_4GB
MLB_CMNPTS,CPU:1.3GHZ,DDR3:HYNIX_8GB
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_ALT_ITEM
D
TABLE_BOMGROUP_ITEM
D
TABLE_BOMGROUP_ITEM
639-4447
PCBA,MLB,BETTER,EL-4GB,J43
MLB_CMNPTS,CPU:1.3GHZ,DDR3:ELPIDA_4GB
639-4448
PCBA,MLB,BETTER,EL-8GB,J43
MLB_CMNPTS,CPU:1.3GHZ,DDR3:ELPIDA_8GB
639-4746
PCBA,MLB,BETTER,MI-4GB,J43
MLB_CMNPTS,CPU:1.3GHZ,DDR3:MICRON_4GB
639-4755
PCBA,MLB,BEST,HY-4GB,J43
MLB_CMNPTS,CPU:1.7GHZ,DDR3:HYNIX_4GB
639-4756
PCBA,MLB,BEST,HY-8GB,J43
MLB_CMNPTS,CPU:1.7GHZ,DDR3:HYNIX_8GB
639-4757
PCBA,MLB,BEST,EL-4GB,J43
MLB_CMNPTS,CPU:1.7GHZ,DDR3:ELPIDA_4GB
639-4758
PCBA,MLB,BEST,EL-8GB,J43
MLB_CMNPTS,CPU:1.7GHZ,DDR3:ELPIDA_8GB
639-4759
PCBA,MLB,BEST,MI-4GB,J43
MLB_CMNPTS,CPU:1.7GHZ,DDR3:MICRON_4GB
685-0025
CMN PTS,PCBA,MLB,J43
MLB_COMMON
985-0018
J43 MLB DEVELOPMENT BOM
MLB_DEVEL:ENG
685-0064
VCORE FET,REN,J43
VCORE_FET:REN
685-0065
VCORE FET,VSHY,J43
VCORE_FET:VSHY
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
C
Programmable Parts
PART NUMBER
QTY
341S3758
1
C
DESCRIPTION
REFERENCE DES
CRITICAL
BOM OPTION
IC,SMC-A3 SCPL,EXT,V22.12a19,PROTO 1,J43
U5000
CRITICAL
SMC:PROG
BOM Groups
TABLE_BOMGROUP_HEAD
BOM GROUP
BOM OPTIONS
MLB_PROGPARTS
BOOTROM:PROG,SMC:PROG,TBTROM:PROG
TABLE_BOMGROUP_ITEM
B
Module Parts
PART NUMBER
QTY
338S1215
1
B
DESCRIPTION
REFERENCE DES
CRITICAL
IC,GL3219,USB3 SD CARD READER,46P,LQFN
U4500
BOM OPTION
CRITICAL
A
SYNC_MASTER=K21_MLB
SYNC_DATE=11/16/2010
PAGE TITLE
BOM Variants
Sub-BOMs
PART NUMBER
DESCRIPTION
REFERENCE DES
985-0018
QTY
1
J43 MLB DEVELOPMENT BOM
DEVEL
CRITICAL
CRITICAL
DEVEL_BOM
685-0025
1
CMN PTS,PCBA,MLB,J43
CMNPTS
CRITICAL
DRAWING NUMBER
BOM OPTION
MLB_CMNPTS
Apple Inc.
R
685-0065
1
8
VCOREFETS
VCORE FET,VSHY,J43
7
CRITICAL
NOTICE OF PROPRIETARY PROPERTY:
VCORE_FETS
6
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
3 OF 121
SHEET
3 OF 76
1
A
8
7
6
5
4
3
2
1
PD Module Parts
PART NUMBER
1
CAN,TOPSIDE,ALT,J41/J43
TBTTOPSIDE_2P_FENCE
806-5108
1
CAN,TOPSIDE,COVER,ALT,J41/J43
TBTTOPSIDE_2P_COVER
CRITICAL
806-3142
1
CAN,TBT,J11/J13
TBTFENCE
CRITICAL
806-3215
1
CAN,COVER,TBT,J11/J13
TBTCOVER
CRITICAL
806-3216
1
CAN,MDP,J11/J13
MDPCAN
CRITICAL
806-3083
1
SHLD,USB,MLB,J11/J13
USBCAN
CRITICAL
725-1792
D
QTY
806-5107
DESCRIPTION
REFERENCE DES
CRITICAL
1
INSULATOR,CPU,J41/J43
CPU_INSULATOR
BOM OPTION
CRITICAL
CRITICAL
D
Plated Board Slot
SL0400
TH-NSP
1
SL-2.3X3.9-2.9X4.5
CPU Heat Sink Mounting Bosses
Z0413
STDOFF-4.5OD1.8H-SM
Can Slots
Z0410
STDOFF-4.5OD1.8H-SM
1
SL0401
TH-NSP
1
SL-1.1X0.4-1.4X0.7
1
Z0411
Z0412
STDOFF-4.5OD1.8H-SM
STDOFF-4.5OD1.8H-SM
1
C
SL0403
TH-NSP
1
1
4x 860-1327
SL-1.1X0.4-1.4X0.7
SL0402
TH-NSP
1
SL-1.1X0.4-1.4X0.7
2x TBT pin diodes
SL0406
TH-NSP
1
SL-1.1X0.4-1.4X0.7
C
2x MDP Connector
Fan Boss
X21 Boss
SSD Boss
SL0405
TH-NSP
SL0407
TH-NSP
Z0405
Z0414
Z0415
SL-1.1X0.45-1.4X0.75
SL-1.1X0.45-1.4X0.75
STDOFF-4.5OD1.8H-SM
STDOFF-4.5OD1.9H-SM
STDOFF-4.5OD1.9H-SM
1
1
860-1327
1
1
2x TBT chip
1
860-1327
SL0404
TH-NSP
860-1327
1
SL-1.1X0.4-1.4X0.7
EMI I/O Pogo Pins
SL0408
TH-NSP
1
2x USB Connector
SL-1.1X0.4-1.4X0.7
DisplayPort PogoUSB/SD Card Pogo
CRITICAL
CRITICAL
ZS0405
ZS0406
POGO-2.0OD-3.6H-K86-K87
POGO-2.0OD-3.6H-K86-K87
SM
SM
1
1
870-1938
870-1938
B
B
A
SYNC_MASTER=MASTER
SYNC_DATE=MASTER
PAGE TITLE
PD PARTS
DRAWING NUMBER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
4 OF 121
SHEET
4 OF 76
1
A
8
7
6
5
4
3
2
1
CRITICAL
OMIT_TABLE
U0500
HASWELL-ULT
2C+GT2
BGA-TSP
SYM 1 OF 19
67 25
OUT
67 25
D
OUT
67 25
OUT
OUT
67 25
OUT
67 25
TBT Sink 0
67 25
OUT
67 25
OUT
67 25
OUT
67 25 18
67 25 18
OUT
67 25 18
OUT
67 25 18
OUT
67 25 18
OUT
67 25 18
OUT
67 25 18
OUT
67 25 18
TBT Sink 1
(MUXed with HDMI
if necessary)
OUT
OUT
DP_TBTSNK0_ML_C_N & lt; 0 & gt;
DP_TBTSNK0_ML_C_P & lt; 0 & gt;
DP_TBTSNK0_ML_C_N & lt; 1 & gt;
DP_TBTSNK0_ML_C_P & lt; 1 & gt;
DP_TBTSNK0_ML_C_N & lt; 2 & gt;
DP_TBTSNK0_ML_C_P & lt; 2 & gt;
DP_TBTSNK0_ML_C_N & lt; 3 & gt;
DP_TBTSNK0_ML_C_P & lt; 3 & gt;
C54
C55
B58
C58
B55
A55
A57
B57
DP_TBTSNK1_ML_C_N & lt; 0 & gt;
DP_TBTSNK1_ML_C_P & lt; 0 & gt;
DP_TBTSNK1_ML_C_N & lt; 1 & gt;
DP_TBTSNK1_ML_C_P & lt; 1 & gt;
DP_TBTSNK1_ML_C_N & lt; 2 & gt;
DP_TBTSNK1_ML_C_P & lt; 2 & gt;
DP_TBTSNK1_ML_C_N & lt; 3 & gt;
DP_TBTSNK1_ML_C_P & lt; 3 & gt;
C51
C50
C53
B54
C49
B50
A53
B53
DDI1_TXN0
DDI1_TXP0
DDI1_TXN1
DDI1_TXP1
DDI1_TXN2
DDI1_TXP2
DDI1_TXN3
DDI1_TXP3
DDI2_TXN0
DDI2_TXP0
DDI2_TXN1
DDI2_TXP1
DDI2_TXN2
DDI2_TXP2
DDI2_TXN3
DDI2_TXP3
eDP Port Assignment:
EDP_TXN0
EDP_TXP0
EDP_TXN1
EDP_TXP1
C45
B46
A47
B47
DP_INT_ML_C_N & lt; 0 & gt;
DP_INT_ML_C_P & lt; 0 & gt;
NC_INT_ML_CN & lt; 1 & gt;
NC_INT_ML_CP & lt; 1 & gt;
EDP_TXN2
EDP_TXP2
EDP_TXN3
EDP_TXP3
DDI
EDP
DDI Port Assignments:
C47
C46
A49
B49
NC_INT_ML_CN & lt; 2 & gt;
NC_INT_ML_CP & lt; 2 & gt;
NC_INT_ML_CN & lt; 3 & gt;
NC_INT_ML_CP & lt; 3 & gt;
EDP_AUXN
EDP_AUXP
A45
B45
DP_INT_AUXCH_C_N
DP_INT_AUXCH_C_P
EDP_RCOMP
EDP_DISP_UTIL
D20
A43
OUT
60 67
OUT
60 67
OUT
64
OUT
64
OUT
64
OUT
64
OUT
64
OUT
64
D
Internal panel
PPVCOMP_S0_CPU
8
1
R0530
MCP_EDP_RCOMP
TP_EDP_DISP_UTIL
BI
60 67
BI
60 67
24.9
1%
1/20W
MF
2 201
MCP Daisy-Chain Strategy:
CRITICAL
OMIT_TABLE
Each corner of CPU has two testpoints.
Other corner test signals connected in
daisy-chain fashion. Continuity should
exist between both TP’s on each corner.
U0500
C
HASWELL-ULT
2C+GT2
NO_TEST
5
TP 1
TP0531 TP-P6
5
5
TP 1
TP0501 TP-P6
5
5
MCP_DC_AW2_AY2
MCP_DC_AW3_AY3
MCP_DC_AY60
MCP_DC_AW61_AY61
MCP_DC_AW62_AY62
MCP_DC_B2
MCP_DC_A3_B3
MCP_DC_A61_B61
MCP_DC_B62_B63
TRUE
TRUE
MCP_DC_C1_C2
5
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
AY2
AY3
AY60
AY61
AY62
B2
B3
B61
B62
B63
C1
C2
BGA-TSP
SYM 17 OF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
19
DAISY_CHAIN_NCTF A3
DAISY_CHAIN_NCTF A4
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
DAISY_CHAIN_NCTF
C
NO_TEST
A60
A61
A62
AV1
AW1
AW2
AW3
AW61
AW62
AW63
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
MCP_DC_A3_B3
MCP_DC_A4
MCP_DC_A60
MCP_DC_A61_B61
MCP_DC_A62
MCP_DC_AV1
MCP_DC_AW1
MCP_DC_AW2_AY2
MCP_DC_AW3_AY3
MCP_DC_AW61_AY61
MCP_DC_AW62_AY62
MCP_DC_AW63
5
1 TP
TP0500
TP0510
1 TP
TP0511
TP-P6
1 TP
TP0520
TP-P6
1 TP
TP0521
TP-P6
TP-P6
1 TP
5
5
TP-P6
5
5
5
1 TP
TP-P6
TP0530
CRITICAL
OMIT_TABLE
U0500
B
B
HASWELL-ULT
2C+GT2
AT2
NC
AU44
NC
AV44
NC
D15
NC
NC
NC
NC
F22
H22
J21
BGA-TSP
SYM 18 OF 19
RSVD
SPARE
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
N23
R23
T23
U10
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
AL1
AM11
AP7
AU10
AU15
AW14
AY14
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
A
SYNC_MASTER=J41_MLB
SYNC_DATE=02/06/2013
PAGE TITLE
CPU GFX/NCTF/RSVD
DRAWING NUMBER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
5 OF 121
SHEET
5 OF 76
1
A
8
7
6
5
4
3
2
1
CRITICAL
OMIT_TABLE
U0500
D
D
HASWELL-ULT
2C+GT2
NC
67 51 38 37
CPU_PROCHOT_L
BI
R0611
2
56
OUT
CPU_CATERR_L
K61
67 38
BI
CPU_PECI
N62
PECI
CPU_PROCHOT_R_L
K63
PROCHOT*
1
5%
1/20W
MF
201
67
67
67
67
1
1
R0650
R0651
200
121
1%
1/20W
MF
201 2
1%
1/20W
MF
201 2
1
R0652
100
1%
1/20W
MF
201 2
PROC_DETECT*
67 37
62
5%
1/20W
MF
201 2
D61
1
R0620
18
OUT
C61
CPU_PWRGD
CATERR*
PROCPWRGD
CPU_SM_RCOMP & lt; 0 & gt;
CPU_SM_RCOMP & lt; 1 & gt;
CPU_SM_RCOMP & lt; 2 & gt;
AU60
AV60
AU61
AV15
SM_DRAMRST*
(IPU) PROC_TDI F63
PROC_TDO F62
10K
5%
1/20W
MF
201 2
17
OUT
CPU_MEMVTT_PWR_EN_LSVDDQ
AV61
XDP_CPU_PRDY_L
XDP_CPU_PREQ_L
OUT
16 64 67
IN
16 64 67
XDP_CPU_TCK
IN
XDP_CPU_TMS
IN
XDP_CPUPCH_TRST_L
IN
16 64 67
16 64 67
12 16 64 67
THERMAL
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
TP_CPU_MEM_RESET_L
(IPU) PRDY* J62
(IPU) PREQ* K62
(IPD) PROC_TCK E60
(IPU) PROC_TMS E61
(IPU) PROC_TRST* E59
PWR
JTAG
R06101
BGA-TSP
SYM 2 OF 19
MISC
PP1V05_S0
DDR3
55 51 42 38 27 17 16 15 11 8
64 62 59 58
SM_PG_CNTL1
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
BPM0*
BPM1*
BPM2*
BPM3*
BPM4*
BPM5*
BPM6*
BPM7*
J60
H60
H61
H62
K59
H63
K60
J61
XDP_CPU_TDI
XDP_CPU_TDO
XDP_BPM_L & lt; 0 & gt;
XDP_BPM_L & lt; 1 & gt;
XDP_BPM_L & lt; 2 & gt;
XDP_BPM_L & lt; 3 & gt;
XDP_BPM_L & lt; 4 & gt;
XDP_BPM_L & lt; 5 & gt;
XDP_BPM_L & lt; 6 & gt;
XDP_BPM_L & lt; 7 & gt;
IN
16 64 67
OUT
16 64 67
BI
16 67
BI
16 67
BI
16 67
BI
16 67
BI
16 67
BI
16 67
BI
16 67
BI
16 67
PLACE_NEAR=U0500.AU60:12.7mm
PLACE_NEAR=U0500.AV60:12.7mm
PLACE_NEAR=U0500.AU61:12.7mm
PLACE_NEAR=U0500.C61:12.7mm
C
C
CRITICAL
OMIT_TABLE
U0500
HASWELL-ULT
2C+GT2
67 16 6
67 16 6
BI
67 16
BI
67 16
BI
67 16
BI
67 16
BI
67 16
BI
16
BI
16
BI
16
BI
16
BI
AC60
AC62
AC63
AA63
AA60
Y62
Y61
Y60
V62
V61
V60
U60
T63
T62
T61
T60
CPU_CFG & lt; 16 & gt;
CPU_CFG & lt; 18 & gt;
CPU_CFG & lt; 17 & gt;
CPU_CFG & lt; 19 & gt;
BI
67 16 6
POWER FEATURES NOT ACTIVE
VR DOES NOT SUPPORT SVID
NOA ALWAYS UNLOCKED
ENABLED
PCH-LESS MODE
STALL AFTER PCU PLL LOCK
BI
67 16 6
=
=
=
=
=
=
BI
67 16 6
0
0
0
0
0
0
BI
67 16
NORMAL OPERATION
VR SUPPORTS SVID
NORMAL OPERATION
DISABLED
NORMAL OPERATION
NORMAL OPERATION
BI
67 16
=
=
=
=
=
=
BI
67 16
1
1
1
1
1
1
BI
67 16 6
CFG & lt; 10 & gt; :SAFE MODE BOOT
CFG & lt; 9 & gt; :NO SVID-CAPABLE VR
CFG & lt; 8 & gt; :ALLOW NOA ON LOCKED UNITS
CFG & lt; 4 & gt; :eDP ENABLE/DISABLE
CFG & lt; 1 & gt; :PCH-LESS MODE
CFG & lt; 0 & gt; :RESET SEQUENCE STALL
BI
67 64 16
B
BI
67 16
CPU_CFG & lt; 0 & gt;
CPU_CFG & lt; 1 & gt;
CPU_CFG & lt; 2 & gt;
CPU_CFG & lt; 3 & gt;
CPU_CFG & lt; 4 & gt;
CPU_CFG & lt; 5 & gt;
CPU_CFG & lt; 6 & gt;
CPU_CFG & lt; 7 & gt;
CPU_CFG & lt; 8 & gt;
CPU_CFG & lt; 9 & gt;
CPU_CFG & lt; 10 & gt;
CPU_CFG & lt; 11 & gt;
CPU_CFG & lt; 12 & gt;
CPU_CFG & lt; 13 & gt;
CPU_CFG & lt; 14 & gt;
CPU_CFG & lt; 15 & gt;
BI
AA62
U63
AA61
U62
NC
These can be placed close to J1800
and are only for debug access
NOSTUFF
HSW_PRE_ES2
R06401
1
1K
A
1K
5%
1/20W
MF
201 2
NOSTUFF
R06381
R0639
1K
5%
1/20W
MF
2 201
5%
1/20W
MF
201 2
NOSTUFF
1
R0631
1K
5%
1/20W
MF
2 201
V63
CPU_CFG_RCOMP
CPU_CFG & lt; 10 & gt;
CPU_CFG & lt; 9 & gt;
CPU_CFG & lt; 8 & gt;
CPU_CFG & lt; 1 & gt;
CPU_CFG & lt; 0 & gt;
NOSTUFF
6 16 67
6 16 67
6 16 67
PCH_TD_IREF
NC
NC
NC
NC
A5
E1
D1
J20
H18
B12
BGA-TSP
SYM 19 OF 19
CFG0 (IPU) RESERVED
RSVD_TP AV63
CFG1 (IPU)
RSVD_TP AU63
CFG2 (IPU)
CFG3 (IPU)
RSVD_TP C63
CFG4 (IPU)
RSVD_TP C62
CFG5 (IPU)
CFG6 (IPU)
EDP_SPARE B43
CFG7 (IPU)
RSVD_TP A51
CFG8 (IPU)
RSVD_TP B51
CFG9 (IPU)
CFG10 (IPU)
RSVD_TP L60
CFG11 (IPU)
CFG12 (IPU)
CFG13 (IPU)
RSVD N60
CFG14 (IPU)
CFG15 (IPU)
RSVD W23
RSVD Y22
CFG16 (IPU)
CFG18 (IPU)
PROC_OPI_COMP AY15
CFG17 (IPU)
CFG19 (IPU)
RSVD AV62
RSVD D58
CFG_RCOMP
RSVD
6 16 67
R06801
49.9
R0630
1%
1/20W
MF
201 2
1K
5%
1/20W
MF
2 201
TP_MCP_RSVD_C63
TP_MCP_RSVD_C62
NC
TP_MCP_RSVD_A51
TP_MCP_RSVD_B51
RSVD
RSVD
RSVD
RSVD
TD_IREF
RSVD P20
RSVD R20
B
TP_MCP_RSVD_L60
NC
NC
NC
CPU_OPI_RCOMP
1
R0690
NC
NC
49.9
1%
1/20W
MF
2 201
VSS P22
VSS N21
6 16 67
1
TP_MCP_RSVD_AV63
TP_MCP_RSVD_AU63
NC
NC
1
R0685
8.25K
1%
1/20W
MF
2 201
SYNC_MASTER=J41_MLB
SYNC_DATE=04/02/2013
PAGE TITLE
NOTE: Pre-ES2 CPUs have issue with Sx cycling, must set CFG & lt; 9 & gt; low to avoid
issue, but this locks CPU VR at 1.7V Vboot (CPU Sighting #4391569).
CPU Misc/JTAG/CFG/RSVD
DRAWING NUMBER
CPU_CFG & lt; 4 & gt; 6
EDP
16 67
Apple Inc.
R
1
R0634
1K
NOTICE OF PROPRIETARY PROPERTY:
5%
1/20W
MF
2 201
8
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
7
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
6 OF 121
SHEET
6 OF 76
1
A
7
6
5
4
3
CRITICAL
OMIT_TABLE
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
D
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63 21
BI
70 63
C
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
70 63
B
BI
70 63
BI
MEM_A_DQ & lt; 0 & gt;
MEM_A_DQ & lt; 1 & gt;
MEM_A_DQ & lt; 2 & gt;
MEM_A_DQ & lt; 3 & gt;
MEM_A_DQ & lt; 4 & gt;
MEM_A_DQ & lt; 5 & gt;
MEM_A_DQ & lt; 6 & gt;
MEM_A_DQ & lt; 7 & gt;
MEM_A_DQ & lt; 8 & gt;
MEM_A_DQ & lt; 9 & gt;
MEM_A_DQ & lt; 10 & gt;
MEM_A_DQ & lt; 11 & gt;
MEM_A_DQ & lt; 12 & gt;
MEM_A_DQ & lt; 13 & gt;
MEM_A_DQ & lt; 14 & gt;
MEM_A_DQ & lt; 15 & gt;
MEM_A_DQ & lt; 16 & gt;
MEM_A_DQ & lt; 17 & gt;
MEM_A_DQ & lt; 18 & gt;
MEM_A_DQ & lt; 19 & gt;
MEM_A_DQ & lt; 20 & gt;
MEM_A_DQ & lt; 21 & gt;
MEM_A_DQ & lt; 22 & gt;
MEM_A_DQ & lt; 23 & gt;
MEM_A_DQ & lt; 24 & gt;
MEM_A_DQ & lt; 25 & gt;
MEM_A_DQ & lt; 26 & gt;
MEM_A_DQ & lt; 27 & gt;
MEM_A_DQ & lt; 28 & gt;
MEM_A_DQ & lt; 29 & gt;
MEM_A_DQ & lt; 30 & gt;
MEM_A_DQ & lt; 31 & gt;
MEM_A_DQ & lt; 32 & gt;
MEM_A_DQ & lt; 33 & gt;
MEM_A_DQ & lt; 34 & gt;
MEM_A_DQ & lt; 35 & gt;
MEM_A_DQ & lt; 36 & gt;
MEM_A_DQ & lt; 37 & gt;
MEM_A_DQ & lt; 38 & gt;
MEM_A_DQ & lt; 39 & gt;
MEM_A_DQ & lt; 40 & gt;
MEM_A_DQ & lt; 41 & gt;
MEM_A_DQ & lt; 42 & gt;
MEM_A_DQ & lt; 43 & gt;
MEM_A_DQ & lt; 44 & gt;
MEM_A_DQ & lt; 45 & gt;
MEM_A_DQ & lt; 46 & gt;
MEM_A_DQ & lt; 47 & gt;
MEM_A_DQ & lt; 48 & gt;
MEM_A_DQ & lt; 49 & gt;
MEM_A_DQ & lt; 50 & gt;
MEM_A_DQ & lt; 51 & gt;
MEM_A_DQ & lt; 52 & gt;
MEM_A_DQ & lt; 53 & gt;
MEM_A_DQ & lt; 54 & gt;
MEM_A_DQ & lt; 55 & gt;
MEM_A_DQ & lt; 56 & gt;
MEM_A_DQ & lt; 57 & gt;
MEM_A_DQ & lt; 58 & gt;
MEM_A_DQ & lt; 59 & gt;
MEM_A_DQ & lt; 60 & gt;
MEM_A_DQ & lt; 61 & gt;
MEM_A_DQ & lt; 62 & gt;
MEM_A_DQ & lt; 63 & gt;
AH63
AH62
AK63
AK62
AH61
AH60
AK61
AK60
AM63
AM62
AP63
AP62
AM61
AM60
AP61
AP60
AP58
AR58
AM57
AK57
AL58
AK58
AR57
AN57
AP55
AR55
AM54
AK54
AL55
AK55
AR54
AN54
AY58
AW58
AY56
AW56
AV58
AU58
AV56
AU56
AY54
AW54
AY52
AW52
AV54
AU54
AV52
AU52
AK40
AK42
AM43
AM45
AK45
AK43
AM40
AM42
AM46
AK46
AM49
AK49
AM48
AK48
AM51
AK51
SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63
U0500
HASWELL-ULT
2C+GT2
BGA-TSP
SYM 3 OF 19
SA_CLK0*
SA_CLK0
SA_CLK1*
SA_CLK1
SA_CKE0
SA_CKE1
SA_CKE2
SA_CKE3
AU37
AV37
AW36
AY36
AU43
AW43
AY42
AY43
MEM_A_CLK_N & lt; 0 & gt;
MEM_A_CLK_P & lt; 0 & gt;
MEM_A_CLK_N & lt; 1 & gt;
MEM_A_CLK_P & lt; 1 & gt;
OUT
20 24 70
70 63
BI
OUT
20 24 70
70 63
BI
MEM_A_CKE & lt; 0 & gt;
MEM_A_CKE & lt; 1 & gt;
MEM_A_CKE & lt; 2 & gt;
MEM_A_CKE & lt; 3 & gt;
OUT
21 24 70
70 63
BI
OUT
21 24 70
70 63
BI
BI
SA_ODT0 AP32
MEM_A_ODT & lt; 0 & gt;
LPDDR3
CAB3 SA_RAS* AY34
CAB2
SA_WE* AW34
CAB1 SA_CAS* AU34
=MEM_A_RAS_L
=MEM_A_WE_L
=MEM_A_CAS_L
70 63
BI
20 24 70
70 63
BI
OUT
21 24 70
70 63
BI
OUT
21 24 70
70 63
BI
BI
OUT
20 21 24 70
70 63
BI
OUT
20 21 24 70
70 63
BI
70 63
MEM_A_CS_L & lt; 0 & gt;
MEM_A_CS_L & lt; 1 & gt;
20 24 70
OUT
70 63
SA_CS0* AP33
SA_CS1* AR32
BI
OUT
OUT
20 21 24 63 70
OUT
63
OUT
OUT
SA_BA0 AU35
SA_BA1 AV35
SA_BA2 AY41
BI
70 63
=MEM_A_BA & lt; 0 & gt;
MEM_A_CAB & lt; 6 & gt;
=MEM_A_BA & lt; 2 & gt;
70 63
BI
70 63
BI
63
70 63
BI
63
70 63
BI
70 63
CAB4
CAB6
CAA5
BI
SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_MA14
SA_MA15
AU36
AY37
AR38
AP36
AU39
AR36
AV40
AW39
AY39
AU40
AP35
AW41
AU41
AR35
AV42
AU42
=MEM_A_A & lt; 0 & gt;
=MEM_A_A & lt; 1 & gt;
=MEM_A_A & lt; 2 & gt;
TP_LPDDR3_RSVD1
TP_LPDDR3_RSVD2
=MEM_A_A & lt; 5 & gt;
=MEM_A_A & lt; 6 & gt;
=MEM_A_A & lt; 7 & gt;
=MEM_A_A & lt; 8 & gt;
=MEM_A_A & lt; 9 & gt;
=MEM_A_A & lt; 10 & gt;
=MEM_A_A & lt; 11 & gt;
MEM_A_CAA & lt; 6 & gt;
=MEM_A_A & lt; 13 & gt;
=MEM_A_A & lt; 14 & gt;
=MEM_A_A & lt; 15 & gt;
OUT
63
70 63
BI
OUT
21 24 63 70
70 63
BI
OUT
63
70 63
BI
70 63
CAB9
CAB8
CAB5
RSVD1
RSVD2
CAA0
CAA2
CAA4
CAA3
CAA1
CAB7
CAA7
CAA6
CAB0
CAA9
CAA8
1
CRITICAL
OMIT_TABLE
70 63
MEMORY CHANNEL A
70 63
2
BI
AJ61
AN62
AM58
AM55
AV57
AV53
AL43
AL48
MEM_A_DQS_N & lt; 0 & gt;
MEM_A_DQS_N & lt; 1 & gt;
MEM_A_DQS_N & lt; 2 & gt;
MEM_A_DQS_N & lt; 3 & gt;
MEM_A_DQS_N & lt; 4 & gt;
MEM_A_DQS_N & lt; 5 & gt;
MEM_A_DQS_N & lt; 6 & gt;
MEM_A_DQS_N & lt; 7 & gt;
SA_DQSP0
SA_DQSP1
SA_DQSP2
SA_DQSP3
SA_DQSP4
SA_DQSP5
SA_DQSP6
SA_DQSP7
AJ62
AN61
AN58
AN55
AW57
AW53
AL42
AL49
MEM_A_DQS_P & lt; 0 & gt;
MEM_A_DQS_P & lt; 1 & gt;
MEM_A_DQS_P & lt; 2 & gt;
MEM_A_DQS_P & lt; 3 & gt;
MEM_A_DQS_P & lt; 4 & gt;
MEM_A_DQS_P & lt; 5 & gt;
MEM_A_DQS_P & lt; 6 & gt;
MEM_A_DQS_P & lt; 7 & gt;
63
70 63
BI
OUT
63
70 63
BI
OUT
63
70 63
BI
OUT
63
70 63
BI
OUT
63
70 63
BI
OUT
63
70 63
BI
OUT
63
70 63
BI
OUT
63
70 63
BI
OUT
63
70 63
BI
OUT
63
70 63
BI
OUT
63
70 63 23
BI
OUT
63
70 63
BI
OUT
20 24 63 70
70 63
BI
OUT
63
70 63
BI
OUT
63
70 63
BI
OUT
63
70 63
BI
70 63
SA_DQSN0
SA_DQSN1
SA_DQSN2
SA_DQSN3
SA_DQSN4
SA_DQSN5
SA_DQSN6
SA_DQSN7
OUT
BI
SM_VREF_DQ1 AP51
CPU_DIMMB_VREFDQ
BI
63 70
70 63
BI
BI
63 70
70 63
BI
BI
63 70
70 63
BI
BI
63 70
70 63
BI
BI
63 70
70 63
BI
BI
21 63 70
70 63
BI
BI
63 70
70 63
BI
BI
BI
63 70
70 63
BI
BI
63 70
70 63
BI
BI
63 70
70 63
BI
BI
63 70
70 63
BI
BI
63 70
70 63
BI
BI
63 70
70 63
BI
BI
21 63 70
70 63
BI
BI
63 70
70 63
BI
BI
BI
70 63
CPU_DIMMA_VREFDQ
BI
70 63
SM_VREF_DQ0 AR51
70 63
70 63
CPU_DIMM_VREFCA
63 70
70 63
SM_VREF_CA AP49
BI
BI
70 63
BI
70 63
BI
70 63
BI
70 63
BI
OUT
OUT
OUT
19
19
19
MEM_B_DQ & lt; 0 & gt;
MEM_B_DQ & lt; 1 & gt;
MEM_B_DQ & lt; 2 & gt;
MEM_B_DQ & lt; 3 & gt;
MEM_B_DQ & lt; 4 & gt;
MEM_B_DQ & lt; 5 & gt;
MEM_B_DQ & lt; 6 & gt;
MEM_B_DQ & lt; 7 & gt;
MEM_B_DQ & lt; 8 & gt;
MEM_B_DQ & lt; 9 & gt;
MEM_B_DQ & lt; 10 & gt;
MEM_B_DQ & lt; 11 & gt;
MEM_B_DQ & lt; 12 & gt;
MEM_B_DQ & lt; 13 & gt;
MEM_B_DQ & lt; 14 & gt;
MEM_B_DQ & lt; 15 & gt;
MEM_B_DQ & lt; 16 & gt;
MEM_B_DQ & lt; 17 & gt;
MEM_B_DQ & lt; 18 & gt;
MEM_B_DQ & lt; 19 & gt;
MEM_B_DQ & lt; 20 & gt;
MEM_B_DQ & lt; 21 & gt;
MEM_B_DQ & lt; 22 & gt;
MEM_B_DQ & lt; 23 & gt;
MEM_B_DQ & lt; 24 & gt;
MEM_B_DQ & lt; 25 & gt;
MEM_B_DQ & lt; 26 & gt;
MEM_B_DQ & lt; 27 & gt;
MEM_B_DQ & lt; 28 & gt;
MEM_B_DQ & lt; 29 & gt;
MEM_B_DQ & lt; 30 & gt;
MEM_B_DQ & lt; 31 & gt;
MEM_B_DQ & lt; 32 & gt;
MEM_B_DQ & lt; 33 & gt;
MEM_B_DQ & lt; 34 & gt;
MEM_B_DQ & lt; 35 & gt;
MEM_B_DQ & lt; 36 & gt;
MEM_B_DQ & lt; 37 & gt;
MEM_B_DQ & lt; 38 & gt;
MEM_B_DQ & lt; 39 & gt;
MEM_B_DQ & lt; 40 & gt;
MEM_B_DQ & lt; 41 & gt;
MEM_B_DQ & lt; 42 & gt;
MEM_B_DQ & lt; 43 & gt;
MEM_B_DQ & lt; 44 & gt;
MEM_B_DQ & lt; 45 & gt;
MEM_B_DQ & lt; 46 & gt;
MEM_B_DQ & lt; 47 & gt;
MEM_B_DQ & lt; 48 & gt;
MEM_B_DQ & lt; 49 & gt;
MEM_B_DQ & lt; 50 & gt;
MEM_B_DQ & lt; 51 & gt;
MEM_B_DQ & lt; 52 & gt;
MEM_B_DQ & lt; 53 & gt;
MEM_B_DQ & lt; 54 & gt;
MEM_B_DQ & lt; 55 & gt;
MEM_B_DQ & lt; 56 & gt;
MEM_B_DQ & lt; 57 & gt;
MEM_B_DQ & lt; 58 & gt;
MEM_B_DQ & lt; 59 & gt;
MEM_B_DQ & lt; 60 & gt;
MEM_B_DQ & lt; 61 & gt;
MEM_B_DQ & lt; 62 & gt;
MEM_B_DQ & lt; 63 & gt;
AY31
AW31
AY29
AW29
AV31
AU31
AV29
AU29
AY27
AW27
AY25
AW25
AV27
AU27
AV25
AU25
AM29
AK29
AL28
AK28
AR29
AN29
AR28
AP28
AN26
AR26
AR25
AP25
AK26
AM26
AK25
AL25
AY23
AW23
AY21
AW21
AV23
AU23
AV21
AU21
AY19
AW19
AY17
AW17
AV19
AU19
AV17
AU17
AR21
AR22
AL21
AM22
AN22
AP21
AK21
AK22
AN20
AR20
AK18
AL18
AK20
AM20
AR18
AP18
SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63
U0500
A
BGA-TSP
SYM 4 OF 19
SB_CK0*
SB_CK0
SB_CK1*
SB_CK1
AM38
AN38
AK38
AL38
MEM_B_CLK_N & lt; 0 & gt;
MEM_B_CLK_P & lt; 0 & gt;
MEM_B_CLK_N & lt; 1 & gt;
MEM_B_CLK_P & lt; 1 & gt;
SB_CKE0
SB_CKE1
SB_CKE2
SB_CKE3
HASWELL-ULT
2C+GT2
MEMORY CHANNEL B
8
AY49
AU50
AW49
AV50
MEM_B_CKE & lt; 0 & gt;
MEM_B_CKE & lt; 1 & gt;
MEM_B_CKE & lt; 2 & gt;
MEM_B_CKE & lt; 3 & gt;
SB_CS0* AM32
SB_CS1* AK32
LPDDR3
CAB3 SB_RAS* AM35
CAB2
SB_WE* AK35
CAB1 SB_CAS* AM33
CAB4
CAB6
CAA5
SB_BA0 AL35
SB_BA1 AM36
SB_BA2 AU49
CAB9
CAB8
CAB5
RSVD3
RSVD4
CAA0
CAA2
CAA4
CAA3
CAA1
CAB7
CAA7
CAA6
CAB0
CAA9
CAA8
SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_MA14
SB_MA15
AP40
AR40
AP42
AR42
AR45
AP45
AW46
AY46
AY47
AU46
AK36
AV47
AU47
AK33
AR46
AP46
SB_DQSN0
SB_DQSN1
SB_DQSN2
SB_DQSN3
SB_DQSN4
SB_DQSN5
SB_DQSN6
SB_DQSN7
AW30
AV26
AN28
AN25
AW22
AV18
AN21
AN18
SB_DQSP0
SB_DQSP1
SB_DQSP2
SB_DQSP3
SB_DQSP4
SB_DQSP5
SB_DQSP6
SB_DQSP7
AV30
AW26
AM28
AM25
AV22
AW18
AM21
AM18
23 24 70
OUT
23 24 70
OUT
22 23 24 70
OUT
22 23 24 70
OUT
22 23 24 63 70
OUT
63
OUT
63
OUT
63
OUT
63
OUT
23 24 63 70
OUT
63
OUT
63
OUT
63
OUT
63
OUT
63
OUT
63
OUT
63
OUT
63
OUT
63
OUT
63
OUT
63
OUT
63
OUT
63
OUT
22 24 63 70
OUT
63
OUT
63
OUT
MEM_B_DQS_P & lt; 0 & gt;
MEM_B_DQS_P & lt; 1 & gt;
MEM_B_DQS_P & lt; 2 & gt;
MEM_B_DQS_P & lt; 3 & gt;
MEM_B_DQS_P & lt; 4 & gt;
MEM_B_DQS_P & lt; 5 & gt;
MEM_B_DQS_P & lt; 6 & gt;
MEM_B_DQS_P & lt; 7 & gt;
22 24 70
OUT
MEM_B_DQS_N & lt; 0 & gt;
MEM_B_DQS_N & lt; 1 & gt;
MEM_B_DQS_N & lt; 2 & gt;
MEM_B_DQS_N & lt; 3 & gt;
MEM_B_DQS_N & lt; 4 & gt;
MEM_B_DQS_N & lt; 5 & gt;
MEM_B_DQS_N & lt; 6 & gt;
MEM_B_DQS_N & lt; 7 & gt;
22 24 70
OUT
=MEM_B_A & lt; 0 & gt;
=MEM_B_A & lt; 1 & gt;
=MEM_B_A & lt; 2 & gt;
TP_LPDDR3_RSVD3
TP_LPDDR3_RSVD4
=MEM_B_A & lt; 5 & gt;
=MEM_B_A & lt; 6 & gt;
=MEM_B_A & lt; 7 & gt;
=MEM_B_A & lt; 8 & gt;
=MEM_B_A & lt; 9 & gt;
=MEM_B_A & lt; 10 & gt;
=MEM_B_A & lt; 11 & gt;
MEM_B_CAA & lt; 6 & gt;
=MEM_B_A & lt; 13 & gt;
=MEM_B_A & lt; 14 & gt;
=MEM_B_A & lt; 15 & gt;
23 24 70
OUT
=MEM_B_BA & lt; 0 & gt;
MEM_B_CAB & lt; 6 & gt;
=MEM_B_BA & lt; 2 & gt;
23 24 70
OUT
=MEM_B_RAS_L
=MEM_B_WE_L
=MEM_B_CAS_L
22 24 70
OUT
MEM_B_ODT & lt; 0 & gt;
22 24 70
OUT
MEM_B_CS_L & lt; 0 & gt;
MEM_B_CS_L & lt; 1 & gt;
SB_ODT0 AL32
OUT
63
BI
63 70
BI
63 70
BI
63 70
BI
63 70
BI
63 70
BI
23 63 70
BI
63 70
BI
63 70
BI
63 70
BI
63 70
BI
63 70
BI
63 70
BI
63 70
BI
23 63 70
BI
C
63 70
BI
D
63 70
B
SYNC_MASTER=J41_MLB
SYNC_DATE=02/06/2013
PAGE TITLE
CPU DDR3/LPDDR3 Interfaces
DRAWING NUMBER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
7 OF 121
SHEET
7 OF 76
1
A
8
7
6
5
4
3
2
HSW-ULT current estimates from Haswell Mobile ULT Processor EDS vol 1, doc #502406, v0.9.
LPT-LP current estimates from Lynx Point-LP PCH EDS, doc #503118, v1.0.
Note [1] current numbers from clarification email, from Srini, dated 9/10/2012 2:11pm.
CRITICAL
OMIT_TABLE
42 10
D
64 62 52 42 10 8
PPVCC_S0_CPU
R08601
PLACE_NEAR=U0500.C50:50.8mm
PP1V05_S0
67 51
1
1
R0800
R0802
75
1%
1/20W
MF
201 2
67 51
IN
CPU_VIDALERT_L
OUT
Max load: 300mA
R0810
43
1
5
Max load: 300mA
5%
1/20W
MF
201
R0811
CPU_VCCSENSE_P
TP_PPVCCIO_S0_CPU
NC
PPVCOMP_S0_CPU
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
NOTE: Aliases not used on CPU supply outputs NC
NC
to avoid any extraneous connections.
2
NC
OUT
CPU_VIDSCLK
1
67 51
BI
CPU_VIDSOUT
17 16
IN
51 17
OUT
51 17
IN
IN
CPU_PWR_DEBUG
2
5%
1/20W
MF
0201
R0812
0
1
R0802.2: PLACE_NEAR=U0500.L63:2.54mm
R0810.2: PLACE_NEAR=U0500.L62:38.1mm
R0800.2: PLACE_NEAR=R0810.1:2.54mm
2
5%
1/20W
MF
0201
C
CRITICAL
OMIT_TABLE
B11
NC
58 17 11
NC
62 59 58 57 46 18 14 11 8
64
42 34 29 28 18 17 16 15 13 11
74 64 62 60 59 58 57
74 65 64 62 61 59 56 45
30 27 18 17 15 13 12 11 8
44 43 42 41 40 39 38 36
11
A
12 11
42 38 27 17 16 15 11 8 6
64 62 59 58 55 51
J13
AH10
PP3V3_S5
114mA Max
PP3V3_S0
40mA Max[1]
RTC
DCPSUS3
AC9
AA9
PP3V3_SUS
59mA Max[1]
V8
W9
HSIO
SPI
AZALIA/HDA
VCCHDA
VCC1P05
VCC1P05
VCC1P05
VCC1P05
VCC1P05
VCCSUS3
VCCSUS3
VCCDSW3_3
VCC3
VCC3
PP1V05_S0_PCH_VCC_ICC
VCCCLK: 200mA Max
A20
DCPSUS1 AD10
DCPSUS1 AD8
THERMAL SENSOR
VCCTS1_5 J15
VCC3 K14
VCC3 K16
VCCACLKPLL
PP3V3_SUS
3.3mA Max[1]
NC
NC
NC
J17
R21
T21
K18
M20
V21
AE20
AE21
VCCCLK
VCCCLK
VCCCLK
VCCCLK
VCCCLK
VCCCLK
VCCSUS3
VCCSUS3
51 42 38 27 17 16 15 11 8 6
64 62 59 58 55
8 11 14 18 46 57 58 59 62 64
PPVRTC_G3H
PPVOUT_S0_PCH_DCPRTC
BYPASS=U0500.AE7:6.35mm
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
C0892 1 C0891
0.1UF
1
C0895
PP3V3_SUS
18mA Max
8 11 14 18 46 57 58 59
62 64
PP1V05_S0
185mA Max[1]
6 8 11 15 16 17 27 38 42
51 55 58 59 62 64
PP1V05_S0
1499mA Max[1]
20%
10V
CERM 2
402
1
0.1UF
20%
10V
CERM 2
402
1
7
VCC_SENSE
AB23
A59
E20
AD23
AA23
AE59
HSW ULT POWER
RSVD
VCCIO_OUT
VCCIOA_OUT
RSVD
RSVD
RSVD
VIDALERT*
VIDSCLK
VIDSOUT
VCCST_PWRGD
VR_EN
VR_READY
12 13 17 62 64
C0890
1UF
10%
6.3V
2 CERM
402
D63
H59
P62
P60
P61
N59
N61
T59
AD60
AD59
AA59
AE60
AC59
AG58
U59
V59
VSS
PWR_DEBUG*
VSS
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
VCCST
VCCST
VCCST
AB57
AD57
AG57
C24
C28
C32
PP1V05_S0
???mA Max
VCC
VCC
VCC
VCC
VCC
VCC
C36
C40
C44
C48
C52
C56
E23
E25
E27
E29
E31
E33
E35
E37
E39
E41
E43
E45
E47
E49
E51
E53
E55
E57
F24
F28
F32
F36
F40
F44
F48
F52
F56
G23
G25
G27
G29
G31
G33
G35
G37
G39
G41
G43
G45
G47
G49
G51
G53
G55
G57
H23
J23
K23
K57
L22
M23
M57
P57
U57
W57
PPVCC_S0_CPU
32A Max
8 10 42 52 62 64
D
C
6 8 11 15 16 17 27 38 42 51 55
58 59 62 64
0.1UF
20%
2 10V
CERM
402
BYPASS=U0500.AG10:6.35mm
BYPASS=U0500.AG10:6.35mm
BYPASS=U0500.AG10:6.35mm
B
PLACE_NEAR=U0500.AG19:2.54mm
PPVOUT_S5_PCH_DCPSUSBYP_R
Powered in DeepSx
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
PP1V05_S0
473mA Max[1]
1
5.11 2
1%
1/20W
MF-LF
201
PPVOUT_S5_PCH_DCPSUSBYP
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
1
C0899
1UF
6 8 11 15 16 17 27 38 42 51 55
58 59 62 64
10%
2 6.3V
CERM
402
BYPASS=R0899:U0500:2.54mm
NC
NC
PP1V5_S0
3mA Max
PP3V3_S0
1mA Max[1]
57 58 59 62 64
62 64 65 74
8 11 12 13 15 17 18 27 30 36 38
39 40 41 42 43 44 45 56 59 61
SERIAL IO
VCCSDIO U8
VCCSDIO T9
SUS OSCILLATOR
DCPSUS4 AB8
VCCAPLL AC20
PP3V3_S0
17mA Max
62 64 65 74
8 11 12 13 15 17 18 27 30 36 38
39 40 41 42 43 44 45 56 59 61
SYNC_MASTER=J41_MLB
SYNC_DATE=04/09/2013
PAGE TITLE
CPU/PCH POWER
DRAWING NUMBER
NC
NC
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
VCCIO AG16
VCCIO AG17
PP1V05_S0
213mA Max[1]
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
6 8 11 15 16 17 27 38 42 51 55
58 59 62 64
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
R
WF: RSVD on Sawtooth Peak rev 1.0
LPT LP POWER
8
VCC
RSVD
RSVD
BGA-TSP
SYM 12 OF 19
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
R0899
VCCASW AE9
VCCASW AF9
VCCASW AG8
VCC1P05
VCC1P05
PP1V05_S0_PCH_VCCACLKPLL
31mA Max
PP1V05_S0
VCCCLK: 200mA Max
J11
H11
H15
AE8
AF22
DCPSUSBYP AG19
DCPSUSBYP AG20
VRM/USB2/AZALIA
DCPSUS2
J18
K19
WF: RSVD on Sawtooth Peak rev 1.0
62 59 58 57 46 18 14 11 8
64
VCCAPLL
VCCAPLL
VCCAPLL
AH13
VCCASW AG14
VCCASW AG13
VCCSATA3PLL
Y20
AA21
W21
AH14
PP1V5_S0SW_AUDIO_HDA
11mA Max
VCCSPI Y8
OPI
WF: RSVD on Sawtooth Peak rev 1.0 NC
PP1V05_S0_PCH_VCCAPLL_OPI
11
57mA Max
VCCUSB3PLL
DCPRTC AE7
USB3
12 11
VCCIO
VCCIO
PP3V3_SUS
0.3mA Max[1]
NC
NC
NC
NC
NC
NC
NC
NC
NC
VCCRTC AG10
BGA-TSP
SYM 13 OF 19
CORE
B
B18
PP1V05_S0SW_PCH_VCCUSB3PLL
41mA Max
PP1V05_S0SW_PCH_VCCSATA3PLL
42mA Max
VCCSUS3 AH11
HASWELL-ULT
2C+GT2
GPIO/LCC
14 11
N8
P9
PP1V05_S0
29mA Max[1]
U0500
VCCHSIO
VCCHSIO
VCCHSIO
ICC
42 38 27 17 16 15 11 8 6
64 62 59 58 55 51
PP1V05_S0SW_PCH_HSIO
1838mA Max
USB2
62 58 11
U0500
HASWELL-ULT
2C+GT2
AC22
AE22
AE23
TP_CPU_RSVD_P60
TP_CPU_RSVD_P61
TP_CPU_RSVD_N59
TP_CPU_RSVD_N61
K9
L10
M9
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
L62
N63
L63
B59
F60
C59
CPU_VIDALERT_R_L
CPU_VIDSCLK_R
CPU_VIDSOUT_R
CPU_VCCST_PWRGD
CPU_VR_EN
CPU_VR_READY
16
67 51
0
AH26
AJ31
AJ33
AJ37
AN33
AP43
AR48
AY35
AY40
AY44
AY50
NC
AC58
NC
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
130
1%
1/20W
MF
2 201
100
5%
1/20W
MF
201 2
RSVD
RSVD
E63
PPVMEMIO_S0_CPU
1.4A Max (DDR3: 1.5-1.35V)
1.1A Max (LPDDR3: 1.2V)
L59
J58
F59
N58
NC
NC
51 42 38 27 17 16 15 11 8 6
64 62 59 58 55
1
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
8 OF 121
SHEET
8 OF 76
1
A
8
7
6
5
4
CRITICAL
OMIT_TABLE
3
2
CRITICAL
OMIT_TABLE
CRITICAL
OMIT_TABLE
U0500
U0500
U0500
HASWELL-ULT
2C+GT2
HASWELL-ULT
2C+GT2
HASWELL-ULT
2C+GT2
BGA-TSP
SYM 14 OF 19
A11
A14
A18
A24
A28
A32
A36
A40
A44
A48
A52
A56
AA1
AA58
AB10
AB20
AB22
AB7
AC61
AD21
AD3
AD63
AE10
AE5
AE58
AF11
AF12
AF14
AF15
AF17
AF18
AG1
AG11
AG21
AG23
AG60
AG61
AG62
AG63
AH17
AH19
AH20
AH22
AH24
AH28
AH30
AH32
AH34
AH36
AH38
AH40
AH42
AH44
AH49
AH51
AH53
AH55
AH57
AJ13
AJ14
AJ23
AJ25
AJ27
AJ29
D
C
B
1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AP22
AP23
AP26
AP29
AP3
AP31
AP38
AP39
AP48
AP52
AP54
AP57
AR11
AR15
AR17
AR23
AR31
AR33
AR39
AR43
AR49
AR5
AR52
AT13
AT35
AT37
AT40
AT42
AT43
AT46
AT49
AT61
AT62
AT63
AU1
AU16
AU18
AU20
AU22
AU24
AU26
AU28
AU30
AU33
AU51
AU53
AU55
AU57
AU59
AV14
AV16
AV20
AV24
AV28
AV33
AV34
AV36
AV39
AV41
AV43
AV46
AV49
AV51
AV55
AJ35
AJ39
AJ41
AJ43
AJ45
AJ47
AJ50
AJ52
AJ54
AJ56
AJ58
AJ60
AJ63
AK23
AK3
AK52
AL10
AL13
AL17
AL20
AL22
AL23
AL26
AL29
AL31
AL33
AL36
AL39
AL40
AL45
AL46
AL51
AL52
AL54
AL57
AL60
AL61
AM1
AM17
AM23
AM31
AM52
AN17
AN23
AN31
AN32
AN35
AN36
AN39
AN40
AN42
AN43
AN45
AN46
AN48
AN49
AN51
AN52
AN60
AN63
AN7
AP10
AP17
AP20
BGA-TSP
SYM 15 OF 19
VSS
VSS AV59
VSS
VSS AV8
VSS
VSS AW16
VSS
VSS AW24
VSS
VSS AW33
VSS
VSS AW35
VSS
VSS AW37
VSS
VSS AW4
VSS
VSS AW40
VSS
VSS AW42
VSS
VSS AW44
VSS
VSS AW47
VSS
VSS AW50
VSS
VSS AW51
VSS
VSS AW59
VSS
VSS AW60
VSS
VSS AY11
VSS
VSS AY16
VSS
VSS AY18
VSS
VSS AY22
VSS
VSS AY24
VSS
VSS AY26
VSS
VSS AY30
VSS
VSS AY33
VSS
VSS AY4
VSS
VSS AY51
VSS
VSS AY53
VSS
VSS AY57
VSS
VSS AY59
VSS
VSS AY6
VSS
VSS B20
VSS
VSS B24
VSS
VSS B26
VSS
VSS B28
VSS
VSS B32
VSS
VSS B36
VSS
VSS B4
VSS
VSS B40
VSS
VSS B44
VSS
VSS B48
VSS
VSS B52
VSS
VSS B56
VSS
VSS B60
VSS
VSS C11
VSS
VSS C14
VSS
VSS C18
VSS
VSS C20
VSS
VSS C25
VSS
VSS C27
VSS
VSS C38
VSS
VSS C39
VSS
VSS C57
VSS
VSS D12
VSS
VSS D14
VSS
VSS D18
VSS
VSS D2
VSS
VSS D21
VSS
VSS D23
VSS
VSS D25
VSS
VSS D26
VSS
VSS D27
VSS
VSS D29
VSS
VSS D30
VSS
VSS D31
D33
D34
D35
D37
D38
D39
D41
D42
D43
D45
D46
D47
D49
D5
D50
D51
D53
D54
D55
D57
D59
D62
D8
E11
E17
F20
F26
F30
F34
F38
F42
F46
F50
F54
F58
F61
G18
G22
G3
G5
G6
G8
H13
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
BGA-TSP
SYM 16 OF 19
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS_SENSE
VSS
H17
H57
J10
J22
J59
J63
K1
K12
L13
L15
L17
L18
L20
L58
L61
L7
M22
N10
N3
P59
P63
R10
R22
R8
T1
T58
U20
U22
U61
U9
V10
V3
V7
W20
W22
Y10
Y59
Y63
D
C
V58
AH46
V23
E62
AH16
CPU_VCCSENSE_N
OUT
51 67
1
R0960
100
5%
1/20W
MF
2 201
PLACE_NEAR=U0500.E62:50.8mm
B
A
SYNC_MASTER=J41_MLB
SYNC_DATE=02/06/2013
PAGE TITLE
CPU/PCH GROUNDS
DRAWING NUMBER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
9 OF 121
SHEET
9 OF 76
1
A
8
7
6
5
4
3
2
1
All Intel recommendations from Intel doc #503160 Shark Bay Ultrabook Platform Power Delivery Design Guide Rev 1.0 unless stated otherwise
CPU VCC Decoupling
64 62 52 42 8
PPVCC_S0_CPU
Intel recommendation (Table 5-1): 23x 22uF 0805 stuff, 7x 22uF 0805 nostuff
Apple implementation
: 18x 10uF 0402 mirrored stuff, 1x 470uF stuff, 50x 10uF mirrored no stuff, 50x 10uF single sided no stuff
CRITICAL
1
CRITICAL
C1000
1
10UF
1
10UF
1
1
10UF
1
1
10UF
1
10UF
20%
4V
2 X6S
0402
1
10UF
NO STUFF
1
1
NO STUFF
C109B
1
10UF
1
1
C1047
C109E
10UF
20%
4V
2 X6S
0402
C1062
C1063
10UF
20%
4V
2 X6S
0402
C109F
C108A
10UF
20%
4V
2 X6S
0402
20%
4V
2 X6S
0402
C1076
20%
4V
2 X6S
0402
1
C1091
10UF
20%
2 4V
X6S
0402
20%
4V
2 X6S
0402
C1028
10UF
20%
4V
2 X6S
0402
C1077
20%
4V
2 X6S
0402
1
C1092
10UF
20%
2 4V
X6S
0402
20%
4V
2 X6S
0402
C1029
10UF
20%
4V
2 X6S
0402
C1078
20%
4V
2 X6S
0402
1
C1093
10UF
20%
4V
2 X6S
0402
20%
4V
2 X6S
0402
C1032
10UF
20%
4V
2 X6S
0402
C1079
20%
4V
2 X6S
0402
1
C1094
10UF
20%
4V
2 X6S
0402
20%
4V
2 X6S
0402
C1033
10UF
20%
4V
2 X6S
0402
C1080
20%
4V
2 X6S
0402
1
20%
4V
2 X6S
0402
C1081
C1095
20%
4V
2 X6S
0402
10UF
20%
4V
2 X6S
0402
C1096
10UF
20%
2 4V
X6S
0402
1
C1035
10UF
20%
4V
2 X6S
0402
C104E
10UF
20%
4V
2 X6S
0402
NO STUFF
1
C1082
20%
2 4V
X6S
0402
C1013
CRITICAL
1
10UF
20%
4V
2 X6S
0402
NO STUFF
1
C104F
C106A
10UF
20%
4V
2 X6S
0402
20%
4V
2 X6S
0402
CRITICAL
C1083
NO STUFF
1
C105A
10UF
20%
4V
2 X6S
0402
NO STUFF
1
10UF
1
C1014
10UF
20%
4V
2 X6S
0402
10UF
NO STUFF
1
10UF
20%
4V
2 X6S
0402
NO STUFF
1
C106B
10UF
20%
4V
2 X6S
0402
C105B
NO STUFF
1
C106C
10UF
20%
4V
2 X6S
0402
1
10UF
20%
4V
2 X6S
0402
NO STUFF
1
C105D
10UF
20%
4V
2 X6S
0402
NO STUFF
1
NO STUFF
C105C
NO STUFF
1
C105E
NO STUFF
1
10UF
C105F
10UF
20%
4V
2 X6S
0402
20%
4V
2 X6S
0402
D
NO STUFF
C106D
1
10UF
C106E
10UF
20%
4V
2 X6S
0402
20%
4V
2 X6S
0402
CRITICAL
1
10UF
C1084
10UF
20%
4V
2 X6S
0402
20%
4V
2 X6S
0402
NO STUFF
1
C1097
10UF
20%
2 4V
X6S
0402
NO STUFF
1
NO STUFF
1
NO STUFF
NO STUFF
NO STUFF
C1034
20%
4V
2 X6S
0402
10UF
1
C1012
10UF
NO STUFF
1
20%
2 4V
X6S
0402
10UF
1
C104D
10UF
NO STUFF
1
CRITICAL
1
NO STUFF
10UF
20%
4V
2 X6S
0402
C1011
10UF
NO STUFF
1
NO STUFF
1
C104C
10UF
NO STUFF
1
NO STUFF
1
NO STUFF
10UF
20%
4V
2 X6S
0402
C1010
10UF
NO STUFF
1
NO STUFF
1
C104B
10UF
NO STUFF
1
CRITICAL
1
NO STUFF
10UF
20%
4V
2 X6S
0402
C1009
10UF
NO STUFF
1
NO STUFF
1
C104A
10UF
NO STUFF
1
NO STUFF
1
NO STUFF
10UF
20%
2 4V
X6S
0402
C1008
10UF
CRITICAL
1
NO STUFF
1
C1030
10UF
NO STUFF
1
NO STUFF
1
NO STUFF
10UF
20%
2 4V
X6S
0402
C1007
10UF
CRITICAL
1
NO STUFF
1
C1036
10UF
20%
4V
2 X6S
0402
NO STUFF
1
C1037
NO STUFF
1
10UF
C
C1038
10UF
20%
4V
2 X6S
0402
20%
4V
2 X6S
0402
NO STUFF
1
C1049
10UF
20%
4V
2 X6S
0402
NO STUFF
1
C1064
10UF
20%
2 4V
X6S
0402
NO STUFF
1
10UF
20%
2 4V
X6S
0402
20%
4V
2 X6S
0402
NO STUFF
1
NO STUFF
1
C1048
C1021
10UF
NO STUFF
1
20%
4V
2 X6S
0402
10UF
20%
2 4V
X6S
0402
20%
4V
2 X6S
0402
10UF
NO STUFF
C109D
C1027
10UF
NO STUFF
1
20%
2 4V
X6S
0402
10UF
20%
4V
2 X6S
0402
C1059
1
NO STUFF
1
20%
4V
2 X6S
0402
10UF
NO STUFF
C109C
10UF
20%
4V
2 X6S
0402
1
20%
2 4V
X6S
0402
C1026
10UF
NO STUFF
C1058
10UF
20%
4V
2 X6S
0402
20%
4V
2 X6S
0402
NO STUFF
1
20%
4V
2 X6S
0402
NO STUFF
C1057
10UF
20%
4V
2 X6S
0402
10UF
20%
4V
2 X6S
0402
C1046
C1090
CRITICAL
1
CRITICAL
NO STUFF
1
10UF
10UF
20%
4V
2 X6S
0402
NO STUFF
C1056
1
C1089
NO STUFF
1
NO STUFF
C1045
10UF
20%
4V
2 X6S
0402
NO STUFF
1
1
10UF
C1025
20%
4V
2 X6S
0402
NO STUFF
C1044
20%
4V
2 X6S
0402
20%
4V
2 X6S
0402
10UF
20%
4V
2 X6S
0402
NO STUFF
C1039
1
20%
4V
2 X6S
0402
10UF
10UF
NO STUFF
C1024
C1075
C1006
10UF
NO STUFF
1
CRITICAL
1
20%
2 4V
X6S
0402
10UF
20%
4V
2 X6S
0402
NO STUFF
1
1
20%
4V
2 X6S
0402
20%
4V
2 X6S
0402
C1088
C1020
10UF
10UF
10UF
NO STUFF
C1023
10UF
20%
4V
2 X6S
0402
1
1
C1074
NO STUFF
1
NO STUFF
NO STUFF
1
CRITICAL
C1087
20%
2 4V
X6S
0402
NO STUFF
C1022
C1073
20%
2 4V
X6S
0402
10UF
20%
4V
2 X6S
0402
NO STUFF
C
1
C1019
20%
4V
2 X6S
0402
10UF
NO STUFF
C1086
10UF
20%
4V
2 X6S
0402
1
20%
4V
2 X6S
0402
10UF
NO STUFF
C1072
C1005
10UF
NO STUFF
1
20%
4V
2 X6S
0402
20%
2 4V
X6S
0402
NO STUFF
C1085
C1018
NO STUFF
1
20%
4V
2 X6S
0402
10UF
10UF
20%
4V
2 X6S
0402
NO STUFF
1
NO STUFF
1
10UF
20%
4V
2 X6S
0402
C1017
C1004
10UF
CRITICAL
20%
4V
2 X6S
0402
C1071
CRITICAL
1
20%
4V
2 X6S
0402
10UF
NO STUFF
C1070
10UF
1
1
20%
4V
2 X6S
0402
NO STUFF
1
C1016
C1003
10UF
CRITICAL
10UF
20%
4V
2 X6S
0402
1
20%
4V
2 X6S
0402
CRITICAL
C1015
NO STUFF
C1002
10UF
20%
4V
2 X6S
0402
NO STUFF
1
1
10UF
20%
4V
2 X6S
0402
D
CRITICAL
C1001
NO STUFF
1
10UF
20%
2 4V
X6S
0402
NO STUFF
1
C108B
10UF
20%
2 4V
X6S
0402
C1065
NO STUFF
1
10UF
20%
4V
2 X6S
0402
NO STUFF
1
C108C
10UF
20%
2 4V
X6S
0402
C1066
NO STUFF
1
10UF
20%
4V
2 X6S
0402
NO STUFF
1
C108D
10UF
20%
4V
2 X6S
0402
C1067
NO STUFF NO STUFF
1
10UF
20%
4V
2 X6S
0402
NO STUFF
1
C108E
10UF
20%
4V
2 X6S
0402
C1068
1
10UF
20%
2 4V
X6S
0402
NO STUFF
1
C108F
10UF
20%
4V
2 X6S
0402
C1069
NO STUFF
1
10UF
20%
2 4V
X6S
0402
NO STUFF
1
C107A
10UF
20%
2 4V
X6S
0402
C1098
NO STUFF
1
C1099
NO STUFF
1
10UF
C109A
10UF
20%
4V
2 X6S
0402
20%
4V
2 X6S
0402
NO STUFF
1
C107B
10UF
20%
2 4V
X6S
0402
B
B
CRITICAL
1
C1031
470UF-0.0045OHM
20%
2 2.5V
POLY-TANT
SM
3
CPU VDDQ DECOUPLING
42 8
PPVMEMIO_S0_CPU
Intel recommendation (Table 5-4): 4x 2.2uF 0402, 6x 10uF 0603
Apple implementation
: 4x 2.2uF 0402, 6x 10uF 0402, 2x 270uF B2 no stuff
1
C1040
1
2.2UF
20%
2 6.3V
CERM
402-LF
1
1
2.2UF
C1050
1
C1051
10UF
20%
6.3V
2 CERM-X5R
0402-1
20%
6.3V
2 CERM-X5R
0402-1
C1042
1
2.2UF
20%
2 6.3V
CERM
402-LF
10UF
A
C1041
1
C1052
10UF
20%
6.3V
2 CERM-X5R
0402-1
C1043
2.2UF
20%
2 6.3V
CERM
402-LF
20%
2 6.3V
CERM
402-LF
1
C1053
10UF
20%
6.3V
2 CERM-X5R
0402-1
1
C1054
10UF
20%
6.3V
2 CERM-X5R
0402-1
1
C1055
10UF
20%
6.3V
2 CERM-X5R
0402-1
SYNC_MASTER=WILL_J43
SYNC_DATE=01/08/2013
PAGE TITLE
CPU Decoupling
DRAWING NUMBER
Apple Inc.
NO STUFF
1
1
C1060
270UF
8
C1061
270UF
20%
2 2V
TANT
CASE-B2-SM
7
20%
2 2V
TANT
CASE-B2-SM
R
2x Bulk nostuff per Harris Beach v1.0 schematic
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
10 OF 121
SHEET
10 OF 76
1
A
8
7
42 34 29 28 18 17 16 15 13 8
74 64 62 60 59 58 57
6
PCH VCCDSW3_3 BYPASS
(PCH 3.3V DSW PWR)
PP3V3_S5
5
4
PCH VCC3_3 BYPASS
(PCH 3.3V GPIO/LPC PWR)
61
PP3V3_S0
8
NO STUFF
51 42 38 27 17 16 15 11 8 6
64 62 59 58 55
74 65 64 62
36 30 27 18 17 15 13 12 11
59 56 45 44 43 42 41 40 39 38
3
PCH VCCASW BYPASS
(PCH 1.05V ME CORE PWR)
PP1V05_S0
C1212 1
C1250 1
10%
6.3V 2
CERM
402
BYPASS=U0500.AH10:6.35mm
20%
6.3V
X5R-CERM-1 2
603
BYPASS=U0500.V8:12.7mm
20%
6.3V
X5R-CERM-1 2
603
1UF
D
64 62 59 58 57 46 18 14 11 8
22UF
C1214 1
20%
10V
CERM 2
402
BYPASS=U0500.Y8:6.35mm
51 42 38 27 17 16 15 11 8 6
64 62 59 58 55
C1264 1
1UF
1UF
10%
2 6.3V
CERM
402
10%
6.3V 2
CERM
402
BYPASS=U0500.AG16:6.35mm
51 42 38 27 17 16 15 11 8 6
64 62 59 58 55
D
PCH VCCCLK BYPASS
(PCH 1.05V CLK PWR)
PP1V05_S0
0.1UF
C1255 1
1
10UF
PCH VCCSUS3_3 BYPASS
(PCH 3.3V SUSPEND PWR)
PP3V3_SUS
C1256
1
1UF
C1257
C1266 1 C1267 1
1UF
10%
2 6.3V
CERM
402
20%
6.3V 2
X5R
603
1UF
10%
2 6.3V
CERM
402
10%
6.3V 2
CERM
402
BYPASS=U0500.J11:12.7mm
BYPASS=U0500.J11:6.35mm
BYPASS=U0500.AE8:6.35mm
C1204 1
22UF
62 58 11 8
20%
6.3V
X5R-CERM-1 2
603
BYPASS=U0500.AC9:12.7mm
1UF
10%
6.3V 2
CERM
402
BYPASS=U0500.J17:6.35mm
BYPASS=U0500.R21:6.35mm
PCH VCCHSIO BYPASS
(PCH 1.05V PCIe/SATA/USB3 PWR)
PP1V05_S0SW_PCH_HSIO
C1260 1
C1261 1
1UF
64 62 59 58 57 46 18 14 11 8
C1251
PCH VCC BYPASS
(PCH 1.05V CORE PWR)
PP1V05_S0
20%
10V
CERM 2
402
BYPASS=U0500.K14:6.35mm
0.1UF
1
PCH VCCIO BYPASS
(PCH 1.05V USB2 PWR)
PP1V05_S0
BYPASS=U0500.AE9:12.7mm
BYPASS=U0500.AE9:6.35mm
74 65 64 62
36 30 27 18 17 15 13 12 11
59 56 45 44 43 42 41 40 39 38
C1202 1
1
22UF
PCH VCC3_3 BYPASS
(PCH 3.3V THERMAL PWR)
61
PP3V3_S0
8
NO STUFF
64 62 59 58 57 46 18 14 11 8
51 42 38 27 17 16 15 11 8 6
64 62 59 58 55
NO STUFF
C1200 1
PCH VCCSPI BYPASS
(PCH 3.3V SPI PWR)
PP3V3_SUS
2
1
1UF
10%
6.3V 2
CERM
402
PCH VCCSUS3_3 BYPASS
(PCH 3.3V SUSPEND RTC PWR)
PP3V3_SUS
C1262
10UF
10%
6.3V 2
CERM
402
20%
2 6.3V
CERM-X5R
0402-1
BYPASS=U0500.K9:6.35mm
BYPASS=U0500.L10:6.35mm
BYPASS=U0500.M9:6.35mm
C1206 1
1UF
10%
6.3V 2
CERM
402
BYPASS=U0500.AH11:6.35mm
C
C
CRITICAL
74 65 64 62 61
36 30 27 18 17 15 13 12 11 8
59 56 45 44 43 42 41 40 39 38
PCH VCCSDIO BYPASS
(PCH 3.3V/1.8V SDIO PWR)
PP3V3_S0
51 42 38 27 17 16 15 11 8 6
64 62 59 58 55
R1270
PP1V05_S0
??mA Max
1
0
2
C1208 1
L1270
2.2UH-240MA-0.221OHM
1
2
PP1V05_S0_PCH_VCCACLKPLL_R
MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
5%
1/16W
MF-LF
402
C1270
1
47UF
C1271 1
1
47UF
20%
4V
CERM-X5R 2
0805-1
10%
6.3V
CERM 2
402
BYPASS=U0500.U8:6.35mm
8 12
VOLTAGE=1.05V
0603
1UF
58 17 8
PCH VCCACLKPLL FILTER/BYPASS
(PCH 1.05V ACLK PLL PWR)
PP1V05_S0_PCH_VCCACLKPLL
MIN_LINE_WIDTH=0.2 MM
31mA Max
MIN_NECK_WIDTH=0.075 MM
C1272
1UF
10%
2 10V
X5R
402
20%
4V
CERM-X5R 2
0805-1
BYPASS=U0500.A20:12.7mm
BYPASS=U0500.A20:12.7mm
BYPASS=U0500.A20:6.35mm
CRITICAL
PCH VCCSUSHDA BYPASS
(PCH 3.3V/1.5V HDA PWR)
PP1V5_S0SW_AUDIO_HDA
1
0
C1210 1
1UF
10%
6.3V 2
CERM
402
BYPASS=U0500.AH14:6.35mm
2.2UH-240MA-0.221OHM
1
PP1V05_S0_PCH_VCC_ICC_R
2
MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
5%
1/16W
MF-LF
402
2
C1275
47UF
0
B
1
20%
4V
CERM-X5R 2
0805-1
C1276 1
1
47UF
C1277
1UF
10%
2 10V
X5R
402
20%
4V
CERM-X5R 2
0805-1
BYPASS=U0500.J18:12.7mm
BYPASS=U0500.J18:12.7mm
BYPASS=U0500.J18:6.35mm
2
5%
1/16W
MF-LF
402
8
VOLTAGE=1.05V
0603
R1280
1
PCH VCCCLK FILTER/BYPASS
(PCH 1.05V VCCCLK PWR)
PP1V05_S0_PCH_VCC_ICC
MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.075 MM
??mA Max
L1275
R1275
CRITICAL
NO STUFF
1
B
PCH OPI VCCAPLL FILTER/BYPASS
(PCH 1.05V OPI PLL PWR)
PP1V05_S0_PCH_VCCAPLL_OPI
8
MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.075 MM
57mA Max
L1280
2.2UH-240MA-0.221OHM
2
VOLTAGE=1.05V
0603
NO STUFF
NO STUFF
C1280
C1281
1
47UF
1
1
47UF
20%
4V
CERM-X5R 2
0805-1
C1282
1UF
10%
2 10V
X5R
402
20%
4V
CERM-X5R 2
0805-1
BYPASS=U0500.AA21:12.7mm
BYPASS=U0500.AA21:12.7mm
BYPASS=U0500.AA21:6.35mm
CRITICAL
PCH VCCSATA3PLL FILTER/BYPASS
(PCH 1.05V SATA3 PLL PWR)
PP1V05_S0SW_PCH_VCCSATA3PLL 8
MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.075 MM
42mA Max
L1290
62 58 11 8
2.2UH-240MA-0.221OHM
PP1V05_S0SW_PCH_HSIO
83mA Max
1
2
0603
C1290
1
C1291
47UF
1
1
47UF
20%
4V
CERM-X5R 2
0805-1
12
VOLTAGE=1.05V
NO STUFF
C1292
1UF
10%
2 10V
X5R
402
20%
4V
CERM-X5R 2
0805-1
BYPASS=U0500.B11:12.7mm
BYPASS=U0500.B11:12.7mm
BYPASS=U0500.B11:6.35mm
A
CRITICAL
PCH VCCUSB3PLL FILTER/BYPASS
(PCH 1.05V USB3 PLL PWR)
PP1V05_S0SW_PCH_VCCUSB3PLL
MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.075 MM
41mA Max
L1295
2.2UH-240MA-0.221OHM
1
2
0603
47UF
1
20%
4V
CERM-X5R 2
0805-1
7
PCH Decoupling
1
1
DRAWING NUMBER
47UF
Apple Inc.
C1297
1UF
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
R
10%
2 10V
X5R
402
20%
4V
CERM-X5R 2
0805-1
BYPASS=U0500.B18:12.7mm
BYPASS=U0500.B18:12.7mm
BYPASS=U0500.B18:6.35mm
LPT-LP current estimates from Lynx Point-LP PCH EDS, doc #503118, v1.0
as well as from clarification email, from Srini, dated 9/10/2012 2:11pm.
8
C1296
SYNC_DATE=02/07/2013
PAGE TITLE
VOLTAGE=1.05V
NO STUFF
C1295
SYNC_MASTER=J41_MLB
8 14
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
12 OF 121
SHEET
11 OF 76
1
A
8
7
6
5
4
3
2
1
PPVRTC_G3H
CRITICAL
OMIT_TABLE
1
R1301
20K
330K
RTCX1
RTCX2
AU6
INTRUDER*
1M
5%
1/20W
MF
201 2
5%
1/20W
MF
2 201
AW5
AY5
PCH_INTRUDER_L
20K
5%
1/20W
MF
201 2
17
PCH_CLK32K_RTCX1
NC_RTC_CLK32K_RTCX2
IN
17
5%
1/20W
MF
2 201
OUT
PCH_INTVRMEN
C1300 1
1
1UF
C1303
1UF
10%
10V 2
X5R
402
69 65 61
10%
2 10V
X5R
402
OUT
INTVRMEN
AV6
AU7
HDA_BIT_CLK
R1310
33
1
2
1
2
1
2
69
69 65 61
OUT
HDA_SYNC
R1311
69 65 61
OUT
HDA_RST_L
R1312
33
69
R1313
HDA_SYNC_R
69
AU8
HDA_RST_R_L
5% 1/20W MF
201
PLACE_NEAR=U0500.AU8:1.27mm
IN
64
HDA_SDOUT
AV11
5% 1/20W MF
201
PLACE_NEAR=U0500.AV11:1.27mm
69 65 61
OUT
AW8
HDA_BIT_CLK_R
5% 1/20W MF
201
PLACE_NEAR=U0500.AW8:1.27mm
33
69 65 61
BGA-TSP
SYM 5 OF 19
SATA_RN0/PERN6_L3 J5
SATA_RP0/PERP6_L3 H5
SRTCRST*
RTC_RESET_L
D
AV7
PCH_SRTCRST_L
U0500
HASWELL-ULT
2C+GT2
33
1
2
69 17
AY10
AU12
HDA_SDIN0
NC_HDA_SDIN1
AU11
HDA_SDOUT_R
5% 1/20W MF
201
PLACE_NEAR=U0500.AU11:1.27mm
AW10
AV10
TP_PCH_I2S1_TXD
TP_PCH_I2S1_SFRM
67 64 16 6
69 64 16
PCIE_SSD_R2D_C_N & lt; 3 & gt;
PCIE_SSD_R2D_C_P & lt; 3 & gt;
SATA_RN1/PERN6_L2 J8
SATA_RP1/PERP6_L2 H8
PCIE_SSD_D2R_N & lt; 2 & gt;
PCIE_SSD_D2R_P & lt; 2 & gt;
SATA_TN1/PETN6_L2 A17
SATA_TP1/PETP6_L2 B17
PCIE_SSD_R2D_C_N & lt; 2 & gt;
PCIE_SSD_R2D_C_P & lt; 2 & gt;
SATA_RN2/PERN6_L1 J6
SATA_RP2/PERP6_L1 H6
PCIE_SSD_D2R_N & lt; 1 & gt;
PCIE_SSD_D2R_P & lt; 1 & gt;
SATA_TN2/PETN6_L1 B14
SATA_TP2/PETP6_L1 C15
PCIE_SSD_R2D_C_N & lt; 1 & gt;
PCIE_SSD_R2D_C_P & lt; 1 & gt;
SATA_RN3/PERN6_L0 F5
SATA_RP3/PERP6_L0 E5
PCIE_SSD_D2R_N & lt; 0 & gt;
PCIE_SSD_D2R_P & lt; 0 & gt;
SATA_TN3/PETN6_L0 C17
SATA_TP3/PETP6_L0 D17
PCIE_SSD_R2D_C_N & lt; 0 & gt;
PCIE_SSD_R2D_C_P & lt; 0 & gt;
V1
U1
V6
AC1
XDP_SSD_PCIE3_SEL_L
XDP_SSD_PCIE2_SEL_L
XDP_SSD_PCIE1_SEL_L
XDP_SSD_PCIE0_SEL_L
HDA_BCLK/I2S0_SCLK
HDA_SYNC/I2S0_SFRM
(IPD-PLTRST#)
HDA_RST*/I2S_MCLK
HDA_SDI0/I2S0_RXD
HDA_SDI1/I2S1_RXD
(IPD)
HDA_SDO/I2S0_TXD
(IPD-PLTRST#)
HDA_DOCK_EN*/I2S1_TXD
HDA_DOCK_RST*/I2S1_SFRM
IN
XDP_CPUPCH_TRST_L
AU62
IN
XDP_PCH_TCK
AE62
SATA0GP/GPIO34
SATA1GP/GPIO35
SATA2GP/GPIO36
SATA3GP/GPIO37
(IPU)
PCH_TRST*
PCH_TCK (IPD)
PCH_TDI (IPU)
30 67
OUT
30 67
IN
D
30 64 67
IN
30 64 67
SSD Lane 2
Unused
SSD Lane 0
Secondary HDD/SSD
30 67
OUT
Reserved: ODD
SSD Lane 1
OUT
30 67
IN
30 64 67
IN
30 64 67
OUT
30 67
OUT
30 67
IN
30 64 67
IN
30 64 67
OUT
30 67
OUT
30 67
IN
16
IN
16
IN
16
IN
16
PCH_TDO
69 64 16
IN
XDP_PCH_TDI
69 64 16
OUT
XDP_PCH_TDO
AE61
XDP_PCH_TMS
AD62
PCH_TMS (IPU)
AL11
RSVD
AC4
RSVD
IN
C
NC
NC
16
30 64 67
OUT
I2S1_SCLK
AD61
69 64 16
Primary HDD/SSD
30 64 67
IN
SATA Port assignments:
SSD Lane 3
IN
RTCRST*
AY8
TP_PCH_I2S1_SCLK
PCIe Port assignments:
PCIE_SSD_D2R_N & lt; 3 & gt;
PCIE_SSD_D2R_P & lt; 3 & gt;
SATA_TN0/PETN6_L3 B15
SATA_TP0/PETP6_L3 A15
RTC
R1303
AUDIO
R13021
1
SATA
R13001
BI
AE63
PCH_JTAGX
NC
AV2
SATA_IREF A12
JTAG
64 62 17 13 8
PP1V05_S0SW_PCH_VCCSATA3PLL
JTAGX
NC
SATALED* U3
RSVD
R1370
NC
RSVD K10
SATA_RCOMP C12
8 11
1
RSVD L11
3.01K
C
1%
1/20W
MF
2 201
PLACE_NEAR=U0500.C12:2.54mm
PCH_SATA_RCOMP
PCH_SATALED_L
12
CRITICAL
OMIT_TABLE
U0500
HASWELL-ULT
2C+GT2
TP_PCIE_CLK100M_ENETSDN
TP_PCIE_CLK100M_ENETSDP
12
69 32
OUT
69 32
OUT
31 12
IN
U2
ENETSD_CLKREQ_L
B41
A41
PCIE_CLK100M_CAMERA_N
PCIE_CLK100M_CAMERA_P
Y5
CAMERA_CLKREQ_L
CLKOUT_PCIE_N0
CLKOUT_PCIE_P0
PCIECLKRQ0*/GPIO18
CLKOUT_PCIE_N1
CLKOUT_PCIE_P1
OUT
69 64 29
OUT
PCIE_CLK100M_AP_N
PCIE_CLK100M_AP_P
C41
B42
IN
AP_CLKREQ_L
AD1
PCIECLKRQ2*/GPIO20
64
NC_PCIE_CLK100M_FWN
NC_PCIE_CLK100M_FWP
B38
C37
CLKOUT_PCIE_N3
CLKOUT_PCIE_P3
12
FW_CLKREQ_L
29 12
64
69 25
OUT
69 25
OUT
27 12
IN
N1
A39
B39
PCIE_CLK100M_TBT_N
PCIE_CLK100M_TBT_P
U5
TBT_CLKREQ_L
67 64 30
OUT
67 64 30
OUT
IN
B37
A37
PCIE_CLK100M_SSD_N
PCIE_CLK100M_SSD_P
SSD_CLKREQ_L
30 12
T2
XTAL24_IN A25
XTAL24_OUT B25
PCH_CLK24M_XTALIN
PCH_CLK24M_XTALOUT
CLKOUT_PCIE_N2
CLKOUT_PCIE_P2
IN
17
OUT
17
PP1V05_S0_PCH_VCCACLKPLL
RSVD K21
RSVD M21
DIFFCLK_BIASREF C26
TESTLOW
TESTLOW
TESTLOW
TESTLOW
C35
C34
AK8
AL8
R1380
NC
NC
3.01K
1%
1/20W
MF
2 201
PLACE_NEAR=U0500.C26:2.54mm
B
PCH_DIFFCLK_BIASREF
PCH_TESTLOW_C35
PCH_TESTLOW_C34
PCH_TESTLOW_AK8
PCH_TESTLOW_AL8
R1390
R1391
R1392
R1393
LPC_CLK24M_SMC_R
OUT
17 69
LPC_CLK24M_LPCPLUS_R
OUT
17 69
PCIECLKRQ3*/GPIO21
CLKOUT_PCIE_N4
CLKOUT_PCIE_P4
PCIECLKRQ4*/GPIO22
CLKOUT_PCIE_N5
CLKOUT_PCIE_P5
CLKOUT_LPC_0 AN15
CLKOUT_LPC_1 AP15
(IPD-PWROK)
CLKOUT_ITPXDP_N B35
CLKOUT_ITPXDP_P A35
8 11
1
PCIECLKRQ1*/GPIO19
69 64 29
B
CLOCK SIGNALS
BGA-TSP
SYM 6 OF 19
C43
C42
10K
10K
10K
10K
1
1
1
1
2
2
2
2
5%
5%
5%
5%
1/20W
1/20W
1/20W
1/20W
MF
MF
MF
MF
201
201
201
201
TP_ITPXDP_CLK100MN
TP_ITPXDP_CLK100MP
PCIECLKRQ5*/GPIO23
A
SYNC_MASTER=J41_MLB
SYNC_DATE=02/06/2013
PAGE TITLE
PP3V3_S0
R1375
R1340
R1341
R1342
R1343
R1344
R1345
100K
1
8
1
1
1
1
1
1
2
2
2
2
2
2
DRAWING NUMBER
PCH_SATALED_L
2
5%
100K
100K
100K
100K
100K
100K
PCH Audio/JTAG/SATA/CLK
64 65 74
8 11 13 15 17 18 27 30 36 38 39
40 41 42 43 44 45 56 59 61 62
1/20W
MF
201
5%
5%
5%
5%
5%
5%
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
MF
MF
MF
MF
MF
MF
201
201
201
201
201
201
ENETSD_CLKREQ_L
CAMERA_CLKREQ_L
AP_CLKREQ_L
FW_CLKREQ_L
TBT_CLKREQ_L
SSD_CLKREQ_L
7
Apple Inc.
12
R
& lt; E4LABEL & gt;
12
NOTICE OF PROPRIETARY PROPERTY:
12 31
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
12 29
12
12 27
12 30
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
BRANCH
& lt; BRANCH & gt;
PAGE
13 OF 121
SHEET
12 OF 76
1
A
8
7
6
5
4
3
2
CRITICAL
OMIT_TABLE
PPVRTC_G3H
U0500
R1450
330K
5%
1/20W
MF
2 201
BGA-TSP
SYM 8 OF 19
R1400 kept for debug purposes.
39
AK2
IN
PM_SYSRST_L
AC3
SYS_RESET*
37 17 16
IN
PM_PCH_SYS_PWROK
AG2
SYS_PWROK
17 13
IN
PM_PCH_PWROK
AY7
IN
PM_PCH_PWROK
AB5
APWROK
OUT
PLT_RESET_L
AG7
PLTRST*
SUSCLK/GPIO62 AE6
IN
PM_RSMRST_L
AW6
RSMRST*
SLP_S5*/GPIO63 AP5
PCH_SUSWARN_L
AV4
SUSWARN*/SUSPWRDNACK/GPIO30
SLP_S4* AJ6
SLP_S3* AT4
64 37 17
NO STUFF
SLP_S0# Isolation
74 65 64 62 61
36 30 27 18 17 15 13 12 11 8
59 56 45 44 43 42 41 40 39 38
R14001
0
PP3V3_S0
5%
1/20W
MF
0201 2
1
17 13
18 16 15
C1420
0.1UF
64 59
10%
10V
0201
2 X5R-CERM
39
OUT
PM_SLP_S0_L
4
CLKRUN*/GPIO32 V5
PCH_PWROK
SUS_STAT*/GPIO61 AG4
PM_DSW_PWRGD
IN
PCIE_WAKE_L
IN
PM_CLKRUN_L
BI
13 29 31 64
13 37 46 64
37
1
R1451
100K
5%
1/20W
MF
2 201
LPC_PWRDWN_L
OUT
37 46 64
PM_CLK32K_SUSCLK_R
OUT
38 69
PM_SLP_S5_L
OUT
13 37 59
PM_SLP_S4_L
OUT
13 18 29 36 37 59
PM_SLP_S3_L
OUT
13 17 18 37 59
OUT
13 42 59
IN
PM_PWRBTN_L
AL7
PWRBTN* (IPU)
38 37
74LVC1G08 6
SOT891
OUT
DPWROK AV5
(IPD-DeepSx) WAKE* AJ5
D
PCH_DSWVRMEN
37 16 13
IN
SMC_ADAPTER_EN
AJ8
37 13
CRITICAL
37 18 13
SYSTEM POWER MANAGEMENT
SUSACK* (IPU)
DSWVRMEN AW7
PCH_SUSACK_L
IN
8 12 17 62 64
1
HASWELL-ULT
2C+GT2
D
1
IN
SLP_SUS* AP4
PM_SLP_SUS_L
SLP_LAN* AJ7
TP_PCH_SLP_LAN_L
PM_BATLOW_L
AN4
PCH_PM_SLP_S0_L
AF3
SLP_S0*
TP_PCH_SLP_WLAN_L
2
U1420 1
08
AM5
SLP_A* AL5
ACPRESENT/GPIO31
(IPD-DeepSx)
BATLOW*/GPIO72
TP_PM_SLP_A_L
SLP_WLAN*/GPIO29
NC
3
5
NC
SLP_S0# can be driven high outside of S0
U1420 ensures signal will only be high in S0.
CRITICAL
OMIT_TABLE
U0500
C
C
HASWELL-ULT
2C+GT2
56
OUT
EDP_BKLT_PWM
B8
EDP_BKLCTL
56 13
OUT
EDP_BKLT_EN
A9
EDP_BKLEN
27 25 13
IN
37 13
IN
64 13
IN
64 13
IN
64
64 13
OUT
28 13
OUT
64 13
OUT
65 61 59 13
OUT
64 13
OUT
EDP_PANEL_PWR
EDP_VDDEN
TBT_EN_CIO_PWR_L
SMC_RUNTIME_SCI_L
AUD_IP_PERIPHERAL_DET
AUD_I2C_INT_L
U6
P4
N4
N2
PIRQA*/GPIO77
PIRQB*/GPIO78
PIRQC*/GPIO79
PIRQD*/GPIO80
NC_PCI_PME_L
ODD_PWR_EN_L
DP_AUXCH_ISOL_L
ENET_LOW_PWR
AUD_PWR_EN
AUD_IPHS_SWITCH_EN
AD4
U7
L1
L3
R5
L4
PME* (IPU)
GPIO55
GPIO52
GPIO54
GPIO51
GPIO53
DDPB_CTRLCLK
DDPB_CTRLDATA
(IPD-PLTRST#)
DDPC_CTRLCLK
DDPC_CTRLDATA
(IPD-PLTRST#)
DISPLAY
OUT
PCI
60 13
C6
eDP
SIDEBAND
BGA-TSP
SYM 9 OF 19
B9
C9
DP_TBTSNK0_DDC_CLK
DP_TBTSNK0_DDC_DATA
OUT
D9
D11
DP_TBTSNK1_DDC_CLK
DP_TBTSNK1_DDC_DATA
OUT
BI
18 28
18 28
18
BI
18
DDPB_AUXN C5
DDPC_AUXN B6
DP_TBTSNK0_AUXCH_C_N
DP_TBTSNK1_AUXCH_C_N
BI
25 67
BI
18 25 67
DDPB_AUXP B5
DDPC_AUXP A6
DP_TBTSNK0_AUXCH_C_P
DP_TBTSNK1_AUXCH_C_P
BI
25 67
BI
18 25 67
DDPB_HPD C8
DP_TBTSNK0_HPD
IN
25
DDPC_HPD A8
DP_TBTSNK1_HPD
IN
18 25
DP_INT_HPD
IN
60
EDP_HPD D6
B
B
PP3V3_S5
PP3V3_S0
A
R1405
R1410
R1452
R1455
R1460
R1461
R1462
R1463
R1464
R1430
R1431
R1440
R1441
R1442
R1443
R1445
R1446
R1447
R1448
R1449
8
8 11 15 16 17 18 28 29 34 42 57
58 59 60 62 64 74
62 64 65 74
8 11 12 13 15 17 18 27 30 36 38
39 40 41 42 43 44 45 56 59 61
1K
1
2
10K
1
2
PM_PWRBTN_L
5%
1
1
1/20W
MF
201
PM_BATLOW_L
1
2
1
2
1
2
1
2
MF
MF
201
1
100K
10K
100K
100K
1
1
1
1
100K
100K
100K
100K
100K
1
1
1
1
1
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
1/20W
MF
5%
1/20W
MF
201
1/20W
MF
13 37 59
201
2
2
PM_SLP_S5_L
PM_SLP_S4_L
PM_SLP_S3_L
PM_SLP_S0_L
PM_SLP_SUS_L
201
5%
1
5%
5%
100K
100K
13 37 46 64
201
1/20W
2
1
1/20W
5%
13 29 31 64
PM_CLKRUN_L
5%
13 37
PCIE_WAKE_L
2
100K
100K
100K
100K
100K
13 16 37
201
2
10K
MF
5%
10K
1/20W
2
2 5%
2 5%
2 5%
5%
2
2 5%
2 5%
2 5%
2 5%
5%
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
MF
MF
MF
MF
MF
MF
MF
MF
MF
201
201
201
201
201
201
201
201
201
EDP_BKLT_EN
EDP_PANEL_PWR
TBT_EN_CIO_PWR_L
SMC_RUNTIME_SCI_L
AUD_IP_PERIPHERAL_DET
AUD_I2C_INT_L
ODD_PWR_EN_L
DP_AUXCH_ISOL_L
ENET_LOW_PWR
AUD_PWR_EN
AUD_IPHS_SWITCH_EN
7
13 18 29 36 37 59
13 17 18 37 59
13 18 37
13 42 59
13 56
13 60
SYNC_MASTER=J41_MLB
13 25 27
SYNC_DATE=02/06/2013
PAGE TITLE
PCH PM/PCI/GFX
13 37
13 64
DRAWING NUMBER
13 64
Apple Inc.
13 64
R
& lt; E4LABEL & gt;
13 28
NOTICE OF PROPRIETARY PROPERTY:
13 64
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
13 59 61 65
13 64
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
BRANCH
& lt; BRANCH & gt;
PAGE
14 OF 121
SHEET
13 OF 76
1
A
8
7
6
5
4
CRITICAL
OMIT_TABLE
PCIe Port Assignments:
69 25
PCIE_TBT_D2R_N & lt; 0 & gt;
PCIE_TBT_D2R_P & lt; 0 & gt;
IN
Thunderbolt lane 0
69 25
OUT
69 25
OUT
69 25
IN
69 25
OUT
Thunderbolt lane 1
69 25
69 25
OUT
Thunderbolt lane 3
69 64 29
IN
69 64 29
IN
AirPort
69 29
OUT
69 29
OUT
64
64
Reserved: FireWire
64
64
68 65 34
C
68 65 34
SD Card Reader
( & Ethernet if combo)
IN
IN
68 65 34
OUT
68 65 34
OUT
69 32
IN
69 32
IN
Camera
69 32
11 8
OUT
69 32
OUT
PP1V05_S0SW_PCH_VCCUSB3PLL
B22
A21
PETN5_L3
PETP5_L3
G11
F11
PERN3
PERP3
C29
B30
PETN3
PETP3
NC_PCIE_FW_D2RN
NC_PCIE_FW_D2RP
F13
G13
PERN4
PERP4
NC_PCIE_FW_R2D_CN
NC_PCIE_FW_R2D_CP
B29
A29
PETN4
PETP4
G17
F17
PERN1/USB3RN2
PERP1/USB3RP2
USB2N1 AR7
USB2P1 AT7
USB_EXTB_N
USB_EXTB_P
BI
61 65 68
BI
61 65 68
USB_BT_N
USB_BT_P
BI
29 68
BI
29 68
NC_USB_IRN
NC_USB_IRP
BI
64
BI
64
USB_TPAD_N
USB_TPAD_P
BI
36 64 68
BI
36 64 68
TP_USB_5N
TP_USB_5P
NC_USB_CAMERAN
NC_USB_CAMERAP
NC_USB_SDN
NC_USB_SDP
PCIE_CAMERA_R2D_C_N
PCIE_CAMERA_R2D_C_P
USB3_EXTB_D2R_N
USB3_EXTB_D2R_P
USB3TN1 B33
USB3TP1 A33
PERN2/USB3RN3
PERP2/USB3RP3
B31
A31
Ext B (LS/FS/HS)
BT
D
IR
Trackpad
Unused
64
Reserved: Camera
64
64
Reserved: SD (HS)
64
USB3_EXTB_R2D_C_N
USB3_EXTB_R2D_C_P
IN
35 68
IN
35 68
OUT
35 68
OUT
35 68
Ext A (SS)
IN
61 65 68
IN
61 65 68
OUT
61 65 68
OUT
61 65 68
Ext B (SS)
C
PETN1/USB3TN2
PETP1/USB3TP2
F15
G15
USB3_EXTA_R2D_C_N
USB3_EXTA_R2D_C_P
USB3RN1 E18
USB3RP1 F18
PCIE_CAMERA_D2R_N
PCIE_CAMERA_D2R_P
USB3_EXTA_D2R_N
USB3_EXTA_D2R_P
USB3TN0 C33
USB3TP0 B34
C30
C31
Ext A (LS/FS/HS)
USB3 Port Assignments:
USB3RN0 G20
USB3RP0 H20
USB3_SD_R2D_C_N
USB3_SD_R2D_C_P
1
35 68
USB2N7 AR13
USB2P7 AP13
(IPD)
PERN5_L3
PERP5_L3
USB3_SD_D2R_N
USB3_SD_D2R_P
OUT
69 25
E6
F6
BI
USB2N6 AP11
USB2P6 AN11
PETN5_L2
PETP5_L2
PCIE_TBT_D2R_N & lt; 3 & gt;
PCIE_TBT_D2R_P & lt; 3 & gt;
IN
69 25
B21
C21
35 68
USB2N5 AM13
USB2P5 AN13
PERN5_L2
PERP5_L2
PCIE_AP_R2D_C_N
PCIE_AP_R2D_C_P
IN
Thunderbolt lane 2
H10
G10
PCIE_AP_D2R_N
PCIE_AP_D2R_P
OUT
69 25
PETN5_L1
PETP5_L1
PCIE_TBT_R2D_C_N & lt; 3 & gt;
PCIE_TBT_R2D_C_P & lt; 3 & gt;
OUT
69 25
B23
A23
PCIE_TBT_R2D_C_N & lt; 2 & gt;
PCIE_TBT_R2D_C_P & lt; 2 & gt;
IN
69 25
PERN5_L1
PERP5_L1
BI
USB2N4 AM15
USB2P4 AL15
PETN5_L0
PETP5_L0
USB_EXTA_N
USB_EXTA_P
USB2N3 AR10
USB2P3 AT10
BGA-TSP
SYM 11 OF 19
2
USB Port Assignments:
USB2N0 AN8
USB2P0 AM8
USB2N2 AR8
USB2P2 AP8
HASWELL-ULT
2C+GT2
PCIE_TBT_D2R_N & lt; 2 & gt;
PCIE_TBT_D2R_P & lt; 2 & gt;
IN
69 25
U0500
PERN5_L0
PERP5_L0
F8
E8
PCIE_TBT_R2D_C_N & lt; 1 & gt;
PCIE_TBT_R2D_C_P & lt; 1 & gt;
OUT
69 25
C23
C22
PCIE_TBT_D2R_N & lt; 1 & gt;
PCIE_TBT_D2R_P & lt; 1 & gt;
IN
69 25
F10
E10
PCIE_TBT_R2D_C_N & lt; 0 & gt;
PCIE_TBT_R2D_C_P & lt; 0 & gt;
IN
PCI-E
USB
69 25
D
3
PCH_PCIE_RCOMP
NC
NC
E15
E13
A27
B27
USBRBIAS* AJ10
USBRBIAS AJ11
RSVD AN10
RSVD AM10
PETN2/USB3TN3
PETP2/USB3TP3
RSVD
RSVD
PCIE_RCOMP
PCIE_IREF
OC0*/GPIO40
OC1*/GPIO41
OC2*/GPIO42
OC3*/GPIO43
AL3
AT1
AH2
AV3
68
PCH_USB_RBIAS
PLACE_NEAR=U0500.AJ10:2.54mm
1
R1570
22.6
NC
NC
XDP_USB_EXTA_OC_L
XDP_USB_EXTB_OC_L
XDP_USB_EXTC_OC_L
XDP_USB_EXTD_OC_L
1%
1/20W
MF
2 201
IN
14 16 35
IN
14 16 61 65
IN
14 16
IN
14 16
1
R1500
3.01K
1%
1/20W
MF
CRITICAL
OMIT_TABLE
201
PLACE_NEAR=U0500.A27:2.54mm 2
U0500
HASWELL-ULT
2C+GT2
BGA-TSP
BI
69 64 46 37
BI
OUT
LPC_FRAME_L
69 64 46 37
33
33
33
33
1
1
1
1
33
1
2
2 5%
2 5%
5%
2
5%
2
5%
1/20W
MF
MF
MF
MF
201
201
201
201
MF
AU14
AW12
AY12
AW11
LPC_FRAME_R_L
1/20W
1/20W
1/20W
1/20W
LPC_AD_R & lt; 0 & gt;
LPC_AD_R & lt; 1 & gt;
LPC_AD_R & lt; 2 & gt;
LPC_AD_R & lt; 3 & gt;
AV12
201
69 46
OUT
SPI_CLK_R
69 46
OUT
SPI_CS0_R_L
AA3
Y7
TP_SPI_CS1_L
TP_SPI_CS2_L
69 46
BI
69 46
Y4
AC2
SPI_MOSI_R
AA2
AA4
PP3V3_SUS
PP3V3_SUS
SPI_MISO
BI
SPI_IO & lt; 2 & gt;
Y6
14
A
BI
14
BI
SPI_IO & lt; 3 & gt;
AF1
(IPU)
LAD0
LAD1
LAD2
LAD3
SYM 7 OF 19
SMBALERT*/GPIO11 AN2
LFRAME*
SPI_CLK
(IPU)
SPI_CS0*
(IPU)
SPI_CS1*
(IPU)
SPI_CS2*
(IPU)
SPI_MOSI
(IPU/IPD)
SPI_MISO
(IPU)
SPI_IO2
(IPU)
SPI_IO3
(IPU)
PCH_SMBALERT_L
SMBCLK AP2
SMBDATA AH1
LPC
69 64 46 37
R1540
R1541
R1542
R1543
R1544
SMBUS
BI
LPC_AD & lt; 0 & gt;
LPC_AD & lt; 1 & gt;
LPC_AD & lt; 2 & gt;
LPC_AD & lt; 3 & gt;
SMBUS_PCH_CLK
SMBUS_PCH_DATA
SML0ALERT*/GPIO60 AL2
SML0CLK AN1
SML0DATA AK1
SML1ALERT*/PCHHOT*/GPIO73 AU4
SML1CLK_GPIO75 AU3
SML1DATA/GPIO74 AH3
SPI
69 64 46 37
B
BI
(IPU/IPD) CL_CLK AF2
C-LINK
69 64 46 37
(IPU/IPD) CL_DATA AD2
CL_RST* AF4
WOL_EN
SML_PCH_0_CLK
SML_PCH_0_DATA
PCH_SML1ALERT_L
14
OUT
BI
16 19 25 40 56 69
B
16 19 25 40 56 69
OUT
14 64
OUT
40 69
BI
OUT
SMBUS_SMC_1_S0_SCLOUT
SMBUS_SMC_1_S0_SDA BI
NC_CLINK_CLK
32 37 40 43 44 64 69 73
32 37 40 43 44 64 69 73
64
NC_CLINK_RESET_L
SML1ALERT# pull-up not provided on this
page, may be wire-ORed into other signals.
Otherwise, 100k pull-up to 3.3V SUS required.
64
NC_CLINK_DATA
40 69
39
64
8 11 14 18 46 57 58 59 62 64
8 11 14 18 46 57 58 59 62 64
SYNC_MASTER=J41_MLB
R1580
R1581
R1582
R1583
R1548
R1549
R1590
R1591
8
100K
100K
100K
100K
1K
1K
100K
100K
1
1
1
1
1
1
1
1
2
2 5%
2 5%
5%
2
5%
2
2 5%
5%
2
2 5%
5%
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
MF
MF
MF
MF
MF
MF
MF
MF
201
201
201
201
201
201
201
201
XDP_USB_EXTA_OC_L
XDP_USB_EXTB_OC_L
XDP_USB_EXTC_OC_L
XDP_USB_EXTD_OC_L
SPI_IO & lt; 2 & gt;
SPI_IO & lt; 3 & gt;
PCH_SMBALERT_L
WOL_EN
7
SYNC_DATE=02/06/2013
PAGE TITLE
14 16 35
PCH PCIe/USB/LPC/SPI/SMBus
14 16 61 65
DRAWING NUMBER
14 16
14 16
Apple Inc.
14
R
14
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
14
14 64
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
15 OF 121
SHEET
14 OF 76
1
A
8
7
6
5
4
3
2
1
TABLE_BOMGROUP_HEAD
BOM GROUP
BOM OPTIONS
RAMCFG_SLOT
RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:H
55 51 42 38 27 17 16 11 8 6
64 62 59 58
TABLE_BOMGROUP_ITEM
RAMCFG3:H
R16311
100K
5%
1/20W
MF
201 2
R16501
62 64 65 74
8 11 12 13 15 17 18 27 30 36 38
39 40 41 42 43 44 45 56 59 61
RAMCFG2:H
RAMCFG1:H
1
RAMCFG0:H
R16351
R1636
100K
100K
5%
1/20W
MF
2 201
1K
5%
1/20W
MF
201 2
1
R1611
U0500
100K
THRMTRIP* D60
HASWELL-ULT
2C+GT2
5%
1/20W
MF
2 201
XDP_MLB_RAMCFG0
XDP_MLB_RAMCFG1
XDP_MLB_RAMCFG2
XDP_MLB_RAMCFG3
D
5%
1/20W
MF
201 2
CRITICAL
OMIT_TABLE
16 15
15 16 18
18 16 15
15 16 18
BI
XDP_MLB_RAMCFG0
AU2
BI
TBT_GO2SX_BIDIR
AM7
LAN_PHY_PWR_CTRL/GPIO12
OUT
TP_MEM_VDD_SEL_1V5_L
AD6
15 16 18
18
GPIO12:
BI
XDP_LPCPLUS_GPIO
64 46 16 15
CR:
TBT_GO2SX_BIDIR,
requires 100k pull-up to SUS
RR/FR: DPHDMIMUX_SEL_TBT, requires 100k pull-up to TBTLC
PM_THRMTRIP_L
38 67
IN
18 25
LPC_SERIRQ
SERIRQ T4
PCH_OPI_COMP AW15
OUT
TBT_CIO_PLUG_EVENT
RCIN*/GPIO82 V4
BI
15 37 46 64
D
PCH_OPI_COMP
GPIO8
Y1
GPIO16
RSVD AF20
RSVD AB21
GSPI0_CS*/GPIO83 R6
PLACE_NEAR=U0500.AW15:2.54mm
1
NC
NC
R1655
49.9
PCH_GSPI0_CS_L
1%
1/20W
MF
2 201
15
IN
16 15
IN
XDP_PCH_GPIO17
T3
GPIO17
GSPI0_CLK/GPIO84 L6
34 15
18 16 15 13
OUT
SD_RESET_L
AD5
GPIO24
37 15
IN
SMC_WAKE_SCI_L
AN5
GPIO27 (IPD-DeepSx)
GSPI0_MISO/GPIO85 N6
(IPD)
GSPI0_MOSI/GPIO86 L8
(IPD-PLTRST#)
36 15
IN
TPAD_SPI_INT_L
AD7
GPIO28
GSPI1_CS*/GPIO87 R7
TPAD_SPI_CS_L
OUT
36 15
OUT
TPAD_USB_IF_EN
AN3
GPIO26
GSPI1_CLK/GPIO88 L5
TPAD_SPI_CLK
OUT
15 36 68
TPAD_SPI_MISO
IN
15 36 68
TPAD_SPI_MOSI
OUT
15 36 68
PLT_RESET_L
R16211
100K
5%
1/20W
MF
201 2
27 18
64 59 58 30 15
OUT
SSD_PWR_EN
AG6
GPIO56
PCH_TBT_PCIE_RESET_L
OUT
64 15
33 16 15
34 15
OUT
AP1
GPIO57
HDD_PWR_EN
AL4
GSPI1_MISO/GPIO89 N7
(IPD)
GSPI_MOSI/GPIO90 K2
PCH_GSPI0_CLK
15
PCH_GSPI0_MISO
15
PCH_GSPI0_MOSI
15
BI
XDP_SDCONN_STATE_CHANGE_L
AT5
OUT
SD_PWR_EN
AK4
AB6
UART0_RXD/GPIO91 J1
GPIO47
GPIO59
GPIO44
UART0_TXD/GPIO92 K3
AP_S0IX_WAKE_L
IN
IN
IN
15 18 25
UART0_CTS*/GPIO94 G1
AP_RESET_L
TBT_PWR_EN
OUT
XDP_JTAG_ISP_TCK
U4
GPIO48
OUT
XDP_JTAG_ISP_TDI
Y3
GPIO49
OUT
JTAG_TBT_TMS
P3
GPIO50
OUT
PCH_HSIO_PWR_EN
Y2
HSIOPC/GPIO71
UART1_RST*/GPIO2 J3
GPIO13
UART1_CTS*/GPIO3 J4
PCH_UART1_CTS_L
I2C0_SDA/GPIO4 F2
PCH_I2C0_SDA
15
GPIO25
I2C0_SCL/GPIO5 F3
PCH_I2C0_SCL
15
I2C1_SDA/GPIO6 G4
PCH_I2C1_SDA
15
I2C1_SCL/GPIO7 F1
PCH_I2C1_SCL
15
TPAD_SPI_IF_EN
18 16 15
BI
XDP_MLB_RAMCFG3
AH4
64 46 15
BI
SPIROM_USE_MLB
AM4
OUT
CAMERA_PWR_EN_PCH
AG5
36 15
18 15
64 15
OUT
B
R1614
R1615
100K
100K
1
1
5%
2
2 5%
5%
A
8
100K
100K
100K
100K
100K
1
1
1
1
1
2
2
2
2
2
100K
100K
100K
100K
100K
100K
100K
100K
100K
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
1
1
AG3
GPIO9
GPIO10
SDIO_CLK/GPIO64 E3
TBT_POC_RESET_L
OUT
27
OUT
15 64
100K
1
10K
1
100K
1
100K
1
100K
100K
100K
1
1
1
GPIO46
XDP_MLB_RAMCFG1
BI
AM2
64 30 15
OUT
SSD_DEVSLP
P2
DEVSLP0*/GPIO33
SDIO_CMD/GPIO65 F4
BT_PWRRST_L
29 15
OUT
AP_S0IX_WAKE_SEL
C4
SDIO_POWER_EN/GPIO70
IN
39
L2
DEVSLP1*/GPIO38
SDIO_D0/GPIO66 D3
(IPD-PLTRST#)
SDIO_D1/GPIO67 E4
PCH_STRP_TOPBLK_SWP_L
SSD_RESET_L
ENET_MEDIA_SENSE
IN
15 64
FW_PME_L
N5
DEVSLP2*/GPIO39
SDIO_D2/GPIO68 C3
LCD_IRQ_L
IN
15 64
PCH_TCO_TIMER_DISABLE
V2
SPKR/GPIO81
(IPD-PLTRST#)
SDIO_D3/GPIO69 E2
LCD_PSR_EN
OUT
15 64
OUT
64 15
NO STUFF
IN
2
5%
1/20W
MF
201
Pull-up on TBT page
Requires connection to SMC via 1K series R
15 18 19 33 36 40 41 58 62 64
31 41
74 65 64 62 61
36 30 27 18 17 15 13 12 11 8
59 56 45 44 43 42 41 40 39 38
62 64 65 74
8 11 12 13 15 17 18 27 30 36 38
39 40 41 42 43 44 45 56 59 61
17 25 26 27 62 64
15
15
XDP_PCH_GPIO76
1/20W
1/20W
1/20W
MF
MF
MF
201
201
201
XDP_LPCPLUS_GPIO
XDP_PCH_GPIO17
15 16
15
15
MF
MF
MF
MF
MF
201
201
201
201
201
5%
5%
5%
5%
5%
5%
5%
5%
5%
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
MF
MF
MF
MF
MF
MF
MF
MF
MF
201
201
201
201
201
201
201
201
201
1/20W
1/20W
1/20W
MF
MF
MF
201
201
201
1/20W
1/20W
MF
MF
201
201
1/20W
MF
SD_RESET_L
SMC_WAKE_SCI_L
TPAD_SPI_INT_L
TPAD_USB_IF_EN
SSD_PWR_EN
15 16
36 15
R1616 should also be stuffed if
platform does not use SD card
15 34
SPIROM_USE_MLB
CAMERA_PWR_EN_PCH
FW_PWR_EN
SSD_DEVSLP
AP_S0IX_WAKE_SEL
201
15 36
29 15
15 36
64 15
15 30 58 59 64
15 64
15
15 16 33
15
15 34
15
15 25
15
15 16 18 25
15
15 18 25
15
15 58
15
PCH_I2C0_SDA
PCH_I2C0_SCL
PCH_I2C1_SDA
PCH_I2C1_SCL
100K
100K
100K
100K
1
1
1
1
47K
47K
47K
47K
1
1
1
1
100K
100K
1
1
100K
100K
100K
100K
1
1
1
1
100K
100K
1
1
100K
100K
1
1
2
5%
2
5%
2
5%
2
5%
2
2 5%
2 5%
2 5%
5%
2
2 5%
5%
2
2 5%
2 5%
5%
2
5%
2
2 5%
5%
2
2 5%
5%
B
1/20W
1/20W
1/20W
1/20W
MF
MF
MF
MF
201
201
201
201
1/20W
1/20W
1/20W
1/20W
MF
MF
MF
MF
201
201
201
201
1/20W
1/20W
MF
MF
201
201
1/20W
1/20W
1/20W
1/20W
MF
MF
MF
MF
201
201
201
201
1/20W
1/20W
MF
MF
201
201
1/20W
1/20W
MF
MF
201
201
15 46 64
15 18
15 64
SYNC_MASTER=J41_MLB
15 30 64
SYNC_DATE=04/02/2013
PAGE TITLE
15 29
PCH GPIO/MISC/LPIO
15 64
15 37 46 64
DRAWING NUMBER
Apple Inc.
201
JTAG_ISP_TDO
MF
PCH_UART1_RXD
PCH_UART1_TXD
PCH_UART1_RTS_L
PCH_UART1_CTS_L
R1660
R1661
R1662
R1663
R1664
R1665
R1666
R1667
R1668
R1669
R1672
R1673
R1674
R1675
R1676
R1677
R1678
R1679
PP3V3_S0
15 36
15 18 25
BT_PWRRST_L
1/20W
AP_S0IX_WAKE_L
HDMITBTMUX_FLAG_L
15 16 18 25
FW_PME_L
MF
68 36 15
TPAD_SPI_CS_L
TPAD_SPI_CLK
TPAD_SPI_MISO
TPAD_SPI_MOSI
15 37
LPC_SERIRQ
1/20W
68 36 15
15
HDD_PWR_EN
XDP_SDCONN_STATE_CHANGE_L
SD_PWR_EN
TBT_PWR_EN
XDP_JTAG_ISP_TCK
XDP_JTAG_ISP_TDI
JTAG_TBT_TMS
PCH_HSIO_PWR_EN
TPAD_SPI_IF_EN
PCH_GSPI0_CS_L
PCH_GSPI0_CLK
PCH_GSPI0_MISO
PCH_GSPI0_MOSI
15 16 46 64
68 36 15
1/20W
1/20W
1/20W
1/20W
1/20W
2
2 5%
5%
2
5%
2
5%
2
5%
2
5%
2
2 5%
2 5%
5%
GPIO45
34 37 39 65
5%
100K
100K
C
8 11 13 16 17 18 28 29 34 42 57
58 59 60 62 64 74
15 18 19 33 36 40 41 58 62 64
5%
5%
5%
5%
5%
100K NO STUFF
1
2
100K 1
2 5%
100K 1
2 5%
15
FW_PWR_EN
SD_ON_MLB
R1616
R1617
R1618
R1619
R1620
R1622
R1623
R1624
R1625
R1626
R1627
R1628
R1629
R1630
R1632
R1633
R1634
R1637
R1638
R1640
R1652
R1670
R1691
R1693
R1694
R1695
15
XDP_MLB_RAMCFG2
100K
PP3V3_S5
PP3V3_S3
PP3V3_S0SW_SD
PP3V3_S3
PP3V3_S3RS0_CAMERA
PP3V3_S0
PP3V3_TBTLC
TBTLC for CR, S0 for RR
2
R1610 100K 1
PCH_UART1_TXD
PCH_UART1_RTS_L
29
15
BI
R1639
1
UART1_TXD/GPIO1 G2
OUT
PCH_UART1_RXD
18 16 15
18 16 15
1K
UART1_RXD/GPIO0 K4
AM3
1
R1641
5%
1/20W
MF
2 201
15
GPIO14
OUT
AT3
GPIO
LPIO
OUT
58 15
PP3V3_S0
13 15 16 18
R1671
15 64
JTAG_ISP_TDO
25 18 15
74 65 64 62 61
36 30 27 18 17 15 13 12 11 8
59 56 45 44 43 42 41 40 39 38
IN
1
100K
HDMITBTMUX_FLAG_L
UART0_RTS*/GPIO93 J2
25 18 16 15
5%
1/20W
MF
201 2
PLT_RESET_L
15 29
25 18 16 15
30
15 36
GPIO58
25 15
C
Pull-up/down on chipset support page (depends on TBT controller)
Cactus Ridge: Alias to TBT_CIO_PLUG_EVENT,
requires pull-down.
Redwood Ridge: Alias to TBT_CIO_PLUG_EVENT_L, requires pull-up (S0).
GPIO15 (IPD-RSMRST#)
15 16 18
25 18
P1
XDP_PCH_GPIO76
BI
BGA-TSP
SYM 10 OF 19
BMBUSY*/GPIO76
CPU/MISC
PP3V3_S0
PP1V05_S0
15 64
R
& lt; E4LABEL & gt;
201
1/20W
MF
201
1/20W
1/20W
1/20W
MF
MF
MF
201
201
201
NOTICE OF PROPRIETARY PROPERTY:
7
ENET_MEDIA_SENSE
LCD_IRQ_L
LCD_PSR_EN
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
15 64
15 64
15 64
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
BRANCH
& lt; BRANCH & gt;
PAGE
16 OF 121
SHEET
15 OF 76
1
A
8
7
6
Extra BPM Testpoints
CRITICAL
XDP_CONN
1 TP
TP1802
XDP_BPM_L & lt; 3 & gt; 1 TP
TP1803
TP-P6
XDP_BPM_L & lt; 4 & gt; 1 TP
TP1804
TP-P6
XDP_BPM_L & lt; 5 & gt; 1 TP
TP1805
TP-P6
XDP_BPM_L & lt; 6 & gt; 1 TP
TP1806
TP-P6
XDP_BPM_L & lt; 7 & gt; 1 TP
TP1807
TP-P6
IN
IN
IN
67 6
37 17 13
PM_PWRBTN_L
OUT
PM_PCH_SYS_PWROK
IN
67 6
IN
67 6
IN
XDP
1K
1
2
5%
PLACE_NEAR=U0500.C61:2.54mm
OUT
IN
67 6
37 13
IN
67 6
R1800
IN
67 6
CPU_VCCST_PWRGD
IN
67 6
1/20W
MF
R1802
0
R1804
0
1
1/20W
MF
8
64
BI
IN
69 64 16 12
16 12
OBSDATA_B2
OBSDATA_B3
XDP_CPU_VCCST_PWRGD
XDP_CPU_PWRBTN_L
PWRGD/HOOK0
HOOK1
VCC_OBS_AB
HOOK2
HOOK3
CPU_PWR_DEBUG
XDP_SYS_PWROK
1/16W MF-LF 402
69 56 40 25 19 14
67 64 16 6
CPU_CFG & lt; 6 & gt;
CPU_CFG & lt; 7 & gt;
OUT
2
5%
OBSDATA_B0
OBSDATA_B1
0201
XDP
1
OBSFN_B0
OBSFN_B1
CPU_CFG & lt; 4 & gt;
CPU_CFG & lt; 5 & gt;
2
69 56 40 25 19 14
C
XDP_BPM_L & lt; 0 & gt;
XDP_BPM_L & lt; 1 & gt;
64
5%
OBSDATA_A2
OBSDATA_A3
201
XDP
PLACE_NEAR=U5000.J3:2.54mm
OBSDATA_A0
OBSDATA_A1
CPU_CFG & lt; 2 & gt;
CPU_CFG & lt; 3 & gt;
IN
67 64 6
OUT
SMBUS_PCH_DATA
SMBUS_PCH_CLK
XDP_PCH_TCK
SDA
SCL
TCK1
TCK0
XDP_CPU_TCK
OUT
PCH_JTAGX
OUT
R1835
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
OBSFN_A0
OBSFN_A1
CPU_CFG & lt; 0 & gt;
CPU_CFG & lt; 1 & gt;
XDP
0
1
2
XDP
5% 1/20W
MF
0201
PLACE_NEAR=J1800.58:28mm
C1804
XDP
1
0.1UF
1K
10%
6.3V
CERM-X5R 2
0201
5%
1/16W
MF-LF
2 402
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
OBSFN_C0
OBSFN_C1
1
64
10%
6.3V
CERM-X5R 2
0201
CPU_CFG & lt; 17 & gt;
CPU_CFG & lt; 16 & gt;
OBSDATA_C0
OBSDATA_C1
CPU_CFG & lt; 8 & gt;
CPU_CFG & lt; 9 & gt;
OBSDATA_C2
OBSDATA_C3
CPU_CFG & lt; 10 & gt;
CPU_CFG & lt; 11 & gt;
OBSFN_D0
OBSFN_D1
IN
IN
IN
6 67
IN
6 67
IN
6 67
CPU_CFG & lt; 19 & gt;
CPU_CFG & lt; 18 & gt;
IN
6
IN
6
OBSDATA_D0
OBSDATA_D1
CPU_CFG & lt; 12 & gt;
CPU_CFG & lt; 13 & gt;
IN
6 67
IN
6 67
OBSDATA_D2
OBSDATA_D3
CPU_CFG & lt; 14 & gt;
CPU_CFG & lt; 15 & gt;
IN
6 67
IN
6 67
ITPCLK/HOOK4
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7
NC
NC
67
TDO
TRSTn
TDI
TMS
XDP_PRESENT#
XDP
1
63
C1801
518S0847
C1806
Q1840
0.1UF
10%
2 6.3V
CERM-X5R
0201
DMN5L06VK-7
10%
2 6.3V
CERM-X5R
0201
SOT-563
XDP_CPU_TDO
D
6
XDP_CPUPCH_TRST_L
XDP_CPUPCH_TRST_L
XDP_USB_EXTD_OC_L
XDP_SDCONN_STATE_CHANGE_L
18 15
18 15
XDP_MLB_RAMCFG1
BI
XDP_MLB_RAMCFG2
BI
IN
XDP_SSD_PCIE3_SEL_L
12
OUT
XDP_SSD_PCIE2_SEL_L
12
OUT
XDP_SSD_PCIE1_SEL_L
12
OUT
XDP_SSD_PCIE0_SEL_L
BI
BI
IN
NC
NC 5
1
5
3
4
OUT
6 64 67
62 57
NC
16 12
R1899
PCH_JTAGX
PP1V05_SUS
NO STUFF
1K
2
1
1/20W
MF
MF
201
1K
1
1
2
5%
1/20W
MF
1/20W
MF
201
SSD_PCIE_SEL_L
IN
1 TP
BI
TP-P6
1 TP
TP-P6
XDP_JTAG_ISP_TDI
OUT
MF
201
5%
1/20W
MF
201
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
1
XDP
51
2
R1896 51 2
PLACE_NEAR=U0500.AE62:28mm
XDP_PCH_TCK
30 64
67 64 16 12 6
XDP_LPCPLUS_GPIO
MAKE_BASE=TRUE
1/20W
XDP
1
NO STUFF
69 64 16 12
201
5%
R1892
XDP_PCH_TMS
201
1
PLACE_NEAR=U0500.AD62:28mm
2
1K
69 64 16 12
NOTE: Must not short XDP pins together!
MF
5%
R1891 51 2
PLACE_NEAR=U0500.AD61:28mm
1/20W
5%
XDP_PCH_TDI
15 16 18 25
201
1/20W
2
5%
R1890 51 2
PLACE_NEAR=U0500.AE61:28mm
XDP
XDP_PCH_TDO
69 64 16 12
OUT
1
PLACE_NEAR=U0500.AE63:28mm
2
5%
XDP_JTAG_ISP_TDI
XDP_CPU_TMS
XDP_JTAG_CPU_ISOL_L
Y 4
1 NC
PLACE_NEAR=J1800.57:28mm
69 64 16 12
5%
1K
XDP_PCH_GPIO76
25 18 16 15
2 A
5%
1/20W
MF
2 201
GND
XDP_JTAG_ISP_TCK
1K
XDP_PCH_GPIO17
15
ALL_SYS_PWRGD
TP1876
TP1877
TP-P6
1 TP
TP1878
TP-P6
R1881
R1882
R1883
R1884
330K
VCC
1 TP
XDP_LPCPLUS_GPIO
OUT
IN
B
R1845
U1845
15 16 33
SOT-563
1
74LVC1G07GF
SOT891
1 TP
MAKE_BASE=TRUE
15
64 46 16 15
A
59 37 17
XDP_SDCONN_STATE_CHANGE_L
IN
XDP_JTAG_ISP_TCK
OUT
0.1UF
14 16 61 65
TP-P6
XDP_MLB_RAMCFG3
12
25 18 16 15
C1845 1
10%
16V
X5R-CERM 2
0201
TP1873
TP-P6
1 TP
TP1874
TP-P6
MAKE_BASE=TRUE
BI
IN
14 16 35
1 TP
6 64 67
3
18 15
MAKE_BASE=TRUE
6 12 16 64 67
2
IN
OUT
14
XDP_USB_EXTB_OC_L
6 12 16 64 67
OUT
G
XDP_USB_EXTC_OC_L
MAKE_BASE=TRUE
DMN5L06VK-7
IN
OUT
OUT
XDP_CPU_TDI
S
OUT
XDP_USB_EXTA_OC_L
6 12 16 64 67
1
OUT
14
Q1842
TP1870
D
65 61 16 14
XDP_USB_EXTB_OC_L
TP-P6
6 16 64 67
CRITICAL
XDP
6
XDP_USB_EXTA_OC_L
PLACE_NEAR=J1800.55:28mm
PP5V_S0
PP3V3_S5
6
OUT
33 16 15
CPU JTAG Isolation
D
SOT-563
BI
C
12 16 64 69
G
DMN5L06VK-7
These signals do not connect to XDP connector in this architecture, only accessible
via Top-Side Probe. Nets are listed here to show XDP associations and to make clear
what restrictions exist on PCH GPIOs when Top-Side Probe is used for PCH debug.
35 16 14
IN
XDP_CPUPCH_TRST_L
S
Q1842
PCH XDP Signals
B
12 16 64 69
MAKE_BASE=TRUE
CRITICAL
XDP
42 34 29 28 18 17 15 13 11 8
74 64 62 60 59 58 57
12 16 64 69
CRITICAL
XDP
PLACE_NEAR=J1800.53:28mm
61 59 58 56 52 51 46 45 32 17
64 62
13 15 18
CRITICAL
XDP
XDP
1
0.1UF
XDP
2
XDP_CPURST_L
R1805 1K 1
PLT_RESET_L
IN
5% 1/20W MF
201
XDP_DBRESET_L
PLACE_NEAR=U0500.AG7:2.54mm
OUT 17 67
NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page
XDP_PCH_TDO
IN
XDP_TRST_L
XDP_PCH_TDI
OUT
XDP_PCH_TMS
OUT
SOT-563
Non-XDP Signals
201
D
Q1840
1 TP
MF
6 67
DMN5L06VK-7
PCH/XDP Signals
1/20W
6
XDP_CPU_PRESENT_L
XDP_MLB_RAMCFG0
5%
PLACE_NEAR=U0500.E60:28mm
6
IN
PLACE_NEAR=J1800.51:28mm
18 15
201
61
XDP
R1831 C1800
0.1UF
1
MF
5
67 64 6
67 6
IN
XDP_CPU_PREQ_L
XDP_CPU_PRDY_L
BI
R1813
XDP_CPU_TCK
1/20W
1
G
67 64 6
67 64 16 6
5%
51 2
TDI and TMS are terminated in CPU.
5%
1/16W
MF-LF
2 402
67 6
17 8
62
150
S
IN
M-ST-SM1
R1830
2
XDP
4
IN
67 6
DF40RC-60DP-0.4V
1
XDP
51 1
PLACE_NEAR=U0500.F62:28mm
2
IN
67 6
D
IN
67 6
R1810
XDP_CPU_TDO
PP1V05_S0
G
67 6
67 64 16 6
D
IN
NOTE: This is not the standard XDP pinout.
Use with 921-0133 Adapter Flex to
support chipset debug.
J1800
TP-P6
67 6
1
51 42 38 27 17 16 15 11 8 6
64 62 59 58 55
S
XDP_BPM_L & lt; 2 & gt;
2
Merged (CPU/PCH) Micro2-XDP
PP1V05_S0
51 42 38 27 17 16 15 11 8 6
64 62 59 58 55
3
1
IN
4
3
67 6
5
XDP_CPUPCH_TRST_L
R1897 51
NO STUFF
2
PLACE_NEAR=U0500.AU62:28mm
15 16 46 64
1
1
TP1886
TP1887
MAKE_BASE=TRUE
15 16 18 25
SYNC_MASTER=J41_MLB
SYNC_DATE=02/06/2013
PAGE TITLE
CPU/PCH Merged XDP
Unused & MLB_RAMCFGx GPIOs have TPs.
USB Overcurrents are aliased, do not cause USB OC# events during PCH debug.
DRAWING NUMBER
Apple Inc.
SDCONN_STATE_CHANGE_L is aliased, do not plug/unplug SD Cards during PCH debug.
R
JTAG_ISP (non-TMS) nets are aliased, do not attempt bit-banged JTAG during PCH debug.
NOTICE OF PROPRIETARY PROPERTY:
NOTE: Should force PCH GPIO47 high to ensure TBT router powered to avoid leakage/clamping of signals.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SSD_PCIEx_SEL_L straps are connected via 1K to common net.
LPCPLUS_GPIO is aliased, do not attempt use during PCH debug.
8
7
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
18 OF 121
SHEET
16 OF 76
1
A
8
7
6
5
4
3
2
1
System RTC Power Source & 32kHz / 25MHz Clock Generator
PCH Reset Button
Chipset uses 24MHz crystal, GreenCLK kept to save 1x 25MHz crystal & 1x 32kHz crystal
PP3V42_G3H
Coin-Cell:
VBAT (300-ohm & 10uF RC)
No Coin-Cell: 3.42V G3Hot (no RC)
70 62 53 42 23 22 21 20 19
XDP
R1996
67 16
C1924 1
C1922
0.1UF
1
1
0.1UF
10%
16V
X5R-CERM 2
0201
C1902
1UF
10%
16V
X5R-CERM 2
0201
XDP_DBRESET_L
1
2
5%
1/20W
MF
2 201
C1970 1
0.1UF
PM_SYSRST_L
NO STUFF
13 37 64
BI
1
R1997
6
IN
1
R1970
330K
VCC
10%
16V
X5R-CERM 2
0201
74AUP1G07GF
SOT891
CPU_MEMVTT_PWR_EN_LSVDDQ
2 A
MEMVTT_PWR_EN
Y 4
MAKE_BASE=TRUE
0
1 NC
NC
NC 5
TQFN
2
R1906
THRM
PAD
GND
5%
1/20W
MF
2 201
1
OUT
25 69
DMN5L06VK-7
C1910
58 11 8
2
1
PCH_CLK24M_XTALOUT_R
CRITICAL
17 12
NC_RTC_CLK32K_RTCX2
MAKE_BASE=TRUE
NC_RTC_CLK32K_RTCX2
NO_TEST=TRUE
IN
37
5%
1/20W
MF
Y1915
NC 24.000MHZ-20PPM-6PF 0201
NC 3.20X2.50MM-SM1
IN
12
OUT
5%
1/20W
MF
2 201
R1916
1M
5%
1/20W
MF
2 201
PCH_CLK24M_XTALIN
IN
G
HDA_SDOUT_R
IPD = 9-50k
S 1
C
12 69
OUT
SPI_DESCRIPTOR_OVERRIDE_L
12
1
2
VCCST (1.05V S0) PWRGD
22
1
PLACE_NEAR=U0500.AN15:5.1mm
PP3V3_S5
MAKE_BASE=TRUE
OUT
1
PLACE_NEAR=U0500.AP15:5.1mm
22
U1930
10%
16V
X5R-CERM 2
0201
R1926
LPC_CLK24M_LPCPLUS_R
CRITICAL
0.1UF
17 37 69
LPC_CLK24M_LPCPLUS
2
OUT
59 37 17 16
46 64 69
5%
1/20W
MF
201
59 37 18 13
IN
74AUP1G09
SOT891
VCC
ALL_SYS_PWRGD
2 A
PM_SLP_S3_L
R1931
10K
5%
1/20W
MF
2 201
1 B
NC
CPU_VCCST_PWRGD
Y 4
OUT
8 16
5 NC
B
GND
3
B
6 8 11 15 16 27 38 42 51 55 58
59 62 64
1
C1930 1
LPC_CLK24M_SMC
2
5%
1/20W
MF
201
PP1V05_S0
17 37 69
6
LPC_CLK24M_SMC_R
34 29 28 18 17 16 15 13 11 8
74 64 62 60 59 58 57 42
LPC_CLK24M_SMC
R1927
IN
1K
PCH uses HDA_SDO as a power-up strap. If low, ME functions normally.
If high, ME is disabled. This allows for full re-flashing of SPI ROM.
SMC controls strap enable to allow in-field control of strap setting.
Q1920 & 5V pull-up allows circuit to work regardless of HDA voltage.
PCH 24MHz Outputs
69 12
R1921
D 6
12 17
+/-0.1PF
25V
C0G
0201
IN
SPI_DESCRIPTOR_OVERRIDE
1
2
PCH_CLK24M_XTALOUT
2
3
4
0
1
6.8PF
69 12
SPI_DESCRIPTOR_OVERRIDE_LS5V
PP1V5_S0SW_AUDIO_HDA
1UF
R1915
C1916
5%
1/20W
MF
2 201
SOT-563
6.8PF
NC
100K
DMN5L06VK-7
C1915
+/-0.1PF
25V
C0G
0201 NC
R1920
Q1920
64
Q1920
PCH 24MHz Crystal
2
1
PCH ME Disable Strap
20%
2 6.3V
X5R
0201
SYSCLK_CLK25M_X1
NOTE: 30 PPM or better required for RTC accuracy
C
1
32 69
SOT-563
1M
SM-3.2X2.5MM
OUT
PP5V_S0
G 5
VOUT 1
1
69
5%
25V
NP0-C0G-CERM
0201
1
X2
X1
17 53
4
12PF
1
69
5%
1/20W
MF
0201
CRITICAL
3
4
SYSCLK_CLK25M_X2_R
NO STUFF
2
25.000MHZ-12PF-20PPM
3
C1906
0
1
Y1905
2 4
NC
1
5%
25V
NP0-C0G-CERM
0201 NC
SYSCLK_CLK25M_X2
SYSCLK_CLK25M_CAMERA
SYSCLK_CLK25M_TBT
PPVRTC_G3H
8 12 13 62
For SB RTC Power
61 59 58 56 52 51 46 45 32 16
64 62
12
D
69
NC
OUT
3
1
7
10
16
2
25M_A 9
25M_B 8
25M_C 15
PCH_CLK32K_RTCX1
S
R1905
12PF
32.768K 12
17
C1905
OUT
GND
CRITICAL
CKPLUS_WAIVE=PwrTerm2Gnd
MEMVTT_PWR_EN
NC
D
17 53
+V3.3A should be first
available ~3.3V power
to reduce VBAT draw.
SLG3NB148CV
11 VIOE_25M_A
6 VIOE_25M_B
14 VIOE_25M_C
TPS51916 I(leak) = +/- 1uA,
Vih(min) = 1.8V
33uW when driven-low
5%
1/20W
MF
2 201
U1970
5%
1/16W
MF-LF
2 402
SILK_PART=SYS RESET
VBAT and +V3.3A are
internally ORed to
create VDD_RTC_OUT.
U1900
20%
2 6.3V
X5R
0201
IN
0
1/20W
0201
MF
5%
VG3HOT 13
64 62 27 26 25 15
PP1V2_CAM_XTALPCIEVDD
PP3V3_TBTLC
62 64 65 74
8 11 12 13 15 17 18 27 30 36 38
39 40 41 42 43 44 45 56 59 61
10K
VDD 5
31
PP3V3_S0
R1995
18
GreenCLK 25MHz Power
Must be powered if any VDDIO is powered.
CAM XTAL Power
TBT XTAL Power
PP1V2_S3
1
PP3V3_S5
Coin-Cell & G3Hot:
3.42V G3Hot
Coin-Cell & No G3Hot: 3.3V S5
No Coin-Cell:
3.3V S5
No bypass necessary
PP3V3_S5RS3RS0_SYSCLKGEN
64 62 60 59
15 13 11 8
18 17 16
74
NC 2
D
PP3V3_S0
6
This looks a little ugly to support
new and old parts. With GreenCLK Rev C
pin 5 must receive S5 power (Stuff 57 42 34 29 28
R2042)
58
Memory VTT Enable Level-Shifter
CPU output is on VDDQ rail (1.2V), TPS51916 has 1.8V Vih(min).
74 65 64 62 61
36 30 27 18 17 15 13 12 11 8
59 56 45 44 43 42 41 40 39 38
3
50 49 46 40 38 37 36 35 30 17
65 64 62 61 59
PCH PWROK Generation
PP3V42_G3H
50 49 46 40 38 37 36 35 30 17
65 64 62 61 59
PM_PCH_PWROK
PM_PCH_PWROK
OUT
74 65 64 62 61
36 30 27 18 17 15 13 12 11 8
59 56 45 44 43 42 41 40 39 38
51 8
IN
5%
1/20W
MF
201 2
51 17 8
OUT
51 17 8
IN
0.1UF
10K
5%
1/20W
MF
201 2
10K
CPU_VR_READY
MAKE_BASE=TRUE
CPU_VR_READY
NO STUFF
R1951
1
0
C1950
10%
16V
2 X5R-CERM
0201
R1950
R1955
A
1
1
1
IN
2
8 74LVC2G08GT
SOT833
ALL_SYS_PWRGD
1
U1950 7
Y
2
5%
1/20W
MF
0201
NO STUFF WF: Do we need this?
R19632
0
CPUVR_PGOOD_R
59 37 17 16
13 17
BYPASS=U1950:5MM
PP3V3_S0
CPU_VR_EN
13 17
OUT
MAKE_BASE=TRUE
A
B
08
5%
1/20W
MF
0201 1
PM_S0_PGOOD
NO STUFF
R19611
4
2
R1960
0
5%
1/20W
MF
1 0201
5
CKPLUS_WAIVE=UNCONNECTED_PINS
8 74LVC2G08GT
SOT833
A
U1950 3
Y
6
B
SYS_PWROK_R
1
1K
2
PM_PCH_SYS_PWROK
4
SYNC_DATE=02/06/2013
PAGE TITLE
OUT
Chipset Support
13 16 37
5%
1/20W
MF
201
08
100K
5%
1/20W
MF
201 2
SYNC_MASTER=J41_MLB
R1962
DRAWING NUMBER
Apple Inc.
CKPLUS_WAIVE=UNCONNECTED_PINS
R
NOTICE OF PROPRIETARY PROPERTY:
38 37 27
8
7
IN
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SMC_DELAYED_PWRGD
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
19 OF 121
SHEET
17 OF 76
1
A
8
7
6
5
4
3
2
GreenCLK 25MHz Power
Platform Reset Connections
DDC Pull-Ups
2.2k pull-ups are required by PCH
to indicate active display interface.
NO STUFF
Unbuffered
R2081
16 15 13
PLT_RESET_L
IN
1
33
R2040
64 62 58 41 40 36 33 19 15
LPCPLUS_RESET_L
2
5%
1/20W
MF
201
0
65
41
13
30
56
64
40
12
27
45
62
39
11
18
44
61
38
8
17
43
PP3V3_S5RS3RS0_SYSCLKGEN
2
5%
1/20W
MF
0201
PP3V3_S5RS3RS0_SYSCLKGEN
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
MAKE_BASE=TRUE
NO STUFF
PCA9557D_RESET_L
2
74 65 64 62 61
36 30 27 18 17 15 13 12 11 8
59 56 45 44 43 42 41 40 39 38
PP3V3_S0
0
5
1
1
2
5%
1/20W
MF
0201
2
U2071
100K
R2042 should be stuffed for GreenCLK C
1
28 18 13
37
BKLT_PLT_RST_L
OUT
0
OUT
IN
1
R2023
2.2K
2.2K
5%
1/20W
MF
2 201
5%
1/20W
MF
201 2
5%
1/20W
MF
2 201
D
DP_TBTSNK0_DDC_CLK
DP_TBTSNK0_DDC_DATA
DP_TBTSNK1_DDC_CLK
DP_TBTSNK1_DDC_DATA
TBTSNK1_DDC is pulled-up just to indicate that
DP port is used. No DDC on this port, AUX-only.
31
NOTE: Only DDC_DATA is sensed by PCH, so
DDC_CLK pull-ups are unstuffed.
2
Thunderbolt Pull-up/downs
2
Cactus Ridge GO2SX signal pulled-up to SUS rail
5%
1/20W
MF
0201
27 18 15
R20221
2.2K
56
CAM_PCIE_RESET_L
18 13
2
5%
1/20W
MF
0201
5%
1/20W
MF
0201
R2089
0
OUT
R2021
5%
1/20W
MF
201 2
18 13
0
1
2.2K
1
PP3V3_S5
NO STUFF
R20201
R2088
1
5%
1/20W
MF
2 201
0.1UF
SMC_LRESET_L
2
PP3V3_S0
NO STUFF
28 18 13
34 29 28 18 17 16 15 13 11 8
74 64 62 60 59 58 57 42
5%
1/20W
MF
0201
R2070
10%
16V
2 X5R-CERM
0201
0
1
1
3
C2071
1
SC70-HF
4
PLT_RST_BUF_L
17 18
R2042
Buffered
R2072
CRITICAL
MC74VHC1G08
74 65 64 62 61
36 30 27 18 17 15 13 12 11 8
59 56 45 44 43 42 41 40 39 38
R2041/2 should be stuffed for
GreekCLK A or B depending on S2 rail
Scrub for Layout Optimization
PP3V3_S0
DP++ spec violation, should remove!
17 18
R2041
19
OUT
5%
1/20W
MF
0201
D
0
1
46 64 69
OUT
R2071
1
74
42
15
36
59
PP3V3_S3
1
PP3V3_SUS
64 62 59 58 57 46 14 11 8
PCH_TBT_PCIE_RESET_L
PCH_TBT_PCIE_RESET_L
OUT
MAKE_BASE=TRUE
R20131
10K
15 18 27
25 18 15
MAKE_BASE
TRUE
TBT_GO2SX_BIDIR
BI
5%
1/20W
MF
201
2
TBT_GO2SX_BIDIR
BI
15 18 25
Cactus Ridge PLUG_EVENT is active-high, always driven (pull-down)
25 18 15
34 29 28 18 17 16 15 13 11 8
74 64 62 60 59 58 57 42
C
OUT
C2030
25
15
IN
OUT
25
NOSTUFF
CRITICAL
OUT
25
0.1UF
IN
25
1
10%
10V
X5R-CERM 2
0201
IN
TBT_CIO_PLUG_EVENT
TRUE
IN
15 18 25
C
Required for unused second TBT port
NOSTUFF
BYPASS=U2030:3mm
59 37 36 29 18 13
TBT_CIO_PLUG_EVENT
PP3V3_S5
OUT
25
TBT_B_CIO_SEL
DP_TBTPB_HPD
TBT_B_CONFIG2_RC
TBT_B_CONFIG1_BUF
TBT_B_LSRX
6 74LVC1G08
2
CAMERA_PWR_EN_PCH
U2030 4
1
08
CAMERA_PWR_EN
5%
1/20W
MF
201 2
1
R2017 R20181
10K
OUT
10K
5%
1/20W
MF
201 2
31
NC
5
100K
R20161
SOT891
PM_SLP_S4_L
R20151
10K
5%
1/20W
MF
2 201
5%
1/20W
MF
201 2
1
R2019
10K
5%
1/20W
MF
2 201
1
R2014
10K
5%
1/20W
MF
2 201
3
NC
Power State Debug LEDs
DBGLED
60
29
13
17
57
74
59
28
11
16
42
64
58
18
8
15
34
62
0
2
PLACE_SIDE=BOTTOM
R2030
PP3V3_S5_DBGLED
1
5%
1/16W
MF-LF
402
TBT Aliases
(For development only)
R2094
PP3V3_S5
1
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=3.3V
DBGLED
DBGLED
DBGLED
DBGLED
R20911
R20921
R20931
5%
1/20W
MF
201 2
5%
1/20W
MF
201 2
5%
1/20W
MF
201 2
5%
1/20W
MF
201 2
IN
28 18 13
BI
20K
DBGLED_S4
DBGLED
A
D2090
GREEN-56MCD-2MA-2.65V
LTQH9G-SM
PLACE_SIDE=BOTTOM
SILK_PART=S5_ON
K
20K
DBGLED_S3
25 18 13
DBGLED
A
D2091
GREEN-56MCD-2MA-2.65V
LTQH9G-SM
PLACE_SIDE=BOTTOM
SILK_PART=STBY_ON
DBGLED_S4_D
GREEN-56MCD-2MA-2.65V
LTQH9G-SM
PLACE_SIDE=BOTTOM
SILK_PART=S3_ON
GREEN-56MCD-2MA-2.65V
LTQH9G-SM
PLACE_SIDE=BOTTOM
SILK_PART=S0I3_ON
DBGLED_S0I3_D
DBGLED
D 6
Q2090
A
D2093
K
Q2091
67 25 18 13
K
GREEN-56MCD-2MA-2.65V
LTQH9G-SM
PLACE_SIDE=BOTTOM
SILK_PART=S0_ON
25 18 15
59 37 17 13
IN
37 13
IN
OUT
25 18 16 15
IN
25 18 16 15
IN
25 18 15
IN
DBGLED
D 6
Q2091
DMN5L06VK-7
SOT-563
DP_TBTSNK0_DDC_CLK
DP_TBTSNK0_DDC_DATA
BI
13 18 28
DP_TBTSNK1_HPD
TRUE
=DP_TBTSNK1_ML_C_P & lt; 3..0 & gt;
TRUE
=DP_TBTSNK1_ML_C_N & lt; 3..0 & gt;
TRUE
DP_TBTSNK1_AUXCH_C_P
TRUE
DP_TBTSNK1_AUXCH_C_N
TRUE
DP_TBTSNK1_DDC_CLK
TRUE
DP_TBTSNK1_DDC_DATA
TRUE
Single-port TBT implementation does
JTAG_ISP_TDO
XDP_JTAG_ISP_TCK
XDP_JTAG_ISP_TDI
JTAG_TBT_TMS
MAKE_BASE
TRUE
DP_TBTSNK1_HPD
IN
DP_TBTSNK1_ML_C_P & lt; 3..0 & gt; OUT
DP_TBTSNK1_ML_C_N & lt; 3..0 & gt; OUT
DP_TBTSNK1_AUXCH_C_P
BI
DP_TBTSNK1_AUXCH_C_N
BI
DP_TBTSNK1_DDC_CLK
13 18
DP_TBTSNK1_DDC_DATA
13 18
not require DDC Crossbar
13 18 28
13 18 25
5 25 67
5 25 67
13 18 25
67
13 18 25
67
B
MAKE_BASE
TRUE
JTAG_ISP_TDO
XDP_JTAG_ISP_TCK
XDP_JTAG_ISP_TDI
JTAG_TBT_TMS
IN
15 18 25
OUT
15 16 18
25
OUT
15 16 18
25
OUT
15 18 25
D 3
SOT-563
G
S 1
5
G
S 4
2
G
S 1
5
G
RAM Configuration Straps
Pull-downs for chip-down RAM systems
S 4
16 15
OUT
16 15
OUT
16 15
S4_PWR_EN
PM_SLP_S4_L
PM_SLP_S3_L
PM_SLP_S0_L
OUT
OUT
XDP_MLB_RAMCFG0
XDP_MLB_RAMCFG1
XDP_MLB_RAMCFG2
XDP_MLB_RAMCFG3
RAMCFG3:L
RAMCFG2:L
RAMCFG1:L RAMCFG0:L
R20501
R20511
R20521
R20531
5%
1/20W
MF
201 2
5%
1/20W
MF
201 2
5%
1/20W
MF
201 2
5%
1/20W
MF
201 2
10K
10K
10K
10K
A
SYNC_MASTER=J41_MLB
18 6
18 15
IN
TP_CPU_MEM_RESET_L
IN
TP_MEM_VDD_SEL_1V5_L
PP0V6_S3_MEM_VREFDQ_A
70 21 20 19 18
PP0V6_S3_MEM_VREFDQ_B
70 23 22 19 18
5
PP0V6_S3_MEM_VREFCA_A
PP0V6_S3_MEM_VREFCA_B
4
VOLTAGE=0.6V
PP0V6_S3_MEM_VREFCA_A
MAKE_BASE=TRUE
VOLTAGE=0.6V
PP0V6_S3_MEM_VREFDQ_B
MAKE_BASE=TRUE
VOLTAGE=0.6V
PP0V6_S3_MEM_VREFCA_B
MAKE_BASE=TRUE
3
Project Chipset Support
DRAWING NUMBER
6 18
Apple Inc.
15 18
VOLTAGE=0.6V
18 19 20 21 70
18 19 20 21 70
18 19 22 23 70
18 19 22 23 70
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
R
PP0V6_S3_MEM_VREFDQ_A
MAKE_BASE=TRUE
70 23 22 19 18
6
TP_MEM_VDD_SEL_1V5_L
MAKE_BASE=TRUE
70 21 20 19 18
7
TP_CPU_MEM_RESET_L
MAKE_BASE=TRUE
SYNC_DATE=02/15/2013
PAGE TITLE
LPDDR3 Alias Support
8
OUT
DMN5L06VK-7
SOT-563
MAKE_BASE
TRUE
TRUE
No MAKE_BASE on TCK/TDI as these are provided on XDP page.
16 15
IN
BI
D2095
DMN5L06VK-7
2
IN
IN
DBGLED
SOT-563
59 58 28
BI
18 13
18 13
DMN5L06VK-7
59 37 36 29 18 13
BI
67 25 18 13
DBGLED_S0_D
DBGLED
D 3
IN
DBGLED_S0
DBGLED
A
D2092
DBGLED_S3_D
DBGLED
Q2090
K
DBGLED
OUT
IN
20K
DBGLED_S0I3
DP_TBTSNK0_DDC_CLK
DP_TBTSNK0_DDC_DATA
MAKE_BASE
5%
1/20W
MF
201 2
20K
DBGLED_S5
K
28 18 13
R20951
20K
A
2
DBGLED
R20901
B
0
5%
1/20W
MF
0201
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
20 OF 121
SHEET
18 OF 76
1
A
CPU-Based Margining
2
CRITICAL
G
DMN5L06VK-7
DDRVREF_DAC
SOT-563
1
D
100K
C2225
Always used, regardless
of margining option.
0.1UF
8.2K
1
Q2225 pin 6:
CPU_MEM_VREFCA_A_ISOL
DDRVREF_DAC
100K
SOT-563
D
2.2UF
40 25 19 16 14
69 56
10%
6.3V
2 CERM-X5R
0201
IN
SMBUS_PCH_DATA
9 A0
Addr=0x98(WR)/0x99(RD)
10 A1
VOUTC 4
R2226
R2246
R2266
R2286
VREFMRGN_CA_AB
VOUTD 5
GND
3
5
G
5
G
0.1UF
VREFMRGN_MEMVREG
1%
1
2
4.02K
1
2
1
2
1/20W
MF
MF
1/20W
MF
R22x6 pin 2:
201
PLACE_NEAR=Q2225.1:2.54mm
PLACE_NEAR=Q2265.1:2.54mm
PLACE_NEAR=Q2225.4:2.54mm
PLACE_NEAR=Q2265.4:2.54mm
201
201
VREFMRGN_CA_B_RDIV
1%
1/20W
MF
16
C2202
1
0.1UF
PCA9557
5
69 56 40 25 19 16 14
IN
BI
SMBUS_PCH_CLK
SMBUS_PCH_DATA
1
2
P1
P2
P3
P4
P5
P6
P7
A0
A1
A2
SCL
SDA
THRM
RST* on ’platform reset’ so that system
watchdog will disable margining.
7
9
10
11
12
13
14
IN
18 22 23 70
R22821
8.2K
1%
1/20W
MF
201 2
C2280
10%
2 6.3V
X5R-CERM
0201
R2280
MEM_VREFCA_B_RC
1
24.9 2
1%
1/20W
MF
201
15 18 19 33 36 40 41 58 62 64
B
C2
V+
DDRVREF_DAC
U2204
MAX4253
UCSP
C1
R2214
VREFMRGN_MEMVREG_BUF
38.3K
2
DDRREG_FB
1
1%
1/20W
MF
201
C4
VB4
OUT
53
PLACE_NEAR=R7415.2:1mm
CRITICAL
DDRVREF_DAC
DDRVREF_DAC
1
R2213
NC
100K
RESET* 15
5%
1/20W
MF
201 2
B1
A2
V+
A3
NOTE: Margining will be disabled across all
soft-resets and sleep/wake cycles.
18
B1
C3
GND
17
PAD
VREFMRGN_CPU_EN
VREFMRGN_DQ_A_EN
VREFMRGN_DQ_B_EN
VREFMRGN_CA_A_EN
VREFMRGN_CA_B_EN
VREFMRGN_MEMVREG_EN
VREFMRGN_SPARE_EN
6
8
4
PP0V6_S3_MEM_VREFCA_B
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
PLACE_NEAR=R2281.2:1mm
CRITICAL
DDRVREF_DAC
1
10%
6.3V
CERM-X5R 2
0201
5%
1/20W
MF
201 2
U2201
3
1%
1/20W
MF
2 201
PLACE_NEAR=Q2260.3:3mm
0.1UF
R22001
100K
(OD) P0
69 56 40 25 19 16 14
C2205
CRITICAL
DDRVREF_DAC
QFN
Addr=0x30(WR)/0x31(RD)
8.2K
NOTE: MEMVREG and SPARE share a
DAC output, cannot enable
both at the same time!
VCC
10%
6.3V
CERM-X5R 2
0201
R2281
2
201
PP3V3_S3
DDRVREF_DAC
24.9 2
0.022UF
VREFMRGN_CA_A_RDIV
1%
4.02K
1/20W
10
1
1%
1/20W
MF
201
1%
1/20W
MF
201
1
VREFMRGN_DQ_B_RDIV
1%
1
SOT-563
1
C
R2260
PLACE_NEAR=Q2260.3:2mm
(All 4 R’s)
DDRVREF_DAC
4.02K 1
2
VREFMRGN_DQ_A_RDIV
4.02K
1%
1/20W
MF
201 2
R2283
10%
6.3V
CERM-X5R 2
0201
DDRVREF_DAC
B
8.2K
DMN5L06VK-7
CRITICAL
8 DDRVREF_DAC
VDD
6 SCL U2200 VOUTA 1
VREFMRGN_DQ_A
MSOP
7 SDA
VREFMRGN_DQ_B
VOUTB 2
SMBUS_PCH_CLK
BI
C2285
5%
1/20W
MF
201 2
18 20 21 70
R2262
MEM_VREFCA_A_RC
Q2265
D
100K
C2201
0.1UF
20%
6.3V
CERM 2
402-LF
PP0V6_S3_MEM_VREFCA_A
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
3
R2207
DDRVREF_DAC
1
1%
1/20W
MF
2 201
PLACE_NEAR=Q2220.3:3mm
1
C2260
1
S
1
C2200 1
40 25 19 16 14
69 56
5%
1/20W
MF
201
VREFMRGN_CA_B_EN_RC
DDRVREF_DAC
8.2K
PLACE_NEAR=R2261.2:1mm
10%
2 6.3V
X5R-CERM
0201
CRITICAL
DDRVREF_DAC
R2285
100K 2
R2261
2
0.022UF
CPU_MEM_VREFCA_B_ISOL
DDRVREF_DAC
DDRVREF_DAC
DDRVREF_DAC
10
1%
1/20W
MF
201
4
NONE
NONE
NONE
402
1
PLACE_NEAR=Q2220.3:2mm
PP3V3_S3_VREFMRGN_DAC
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
R2263
0.1UF
1
24.9 2
1%
1/20W
MF
201
SOT-563
1
1
DAC5574
SHORT2
1
1
DMN5L06VK-7
1
10%
6.3V
CERM-X5R 2
0201
5%
1/20W
MF
201 2
1%
1/20W
MF
201 2
R2240
MEM_VREFDQ_B_RC
Q2225
18 22 23 70
8.2K
C2240
3
R2215
DMN5L06VK-7
C2265
S
1
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
R22421
10%
2 6.3V
X5R-CERM
0201
CRITICAL
DDRVREF_DAC
4
Q2260
5%
1/20W
MF
201
PP0V6_S3_MEM_VREFDQ_B
3
5
G
S
4
DDRVREF_DAC
8.2K
1%
1/20W
MF
2 201
PLACE_NEAR=Q2260.6:3mm
PLACE_NEAR=R2241.2:1mm
0.022UF
VREFMRGN_CA_A_EN_RC
DDRVREF_DAC
R2241
2
PLACE_NEAR=Q2260.6:2mm
1
R2218
PP3V3_S3
2
PLACE_NEAR=Q2260.6:2.54mm
CRITICAL
10
1%
1/20W
MF
201
SOT-563
DAC sets voltage level, PCA9557 & FETs enable outputs
and disables margining after platform reset.
OMIT
36 33 19 18 15
64 62 58 41 40
1
1
24.9 2
1%
1/20W
MF
201
SOT-563
Q2265 pin 6:
R2265
DAC-Based Margining
C
0.1UF
100K 2
1
1
R2243
10%
6.3V
CERM-X5R 2
0201
D
1%
1/20W
MF
201 2
DMN5L06VK-7
1
DMN5L06VK-7
3
CPU_DIMM_VREFCA
4
IN
S
7
Q2220
D
5
CRITICAL
NOTE: CPU has single output for
VREFCA. Split into two
signals for independent DAC
margining support. When
DAC margining VREFCA ensure
VREFMRGN_CPU_EN is low
to remove short due to CPU.
C2245
5%
1/20W
MF
201 2
8.2K
R2220
MEM_VREFDQ_A_RC
Q2265
D
100K
R2222
6
R2202
step sizes:
7.70mV per step
6.99mV per step
?.??mV per step
G
NOTE: CPU DAC output
DDR3
(1.5V)
DDR3L (1.35V)
LPDDR3 (1.2V)
G
5%
1/20W
MF
201
1
VREFMRGN_DQ_B_EN_RC
DDRVREF_DAC
S
DDRVREF_DAC
100K 2
18 20 21 70
1
10%
2 6.3V
X5R-CERM
0201
CRITICAL
DDRVREF_DAC
1
D
6
1
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
PLACE_NEAR=R2221.2:1mm
C2220
D
2
G
S
1
IN
CPU_DIMMB_VREFDQ
PP0V6_S3_MEM_VREFDQ_A
2
0.022UF
R2245
7
10
PLACE_NEAR=Q2220.6:2mm
CRITICAL
SOT-563
1%
1/20W
MF
2 201
PLACE_NEAR=Q2220.6:3mm
1%
1/20W
MF
201
1
DMN5L06VK-7
17 20 21 22 23 42 53 62 70
R2221
SOT-563
PLACE_NEAR=Q2220.6:2.54mm
CPU_MEM_VREFDQ_B_ISOL
DDRVREF_DAC
PP1V2_S3
1
DMN5L06VK-7
R2223
BOM options provided by this page:
- DDRVREF_DAC - Stuffs DAC margining circuit.
Q2260
1
Q2225
1
10%
6.3V
CERM-X5R 2
0201
5%
1/20W
MF
201 2
6
S
CPU_DIMMA_VREFDQ
1
IN
DDRVREF_DAC
5%
1/20W
MF
201
R2201
7
CRITICAL
DDRVREF_DAC
2
Q2220
2
VRef Dividers
CPU_MEM_VREFDQ_A_ISOL
DDRVREF_DAC EN RC’s to avoid drain glitches
May not be necessary due to C22x0
R2225
100K 2
1
VREFMRGN_DQ_A_EN_RC
FETs for CPU isolation during DAC margining
Signal aliases required by this page:
- =I2C_VREFDACS_SCL
- =I2C_VREFDACS_SDA
- =I2C_PCA9557D_SCL
- =I2C_PCA9557D_SDA
3
6
Power aliases required by this page:
- =PP3V3_S3_VREFMRGN
- =PPDDR_S3_MEMVREF
D
4
G
Page Notes
5
D
6
S
7
1
8
U2204
MAX4253
UCSP
A1
VREFMRGN_SPARE_BUF
DDRVREF_DAC
A4
V-
1
R2217
B4
Pins B1 & B4:
CKPLUS_WAIVE=unconnected_pins
PCA9557D_RESET_L
DDRVREF_DAC
1M
5%
1/20W
MF
2 201
R22121
100K
MEM A VREF DQ
A
DAC Channel:
PCA9557D Pin:
MEM B VREF DQ
MEM A VREF CA
MEM B VREF CA
A
B
C
C
1
2
3
4
LPDDR3 (1.2V)
Nominal value
SYNC_MASTER=J41_MLB
DDR3 VREF MARGINING
5
0.675V (DAC: 0x34)
DDR3L (1.35V)
1.200V (DAC: 0x5D)
Margined target:
0.300V - 0.900V (+/- 300mV)
0.337V - 1.013V (+/- 337.5mV)
0.800V - 1.600V (+/- 400mV)
0.972V - 1.714V (+/- 371mV)
DAC range:
0.000V - 1.199V (0x00 - 0x5D)
0.000V - 1.354V (0x00 - 0x69)
0.000V - 2.397V (0x00 - 0xBA)
0.000V - 2.694V (0x00 - 0xD1)
VRef current:
DAC step size:
8
+73uA - -73uA
(- = sourced)
6.36mV / step @ output
+82uA - -82uA
(- = sourced)
6.36mV / step @ output
7
+21uA -
-21uA (- = sourced)
+25uA -
4.28mV / step @ output
6
DRAWING NUMBER
NOTE: LPDDR3 assumes TPS51916 supply with 28.7k/57.6k divider
DDR3L assumes TPS51916 supply with 19.6k/57.6k divider
1.343V (DAC: 0x68)
LPDDR3 (1.2V)
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
-25uA (- = sourced)
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
3.53mV / step @ output
5
SYNC_DATE=02/12/2013
PAGE TITLE
D
DDR3L (1.35V)
0.600V (DAC: 0x2E.5)
5%
1/20W
MF
201 2
MEM VREG
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
22 OF 121
SHEET
19 OF 76
1
A
8
7
6
5
4
3
2
1
LPDDR3 CHANNEL A (0-31)
D
D
U2300
U2300
LPDDR3-16GB
LPDDR3-16GB
FBGA
70 63 24
IN
70 63 24
IN
70 63 24
IN
70 63 24
IN
70 63 24
IN
70 63 24 7
IN
70 63 24
IN
70 63 24
IN
70 63 24
IN
70 24 7
70 24 7
IN
70 24 7
IN
70 24 7
IN
70 24 21 7
IN
70 24 21 7
C
IN
IN
MEM_A_CAA & lt; 0 & gt;
MEM_A_CAA & lt; 1 & gt;
MEM_A_CAA & lt; 2 & gt;
MEM_A_CAA & lt; 3 & gt;
MEM_A_CAA & lt; 4 & gt;
MEM_A_CAA & lt; 5 & gt;
MEM_A_CAA & lt; 6 & gt;
MEM_A_CAA & lt; 7 & gt;
MEM_A_CAA & lt; 8 & gt;
MEM_A_CAA & lt; 9 & gt;
R2
P2
N2
N3
M3
F3
E3
E2
D2
C2
MEM_A_CKE & lt; 0 & gt;
MEM_A_CKE & lt; 1 & gt;
K3 CKE0
K4 CKE1
MEM_A_CLK_P & lt; 0 & gt;
MEM_A_CLK_N & lt; 0 & gt;
J3 CK_T
J2 CK_C
MEM_A_CS_L & lt; 0 & gt;
MEM_A_CS_L & lt; 1 & gt;
L3 CS0*
L4 CS1*
L8
G8
P8
D8
70 63 24 21 7
IN
243
243
1%
1/20W
MF
201 2
1%
1/20W
MF
201 2
70 21 19 18
70 21 19 18
C2340 1
0.047UF
10%
6.3V
X5R 2
201
1
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
0.047UF
10%
6.3V
2 X5R
201
B
NC
NC
NC
=MEM_A_DQS_N & lt; 0 & gt;
=MEM_A_DQS_N & lt; 1 & gt;
=MEM_A_DQS_N & lt; 2 & gt;
=MEM_A_DQS_N & lt; 3 & gt;
DQS0_T
DQS1_T
DQS2_T
DQS3_T
L10
G10
P10
D10
=MEM_A_DQS_P & lt; 0 & gt;
=MEM_A_DQS_P & lt; 1 & gt;
=MEM_A_DQS_P & lt; 2 & gt;
=MEM_A_DQS_P & lt; 3 & gt;
CRITICAL
DM0
DM1
DM2
DM3
A1
A2
A12
A13
B1
B13
T1
T13
U1
U2
U12
U13
C4
K9
R3
NU
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
C2300
0.1UF
10%
16V
2 X5R-CERM
0201
70 62 53 42 23 22 21 20 19 17
70 62 53 42 23 22 21 20 19 17
70 62 53 42 23 22 21 20 19 17
NC
1
C2301
0.1UF
10%
16V
2 X5R-CERM
0201
1
C2302
1UF
10%
10V
2 X5R
402
1
C2303
1UF
10%
10V
2 X5R
402
1
C2304
1UF
10%
10V
2 X5R
402
1
(2 OF 2)
63
BI
A3
A4
A5
A6
A10
U3
U4
U5
U6
U10
63
BI
PP1V8_S3
63
BI
62 57 23 22 21 20
PP1V2_S3
1
C2305
1UF
10%
10V
2 X5R
402
1
C2306
10UF
20%
25V
2 X5R-CERM
0603
1
C2307
10UF
20%
25V
2 X5R-CERM
0603
PP1V2_S3
PP1V2_S3
PP1V2_S3
A8
A9
D4
D5
D6
G5
H5
H6
H12
J5
J6
K5
K6
K12
L5
P4
P5
P6
U8
U9
F2
G2
H3
L2
M2
A11
C12
E8
E12
G12
H8
H9
H11
J9
J10
K8
K11
L12
N8
N12
R12
U11
VDD1
OMIT_TABLE
VSS
CRITICAL
VDD2
VSSCA
VDDCA
VSSQ
VDDQ
B2
B5
C5
E4
E5
F5
J12
K2
L6
M5
N4
N5
R4
R5
T2
T3
T4
T5
H2
C
C3
D3
F4
G3
G4
P3
M4
J4
B6
B12
C6
D12
E6
F6
F12
G6
G9
H10
K10
L9
M6
M12
N6
P12
R6
T6
T12
B
PP1V2_S3
1
C2320
1UF
10%
10V
2 X5R
402
70 62 53 42 23 22 21 20 19 17
DQS0_C
DQS1_C
DQS2_C
DQS3_C
L11
G11
P11
D11
OMIT_TABLE
H4 VREFCA
J11 VREFDQ
C2341
70 62 53 42 23 22 21 20 19 17
=MEM_A_DQ & lt; 0 & gt;
=MEM_A_DQ & lt; 1 & gt;
=MEM_A_DQ & lt; 2 & gt;
=MEM_A_DQ & lt; 3 & gt;
=MEM_A_DQ & lt; 4 & gt;
=MEM_A_DQ & lt; 5 & gt;
=MEM_A_DQ & lt; 6 & gt;
=MEM_A_DQ & lt; 7 & gt;
=MEM_A_DQ & lt; 8 & gt;
=MEM_A_DQ & lt; 9 & gt;
=MEM_A_DQ & lt; 10 & gt;
=MEM_A_DQ & lt; 11 & gt;
=MEM_A_DQ & lt; 12 & gt;
=MEM_A_DQ & lt; 13 & gt;
=MEM_A_DQ & lt; 14 & gt;
=MEM_A_DQ & lt; 15 & gt;
=MEM_A_DQ & lt; 16 & gt;
=MEM_A_DQ & lt; 17 & gt;
=MEM_A_DQ & lt; 18 & gt;
=MEM_A_DQ & lt; 19 & gt;
=MEM_A_DQ & lt; 20 & gt;
=MEM_A_DQ & lt; 21 & gt;
=MEM_A_DQ & lt; 22 & gt;
=MEM_A_DQ & lt; 23 & gt;
=MEM_A_DQ & lt; 24 & gt;
=MEM_A_DQ & lt; 25 & gt;
=MEM_A_DQ & lt; 26 & gt;
=MEM_A_DQ & lt; 27 & gt;
=MEM_A_DQ & lt; 28 & gt;
=MEM_A_DQ & lt; 29 & gt;
=MEM_A_DQ & lt; 30 & gt;
=MEM_A_DQ & lt; 31 & gt;
B3 ZQ0
B4 ZQ1
PP0V6_S3_MEM_VREFCA_A
PP0V6_S3_MEM_VREFDQ_A
70 62 53 42 23 22 21 20 19 17
P9
N9
N10
N11
M8
M9
M10
M11
F11
F10
F9
F8
E11
E10
E9
D9
T8
T9
T10
T11
R8
R9
R10
R11
C11
C10
C9
C8
B11
B10
B9
B8
J8 ODT
MEM_A_ODT & lt; 0 & gt;
MEM_A_ZQ & lt; 0 & gt;
MEM_A_ZQ & lt; 1 & gt;
R23001 R23011
FBGA
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
(1 OF 2)
CA0
CA1
CA2
CA3
CA4
CA5
CA6
CA7
CA8
CA9
EDFA232A1MA-GD-F
IN
EDFA232A1MA-GD-F
70 63 24
1
C2321
1UF
10%
10V
2 X5R
402
1
C2322
1UF
10%
10V
2 X5R
402
1
C2323
10UF
20%
25V
2 X5R-CERM
0603
1
C2324
10UF
20%
25V
2 X5R-CERM
0603
PP1V2_S3
1
C2310
1UF
A
10%
10V
2 X5R
402
1
C2311
1UF
10%
10V
2 X5R
402
1
PLACEMENT_NOTE:
C2312
10UF
20%
25V
2 X5R-CERM
0603
10uF caps are shared between DRAM.
Distribute evenly.
SYNC_MASTER=J41_MLB
SYNC_DATE=02/06/2013
PAGE TITLE
LPDDR3 DRAM Channel A (0-31)
DRAWING NUMBER
62 57 23 22 21 20
PP1V8_S3
Apple Inc.
1
C2330
1UF
10%
10V
2 X5R
402
8
7
1
C2331
1UF
10%
10V
2 X5R
402
6
1
C2332
10UF
20%
25V
2 X5R-CERM
0603
1
& lt; SCH_NUM & gt;
REVISION
R
C2333
10UF
NOTICE OF PROPRIETARY PROPERTY:
20%
25V
2 X5R-CERM
0603
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
5
4
3
2
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
23 OF 121
SHEET
20 OF 76
1
SIZE
D
A
8
7
6
5
4
3
2
1
LPDDR3 CHANNEL A (32-63)
D
D
U2400
U2400
LPDDR3-16GB
LPDDR3-16GB
FBGA
70 63 24
IN
70 63 24
IN
70 63 24
IN
70 63 24
IN
70 63 24
IN
70 63 24 7
IN
70 63 24
IN
70 63 24
IN
70 63 24
IN
70 24 7
70 24 7
IN
70 24 7
IN
70 24 7
IN
70 24 20 7
IN
70 24 20 7
C
IN
IN
MEM_A_CAB & lt; 0 & gt;
MEM_A_CAB & lt; 1 & gt;
MEM_A_CAB & lt; 2 & gt;
MEM_A_CAB & lt; 3 & gt;
MEM_A_CAB & lt; 4 & gt;
MEM_A_CAB & lt; 5 & gt;
MEM_A_CAB & lt; 6 & gt;
MEM_A_CAB & lt; 7 & gt;
MEM_A_CAB & lt; 8 & gt;
MEM_A_CAB & lt; 9 & gt;
R2
P2
N2
N3
M3
F3
E3
E2
D2
C2
MEM_A_CKE & lt; 2 & gt;
MEM_A_CKE & lt; 3 & gt;
K3 CKE0
K4 CKE1
MEM_A_CLK_P & lt; 1 & gt;
MEM_A_CLK_N & lt; 1 & gt;
J3 CK_T
J2 CK_C
MEM_A_CS_L & lt; 0 & gt;
MEM_A_CS_L & lt; 1 & gt;
L3 CS0*
L4 CS1*
L8
G8
P8
D8
70 63 24 20 7
IN
243
243
1%
1/20W
MF
201 2
1%
1/20W
MF
201 2
70 20 19 18
70 20 19 18
C2440 1
0.047UF
10%
6.3V
X5R 2
201
1
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
0.047UF
10%
6.3V
2 X5R
201
B
NC
NC
NC
=MEM_A_DQS_N & lt; 4 & gt;
=MEM_A_DQS_N & lt; 5 & gt;
MEM_A_DQS_N & lt; 6 & gt;
=MEM_A_DQS_N & lt; 7 & gt;
DQS0_T
DQS1_T
DQS2_T
DQS3_T
L10
G10
P10
D10
=MEM_A_DQS_P & lt; 4 & gt;
=MEM_A_DQS_P & lt; 5 & gt;
MEM_A_DQS_P & lt; 6 & gt;
=MEM_A_DQS_P & lt; 7 & gt;
CRITICAL
DM0
DM1
DM2
DM3
A1
A2
A12
A13
B1
B13
T1
T13
U1
U2
U12
U13
C4
K9
R3
NU
BI
BI
63
BI
63
BI
63
BI
63
BI
63
BI
C2400
0.1UF
10%
16V
2 X5R-CERM
0201
63
BI
63
BI
63
BI
63
BI
63
BI
7 63 70
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
BI
63
BI
63
C2401
0.1UF
10%
16V
2 X5R-CERM
0201
1
C2402
1UF
10%
10V
2 X5R
402
1
C2403
1UF
10%
10V
2 X5R
402
1
C2404
1UF
10%
10V
2 X5R
402
1
A3
A4
A5
A6
A10
U3
U4
U5
U6
U10
(2 OF 2)
VDD1
63
70 62 53 42 23 22 21 20 19 17
70 62 53 42 23 22 21 20 19 17
BI
63
BI
63
BI
7 63 70
BI
63
A8
A9
D4
D5
D6
G5
H5
H6
H12
J5
J6
K5
K6
K12
L5
P4
P5
P6
U8
U9
F2
G2
H3
L2
M2
OMIT_TABLE
VSS
CRITICAL
VDD2
VSSCA
VDDCA
63
BI
PP1V2_S3
7 63 70
BI
PP1V2_S3
63
BI
70 62 53 42 23 22 21 20 19 17
NC
1
PP1V8_S3
63
BI
62 57 23 22 21 20
63
PP1V2_S3
1
C2405
1UF
10%
10V
2 X5R
402
1
C2406
10UF
20%
25V
2 X5R-CERM
0603
PP1V2_S3
A11
C12
E8
E12
G12
H8
H9
H11
J9
J10
K8
K11
L12
N8
N12
R12
U11
VSSQ
VDDQ
B2
B5
C5
E4
E5
F5
J12
K2
L6
M5
N4
N5
R4
R5
T2
T3
T4
T5
H2
C
C3
D3
F4
G3
G4
P3
M4
J4
B6
B12
C6
D12
E6
F6
F12
G6
G9
H10
K10
L9
M6
M12
N6
P12
R6
T6
T12
B
PP1V2_S3
1
C2420
1UF
10%
10V
2 X5R
402
70 62 53 42 23 22 21 20 19 17
DQS0_C
DQS1_C
DQS2_C
DQS3_C
L11
G11
P11
D11
OMIT_TABLE
H4 VREFCA
J11 VREFDQ
C2441
70 62 53 42 23 22 21 20 19 17
=MEM_A_DQ & lt; 32 & gt;
=MEM_A_DQ & lt; 33 & gt;
=MEM_A_DQ & lt; 34 & gt;
=MEM_A_DQ & lt; 35 & gt;
=MEM_A_DQ & lt; 36 & gt;
=MEM_A_DQ & lt; 37 & gt;
=MEM_A_DQ & lt; 38 & gt;
=MEM_A_DQ & lt; 39 & gt;
=MEM_A_DQ & lt; 40 & gt;
=MEM_A_DQ & lt; 41 & gt;
=MEM_A_DQ & lt; 42 & gt;
=MEM_A_DQ & lt; 43 & gt;
MEM_A_DQ & lt; 32 & gt;
=MEM_A_DQ & lt; 45 & gt;
=MEM_A_DQ & lt; 46 & gt;
=MEM_A_DQ & lt; 47 & gt;
=MEM_A_DQ & lt; 48 & gt;
=MEM_A_DQ & lt; 49 & gt;
=MEM_A_DQ & lt; 50 & gt;
=MEM_A_DQ & lt; 51 & gt;
=MEM_A_DQ & lt; 52 & gt;
=MEM_A_DQ & lt; 53 & gt;
=MEM_A_DQ & lt; 54 & gt;
=MEM_A_DQ & lt; 55 & gt;
=MEM_A_DQ & lt; 56 & gt;
=MEM_A_DQ & lt; 57 & gt;
=MEM_A_DQ & lt; 58 & gt;
=MEM_A_DQ & lt; 59 & gt;
=MEM_A_DQ & lt; 60 & gt;
=MEM_A_DQ & lt; 61 & gt;
=MEM_A_DQ & lt; 62 & gt;
=MEM_A_DQ & lt; 63 & gt;
B3 ZQ0
B4 ZQ1
PP0V6_S3_MEM_VREFCA_A
PP0V6_S3_MEM_VREFDQ_A
70 62 53 42 23 22 21 20 19 17
P9
N9
N10
N11
M8
M9
M10
M11
F11
F10
F9
F8
E11
E10
E9
D9
T8
T9
T10
T11
R8
R9
R10
R11
C11
C10
C9
C8
B11
B10
B9
B8
J8 ODT
MEM_A_ODT & lt; 0 & gt;
MEM_A_ZQ & lt; 2 & gt;
MEM_A_ZQ & lt; 3 & gt;
R24001 R24011
FBGA
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
(1 OF 2)
CA0
CA1
CA2
CA3
CA4
CA5
CA6
CA7
CA8
CA9
EDFA232A1MA-GD-F
IN
EDFA232A1MA-GD-F
70 63 24
1
C2421
1UF
10%
10V
2 X5R
402
1
C2422
1UF
10%
10V
2 X5R
402
1
C2423
10UF
20%
25V
2 X5R-CERM
0603
PP1V2_S3
1
C2410
1UF
A
10%
10V
2 X5R
402
1
C2411
1UF
10%
10V
2 X5R
402
1
PLACEMENT_NOTE:
C2412
10UF
20%
25V
2 X5R-CERM
0603
10uF caps are shared between DRAM.
Distribute evenly.
SYNC_MASTER=J41_MLB
SYNC_DATE=02/06/2013
PAGE TITLE
LPDDR3 DRAM Channel A (32-63)
DRAWING NUMBER
62 57 23 22 21 20
PP1V8_S3
Apple Inc.
1
C2430
1UF
10%
10V
2 X5R
402
8
7
1
C2431
1UF
10%
10V
2 X5R
402
6
1
& lt; SCH_NUM & gt;
REVISION
R
C2432
10UF
NOTICE OF PROPRIETARY PROPERTY:
20%
25V
2 X5R-CERM
0603
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
5
4
3
2
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
24 OF 121
SHEET
21 OF 76
1
SIZE
D
A
8
7
6
5
4
3
2
1
LPDDR3 CHANNEL B (0-31)
D
D
U2500
U2500
LPDDR3-16GB
LPDDR3-16GB
FBGA
70 63 24
IN
70 63 24
IN
70 63 24
IN
70 63 24
IN
70 63 24
IN
70 63 24 7
IN
70 63 24
IN
70 63 24
IN
70 63 24
IN
70 24 7
70 24 7
IN
70 24 7
IN
70 24 7
IN
70 24 23 7
IN
70 24 23 7
C
IN
IN
MEM_B_CAA & lt; 0 & gt;
MEM_B_CAA & lt; 1 & gt;
MEM_B_CAA & lt; 2 & gt;
MEM_B_CAA & lt; 3 & gt;
MEM_B_CAA & lt; 4 & gt;
MEM_B_CAA & lt; 5 & gt;
MEM_B_CAA & lt; 6 & gt;
MEM_B_CAA & lt; 7 & gt;
MEM_B_CAA & lt; 8 & gt;
MEM_B_CAA & lt; 9 & gt;
R2
P2
N2
N3
M3
F3
E3
E2
D2
C2
MEM_B_CKE & lt; 0 & gt;
MEM_B_CKE & lt; 1 & gt;
K3 CKE0
K4 CKE1
MEM_B_CLK_P & lt; 0 & gt;
MEM_B_CLK_N & lt; 0 & gt;
J3 CK_T
J2 CK_C
MEM_B_CS_L & lt; 0 & gt;
MEM_B_CS_L & lt; 1 & gt;
L3 CS0*
L4 CS1*
L8
G8
P8
D8
70 63 24 23 7
IN
243
243
1%
1/20W
MF
201 2
1%
1/20W
MF
201 2
70 23 19 18
70 23 19 18
C2540 1
0.047UF
10%
6.3V
X5R 2
201
1
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
0.047UF
10%
6.3V
2 X5R
201
B
NC
NC
NC
=MEM_B_DQS_N & lt; 0 & gt;
=MEM_B_DQS_N & lt; 1 & gt;
=MEM_B_DQS_N & lt; 2 & gt;
=MEM_B_DQS_N & lt; 3 & gt;
DQS0_T
DQS1_T
DQS2_T
DQS3_T
L10
G10
P10
D10
=MEM_B_DQS_P & lt; 0 & gt;
=MEM_B_DQS_P & lt; 1 & gt;
=MEM_B_DQS_P & lt; 2 & gt;
=MEM_B_DQS_P & lt; 3 & gt;
CRITICAL
DM0
DM1
DM2
DM3
A1
A2
A12
A13
B1
B13
T1
T13
U1
U2
U12
U13
C4
K9
R3
NU
BI
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
C2500
0.1UF
10%
16V
2 X5R-CERM
0201
70 62 53 42 23 22 21 20 19 17
70 62 53 42 23 22 21 20 19 17
70 62 53 42 23 22 21 20 19 17
NC
1
C2501
0.1UF
10%
16V
2 X5R-CERM
0201
1
C2502
1UF
10%
10V
2 X5R
402
1
C2503
1UF
10%
10V
2 X5R
402
1
C2504
1UF
10%
10V
2 X5R
402
1
(2 OF 2)
63
BI
A3
A4
A5
A6
A10
U3
U4
U5
U6
U10
63
BI
PP1V8_S3
63
BI
62 57 23 22 21 20
63
PP1V2_S3
1
C2505
1UF
10%
10V
2 X5R
402
1
C2506
10UF
20%
25V
2 X5R-CERM
0603
PP1V2_S3
PP1V2_S3
PP1V2_S3
A8
A9
D4
D5
D6
G5
H5
H6
H12
J5
J6
K5
K6
K12
L5
P4
P5
P6
U8
U9
F2
G2
H3
L2
M2
A11
C12
E8
E12
G12
H8
H9
H11
J9
J10
K8
K11
L12
N8
N12
R12
U11
VDD1
OMIT_TABLE
VSS
CRITICAL
VDD2
VSSCA
VDDCA
VSSQ
VDDQ
B2
B5
C5
E4
E5
F5
J12
K2
L6
M5
N4
N5
R4
R5
T2
T3
T4
T5
H2
C
C3
D3
F4
G3
G4
P3
M4
J4
B6
B12
C6
D12
E6
F6
F12
G6
G9
H10
K10
L9
M6
M12
N6
P12
R6
T6
T12
B
PP1V2_S3
1
C2520
1UF
10%
10V
2 X5R
402
70 62 53 42 23 22 21 20 19 17
DQS0_C
DQS1_C
DQS2_C
DQS3_C
L11
G11
P11
D11
OMIT_TABLE
H4 VREFCA
J11 VREFDQ
C2541
70 62 53 42 23 22 21 20 19 17
=MEM_B_DQ & lt; 0 & gt;
=MEM_B_DQ & lt; 1 & gt;
=MEM_B_DQ & lt; 2 & gt;
=MEM_B_DQ & lt; 3 & gt;
=MEM_B_DQ & lt; 4 & gt;
=MEM_B_DQ & lt; 5 & gt;
=MEM_B_DQ & lt; 6 & gt;
=MEM_B_DQ & lt; 7 & gt;
=MEM_B_DQ & lt; 8 & gt;
=MEM_B_DQ & lt; 9 & gt;
=MEM_B_DQ & lt; 10 & gt;
=MEM_B_DQ & lt; 11 & gt;
=MEM_B_DQ & lt; 12 & gt;
=MEM_B_DQ & lt; 13 & gt;
=MEM_B_DQ & lt; 14 & gt;
=MEM_B_DQ & lt; 15 & gt;
=MEM_B_DQ & lt; 16 & gt;
=MEM_B_DQ & lt; 17 & gt;
=MEM_B_DQ & lt; 18 & gt;
=MEM_B_DQ & lt; 19 & gt;
=MEM_B_DQ & lt; 20 & gt;
=MEM_B_DQ & lt; 21 & gt;
=MEM_B_DQ & lt; 22 & gt;
=MEM_B_DQ & lt; 23 & gt;
=MEM_B_DQ & lt; 24 & gt;
=MEM_B_DQ & lt; 25 & gt;
=MEM_B_DQ & lt; 26 & gt;
=MEM_B_DQ & lt; 27 & gt;
=MEM_B_DQ & lt; 28 & gt;
=MEM_B_DQ & lt; 29 & gt;
=MEM_B_DQ & lt; 30 & gt;
=MEM_B_DQ & lt; 31 & gt;
B3 ZQ0
B4 ZQ1
PP0V6_S3_MEM_VREFCA_B
PP0V6_S3_MEM_VREFDQ_B
70 62 53 42 23 22 21 20 19 17
P9
N9
N10
N11
M8
M9
M10
M11
F11
F10
F9
F8
E11
E10
E9
D9
T8
T9
T10
T11
R8
R9
R10
R11
C11
C10
C9
C8
B11
B10
B9
B8
J8 ODT
MEM_B_ODT & lt; 0 & gt;
MEM_B_ZQ & lt; 0 & gt;
MEM_B_ZQ & lt; 1 & gt;
R25001 R25011
FBGA
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
(1 OF 2)
CA0
CA1
CA2
CA3
CA4
CA5
CA6
CA7
CA8
CA9
EDFA232A1MA-GD-F
IN
EDFA232A1MA-GD-F
70 63 24
1
C2521
1UF
10%
10V
2 X5R
402
1
C2522
1UF
10%
10V
2 X5R
402
1
C2523
10UF
20%
25V
2 X5R-CERM
0603
PP1V2_S3
1
C2510
1UF
A
10%
10V
2 X5R
402
1
C2511
1UF
10%
10V
2 X5R
402
1
PLACEMENT_NOTE:
C2512
10UF
20%
25V
2 X5R-CERM
0603
10uF caps are shared between DRAM.
Distribute evenly.
SYNC_MASTER=J41_MLB
SYNC_DATE=02/06/2013
PAGE TITLE
LPDDR3 DRAM Channel B (0-31)
DRAWING NUMBER
62 57 23 22 21 20
PP1V8_S3
Apple Inc.
1
C2530
1UF
10%
10V
2 X5R
402
8
7
1
C2531
1UF
10%
10V
2 X5R
402
6
1
& lt; SCH_NUM & gt;
REVISION
R
C2532
10UF
NOTICE OF PROPRIETARY PROPERTY:
20%
25V
2 X5R-CERM
0603
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
5
4
3
2
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
25 OF 121
SHEET
22 OF 76
1
SIZE
D
A
8
7
6
5
4
3
2
1
LPDDR3 CHANNEL B (32-63)
D
D
U2600
U2600
LPDDR3-16GB
LPDDR3-16GB
FBGA
70 63 24
IN
70 63 24
IN
70 63 24
IN
70 63 24
IN
70 63 24
IN
70 63 24 7
IN
70 63 24
IN
70 63 24
IN
70 63 24
IN
70 24 7
IN
70 24 7
IN
70 24 7
IN
70 24 22 7
IN
70 24 22 7
C
IN
70 24 7
IN
MEM_B_CAB & lt; 0 & gt;
MEM_B_CAB & lt; 1 & gt;
MEM_B_CAB & lt; 2 & gt;
MEM_B_CAB & lt; 3 & gt;
MEM_B_CAB & lt; 4 & gt;
MEM_B_CAB & lt; 5 & gt;
MEM_B_CAB & lt; 6 & gt;
MEM_B_CAB & lt; 7 & gt;
MEM_B_CAB & lt; 8 & gt;
MEM_B_CAB & lt; 9 & gt;
R2
P2
N2
N3
M3
F3
E3
E2
D2
C2
MEM_B_CKE & lt; 2 & gt;
MEM_B_CKE & lt; 3 & gt;
K3 CKE0
K4 CKE1
MEM_B_CLK_P & lt; 1 & gt;
MEM_B_CLK_N & lt; 1 & gt;
J3 CK_T
J2 CK_C
MEM_B_CS_L & lt; 0 & gt;
MEM_B_CS_L & lt; 1 & gt;
L3 CS0*
L4 CS1*
L8
G8
P8
D8
70 63 24 22 7
IN
243
243
1%
1/20W
MF
201 2
1%
1/20W
MF
201 2
70 22 19 18
70 22 19 18
C2640 1
0.047UF
10%
6.3V
X5R 2
201
1
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
0.047UF
10%
6.3V
2 X5R
201
B
NC
NC
NC
=MEM_B_DQS_N & lt; 4 & gt;
=MEM_B_DQS_N & lt; 5 & gt;
=MEM_B_DQS_N & lt; 6 & gt;
MEM_B_DQS_N & lt; 6 & gt;
DQS0_T
DQS1_T
DQS2_T
DQS3_T
L10
G10
P10
D10
=MEM_B_DQS_P & lt; 4 & gt;
=MEM_B_DQS_P & lt; 5 & gt;
=MEM_B_DQS_P & lt; 6 & gt;
MEM_B_DQS_P & lt; 6 & gt;
CRITICAL
DM0
DM1
DM2
DM3
A1
A2
A12
A13
B1
B13
T1
T13
U1
U2
U12
U13
C4
K9
R3
NU
BI
BI
63
BI
C2600
0.1UF
10%
16V
2 X5R-CERM
0201
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
7 63 70
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
63
BI
7 63 70
C2601
0.1UF
10%
16V
2 X5R-CERM
0201
1
C2602
1UF
10%
10V
2 X5R
402
1
C2603
1UF
10%
10V
2 X5R
402
1
C2604
1UF
10%
10V
2 X5R
402
1
(2 OF 2)
VDD1
7 63 70
BI
A3
A4
A5
A6
A10
U3
U4
U5
U6
U10
63
70 62 53 42 23 22 21 20 19 17
70 62 53 42 23 22 21 20 19 17
70 62 53 42 23 22 21 20 19 17
NC
1
PP1V8_S3
63
BI
62 57 23 22 21 20
63
PP1V2_S3
1
C2605
1UF
10%
10V
2 X5R
402
1
C2606
10UF
20%
25V
2 X5R-CERM
0603
PP1V2_S3
PP1V2_S3
PP1V2_S3
A8
A9
D4
D5
D6
G5
H5
H6
H12
J5
J6
K5
K6
K12
L5
P4
P5
P6
U8
U9
F2
G2
H3
L2
M2
A11
C12
E8
E12
G12
H8
H9
H11
J9
J10
K8
K11
L12
N8
N12
R12
U11
OMIT_TABLE
VSS
CRITICAL
VDD2
VSSCA
VDDCA
VSSQ
VDDQ
B2
B5
C5
E4
E5
F5
J12
K2
L6
M5
N4
N5
R4
R5
T2
T3
T4
T5
H2
C
C3
D3
F4
G3
G4
P3
M4
J4
B6
B12
C6
D12
E6
F6
F12
G6
G9
H10
K10
L9
M6
M12
N6
P12
R6
T6
T12
B
PP1V2_S3
1
C2620
1UF
10%
10V
2 X5R
402
70 62 53 42 23 22 21 20 19 17
DQS0_C
DQS1_C
DQS2_C
DQS3_C
L11
G11
P11
D11
OMIT_TABLE
H4 VREFCA
J11 VREFDQ
C2641
70 62 53 42 23 22 21 20 19 17
=MEM_B_DQ & lt; 32 & gt;
=MEM_B_DQ & lt; 33 & gt;
=MEM_B_DQ & lt; 34 & gt;
=MEM_B_DQ & lt; 35 & gt;
=MEM_B_DQ & lt; 36 & gt;
=MEM_B_DQ & lt; 37 & gt;
=MEM_B_DQ & lt; 38 & gt;
=MEM_B_DQ & lt; 39 & gt;
=MEM_B_DQ & lt; 40 & gt;
MEM_B_DQ & lt; 33 & gt;
=MEM_B_DQ & lt; 42 & gt;
=MEM_B_DQ & lt; 43 & gt;
=MEM_B_DQ & lt; 44 & gt;
=MEM_B_DQ & lt; 45 & gt;
=MEM_B_DQ & lt; 46 & gt;
=MEM_B_DQ & lt; 47 & gt;
=MEM_B_DQ & lt; 48 & gt;
=MEM_B_DQ & lt; 49 & gt;
=MEM_B_DQ & lt; 50 & gt;
=MEM_B_DQ & lt; 51 & gt;
=MEM_B_DQ & lt; 52 & gt;
=MEM_B_DQ & lt; 53 & gt;
=MEM_B_DQ & lt; 54 & gt;
=MEM_B_DQ & lt; 55 & gt;
=MEM_B_DQ & lt; 56 & gt;
=MEM_B_DQ & lt; 57 & gt;
=MEM_B_DQ & lt; 58 & gt;
=MEM_B_DQ & lt; 59 & gt;
=MEM_B_DQ & lt; 60 & gt;
=MEM_B_DQ & lt; 61 & gt;
=MEM_B_DQ & lt; 62 & gt;
=MEM_B_DQ & lt; 63 & gt;
B3 ZQ0
B4 ZQ1
PP0V6_S3_MEM_VREFCA_B
PP0V6_S3_MEM_VREFDQ_B
70 62 53 42 23 22 21 20 19 17
P9
N9
N10
N11
M8
M9
M10
M11
F11
F10
F9
F8
E11
E10
E9
D9
T8
T9
T10
T11
R8
R9
R10
R11
C11
C10
C9
C8
B11
B10
B9
B8
J8 ODT
MEM_B_ODT & lt; 0 & gt;
MEM_B_ZQ & lt; 2 & gt;
MEM_B_ZQ & lt; 3 & gt;
R26001 R26011
FBGA
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
(1 OF 2)
CA0
CA1
CA2
CA3
CA4
CA5
CA6
CA7
CA8
CA9
EDFA232A1MA-GD-F
IN
EDFA232A1MA-GD-F
70 63 24
1
C2621
1UF
10%
10V
2 X5R
402
1
C2622
1UF
10%
10V
2 X5R
402
1
C2623
10UF
20%
25V
2 X5R-CERM
0603
PP1V2_S3
1
C2610
1UF
A
10%
10V
2 X5R
402
1
PLACEMENT_NOTE:
C2611
1UF
10%
10V
2 X5R
402
10uF caps are shared between DRAM.
Distribute evenly.
SYNC_MASTER=J41_MLB
SYNC_DATE=02/06/2013
PAGE TITLE
LPDDR3 DRAM Channel B (32-63)
DRAWING NUMBER
62 57 23 22 21 20
PP1V8_S3
Apple Inc.
1
C2630
1UF
10%
10V
2 X5R
402
8
7
1
C2631
1UF
10%
10V
2 X5R
402
6
1
& lt; SCH_NUM & gt;
REVISION
R
C2632
10UF
NOTICE OF PROPRIETARY PROPERTY:
20%
25V
2 X5R-CERM
0603
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
5
4
3
2
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
26 OF 121
SHEET
23 OF 76
1
SIZE
D
A
8
7
6
5
4
3
2
1
D
Intel reccomends 55 Ohm for CMD/ADDR, 80 Ohm for CTRL/CKE, 38 Ohm for CLK
D
62 53 24
70 63 20
IN
70 63 20
IN
70 63 20 7
IN
70 63 20
IN
70 63 20
IN
70 20 7
IN
70 20 7
IN
70 20 7
IN
70 20 7
IN
70 63 20
IN
70 63 20
IN
70 63 20
IN
70 63 20
IN
70 63 20
IN
70 63 21
IN
70 63 21
IN
70 63 21 7
IN
70 63 21
IN
70 63 21
IN
70 21 7
IN
70 21 7
70 21 7
IN
70 21 7
C
IN
IN
70 63 21
70 63 21
70 63 21
IN
IN
IN
70 63 21
IN
70 63 21
IN
70 21 20 7
IN
70 21 20 7
IN
70 63 21 20 7
IN
MEM_A_CAA & lt; 9 & gt;
MEM_A_CAA & lt; 8 & gt;
MEM_A_CAA & lt; 6 & gt;
MEM_A_CAA & lt; 7 & gt;
MEM_A_CAA & lt; 5 & gt;
MEM_A_CLK_P & lt; 0 & gt;
MEM_A_CLK_N & lt; 0 & gt;
MEM_A_CKE & lt; 1 & gt;
MEM_A_CKE & lt; 0 & gt;
MEM_A_CAA & lt; 4 & gt;
MEM_A_CAA & lt; 3 & gt;
MEM_A_CAA & lt; 2 & gt;
MEM_A_CAA & lt; 1 & gt;
MEM_A_CAA & lt; 0 & gt;
MEM_A_CAB & lt; 9 & gt;
MEM_A_CAB & lt; 8 & gt;
MEM_A_CAB & lt; 6 & gt;
MEM_A_CAB & lt; 7 & gt;
MEM_A_CAB & lt; 5 & gt;
MEM_A_CLK_P & lt; 1 & gt;
MEM_A_CLK_N & lt; 1 & gt;
MEM_A_CKE & lt; 2 & gt;
MEM_A_CKE & lt; 3 & gt;
MEM_A_CAB & lt; 4 & gt;
MEM_A_CAB & lt; 2 & gt;
MEM_A_CAB & lt; 3 & gt;
MEM_A_CAB & lt; 1 & gt;
MEM_A_CAB & lt; 0 & gt;
MEM_A_CS_L & lt; 0 & gt;
MEM_A_CS_L & lt; 1 & gt;
MEM_A_ODT & lt; 0 & gt;
RP2701
RP2701
RP2701
RP2701
R2700
R2701
R2702
R2703
R2704
R2705
R2706
RP2703
RP2703
RP2703
R2725
RP2707
RP2707
RP2707
RP2707
R2707
R2708
R2709
R2720
R2721
RP2704
RP2704
RP2704
RP2704
R2722
R2723
R2724
56
56
56
56
56
39
39
82
82
56
56
56
56
56
56
56
56
56
56
39
39
82
82
56
56
56
56
56
82
82
82
4
PP0V6_S0_DDRVTT
5
3
6
2
7
1
8
1
2
1
2
1
2
1
2
1
2
1
2
1
4
2
5
3
6
2
7
1
2
4
5
3
6
2
7
1
8
1
2
1
2
1
2
1
2
1
2
4
5
3
6
2
7
1
8
1
2
1
2
1
2
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
1/32W
1/32W
1/32W
1/32W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/32W
1/32W
1/32W
1/20W
1/32W
1/32W
1/32W
1/32W
1/20W
1/20W
1/20W
1/20W
1/20W
1/32W
1/32W
1/32W
1/32W
1/20W
1/20W
1/20W
4X0201-HF
4X0201-HF
4X0201-HF
4X0201-HF
201 MF
201 MF
201 MF
201 MF
201 MF
201 MF
201 MF
62 53 24
1
C2700
70 63 22
20%
4V
2 CERM-X5R-1
201
IN
70 63 22
0.47UF
IN
70 63 22
IN
0.47UF
20%
4V
2 CERM-X5R-1
201
IN
70 22 7
C2701
IN
70 63 22
1
70 63 22 7
IN
C2702
70 22 7
0.47UF
1
IN
70 22 7
IN
70 22 7
IN
20%
4V
2 CERM-X5R-1
201
4X0201-HF
4X0201-HF
4X0201-HF
4X0201-HF
201 MF
201 MF
201 MF
201 MF
201 MF
4X0201-HF
4X0201-HF
4X0201-HF
4X0201-HF
201 MF
201 MF
201 MF
1
C2703
0.47UF
20%
4V
2 CERM-X5R-1
201
IN
70 63 22
IN
70 63 22
4X0201-HF
4X0201-HF
4X0201-HF
201 MF
70 63 22
IN
C2704
70 63 22
0.47UF
1
IN
70 63 22
IN
20%
4V
2 CERM-X5R-1
201
70 63 23
IN
70 63 23
IN
70 63 23
IN
70 63 23 7
1
C2705
0.47UF
20%
4V
2 CERM-X5R-1
201
1
70 63 23
0.47UF
20%
4V
2 CERM-X5R-1
201
IN
70 23 7
C2706
IN
IN
70 23 7
IN
70 23 7
IN
70 23 7
IN
70 63 23
1
C2707
0.47UF
20%
4V
2 CERM-X5R-1
201
1
C2708
IN
70 63 23
70 63 23
0.47UF
20%
4V
2 CERM-X5R-1
201
IN
IN
70 63 23
IN
70 63 23
IN
70 23 22 7
IN
70 23 22 7
1
0.47UF
IN
70 63 23 22 7
C2709
IN
MEM_B_CAA & lt; 9 & gt;
MEM_B_CAA & lt; 8 & gt;
MEM_B_CAA & lt; 7 & gt;
MEM_B_CAA & lt; 6 & gt;
MEM_B_CAA & lt; 5 & gt;
MEM_B_CLK_P & lt; 0 & gt;
MEM_B_CLK_N & lt; 0 & gt;
MEM_B_CKE & lt; 1 & gt;
MEM_B_CKE & lt; 0 & gt;
MEM_B_CAA & lt; 4 & gt;
MEM_B_CAA & lt; 2 & gt;
MEM_B_CAA & lt; 3 & gt;
MEM_B_CAA & lt; 1 & gt;
MEM_B_CAA & lt; 0 & gt;
MEM_B_CAB & lt; 9 & gt;
MEM_B_CAB & lt; 8 & gt;
MEM_B_CAB & lt; 7 & gt;
MEM_B_CAB & lt; 6 & gt;
MEM_B_CAB & lt; 5 & gt;
MEM_B_CLK_N & lt; 1 & gt;
MEM_B_CLK_P & lt; 1 & gt;
MEM_B_CKE & lt; 2 & gt;
MEM_B_CKE & lt; 3 & gt;
MEM_B_CAB & lt; 4 & gt;
MEM_B_CAB & lt; 2 & gt;
MEM_B_CAB & lt; 3 & gt;
MEM_B_CAB & lt; 1 & gt;
MEM_B_CAB & lt; 0 & gt;
MEM_B_CS_L & lt; 0 & gt;
MEM_B_CS_L & lt; 1 & gt;
MEM_B_ODT & lt; 0 & gt;
RP2712
RP2712
RP2712
RP2712
R2710
R2711
R2712
R2713
R2714
R2715
R2716
RP2713
RP2713
RP2713
R2735
RP2717
RP2717
RP2717
RP2717
R2717
R2718
R2719
R2730
R2731
RP2714
RP2714
RP2714
RP2714
R2732
R2733
R2734
20%
4V
2 CERM-X5R-1
201
Spare
1
56
8
5%
1/32W
4X0201-HF
4
5
3
6
2
7
1
8
1
2
1
2
1
2
1
2
1
2
1
2
1
4
2
5
3
6
2
7
1
2
4
5
3
6
2
7
1
8
1
2
1
2
1
2
1
2
1
2
4
5
3
6
2
7
1
8
1
2
1
2
1
2
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
1/32W
1/32W
1/32W
1/32W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/32W
1/32W
1/32W
1/20W
1/32W
1/32W
1/32W
1/32W
1/20W
1/20W
1/20W
1/20W
1/20W
1/32W
1/32W
1/32W
1/32W
1/20W
1/20W
1/20W
4X0201-HF
4X0201-HF
4X0201-HF
4X0201-HF
201 MF
201 MF
201 MF
201 MF
201 MF
201 MF
201 MF
1
4X0201-HF
4X0201-HF
4X0201-HF
201 MF
1
4X0201-HF
4X0201-HF
4X0201-HF
4X0201-HF
201 MF
201 MF
201 MF
201 MF
201 MF
4X0201-HF
4X0201-HF
4X0201-HF
4X0201-HF
201 MF
201 MF
201 MF
C2710
0.47UF
20%
2 4V
CERM-X5R-1
201
1
C2711
0.47UF
20%
2 4V
CERM-X5R-1
201
C2713
0.47UF
20%
2 4V
CERM-X5R-1
201
1
C2715
0.47UF
20%
2 4V
CERM-X5R-1
201
1
C2717
0.47UF
20%
2 4V
CERM-X5R-1
201
1
1
C2712
0.47UF
20%
4V
2 CERM-X5R-1
201
1
C2714
0.47UF
20%
4V
2 CERM-X5R-1
201
1
C2716
0.47UF
20%
4V
2 CERM-X5R-1
201
1
C
C2718
0.47UF
20%
4V
2 CERM-X5R-1
201
C2719
0.47UF
20%
2 4V
CERM-X5R-1
201
Spare
RP2703
NC
56
56
56
56
56
39
39
82
82
56
56
56
56
56
56
56
56
56
56
39
39
82
82
56
56
56
56
56
82
82
82
PP0V6_S0_DDRVTT
RP2713
NC
CRITICAL
PLACE_NEAR=RP2701.5:4mm 1
NC
C2720
1
56
8
5%
1/32W
4X0201-HF
22UF
20%
2 6.3V
X5R-CERM-1
603
NC
CRITICAL
PLACE_NEAR=RP2714.8:4mm 1
C2740
22UF
20%
2 6.3V
X5R-CERM-1
603
B
B
A
SYNC_MASTER=J41_MLB
SYNC_DATE=02/06/2013
PAGE TITLE
LPDDR3 DRAM Termination
DRAWING NUMBER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
27 OF 121
SHEET
24 OF 76
1
A
8
7
6
5
4
3
2
1
CRITICAL
1
2
10%
0.1UF
69 14
IN
C2801
PCIE_TBT_R2D_C_N & lt; 0 & gt;
1
IN
C2802
PCIE_TBT_R2D_C_P & lt; 1 & gt;
69 14
IN
C2803
PCIE_TBT_R2D_C_N & lt; 1 & gt;
1
1
69 14
IN
C2804
PCIE_TBT_R2D_C_P & lt; 2 & gt;
69 14
62 28 27 26 25
IN
C2805
PCIE_TBT_R2D_C_N & lt; 2 & gt;
PP3V3_S4_TBTAPWR
69 14
IN
PCIE_TBT_R2D_C_P & lt; 3 & gt;
C2806
IN
PCIE_TBT_R2D_C_N & lt; 3 & gt;
C2807
47K
69 14
5%
1/20W
MF
201 2
27
16V
X5R-CERM
1
2
10%
1
0201
16V
X5R-CERM
10%
0.1UF
69
69
69
2
PETP_0
PETN_0
U2800
CACTUSRIDGE4C
AA12
AB13
PCIE_TBT_R2D_P & lt; 1 & gt;
PCIE_TBT_R2D_N & lt; 1 & gt;
PERP_1
PERN_1
AB15
AA16
PCIE_TBT_R2D_P & lt; 2 & gt;
PCIE_TBT_R2D_N & lt; 2 & gt;
PERP_2
PERN_2
0201
16V
X5R-CERM
10%
0.1UF
R28101
0201
69
2
0.1UF
69
0201
16V
X5R-CERM
2
10%
1
PERP_0
PERN_0
AA18
AB19
PCIE_TBT_R2D_P & lt; 3 & gt;
PCIE_TBT_R2D_N & lt; 3 & gt;
TBT_PCIE_RESET_L
IN
R6
(TBT_SPI_CS_L)
(TBT_SPI_MISO)
71
71
MLP
71
7 HOLD*
VSS
4
THM
PAD
9
IN
18 15
IN
18 16 15
3 W*
TBTROM_HOLD_L
IN
18 15
R28251
5%
1/20W
MF
0201
OUT
1
R2829
0
67 25
0
5%
1/20W
MF
2 0201
2
67 25
67 25
67 25
67 25
67 25
67 25
67 25
67 25
67 5
IN
SNK0 AC Coupling
DP_TBTSNK0_ML_C_P & lt; 0 & gt; C2820
10% 16V
1
0.1UF
67 5
IN
DP_TBTSNK0_ML_C_N & lt; 0 & gt;
C2821
1
0.1UF
67 5
IN
DP_TBTSNK0_ML_C_P & lt; 1 & gt;
C2822
1
0.1UF
67 5
IN
DP_TBTSNK0_ML_C_N & lt; 1 & gt;
C2823
1
0.1UF
B
67 5
IN
DP_TBTSNK0_ML_C_P & lt; 2 & gt;
C2824
1
0.1UF
67 5
IN
DP_TBTSNK0_ML_C_N & lt; 2 & gt;
C2825
1
0.1UF
2
67 25
DP_TBTSNK0_ML_P & lt; 0 & gt;
13
25 67
OUT
IN
DP_TBTSNK0_ML_C_P & lt; 3 & gt;
C2826
1
0.1UF
67 5
IN
DP_TBTSNK0_ML_C_N & lt; 3 & gt;
C2827
1
0.1UF
X5R-CERM
2
DP_TBTSNK0_ML_N & lt; 0 & gt;
10% 16V
X5R-CERM
R28301
0201
2
DP_TBTSNK0_ML_P & lt; 1 & gt;
10% 16V
X5R-CERM
DP_TBTSNK0_ML_N & lt; 1 & gt;
10% 16V
X5R-CERM
67 25
100K
67 25
5%
1/20W
MF
201 2
0201
2
25 67
67 25
0201
25 67
67 25
67 25
25 67
67 25
2
DP_TBTSNK0_ML_P & lt; 2 & gt;
10% 16V
X5R-CERM
0201
2
DP_TBTSNK0_ML_N & lt; 2 & gt;
10% 16V
X5R-CERM
0201
67 25
25 67
67 25
25 67
67 25
2
DP_TBTSNK0_ML_P & lt; 3 & gt;
10% 16V
X5R-CERM
0201
2
DP_TBTSNK0_ML_N & lt; 3 & gt;
10% 16V
X5R-CERM
0201
25 67
18 13
BI
DP_TBTSNK0_AUXCH_C_P
C2828
1
0.1UF
67 13
BI
DP_TBTSNK0_AUXCH_C_N
C2829
1
0.1UF
67 18 5
25 67
R28311
DP_TBTSNK1_ML_C_P & lt; 0 & gt;
IN
DP_TBTSNK1_ML_C_N & lt; 0 & gt;
1
0.1UF
67 18 5
C2831
1
0.1UF
67 18 5
IN
DP_TBTSNK1_ML_C_P & lt; 1 & gt;
C2832
IN
DP_TBTSNK1_ML_C_N & lt; 1 & gt;
C2833
1
0.1UF
67 18 5
1
0.1UF
A
67 18 5
IN
DP_TBTSNK1_ML_C_P & lt; 2 & gt;
C2834
1
0.1UF
67 18 5
IN
DP_TBTSNK1_ML_C_N & lt; 2 & gt;
IN
DP_TBTSNK1_ML_C_P & lt; 3 & gt;
C2835
1
0.1UF
67 18 5
C2836
1
0.1UF
67 18 5
IN
0201
2
DP_TBTSNK0_AUXCH_N
10% 16V
X5R-CERM
DP_TBTSNK1_ML_C_N & lt; 3 & gt;
C2837
1
0.1UF
OUT
71 28
OUT
71 28
IN
IN
28
DP_TBTSNK0_AUXCH_P
10% 16V
X5R-CERM
5%
1/20W
MF
201 2
71 28
71 28
100K
2
IN
IN
0201
SNK1 AC Coupling
C2830
10% 16V
IN
2
25 67
25 67
BI
DP_TBTSNK1_AUXCH_C_P
C2838
1
0.1UF
67 18 13
BI
DP_TBTSNK1_AUXCH_C_N
C2839
1
0.1UF
8
71 28
25 67
0201
OUT
71 28
OUT
71 28
IN
71 28
IN
X5R-CERM
2
DP_TBTSNK1_ML_N & lt; 0 & gt;
10% 16V
X5R-CERM
0201
2
DP_TBTSNK1_ML_P & lt; 1 & gt;
25 67
25 67
OUT
IN
0201
DP_TBTSNK1_ML_N & lt; 1 & gt;
28
28
10% 16V
X5R-CERM
2
10% 16V
X5R-CERM
1
C2844
PCIE_TBT_D2R_C_P & lt; 2 & gt;
PCIE_TBT_D2R_C_N & lt; 2 & gt;
1
0.1UF
C2845
1
AD17
AD19
U20
TBT_RBIAS
1
TDI
TMS
TCK
TDO
TEST_EN
TEST_PWR_GOOD
DP_TBTSNK0_ML_P & lt; 3 & gt;
DP_TBTSNK0_ML_N & lt; 3 & gt;
E14
D13
69
69
PCIE_TBT_D2R_C_P & lt; 3 & gt;
PCIE_TBT_D2R_C_N & lt; 3 & gt;
PCIE_RST_0_N
PCIE_RST_1_N
PCIE_RST_2_N
PCIE_RST_3_N
N6
T1
Y5
U2
W6
DP_TBTSNK0_ML_P & lt; 2 & gt;
DP_TBTSNK0_ML_N & lt; 2 & gt;
E16
D15
DPSNK0_2_P
DPSNK0_2_N
DP_TBTSNK0_ML_P & lt; 1 & gt;
DP_TBTSNK0_ML_N & lt; 1 & gt;
E18
D17
DPSNK0_1_P
DPSNK0_1_N
DP_TBTSNK0_ML_P & lt; 0 & gt;
DP_TBTSNK0_ML_N & lt; 0 & gt;
E20
D19
DPSNK0_0_P
DPSNK0_0_N
DP_TBTSNK0_AUXCH_P
DP_TBTSNK0_AUXCH_N
A6
B5
U6
E6
D5
E8
D7
DP_TBTSNK1_ML_P & lt; 2 & gt;
DP_TBTSNK1_ML_N & lt; 2 & gt;
DP_TBTSNK1_ML_P & lt; 1 & gt;
DP_TBTSNK1_ML_N & lt; 1 & gt;
E10
D9
DP_TBTSNK1_ML_P & lt; 0 & gt;
DP_TBTSNK1_ML_N & lt; 0 & gt;
E12
D11
DP_TBTSNK1_AUXCH_P
DP_TBTSNK1_AUXCH_N
A4
B3
T5
PCIE_TBT_D2R_P & lt; 1 & gt;
X5R-CERM
16V
2
PCIE_TBT_D2R_N & lt; 1 & gt;
10%
16V
2
PCIE_TBT_D2R_P & lt; 2 & gt;
X5R-CERM
X5R-CERM
DPSNK0_HPD
DPSNK1_3_P
DPSNK1_3_N
DPSNK1_1_P
DPSNK1_1_N
DPSNK1_0_P
DPSNK1_0_N
0201
0201
10%
16V
2
PCIE_TBT_D2R_N & lt; 2 & gt;
10%
16V
2
PCIE_TBT_D2R_P & lt; 3 & gt;
X5R-CERM
0201
0201
14 69
OUT
14 69
OUT
14 69
OUT
14 69
OUT
14 69
OUT
14 69
OUT
14 69
OUT
14 69
D
0.1UF
C2847
1
10%
16V
2
PCIE_TBT_D2R_N & lt; 3 & gt;
X5R-CERM
10%
16V
X5R-CERM
XTAL_25_IN
XTAL_25_OUT
AA24
AB23
AA4
Y3
0201
NOTE: The following pins
0 - GPIO_13
8
9
1 - GPIO_1
10
2 - GPIO_2
3 - GPIO_3
11
12
4 - GPIO_5
5 - PCIE_RST_1_N
13
6 - PCIE_RST_2_N
14
7 - PCIE_RST_3_N
15
1%
1/20W
MF
2 201
Not used in host mode.
TP_TBT_PCIE_RESET0_L
TP_TBT_PCIE_RESET1_L
TP_TBT_PCIE_RESET2_L
TP_TBT_PCIE_RESET3_L
OUT
27
PP3V3_TBTLC
27
OUT
15 17 25 26 27 62 64
1
IN
R2898
IN
5%
1/20W
MF
2 201
12 69
12 69
C
R2895
SYSCLK_CLK25M_TBT_R
TP_TBT_XTAL25OUT
1
806
SYSCLK_CLK25M_TBT
2
1%
1/20W
MF
201
TBT_TMU_CLK_OUT
TBT_TMU_CLK_IN
DPSRC_3_P
DPSRC_3_N
A14
B15
TP_DP_TBTSRC_ML_CP & lt; 3 & gt;
TP_DP_TBTSRC_ML_CN & lt; 3 & gt;
DPSRC_2_P
DPSRC_2_N
A12
B13
TP_DP_TBTSRC_ML_CP & lt; 2 & gt;
TP_DP_TBTSRC_ML_CN & lt; 2 & gt;
DPSRC_1_P
DPSRC_1_N
A10
B11
NC_DP_TBTSRC_ML_CP & lt; 1 & gt;
NC_DP_TBTSRC_ML_CN & lt; 1 & gt;
DPSRC_0_P
DPSRC_0_N
A8
B9
TP_DP_TBTSRC_ML_CP & lt; 0 & gt;
TP_DP_TBTSRC_ML_CN & lt; 0 & gt;
DPSRC_AUX_P
DPSRC_AUX_N
C2
D3
NC_DP_TBTSRC_AUXCH_CP
NC_DP_TBTSRC_AUXCH_CN
DPSRC_HPD_OD
V3
1
1
DP_TBTSNK1_ML_P & lt; 2 & gt;
10% 16V
X5R-CERM
0201
2
DP_TBTSNK1_ML_N & lt; 2 & gt;
10% 16V
X5R-CERM
0201
2
DP_TBTSNK1_ML_P & lt; 3 & gt;
10% 16V
X5R-CERM
0201
2
DP_TBTSNK1_ML_N & lt; 3 & gt;
10% 16V
X5R-CERM
0201
71 28
R2897 R2899
1
R2896
R2880
DP_TBTSRC_HPD
64
100K
5%
1/20W
MF
2 201
64
64
10K
1K
5%
1/20W
MF
201 2
10K
5%
1/20W
MF
2 201
5%
1/20W
MF
2 201
64
TBT_DDC_XBAR_EN_L
25
TBT_GO2SX_BIDIR
R2881 for CYA,
allows separation
of GPIO_2/GPIO_9
if necessary.
Stuff one of R2881/2.
25 18 15
64
64
64
64
64
64
25
25
Y1
W2
J4
AA2
AB1
AC2
P3
M5
T3
V5
TBT_GO2SX_BIDIR
TBT_PWR_EN
SMC_PME_S4_DARK_L
TBT_CIO_PLUG_EVENT
SMBUS_PCH_DATA
SMBUS_PCH_CLK
(TBT_EN_CIO_PWR_L)
TBT_GPIO_9
TBT_GPIO_14
TBT_DDC_XBAR_EN_L
PB_CIO2_TX_P/DP_SRC_0_P
PB_CIO2_TX_N/DP_SRC_0_N
R24
N24
NC_TBT_B_R2D_CP & lt; 0 & gt;
NC_TBT_B_R2D_CN & lt; 0 & gt;
R22
N22
DPSNK1_AUX_P
DPSNK1_AUX_N
DPSNK1_HPD
G22
E22
PA_CIO0_RX_P
PA_CIO0_RX_N
DP_TBTSNK1_AUXCH_P
10% 16V
X5R-CERM
OUT
71 28
OUT
25 67
DP_TBTSNK1_AUXCH_N
10% 16V
X5R-CERM
R2881
0
5%
1/20W
MF
2 0201
TBT_GPIO_9
TBT_GPIO_14
1
BI
IN
15 18 25
15
OUT
33 37 38
OUT
15 18
BI
IN
R28831
R2832
100K
10K
5%
1/20W
MF
2 201
5%
1/20W
MF
201 2
TBT_A_D2R_P & lt; 1 & gt;
TBT_A_D2R_N & lt; 1 & gt;
L22
J22
PA_CIO1_RX_P
PA_CIO1_RX_N
PA_LSTX/CIO_1_LSEO
PA_LSRX/CIO_1_LSOE
R2882
10K
5%
1/20W
MF
2 201
B
14 16 19 40 56 69
TBT_EN_CIO_PWR_L
TBT_EN_CIO_PWR_L
25
MAKE_BASE=TRUE
OUT
13 25 27
OUT
13 25 27
62 28 27 26 25
PP3V3_S4_TBTAPWR
25
OUT
64
OUT
64
NC_TBT_B_D2RP & lt; 0 & gt;
NC_TBT_B_D2RN & lt; 0 & gt;
IN
64
IN
64
P1
H5
TBT_B_CONFIG1_BUF
TBT_B_CONFIG2_RC
IN
18
25
IN
18
28 27 25
PB_CIO3_TX_P/DP_SRC_2_P
PB_CIO3_TX_N/DP_SRC_2_N
PA_CIO1_TX_P/DP_SRC_2_P
PA_CIO1_TX_N/DP_SRC_2_N
1
14 16 19 40 56 69
OUT
W24
U24
NC_TBT_B_R2D_CP & lt; 1 & gt;
NC_TBT_B_R2D_CN & lt; 1 & gt;
OUT
64
OUT
64
W22
U22
NC_TBT_B_D2RP & lt; 1 & gt;
NC_TBT_B_D2RN & lt; 1 & gt;
IN
64
IN
64
L6
G6
NC_TBT_B_LSTX
TBT_B_LSRX
OUT
64
IN
18
PB_DPSRC_1_P
PB_DPSRC_1_N
A20
B21
DP_TBTPB_ML_C_P & lt; 1 & gt;
DP_TBTPB_ML_C_N & lt; 1 & gt;
OUT
PB_DPSRC_3_P
PB_DPSRC_3_N
A22
B23
DP_TBTPB_ML_C_P & lt; 3 & gt;
DP_TBTPB_ML_C_N & lt; 3 & gt;
OUT
D1
E2
NC_DP_TBTPB_AUXCH_CP
NC_DP_TBTPB_AUXCH_CN
PB_CIO2_RX_P
PB_CIO2_RX_N
PB_CONFIG1/CIO_2_LSEO
PB_CONFIG2/CIO_2_LSOE
L24
J24
DP_TBTPA_ML_C_P & lt; 1 & gt;
DP_TBTPA_ML_C_N & lt; 1 & gt;
A16
B17
DP_TBTPA_ML_C_P & lt; 3 & gt;
DP_TBTPA_ML_C_N & lt; 3 & gt;
A18
B19
F3
F1
OUT
71 28
OUT
71 28
BI
71 28
25 67
BI
DP_TBTPA_AUXCH_C_P
DP_TBTPA_AUXCH_C_N
IN
DP_TBTPA_HPD
H1
TBT_A_HV_EN
TBT_A_CIO_SEL
TBT_A_DP_PWRDN
G2
M3
H3
25 67
25 67
28
28
0201
OUT
OUT
28 25
0201
2
1
25
PA_CONFIG1/CIO_0_LSEO
PA_CONFIG2/CIO_0_LSOE
TBT_A_R2D_C_P & lt; 1 & gt;
TBT_A_R2D_C_N & lt; 1 & gt;
71 28
2
PP3V3_TBTLC
1
NO STUFF
TBT_A_D2R_P & lt; 0 & gt;
TBT_A_D2R_N & lt; 0 & gt;
N2
J6
17 69
IN
Divides 3.3V to 1.8V
64 62 27 26 25 17 15
GPIO_2/GO2SX
(FORCE_PWR) GPIO_3
GPIO_4/WAKE_N_OD
GPIO_5/CIO_PLUG_EVENT
GPIO_6/CIO_SDA_OD
GPIO_7/CIO_SCL_OD
GPIO_8/EN_CIO_PWR_OD*
GPIO_9/OK2GO2SX_OD*
GPIO_14
GPIO_15
PA_CIO0_TX_P/DP_SRC_0_P
PA_CIO0_TX_N/DP_SRC_0_N
TBT_A_LSTX
TBT_A_LSRX
require testpoints:
- GPIO_15
- GPIO_11
- GPIO_14
- GPIO_0
- GPIO_12
- GPIO_10
- PB_LSTX
- PB_LSRX
10K
PCIE_CLK100M_TBT_P
PCIE_CLK100M_TBT_N
69
0201
NO STUFF
DPSNK0_AUX_P
DPSNK0_AUX_N
DPSNK1_2_P
DPSNK1_2_N
0201
10%
R2855
NC
AB21
AD21
TMU_CLK_OUT
TMU_CLK_IN
G24
E24
K1
G4
2
TBT_EN_LC_PWR
REFCLK_100_IN_P
REFCLK_100_IN_N
TBT_A_R2D_C_P & lt; 0 & gt;
TBT_A_R2D_C_N & lt; 0 & gt;
TBT_A_CONFIG1_BUF
TBT_A_CONFIG2_RC
16V
OUT
1
TBT_CLKREQ_ISOL_L
K5
DPSNK0_3_P
DPSNK0_3_N
DP_TBTSNK1_ML_P & lt; 3 & gt;
DP_TBTSNK1_ML_N & lt; 3 & gt;
10%
X5R-CERM
0201
TBT_RSENSE
W20
C2846
X5R-CERM
R28851
10K
5%
1/20W
MF
201 2
28 25
PB_CIO3_RX_P
PB_CIO3_RX_N
PB_LSTX/CIO_3_LSEO
PB_LSRX/CIO_3_LSOE
1
R2886
10K
5%
1/20W
MF
2 201
TBT_A_DP_PWRDN
TBT_B_DP_PWRDN
TBT_A_HV_EN
TBT_B_HV_EN
R28881
10K
5%
1/20W
MF
201 2
1
R2887
10K
5%
1/20W
MF
2 201
25 67
0201
2
7
C2843
16V
PCIE_TBT_D2R_N & lt; 0 & gt;
25
DP_TBTSNK1_ML_P & lt; 0 & gt;
28 27 25
67 18 13
V1
AB3
AA6
R2
N4
AB5
DP_TBTSNK1_HPD
OUT
28
67 13
XDP_JTAG_ISP_TDI
JTAG_TBT_TMS
XDP_JTAG_ISP_TCK
JTAG_ISP_TDO
TBT_TEST_EN
TBT_TEST_PWR_GOOD
0201
67 25
67 5
EE_DI
EE_DO
EE_CS_N
EE_CLK
DP_TBTSNK0_HPD
18 16 15
TBTROM_WP_L
C
R4
P5
AD3
W4
TBT_SPI_MOSI
TBT_SPI_MISO
TBT_SPI_CS_L
TBT_SPI_CLK
1 S*
C
69
EN_LC_PWR
THERMDA
Use AA8 GND ball for THERM_DN
CLOCKS
6
Y7
TP_TBT_THERM_DP
SOURCE PORT 0
(TBT_SPI_CLK)
69
PCIE_CLKREQ_OD_N
DEBUG: For monitoring clock
MISC
2
U2890 Q
M95256-RMC6XG
D
AD13
AD15
MONOBS_P
MONOBS_N
PORT0
5
PETP_2
PETN_2
U4
PCIE RESET
DEBUG: For monitoring current/voltage
W18
TBT_MONOBSP
W16
TBT_MONOBSN
71
(TBT_SPI_MOSI)
1
0.1UF
0.1UF
NC
DISPLAYPORT
5%
1/20W
MF
2 201
C2842
PCIE_TBT_D2R_C_P & lt; 1 & gt;
PCIE_TBT_D2R_C_N & lt; 1 & gt;
PORT2
3.3K
69
69
PCIE_TBT_D2R_P & lt; 0 & gt;
10%
2
PORT3
CRITICAL
OMIT_TABLE
NONE
NONE
NONE
0201 2
1
2
1K
MONDC0
MONDC1
PORT1
8
VCC
5%
1/20W
MF
201 2
OMIT
R28151
NOSTUFF
AD23
AC24
OUT
25 67
25 67
PA_DPSRC_1_P
PA_DPSRC_1_N
PA_DPSRC_3_P
PA_DPSRC_3_N
PORTS
5%
1/20W
MF
2 201
3.3K
10%
6.3V 2
CERM
402
TP_TBT_MONDC0
TP_TBT_MONDC1
JTAG/TEST PORT
3.3K
1UF
R2893
AD9
AD11
RBIAS
PWR_ON_POC_RSTN
SINK PORT 0
5%
1/20W
MF
201 2
R2891
10%
16V
X5R-CERM 2
0201
1
PETP_1
PETN_1
PETP_3
PETN_3
SINK PORT 1
3.3K
1
R28921
C2841
0.1UF
PERST_N
J2
EEPROM
R28901
C2890
1
0.1UF
0.1UF
C2810 1
BYPASS=U2890.8:2mm
1
C2840
PCIE_TBT_D2R_C_P & lt; 0 & gt;
PCIE_TBT_D2R_C_N & lt; 0 & gt;
RSENSE
PERP_3
PERN_3
TBT_PWR_ON_POC_RST_L
27
0.1UF
69
0201
IN
15 17 25 26 27 62 64
69
0.1UF
NO STUFF
PP3V3_TBTLC
AD5
AD7
(SYM 1 OF 2)
16V
X5R-CERM
10%
1
0201
PCIE_TBT_R2D_P & lt; 0 & gt;
PCIE_TBT_R2D_N & lt; 0 & gt;
OMIT_TABLE
FCBGA
69
2
0.1UF
69
AB9
AA10
0201
16V
X5R-CERM
2
10%
0.1UF
D
16V
X5R-CERM
10%
0.1UF
0201
69
2
0.1UF
69 14
16V
X5R-CERM
TRANSMIT
C2800
PCIE_TBT_R2D_C_P & lt; 0 & gt;
PCIE GEN2
IN
RECEIVE
69 14
PA_AUX_P
PA_AUX_N
PA_DPSRC_HPD
GPIO_0/PA_HV_EN/BYP0
GPIO_10/PA_CIO_SEL/BYP1
GPIO_12/PA_DP_PWRDN/BYP2
PB_AUX_P
PB_AUX_N
PB_DPSRC_HPD
K3
GPIO_1/PB_HV_EN/BYP0
GPIO_11/PB_CIO_SEL/BYP1
GPIO_13/PB_DP_PWRDN/BYP2
TBT_B_HV_EN
TBT_B_CIO_SEL
TBT_B_DP_PWRDN
For unused port, pull CONFIG1, CONFIG2, LSRX, HPD and CIO_SEL low (10k).
6
5
4
SYNC_MASTER=J41_MLB
SYNC_DATE=02/06/2013
PAGE TITLE
Thunderbolt Host (1 of 2)
OUT
DRAWING NUMBER
BI
64 71
BI
64 71
Apple Inc.
IN
OUT
18
OUT
25
BRANCH
& lt; BRANCH & gt;
25
OUT
All other port signals can be NC.
3
& lt; E4LABEL & gt;
18
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
R
DP_TBTPB_HPD
M1
L2
L4
OUT
PAGE
28 OF 121
SHEET
25 OF 76
1
A
8
7
6
5
4
3
2
PP1V05_TBTCIO
27 62
???? mW (Single-Port)
2700 mW (Dual-Port)
EDP: 1100 mA
CRITICAL
1
20%
6.3V
CERM-X5R 2
0402-1
20%
2 6.3V
X5R
0201-1
C2901 1
1
10UF
10UF
20%
6.3V
CERM-X5R 2
0402-1
C2910
1.0UF
C2914
1.0UF
20%
2 6.3V
X5R
0201-1
1
C2911
1.0UF
20%
6.3V
2 X5R
0201-1
1
C2915
1.0UF
20%
6.3V
2 X5R
0201-1
1
C2912
1.0UF
20%
2 6.3V
X5R
0201-1
1
C2916
1.0UF
20%
2 6.3V
X5R
0201-1
1
C2913
1.0UF
20%
2 6.3V
X5R
0201-1
1
C2917
1.0UF
20%
2 6.3V
X5R
0201-1
VCC1P0_ON
VCC1P0_ON
VCC1P0_ON
VCC1P0_ON
VCC1P0_ON
VCC1P0_ON
VCC1P0_ON
VCC1P0_ON
VCC1P0_ON
VCC1P0_ON
G10
G12
G14
G16
G18
H19
K19
M19
P19
T19
V15
V19
W12
W14
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
C
G8
H9
B
AD1
K13
K9
L12
L16
L8
M13
M17
M9
N12
N16
N8
P13
P17
P9
R12
R16
R8
T13
T17
T9
U12
U16
U8
V9
A2
A24
AA14
AA20
AA22
AA8
AB11
AB17
AB7
AC10
AC12
AC14
AC16
AC18
AC20
AC22
AC4
AC6
AC8
B1
B7
C10
C12
C14
C16
C18
C20
A
OMIT_TABLE
CACTUSRIDGE4C
FCBGA
(SYM 2 OF 2)
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
K11
K15
L10
L14
M11
M15
N10
N14
P11
P15
R10
R14
T11
U10
V11
W10
M7
P7
T7
VCC3P3_CIO
VCC3P3_CIO
VCC3P3_CIO
L18
N18
R18
VCC3P3_DP
VCC3P3_DP
VCC3P3_DP
VCC3P3_DP
VCC1P0_DPAUX
VCC1P0_DPAUX
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC3P3
VCC3P3
VCC3P3
U2800
VCC
C2900 1
J10
J12
J14
J16
J8
K17
T15
U14
V7
W8
C2940 1
C2941 1
C2942 1
C2943 1
20%
6.3V 2
X5R
0201-1
20%
6.3V 2
X5R
0201-1
20%
6.3V 2
X5R
0201-1
20%
6.3V 2
X5R
0201-1
1.0UF
1.0UF
1.0UF
1.0UF
C2944 1 C2945 1
1.0UF
20%
6.3V 2
X5R
0201-1
1.0UF
20%
6.3V 2
X5R
0201-1
1
C2971 1
C2972 1
C2973 1
C2974 1
1.0UF
1.0UF
1.0UF
1.0UF
1.0UF
1
D
C2905
10UF
20%
2 6.3V
CERM-X5R
0402-1
PP3V3_TBTLC
15 17 25
??? mW (Single-Port)
250 mW (Dual-Port)
EDP: 50 mA
C2970 1
64
27 62 64
C2960
10UF
H11
H13
H15
H17
VCC3P3_DPAUX
20%
6.3V 2
X5R
0201-1
20%
6.3V 2
X5R
0201-1
20%
6.3V 2
X5R
0201-1
20%
6.3V 2
X5R
0201-1
20%
6.3V 2
X5R
0201-1
20%
2 6.3V
CERM-X5R
0402-1
C
H7
VCC3P3_POC
GND
D
PP1V05_TBTLC
??? mW (Single Port)
250 mW (Dual Port)
EDP: 1600 mA
64 62 27
1
K7
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
C22
C24
C4
C6
C8
D21
D23
E4
F11
F13
F15
F17
F19
F21
F23
F5
F7
F9
G20
H21
H23
J18
J20
K21
K23
L20
M21
M23
N20
P21
P23
R20
T21
T23
U18
V13
V17
V21
V23
Y11
Y13
Y15
Y17
Y19
Y21
Y23
Y9
PP3V3_S4_TBTAPWR 25
EDP: 10 mA
27 28 62
C2990 1
1.0UF
20%
6.3V 2
X5R
0201-1
B
SYNC_MASTER=J41_MLB
SYNC_DATE=02/06/2013
PAGE TITLE
Thunderbolt Host (2 of 2)
DRAWING NUMBER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
EDP numbers are from 12/22/2011 email from Haim Lustig (Intel) to Paul Baker (Apple)
Power consumption figures from CR DG v0.57, IBL doc #472455.
8
7
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
29 OF 121
SHEET
26 OF 76
1
A
6
5
Page Notes
Q3080
SI8409DB
PPBUS_G3H
8-13V Input
Changes required
for 2S.
R30801
1
470K
Signal aliases required by this page:
- =TBT_CLKREQ_L
- =TBT_RESET_L
C3080
D
2 3
S
BGA
64 62
CRITICAL
10%
25V
2 X5R
402
1
C3090
C3091 1
1
10UF
10UF
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
1%
1/20W
MF
201 2
VIN
TBTBST_EN_UVLO
150K
5%
1/20W
MF
201 2
25 EN/UVLO
28 INTVCC
TBTBST_INTVCC
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
TBTBST_PWREN_L
C3081
DMN32D2LFB4
2.2UF
DFN1006H4-3
1
1
C3087
47PF
20%
10V
X5R-CERM 2
402
1
R3093
S 2
1%
1/20W
MF
201 2
FBX
SGND shorted to
GND inside package,
no XW necessary.
SGND
GND
1
73.2K
1%
1/20W
MF
2 201
& lt; R2 & gt;
C3082
1
2.2UF
R30941
C3093
1
41.2K
3300PF
20%
10V
2 X5R-CERM
402
C3094
0.33UF
1%
1/20W
MF
201 2
10%
10V
2 X7R-CERM
0201
10%
6.3V
2 CERM-X5R
402
1
NC
1
C3088
PLACE_NEAR=C3095.1:2 mm
10UF
C3098
10UF
133K
1
10UF
20%
25V
X5R-CERM 2
0603
1%
1/16W
MF-LF
402 2
5%
2 50V
CERM
0402
C3097
20%
25V
2 X5R-CERM
0603
C3096 1
R30951
22PF
1
20%
25V
2 X5R-CERM
0603
20%
25V
X5R-CERM 2
0603
& lt; Ra & gt;
TBTBST_FBX
31
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
NO STUFF
1
C3089
R30961
5%
50V
2 CERM
402
1
1
1
10UF
20%
25V
X5R-CERM 2
0603
C309B
C3099
0.001UF
20%
2 25V
X5R-CERM
0603
C3085 1
Vout = 1.6V * (1 + Ra / Rb)
C309A
10UF
20%
2 25V
X5R-CERM
0603
1%
1/16W
MF-LF
402 2
& lt; Rb & gt;
GND_TBTBST_SGND
C3084
10UF
15.8K
100PF
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=0V
UVLO(falling) = 1.22 * (R1 + R2) / R2
UVLO(rising) = UVLO(falling) + (2uA * R1)
UVLO = 4.55V (falling), 4.95 (rising)
C3095
10UF
TBTBST_VSNS_RC
12
13
14
15
16
17
R3092
10%
50V
2 X7R-CERM
0402
1
10UF
20%
25V
X5R-CERM 2
0603
C
Supervisor & CLKREQ# Isolation
PP3V3_S0
6
PP3V3_TBTLC
D
15 17 25 26 27 62 64
Q3088
DMN5L06VK-7
1
R3088
SOT-563
CRITICAL
10K
S
U3000
TDFN
C3000
1
10%
16V
X5R-CERM 2
0201
TBTBST_SHDN_DIV
PP1V05_TBTLC
26 27 62 64
R3087
D
3
330K
TBT_PCIE_RESET_L
DLY = 60 ms +/- 20%
OUT
Q3088
DMN5L06VK-7
5%
1/20W
MF
2 201
SOT-563
25
S
4
TBT_CLKREQ_ISOL_L
TBT_CLKREQ_ISOL_L
IN 7
G 5
MAKE_BASE=TRUE
THRM
PAD
IN
17 37 38
25 27
9
5
GND
IN
25 27
TBT " POC " Power-up Reset
TBT_EN_LC_ISOL
R3011
PP3V3_S4_TBTAPWR
62 28 26 25
B
TBT_EN_LC_RC3V3
U3010
C3031
GND
20%
6.3V 2
X5R
0201-1
Part
TPS22924C
Type
Load Switch
R(on)
@ 2.5V
1.0UF
1
C1
C2 ON
U3030RESET*
TPS3808
TBTPOCRST_CT
U3010
CRITICAL
C3010 1
2 SENSE
18.5 mOhm Typ
25.8 mOhm Max
C3030
10%
25V
2 CERM
0402
0.0047UF
QFN
3 CT
GND
PP3V3_S0
TBT_PWR_ON_POC_RST_L
6
OUT
1
(IPU) 4
MR*
Q3025
TBTPOCRST_MR_L
DMN5L06VK-7
THRM
PAD
SOT-563
1
0.1UF
TPS3808G25
Vt = 2.33V +/- 2%
Delay = 27.3ms
C3025
330PF
10%
16V
X5R-CERM 2
0201
C3011 1
62 64 65 74
8 11 12 13 15 17 18 27 30 36 38
39 40 41 42 43 44 45 56 59 61
25
R3030
S
VOUT
27 62 64
100K
5%
1/20W
MF
2 201
TBT_POC_RESET_L
IN
15
4
VIN
A1
B1
PP3V3_TBTLC
15 17 25 26
Max Current = 2A (85C)
D
A2
B2
CSP
Pull-up: R2810
VDD
TPS22924
PP3V3_S0
CRITICAL
G 5
1
3.3V TBT " LC " Switch
1%
1/20W
MF
201
65 64 62 61 59 56 45 44
27 18 17 15 13 12 11 8
43 42 41 40 39 38 36 30
74
5%
1/20W
MF
2 201
SMC_DELAYED_PWRGD
6 EN
8 OUT
Pull-up provided by SB page.
36.5K1
G
Max Vgs: 10V
2
1
RESET* 4
(OD)
2
S
DLY
3 MR*
TBT_CLKREQ_L
1
+ SENSE 2
- 0.7V
0.1UF
PCH_TBT_PCIE_RESET_L
IN
Platform (PCIe) Reset
OUT
5%
1/20W
MF
2 201
7
12
TBT_EN_LC_PWR
R3007
100K
SLG4AP016V
330K
1
5
18 15
IN
3
25
D
SYM_VER_3
VDD
5%
1/20W
MF
2 201
2
Q3040
DMN32D2LFB4
DFN1006H4-3
G 1
R3040
1
1
3
74 65 64 62 61 59 56
30 27 18 17 15 13 12 11 8
45 44 43 42 41 40 39 38 36
B
1%
1/16W
MF-LF
402 1
32 SS
TBTBST_SS
1
49.9K
34 SYNC
1
C
NC
TBTBST_VC_RC
TBT_A_HV_EN
2
R3090
1
2
10
35
36
33 RT
TBTBST_RT
10K
5%
25V
2 NP0-C0G-CERM
0201
3
QFN
4
23
24
37
IN
G
1
2.2UF
20%
10V
X5R-CERM 2
402
SYM_VER_2
28 25
C3092
1
TBTBST_VSNS
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
30 VC
TBTBST_VC
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
D 3
D
XW3095
SM
2
6
SNS2
LT3957
2
TBTBST_SNS2
SNS1
U3090
28 62 64
Vout = 15.1V
Max Current = 1.0A
Freq = 300KHz
5%
1/20W
MF
0201
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
SW
CRITICAL
0
1
PP15V_TBT
K
DFLS230L
R3089
TBTBST_SNS1
20%
25V
X5R-CERM 2
0603
200K
& lt; R1 & gt;
A
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
SWITCH_NODE=TRUE
DIDT=TRUE
R30911
R30811
Q3005
D3095
POWERDI-123
TBTBST_BOOST
2
PIMB062D-SM
20%
25V
X5R-CERM 2
0603
TBTBST_PWREN_DIV_L
BOM options provided by this page:
(NONE)
CRITICAL
L3095
0.1UF
5%
1/20W
MF
201 2
1
6.8UH-4.0A
PPVIN_S4SW_TBTBST_FET
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
Voltage not specified here,
add property on another page.
2
TBT 15V Boost Regulator
G
62 56 50 49 42 41
3
-30V
+/-12V
-1.4V
46mOhm @ 4.5V Vgs
3.7A @ 70C
1
D
CRITICAL
4
Power aliases required by this page:
- =PPVIN_SW_TBTBST
(8-13V Boost Input)
- =PP15V_TBT_REG
(15V Boost Output)
- =PP3V3_TBT_P3V3TBTFET
(3.3V FET Input)
64
- =PP3V3_TBT_FET
(3.3V FET Output)
- =PP3V3_S0_TBTPWRCTL
- =PP1V05_TBT_P1V05TBTFET
(1.05V FET Input)
- =PP1V05_TBT_FET
(1.05V FET Output)
4
SI8409DB:
Vds(max):
Vgs(max):
Vgs(th):
Rds(on):
Id(max):
8
9
20
21
38
7
27
8
1
10%
16V
X7R-CERM 2
0201
1.0UF
20%
6.3V
X5R 2
0201-1
R3016
2
TBT_EN_LC_RC1V05
1.05V TBT " LC " Switch
51 42 38 27 17 16 15 11 8 6
64 62 59 58 55
51 42 38 27 17 16 15 11 8 6
64 62 59 58 55
U3015
64 62 27 26 25 17 15
TPS22920
PP1V05_S0
A2
B2
C2
A
CSP
VIN
VOUT
CRITICAL
C3015 1
1.0UF
20%
6.3V 2
X5R
0201-1
D2 ON
GND
A1
B1
C1
PP1V05_TBTLC
26 27 62 64
Max Current = 4A (85C)
1.05V TBT " CIO " Switch
PP1V05_S0
PP3V3_TBTLC
U3020
5%
1/20W
MF
201 2
TPS22920
Type
6.1 mOhm Typ
10.4 mOhm Max
TBT_EN_CIO_PWR
D 6
DMN5L06VK-7
VOUT
D2 ON
C3020
1.0UF
1
20%
6.3V 2
X5R
0201-1
SOT-563
C3016 1
A1
B1
C1
PP1V05_TBTCIO
26 62 64
Max Current = 4A (85C)
U3020
Part
TPS22920
Type
SYNC_DATE=02/06/2013
PAGE TITLE
Load Switch
R(on)
@ 1.05V
SYNC_MASTER=J41_MLB
6.1 mOhm Typ
10.4 mOhm Max
TBT Power Support
DRAWING NUMBER
Apple Inc.
2
20%
6.3V
X5R 2
0201-1
25 13
6
IN
G
S 1
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
TBT_EN_CIO_PWR_L
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
1.0UF
7
VIN
GND
Q3025
NO STUFF
8
CSP
CRITICAL
Load Switch
R(on)
@ 1.05V
A2
B2
C2
100K
U3015
Part
TPS22920
R30201
D1
0
5%
1/20W
MF
0201
D1
1
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
30 OF 121
SHEET
27 OF 76
1
A
8
7
6
5
4
3
2
1
3.3V/HV Power MUX
V3P3 must be S4 to support wake
from Thunderbolt device attach.
62 28 27 26 25
C3280 1
20%
6.3V
POLY-TANT 2
CASE-B2-SM
20%
6.3V
X5R-CERM-1 2
603
100UF
D
64 62 27
1
22UF
C3281
0.1UF
C3215
PP3V3_S4_TBTAPWR
19
20
OUT
4.7UF
C3210
0.1UF
10%
25V
X5R-CERM 2
0603
C3285 1
CRITICAL
QFN
C3286
10UF
10%
16V
X5R-CERM 2
0201
CD3211A0RGPR
16 ENHVU
1
0.1UF
U3210
10%
2 25V
X5R
402
20%
2 6.3V
CERM-X5R
0402-1
71 25
OUT
OUT
C3277
TBT_A_D2R_N & lt; 1 & gt;
TBT_A_D2R_P & lt; 1 & gt;
1
0.47UF
C3276
1
0.47UF
0.1UF
10%
2 25V
X5R
402
71 25
71 25
BI
BI
C3230
DP_TBTPA_AUXCH_C_N
DP_TBTPA_AUXCH_C_P
1
0.1UF
C3231
1
0.1UF
FAULTZ 4
IN
S4_PWR_EN
IN
TBT_A_HV_EN
11 HV_EN
ISET_S0 10
59 57
IN
PM_SLP_S3_BUF_L
17 S0
ISET_S3 9
TBTAPWRSW_ISET_S3
TBTHV:P15V
THRM
PAD
1
R3210
12V: See
22.6K
below
1%
21
1
2
3
13
15
GND
1
R3211
R3212
22.6K
1/20W
MF
201 2
R32131
22.6K
1%
1/20W
MF
201 2
IN
1%
1/20W
MF
2 201
1
0.22UF
C3233
1
0.22UF
36.5K
TBTAPWRSW_ISET_S3_R
TBTAPWRSW_ISET_S0_R
TBTHV:P15V
Single-fault protection
1
R3214
requires two R’s per HV
22.6K
1%
ISET_Sx with CD3210.
1/20W
MF
Single R on ISET_V3P3 OK.
TBTHV:P15V
IN
71 25
TBTHV:P15V
1
C3232
1%
1/20W
MF
2 201
2
20%
X5R
2
20%
X5R
1
2
IN
DP_TBTSNK0_DDC_DATA
DP_TBTSNK0_DDC_CLK
4
5
OUT
TBT_A_CONFIG1_BUF
71
25
DP_TBTPA_ML_C_P & lt; 1 & gt;
DP_TBTPA_ML_C_N & lt; 1 & gt;
DP_TBTPA_AUXCH_N
DP_TBTPA_AUXCH_P
71
18 13
71 25
7 TB8 TB+
71
18 13
6.3V
0201
71
71
HVQFN24-COMBO
TB_ENA
AUXIO_EN
DP_PD
AUXAUX+
(IPU) AUXIO(IPD) AUXIO+
DDC_DAT
DDC_CLK
TBT_A_D2R_C_N & lt; 1 & gt;
TBT_A_D2R_C_P & lt; 1 & gt;
71
TBTAPWRSW_ISET_V3P3
ISET_V3P3 8
D
U3220
CBTL05024
2
20% 4V 201
CERM-X5R-1
2
20% 4V 201
CERM-X5R-1
2
10% 16V
X5R-CERM
0201
2
10% 16V
X5R-CERM
0201
TBTAPWRSW_ISET_S0
5 EN
SIGNAL_MODEL=TBT_MUX
VDD
CRITICAL
(Both C’s)
71 25
C3211
27 25
10%
16V
X5R-CERM 2
0201
GND_VOID=TRUE
MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=15V
1
59 58 18
C
0.1UF
PP3V3RHV_S4_TBTAPWR
12
14
VHV
C3220 1
25 26 27 28 62
MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=3.3V
V3P3OUT 18
V3P3
6
7
1
PP3V3_S4_TBTAPWR
Max
1200mA
930mA (assumes 15V, 12W minimum)
930mA (assumes 3S, 9-12.6V, 7.5-11.7W)
10%
16V
2 X5R-CERM
0201
PP15V_TBT
18.9V Max
1
Min
1030mA
830mA
830mA
BI
16 CA_DETOUT
11 DP+
10 DP-
DP_TBTPA_ML_P & lt; 1 & gt;
DP_TBTPA_ML_N & lt; 1 & gt;
6.3V
0201
OUT
TBT_A_LSTX
TBT_A_LSRX
14 LSTX (IPU)
13 LSRX (IPD)
OUT
DP_TBTPA_HPD
IN
25
25
& lt; RV3P3 & gt;
TBT_A_CIO_SEL
DP_AUXCH_ISOL_L
TBT_A_DP_PWRDN
23
22
TBT_A_D2R1_AUXDDC_N
TBT_A_D2R1_AUXDDC_P
TBT: RX_1
IN
25
IN
13
IN
25
28 71
28 71
CA_DET 18
TBT_A_CONFIG1_RC
DPMLO+ 19
DPMLO- 20
DP_A_LSX_ML_P & lt; 1 & gt;
28 71
DP_A_LSX_ML_N & lt; 1 & gt;
28 71
TBT: LSX_A_R2P/P2R (P/N)
12 HPDOUT
25
15
24
6
HPD 17
TBT_A_HPD
28
28
GND THMPAD
25
CRITICAL
C3287 1
Nominal
1100mA
890mA
890mA
IV3P3
IHVS0
IHVS3
3
PP3V3_S5
9
21
34 29 18 17 16 15 13 11 8
74 64 62 60 59 58 57 42
2 201
& lt; RHVS3 & gt;
& lt; RHVS0 & gt; ILIM = 40000 / RISET
C
For 12V systems:
PART NUMBER
QTY
DESCRIPTION
REFERENCE DES
118S0145
118S0145
2
RES,MTL FILM,1/20W,17.8K,1,0201,SMD,LF
R3210,R3213
TBTHV:P12V
2
RES,MTL FILM,1/20W,17.8K,1,0201,SMD,LF
R3211,R3214
TBTHV:P12V
Nominal
IHVS0/S3 1120mA
Min
1090mA
CRITICAL
BOM OPTION
Thunderbolt Connector A
CRITICAL
L3200
Max
1170mA (12W minimum)
FERR-120-OHM-3A
1
2
PP3V3RHV_S4_TBTAPWR_F
0603
C3200 1
0.01UF
10%
50V
X7R-CERM 2
0402
MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=15V
TBTACONN_20_RC
1
C3201
MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=18V
0.01UF
10%
50V
2 X7R-CERM
0402
GND_VOID=TRUE
(Both C’s)
71 25
OUT
71 25
OUT
TBT_A_D2R_P & lt; 0 & gt;
TBT_A_D2R_N & lt; 0 & gt;
C3274
1
0.47UF
C3275
1
0.47UF
2
20% 4V 201
CERM-X5R-1
2
20% 4V 201
CERM-X5R-1
71
71
GND_VOID=TRUE
1
R3294
5%
1/20W
MF
201 2
NO_XNET_CONNECTION=TRUE
71 25
71 25
IN
IN
DP_TBTPA_ML_C_P & lt; 3 & gt;
DP_TBTPA_ML_C_N & lt; 3 & gt;
C3278
1
0.22UF
C3279
1
0.22UF
2
20%
X5R
2
20%
X5R
6.3V
0201
71
71
1
12
MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=18.9V
2
10%
25V
X5R-CERM 2
0201
TBT Dir
DP Dir
DP Dir
71
MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=18.9V
CRITICAL
514-0818
5%
1/20W
MF
2 201
NO_XNET_CONNECTION=TRUE
DP_TBTPA_ML_P & lt; 3 & gt;
DP_TBTPA_ML_N & lt; 3 & gt;
TBT: Unused
R32791
1
R3278
470K
470K
5%
1/20W
MF
2 201
HOT_PLUG_DETECT
GND
CONFIG1
ML_LANE0P
CONFIG2
ML_LANE0N
GND
GND
ML_LANE3P
ML_LANE1P
ML_LANE3N
ML_LANE1N
GND
GND
AUX_CHP
ML_LANE2P
AUX_CHN
ML_LANE2N
DP_PWR
RETURN
R32521
1M
5%
1/20W
MF
201 2
A
C3202
0.01UF
1
R3251 C3294 1
1M
5%
1/20W
MF
2 201
330PF
10%
16V
X7R-CERM 2
0201
1
C3295
330PF
10%
16V
2 X7R-CERM
0201
1
R3241
TBT_A_R2D_C_P & lt; 0 & gt;
TBT_A_R2D_C_N & lt; 0 & gt;
IN
25 71
IN
25 71
6.3V
0201
R3271
470K
470K
5%
1/20W
MF
2 201
5%
1/20W
MF
2 201
B
28 71
28 71
GND_VOID=TRUE
1
TBT_A_CONFIG2_RC
6.3V
0201
GND_VOID=TRUE
1
R3270
(Both C’s)
C3272
TBT: TX_1
TBT_A_D2R1_AUXDDC_P
TBT_A_D2R1_AUXDDC_N
TBT_A_CONFIG1_RC
OUT
GND_VOID=TRUE
1
SHIELD PINS
10%
16V
2 X5R-CERM
0201
100K
C3273
1
0.22UF
GND_VOID=TRUE
1
470K
DP Source must pull
down HPD input with
greater than or equal
to 100K (DPv1.1a).
2
20%
X5R
2
20%
X5R
6.3V
0201
TBT_A_R2D_C_P & lt; 1 & gt;
TBT_A_R2D_C_N & lt; 1 & gt;
IN
25 71
IN
25 71
6.3V
0201
GND_VOID=TRUE
1
R3273
470K
5%
1/20W
MF
2 201
5%
1/20W
MF
2 201
470k R’s for ESD protection
on AC-coupled signals.
Sink HPD range:
High: 2.0 - 5.0V
Low: 0 - 0.8V
5%
1/20W
MF
2 201
1
0.22UF
TBT_A_R2D_P & lt; 1 & gt;
TBT_A_R2D_N & lt; 1 & gt;
R3272
TBT_A_HPD
28
25
1
TBT: LSX_R2P/P2R (P/N)
TBT: RX_1
28
C3271
2
20%
X5R
2
20%
X5R
DP_A_LSX_ML_P & lt; 1 & gt;
DP_A_LSX_ML_N & lt; 1 & gt;
71
71 28
C3206 1
10%
25V
X5R-CERM 2
0201
71
71 28
GND_VOID=TRUE
0.01UF
1
3
5
7
9
11
8
15
17
19
1
0.22UF
0.22UF
(0-18.9V)
28
27
26
25
24
23
22
21
5%
1/20W
MF
201 2
2
4
6
13
10
12
14
16
18
20
TBT_A_R2D_P & lt; 0 & gt;
TBT_A_R2D_N & lt; 0 & gt;
TBT: TX_0
TBTACONN_7_C
TBT: RX_0
1K
C3270
TBT Dir
71
F-RT-TH
6.3V
0201
GND_VOID=TRUE
(Both C’s)
J3200
R3295
C3205 1
0.01UF
5%
1/20W
MF
201
MDP-J11
GND_VOID=TRUE
1
GND_VOID=TRUE
(0-18.9V)
TBT_A_D2R_C_P & lt; 0 & gt;
TBT_A_D2R_C_N & lt; 0 & gt;
1K
B
TBTACONN_1_C
R3201
SYNC_MASTER=J41_MLB
SYNC_DATE=02/07/2013
PAGE TITLE
Thunderbolt Connector A
DRAWING NUMBER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
32 OF 121
SHEET
28 OF 76
1
A
8
7
6
5
4
3
2
1
3.3V WLAN Switch
Part
Load Switch
R(on)
@ 2.5V
D
TPS22924C
Type
18.5 mOhm Typ
25.8 mOhm Max
Sense resistor on
sensor page
PP3V3_WLAN
1
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
C3521
37 38 39 41 64
J3501
CSP
VIN
VOUT
PP3V3_S5
8 11 13 15 16 17 18 28 29 34 42
57 58 59 60 62 64 74
A2
B2
CRITICAL
SMC_WIFI_PWR_EN 29
IN
ON C2
C1
1
37 39
1.0UF
20%
6.3V
0201-1
WIFI_EVENT_L
69 64
PCIE_AP_R2D_N
C3531
69 64
PCIE_AP_R2D_P
C3530
1
1
14 69
IN
14 69
IN
12 64 69
IN
12 64 69
OUT
14 64 69
OUT
14 64 69
16V
0201
2
10%
X5R-CERM
0.1UF
37 38 64
IN
PCIE_AP_R2D_C_P
10%
X5R-CERM
0.1UF
OUT
PCIE_AP_R2D_C_N
2
16V
0201
C3550
2 X5R
AIRPORT
F-RT-SM1
C
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
GND
SSD-K99
1
2
3
4
5
6
7
8
9
10
11
12
A1
B1
Max Current = 2A (85C)
10%
2 6.3V
CERM-X5R
0201
BYPASS=J3501:5mm
514S0335
CRITICAL
U3550
TPS22924
PP3V3_WLAN_R
41
0.1UF
D
PCIE_CLK100M_AP_N
PCIE_CLK100M_AP_P
PCIE_AP_D2R_P
PCIE_AP_D2R_N
C
Supervisor & CLKREQ# Isolation
13
14
15
16
17
18
Delay = 130 ms +/- 20%
PP3V3_S5
29 33 36 38 39 58 62 64
APCLKRQ:ISOL
R35531
1
19
20
21
1
R3554
100K
C3532
0.1UF
10%
6.3V
2 CERM-X5R
0201
BYPASS=J3501:1.5mm
10%
0201
SLG4AP041V
P3V3WLAN_VMON
TDFN
CRITICAL
2 SENSE
+
VREF -
AP_RESET_CONN_R_L
4 RESET*
R3558
64
AP_RESET_CONN_L
1
0
C3540
2 6.3V
CERM-X5R
U3540
1%
1/20W
MF
2 201
8 11 13 15 16 17 18 28 29 34 42
57 58 59 60 62 64 74
0.1UF
VDD
232K
5%
1/20W
MF
201 2
1
1
PP3V3_S4
DLY
2
R3556
60
29
13
17
57
74
59
28
11
16
42
64
58
18
8
15
34
62
0
1%
1/20W
MF
2 201
PCIe Wake Muxing
APCLKRQ:BIDIR
R3561
100K
5%
1/20W
MF
2 201
SEL
C3560
1
OUTPUT
L
H
5
0.1UF
0
B
2
1
AP_CLKREQ_L
BI
12
5%
1/20W
MF
0201
PCIE_WAKE_L (B0)
AP_S0IX_WAKE_L (B1)
VCC
10%
6.3V
CERM-X5R 2
0201
CRITICAL
U3560
S 6
AP_S0IX_WAKE_SEL
NOSTUFF
IN
15
R3559
NC7SB3157P6XG
SC70
VER-3
AP_PCIE_WAKE_L
5%
1/20W
MF
2 0201
R3557
PP3V3_S5
1
29 37 39
1
100K
B
15
APCLKRQ:ISOL
GND
5
R3555
IN
IN
(OD)
THRM
PAD
1
SMC_WIFI_PWR_EN
AP_CLKREQ_R_L
EN 6
OUT 8
7 IN
9
AP_CLKREQ_Q_L
64
AP_RESET_L
MR* 3
5%
1/20W
MF
0201
4 A
B0 3
B1 1
0
2
PCIE_WAKE_L
AP_S0IX_WAKE_L
OUT
13 31 64
OUT
15
1
5%
1/20W
MF
0201
GND
2
NOSTUFF
BLUETOOTH
R3560
1
0
2
58 39 38 36 33 29
64 62
PP3V3_S4
5%
1/20W
MF
0201
5
USB3740
68 64
68 64
USB_BT_CONN_P
10
USB_BT_CONN_N
9
DP
BI
14 68
USB_BT_N
BI
1
5
S 2
SYNC_MASTER=J41_MLB
SYNC_DATE=02/06/2013
PAGE TITLE
Wireless Connector
DRAWING NUMBER
1
PM_SLP_S4_L
GND
SEL
8
6
G
BT_WAKE
3
S 4
DFN1006H4-3
SYM_VER_2
NC
L
H
7
D 3
14 68
OE*
8
Q3510
USB_BT_P
DM_1 1
SIGNAL_MODEL=BT_MUX
36 37 39
DMN32D2LFB4
DP_2 6
DP_1 2
DM
OUT
NO_XNET_CONNECTION=TRUE
DM_2 7
CRITICAL
A
SMC_PME_S4_WAKE_L
0.1UF
10%
2 6.3V
CERM-X5R
0201
U3510
DFN
C3510
1
VDD
4
R3512
IN
13 18 36 37 59
OUTPUT
Apple Inc.
15K
1%
1/20W
MF
2 201
BT_WAKE (1)
USB_BT (2)
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
35 OF 121
SHEET
29 OF 76
1
A
8
7
6
5
4
3
2
1
OOB Isolation
D
64 62 41 30
D
PP3V3_S0SW_SSD
BYPASS=U3710:5 mm
1
C3718
0.1UF
10%
10V
0201
2 X5R-CERM
PLACE_NEAR=J3700.1:3mm
CRITICAL
CRITICAL
L3700
74LVC1G08 6
SOT891
FERR-26-OHM-6A
64 62 41 30
1
PP3V3_S0SW_SSD
2
64
PP3V3_S0SW_SSD_FLT
1
C3701
1
0.1UF
4
MIN_LINE_WIDTH=0.6mm
MIN_NECK_WIDTH=0.15mm
VOLTAGE=3.3V
0603
C3702
74 65 64 62 61
36 30 27 18 17 15 13 12 11 8
59 56 45 44 43 42 41 40 39 38
10%
10V
2 X5R-CERM
0201
PLACE_NEAR=L3700.1:1mm
10%
10V
2 X5R-CERM
0201
PLACE_NEAR=L3700.1:1mm
C
64
IN
PCIE_SSD_R2D_C_N & lt; 3 & gt;
C3710
67 12
IN
PCIE_SSD_R2D_C_P & lt; 3 & gt;
C3711
67 12
IN
PCIE_SSD_R2D_C_N & lt; 2 & gt;
C3712
67 12
IN
PCIE_SSD_R2D_C_P & lt; 2 & gt;
C3713
IN
PCIE_SSD_R2D_C_N & lt; 1 & gt;
C3714
67 12
1
2 GND_VOID=TRUE
10% 16V X5R-CERM
0.1UF
2 GND_VOID=TRUE
10% 16V X5R-CERM
0.1UF
1
GND_VOID=TRUE
10% 16V X5R-CERM
PCIE_SSD_R2D_C_P & lt; 1 & gt;
C3715
GND_VOID=TRUE
10% 16V X5R-CERM
PCIE_SSD_R2D_C_N & lt; 0 & gt;
IN
C3716
PCIE_SSD_R2D_C_P & lt; 0 & gt;
IN
C3717
0201
2 GND_VOID=TRUE
10% 16V X5R-CERM
67 64
PCIE_SSD_R2D_N & lt; 1 & gt;
PCIE_SSD_R2D_P & lt; 1 & gt;
0201
67 64
2
GND_VOID=TRUE
10% 16V X5R-CERM
1
PCIE_SSD_R2D_N & lt; 0 & gt;
PCIE_SSD_R2D_P & lt; 0 & gt;
64
1
SSD_CLKREQ_CONN_L
67 64
0201
2
GND_VOID=TRUE
10% 16V X5R-CERM
0.1UF
0201
Per Intel PDG, use PCIe style decoupling, when muxing PCIe & SATA
B
Delay = ~55ms
5%
1/20W
MF
201
CRITICAL
1
R3741
100K
PP3V42_G3H
2
2
1
SLG4AP016V
BYPASS=U3711:5 mm
C3719 1
0.1UF
10%
10V
X5R-CERM 2
0201
CRITICAL
6 74LVC1G08
SOT891
2
U3711
1
4
SMC_OOB1_D2R_L
C
08
NC
5
3
NC
39
38 TRUE
37 TRUE
36
35 TRUE
34 TRUE
33
32
31
30
29
PCIE_SSD_D2R_N & lt; 1 & gt;
PCIE_SSD_D2R_P & lt; 1 & gt;
OUT
12 64 67
OUT
12 64 67
PCIE_SSD_D2R_N & lt; 0 & gt;
PCIE_SSD_D2R_P & lt; 0 & gt;
OUT
12 64 67
OUT
12 64 67
IN
12 64 67
IN
12 64 67
PCIE_CLK100M_SSD_N
PCIE_CLK100M_SSD_P
59
60
61
62
PCIe polarity inversion and lane reversal
are only permitted on the device side,
provided the device PHY supports it.
B
63
Gumstick3 Connector
10%
2 6.3V
CERM-X5R
U3740
1%
1/20W
MF
201
37
PP3V3_S0
C3740
0.1UF
VDD
232K
OUT
NC
61 59 56 45 44 43 42
18 17 15 13 12 11 8
41 40 39 38 36 30 27
74 65 64 62
17 35 36 37 38 40 46 49 50 59
61 62 64 65
30 41 62 64
1
R37401
TRUE 18
TRUE 19
20
TRUE 21
TRUE 22
23
24
25
26
27
28
54
55
56
57
58
Supervisor & CLKREQ# Isolation
PP3V3_S0SW_SSD
1%
1/20W
MF
201 2
100K
GND_VOID F-RT-SM GND_VOID
53
1
52
2
64
SMC_OOB1_R2D_CONN_L
51
3
SMC_OOB1_D2R_CONN_L
64
4
50
5
SSD_PCIE_SEL_L
OUT 16 64
49
6
SSD_DEVSLP
IN 15 64
48
7
SMC_PWRFAIL_WARN_L
IN 37
47
8
SSD_PWR_EN
IN 15 30 58 59 64
9
SMC_PWRFAIL_WARN_L Signal has PU on SSD module
46
10
45 TRUE PCIE_SSD_D2R_N & lt; 3 & gt;
TRUE 11
OUT 12 64 67
44 TRUE PCIE_SSD_D2R_P & lt; 3 & gt;
TRUE 12
OUT 12 64 67
43
13
42 TRUE PCIE_SSD_D2R_N & lt; 2 & gt;
14
TRUE
OUT 12 64 67
41 TRUE PCIE_SSD_D2R_P & lt; 2 & gt;
TRUE 15
OUT 12 64 67
40
16
17
67 64
1
0.1UF
67 12
PCIE_SSD_R2D_N & lt; 2 & gt;
PCIE_SSD_R2D_P & lt; 2 & gt;
37
0201
2 GND_VOID=TRUE
10% 16V X5R-CERM
1
0.1UF
67 12
67 64
0201
2
0.1UF
IN
PCIE_SSD_R2D_N & lt; 3 & gt;
PCIE_SSD_R2D_P & lt; 3 & gt;
0201
67 64
1
0.1UF
67 12
67 64
2
0.1UF
67 12
0201
67 64
1
PP3V3_S0
SSD_RESET_CONN_L
NC_SSD_MFG_RSVD
IN
5
R37001
5%
1/20W
MF
201 2
100K
J3700
SMC_OOB1_R2D_L
1
NC
3
R37101
514S0449
CRITICAL
SSD-GS3
74 65 64 62 61
36 30 27 18 17 15 13 12 11 8
59 56 45 44 43 42 41 40 39 38
08
PP3V3_S0
0.1UF
2
U3710
0201
TDFN
P3V3SSD_VMON
2 SENSE +
0.7V DLY
4 RESET*
MR* 3
7 IN
IN
15
IN
15 30 58 59 64
12
5
OUT
GND
9
R3742
SSD_PWR_EN
SSD_CLKREQ_L
(OD)
THRM
PAD
1
SSD_RESET_L
EN 6
OUT 8
100K
1%
1/20W
MF
2 201
A
SYNC_MASTER=J41_MLB
SYNC_DATE=04/09/2013
PAGE TITLE
SSD Connector
DRAWING NUMBER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
37 OF 121
SHEET
30 OF 76
1
A
8
7
6
5
4
3
2
PP1V8_CAM
L3902
72 32 31
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.35V
1
L3906
1
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.35V
N7
N8
N6
1
FBGA
SYM 3 OF 3
CRITICAL
MIPI_AGND
PCIE_GND
A4
D4
G4
K4
N4
10%
2 6.3V
CERM-X5R
0201
N13
P14
P15
R15
GND_CAM_PVSSD
K15
L12
L13
L14
L15
A1
A6
B6
D1
D5
E5
G1
G6
G7
G8
G9
H5
H6
H7
H8
H9
J5
J6
J7
J8
J9
K1
K5
K6
K7
K8
K9
A14
M9
N1
P5
R1
R5
E9
C
B
4.7UF
10%
2 6.3V
CERM-X5R
0201
C3913
PLACE_NEAR=U3900.K13:4MM
4.7UF
20%
6.3V
2 X5R
402
20%
6.3V
2 X5R
402
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=0.675V
100K
DDR_VDDIO_CK G5
1
1
C3930
1.0UF
C3927
20%
6.3V
0201-1
1
PP1V2_CAM_XTALPCIEVDD
C3931
10UF
31
R3931
20%
6.3V
2 CERM-X5R
0402-1
2 X5R
1
1
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.2V
C3932
1.0UF
C3970
1
C3971
1000PF
10%
10%
16V
2 X7R-CERM
0201
2 6.3V
CERM-X5R
C3933
0201
1
C3972
1
0.1UF
C3973
1
1000PF
10%
2 6.3V
CERM-X5R
0201
C3974
0.1UF
10%
2 16V
X7R-CERM
0201
10%
2 6.3V
CERM-X5R
0201
1
C3975
1
0.1UF
C3914
31
GND_CAM_PVSSC
20%
6.3V
2 CERM-X5R
0402-1
72 32
1
(=PP3V3_S3RS0_CAMERA)
SR_VDD_3P3D
C3919
0.1UF
BYPASS=U3900.D7:2.54MM
C3918
1
1000PF
10%
6.3V
0201
2 CERM-X5R
C3938
1
C3916
0.1UF
10%
16V
2 X7R-CERM
0201
10%
2 6.3V
CERM-X5R
0201
1
C3917
1000PF
10%
2 16V
X7R-CERM
0201
1
C3910
0.1UF
10%
2 6.3V
CERM-X5R
0201
1
72 32
10%
2 16V
X7R-CERM
0201
C3928
4.7UF
20%
6.3V
2 X5R
402
SR_VLXC_O
SR_VLXD_O
H14
H15
J13
J14
J15
69 32
P1V2_CAM_SRVLXC_PHASE 31
1
4.7UF
P1V35_CAM_SRVLXD_PHASE
K13
K14
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
DIDT=TRUE
PP1V35_CAM
31
PP1V8_CAM
32 31
20%
6.3V
2 X5R
402
GND_CAM_PVSSD
1
2
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=0V
31 32 72
PP1V2_CAM_XTALPCIEVDD
1
C3942
4.7UF
PP1V8_CAM
1
F6
F7
F8
F9
L6
L5
L8
L9
C3941
2.2UF
1
C3939
1UF
PP1V2_CAM
PP3V3_S3RS0_CAMERA
20%
6.3V
2 CERM
402-LF
20%
6.3V
2 X5R
402
1
15 41
1K
10%
6.3V
2 CERM-X5R
0201
10%
16V
2 X7R-CERM
0201
1
C3935
0.1UF
10%
2 6.3V
CERM-X5R
0201
1
C3936
1000PF
10%
2 16V
X7R-CERM
0201
1
1K
0.1UF
64 32
NOSTUFF
R3991
64 29 13
OUT
32 31
PCIE_WAKE_L
72 32
OUT
72 32
OUT
OUT
72 32
OUT
72 32
OUT
72 32
OUT
72 32
17 31
72 32
OUT
OUT
72 32
OUT
72 32
OUT
72 32
OUT
72 32
OUT
72 32
OUT
31
31 32 72
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.2V
MAKE_BASE=TRUE
17 31
C3960
0.1UF
10%
2 6.3V
CERM-X5R
0201
OUT
72 32
CAM_UARTRXD
OUT
72 32
CAM_UARTCTS
OUT
72 32
OUT
72 32
OUT
72 32
1
R3976
OUT
72 32
5%
1/20W
MF
2 201
R3912
1
240
1%
1/20W
MF
201
OUT
72 32
51K
7
1
0
2
5%
1/20W
MF
0201
PP1V8_CAM
31
OUT
72 32
OUT
2
72 32
OUT
72 32
OUT
6
FBGA
SYM 2 OF 3
L3
M4
N3
M3
M1
M2
P4
N2
P3
P2
J4
R2
L1
P1
R4
MEM_CAM_BA & lt; 0 & gt;
MEM_CAM_BA & lt; 1 & gt;
MEM_CAM_BA & lt; 2 & gt;
K3 DDR_BA0
L2 DDR_BA1
K2 DDR_BA2
DDR_DQS_P0 E2
DDR_DQS_N0 D2
MEM_CAM_DQS_P & lt; 0 & gt;
MEM_CAM_DQS_N & lt; 0 & gt;
MEM_CAM_CLK_P
MEM_CAM_CLK_N
H2 DDR_CK_P0
G2 DDR_CK_N0
DDR_DQS_P1 A2
DDR_DQS_N1 A3
MEM_CAM_DQS_P & lt; 1 & gt;
MEM_CAM_DQS_N & lt; 1 & gt;
MEM_CAM_DM & lt; 0 & gt;
MEM_CAM_DM & lt; 1 & gt;
C1 DDR_DM0
C4 DDR_DM1
MEM_CAM_ZQ_S2
MEM_CAM_CKE
MEM_CAM_CS_L
G3 DDR_ZQ
J3 DDR_CKE
L4 DDR_CS*
DDR_RAS*
DDR_WE*
DDR_CAS*
DDR_RESET*
CRITICAL
OMIT_TABLE
OUT
18
IN
5%
1/20W
MF
2 201
MEM_CAM_A & lt; 0 & gt;
MEM_CAM_A & lt; 1 & gt;
MEM_CAM_A & lt; 2 & gt;
MEM_CAM_A & lt; 3 & gt;
MEM_CAM_A & lt; 4 & gt;
MEM_CAM_A & lt; 5 & gt;
MEM_CAM_A & lt; 6 & gt;
MEM_CAM_A & lt; 7 & gt;
MEM_CAM_A & lt; 8 & gt;
MEM_CAM_A & lt; 9 & gt;
MEM_CAM_A & lt; 10 & gt;
MEM_CAM_A & lt; 11 & gt;
MEM_CAM_A & lt; 12 & gt;
MEM_CAM_A & lt; 13 & gt;
MEM_CAM_A & lt; 14 & gt;
DDR_AD00
DDR_AD01
DDR_AD02
DDR_AD03
DDR_AD04
DDR_AD05
DDR_AD06
DDR_AD07
DDR_AD08
DDR_AD09
DDR_AD10
DDR_AD11
DDR_AD12
DDR_AD13
DDR_AD14
12
100K
PP1V2_CAM_XTALPCIEVDD
1
BI
DDR_DQ00
DDR_DQ01
DDR_DQ02
DDR_DQ03
DDR_DQ04
DDR_DQ05
DDR_DQ06
DDR_DQ07
DDR_DQ08
DDR_DQ09
DDR_DQ10
DDR_DQ11
DDR_DQ12
DDR_DQ13
DDR_DQ14
DDR_DQ15
C2
E3
E4
D3
F3
F1
F4
F2
B5
C3
B1
B4
A5
C5
B2
B3
H3
J2
H4
R3
MEM_CAM_DQ & lt; 0 & gt;
MEM_CAM_DQ & lt; 1 & gt;
MEM_CAM_DQ & lt; 2 & gt;
MEM_CAM_DQ & lt; 3 & gt;
MEM_CAM_DQ & lt; 4 & gt;
MEM_CAM_DQ & lt; 5 & gt;
MEM_CAM_DQ & lt; 6 & gt;
MEM_CAM_DQ & lt; 7 & gt;
MEM_CAM_DQ & lt; 8 & gt;
MEM_CAM_DQ & lt; 9 & gt;
MEM_CAM_DQ & lt; 10 & gt;
MEM_CAM_DQ & lt; 11 & gt;
MEM_CAM_DQ & lt; 12 & gt;
MEM_CAM_DQ & lt; 13 & gt;
MEM_CAM_DQ & lt; 14 & gt;
MEM_CAM_DQ & lt; 15 & gt;
MEM_CAM_RAS_L
MEM_CAM_WE_L
MEM_CAM_CAS_L
MEM_CAM_RESET_L
F13
E12
F12
D12
D11
C11
100K
5%
1/20W
MF
R12 CAM_RAMCFG0
31
201 2
P12 CAM_RAMCFG1
31
P11 CAM_RAMCFG2
31
P10 CAM_GPIO3
P9 TP_CAM_PLL_BYPASS
N11
NC
NOSTUFF
N10
NC
1
N9
GPIO_00
GPIO_01
GPIO_02
GPIO_03
GPIO_04
GPIO_05
GPIO_06
GPIO_07
I2C_CLK_DBG
I2C_CLK_SENSOR
I2C_DATA_DBG
I2C_DATA_SENSOR
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST*
JTAG_SRST*
CAMERA_CLKREQ_L
CAM_PCIE_RESET_L
CAM_PCIE_WAKE_L
31
D15
R10
C15
R9
TP_CAM_JTAG_TCK
TP_CAM_JTAG_TDI
TP_CAM_JTAG_TDO
TP_CAM_JTAG_TMS
TP_CAM_JTAG_TRST_L
CAM_JTAG_SRST_L
OUT
P13 PCIE_CLKREQ*
R14 PCIE_RST*
N12 PCIE_WAKE*
CAM_PWR_SEL
CAM_DEBUG_RESET_L
32 72
BI
32 72
BI
32 72
BI
32 72
BI
32 72
BI
32 72
BI
32 72
BI
32 72
BI
UARTRXD E13
UARTTXD E14
CAM_UARTRXD
TP_CAM_UARTTXD
TEST_OUT J12
TEST_MODE M10
32 72
32
IN
BI
32 72
18
IN
BI
32 72
BI
32 72
BI
BI
32 72
BI
32 72
BI
32 72
BI
32 72
BI
32 72
CAM_XTAL_SEL
R3901
100K
0.1UF
5%
1/20W
MF
10%
6.3V
2 CERM-X5R
0201
32 31
CAM_A1
31
100K
NO STUFF
1
PU on PCH page
4
R3911
100K
31
A1 SILICON BUG
31 32
1
R3910
2 201
CAM_JTAG_SRST_L
PP1V8_CAM
CAM_TEST_MODE
100K
5%
1/20W
MF
2 201
5%
1/20W
MF
2 201
CAM_XTAL:YES
R3904
1
R3906
100K
CAM_XTAL_FREQ
PU = 25MHz
5%
1/20W
MF
2 201
100K
5%
1/20W
MF
SYNC_MASTER=J41_MLB
2 201
CAM_XTAL_SEL
CAM_XTAL:NO
PAGE TITLE
31
DRAWING NUMBER
1
R3907
32 72
32
Apple Inc.
100K
5%
1/20W
MF
2 201
3
SYNC_DATE=04/02/2013
Camera 1 of 2
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
5
31
31
CAM_TEST_OUT
5%
1/20W
MF
CAM_SENSOR_WAKE_L
CAMERA_PWR_EN
32 72
OUT
31
R3915
32 72
OUT
31
PP1V8_CAM
1
31
OUT
B
31
PD = 1.35V
2 201
1
OUT
5%
1/20W
MF
201 2
31
CAM_XTAL_FREQ
32 72
1
C3990
31
CAM_TEST_OUT
CAM_TEST_MODE
STRAP_XTAL_FREQ C13
32 72
BI
NOSTUFF
1
100K
CAM_UARTCTS
TP_CAM_UARTRTS
DDR_PWR_SEL
RESET*
SENSOR_WAKE*
SHUTDOWN*
32 72
BI
G12
E15
R13
H12
R3937
NC
UARTCTS D13
UARTRTS D14
STRAP_XTAL_SEL C12
BI
C
R3936
A13 XTAL_P
A12 XTAL_N
I2C_CAM_SMBDBG_CLK
I2C_CAM_SCK
I2C_CAM_SMBDBG_DAT
I2C_CAM_SDA
IN
31
64 32
10%
2 6.3V
CERM-X5R
0201
A8 PCIE_TDP0
B8 PCIE_TDN0
CLK25M_CAM_CLKP
CLK25M_CAM_CLKN
OUT
69 32
R3990
72 32
PP1V2_CAM
PP1V35_CAM
69 32
5%
1/20W
MF
201 2
C3937
BCM15700
VSENSE_C M11
VSENSE_D K12
PCIE_CAMERA_D2R_C_P
PCIE_CAMERA_D2R_C_N
B10 PCIE_REFCLKP
A10 PCIE_REFCLKN
B9 PCIE_TESTP
NC
C9 PCIE_TESTN
NC
1
PP1V2_CAM_XTALPCIEVDD
5%
1/20W
MF
2 201
1000PF
U3900
XTAL_AVDD1P2 B13
51K
C3934
BYPASS=U3900.F15:2.54MM
72 32
R3975
1
BYPASS=U3900:7mm
BYPASS=U3900:3mm
BYPASS=U3900:3mm
BYPASS=U3900:5mm
BYPASS=U3900:5mm
BYPASS=U3900:5mm
R11
1
0.1UF
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.2V
B15
L3901:1
L3902:1
C3940
10%
2 10V
X5R
402
BYPASS=U3900.G15:2.54MM
31
OUT
R39131 R39141
5%
1/20W
MF
201 2
VDD1P8_O G15
OUT
B7 PCIE_RDP0
A7 PCIE_RDN0
PCIE_CLK100M_CAMERA_C_P
PCIE_CLK100M_CAMERA_C_N
XW3901
SM
VDD_3P3A J11
VDD1P2_O F15
IN
69 32
C3926
IN
69 32
PLACE_NEAR=U3900.M14:2.54MM
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
DIDT=TRUE
IN
69 32
PCIE_CAMERA_R2D_P
PCIE_CAMERA_R2D_N
IN
69 32
2
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=0V
M13
N14
P8 MIPI_DP0
R8 MIPI_DM0
B11 TP_CAM_TEST_MODE0
C14 TP_CAM_TEST_MODE1
B14 TP_CAM_TEST_MODE2
A15 TP_CAM_LV_JTAG_TCK
E11 TP_CAM_LV_JTAG_TDI
E10 TP_CAM_LV_JTAG_TDO
F11 TP_CAM_LV_JTAG_TMS
F10 TP_CAM_LV_JTAG_TRSTN
G11
NC
G10
NC
H11
NC
H10
NC
J10
NC
K11
NC
K10
NC
L11
PP1V8_CAM
32 31
NC
L10
NOSTUFF
NC
1
DEBUG_00
DEBUG_01
DEBUG_02
DEBUG_03
DEBUG_04
DEBUG_05
DEBUG_06
DEBUG_07
DEBUG_08
DEBUG_09
DEBUG_10
DEBUG_11
DEBUG_12
DEBUG_13
DEBUG_14
DEBUG_15
DEBUG_16
CRITICAL
OMIT_TABLE
P6
69 32
1
FBGA
SYM 1 OF 3
MIPI_DP1
NC
R6 MIPI_DM1
NC
XW3900
SM
GND_CAM_PVSSC
VDD_1P35A F14
VDDC
IN
BYPASS=U3900.J1:2.54MM
BYPASS=U3900.L7:2.54MM
BYPASS=U3900.J1:2.54MM
BYPASS=U3900.D6:2.54MM
BYPASS=U3900.L7:2.54MM
BYPASS=U3900.D6:2.54MM
(=PP3V3_S3RS0_CAMERA)
VSSC
IN
72 32
P7 MIPI_CP_CLK
R7 MIPI_CM_CLK
MIPI_DATA_P
MIPI_DATA_N
IN
0.1UF
10%
2 6.3V
CERM-X5R
0201
MIPI_CLK_P
MIPI_CLK_N
IN
72 32
C3951
1000PF
1
4.7UF
20%
6.3V
2 X5R
402
20%
6.3V
2 X5R
402
U3900
1
SR_VDD_3P3C
PLACE_NEAR=U3900.M13:4MM
BCM15700
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.8V
M14
M15
N15
31
1008
C3915
PLACE_NEAR=U3900.M13:2.54MM
BYPASS=U3900.F6:2.54MM
BYPASS=U3900.F9:2.54MM
BYPASS=U3900.F6:2.54MM
BYPASS=U3900.L9:2.54MM
BYPASS=U3900.F9:2.54MM
BYPASS=U3900.L9:2.54MM
PP1V8_CAM
OTP_VDD3P3 D7
1
4.7UF
10%
2 6.3V
CERM-X5R
0201
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.2V
PLL_VDD1P8 D6
2
5%
1/20W
MF
201
L3901
MIPI_AVDD1P8 L7
SR_PVSSD
D
330K
5%
1/20W
MF
201
2
0603
10UF
20%
6.3V
0201-1
PP1V2_CAM_PCIE_PVDD_FLT
DDR_AVDD1P8 J1
1
31
1.0UH-1.6A-55MOHM
1
2
P1V2_CAM_SRVLXC_PHASE
0.1UF
L3904
PP1V2_CAM_PCIE_VDD_FLT
2
31
R3935
330K
5%
1/20W
MF
2 201
31
1
R3933
330K
I2C_CAM_SMBDBG_CLK 31
I2C_CAM_SMBDBG_DAT 31
17 31
1
PP1V2_CAM
220-OHM-1.4A
PCIE_PVDD1P2 D9
31
1
5%
1/20W
MF
2 201
0603
1
31
CAM_RAMCFG2
CAM_RAMCFG1
CAM_RAMCFG0
100K
5%
1/20W
MF
2 201
2
32 72
10%
2 6.3V
CERM-X5R
0201
SR_PVSSC
5%
1/20W
MF
2 201
R3920 1R3921
GND_CAM_PVSSD
1
PP0V675_CAM_VREF
PCIE_VDD1P2 C8
100K
5%
1/20W
MF
2 201
PP1V8_CAM
32 31
L3903
VDDO18
8
1
R3934
100K
5%
1/20W
MF
2 201
220-OHM-1.4A
PMU_AVSS
B12 XTAL_AVSS
A
C3912
1
0.1UF
20%
2 6.3V
X5R
0201-1
31
2 X5R
31
C3924
1
R3932
100K
1
DDR_VREF_O N5
GND_CAM_PVSSC
1
NOSTUFF
NOSTUFF
1
R3930
1008
C3900
0.1UF
31
C3923
1.0UF
10%
2 6.3V
CERM-X5R
0201
DDR_VDDIO
G14
M12
1
0.1UF
20%
6.3V
2 X5R
0201-1
2
C3922
0.1UF
OMIT_TABLE
C10
C7
1
NOSTUFF
1
31
0402
BCM15700
D
C3921
1.0UF
22NH
PP1V35_DDR_CLK
U3900
1.0UH-1.6A-55MOHM
1
2 P1V35_CAM_SRVLXD_PHASE
BYPASS=U3900.K13:2.54MM
PP1V35_CAM
1
31 32
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
39 OF 121
SHEET
31 OF 76
1
A
8
6
5
1
BYPASS=U4000.B2:4mm
C4002
1
10UF
C4003
1
10UF
20%
6.3V
2 CERM-X5R
0402-1
PP0V675_CAM_VREF
1
0201
0
2
72
0.47UF
BYPASS=U4000.D2:4mm
1
1
0.1UF
C4006
2.2UF
20%
10V
2 X5R-CERM
402
C4007
1
2
0.1UF
72
20%
10V
2 X5R-CERM
402
0.1UF
69 14
10%
2 6.3V
CERM-X5R
0201
69 31
BYPASS=U4000.R9:4mm
69 12
C4011
1K
5%
1/20W
MF
201
72 31
IN
72 31
IN
72 31
IN
72 31
IN
72 31
IN
72 31
IN
72 31
C
IN
72 31
2
IN
72 31
IN
72 31
72 31
IN
72 31
MEM_CAM_BA & lt; 0 & gt;
MEM_CAM_BA & lt; 1 & gt;
MEM_CAM_BA & lt; 2 & gt;
IN
IN
U4000
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14
4GB-DDR3-256MX16
FBGA
NC
H5TC4G63AFR
72 31
84.5
1%
1/20W
MF
2 201
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
IN
72 31
IN
72 31
MEM_CAM_ODT
BI
31 72
BI
31 72
BI
31 72
BI
31 72
BI
31 72
BI
PCIE_CAMERA_D2R_C_N
C4030
IN
PCIE_CLK100M_CAMERA_P
C4061
IN
PCIE_CLK100M_CAMERA_N
C4062
1
14 69
2
PCIE_CAMERA_D2R_N OUT
10% 16V X5R-CERM 0201
1
14 69
D
PCIE_CLK100M_CAMERA_C_P
2
10% 16V X5R-CERM
1
10% 16V X5R-CERM
0201
OUT
31 69
OUT
31 69
IN
0201
PCIE_CLK100M_CAMERA_C_N
2
IN
BI
12PF
CAM_XTAL:NO
SYSCLK_CLK25M_CAMERA
CLK25M_CAM_XTALP
0201
CRITICAL
0
1
NC Y4000
NC SM-3.2X2.5MM
0
1
2
CLK25M_CAM_CLKP
31 69
0201 5%
MF
1/20W
R4009
2
CLK25M_CAM_XTALP_R
NOSTUFF
69
5%
1/20W
MF
1
1
R4012
1M
1%
1/20W
MF
2 201
25.000MHZ-12PF-20PPM
CAM_XTAL:YES
0
5%
1/20W
MF
0201
2
CAM_XTAL:YES
R4010
31 72
31 72
MEM_CAM_DQS_P & lt; 1 & gt;
MEM_CAM_DQS_N & lt; 1 & gt;
BI
69
5% CAM_XTAL:YES
25V
NP0-C0G-CERM
0201
CLK25M_CAM_XTALN
1
0
5%
1/20W
MF
0201
NOTE: TBD PPM crystal required
2
CLK25M_CAM_CLKN OUT 31 69
CAM_XTAL:YES
CAM_XTAL:NO
1
C4016
100PF
5%
2 25V
NP0-CERM
0201
31 72
BI
2
31 72
DQSU C7
DQSU* B7
1
31 72
BI
31 72
C
PP1V8_CAM
31
1
D7
C3
C8
C2
A7
A2
B8
A3
MEM_CAM_DQ & lt; 8 & gt;
MEM_CAM_DQ & lt; 9 & gt;
MEM_CAM_DQ & lt; 10 & gt;
MEM_CAM_DQ & lt; 11 & gt;
MEM_CAM_DQ & lt; 12 & gt;
MEM_CAM_DQ & lt; 13 & gt;
MEM_CAM_DQ & lt; 14 & gt;
MEM_CAM_DQ & lt; 15 & gt;
DML E7
DMU D3
MEM_CAM_DM & lt; 0 & gt;
MEM_CAM_DM & lt; 1 & gt;
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
R4005
100K
BI
31 72
BI
31 72
BI
31 72
BI
31 72
BI
31 72
BI
31 72
BI
31 72
CAM_WAKE:NO
BI
31 72
R40311
L8 ZQ
T2
MEM_CAM_DQ & lt; 0 & gt;
MEM_CAM_DQ & lt; 1 & gt;
MEM_CAM_DQ & lt; 2 & gt;
MEM_CAM_DQ & lt; 3 & gt;
MEM_CAM_DQ & lt; 4 & gt;
MEM_CAM_DQ & lt; 5 & gt;
MEM_CAM_DQ & lt; 6 & gt;
MEM_CAM_DQ & lt; 7 & gt;
BI
K1 ODT
MEM_CAM_RESET_L
IN
2
PCIE_CAMERA_D2R_P OUT
10% 16V X5R-CERM 0201
1
31 72
K9 CKE
L2 CS*
MEM_CAM_ZQ_DDR
NO STUFF
C4014
BI
J7 CK
K7 CK*
MEM_CAM_CKE
MEM_CAM_CS_L
IN
E3
F7
F2
F8
H3
H8
G2
H7
MEM_CAM_DQS_P & lt; 0 & gt;
MEM_CAM_DQS_N & lt; 0 & gt;
J3 RAS*
K3 CAS*
L3 WE*
MEM_CAM_CLK_P
MEM_CAM_CLK_N
IN
C4031
R4007
69
5%
25V
NP0-C0G-CERM
0201
DQSL F3
DQSL* G3
M2 BA0
N8 BA1
M3 BA2
MEM_CAM_RAS_L
MEM_CAM_CAS_L
MEM_CAM_WE_L
IN
72 31
R4020
12PF
CAM_XTAL:YES 1
2
NC
NC
NC
NC
NC
CRITICAL
IN
1
IN
C4015
J1
J9
L1
L9
M7
1
IN
PCIE_CAMERA_D2R_C_P
31 69
CAM_XTAL:YES
4 2
IN
72 31
R4003
IN
72 31
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
69 17
3
72 31
1
MEM_CAM_A & lt; 0 & gt;
MEM_CAM_A & lt; 1 & gt;
MEM_CAM_A & lt; 2 & gt;
MEM_CAM_A & lt; 3 & gt;
MEM_CAM_A & lt; 4 & gt;
MEM_CAM_A & lt; 5 & gt;
MEM_CAM_A & lt; 6 & gt;
MEM_CAM_A & lt; 7 & gt;
MEM_CAM_A & lt; 8 & gt;
MEM_CAM_A & lt; 9 & gt;
MEM_CAM_A & lt; 10 & gt;
MEM_CAM_A & lt; 11 & gt;
MEM_CAM_A & lt; 12 & gt;
MEM_CAM_A & lt; 13 & gt;
MEM_CAM_A & lt; 14 & gt;
VREFDQ H1
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
VDD
1K
NOSTUFF
IN
31 69
2
PCIE_CAMERA_R2D_N OUT
10% 16V X5R-CERM 0201
1
R4008
VDDQ
IN
C4032
0.1UF
10%
2 6.3V
CERM-X5R
0201
R40021
72 31
PCIE_CAMERA_R2D_C_N
0.1UF
1K
IN
IN
0.1UF
69 12
72 31
2
PCIE_CAMERA_R2D_P OUT
10% 16V X5R-CERM 0201
0.1UF
69 31
1
10%
6.3V
CERM-X5R 2
0201
IN
1
0.1UF
0.1UF
72 31
C4033
0.1UF
C4010 1
5%
1/20W
MF
201 2
PCIE_CAMERA_R2D_C_P
1
0.1UF
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.675V
1%
1/20W
MF
201 2
IN
C4009
PP0V675_MEM_CAM_VREFCA
R40231
1
5%
1/20W
MF
CAM_WAKE:YES
2 201
R4030
64 32
CAM_SENSOR_WAKE_L_CONN
1
0201
0
2
31
CAM_SENSOR_WAKE_L
5%
1/20W
MF
0
R4021
82
72
1%
1/20W
MF
2 201
MEM_CAM_CKE_R
31
NO STUFF
IN
R4006
IN
31 72
5%
1/20W
MF
0201 2
VSS
B1
B9
D1
D8
E2
E8
F9
G1
G9
5%
25V
2 NP0-CERM
0201
31 72
RESET*
VSSQ
100PF
IN
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
1
C4008
2.2UF
10%
2 6.3V
CERM-X5R
0201
69 14
BYPASS=U4000.K2:4mm
1
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.675V
1%
1/20W
MF
201 2
72 31
C4005
PP0V675_MEM_CAM_VREFDQ
5% MF
1/20W
1K
72 31
1
BYPASS=U4000.H9:4mm
R40221
72 31
C4004
20%
10%
6.3V
4V
2 CERM-X5R-1 2 CERM-X5R
201
0201
20%
6.3V
2 CERM-X5R
0402-1
R4000
72 31
3
PP1V35_CAM
BYPASS=U4000.A1:4mm
D
4
VREFCA M8
72 31
7
1
R4004
B
B
240
1%
1/20W
MF
2 201
CAMERA SENSOR
L4009
90-OHM-50MA
TCM0605-1
SYM_VER-1
CRITICAL
1
4
MIPI_CLK_N
IN
31 72
2
3
MIPI_CLK_P
IN
31 72
J4002
CCR20-AK7100-1
F-RT-SM
14
PLACE_NEAR=J4002.2:2.54MM
CRITICAL
1
2
72 64
3
72 64
4
5
72 64
6
72 64
MIPI_CLK_CONN_N
MIPI_CLK_CONN_P
CAM_SENSOR_WAKE_L_CONN
MIPI_DATA_CONN_N
MIPI_DATA_CONN_P
L4007
90-OHM-50MA
TCM0605-1
SYM_VER-1
32 64
1
4
MIPI_DATA_N
BI
31 72
2
3
MIPI_DATA_P
BI
31 72
7
A
ALS
8
9
10
11
12
13
64
SMBUS_SMC_1_S0_SDA 14 37
BI
SMBUS_SMC_1_S0_SCL 14 37
IN
I2C_CAM_SCK
IN 31 64
I2C_CAM_SDA
BI 31 64
PP5V_S3RS0_ALSCAM_F
40 43 44 64 69 73
PLACE_NEAR=J4002.5:2.54MM
40 43 44 64 69 73
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V
CRITICAL
L4010
FERR-120-OHM-1.5A
2
1
PP5V_S0
0402-LF
C4013 1
0.1uF
20%
10V
CERM 2
402
518S0892
SYNC_MASTER=J41_MLB
PAGE TITLE
16 17 45 46 51 52 56 58 59 61
62 64
DRAWING NUMBER
Apple Inc.
NOSTUFF
L4011
NOTICE OF PROPRIETARY PROPERTY:
7
6
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
35 47 49 54 55 58 62 64
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
77.2 mA nominal max
96.2 mA peak
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
R
FERR-120-OHM-1.5A
2
1
PP5V_S4RS3
0402-LF
8
SYNC_DATE=03/20/2013
Camera 2 of 2
PAGE
40 OF 121
SHEET
32 OF 76
1
A
8
7
6
5
4
3
2
1
PP3V3_S4
64 62 58 39 38 36 33 29
1
R4410
470K
Q4410
DMN5L06VK-7
1
R4411
SOT-563
SMC_PME_S4_DARK_L
1
6
S
SMC_PME_SDCONN
G 5
SOT-563
SDCONN_STATE_CHANGE Isolation
4
3
38 37 33 25
DMN5L06VK-7
SMC_PME_S4_DARK_L
S
25
33
D
To SMC37
38
D
5%
1/20W
MF
201 2
Q4410
D
G 2
470K
D
5%
1/20W
MF
2 201
PP3V3_S3
64 62 58 41 40 36 19 18 15
CRITICAL
U4410
6
74AUP1G09
SOT891
VCC
16 15
XDP_SDCONN_STATE_CHANGE_L
OUT
A 2
4 Y
BYPASS=U4410.5:5mm
To PCH
C4410
B 1
1
0.1UF
NC 5
10%
6.3V
CERM-X5R 2
0201
NC
3
GND
PP3V3_S4
64 62 58 39 38 36 33 29
BYPASS=U4430.1:5mm
C4430 1
C
0.1UF
C
CRITICAL
1
10%
16V
X5R-CERM 2
0201
VDD
U4430
SLG4AP014V
TDFN
2
LOW_PWR
3
RST_IN*
6
DET_IN
(IPU)
4
DLY
(OD)
8
DET_CHNGD*
(OD)
7
XOR
FROM SD CONN - & gt;
DLY block is 20ms nominal
RST_OUT*
RST
LOGIC
(IPU)
NC
SDCONN_STATE_CHANGE_SAK_L
SDCONN_DETECT_L
OUT
34 75
DET_OUT
THRM
PAD
9
5
GND
SD CARD CONNECTOR
CRITICAL
516-0253
J4400
SD-CARD-K16
CRITICAL
F-RT-TH-1
R4480
L4400
B
75 34
IN
75 34
OUT
75 34
BI
75 34
BI
75 34
BI
75 34
BI
SDCONN_CLK R4479 33
SDCONN_CMD
SDCONN_DATA & lt; 0 & gt;
SDCONN_DATA & lt; 1 & gt;
SDCONN_DATA & lt; 2 & gt;
SDCONN_DATA & lt; 3 & gt;
1
2 5% 1/20W
MF
R4461
R4471
R4472
R4473
R4474
R4481
0
402
5% MF-LF 1/16W
47NH-1.3OHM 0402
2 SDCONN_CLK_R1
201 SDCONN_CLK_L 1
2 5% 1/20W MF 0201
0 1
2 5% 1/20W MF 0201
0 1
2 5% 1/20W MF 0201
0 1
2 5% 1/20W MF 0201
0 1
2 5% 1/20W MF 0201
0 1
1
2
3
0
5%
SDCONN_CLK_R2
1
402
MF-LF 1/16W
6
SD_CONN_CLK
SDCONN_CMD_R
SDCONN_R_DATA & lt; 0 & gt;
SDCONN_R_DATA & lt; 1 & gt;
SDCONN_R_DATA & lt; 2 & gt;
SDCONN_R_DATA & lt; 3 & gt;
5
2
SD_CD_L
2
7
8
9
1
NC
NC
NC
NC
10
11
12
13
14
15
NOSTUFF
NOSTUFF
1
C4471
22PF
5%
2 50V
CERM
402
1
NOSTUFF
NOSTUFF
C4470
C4473
C4475
1
15PF
1
10PF
5%
50V
2 CERM
402
10PF
5%
50V
2 CERM
402
5%
50V
402
2 CERM
NOSTUFF
1
NOSTUFF
1
C4474
10PF
C4472
5%
10PF
2 50V
CERM
5%
50V
402
402
2 CERM
SDCONN_WP
OUT
34 PP3V3_S0_SD_CONN
75 34
NOSTUFF
1
16
4
R4482
17
0
18
5%
1/16W
MF-LF
2 402
19
NOSTUFF
1
20
B
VSS
VSS
CLK
CMD
DAT0
DAT1
DAT2
CD/DAT3
DAT4
DAT5
DAT6
DAT7
CARD_DETECT_SW
CARD_DETECT_GND
WRITE_PROTECT_SW
VDD
(CARD INSERTED = GROUND)
SHLD_PIN
SHLD_PIN
SHLD_PIN
SHLD_PIN
C4476
10PF
5%
2 50V
CERM
402
SD CARD
A
SYNC_MASTER=MASTER
SYNC_DATE=07/01/2011
PAGE TITLE
SD READER CONNECTOR
DRAWING NUMBER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
44 OF 121
SHEET
33 OF 76
1
A
8
7
6
5
4
3
2
1
3.3V S3 SD Card Switch
PP3V3_S5
42 29 28 18 17 16 15 13 11 8
74 64 62 60 59 58 57
1
NOSTUFF 1
R4595
VDD
10K
U4550
5%
1/20W
MF
201 2
15
D
7
ON
TDFN
CAP
2
SD_PWR_EN
IN
1.0UF
S
5
65 39 37 34 15
PP3V3_S0SW_SD
C4561
20%
6.3V 2
X5R
0201-1
D
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=3.3V
MAKE_BASE=TRUE
GND
1
U4550
4700PF
10%
10V 2
X7R
201
EDP: 1.05A
Part
SLG5AP1438V
Type
Load Switch
R(on)
15 mOhm Typ
17 mOhm Max
Current
2.5A
CRITICAL
CRITICAL
L4500
L4501
FERR-1000-OHM-450MA
1
15 34 37 39 65
3
8
1
D
CRITICAL
BYPASS=U4550.A2:5mm
C4560
PP3V3_S0SW_SD
SLG5AP1443V
P3V3_SD_FET_RAMP
FERR-1000-OHM-450MA
PP1V2_S0_SD_AVDD12
0402
BYPASS=U4500.46:5mm BYPASS=U4500.3:5mm
C4523 1
C4524 1
0.1UF
1.0UF
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
C4525 1
0.1UF
PP3V3_S0_SD_AVDD33
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.2V
2
10%
16V
X5R-CERM 2
0201
10%
16V
X5R-CERM 2
0201
10%
6.3V
X5R-CERM 2
0201-1
1
C4526 1 C4527
0.1UF
BYPASS=U4500.3:5mm
2
0402
BYPASS=U4500.43:5mm
1
C4528 1
0.1UF
10%
16V
X5R-CERM 2
0201
2.2UF
BYPASS=U4500.43:5mm
20%
6.3V
CERM 2
402-LF
10%
16V
X5R-CERM 2
0201
BYPASS=U4500.9:5mm
C
C
PP1V2_S3_SD_DVDD12
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.2V
C4520
1
0.1UF
2.2UF
10%
16V
X5R-CERM 2
0201
PP1V2_S0_SD_VUHS1
34 33
PP3V3_S0_SD_CONN
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.20MM
20%
4V
X5R-CERM 2
0201
VOLTAGE=3.3V
MAKE_BASE=TRUE
900mA max
PP3V3_S0_SD_CONN
47PF
45
44
DM
DP
7
8
X1
X2
4
5
RXN
RXP
U4500
GL3219
LQFN
PLACE_NEAR=U4500.4:5mm
C4510
USB3_SD_R2D_C_N
1
0.1UF
68 65 14
IN
C4511
PLACE_NEAR=U4500.5:5mm
USB3_SD_R2D_C_P
R4570
B
15
IN
SD_RESET_L
1
3.3K 2
1
0.1UF
2
68
GND_VOID=TRUE
10% 16V X5R-CERM 0201
68
2
GND_VOID=TRUE
10% 16V X5R-CERM 0201
USB3_SD_R2D_N
USB3_SD_R2D_P
SD_RTERM
10
SD_RESET_R_L
41
5%
1/20W
MF
201
C4570 1
0.047UF
680
1%
1/20W
MF
201 2
OMIT_TABLE
V33IN 22
VUHSI 30
24
25
29
28
SDCONN_DATA & lt; 1 & gt;
SDCONN_DATA & lt; 0 & gt;
SDCONN_DATA & lt; 2 & gt;
SDCONN_DATA & lt; 3 & gt;
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
1
BYPASS=U4500.31:5mm
0.1UF
10%
16V
X5R-CERM 2
0201
10%
6.3V
X5R-CERM 2
0201-1
BI
33 75
BI
33 75
BI
33 75
BI
33 75
PLACE_NEAR=U4500.1:5mm
68
TXN 1
68
TXP 2
C4512
USB3_SD_D2R_C_N
USB3_SD_D2R_C_P
26
23
27
20
SDCONN_CLK
SDCONN_WP
SDCONN_CMD
SDCONN_DETECT_L
35
34
36
37
1
0.1UF
C4513
SPI_CK
75
SPI_CS
75
SPI_SI
75
SPI_SO
RSTZ* (IPU)
1.0UF
C4518
10%
6.3V
X5R-CERM 2
0201-1
BYPASS=U4500.30:5mm
SD_CLK
(IPU) SD_WP
SD_CMD
(IPU) SD_CDZ
RTERM
100PF
1
1.0UF
20%
6.3V 2
X5R
402
1
1
USB3_SD_D2R_N
OUT
14 65 68
2
GND_VOID=TRUE
10% 16V X5R-CERM 0201
USB3_SD_D2R_P
OUT
14 65 68
SD_SPI_CLK
SD_SPI_CS_L
SD_SPI_MOSI
SD_SPI_MISO
75
LED 33
OUT
33 75
IN
0.1UF
2
GND_VOID=TRUE
10% 16V X5R-CERM 0201
PLACE_NEAR=U4500.2:5mm
33 75
BI
IN
B
33 75
C4590
33 75
1
1.0UF
10%
6.3V
X5R-CERM 2
0201-1
NOSTUFF 1
VCC
R4590
U4590
NC
3.3K
5%
1/20W
MF
201 2
512KB
USON
W25X05CL
5 DIO(IO0)
CRITICAL
2 DO(IO1)
NOSTUFF
THRM
PAD
BYPASS=U4590.8:5mm
NOSTUFF
NOSTUFF
1
R4591
3.3K
5%
1/20W
MF
2 201
CLK 6
CS* 1
WP* 3
HOLD* 7
SD_SPI_WP_L
SD_SPI_HOLD_L
GND
9
10%
6.3V 2
X5R
201
R45001
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
11
12
13
14
15
16
17
18
19
32
CRITICAL
6 GND
IN
SD_D1
SD_D0
SD_D2
SD_D3
C4531
1
5%
25V
NP0-CERM 2
0201
0201
47 THRM
PAD
USB_SD_DP
68 65 14
DVDD33 31
DVDD33 38
DVDD33 40
0
5%
1/20W
MF
0201 2
DVDD12 21
DVDD12 42
R4580
AVDD33 9
AVDD33 43
1
AVDD12 3
AVDD12 46
20%
6.3V 2
X5R
402
PMOS33 39
NO USB 2.0 INTERFACE
USB_SD_DM
4.7UF
C4530
BYPASS=U4500.22:5mm
C4522
4.7UF
BYPASS=U4500.30:5mm
1
5%
BYPASS=U4500.30:5mm 25V
NP0-C0G-CERM 2
BYPASS=U4500.39:5mm
C4550
C4521 1
C4529
34 33
1
BYPASS=U4500.38:5mm
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.8V
1
8
C4519
4
BYPASS=U4500.42:5mm BYPASS=U4500.21:5mm
USING ON CHIP CLOCK SOURCE MODE (CRYSTAL AS BACK-UP)
C4580
R4581
12PF
2
1
69
A
1
0
5%
1/20W
MF
0201
CRITICAL
25.000MHZ-12PF-20PPM
3
12PF
1
Y4580
2 4
NC
C4581
1
5%
25V
NP0-C0G-CERM
0201 NC
SDCLK_CLK25M_X2
SM-3.2X2.5MM
2
2
75 69
SDCLK_CLK25M_X2_R
1
R4582
1M
5%
1/20W
MF
2 201
69
SDSCLK_CLK25M_X1
SYNC_MASTER=MASTER
5%
25V
NP0-C0G-CERM
0201
SYNC_DATE=10/11/2010
PAGE TITLE
SD CONTROLLER (GL3219)
DRAWING NUMBER
Apple Inc.
& lt; SCH_NUM & gt;
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
45 OF 121
SHEET
34 OF 76
1
SIZE
D
A
8
7
6
5
4
3
2
1
Right USB Port A
D
USB Port Power Switch
D
CRITICAL
CRITICAL
L4605
U4600
FERR-120-OHM-3A
TPS2557DRB
PP5V_S3_RTUSB_A_ILIM
SON
16 14
OUT
65 61 59
2 IN_0
3 IN_1
XDP_USB_EXTA_OC_L
8 FAULT*
ILIM 5
USB_PWR_EN
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.15 mm
VOLTAGE=5V
OUT1 6
OUT2 7
4 EN
PP5V_S4RS3
CRITICAL
1
1
2
2
10UF
20%
6.3V
CERM-X5R
0402-1
C4691
1
0.1UF
10%
16V
X5R-CERM
0201
GND
C4696
1
C4690
R4600
220UF-35MOHM
USB_ILIM_R
20%
2 6.3V
POLY-TANT
CASE-B2-SM1
CRITICAL
2
J4600
USB3.0-J11-J13
22.1K
1%
1/20W
MF
201 2
1
R4601
PP5V_S3_RTUSB_A_F
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.375 mm
VOLTAGE=5V
1
0.01UF
10%
16V
X5R-CERM
0201
1
THRM
PAD
2
0603
C4605
USB_ILIM
9
64 62 58 55 54 49 47 32
1
F-RT-TH
CRITICAL
C4695
L4600
1
90-OHM
DLP0NS
10UF
20%
6.3V
CERM-X5R
0402-1
1
2
3
4
5
6
7
8
9
10
SYM_VER-1
2
4
22.1K
68
1%
1/20W
MF
2 201
68
3
1
USB2_EXTA_MUXED_N
USB2_EXTA_MUXED_P
2
68
68
CRITICAL
2
D4601
CRITICAL
2
D4600
ESD0P2RF-02LS
Current limit per port (R4600+R4601): 2.19A min / 2.76A max
ESD0P2RF-02LS
TSSLP-2-1
TSSLP-2-1
1
C
USB2_EXTA_MUXED_F_N
USB2_EXTA_MUXED_F_P
11
12
13
14
15
16
17
18
1
Mojo SMC Debug Mux
59 50 49 46 40 38 37 36 30 17
65 64 62 61
VBUS
SSTX+
SSTXGND
DD+
GND
SXRX+
SSRXGND
C
PP3V42_G3H
BYPASS=U4650.9:3:5mm
C4650 1
1
R4650
0.1UF
100K
68 38 37
IN
68 38 37
OUT
VCC
SMC_DEBUGPRT_RX_L
SMC_DEBUGPRT_TX_L
5 M+
4 M-
USB_EXTA_P
USB_EXTA_N
7 D+
6 D-
U4650
68 14
OUT
OUT
USB3_EXTA_D2R_P
Y+ 1
Y- 2
GND_VOID=TRUE
CRITICAL
PI3USB102EZLE
68 14
BI
68 14
BI
APN: 514-0819
USB3_EXTA_D2R_N
68 14
5%
1/20W
MF
2 201
9
10%
10V
X5R-CERM 2
0201
TQFN
D4621
CRITICAL
2
2
ESD0P2RF-02LS
SEL 10
OE*
GND
SMC_DEBUGPRT_EN_L
TSSLP-2-1
37
1
1
OUTPUT
SMC (M)
USB (D)
3
SEL
L
H
SIGNAL_MODEL=MOJO_MUX_SMSC
IN
D4620
ESD0P2RF-02LS
TSSLP-2-1
8
GND_VOID=TRUE
CRITICAL
B
B
GND_VOID=TRUE
C4620
0.1UF
68 14
IN
USB3_EXTA_R2D_C_N
1
2
68 14
IN
68
USB3_EXTA_R2D_N
C4621
10% 6.3V
CERM-X5R201
0
USB3_EXTA_R2D_C_P
0.1UF
1
2
68
USB3_EXTA_R2D_P
10% 6.3V
CERM-X5R201
0
GND_VOID=TRUE
GND_VOID=TRUE
CRITICAL
D4611
2
2
ESD0P2RF-02LS
ESD0P2RF-02LS
TSSLP-2-1
TSSLP-2-1
1
A
GND_VOID=TRUE
CRITICAL
D4610
1
SYNC_MASTER=J41_MLB
SYNC_DATE=02/07/2013
PAGE TITLE
External A USB3 Connector
DRAWING NUMBER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
46 OF 121
SHEET
35 OF 76
1
A
8
7
6
5
4
3
2
1
PLACE_NEAR=J4800.10:1.5MM
R4830
PP3V3_S4
64 62 58 39 38 36 33 29
0
1
2
5%
1/20W
MF
0201
C4800 1
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.5 mm
IPD Flex Connector
0.1UF
10%
6.3V
CERM-X5R 2
0201
BYPASS=J4800.10:1.5MM
CRITICAL
PLACE_NEAR=J4800.14:1.5MM
518S0884
L4820
D
1
PP5V_S5
62 54 53
F-RT-SM-1
22
2
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V
0402-LF
C4810
1
R4850
0.1UF
15
68
10%
16V
X5R-CERM 2
0201
OUT
TPAD_SPI_MISO
5%
1
1/20W
33
65 64 61 38 37 36
64
MF
50 49 46 40 38 37 35 30 17
65 64 62 61 59
PP3V42_G3H
15
68
TPAD_INTWAKE:SPLIT
PLACE_NEAR=R4844.1:1.5MM
R4841
0
1
(TPAD_WAKE_L)
2
5%
1/20W
MF
0201
TPAD_INTWAKE:SHARED
R4843
SMC_PME_S4_WAKE_L
0
1
(TPAD_SPI_INT_S4_WAKE_L_CONN)
2
5%
1/20W
MF
PLACE_NEAR=R4841.1:1.5MM
0201
IN
15
68
10%
6.3V
CERM-X5R 2
0201
C
2
3
BI
4
5
6
0.1UF
To SMC
1
USB_TPAD_P
USB_TPAD_N
BI
68 64 14
C4820 1
OUT
SMC_LID
TPAD_SPI_MISO_R
201
68 64 14
BYPASS=J4800.19:1.5MM
39 37 29
IN
2
PLACE_NEAR=J4800.2:2.54mm
PLACE_NEAR=J4800.14:1.5MM
D
J4800
TF13BS-20S-0.4SH
FERR-120-OHM-1.5A
IN
TPAD_SPI_CLK
33
R4851
TPAD_SPI_CLK_R
64 TPAD_WAKE_L
PLACE_NEAR=J4800.7:2.54mm
2 33 R4852 64 TPAD_SPI_MOSI_R
TPAD_SPI_MOSI 1
5% 1/20W
MF 201
64 PP3V3_S4_IPD
PLACE_NEAR=J4800.9:2.54mm
1
2 33 R4853 64 TPAD_SPI_CS_R_L
5% 1/20W
MF 201
64 TPAD_SPI_IF_EN_CONN
PLACE_NEAR=J4800.12:2.54mm
64 TPAD_SPI_INT_S4_WAKE_L_CONN
64 PP5V_S4_IPD
64 TPAD_USB_IF_EN_CONN
SMBUS_SMC_3_SDA
73 64 44 40 37 36 BI
SMBUS_SMC_3_SCL
73 64 44 40 37 36 BI
SMC_LSOC_RST_L
64 38 36
OUT
(=PP3V42_G3H_IPD)
SMC_ONOFF_L
64 38 37 36
OUT
5%
1
1/20W
2
MF
64
201
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
C
TPAD_INTWAKE:SHARED
R48441
TPAD_INTWAKE:SHARED
Q4800
1
PP3V3_S3
5%
1/20W
MF
0201 2
DMN32D2LFB4
DFN1006H4-3
G
64 62 58 41 40 36 33 19 18 15
0
SYM_VER_3
D
3
TPAD_SPI_INT_L
2
OUT
S
PLACE_NEAR=J4800.8:1.5MM
15
To PCH
PLACE_NEAR=R4842.2:5MM
TPAD_INTWAKE:SPLIT
R4842
0
1
2
5%
1/20W
MF
0201
PLACE_NEAR=R4843.2:1.5MM
64 62 58 39 38 36 33 29
PP3V3_S4
C4841 1
0.1UF
10%
BYPASS=U4810:3mm 6.3V
CERM-X5R 2
0201
CRITICAL
59 37 36 29 18 13
8 74LVC2G08GT
PM_SLP_S4_L
IN
1
SOT833
A
U4810Y 7
B
15
TPAD_USB_IF_EN
IN
From PCH
2
B
(TPAD_USB_IF_EN_CONN)
B
08
4
NOSTUFF
1
R4810
100K
5%
1/20W
MF
2 201
CKPLUS_WAIVE=UNCONNECTED_PINS
59 37 36 29 18 13
8 74LVC2G08GT
PM_SLP_S4_L
IN
5
SOT833
A
U4810Y 3
15
TPAD_SPI_IF_EN
IN
6
B
(TPAD_SPI_IF_EN_CONN)
08
4
From PCH
CKPLUS_WAIVE=UNCONNECTED_PINS
64 62 58 41 40 36 33 19 18 15
PP3V3_S3
NOSTUFF
1
C4832
100PF
5%
2 25V
NP0-CERM
0201
TPAD_SPI_CS_L
D
G
SYM_VER_3
R4860
100K
5%
1/20W
MF
2 201
TPAD_SPI_CS_CONN_L
3
IN
DMN32D2LFB4
DFN1006H4-3
2
15
Q4860
S
SMBUS_SMC_3_SDA 36 37 40 44 64 73
SMBUS_SMC_3_SCL 36 37 40 44 64 73
SMC_ONOFF_L
36 37 38 64
SMC_LID
36 37 38 61 64 65
SMC_LSOC_RST_L 36 38 64
A
PP3V3_S0
1
1
74 65 64 62
38 30 27 18 17 15 13 12 11 8
61 59 56 45 44 43 42 41 40 39
SYNC_MASTER=J41_MLB
SYNC_DATE=02/12/2013
PAGE TITLE
IPD Connector
NOSTUFF
1
C4833
100PF
5%
25V
2 NP0-CERM
0201
DRAWING NUMBER
1
C4834
100PF
5%
2 25V
NP0-CERM
0201
1
C4835
100PF
5%
2 25V
NP0-CERM
0201
1
C4836
Apple Inc.
100PF
5%
25V
2 NP0-CERM
0201
R
NOTICE OF PROPRIETARY PROPERTY:
BYPASS=J4800.6:1.5MM
BYPASS=J4800.4:1.5MM
BYPASS=J4800.1:1.5MM
BYPASS=J4800.5:1.5mm
BYPASS=J4800.3:8.5MM
8
7
& lt; SCH_NUM & gt;
REVISION
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
6
5
4
3
2
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
48 OF 121
SHEET
36 OF 76
1
SIZE
D
A
8
7
6
5
4
3
2
1
D
D
U5000
LM4FSXAH5BB
69 64 46 14
BI
69 64 46 14
BI
69 64 46 14
BI
69 64 46 14
BI
69 17
IN
69 64 46 14
IN
18
IN
64 46 15
BI
64 46 13
OUT
64 46 13
IN
13
OUT
15
OUT
73 60 40
BI
73 60 40
73 69 64 44 43 40 32 14
BI
73 69 64 44 43 40 32 14
BI
73 65 61 40
BI
73 65 61 40
BI
73 64 44 40 36
C
BI
BI
73 64 44 40 36
BI
64
BI
64
BI
73 64 50 48 40
BI
73 64 50 48 40
BI
45
OUT
45
IN
64
OUT
64
IN
39
OUT
58 42 39
OUT
56
OUT
64
OUT
39
65 61
OUT
IN
64
OUT
39
OUT
38
BI
38
OUT
38
IN
64
IN
39 36 29
B
38 33 25
IN
IN
59 38
OUT
39 38
IN
65 64 61 38 36
39
IN
IN
38
IN
65 61 50 38
IN
18 13
IN
59 18 17 13
IN
59 36 29 18 13
IN
59 13
IN
64 38 36
IN
64 46 38
IN
64 46 38
OUT
30
OUT
39 29
OUT
LPC_AD & lt; 0 & gt;
LPC_AD & lt; 1 & gt;
LPC_AD & lt; 2 & gt;
LPC_AD & lt; 3 & gt;
LPC_CLK24M_SMC
LPC_FRAME_L
SMC_LRESET_L
LPC_SERIRQ
PM_CLKRUN_L
LPC_PWRDWN_L
SMC_RUNTIME_SCI_L
SMC_WAKE_SCI_L
SMBUS_SMC_0_S0_SCL
SMBUS_SMC_0_S0_SDA
SMBUS_SMC_1_S0_SCL
SMBUS_SMC_1_S0_SDA
SMBUS_SMC_2_S3_SCL
SMBUS_SMC_2_S3_SDA
SMBUS_SMC_3_SCL
SMBUS_SMC_3_SDA
NC_SMBUS_SMC_4_ASF_SCL
NC_SMBUS_SMC_4_ASF_SDA
SMBUS_SMC_5_G3_SCL
SMBUS_SMC_5_G3_SDA
B13
A13
C12
D11
H12
D12
C13
H13
G11
F13
F12
B12
(OD)
(OD)
E10
D13
M4
N2
N8
M8
L8
K8
N7
M7
N4
N3
(OD)
(OD)
(OD)
(OD)
(OD)
(OD)
(OD)
(OD)
(OD)
(OD)
(OD)
(OD)
SMC_FAN_0_CTL
SMC_FAN_0_TACH
NC_SMC_FAN_1_CTL
NC_SMC_FAN_1_TACH
SMC_TOPBLK_SWP_L
SMC_SENSOR_PWR_EN
SMC_SYS_KBDLED
NC_SMC_T25_EN_L
TP_SMC_5VSW_PWR_EN
SYS_ONEWIRE
NC_SMC_FAN_5_CTL
SMC_PCH_SUSACK_L
BGA
LPC0AD0
(1 OF 2)
LPC0AD1
LPC0AD2 OMIT_TABLE
LPC0AD3
LPC0CLK
LPC0FRAME*
LPC0RESET*
LPC0SERIRQ
LPC0CLKRUN*
LPC0PD*
LPC0SCI*
PK5
PM6/FAN0PWM0
PM7/FAN0TACH0
PK6/FAN0PWM1
PK7/FAN0TACH1
PN2/FAN0PWM2
D10 PN3/FAN0TACH2
L11
N12
N11
M11
PN4/FAN0PWM3
PN5/FAN0TACH3
PN6/FAN0PWM4
PN7/FAN0TACH4
J4 PH2/FAN0PWM5
J2 PH3/FAN0TACH5
CPU_PECI_R
SMC_PECI_L
E2
E1
F2
F1
B3
A3
B4
A4
B5
A5
B6
A6
C1
C2
B1
B2
G2
G1
H1
H2
B7
A7
B8
A8
SMC_HS_COMPUTING_ISENSE
SMC_PBUS_VSENSE
SMC_BMON_ISENSE
SMC_DCIN_ISENSE
SMC_DCIN_VSENSE
SMC_BMON_DISCRETE_ISENSE
SMC_CPU_ISENSE
SMC_OTHER_HI_ISENSE
SMC_PANEL_ISENSE
SMC_1V2S3_ISENSE
SMC_LCDBKLT_ISENSE
SMC_P3V3S5_ISENSE
SMC_WLAN_ISENSE
SMC_SSD_ISENSE
SMC_P3V3S0_ISENSE
SMC_CAMERA_ISENSE
PP3V3_S0SW_SD
SMC_P1V05S0_VSENSE
SMC_CPUDDR_ISENSE
SMC_P1V05S0_ISENSE
SMC_CPU_VSENSE
SMC_CPUVR_ADJUST_ISENSE
SMC_CPU_IMON_ISENSE
PP3V3_WLAN
C0C0+
C1PC5/C1+
T3CCP1/PJ5/C2T3CCP0/PJ4/C2+
K2
K1
L2
L1
C5
D5
CPU_PROCHOT_L
SMC_VCCIO_CPU_DIV2
SMC_S5_PWRGD_VIN
SSI0CLK/PA2
SSI0FSS/PA3
SSI0RX/PA4
SSI0TX/PA5
M2
M3
L4
N1
SMC_PM_G2_EN
PM_DSW_PWRGD
SMC_DELAYED_PWRGD
SMC_PROCHOT
U1RX/B0
U1TX/PB1
T0CCP0/PB6
T0CCP1/PB7
F11
E11
F4
F3
SMC_DEBUGPRT_RX_L
SMC_DEBUGPRT_TX_L
NC_SMC_SYS_LED
NC_SMC_GFX_THROTTLE_L
SSI1RX/PF0
SSI1TX/PF1
SSI1CLK/PF2
SSI1FSS/PF3
PF4
PF5
M9
N9
L10
K10
L9
K9
I2C0SCL
I2C0SDA
I2C1SCL
I2C1SDA
I2C2SCL
I2C2SDA
I2C3SCL
I2C3SDA
I2C4SCL
I2C4SDA
I2C5SCL
I2C5SDA
H11
L13
C11
A12
G3
(OD)
AIN00
AIN01
AIN02
AIN03
AIN04
AIN05
AIN06
AIN07
AIN08
AIN09
AIN10
AIN11
AIN12
AIN13
AIN14
AIN15
AIN16
AIN17
AIN18
AIN19
AIN20
AIN21
AIN22
AIN23
C4 PECI0RX
C6 PECI0TX
SMC_BIL_BUTTON_L
NC_SMC_DP_HPD_L
SMC_PME_S4_WAKE_L
SMC_PME_S4_DARK_L
SMC_S4_WAKESRC_EN
SMC_SENSOR_ALERT_L
M13
L12
M5
J12
J13
L5
D8
NC
K6
(OD)
SMC_LID
PP0/IRQ116
PP1/IRQ117
PP2/IRQ118
PP3/IRQ119
PP4/IRQ120
PP5/IRQ121
PP6/IRQ122
PP7/IRQ123
SMC_PCH_SUSWARN_L
SMS_INT_L
SMC_BC_ACOK
PM_SLP_S0_L
PM_SLP_S3_L
PM_SLP_S4_L
PM_SLP_S5_L
SMC_ONOFF_L
D4
E4
F5
N5
N6
K5
M6
L6
SMC_RX_L
SMC_TX_L
SMC_PWRFAIL_WARN_L
SMC_WIFI_PWR_EN
E13 USB0DM (PL7)
E12 USB0DP (PL6)
(OD)
SPI_SMC_MISO
SPI_SMC_MOSI
SPI_SMC_CLK
SPI_SMC_CS_L
S5_PWRGD
PM_PCH_SYS_PWROK
39 41
IN
39 42
IN
39 43
IN
39 42
IN
39 41
IN
39 43
IN
39 41
IN
39 41
IN
39 41
IN
39 41
IN
39 41
IN
39 42
IN
39 42
IN
39 43
IN
39 43
IN
29 38 39 41 64
IN
IN
IN
C5003
0.1UF
10%
2 10V
X5R-CERM
0201
C5004
0.1UF
10%
10V
2 X5R-CERM
0201
1
C5005
0.1UF
10%
2 10V
X5R-CERM
0201
1
MIN_LINE_WIDTH=0.25MM
MIN_NECK_WIDTH=0.1MM
VOLTAGE=3.3V
1
R5002
C5006
1M
0.1UF
50 46 38
64
IN
64 38 29
1
C5007
0.1UF
10%
2 10V
X5R-CERM
0201
1
C5008
0.1UF
10%
10V
2 X5R-CERM
0201
1
BI
C5009
0.1UF
10%
2 10V
X5R-CERM
0201
69 38
38
0.1UF
BGA
(2 OF 2)
SWCLK/TCK
SWDIO/TMS
PK4/RTCCLK
SWO/TDO
WAKE*
TDI
HIB*
NC
XOSC0
XOSC1
VDDA
OSC0
OSC1
VREFA+
VREFAVBAT
SMC_RESET_L
G10 RST*
WIFI_EVENT_L (OD)
SMC_WAKE_L
NC_SMC_HIB_L
B11
N13
M12
SMC_CLK32K
NC_SMC_XOSC1
M10
G12
G13
N10
17
K12
OUT
OUT
13
OUT
17 27 38
OUT
D7
E6
E8
E9
F10
J7
J9
J10
38 54 59
38
IN
35 38 68
OUT
35 38 68
OUT
GNDA
OMIT_TABLE
VDD
GND
J1
J6
PP1V2_S5_SMC_VDDC
64
MIN_LINE_WIDTH=0.25MM
MIN_NECK_WIDTH=0.1MM
VOLTAGE=1.2V
K13
D6
46 69
46 69
C10
A10
A11
B10
A2
SMC_TCK
SMC_TMS
SMC_TDO
SMC_TDI
38 46 64
38 46 64
38 46 64
C
38 46 64
NC
D3
PP3V3_S5_AVREF_SMC
D2
D1
38
XW5000
SM
43 42
41
38
GND_SMC_AVSS
C3
E3
2
1
PLACE_NEAR=U5000.A1:4MM
64
BI
C5001
10%
2 10V
X5R-CERM
0201
LM4FSXAH5BB
SMC_EXTAL
SMC_XTAL
IN
1
U5000
5%
1/20W
MF
2 201
10%
10V
2 X5R-CERM
0201
38
VDDC
A1
C7
D9
E5
F9
H5
H9
J5
J8
J11
1
C5020
1
0.01UF
10%
10V
2 X5R-CERM
0201
C5021
1UF
20%
6.3V
0201
2 X5R
46 69
BYPASS=U5000.D2:D1:1MM
BYPASS=U5000.D2:D1:1MM
K11
46 69
54 59
13 16 17
OUT
PLACE_NEAR=U5000.D6:5MM
PLACE_NEAR=U5000.K13:5MM PLACE_NEAR=U5000.J6:5MM
PLACE_NEAR=U5000.J1:5MM
PLACE_NEAR=U5000.D6:5MM PLACE_NEAR=U5000.K13:5MM PLACE_NEAR=U5000.J6:5MM
PLACE_NEAR=U5000.J1:5MM
64
B
35
IN
IN
1
C5010
1.0UF
20%
6.3V
2 X5R
0201-1
16 17 59
OUT
38
OUT
1
C5017
1.0UF
20%
6.3V
2 X5R
0201-1
1
C5015
0.1UF
10%
2 10V
X5R-CERM
0201
1
C5016
0.1UF
1
C5014
1.0UF
10%
10V
2 X5R-CERM
0201
1
C5012
0.1UF
20%
6.3V
2 X5R
0201-1
10%
10V
2 X5R-CERM
0201
1
C5013
1
0.1UF
C5011
0.1UF
10%
10V
2 X5R-CERM
0201
10%
10V
0201
2 X5R-CERM
13 16
OUT
SMC_OOB1_D2R_L
SMC_OOB1_R2D_L
SMC_CPU_DBGPWR_RD_L
NC_BDV_BKL_PWM
20%
6.3V
2 X5R
0201
38
IN
C9
B9
A9
C8
1UF
1
38
IN
T1CCP0/PJ0
T1CCP1/PJ1
T2CCP0/PJ2
T2CCP1/PJ3
C5002
1
6 67
OUT
(OD)
1
38
OUT
PP3V3_S5_SMC_VDDA
0402
6 38 51 67
OUT
PM_PWRBTN_L
PM_SYSRST_L
MEM_EVENT_L
SMC_ADAPTER_EN
2
39 42
IN
1
39 42
IN
L5001
30-OHM-1.7A
15 34 39 65
IN
17 30 35 36 38 40 46 49 50 59
61 62 64 65
39 42
IN
PP3V42_G3H
39 41
IN
IN
J3
H4
H3
G4
PM_BATLOW_L
39 41
IN
OUT
WT3CCP0/PH4
WT3CCP1/PH5
WT4CCP0/PH6
WT4CCP1/PH7
WT5CCP1/PM3 H10
39 42
IN
IN
ALL_SYS_PWRGD
SMC_THRMTRIP
WT2CCP0/PH0 K3
WT2CCP1/PH1 K4
39 41
IN
IN
SMC_DEBUGPRT_EN_L
NC_SMC_GFX_OVERTEMP
WT0CCP0/PG4 K7
WT0CCP1/PG5 L7
L3 U0RX
M1 U0TX
PQ0/IRQ124
PQ1/IRQ125
PQ2/IRQ126
PQ3/IRQ127
PQ4/IRQ128
PQ5/IRQ129
PQ6/IRQ130
PQ7/IRQ131
SPI_DESCRIPTOR_OVERRIDE_L
CPU_CATERR_L
CPU_THRMTRIP_3V3
IN
13 17 64
BI
OUT
38
13 38
IN
30
OUT
30
OUT
43
OUT
64
OUT
13
NOTE:
SMS Interrupt can be active high or low, rename net accordingly.
If SMS interrupt is not used, pull up to SMC rail.
A
NOTE:
Unused pins have " SMC_Pxx " names. Unused
pins designed as outputs can be left floating,
those designated as inputs require pull-ups.
SYNC_MASTER=J41_MLB
SYNC_DATE=02/06/2013
PAGE TITLE
SMC
DRAWING NUMBER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
50 OF 121
SHEET
37 OF 76
1
A
8
7
6
5
4
3
2
1
SMC Reset " Button " , Supervisor & AVREF Supply
R5127
65
49
35
38
61
64
46
30
37
59
62
40
17
36
50
PP3V42_G3H
0
1
67 51 37 6
CPU_PROCHOT_L
BI
PP3V42_G3H_SMC_SPVSR
MIN_LINE_WIDTH=0.4 mm
NOSTUFF MIN_NECK_WIDTH=0.1 mm
2
5%
1/16W
MF-LF
402
1
C5127
6
VOLTAGE=3.42V
C5131
4.7UF
20%
6.3V
2 X5R
402
Desktops: 5V
Mobiles: 3.42V
V+
0.47UF
64 36
IN
R5101
0
1
20%
10V
X5R-CERM 2
0402-1
SILK_PART=SMC_RST
1
R5152
Q5159
DMN5L06VK-7
MR1* and MR2* must both be low to cause manual reset.
Used on mobiles to support SMC reset via keyboard.
NOTE: Internal pull-ups are to VIN, not V+.
S
0.01UF
0
S 2
NOSTUFF
1
R5153
IN
37 38
2
1
R5151
330
5%
1/20W
MF
201
5%
1/20W
MF
2 201
37 38 41 42 43
38 37
CPU_THRMTRIP_3V3
OUT
CRITICAL
R5134
3
Q5158
65 61 50 38 37
SMC_BC_ACOK
SMC_BC_ACOK
MAKE_BASE=TRUE
1
MMBT3904LP-7
37 38 50 61 65
37
R5158
DFN1006-3
2
36 37 38 64
3.3K 2
1
NOSTUFF
1
PM_THRMTRIP_L IN
43
1
CPU_PECI_R
OUT
To SMC
2
CPU_PECI
5%
1/20W
MF
201
C5134
47PF
15 38 67
6
67
BI
From/To CPU/PCH
5%
2 25V
NP0-C0G-CERM
0201
5%
1/20W
MF
201
R5115
0
5%
1/10W
MF-LF
603 2
5%
1/20W
MF
0201
10%
10V
2 X5R-CERM
0201
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.1 mm
VOLTAGE=0V
G
SMC_PECI_L_R
2
1.6K
1
R51161
0
1
G 5
PM_THRMTRIP_R_L
OUT
IN
SMC_PECI_L
From SMC
SMC_THRMTRIP
Debug Power " Buttons "
SMC_ONOFF_L
OMIT
37
SOT-563
37
C5126
GND_SMC_AVSS
PLACE_SIDE=BOTTOM
C
D
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.1 mm
VOLTAGE=3.3V
10UF
10%
10V
X5R-CERM 2
0201
PLACE_SIDE=BOTTOM
3
37 46 50 64
PAD
0.01UF
OMIT
OUT
1
OUT
PP3V3_S5_AVREF_SMC
C5125
D
D 3
PM_THRMTRIP_L
4
C5101 1
5%
1/10W
MF-LF
2 603
67 38 15
SMC_RESET_L
CRITICAL THRM
2
1
REFOUT 8
GND
Q5150
DFN1006H4-3
SYM_VER_2
RESET* 5
4 DELAY
SMC_MANUAL_RST_L
OMIT
37
DMN32D2LFB4
5%
1/20W
MF
2 201
VREF-3.3V-VDET-3.0V
DFN
CRITICAL
IN
100K
6 MR1* (IPU)
SN0903049
7 MR2* (IPU)
SMC_LSOC_RST_L
SMC_ONOFF_L
IN
G 2
R5100
U5110
10%
6.3V
CERM-X5R 2
402
64 38 37 36
S
1
VIN
55 58 59 62 64
6 8 11 15 16
17 27 38 42 51
PP1V05_S0
1
SMC_PROCHOT
C5120 1
SMC12 PECI Support
SOT-563
PLACE_NEAR=Q5159.6:5MM
3
D
GND_SMC_AVSS
PP3V42_G3H
17
59
9
50 49 46 40 38 37 36 35 30
65 64 62 61
Q5159
DMN5L06VK-7
5%
25V
NP0-C0G-CERM 2
0201
1
43 42 41 38 37
D
1
47PF
PLACE_NEAR=Q5150.2:5MM
PLACE_SIDE=TOP
5%
1/10W
MF-LF
2 603
SILK_PART=PWR_BTN
C
SILK_PART=PWR_BTN
50 49 46 40 38 37 36 35 30 17
65 64 62 61 59
SMC Crystal Circuit
74 65 64 62
36 30 27 18 17 15 13 12 11 8
61 59 56 45 44 43 42 41 40 39
SMC USB Clock require these crystal
values:5,6,8,10,12,16,18,20,24,25 MHz
38 37 33 25
R5167
SMC_PME_S4_DARK_L
PP3V42_G3H
PP3V3_S4
64 62 58 39 36 33 29
PP3V3_S0
100K
1
2
5%
1/20W
MF
201
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
5%
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
1/20W
MF
MF
MF
MF
MF
MF
MF
MF
MF
MF
MF
MF
MF
MF
MF
201
201
201
201
201
201
201
201
201
201
201
201
201
201
201
5%
5%
1/20W
1/20W
MF
MF
201
201
5%
5%
5%
1/20W
1/20W
1/20W
MF
MF
MF
201
201
201
5%
1/20W
MF
201
5%
1/20W
MF
201
R5110
2.49K
2
SMC_XTAL
SMC_XTAL_R
CRITICAL
1
1%
1/20W
MF
201
1
10K
10K
100K
10K
100K
20K
20K
10K
10K
10K
10K
10K
100K
100K
10K
MEM_EVENT_L
CPU_THRMTRIP_3V3
R5114
R5117
10KNO STUFF
1
2
100K 1
2
64 46
SMC_ROMBOOT
39 37
Y5110
3.2X2.5MM-SM
SMC_EXTAL
R5170
R5172
R5171
R5173
R5174
R5175
R5176
R5177
R5178
R5179
R5180
R5181
R5187
R5192
R5193
64 38 37 36
65 64 61 37 36
64 46 37
12.000MHZ-30PPM-10PF-85C
37
SMC_ONOFF_L
SMC_SENSOR_ALERT_L
SMC_LID
SMC_TX_L
SMC_RX_L
SMC_DEBUGPRT_TX_L
SMC_DEBUGPRT_RX_L
SMC_TMS
SMC_TDO
SMC_TDI
SMC_TCK
SMC_BIL_BUTTON_L
SMC_BC_ACOK
SMC_S5_PWRGD_VIN
SMS_INT_L
38 37
37
64 46 37
3
68 37 35
2
1
C5110
4
68 37 35
NCNC
1
12PF
C5111
38 37 33 25
SMC_PME_S4_DARK_L
SMC_PME_S4_DARK_L
MAKE_BASE=TRUE
IN
64 46 37
25 33 37 38
12PF
5%
2 25V
NP0-C0G-CERM
0201
64 46 37
5%
2 25V
NP0-C0G-CERM
0201
51 42 38 27 17 16 15 11 8 6
64 62 59 58 55
B
69 13
IN
PM_CLK32K_SUSCLK_R 1
PLACE_NEAR=U0500.AE6:5.1mm
R5112
22
2
64 46 37
PP1V05_S0
64 46 37
1
R5197
SMC_CLK32K
5%
1/20W
MF 201
100K
OUT
37 69
37
SMC_VCCIO_CPU_DIV2
1%
1/20W
MF
2 201
37
65 61 50 38 37
37
37
37
1
R5196
100K
1%
1/20W
MF
2 201
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
B
1
R5188
1K
5%
1/20W
MF
2 201
59 54 37
37 13
38 37
SMC_PM_G2_EN
SMC_ADAPTER_EN
SMC_THRMTRIP
37 27 17
SMC_DELAYED_PWRGD
59 37
SMC_S4_WAKESRC_EN
R5198 100K
R5185 10K
R5186 10K
R5191 100K
R5190 100K
1
2
1
1
2
2
1
2
1
2
PP3V3_WLAN
Module has 3.3K PU
NO STUFF
R5189 10K 1
2
WIFI_EVENT_L
64 41 39 37 29
64 37 29
5%
A
SYNC_MASTER=J41_MLB
1/20W
MF
201
SYNC_DATE=02/06/2013
PAGE TITLE
SMC Shared Support
DRAWING NUMBER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
51 OF 121
SHEET
38 OF 76
1
A
8
7
6
5
4
41 39 37
SMC_HS_COMPUTING_ISENSE SMC_HS_COMPUTING_ISENSE
42 39 37
SMC_PBUS_VSENSE
41 39 37
SMC_BMON_ISENSE
41 39 37
SMC_DCIN_ISENSE
42 39 37
SMC_DCIN_VSENSE
MAKE_BASE=TRUE
SMC_PBUS_VSENSE
3
2
1
37 39 41
37 39 42
MAKE_BASE=TRUE
SMC_BMON_ISENSE
37 39 41
MAKE_BASE=TRUE
SMC_DCIN_ISENSE
37 39 41
MAKE_BASE=TRUE
SMC_DCIN_VSENSE
37 39 42
MAKE_BASE=TRUE
43 39 37
SMC_BMON_DISCRETE_ISENSE
SMC_BMON_DISCRETE_ISENSE
42 39 37
SMC_CPU_ISENSE
37 39 43
MAKE_BASE=TRUE
SMC_CPU_ISENSE
37 39 42
MAKE_BASE=TRUE
41 39 37
SMC_OTHER_HI_ISENSE
43 39 37
D
SMC_PANEL_ISENSE
SMC_OTHER_HI_ISENSE
D
37 39 41
MAKE_BASE=TRUE
SMC_PANEL_ISENSE
37 39 43
MAKE_BASE=TRUE
41 39 37
SMC_1V2S3_ISENSE
41 39 37
SMC_LCDBKLT_ISENSE
42 39 37
SMC_P3V3S5_ISENSE
41 39 37
SMC_WLAN_ISENSE
41 39 37
SMC_SSD_ISENSE
41 39 37
SMC_P3V3S0_ISENSE
SMC_1V2S3_ISENSE
37 39 41
MAKE_BASE=TRUE
SMC_LCDBKLT_ISENSE
37 39 41
MAKE_BASE=TRUE
41 39 37
SMC_P3V3S5_ISENSE
37 39 42
MAKE_BASE=TRUE
SMC_WLAN_ISENSE
37 39 41
MAKE_BASE=TRUE
SMC_SSD_ISENSE
37 39 41
MAKE_BASE=TRUE
SMC_P3V3S0_ISENSE
37 39 41
MAKE_BASE=TRUE
SMC_CAMERA_ISENSE
SMC_CAMERA_ISENSE
37 39 41
MAKE_BASE=TRUE
PP3V3_S0SW_SD
15 34 37
65
OUT
42 39 37
SMC_P1V05S0_VSENSE
42 39 37
SMC_CPUDDR_ISENSE
SD alias on page 103
SMC_P1V05S0_VSENSE
37 39 42
MAKE_BASE=TRUE
SMC_CPUDDR_ISENSE
37 39 42
MAKE_BASE=TRUE
42 39 37
SMC_P1V05S0_ISENSE
42 39 37
SMC_CPU_VSENSE
43 39 37
SMC_CPUVR_ADJUST_ISENSE SMC_CPUVR_ADJUST_ISENSE
43 39 37
SMC_CPU_IMON_ISENSE
64 41 39 38 37 29
SMC_P1V05S0_ISENSE
SMC_CPU_VSENSE
37 39 42
MAKE_BASE=TRUE
MAKE_BASE=TRUE
SMC_CPU_IMON_ISENSE
37 39 43
37 39 43
MAKE_BASE=TRUE
PP3V3_WLAN
PP3V3_WLAN
29 37 38 39 41 64
MAKE_BASE=TRUE
C
58 42 39 37
37 39 42
MAKE_BASE=TRUE
SMC_SENSOR_PWR_EN
SMC_SENSOR_PWR_EN
SMC_WIFI_PWR_EN
C
37 39 42 58
29 37 39
TP_SMC_5VSW_PWR_EN
SMC_SENSOR_PWR_EN
37 39
37 39 42 58
MAKE_BASE=TRUE
39 37 29
SMC_WIFI_PWR_EN
MAKE_BASE=TRUE
39 37
TP_SMC_5VSW_PWR_EN
MAKE_BASE=TRUE
R5230
37
IN
SMC_PCH_SUSWARN_L
0
1
MAKE_BASE=TRUE
2
PCH_SUSWARN_L
OUT
13
IN
13
5%
1/20W
MF
0201
Top-Block Swap
R5231
PP3V3_S0
64 65 74
8 11 12 13 15 17 18 27 30 36 38
40 41 42 43 44 45 56 59 61 62
37
OUT
SMC_PCH_SUSACK_L
0
1
MAKE_BASE=TRUE
1
R5296
1K
5%
1/20W
MF
201 2
37
IN
SMC_TOPBLK_SWP_L
2
PCH_SUSACK_L
5%
1/20W
MF
0201
R5283
1
1K
2
PCH_STRP_TOPBLK_SWP_L
OUT
15
5%
1/20W
MF
201
B
B
R5216
64 62 58 39 38 36 33 29
PP3V3_S4
43
IN
SMC_HS_COMP_ALERT_L
1
R5215
IN
PCH_SML1ALERT_L
100
1
2
5%
1/20W
MF
201
39 37 29
58 42 39 37
SMC_WIFI_PWR_EN
R5295
10K
1
2
NOSTUFF
5%
SMC_SENSOR_PWR_EN
R5294
10K
1
2
1/20W
NOSTUFF
5%
1/20W
MF
MF
43
201
IN
R5213
SMC_BMON_COMP_ALERT_L
201
1
IN
FINSTACKSNS_ALERT_L
100
1
A
IN
R5214
CPUTHMSNS_ALERT_L
1
NOSTUFF
PP3V3_S4
R5211
29 33 36 38 39 58 62 64
44
IN
CPUBMONSNS_ALERT_L
1
1
R5282
37 36 29
39
IN
37 36 29
39
IN
SMC_PME_S4_WAKE_L
SMC_PME_S4_WAKE_L
5%
1/20W
MF
2 201
44
SMC_PME_S4_WAKE_L
MAKE_BASE=TRUE
8
7
100
5%
1/20W
MF
201
100K
OUT
IN
TBTMLBSNS_ALERT_L
2
2
5%
1/20W
MF
201
44
100
5%
1/20W
MF
201
R5210
65 61
2
5%
1/20W
MF
201
NOSTUFF
14
100
100
2
5%
1/20W
MF
201
SYNC_MASTER=J41_MLB
SMC Project Support
DRAWING NUMBER
R5212
1
100
2
Apple Inc.
SMC_SENSOR_ALERT_L
OUT
37 38
6
5
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
R
5%
1/20W
MF
201
29 36 37 39
SYNC_DATE=02/06/2013
PAGE TITLE
2
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
52 OF 121
SHEET
39 OF 76
1
A
8
7
6
5
LYNX POINT LP S0 SMBus " 0 " Connections
4
3
SMC " 0 " SMBus S0 Connections
1K
5%
1/20W
MF
201 2
(MASTER)
D
59 50 49 46 38 37 36 35 30 17 PP3V42_G3H
65 64 62 61
R53001
U0500
1
SMC " 5 " SMBus G3H Connections
74 65 64 62 61
36 30 27 18 17 15 13 12 11 8 PP3V3_S0
59 56 45 44 43 42 41 40 39 38
LYNX POINT LP
2
Pullups are on eDP
connector page and
gated by EDP_PANEL_PWR
1
R5301
LCD BACKLIGHT
1K
5%
1/20W
MF
2 201
SMC
U7701
(Write: 0x58 Read: 0X59)
SMC
J8300
(See Table)
U5000
69
14 16 19
25 40 56
69
14 16 19
25 40 56
73 60 40 37 SMBUS_SMC_0_S0_SDA
SMBUS_SMC_0_S0_SCL
1
R5381
2.0K
Battery Charger
2.0K
5%
1/20W
MF
201 2
(MASTER)
73 60 40 37 SMBUS_SMC_0_S0_SCL
SMBUS_PCH_DATA
R53801
U5000
(MASTER)
SMBUS_PCH_CLK
25 19 16 14 SMBUS_PCH_CLK
69 56 40 MAKE_BASE=TRUE
25 19 16 14 SMBUS_PCH_DATA
69 56 40 MAKE_BASE=TRUE
Internal DP
5%
1/20W
MF
2 201
ISL6259 - U7100
(Write: 0x12 Read: 0x13)
37 40 60
73
SMBUS_SMC_0_S0_SDA
MAKE_BASE=TRUE
50 48 40 37 SMBUS_SMC_5_G3_SCL
73 64 MAKE_BASE=TRUE
SMBUS_SMC_5_G3_SCL
37 40 48
50 64 73
37 40 60
73
MAKE_BASE=TRUE
50 48 40 37 SMBUS_SMC_5_G3_SDA
73 64 MAKE_BASE=TRUE
SMBUS_SMC_5_G3_SDA
37 40 48
50 64 73
VRef DACs
D
Battery
U2200
J6950
Battery
(Write: 0x98 Read: 0x99)
(See Table)
TBT
Battery Manager - (Write: 0x16 Read: 0x17)
69
19 16 14 SMBUS_PCH_CLK
56 40 25
SMBUS_SMC_5_G3_SCL
37 40 48
50 64 73
SMBUS_SMC_5_G3_SDA
37 40 48
50 64 73
U2800
69
19 16 14 SMBUS_PCH_DATA
56 40 25
(Write: 0xFE Read: 0XFF)
SMBUS_PCH_CLK
69
14 16 19
25 40 56
SMBUS_PCH_DATA
69
14 16 19
25 40 56
Margin Control
SMC " 3 " SMBus S0
U2201
Connections
(Write: 0x30 Read: 0x31)
(* = Multiple options)
69
19 16 14 SMBUS_PCH_CLK
56 40 25
69
19 16 14 SMBUS_PCH_DATA
56 40 25
J43
Samsung LGD
Analogix T-con - (Write: 0x7B/0x87 Read: 0x7C/0x88)
N
Y
Parade T-con
- (0x10-0x1F or 0x30-0x3F)
Y
N
DVR
- (Write: 0x4E Read: 0x4F)
Y
Y
Internal DP
Samsung
*
*
Y
J41
LGD
Y
N
Y
74 65 64 62 61
36 30 27 18 17 15 13 12 11 8 PP3V3_S0
59 56 45 44 43 42 41 40 39 38
Trackpad
AUO
*
*
N
SMC
R53901
R5391
2.0K
2.0K
5%
1/20W
MF
201 2
U5000
(MASTER)
J4800
1
5%
1/20W
MF
(Write: 0x90 Read: 0x91)
SMBUS_SMC_3_SCL
36 37 40
44 64 73
2 201
SMBUS_SMC_3_SDA
36 37 40
44 64 73
44 40 37 36 SMBUS_SMC_3_SCL
73 64 MAKE_BASE=TRUE
C
XDP Connectors
C
44 40 37 36 SMBUS_SMC_3_SDA
73 64 MAKE_BASE=TRUE
SMC " 2 " SMBus S3 Connections
J1800
TBT & MLBBOT, TBD Temp
(MASTER)
64 62 58 41 36 33 19 18 15 PP3V3_S3
25 19 16 14 SMBUS_PCH_CLK
69 56 40
EMC1414: U5810
(Write: 0x98 Read: 0x99)
25 19 16 14 SMBUS_PCH_DATA
69 56 40
R53701
SMC
1
R5371
1K
5%
1/20W
MF
201 2
U5000
(MASTER)
SMBUS_SMC_2_S3_SCL
65 61 40 37 SMBUS_SMC_2_S3_SDA
73 MAKE_BASE=TRUE
SMBUS_SMC_2_S3_SDA
36 37 40 44
64 73
SMBUS_SMC_3_SDA
J9500
(Write: 0x92 Read 0x93)
5%
1/20W
MF
2 201
65 61 40 37 SMBUS_SMC_2_S3_SCL
73
MAKE_BASE=TRUE
B
SMBUS_SMC_3_SCL
LIO Finstack Temp
1K
36 37 40 44
64 73
37 40 61
65 73
37 40 61
65 73
B
LYNX POINT LP S0 " SMLink 0 " Connections
74 65 64 62 61
36 30 27 18 17 15 13 12 11 8 PP3V3_S0
59 56 45 44 43 42 41 40 39 38
LYNX POINT LP
U0500
(MASTER)
SMC S0 " 1 " SMBus Connections
R53101
8.2K
5%
1/20W
MF
201 2
1
74 65 64 62 61
36 30 27 18 17 15 13 12 11 8 PP3V3_S0
59 56 45 44 43 42 41 40 39 38
R5311
8.2K
5%
1/20W
MF
2 201
R53601
SMC
2.0K
69 14 SML_PCH_0_CLK
5%
1/20W
MF
201 2
U5000
MAKE_BASE=TRUE
69 14 SML_PCH_0_DATA
(MASTER)
MAKE_BASE=TRUE
1
R5361
2.0K
CPU Temp, Inlet, DDR, BMON THR
5%
1/20W
MF
2 201
EMC1704-02: U5800
(Write: 0x98 Read: 0x99)
73
40 37 32 14 SMBUS_SMC_1_S0_SCL
69 64 44 43 MAKE_BASE=TRUE
SMBUS_SMC_1_S0_SCL
14 32 37 40 43 44 64
69 73
73
40 37 32 14 SMBUS_SMC_1_S0_SDA
69 64 44 43 MAKE_BASE=TRUE
SMBUS_SMC_1_S0_SDA
14 32 37 40 43 44 64
69 73
LYNX POINT LP S0 " SMLink 1 " Connections
Chipset current
PAC1921: U5620
(Write: 0x30 Read: 0x31)
SMBUS_SMC_1_S0_SCL
A
64 69 73
14 32 37
40 43 44
SMBUS_SMC_1_S0_SDA
LYNX POINT LP
64 69 73
14 32 37
40 43 44
U0500
SYNC_MASTER=J41_MLB
(Write: 0x88 Read: 0x89)
SYNC_DATE=02/06/2013
PAGE TITLE
73 69
40 37 32 14 SMBUS_SMC_1_S0_SCL
64 44 43
73
40 37 32 14 SMBUS_SMC_1_S0_SDA
69 64 44 43
SMBus Connections
ALS
J4002
(Write: 0x72 Read 0x73)
SMBUS_SMC_1_S0_SCL
64 69 73
14 32 37
40 43 44
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
access PCH
8
7
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
R
64 69 73
14 32 37
40 43 44
SMBUS_SMC_1_S0_SDA
SMLink 1 is slave port to
DRAWING NUMBER
Apple Inc.
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
53 OF 121
SHEET
40 OF 76
1
A
8
7
6
5
4
3
2
1
IC0R : COMPUTING High Side Current Sense
IM3C :DDR 1V2 Current Sense (LPDDR + CPUDDR)
EDP Current :12A
PP3V3_S0
EDP Current : 7.57A
100X
MAX Vdiff :
PPBUS_S5_HS_COMPUTING_ISNS
CRITICAL
R5450
74
43
ISNS_HS_COMPUTING_N
5 IN-
SC70
OUT
ISNS_HS_COMPUTING_IOUT
43
1
4.53K
CRITICAL
1%
1W
MF
0612
ISNS_HS_COMPUTING_P
74 43
4 IN+
20K
5%
1/20W
MF
201 2
GND
2
PPBUS_G3H
2
1
U5460
SMC_HS_COMPUTING_ISENSE
OUT
1
C5455
74 53
ISNS_1V2_S3_N
IN
5 IN-
0.22UF
74 53
20%
6.3V
GND_SMC_AVSS
ISNS_1V2_S3_P
IN
4 IN+
R5465
4.53K
1
(200V/V)
R5461
20K
5%
1/20W
MF
201 2
GND
0201
37 38 41 42 43
SMC_1V2S3_ISENSE
2
1%
1/20W
MF
201
1
REF 1
2 X5R
Place close to SMC
(For R and C)
PLACE_NEAR=U5000.A5:11mm
ISNS_1V2_IOUT
OUT 6
SC70
DRAM_ISNS:YES
10%
6.3V
CERM-X5R
0201
CRITICAL
CPU_HS_ISNS:YES
PLACEMENT_NOTEs:
2
INA210
37 39
DRAM_ISNS:YES
C5460
0.1UF
V+
PLACE_NEAR=U5000.E2:11mm
1%
1/20W
MF
201
R54511
REF 1
(100V/V)
APN: 107S0137 2 4
56 50
41 27
49 42
64 62
6
PLACE_NEAR=R7450:5mm
DRAM_ISNS:YES
R5455
0201
INA214
R7450 0.002R
42 41
62 58 43
PLACE_NEAR=U5000.E2:11mm
2 6.3V
CERM-X5R
U5450
1 3
0.002
D
10%
200X
SENSE R :
CPU_HS_ISNS:YES
0.1UF
V+
64 62
52 51
55 53
PP3V3_S4SW_SNS
15.14 mV
GAIN :
CPU_HS_ISNS:YES
C5450
3
CPU_HS_ISNS:YES
1
2
GAIN :
74 65 64 62 61
36 30 27 18 17 15 13 12 11 8
59 56 45 44 43 42 41 40 39 38
24 mV
3
MAX Vdiff :
PLACEMENT_NOTEs:
37 39
D
C5465 DRAM_ISNS:YES
0.22UF
2
Place close to SMC
(For R and C)
OUT
PLACE_NEAR=U5000.A5:11mm
1
20%
6.3V
X5R
0201
GND_SMC_AVSS
37 38 41 42 43
IO0R : OTHER High Side Current Sense
EDP Current :10.75A
53.75 mV
50X
IAPC :AirPort Current Sense
PP3V3_S4SW_SNS
OTHER_HS_ISNS:YES
1 C5430
0.1UF
OTHER_HS_ISNS:YES
10%
PLACE_NEAR=R5430:5mm
3
OTHER_HS_ISNS:YES
V+
62 54
64
OUT
PPBUS_S5_HS_OTHER_ISNS
OMIT
R5430 1
3
74
ISNS_HS_OTHER_N
5 IN-
0.003
1%
1w
CYN
0612-SHORT
IN
SC70
1
CRITICAL
74
ISNS_HS_OTHER_P
4 IN+
(50V/V)
20K
2 4
100X
62 58 43 42 41
37 39
OUT
AIRPORT_ISNS:YES
PLACE_NEAR=U5000.A4:11mm
1
64 39 38 37 29
C5433
CRITICAL2
20%
6.3V
2 X5R
PLACEMENT_NOTEs:
AIRPORT_ISNS:YES
C5470
R5470
OTHER_HS_ISNS:YES
4
74
1%
1W
74
MTL
0612 1 3
ISNS_AIRPORT_N
ISNS_P5VWLAN_IOUT
CRITICAL
ISNS_AIRPORT_P
4 IN+
1
R5471
REF 1
(100V/V)
PP3V3_WLAN_R
0.22UF
20K
5%
1/20W
MF
201 2
GND
PLACEMENT_NOTEs:
3
0.1UF
74
ISNS_P3V3_S0_N
INA212
5 IN-
SC70
OUT 6
CRITICAL
74
ISNS_P3V3_S0_P
4 IN+
3
(1000V/V)
OMIT
REF 1
5%
1/20W
MF
201 2
GND
2
PP3V3_S0_FET_R
2
PLACEMENT_NOTEs:
EDP Current : 3.00A
MAX Vdiff :
15 mV
GAIN :
200X
37 39
62 58 43 42 41
37 38 41 42 43
64 62 30
PP3V3_S0SW_SSD
R5480
1%
1W
MF
0612
58
PP3V3_S4SW_SNS
PP3V3_S3RS0_CAMERA
1
PLACE_NEAR=R8061:5mm
U5420
2 4
74
ISNS_CAMERA_N
5 IN-
INA210
SC70
3
4 IN+
(200V/V)
OUT 6
ISNS_SSD_P
4 IN+
(200V/V)
R5481
REF 1
0.22UF
20K
2 4
PLACEMENT_NOTEs:
5%
1/20W
MF
201 2
GND
OMIT_TABLE
PP3V3_S0SW_SSD_FET_R
2
Place close to SMC
(For R and C)
20%
6.3V
X5R
0201
REF 1
1
R5424
37 39
PLACE_NEAR=U5000.C2:11mm
GND_SMC_AVSS
37 38 41 42 43
0
1
2
IBLC : LCD Backlight Driver Input Current Sense
CAM_ISNS:YES
R5425
4.53K
1
2
SMC_CAMERA_ISENSE
1%
CAM_ISNS:YES
1/20W
1
MF
C5425
201
0.22UF
20K
5%
1/20W
MF
201 2
PLACEMENT_NOTEs:
2
Place close to SMC
(For R and C)
R5421
20%
6.3V
X5R
0201
EDP Current : 0.67A
MAX Vdiff :
37 39
0.06 mV
GAIN :
OUT
500X
62 58 43 42 41
PLACE_NEAR=R5490:5mm
GND_SMC_AVSS 37
56 41
38 41 42 43
56 41
2
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=8.6V
MAKE_BASE=TRUE
R5423
0
LCDBKLT_ISNS:YES
PPVIN_S0SW_LCDBKLT
PPVIN_S0SW_LCDBKLT
NOSTUFF
1
PP3V3_S4SW_SNS
PLACE_NEAR=U5000.B2:11mm
5%
1/16W
MF-LF
402
2
56 41
56 41
1
LCDBKLT_ISNS:YES
C5490
0.1UF
V+
0612-SHORT 2 4
MF
1w
0.5%
74
ISNS_LCDBKLT_N
5 IN-
INA211
OUT
SC70
6
ISNS_LCDBKLT_IOUT
CRITICAL
74
ISNS_LCDBKLT_P
3
4 IN+
(500V/V)
PPVIN_S0SW_LCDBKLT_FET
PPVIN_S0SW_LCDBKLT_FET
REF 1
PLACE_NEAR=U5000.A4:11MM
R5491
45.3K
2
SMC_BMON_ISENSE
OUT
37 39
50
IN
CHGR_AMON
1 C5422
3300PF
2
1
2
1%
1/20W
MF
201
PLACE_NEAR=U5000.A4:11MM
Scale: 2.78A / V
10%
10V
X7R-CERM
1
QTY
DESCRIPTION
REFERENCE DES
1
RES,MF,1/20W,100K OHM,5,0201,SMD
C5455
117S0008
1
RES,MF,1/20W,100K OHM,5,0201,SMD
C5465
DRAM_ISNS:NO
117S0008
OUT
CRITICAL
BOM OPTION
1
RES,MF,1/20W,100K OHM,5,0201,SMD
C5475
Place close to SMC
(For R and C)
AIRPORT_ISNS:NO
37 39
CPU_HS_ISNS:NO
PLACE_NEAR=U5000.B3:11MM
C5431
2.2NF
2
ISL6259 Gain: 20x
PART NUMBER
117S0008
SMC_DCIN_ISENSE
Sense R is R7120, 20mOhm
0201
10%
10V
X5R-CERM
0201
2
20%
6.3V
X5R
0201
PLACE_NEAR=U5000.B6:11mm
GND_SMC_AVSS
37 38 41 42 43
37 38 41 42 43
GND_SMC_AVSS
1
RES,MF,1/20W,100K OHM,5,0201,SMD
C5485
SYNC_DATE=03/28/2013
PAGE TITLE
High Side Current Sensing
RES,MF,1/20W,100K OHM,5,0201,SMD
C5495
LCDBKLT_ISNS:NO
1
RES,MF,1/20W,100K OHM,5,0201,SMD
C5433
OTHER_HS_ISNS:NO
1
RES,MF,1/20W,100K OHM,5,0201,SMD
C5425
CAM_ISNS:NO
117S0008
1
RES,MF,1/20W,100K OHM,5,0201,SMD
C5445
3V3S0_ISNS:NO
Apple Inc.
SSD_ISNS:NO
1
117S0008
37 38 41 42 43
117S0008
117S0008
Max VOut: 1.4V at 8.25A
Scale: 2.5A / V
SYNC_MASTER=J41_MLB
DRAWING NUMBER
117S0008
GND_SMC_AVSS
EDP Current: 310A
PLACEMENT_NOTEs:
R
NOTICE OF PROPRIETARY PROPERTY:
QTY
107S0248
1
DESCRIPTION
REFERENCE DES
CRITICAL
RES,SENSE,0.003OHM,1W,4-TERM,1%,0612,TFT
R5480
CRITICAL
7
6
BOM OPTION
5
4
3
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
BRANCH
EDP Current: 3.5A
PART NUMBER
37 39
R5431
300K
1%
1/20W
MF
201
Max VOut: 3.3V at 9.167A
0.22UF
20K
5%
1/20W
MF
201 2
GND
OUT
Replacing caps with 100K PD on ISENSE SMC inputs
PLACE_NEAR=U5000.B3:11MM
R5422
ISL6259 Gain: 36x
1
DC-IN (AMON) Current Sense
CHARGER BMON High Side Current Sense
1
LCDBKLT_ISNS:YES
R5495
4.53K
1
2
SMC_LCDBKLT_ISENSE
1%
LCDBKLT_ISNS:YES
1/20W
1
MF
C5495
201
0201
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=8.6V
MAKE_BASE=TRUE
CHGR_BMON
PLACE_NEAR=U5000.B6:11mm
10%
6.3V
2 CERM-X5R
U5490
0.020
R5490 1
OMIT
5%
1/16W
MF-LF
402
8
OUT
B
ISNS_CAMERA_IOUT
GND
VOLTAGE=3.3V
IN
74
1
PLACE_NEAR=U5000.B2:11mm
CRITICAL
ISNS_CAMERA_P
PP3V3_S3RS0_CAMERA_R
50
1
CRITICAL
3
0612-SHORT
MF
1w
0.5%
0.020
OMIT
A
SSD_ISNS:YES
R5485
4.53K
2
SMC_SSD_ISENSE
1%
SSD_ISNS:YES
1/20W
1
MF
C5485
201
ISNS_P5VSSD_IOUT
6
2
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
MAKE_BASE=TRUE
PP3V3_S3
OUT
SC70
C5420
10%
6.3V
2 CERM-X5R
0201
V+
R5420 1
64
40 36
18 15
33 19
62 58
INA210
5 IN-
PLACE_NEAR=U5000.C2:11mm
0.1UF
3
CAM_ISNS:YES
PP3V3_S3RS0_CAMERA
PP3V3_S0
0.1UF
CAM_ISNS:YES
PP3V3_S3RS0_CAMERA
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
ISNS_SSD_N
0.003
200X
62 58 43 42 41
1 3 74
C5480
10%
6.3V
2 CERM-X5R
0201
U5480
CRITICAL
16.36 mV
1
V+
EDP Current : 0.82A
GAIN :
SSD_ISNS:YES
PLACE_NEAR=R5480:5mm
SSD_ISNS:YES
IS2C : 3.3V Camera Current Sense
MAX Vdiff :
PP3V3_S4SW_SNS
6.3V
X5R
0201
GND_SMC_AVSS
Place close to SMC
(For R and C)
41
15
31
C
37 38 41 42 43
ISDC : SSD Current Sense
PLACE_NEAR=U5000.B1:11mm
3V3S0_ISNS:YES
R5445
4.53K
1
2
ISNS_P3V3_S0_IOUT
SMC_P3V3S0_ISENSE
OUT
1%
3V3S0_ISNS:YES
1/20W
1
1 C5445 PLACE_NEAR=U5000.B1:11mm
MF
R5441
201
0.22UF
20K
20%
3
2 4
0.003
41
15
31
GND_SMC_AVSS
C5440
10%
6.3V
2 CERM-X5R
0201
U5440
R5440 1
58
1
V+
PP3V3_S0
0612-SHORT
CYN
1w
1%
B
PLACE_NEAR=U5000.C1:11mm
20%
6.3V
X5R
0201
3V3S0_ISNS:YES
PLACE_NEAR=R5440:5mm
3V3S0_ISNS:YES
74
45 44 43 42 41 40
17 15 13 12 11 8
39 38 36 30 27 18
65 64 62 61 59 56
41
15
31
37 39
PP3V3_S4SW_SNS
62 58 43 42 41
2
1000X
OUT
3.06 mV
GAIN :
2
Place close to SMC
(For R and C)
EDP Current :1.02A
MAX Vdiff :
AIRPORT_ISNS:YES
R5475
4.53K
1
2
SMC_WLAN_ISENSE
1%
AIRPORT_ISNS:YES
1/20W
1
MF
C5475
201
0201
OUT 6
SC70
PLACE_NEAR=U5000.C1:11mm
10%
6.3V
INA214
5 IN-
APN: 104S0024
29
0.1UF
2 CERM-X5R
U5470
0.025
0201
GND_SMC_AVSS
IR0C : 3.3V S0 FET Current Sense
1
V+
PP3V3_WLAN
Place close to SMC
(For R and C)
C
PP3V3_S4SW_SNS
PLACE_NEAR=R5470:5mm
SMC_OTHER_HI_ISENSE
2
0.22UF
5%
1/20W
MF
201 2
GND
PPBUS_G3H
4.53K
1%
1/20W
MF
201
R54321
REF 1
25 mV
GAIN :
R5433
HS_OTHER_IOUT
OUT 6
MAX Vdiff :
PLACE_NEAR=U5000.A4:11mm
2
56 50
41 27
49 42
64 62
2
U5430
INA213
6.3V
CERM-X5R
0201
EDP Current : 1.00A
3
62 58 43 42 41
2
MAX Vdiff :
GAIN :
& lt; BRANCH & gt;
PAGE
54 OF 121
SHEET
41 OF 76
1
A
8
7
6
5
4
3
2
1
VP0R: PBUS Voltage Sense Enable & Filter
ICS0 : CPU VCore Load Side Current Sense
Q5500
NTUD3169CZ
SOT-963
N-CHANNEL
PBUSVSENS_EN_L
6
D
58
37
39
SMC_SENSOR_PWR_EN
IN
2
PLACE_NEAR=U5540.5:3MM
100K
G
CPUVR_ISNS:YES
1%
1/20W
MF
201 2
S
1
D
1
Max VOut: 3.3V at 19.77V Input
R5540
1
R5503
62 56 50 49 41 27
64
74 52
4.42K
2
CPUVR_ISNS1_P
IN
27.4K
G
1%
1/20W
MF
201 2
S
PPBUS_G3H
4
SMC_PBUS_VSENSE
PLACE_NEAR=U5000.A3:11MM
1%
1/20W
MF
201 2
1
5.49K
PBUSVSENS_EN_L_DIV
37 39
1%
1/16W
MF-LF
402
Sense R is R7310, R7320
Sense R is 0.75mOhm each, combined 0.375mOhm
PLACE_NEAR=R7320.3:5MM
C5504
IN
4.42K2
CPUVR_ISNS2_P
1
U5540
1%
1/16W
MF-LF
402
20%
2 6.3V
X5R
0201
GND_SMC_AVSS
74
R5542
74 52
4.42K2
CPUVR_ISNS1_N
IN
1
74 43
3
1.43K2
CPUVR_ISNS1_N_R
1
74
Enables DC-In VSense
divider when SUS present.
13
59
IN
PM_SLP_SUS_L
6
DCINVSENS_EN_L
G
2
74 52
1%
1/20W
MF
201 2
S
C
1
IN
1
3
1
C5541
GND_SMC_AVSS
37 38 41 42 43
R5547
1
1
1M
2
1%
1/16W
MF-LF
402
CPUVR_ISNS:YES
1%
1/16W
MF-LF
402
Max VOut: 3.3V at 19.77V Input
37 39
OUT
PLACE_NEAR=U5000.B4:11MM
CPUVR_ISNS:YES
4.42K
2
CPUVR_ISNS2_N
100K
2
0.22UF
R5543
R5512
SMC_CPU_ISENSE
CPUVR_ISNS:YES
1%
1/20W
MF
201
20%
6.3V
2 X5R
0201
PLACE_NEAR=R7320.3:5MM
D
-
4.53K
2
1
CPUVR_ISUM_R_N
CPUVR_ISNS:YES
SOT-963
CPUVR_ISUM_IOUT
V-
1%
1/16W
MF-LF
402
NTUD3169CZ
N-CHANNEL
PLACE_NEAR=U5000.B4:11MM
R5548
SC70-5
4
TDP :28.05A
CPUVR_ISNS:YES
OPA333DCKG4
5
+
R5545
1%
1/16W
MF-LF
402
Q5510
1
CPUVR_ISNS:YES
PLACE_NEAR=R7310.3:5MM
VD0R: DC-In Voltage Sense Enable & Filter
CPUVR_ISUM_R_P
V+
CPUVR_ISNS:YES
37 38 41 42 43
EDP: 32A
CPUVR_ISNS:YES
CRITICAL
R5541
74 52
0.22UF
1%
1/20W
MF
201 2
D
Gain:274.72x
1.43K2
1
CPUVR_ISNS:YES
OUT
PLACE_NEAR=U5000.E1:11MM
R55041
100K
CPUVR_ISNS1_P_R
R5544
1%
1/16W
MF-LF
402
PLACE_NEAR=U5000.E1:11MM
RTHEVENIN = 4573 Ohms
P-CHANNEL
R55011
74 43
1
10%
2 6.3V
CERM-X5R
0201
CPUVR_ISNS:YES
PLACE_NEAR=R7310.3:5MM
D
C5540
0.1UF
CPUVR_ISNS:YES
PBUS_S0_VSENSE
3
5
PP3V3_S0
74 65 64 62
36 30 27 18 17 15 13 12 11 8
61 59 56 45 44 43 41 40 39 38
R55021
1
R5546
NO_XNET_CONNECTION=TRUE
1M
C
1%
1/16W
MF-LF
2 402
DCIN_S5_VSENSE
D
R5513 1
27.4K
G
5
1%
1/20W
MF
201
S
4
PLACE_NEAR=U5000.B3:11MM
2
RTHEVENIN = 4573 Ohms
P-CHANNEL
PPDCIN_G3H_ISOL
SMC_DCIN_VSENSE
OUT
IM0C : CPU DDR Current Sense
37 39
PLACE_NEAR=U5000.F1:11MM
1%
1/20W
MF
201
PDCINVSENS_EN_L_DIV
2
2
C5514
MAX Vdiff :
12.60 mV
0.22UF
1
5.49K
1%
1/20W
MF
201 2
EDP Current : 3.00A
GAIN :
200X
20%
6.3V
X5R
0201
62 58 43 42 41
42 10 8
GND_SMC_AVSS
64
10 8
62 52
PPVCC_S0_CPU
1
42 10 8
4.53K
2
1%
1/20W
MF
201
PLACE_NEAR=R7310.2:5 MM
PLACE_NEAR=U5000.B7:11MM
B
0612-SHORT
CYN
1w
1%
37 39
R5570 1
C5520
20%
2 6.3V
X5R
0201
XW5530
SM
PP1V05_S0
1
2
70 62 53 23 22 21 20 19 17
4.53K
2
1%
1/20W
MF
201
PLACE_NEAR=R7640.2:5 MM
PLACE_NEAR=U5000.G1:11MM
4
IN+
3
MAX Vdiff :
62 58 43 42 41
34 29 28 18 17 16 15 13 11 8
74 64 62 60 59 58 57
P3V3S5_ISNS:YES
PP3V3_S5
V+
74 55
IN
ISNS_1V05_S0_N
10%
6.3V
2 CERM-X5R
0201
U5560
PLACE_NEAR=R7640.4:5MM
5 IN-
INA211
SC70
OUT 6
P1V05S0_IOUT
CRITICAL
74 55
IN
ISNS_1V05_S0_P
REF 1
(500V/V)
GND
2
PLACE_NEAR=R7640.3:5MM
4 IN+
R55621
20K
5%
1/20W
MF
201 2
PLACE_NEAR=U5000.H1:11mm
37 38 41 42 43
B
R5590 1
3 74
ISNS_P3V3S5_N
5 IN-
54 42
74
ISNS_P3V3S5_P
4 IN+
PP3V3_S5_REG_R
(100V/V)
P1V05_ISNS:YES
54 42
4.53K
2
1%
1/20W
MF
201
SMC_P1V05S0_ISENSE
P1V05_ISNS:YES
1
0201
OUT
6
REF 1
ISNS_P3V3S5_IOUT
OUT
1
R5591
P3V3S5_ISNS:YES
R5595
4.53K
2
SMC_P3V3S5_ISENSE
OUT
1%
P3V3S5_ISNS:YES
1/20W
1 C5595
MF
201
PLACE_NEAR=U5000.A6:11mm
1
20%
5%
1/20W
MF
201 2
GND
PP3V3_S5_REG_R
37 39
0.22UF
20K
2 4
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=3.3V
MAKE_BASE=TRUE
R5561
PLACE_NEAR=U5000.A6:11mm
10%
CRITICAL
PLACE_NEAR=U5000.H2:11MM
1
0.1UF
INA214
SC70
P3V3S5_ISNS:YES
C5590
2
3
0.1UF
20%
6.3V
X5R
0201
GND_SMC_AVSS
6.3V
2 CERM-X5R
U5590
OMIT
P1V05_ISNS:YES
1
V+
PP3V3_S4SW_SNS
C5560
2
37 39
Place close to SMC
(For R and C)
PLACE_NEAR=R5590:5mm
37 38 41 42 43
1%
1w
CYN
0612-SHORT
P1V05_ISNS:YES
0.22UF
20K
5%
1/20W
MF
201 2
OUT
PP3V3_S4SW_SNS
20%
2 6.3V
X5R
0201
1
R5571
CPUDDR_ISNS:YES
R5575
4.53K
2
SMC_CPUDDR_ISENSE
1%
CPUDDR_ISNS:YES
1/20W
1 C5575
MF
201
1
100X
0.22UF
PLACE_NEAR=R7640:5mm
1
1
GND
0.003
62 58 43 42 41
REF
(200V/V)
ISNS_CPUDDR_IOUT
6
30.00 mV
GAIN :
C5530
5.65 mV
500X
OUT
37 39
EDP Current : 1A
A
ISNS_CPUDDR_P
SC70
PP1V2_S3
IC1C: 1.05V S0 CURRENT SENSE / FILTER
GAIN :
74
IN-
EDP Current : 3.00A
OUT
PLACE_NEAR=U5000.G1:11MM
GND_SMC_AVSS
MAX Vdiff :
0201
IR5C :3.3 S5 REG Current Sense
SMC_P1V05S0_VSENSE
1
5
PLACE_NEAR=U5000.H1:11mm
10%
PLACEMENT_NOTEs:
R5530
1
P1V05VSENSE_IN
0.1UF
37 38 41 42 43
1.05V Voltage Sense / Filter
62
27
6
15
55
ISNS_CPUDDR_N
CPUDDR_ISNS:YES
C5570
6.3V
2 CERM-X5R
INA210
74
OMIT
0.22UF
GND_SMC_AVSS
64
51 38
11 8
17 16
59 58
2 4
0.003
PLACE_NEAR=U5000.B7:11MM
1
1
V+
U5570
SMC_CPU_VSENSEOUT
1
CPUDDR_ISNS:YES
PPVMEMIO_S0_CPU
R5520
CPUVSENSE_IN
2
PLACE_NEAR=R5570:5mm
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.1 MM
VOLTAGE=1.2V
MAKE_BASE=TRUE
37 38 41 42 43
CPU Vcore Voltage Sense / Filter
XW5520
SM
PP3V3_S4SW_SNS
PPVMEMIO_S0_CPU
3
R5514
100K
PLACE_NEAR=U5000.B3:11MM
1
2
R5511 1
3
62
49
50
64
2 6.3V
X5R
0201
GND_SMC_AVSS
37 38 41 42 43
PLACEMENT_NOTEs:
Place close to SMC
(For R and C)
37 39
C5561
0.22UF
20%
2 6.3V
X5R
0201
SYNC_MASTER=J41_MLB
PLACE_NEAR=U5000.H2:11MM
GND_SMC_AVSS
SYNC_DATE=03/28/2013
Replacing caps with 100K PD on ISENSE SMC inputs
37 38 41 42 43
CRITICAL
DRAWING NUMBER
PART NUMBER
QTY
DESCRIPTION
REFERENCE DES
117S0008
1
RES,MF,1/20W,100K OHM,5,0201,SMD
C5541
117S0008
1
RES,MF,1/20W,100K OHM,5,0201,SMD
C5561
P1V05_ISNS:NO
117S0008
1
RES,MF,1/20W,100K OHM,5,0201,SMD
C5595
P3V3S5_ISNS:NO
117S0008
1
RES,MF,1/20W,100K OHM,5,0201,SMD
C5575
CPUDDR_ISNS:NO
Apple Inc.
BOM OPTION
7
6
5
4
CPUVR_ISNS:NO
3
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
R
8
A
PAGE TITLE
Voltage & Load Side Current Sensing
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
55 OF 121
SHEET
42 OF 76
1
8
7
6
5
4
3
2
1
Sense Pins gain stage for U5800 (EMC1704)
ICS3 : Adjustable Gain CPU VR Current
R5620
PP3V3_S4SW_SNS
58 43 42 41
62
1
100
1
74 65 64 62 61
36 30 27 18 17 15 13 12 11 8
59 56 45 44 43 42 41 40 39 38
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
VOLTAGE=3.3V
C5620
1.0UF
R5666
R5660
PP3V3_SNS_CPUVR_ADJUST_ISNS
2
1%
1/16W
MF-LF
402
PP3V3_S0
0
1
5%
1/20W
MF
0201
20%
6.3V
2 X5R
0201-1
10%
6.3V
CERM-X5R
0201
2
PU: SMBus mode
74
41
43
0
PAC1921-1-AIA
74 42
74 42
2 SENSE+
3 SENSE-
CPUVR_ISNS1_P_R
CPUVR_ISNS1_N_R
IN
IN
PLACE_NEAR=U5000.A7:5MM
OUT 4
READ*/INT
SM_CLK/INT_SEL
SM_DATA/OUT_SEL
COMM_SEL
PLACE_NEAR=U5540.1:5MM
8
10
9
7
SMC_CPU_DBGPWR_RD_L
SMBUS_SMC_1_S0_SCL
SMBUS_SMC_1_S0_SDA
PLACE_NEAR=R7150:5MM
R5625
0 2 SMC_CPUVR_ADJUST_ISENSE
IN
1
5%
1/20W
MF
0201
37
OUT
U5660
C5625
20%
14 32 37
40 44 64 69 73
BI
14 32 37 40 44 64 69 73
CKPLUS_WAIVE=NdifPr_badTerm
INA211
5 INISNS_HS_COMPUTING_P
SC70
OUT 6
IN
CKPLUS_WAIVE=NdifPr_badTerm
CRITICAL
4 IN+
ISNS_HS_COMPUTING_N
REF 1
IN
(500V/V)
74 43 41
2 6.3V
X5R
0201
NO STUFF
74 43 41
EPAD
5
PLACE_NEAR=U5000.A7:5MM
GND
27K
37 39
0.22UF
BI
OUT
44 74
2
5%
1/20W
MF
0201
2 ISNS_HS_GAIN_N
D
R5665
ISNS_HS_GAIN_OUT
11
37 38 41 42 43
0
1
R5663
20K
5%
1/20W
MF
201 2
GAIN: 500X
ISNS_HS_GAIN_OUT_R
NO STUFF
2
5%
1/20W
MF
0201
1
GND
GND_SMC_AVSS
NO STUFF
R56611
V+
1
SMC_CPUVR_ADJUST_ISENSE_R
3
DFN
6 ADDR_SEL/GAIN_SEL
0
1
5%
1/20W
MF
0201
U5620
2
44 74
R5667
R5668
ISNS_HS_GAIN_N_R1
OUT
NO STUFF
ISNS_HS_COMPUTING_P
IN
VDD
2
5%
1/20W
MF
201
BYPASS=U5620.1:5:3MM
1
R5621
4.3K
1%
1/20W
MF
201 2
0.1UF
CPUVRSNS_ADDR_SEL
D
1K
C5660
ISNS_HS_GAIN_P
2
5%
1/20W
MF
0201
R56621
PLACE_NEAR=U5660.3:5MM
1
R5821: ADDR - 0x56/0x57 (r/w)
1
0
ISNS_HS_GAIN_P_R 1
2
1
1%
1/20W
MF
201 2
R5669
74
41
43
0
ISNS_HS_COMPUTING_N 1
IN
2
5%
1/20W
MF
0201
C5665
0.22UF
2
20%
6.3V
X5R
0201
ILDC :LCD Panel Current Sense / Filter
62 58 43 42 41
PP3V3_S0SW_LCD
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
MAKE_BASE=TRUE
60 43
PANEL_ISNS:YES
PLACE_NEAR=R5470:5mm
PANEL_ISNS:YES
0.1UF
V+
PP3V3_S0SW_LCD
OMIT
R5670 1
0.020
0.5%
1w
MF
0612-SHORT
3
74
ISNS_PANEL_N
INA210
5 IN-
SC70
OUT
60 43
PANEL_ISNS:YES
R5675
4.53K
1
2
SMC_PANEL_ISENSE
1%
PANEL_ISNS:YES
1/20W
1 C5675
MF
201
ISNS_PANEL_IOUT
6
CRITICAL
74
ISNS_PANEL_P
4 IN+
(200V/V)
1
R5671
REF 1
5%
1/20W
MF
201 2
2
PP3V3_S0SW_LCD_R
PP3V3_S0SW_LCD_R
EDP Current: 0.750 A
Max Vdiff:
15 mV
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
MAKE_BASE=TRUE
OUT
C
37 39
VR IMON Current Sense Filter
0.22UF
20K
2 4
GND
60 43
PLACE_NEAR=U5000.C1:11mm
10%
6.3V
2 CERM-X5R
0201
U5670
C
C5670
1
3
60 43
With 100mA battery current, Will have 10.2mV difference
going into sense pins of U5800.
This will set the minumum current threshold at 0.100mA
In battery discharge scenario negative voltage will be
present on IN+/- pins with INA output voltage decreasing
from 3.3V with increasing discharge current.
PP3V3_S4SW_SNS
Gain: 200x
Scale:
0.25A / V
MAX VOUT: 3V AT 0.825A
PLACEMENT_NOTEs:
20%
6.3V
X5R
0201
2
PLACE_NEAR=U5000.C1:11mm
PLACE_NEAR=U5000.B8:5MM
GND_SMC_AVSS
R5641
37 38 41 42 43
51
CPUVR_IMON
IN
0
1
Place close to SMC
(For R and C)
SMC_CPU_IMON_ISENSE
2
5%
1/20W
MF
0201
1
62
45
41
36
17
11
13
27
39
43
59
65
74
61
44
40
30
15
8
12
18
38
42
56
64
0.22UF
1
2
BMON : Discrete BMON Current Sense / Filter
BYPASS=U5601:3MM
C5613
20%
6.3V
X5R
0201
0.1UF
10%
2 6.3V
CERM-X5R
HS_COMP_FB
1
R5614
R5616
294K
B
3
1%
1/16W
MF-LF
402
HS_COMP_VREF
NO STUFF
74 65 64 62 61
36 30 27 18 17 15 13 12 11 8
59 56 45 44 43 42 41 40 39 38
5
255K 2
0.22UF
PP3V3_S0
1
10%
6.3V
0201
SMC_HS_COMP_ALERT_L
4
U5612
1
OUT
R5604
39
DFN1006H4-3
BMON_COMP_VREF
NOSTUFF
1
1
C5610
1
R5610
0
10%
25V
2 X5R
402
DFN1006H4-3
SYM_VER_2
1%
1/16W
MF-LF
402
1
G
S 2
BMON_COMP_OUT
1
4
100K
1%
1/16W
MF-LF
2 402
BMON_IOUT_R
1
NOSTUFF
C5600
0.1UF
NOSTUFF
HS_IOUT_D
NOSTUFF
1
1
R5607
R5600
0
BYPASS=U5600:3MM
C5606 1
K
10%
25V
2 X5R
402
0
5%
1/20W
MF
2 0201
A
RB521ZS-30
5%
1/20W
MF
2 0201
BMON_IOUT_D
NOSTUFF
0.1UF
10%
6.3V
CERM-X5R 2
0201
D5607
SM-201
A
RB521ZS-30
IN
K
ISNS_HS_COMPUTING_IOUT
CHGR_CSO_R_P/N are swapped on purpose
to measure power into the system
CKPLUS_WAIVE=NdifPr_badTerm
73 50
IN
CHGR_CSO_R_P
IN
CHGR_CSO_R_N
5 IN-
Debug Sensors 1
U5600
PLACE_NEAR=U5000.A3:5MM
INA213
SC70
4 IN+
OUT
6
REF 1
(50V/V)
CKPLUS_WAIVE=NdifPr_badTerm
Replacing caps with 100K PD on ISENSE SMC inputs
PART NUMBER
117S0008
8
QTY
1
DESCRIPTION
REFERENCE DES
RES,MF,1/20W,100K OHM,5,0201,SMD
C5675
7
CRITICAL
BMON_IOUT
R56011
20K
5%
1/20W
MF
201 2
GND
BOM OPTION
5
4
DRAWING NUMBER
R5608
Apple Inc.
4.53K
1
2
1%
1/20W
MF
201
SMC_BMON_DISCRETE_ISENSE
PLACE_NEAR=U5000.A3:5MM
1
C5602
0.22UF
20%
2 6.3V
X5R
0201
GND_SMC_AVSS
PANEL_ISNS:NO
6
SYNC_DATE=03/28/2013
PAGE TITLE
V+
CRITICAL
73 50
SYNC_MASTER=J41_MLB
3
41
2
A
B
DMN32D2LFB4
R5605
5%
1/20W
MF
2 0201
D5617
SM-201
MCP6541T
SC70-5
U5602
200K 2
39
1
0
5%
1/20W
MF
2 0201
5
1
OUT
D 3
2
S 2
Gain: 50x
Scale: 2A / V
Max VOut: 3.3V at 6.6A
0.1UF
NOSTUFF
R5617
G
3
1%
1/16W
MF-LF
402
SYM_VER_2
HS_IOUT_R
U5601
10.2K2
1
1%
1/16W
MF-LF
2 402
DMN32D2LFB4
49.9K
R5606
100K
D 3
SMC_BMON_COMP_ALERT_L
R5609
BMON_COMP_FB
1
R5615
1
20%
6.3V
X5R
0201
0.1UF
2
1%
1/16W
MF-LF
2 402
C5603
2 CERM-X5R
MCP6541T
SC70-5 HS_COMP_OUT
1
2
BYPASS=U5601:3MM
1
1%
1/16W
MF-LF
402
U5611
10.2K2
1
1%
1/16W
MF-LF
2 402
1
Hysteresis TBD based on RC value changes
C5601
R5619
0201
37 38 41 42 43
Vref = 0.406mV
Vth = 0.442 = 1A from Battery
Vtl = 0.290mv = 0.687A from battery
C5611
1
10%
10V
X5R-CERM
0201
GND_SMC_AVSS
NO STUFF
PP3V3_S0
C5641
2.2NF
2
Discrete High side Current threshold
37 39
OUT
NO STUFF
PLACE_NEAR=U5000.B8:5MM
3
43
41
37
38
42
OUT
37 39
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
56 OF 121
SHEET
43 OF 76
1
A
8
7
6
5
4
3
2
1
CPU Proximity, Inlet ,DDR and BMON THR Sensor
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.25 mm
R5800
74 65 64 62 61
36 30 27 18 17 15 13 12 11 8
59 56 45 44 43 42 41 40 39 38
PP3V3_S0
47
1
PP3V3_S0_CPUTHMSNS_R
2
1
5%
1/20W
MF
201
C5800
0.1UF
10%
6.3V
2 CERM-X5R
0201
D
3
Placement note:
1
1
NO_XNET_CONNECTION=TRUE
C5830
PLACE_NEAR=U5800.2:5mm
5%
2 25V
NP0-C0G-CERM
0201
DFN1006H4-3
2
10%
10V
X7R-CERM
0201
PLACE_NEAR=U5800.3:5mm
R5806
100K
CRITICAL
100K
5%
1/20W
MF
2 201
VDD
2200PF
47PF
BC846BLP
C5801
1
U5800
D
1
R5802
PLACE_NEAR=Q5830:3MM
Q5830
Place Q5810 next to DDR/5V/3.3V supply on TOP side
NOSTUFF
1
INLET_THMSNS_D1_P
1
74
5%
1/20W
MF
2 201
EMC1704-2
2
QFN
C5860 1
47PF
5%
25V
2 NP0-C0G-CERM
0201
BC846BLP
Place Q5830 between near rear vent on bottom side
C5811
47PF
1
DFN1006H4-3
2
NO_XNET_CONNECTION=TRUE
Q5860
1
C5802
39
OUT
39
4
DP2/DN3
SMDATA 11
SMBUS_SMC_1_S0_SDA
BI
14 32 37 40 43 64 69 73
5
CPUTHMSNS_D2_P
DN2/DP3
SMCLK 12
SMBUS_SMC_1_S0_SCL
BI
14 32 37 40 43 64 69 73
PLACE_NEAR=U5800.4:5mm
10%
10V
X7R-CERM
0201
BC846BLP
16
15
PLACE_NEAR=U5800.5:5mm
74
CPUTHMSNS_D2_N
74 43
OUT
ISNS_HS_GAIN_P
74 43
OUT
SENSE+
SENSE-
13
14
2
3
PLACE_NEAR=Q5860:3MM
OUT
CPUTHMSNS_ALERT_L
2200PF
DFN1006H4-3
5%
25V
NP0-C0G-CERM 2
0201
1
CPUBMONSNS_ALERT_L
ALERT* 10
DUR_SEL
TH_SEL
ISNS_HS_GAIN_N
Detect DDR/5V/3.3V Proximity Temperature
ADDR_SEL 6
GPIO 7
R5803
10K
GND
5%
1/20W
MF
201
THRM_PAD
NOSTUFF1
10K
5%
1/20W
MF
201
R5805
0
Placement note:
Write Address: 0x98
Read Address: 0x99
R5804
2
1
NC
Place U5800 under CPU
17
CPUTHMSNS_DUR_SEL
CPUTHMSNS_TH_SEL
NOSTUFF 1
CPUTHMSNS_ADDR_SEL
5%
1/20W
MF
2 0201
8
1
Q5810
Placement note:
2
THERM* 9
DN1
INLET_THMSNS_D1_N
74
PLACE_NEAR=Q5810:3MM
3
DP1
3
74
2
2
C
C
TBT,MLB Bottom Proximity Sensors
B
B
R5840
74
3
TBTTHMSNS_D2_R_P
1
Q5820
1
2
TBT_MLBBOT_THMSNS_P
TBT, MLBBOT and TBD Temp Sensor
44 74
5%
1/20W
MF
0201
PLACE_NEAR=Q5820:3MM
1
0
C5820
R5810
47PF
BC846BLP
5%
25V
2 NP0-C0G-CERM
0201
DFN1006H4-3
2
R5841
TBTTHMSNS_D2_R_N
74
74 65 64 62 61
36 30 27 18 17 15 13 12 11 8
59 56 45 44 43 42 41 40 39 38
1
0
2
TBT_MLBBOT_THMSNS_N
44 74
44 74
Q5840
1
2
C5813
10%
6.3V
CERM-X5R
0201
R58111
3 DN1
THERM*/ADDR
CRITICAL
22K
5%
1/20W
MF
201 2
7 TBT_INLET_THM_L
TBDTHMSNS_D2_N
8
TBTMLBSNS_ALERT_L
4 DP2/DN3
2
ALERT*
SMDATA
9
SMBUS_SMC_3_SDA
BI
36 37 40 64 73
5 DN2/DP3
C5840
10%
10V
X7R-CERM
0201
TBT_MLBBOT_THMSNS_P
2 DP1
1
2200PF
BI
C5810
0.1UF
2
MSOP
NO_XNET_CONNECTION=TRUE
74 44
1
1
VDD
BI
Place Q5820 close to TBT on TOP side
5%
25V
2 NP0-C0G-CERM
0201
DFN1006H4-3
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
VOLTAGE=3.3V
U5810
47PF
BC846BLP
PP3V3_S0_TBTMLB_ISNS_R
2
EMC1414-1-AIZL
Placement note:
PLACE_NEAR=Q5840:3MM
1
47
TBDTHMSNS_D2_P
74 44
3
1
5%
1/20W
MF
201
5%
1/20W
MF
0201
TBT_MLBBOT_THMSNS_N
PP3V3_S0
SMCLK
10
SMBUS_SMC_3_SCL
BI
36 37 40 64 73
OUT
39
GND
6
44 74
Placement note:
Place Q5840 on MLB bottom side opposite U5810
74 44
TBDTHMSNS_D2_P
TBT_MLBBOT_THMSNS_P
PLACE_NEAR=Q5850:3MM
1
BC846BLP
C5850
TBD
5%
25V
2 NP0-C0G-CERM
0201
DFN1006H4-3
2
C5812
Placement note:
47PF
1
Q5850
BI
NO_XNET_CONNECTION=TRUE
3
A
44 74
PLACE_NEAR=U5810.4:5mm
PLACE_NEAR=U5810.5:5mm
TBDTHMSNS_D2_N
74 44
44 74
BI
1
2200PF
10%
10V
X7R-CERM
0201
SYNC_MASTER=J41_MLB
2
SYNC_DATE=02/06/2013
PAGE TITLE
Thermal Sensors
Write Address: 0x39
Read Address: 0x38
TBT_MLBBOT_THMSNS_N
DRAWING NUMBER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
74 44
74 44
TBT_MLBBOT_THMSNS_P
TBT_MLBBOT_THMSNS_N
74
44
74
44
TBT_MLBBOT_THMSNS_P
TBT_MLBBOT_THMSNS_P
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
44 74
TBT_MLBBOT_THMSNS_N
44 74
MAKE_BASE=TRUE
TBT_MLBBOT_THMSNS_N
MAKE_BASE=TRUE
8
7
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
58 OF 121
SHEET
44 OF 76
1
A
8
7
6
5
4
3
2
1
FAN CONNECTOR
D
R6010
1
0
PP3V3_S0
2
64 65 74
8 11 12 13 15 17 18 27 30 36 38
39 40 41 42 43 44 56 59 61 62
NOSTUFF
5%
1/20W
MF
0201
1
C6010
0.1UF
10%
6.3V BYPASS=U6010:3mm
0201
NOSTUFF
CRITICAL
2 CERM-X5R
74LVC1G08 6
SOT891
PP3V3_S0_FAN
4
MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.1 MM
VOLTAGE=3.3V
C
D
2
U6010
08
1
PP5V_S0
16 17 32 46 51 52 56 58 59 61
62 64
NC
3
C
5
NC
518S0793
CRITICAL
R6060
J6000
1
FF14A-4C-R11DL-B-3H
47K
5%
1/20W
MF
201 2
R6065
37
OUT
SMC_FAN_0_TACH
1
47K
2
64
NC
1
2
3
4
FAN_RT_TACH
5%
1/20W
MF
201
NC
37
B
IN
1
G
2
2
SMC_FAN_0_CTL
6
Q6060
S
5%
1/20W
MF
201
5V DC
TACH
MOTOR CONTROL
GND
1
100K
DMN32D2LFB4
DFN1006H4-3
SYM_VER_3
3 D
R6061
F-RT-SM
5
64
FAN_RT_PWM
B
A
SYNC_MASTER=J41_MLB
SYNC_DATE=02/06/2013
PAGE TITLE
Fan
DRAWING NUMBER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
60 OF 121
SHEET
45 OF 76
1
A
8
7
6
5
4
3
2
1
DUAL I/O MODE (MODE 0 & 3) SUPPORTED
High Speed CLK Frequency - 50MHz for fast read dual I/O
PP3V3_SUS
1
R6102
100K
5%
1/20W
MF
2 201
D
BYPASS=U6100:3mm
1
1
R6101
3.3K
8
59 58 57 18 14 11 8
64 62
C6100
5%
1/20W
MF
2 201
CRITICAL
VDD
0.1UF
U6100
10%
16V
X5R-CERM 2
0201
64MBIT
D
WSON
69 46
SPI_MLB_CLK
6
SCK
1
3
7
CE*
WP*
RST*/HOLD*
SI/SIO0
5
SPI_MLB_MOSI
46 69
2
SPI_MLB_MISO
46 69
LPC+SPI Connector
SST25VF064C
64 46 15
IN
OMIT_TABLE
SO/SOI1
LPCPLUS
CRITICAL
J6100
VSS THRM_PAD
4
NOTE: If HOLD* is asserted
ROM will ignore SPI cycles.
DF40C-30DP-0.4V
9
SPI_MLB_CS_L
SPI_WP_L
SPIROM_USE_MLB
69 46
59 50 49 40 38 37 36 35 30 17
65 64 62 61
61 59 58 56 52 51 45 32 17 16
64 62
M-ST-SM
31
32
PP3V42_G3H
PP5V_S0
IN
BI
69 64 37 14
BI
69 64 37 14
BI
69 64 37 14
BI
64 46
IN
64 16 15
BI
69 64 18
IN
64 38 37
OUT
64
64
64 38 37
IN
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
33
69 64 17
69 64 37 14
34
LPC_CLK24M_LPCPLUS
LPC_AD & lt; 0 & gt;
LPC_AD & lt; 2 & gt;
LPC_AD & lt; 1 & gt;
LPC_AD & lt; 3 & gt;
SPI_ALT_MOSI
XDP_LPCPLUS_GPIO
LPCPLUS_RESET_L
SMC_TDO
TP_SMC_TRST_L
TP_SMC_MD1
SMC_TX_L
C
SPI_ALT_MISO
LPC_FRAME_L
SPIROM_USE_MLB
OUT
IN
BI
PM_CLKRUN_L
SPI_ALT_CLK
SPI_ALT_CS_L
LPC_SERIRQ
LPC_PWRDWN_L
SMC_TDI
SMC_TCK
SMC_RESET_L
SMC_ROMBOOT
SMC_RX_L
SMC_TMS
OUT
46 64
14 37 64 69
15 46 64
13 37 64
IN
46 64
IN
46 64
BI
15 37 64
IN
13 37 64
OUT
37 38 64
OUT
37 38 64
OUT
37 38 50 64
OUT
38 64
OUT
37 38 64
OUT
37 38 64
C
516S1039
SPI Bus Series Termination
SPI_ALT_MISO
PLACE_NEAR=J6100.2:5mm
SPI_ALT_MOSI
PLACE_NEAR=J6100.15:5mm
SPI_ALT_CLK
PLACE_NEAR=J6100.12:5mm
SPI_ALT_CS_L
PLACE_NEAR=J6100.14:5mm
LPCPLUS
LPCPLUS
1
LPCPLUS
1
R6128
1%
1/20W
MF
2 201
R6125
43
5%
1/20W
MF
2 201
43
5%
1/20W
MF
2 201
5%
1/20W
MF
2 201
R6110
69 14
IN
SPI_CS0_R_L
B
1
PLACE_NEAR=U0500.Y7:5mm
R6111
69 14
IN
SPI_CLK_R
1
PLACE_NEAR=U0500.AA3:5mm
CPU Master
69 14
BI
SPI_MOSI_R
15
BI
SPI_MISO
1
15
R6120
69
SPI_CS0_L
SPI_CLK
1
R6112
15
2
5%
1/20W
MF
201
SPI_MOSI
5%
1/20W
MF
201
2
SPI_MISO_R
1
24.9 2
1%
1/20W
MF
201
46 69
OUT
46 69
B
PLACE_NEAR=R6126.2:5mm
MLB ROM Slave
SPI_MLB_MOSI
2
BI
46 69
BI
46 69
PLACE_NEAR=R6127.2:5mm
5%
1/20W
MF
201
R6123
69
OUT
SPI_MLB_MISO
1
5%
1/20W
MF
201
43
SPI_MLB_CS_L
2
PLACE_NEAR=R6125.2:5mm
2
5%
1/20W
MF
201
R6122
69
43
43
SPI_MLB_CLK
1
R6121
69
1
PLACE_NEAR=U0500.AA2:5mm
PLACE_NEAR=U0500.AA2:5mm
2
5%
1/20W
MF
201
2
5%
1/20W
MF
201
R6113
69 14
15
Matt Card ROM Slave
1
R6126
43
46 64
46 64
LPCPLUS
1
R6127
24.9
46 64
46 64
PLACE_NEAR=U6100.2:5mm
R6114
69 37
OUT
SPI_SMC_MISO
1
24.9 2
1%
1/20W
MF
201
69 37
IN
SPI_SMC_MOSI
PLACE_NEAR=U6100.2:1mm
R6115
1
15
5%
1/20W
MF
201
SMC12 Master
69 37
IN
SPI_SMC_CLK
2
PLACE_NEAR=U6100.5:1mm
R6116
1
15
5%
1/20W
MF
201
69 37
IN
SPI_SMC_CS_L
2
PLACE_NEAR=U6100.6:1mm
R6117
1
15
5%
1/20W
MF
201
A
2
PLACE_NEAR=U6100.1:1mm
SYNC_MASTER=J41_MLB
SYNC_DATE=04/02/2013
PAGE TITLE
LPC+SPI Debug Connector
DRAWING NUMBER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
61 OF 121
SHEET
46 OF 76
1
A
8
7
6
5
4
3
2
1
SPEAKER AMPLIFIERS
APN:353S2888
SPEAKER LOWPASS
80 HZ & lt; FC & lt; 132 HZ
GAIN
6DB
D
D
Right Speaker Connector
R6414
0
PP5V_S4RS3
1
PP5V_S3_U6210
2
5%
1/10W
MF-LF
603
1
C6407
10%
16V
2 X5R-CERM
0201
C6410
74 65 61
IN
1
SPKRAMP_INR_P
CRITICAL
C6411
IN
5%
1/20W
MF
201
2
74
74
10%
16V
X5R-CERM
0201
MAX98300_R_P
MAX98300_R_N
A3
B3
1
SPKRAMP_INR_N
C2
IN
SHDN*
B1
74 64
C1
74 64
1
SPKRAMP_ROUT_P
SPKRAMP_ROUT_N
2
NC
GAIN
C3
4
R_AMP_GAIN
1
PGND
SPKRAMP_SHDN_L
1
M-RT-SM
3
MIN_NECK_WIDTH=0.20 mm
MIN_LINE_WIDTH=0.30 mm
2
A2
65 61
2
MIN_NECK_WIDTH=0.20 mm
MIN_LINE_WIDTH=0.30 mm
10%
16V
X5R-CERM
0201
C
J6404
78171-0002
20%
2 6.3V
POLY-TANT
0805-LLP
WLP
OUT+
IN+
CRITICAL
OUTIN-
C6401
47UF
100K
B2
0.1UF
74 65 61
PVDD
MAX98300
0.1UF
1
R6413 1
U6410
CRITICAL
518S0519
CRITICAL
CRITICAL
NOSTUFF
0.1UF
A1
ALIAS OF PP5VRT_S0, MIN_LINE_WIDTH=0.50MM, MIN_NECK_WIDTH=0.20MM
64 62 58 55 54 49 35 32
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.5 mm
VOLTAGE=5V
R6411
R6412
100K
C
5%
1/20W
MF
2 201
100K
2
5%
1/20W
MF
201
B
B
A
SYNC_MASTER=J41_MLB
SYNC_DATE=02/06/2013
PAGE TITLE
Audio: Speaker Amp
DRAWING NUMBER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
64 OF 121
SHEET
47 OF 76
1
A
8
7
6
5
4
3
2
1
D
D
13 " SPECIFIC
Battery Connector
C
PPVBAT_G3H_CONN
CRITICAL
C6951 1
1UF
J6950
10%
16V 2
X5R
402
WTB-PWR-M82
M-RT-SM
1
C
50 64
C6950
0.1UF
10%
2 25V
X5R
402
1
2
3
4
5
6
64
SMBUS_SMC_5_G3_SCL
SMBUS_SMC_5_G3_SDA
SYS_DETECT_L
IN
BI
37 40 50 64 73
37 40 50 64 73
9
518S0540
2
R69501
10K
CRITICAL
NO STUFF
D6950
5%
1/20W
MF
201 2
RCLAMP2402B
3
8
1
7
SC-75
B
B
A
SYNC_MASTER=MASTER
SYNC_DATE=MASTER
PAGE TITLE
Battery Connector
DRAWING NUMBER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
69 OF 121
SHEET
48 OF 76
1
A
8
7
6
5
4
3
2
1
MLB to LIO Power Cable Connector
CRITICAL
J7000
WTB-PWR-M82
M-RT-SM
64 62 50
PPDCIN_G3H
1
2
3
D
PP5V_S4RS3
6
518S0508
1
NO STUFF
CRITICAL
C7006 C7007 1
0.1UF
10%
16V
2 X5R-CERM
0201
D
62 64
32 35 47
54 55 58
4
5
1UF
10%
35V
X5R 2
603
1
NO STUFF
CRITICAL
C7008 STUFF
NO
1UF
1
10% C7005
35V
0.1UF
2 X5R
603
10%
50V 2
X7R
603-1
Input impedance of 68K meets
sparkitecture requirements
for detection of B121 (16.5V)
1
R7012
68K
1%
1/20W
MF
2 201
CRITICAL
Q7010
SI5419DU
POWERPAK
5A
1
S
D
R7010
G
1
4
100K
5
C7012 1
0.047UF
10%
25V
X5R
0402
C
5%
1/20W
MF
2 201
CRITICAL
2
R7011
C
10K
1
DCIN_ISOL_GATE_R 2
1%
1/20W
MF
201
DCIN_ISOL_GATE
PPDCIN_G3H_ISOL
CRITICAL
K
D7012
GDZT2R6.8
6.8V Zener
A
GDZ-0201
3.425V " G3Hot " Supply
CRITICAL
D7005
R7006
PPBUS_G3H
5%
1/8W
MF-LF
805
R7005
1
10
5%
1/8W
MF-LF
805
B
2
Supply needs to guarantee 3.31V delivered to SMC VRef generator
MIN_LINE_WIDTH=0.4 mm
1
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=8.6V
PPVIN_G3H_P3V42G3H
3
PP18V5_DCIN_ISOL_R
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=18.5V
2
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=18.5V
P3V42G3H_BOOST
6
64 62 56 50 42 41 27
BAT30CWFILM
1 4.7 2 PPBUS_G3H_R SOT-323
DIDT=TRUE
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm
3
64 62 50 42
VIN
C7094 1
BOOST
0.22UF
U7090
LT3470AED
P3V42G3H_SHDN_L 8
R7080
0
DFN
SHDN*
SW
1
C7091 1
CRITICAL
1
1UF
10%
25V
X5R
402
2
C7090
2
25V
X5R
402
NC
CRITICAL
GND
1 CRITICAL
C7092
1UF
10%
7
FB
THRM
PAD
4
2
P3V42G3H_SW
2
R7081
49.9K
1
1%
1/20W
MF
2 201
2520
C7095
5%
50V
NP0-C0G-CERM
0201
& lt; Ra & gt;
R70951
348K
1%
1/20W
MF
201 2
CRITICAL
C7080 1
C7099 1
10UF
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
& lt; Rb & gt;
R70961
1000PF
5%
25V
CERM 2
0402
30 35 36 37 38 40
50 59 61 62 64 65
Vout = 3.425V
300mA Max Output
(Switcher limit)
P3V42G3H_FB
NO STUFF
PP3V42_G3H 17
46
2
22PF
2
NO STUFF
10UH-20%-0.85A-0.46OHM
1
5.6UF
20%
25V
POLY-TANT
CASE-B2-SM
L7095
1
1
B
CRITICAL
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm
SWITCH_NODE=TRUE
DIDT=TRUE
9
CRITICAL
BIAS
NC
5
5%
1/20W
MF
2 0201
10%
10V
CERM 2
402
200K
20%
10V
X5R-CERM
0402-1
CRITICAL
1
C7098
10UF
20%
2
2
10V
X5R-CERM
0402-1
1%
1/20W
MF
201 2
Vout = 1.25V * (1 + Ra / Rb)
A
SYNC_MASTER=J41_MLB
SYNC_DATE=02/06/2013
PAGE TITLE
DC-In & G3H Supply
DRAWING NUMBER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
70 OF 121
SHEET
49 OF 76
1
A
8
7
6
5
4
Reverse-Current Protection
3
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.5 mm
R7192
PPCHGR_DCIN_D_R
Inrush Limiter
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.5 mm
0
1
2
5%
1/16W
4
5
S
R7180 1
IRF9395TRPBF
10%
25V
X5R-CERM
0603
PPDCIN_G3H_ISOL
50
20
1
PPCHGR_DCIN_D_R
2
1
30mA max load
C7120
2
PP5V1_CHGR_VDDP
C7101
5% 48 40 37
1/20W 73 64
MF 48 40 37
73 64
0201
59
Float CELL for 1S
IN
BI
IN
CHGR_ACIN
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
1
R7115
73
255K
73
1%
1/20W
MF
2 201
1
C7150
0.47UF
46.4K
CHGR_VCOMP_R
1%
1/20W
MF
2 201
2
C7115
10%
10V
X5R
0402
1
6
1%
10
4
CHGR_CSI_R_P
2
73
CRITICAL
0.5%
1W
MF-LF
0612
CHGR_CSI_R_N
3 1
2
1
2
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.15 mm
VOLTAGE=18.5V
CRITICAL
C7130
C7121
20%
25V
POLY-TANT
CASE-D3L
0.1UF
2
2
B
1
10%
25V
X5R
402
73
73
CHGR_DCIN
1
20%
25V
POLY-TANT
CASE-D3L
2
C7135
1
1UF
2
2
C7136
C7137
1
1UF
10%
25V
X5R
603-1
2
0.001UF
10%
25V
X5R
603-1
10%
50V
X7R-CERM
0402
2
C
Max Current = 8A
CHGR_SGATE
CHGR_AGATE
CHGR_CSI_P
CHGR_CSI_N
CHGR_BOOT
CHGR_UGATE
CHGR_PHASE
CHGR_LGATE
PLACE_NEAR=U7100.25:2mm
1
2
MIN_LINE_WIDTH=0.5 mm
Q7130
CRITICAL
RJK03P0DPA
MIN_LINE_WIDTH=0.5 mm
DIDT=TRUE
1
7
SWITCH_NODE=TRUE
8AMP-24V
2
1
2
PPBUS_G3H
27 41 42 49 56 62 64
PIMC104T4R7MN-SM
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.6 mm
DIDT=TRUE
DIDT=TRUE
F7140
4.7UH-17A
GATE_NODE=TRUE
MIN_NECK_WIDTH=0.2 mm
CRITICAL
L7130
WPAK
1
DIDT=TRUE
MIN_NECK_WIDTH=0.2 mm
TO SYSTEM
f = 400 kHz
CRITICAL
10%
10V
CERM
402
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.5 mm
CHGR_BGATE
CHGR_AMON
CHGR_BMON
SMC_BC_ACOK
C7125
0.22UF
2
VOLTAGE=8.6V
1206
GATE_NODE=TRUE
6
OUT
41
OUT
41
OUT
37 38 61 65
PPVBAT_G3H_CHGR_REG
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=8.6V
3 4 5
BYPASS=L7130:Q7130:1.5mm
C7140 1
62UF-0.023OHM
20%
11V
TANT-POLY
CASE-B2S-1
C7141 1
C7143 1
62UF-0.023OHM
2
1
20%
11V
TANT-POLY
CASE-B2S-1
20%
11V
TANT-POLY
CASE-B2S-1
2
C7145
1000PF
62UF-0.023OHM
2
2
10%
16V
X7R-CERM
0201
2
10K
1%
1/20W
MF
201 2
B
C7102
10%
10V
X5R
402
CRITICAL
XW7100
R7150
0.01
SM
1
Q7155
SI7137DP
(GND)
2
0.5%
SO-8
1W
TO/FROM BATTERY
MF
PLACE_NEAR=U7100.22:1mm
0612-4
1
3
CHGR_VNEG_R
(CHGR_CSO_N)
2.2
R7152
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.1 mm
0
1
201
2
73 43
1
2
73 43
5%
5%
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.1 mm
(PPVBAT_G3H_CHGR_R)
PPVBAT_G3H_CHGR_R
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=8.6V
CHGR_CSO_R_P
1/20W
PPVBAT_G3H_CONN
48 64
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.15 mm
VOLTAGE=8.6V
1
R7151
(CHGR_CSO_P)
10%
16V
X5R-X7R-CERM
0201
2
4
MF
G
C7116
470PF
2
BYPASS=Q7130:1.5mm
1
1UF
R71161
CHGR_ICOMP_R
1
C7131
33UF-0.06OHM
2
1K
5%
1/20W
MF
201 2
CRITICAL
1
33UF-0.06OHM
CHGR_CSO_R_N
1/20W
MF
0201
4
R71421
2
R7120
470PF
10%
16V
X5R-X7R-CERM
0201
201
0.020
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
D
R7111
200K
5
1
R7196
S
2
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
& lt; Rb & gt;
NO STUFF 1
5%
1/20W
MF
201
3
5%
1/20W
MF
201
(AGND)
MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm
100
CHGR_ICOMP
CHGR_VCOMP
CHGR_VNEG
CHGR_CSO_P
CHGR_CSO_N
29
R7113
1
50
U7100
ISL6259
CHGR_RST_L
SMBUS_SMC_5_G3_SCL
SMBUS_SMC_5_G3_SDA
CHGR_VFRQ
CHGR_CELL
2
10%
25V
X5R
402
1
0.1UF
PGND
1
R7181
22
SMC_RESET_L
VDD
VDDP
VHST CRITICAL DCIN 2
SMB_RST_N
SGATE 26
SCL
AGATE 1
TQFN
SDA
CSIP 28
VFRQ
CSIN 27
CELL
BOOT 25
3 ACIN
UGATE 24
5 ICOMP
PHASE 23
7 VCOMP
LGATE 21
8 VNEG
18 CSOP
BGATE 16
17 CSON
20V/V AMON 9
36V/V BMON 15
(OD) ACOK 14
12
13
11
10
4
6
2
0201
20
19
1
THRM_PAD
IN
C7122
1
10%
10V
X5R
402
2
73
R7122
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5.1V
NO STUFF
0
201
NP0-C0G-CERM
P5V1_FB
5%
1/20W
MF
201
1UF
5%
1/20W
MF
201
Vout = 5.50V
200MA MAX OUTPUT
(Switcher limit)
PPDCIN_G3H_CHGR
50
1
64 46 38 37
10%
16V
X7R-CERM
0402
1
5%
1/16W
MF-LF
402
100K
2
MF
2
5%
1/20W
MF
201
R7101
PP3V42_G3H
2
1%
20%
10V
X5R
603
D
10UF
20%
10V
X5R
603
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.5 mm
VOLTAGE=5.5V
10
2
1
C7199
10UF
1/20W
Vout = 1.25V * (1 + Ra / Rb)
1
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
0.047UF
R7100
681K
CRITICAL
1
R7121
(CHGR_DCIN)
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm
DIVIDER SETS ACIN THRESHOLD AT 13.55V
4.7
PP5V1_CHGR_VDDP 50
1/20W
ACIN pin threshold is 3.2V, +/- 50mV
R7102
C7195
MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.2 mm
5%
1/10W
MF-LF
603
PP5V1_CHGR_VDD
2
402
MF
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=18.5V
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.1 mm
VOLTAGE=5.1V
C7198
R7195
22PF
(CHGR_SGATE)
PP5V5_DCIN:NO
R7105
1%
1/20W
MF
2 201
1
2
2
3
130K
NO STUFF 1
& lt; Ra & gt;
NO STUFF
1
NO STUFF
CRITICAL
(CHGR_AGATE)
MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.2 mm
5%
1/16W
PP5V5_CHGR_VDDP
NO STUFF
1
62K
1
C
GND
FB
THRM
PAD
2
2520
CHGR_SGATE_DIV
2
SOT-323
R7110
NC
2
1
P5V1_SW
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
SWITCH_NODE=TRUE
DIDT=TRUE
5%
50V
1
BAT30CWFILM
59 49 46 40 38 37 36 35 30 17
65 64 62 61
2
MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.2 mm
D7105
2
4
CRITICAL
2
1
0
MF-LF
10UH-20%-0.85A-0.46OHM
2
64 62 49 42
1%
1/20W
MF
201
7
SW
BIAS
1
4.7UF
332K
CRITICAL
L7195
2
402
SHDN*
5
G
R7186
3
CHGR_AGATE_DIV
5%
1/20W
MF
201
CHGR_DCIN 50
DFN
C7184
100K
DIRECTFET-MC
2
G
10%
25V
X5R
402
CERM
1
NO STUFF
9
7
10
8
9
1
2
Q7180
0.1UF
CRITICAL
10%
10V
LT3470A
8
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.4 mm
VOLTAGE=18.5V
2
402
R7191
1
0.22UF
U7190
2
PPDCIN_G3H_INRUSH
CRITICAL
1
6
D
1/20W
MF
201
C7194
VIN
BOOST
NO STUFF
4.7UF
5%
1/16W
PP5V5_VDDP
NO STUFF
C7190
D
2
C7185
D
PPDCIN_G3H
S
64 62 49
MF-LF
402
10%
25V
X5R-CERM
0603
0
P5V1_BOOST
DIDT=TRUE
MF-LF
NCNCNCNC
470K
1%
R7190
1
CHGR_DCIN_D
NO STUFF
1
FROM ADAPTER
PP5V5_DCIN:YES
3
50
R7185
1
5.5v " G3Hot " Supply
For Erp Lot6 spec
NO STUFF
1
2
Need to stuff R7192 if either PP5V5_DCIN:YES or PP5V5_VDDP are used!
(PPVBAT_G3H_CHGR_R)
(CHGR_BGATE)
MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.2 mm
2
C7142
C7111
0.1UF
1
0.01UF
10%
6.3V
CERM-X5R
0201
10%
10V
X5R-CERM
0201
1
2
2
C7100
C7105
1UF
1
0.22UF
10%
10V
X5R
402-1
10%
50V
X5R-CERM
0603-1
C7126
1
1
* R7151 HAS 2.2OHM TO COMPENSATE UNBALANCED VOLTAGE
DUE TO DIFFERENT CURRENT ON _P AND _N. (FROM INTERSIL)
1000PF
10%
16V
X7R-CERM
0201
2
2
C7117
1
1
10UF
GND_CHGR_AGND
10%
25V
X5R
805
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V
A
C7114
1
C7113
1UF
2
2
10%
25V
X5R
402
1
0.1UF
10%
25V
X5R
603-1
2
C7112
0.01UF
2
10%
25V
X7R
402
SYNC_MASTER=J41_MLB
SYNC_DATE=02/09/2013
PAGE TITLE
PBus Supply & Battery Charger
DRAWING NUMBER
Apple Inc.
R
& lt; E4LABEL & gt;
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
.
BRANCH
& lt; BRANCH & gt;
PAGE
71 OF 121
SHEET
50 OF 76
1
A
8
7
6
5
4
3
2
1
D
D
R7201
61 59 58 56 52 46 45 32 17 16
64 62
PP5V_S0
1
1
2
R7202
PP5V_S0_CPUVR_VDD
1
PLACE_NEAR=U7200.16:2mm
1%
1/20W
MF
201
1%
1/20W
MF
201 2
R7223 1R7222 1R7221 1R7220
16.9K
BI
OUT
67 8
IN
IN
1%
1/20W
MF
2 201
ISL95826HRZ-_R6200
CPUVR_NTC
67 38 37 6
NTC
CPU_PROCHOT_L
OUT
5
4
VR_HOT*
17 8
29
28
27
26
1
C7214
52
IN
52
IN
845
1
220PF
IN
C7215
R7215
10%
25V
X7R-CERM 2
201
52
6
CPUVR_COMP
1
1%
1/20W
CPUVR_ISUMN_RC
2
201
MF
1
1
10%
25V
R7210
CPUVR_ISUMN
1
255
0201
X7R-CERM
1
C7210
0.01UF
10%
2 10V
X7R-CERM
0201
43
C7211
C7240
R72401
1
5%
25V
NP0-C0G-CERM 2
0201
C7230
OUT
52
OUT
52
PGOOD
2
CPU_VR_READY
CRITICAL
1
OUT
8 17
0
C
2
5%
1/20W
MF
0201
NC
NC
NC
NC
IMON
ISEN1
ISEN2
ISEN3
1
1
1800PF
NO_XNET_CONNECTION=TRUE
10%
10V
X5R-CERM 2
201
1%
1/20W
MF
201 2
10%
6.3V
CERM-X5R 2
0201
5%
1/20W
MF
2 0201
NC
C7241 1
75K
0.1UF
R7225
56PF
CPUVR_COMP_RC
C7213
3
CPUVR_IMON
1
ISUMP
ISUMN
1
+/-10%
10V
CERM 2
0201-1
CPUVR_DRSEL
NC 9
NC 19
NC 21
NC 24
1.2NF
10%
2 10V
X7R-CERM
0201
25
52
R7224
FB
FB2
12
11
10
0.01UF
1
OUT
DRSEL
RTN
15
14
CPUVR_ISUMN_R
2
1%
1/20W
MF
201
CPUVR_ISEN1
CPUVR_ISEN2
B
2
5%
0201
25V NP0-C0G-CERM
COMP
7
8
CPUVR_FB
CPUVR_FB2
(CPUVR_ISUMP)
47PF
2
CPUVR_PWM2
CPUVR_PWM1
OUT
0
SDA
ALERT*
SCLK
13
CPU_RTN
C7216
820PF
23
22
20
CPUVR_FCCM
VR_ON
30
31
32
CPUVR_ISUMP
18
PWM3
PWM2
PWM1
PROG1
PROG2
PROG3
CPU_VR_EN
IN
41 52 53 55 62 64
NOSTUFF
FCCM
SLOPE
CPUVR_PROG1
CPUVR_PROG2
CPUVR_PROG3
PLACE_NEAR=U7200.30:2mm
NO_XNET_CONNECTION=TRUE
LLP
CPUVR_SLOPE
1%
1/20W
MF
2 201
CPU_VIDSOUT
CPU_VIDALERT_L
CPU_VIDSCLK
52
6.04K
1%
1/20W
MF
2 201
130
1%
1/20W
MF
201 2
67 8
21K
1%
1/20W
MF
2 201
R7280
54.9
67 8
9.31K
1%
1/20W
MF
2 201
PPBUS_S5_HS_COMPUTING_ISNS
FCCM = 1: Forced CCM
FCCM = 0: DCM
FCCM = FLOATING: PS4
U7200
1
R72791
PLACE_NEAR=U7200.32:2mm
C
16
1
2
PP1V05_S0
0.1UF
(GND)
VDD VIN
100KOHM
0201
55 42 38 27 17 16 15 11 8 6
64 62 59 58
C7278 1
10%
25V
X7R 2
0402
1UF
R7237
95.3K
10%
PLACE_NEAR=R7279.32:2mm 6.3V
CERM-X5R 2
0201
0.22UF
C7201
2
5%
1/16W
MF-LF
402
PLACE_NEAR=U7200.17:2mm
33 THRM
PAD
R72361
C7202
1
1
17
9.31K2
1
1
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=12.9V
10%
2 10V
X5R
402-1
R7235
CPUVR_NTC_R
PPVIN_S0_CPUVR_VIN
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V
5%
1/16W
MF-LF
402
10
R7230
95.3K
1%
1/20W
MF
2 201
B
NO_XNET_CONNECTION=TRUE
R7241
NO_XNET_CONNECTION=TRUE
R7243
67 8
IN
CPU_VCCSENSE_P
0
1
CPU_VCCSENSE_P_R
C7242
100PF
2
CPU_VCCSENSE_P_RC
1
5%
25V
NP0-CERM
0201
IN
1%
1/20W
MF
201
NO_XNET_CONNECTION=TRUE
2
5%
1/20W
MF
0201
67 9
1.37K2
1
CPU_VCCSENSE_N
XW7261
SM
1
NOSTUFF
NO_XNET_CONNECTION=TRUE
R7242
1K
2
1%
1/20W
MF
201
1
R7250
1
2K
2
CPUVR_FB_RC
1%
1/20W
MF
201
NOSTUFF
1
330PF
NO_XNET_CONNECTION=TRUE
1
C7260
330PF
10%
16V
2 X7R-CERM
0201
1
C7250
10%
16V
2 X7R-CERM
0201
2
C7261
330PF
10%
16V
2 X7R-CERM
0201
A
SYNC_MASTER=J41_MLB
SYNC_DATE=04/09/2013
PAGE TITLE
CPU VR12.6 VCC Regulator IC
DRAWING NUMBER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
72 OF 121
SHEET
51 OF 76
1
A
8
7
64 62 55 53 51 41
6
5
4
3
2
1
Additonal Input Bulk Caps
PPBUS_S5_HS_COMPUTING_ISNS
THESE TWO CAPS ARE FOR EMC
NOSTUFF
CRITICAL
1
1
C7313
C7314
62UF-0.023OHM
2
20%
11V
TANT-POLY
CASE-B2S-1
1
62UF-0.023OHM
20%
11V
TANT-POLY
CASE-B2S-1
2
2
NOSTUFF
CRITICAL
CRITICAL
CRITICAL
CRITICAL
1
C7315
10UF
20%
16V
X6S-CERM
0603
1
1
C7316
10UF
2
20%
16V
X6S-CERM
0603
1
C7317
1UF
2
10%
16V
X6S-CERM
0402
C7318
0.001UF
2
10%
50V
X7R-CERM
0402
1
2
C7319
0.001UF
C7370
CRITICAL
1
62UF-0.023OHM
10%
50V
X7R-CERM
0402
2
20%
11V
TANT-POLY
CASE-B2S-1
C7371
CRITICAL
1
62UF-0.023OHM
2
20%
11V
TANT-POLY
CASE-B2S-1
C7372
CRITICAL
1
62UF-0.023OHM
2
20%
11V
TANT-POLY
CASE-B2S-1
C7373
CRITICAL
1
62UF-0.023OHM
20%
11V
TANT-POLY
CASE-B2S-1
2
CRITICAL
1
C7374
62UF-0.023OHM
2
20%
11V
TANT-POLY
CASE-B2S-1
C7375
CRITICAL
1
62UF-0.023OHM
2
20%
11V
TANT-POLY
CASE-B2S-1
CRITICAL
1
C7376
62UF-0.023OHM
2
20%
11V
TANT-POLY
CASE-B2S-1
C7377
62UF-0.023OHM
2
20%
11V
TANT-POLY
CASE-B2S-1
CRITICAL
64 62 61
46 45 32 17 16
59 58 56 52 51
PP5V_S0
5
C7310 1
1UF
10%
16V
X6S-CERM
0402
D
D
SWITCH_NODE=TRUE
2
MPCG0730-SM
152S1757
DIDT=TRUE
PWRPAK-SM
NOSTUFF
R7312
2.2
DIDT=TRUE
S
1
6
52 51
IN
IN
CPUVR_FCCM
DFN
7 FCCM
1
2
5
CRITICAL
PHASE 8
OMIT_TABLE
CRITICAL
D
5
THRM LGATE
PAD
CPUVR_LGATE1
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
9
4
353S3942
DIDT=TRUE
C7311
1
R73151
4
5%
1/16W
MF-LF
402
PP5V_S0
R7316
200K
CPUVR_ISEN1
NOSTUFF
DIDT=TRUE
CRITICAL
1
C7323
CRITICAL
1
C7324
62UF-0.023OHM
2
62UF-0.023OHM
20%
11V
TANT-POLY
CASE-B2S-1
20%
11V
TANT-POLY
CASE-B2S-1
2
2
20%
16V
X6S-CERM
0603
6
SWITCH_NODE=TRUE
NOSTUFF
R7322
2.2
Q7320
2
10%
16V
X6S-CERM
0402
1
2
C7328
0.001UF
10%
50V
X7R-CERM
0402
1
2
C7329
0.001UF
10%
50V
X7R-CERM
0402
C
1
PPVCC_S0_CPU
1%
1W
MF
0612
PPVCC_S0_CPU_PH2
1
MIN_LINE_WIDTH=0.6 MM
3
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=1.8V
CPUVR_ISNS2_P
74 42
OUT
CPUVR_ISNS2_N
1
CPUVR_PH2_SNUB
2
S
BOOT 2
2
UGATE 1
5
CRITICAL
PHASE 8
5
THRM LGATE
PAD
CPUVR_LGATE2
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
9
D
OMIT_TABLE
CRITICAL
Q7321
1%
1/20W
MF-LF
0201
G
OUT
51 52
R73251
1K
1%
1/20W
MF
201 2
R7327
NOSTUFF
1
2
1
R7326
200K
NONE
NONE
NONE
0201
1%
1/20W
MF
2 201
OUT
OUT
CPUVR_ISNS1_N
42 52 74
NO_XNET_CONNECTION=TRUE
51
CPUVR_ISUMP
SISA12DN
PWRPAK-SM
353S3942
10%
50V
X7R-CERM
0402
OMIT
CPUVR_ISUMN
NO_XNET_CONNECTION=TRUE
CPUVR_ISEN2
DIDT=TRUE
4
C7322
0.001UF
42 52 74
R7324
1.00
DIDT=TRUE
NOSTUFF
1
1 2 3
OUT
8 10 42 62 64
Vout = 1.85V max
32A max output
f = 700kHz
2
4
5%
1/10W
MF-LF
603 2
SISA18DN
PWRPAK-SM
U7320
4
20%
16V
X6S-CERM
0603
C7327
1UF
0.00075
2
MPCG0730-SM
152S1757
DIDT=TRUE
OMIT_TABLE
CRITICAL
G
4
ISL6208D
GND
2
1
C7326
10UF
R7320
1
CPUVR_PHASE2
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
5
DIDT=TRUE
7 FCCM
THESE TWO CAPS ARE FOR EMC
CRITICAL
1
C7325
10UF
L7320
VCC
CPUVR_FCCM
51 52
CRITICAL
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
DFN
51
OUT
NOSTUFF
CRITICAL
1
0.40UH-20%-16A
CPUVR_UGATE2
CPUVR_ISNS2_N
42 52 74
NO_XNET_CONNECTION=TRUE
2
CPUVR_BOOT1_RC
2
PHASE 2
OUT
CPUVR_ISUMP
PWRPAK-SM
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM
D
IN
NONE
NONE
NONE
0201
1%
1/20W
MF
2 201
1%
1/20W
MF
201 2
CRITICAL
52 51
NOSTUFF
1
2
SISA12DN
C7320 1
1UF
10%
16V
X6S-CERM
0402
R7317
51 52
Q7311
G
10%
16V
CERM
402
3 PWM
OUT
1
1K
10%
50V
X7R-CERM
0402
2
CPUVR_PWM2
OMIT
CPUVR_ISUMN
NO_XNET_CONNECTION=TRUE
C7312
0.001UF
0.22UF
IN
1%
1/20W
MF-LF
0201
1 2 3
2.2
1
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM
51
R7314
1.00
S
CPUVR_BOOT1
59 58 56 52 51 46 45 32 17 16
64 62 61
2
OUT
42 52 74
DIDT=TRUE
R7311
C
CPUVR_ISNS1_N
DIDT=TRUE
NOSTUFF
BOOT 2
UGATE 1
GND
D
1
3
CPUVR_PH1_SNUB
ISL6208D
3 PWM
2
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM 4
VOLTAGE=1.8V
CPUVR_ISNS1_P
74 42
OUT
1
U7310
CPUVR_PWM1
PPVCC_S0_CPU_PH1
5%
1/10W
MF-LF
603 2
1 2 3
VCC
1
CPUVR_PHASE1
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
SISA18DN
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
1%
1W
MF
0612
0.40UH-20%-16A
Q7310
G
4
CPUVR_UGATE1
0.00075
L7310
OMIT_TABLE
CRITICAL
2
PHASE 1
51
R7310
CRITICAL
51 52
S
B
R7321
CPUVR_BOOT2
2
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM
DIDT=TRUE
C7321
2.2
5%
1/16W
MF-LF
402
B
1 2 3
1 CPUVR_BOOT2_RC
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM
DIDT=TRUE
0.22UF
1
2
10%
16V
CERM
402
A
SYNC_MASTER=J41_MLB
SYNC_DATE=04/09/2013
PAGE TITLE
CPU VR12.5 VCC Power Stage
DRAWING NUMBER
Apple Inc.
R
& lt; E4LABEL & gt;
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
.
BRANCH
& lt; BRANCH & gt;
PAGE
73 OF 121
SHEET
52 OF 76
1
A
8
7
6
5
4
3
2
1
D
D
64 62 55 52 51 41
PPBUS_S5_HS_COMPUTING_ISNS
1
1
C7430
62UF-0.023OHM
70 62 53 42 23 22 21 20 19 17
62 54 36
20%
2 11V
TANT-POLY
CASE-B2S-1
PP1V2_S3
1
C7431
62UF-0.023OHM
20%
2 11V
TANT-POLY
CASE-B2S-1
C7432
1
1UF
C7433
1
0.001UF
10%
2 25V
X5R
603-1
10%
50V
2 X7R-CERM
0402
C7434
62UF-0.023OHM
20%
2 11V
TANT-POLY
CASE-B2S-1
BYPASS=U7400.2:1mm
PP5V_S5
C7401 1
10UF
20%
10V 2
X5R
603
BYPASS=U7400.12:1mm
C7400 1
10UF
20%
10V 2
X5R
603
CRITICAL
Q7430
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VLDOIN
12 V5IN
17
59
IN
IN
MEMVTT_PWR_EN
DDRREG_EN
(VTT Enable)
(VDDQ/VTTREF Enable)
DDRREG_1V8_VREF
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.1 mm
C7415 1
0.1UF
10%
16V
X7R-CERM 2
0402
BYPASS=U7400.6:1mm
1
R7415
28.7K
1%
1/20W
MF
2 201
19
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.1 mm
DDRREG_FB
DDRREG_MODE
DDRREG_TRIP
PLACE_NEAR=U7400.8:5mm
U7400
17 S3
16 S5
DDRREG_VBST
DDRREG_DRVH
VBST 15
DRVH 14
SW 13
TPS51916
DDRREG_LL
QFN
DRVL
6 VREF
CRITICAL PGOOD
VDDQSNS
8 REFIN
VTT
19 MODE
VTTSNS
18 TRIP
VTTREF
11
20
9
62
3 24
1
5
SM
1
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.1 mm
2
0.01UF
1%
1/20W
MF
2 201
10%
2 16V
X7R-CERM
0402
BYPASS=U7400.8:1mm
PLACE_NEAR=U7400.19:3mm
PLACE_NEAR=U7400.18:3mm
1
1
R7417 R7418
200K
1%
1/20W
MF
2 201
49.9K
TGR
VSW
6
7
8
MIN_LINE_WIDTH=0.6 MM FDSD0630-SM
MIN_NECK_WIDTH=0.1 MM
DIDT=TRUE
NOSTUFF
1
(DDRREG_DRVL)
XW7460
5
BG
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
1
R7450
R7435
74 41
5%
1/10W
MF-LF
2 603
OUT
OUT
ISNS_1V2_S3_N
PDDR_S3_REG_SNUB
DIDT=TRUE
NOSTUFF
C7462
C7435
10UF
0.001UF
20%
6.3V
2 X5R
603
C7440
330UF
10%
50V
X7R-CERM 2
0402
Vout = 1.35V
C7446
1
20%
2.0V
2 POLY-TANT
0.001UF
10%
CASE-B2-SM1
50V
X7R-CERM 2
CRITICAL
0402
1
C7441
1
62 70
17 19 20 21
22 23 42 53
CRITICAL
1
ISNS_1V2_S3_P
74 41
2.2
PP1V2_S3
VOLTAGE=1.2V 3
4
MIN_LINE_WIDTH=0.8 MM
MIN_NECK_WIDTH=0.1 MM
330UF
20%
2.0V
POLY-TANT 2
CASE-B2-SM1
C7445
1
20%
10UF
2 6.3V
X5R
603
14.1A max output
(Q7435 limit)
f = 400 kHz
PLACE_NEAR=C7440.1:1mm
2
XW7401
SM
1
BYPASS=U7400.3:3mm
1%
1/20W
MF
2 201
PLACE_NEAR=U7400.21:1mm
2
C7450
XW7400
SM
0.22UF
1
B
4
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
CRITICAL
L7430
0.002
1.0UH-20%-11A-0.011OHM
MF-LF
1/4W
1206 1%
1
2 PPDDR_S3_REG_R 1
2
PDDR_S3_REG_L
TG
CRITICAL
PPVTT_S3_DDR_BUF
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.1 mm
VOLTAGE=0.6V
21
C7416
3
(DDRREG_LL)
DDRREG_DRVL DIDT=TRUE GATE_NODE=TRUE
DDRREG_PGOOD
OUT 59
DDRREG_VDDQSNS
PP0V6_S0_DDRVTT
DDRREG_VTTSNS
CRITICAL
PLACE_NEAR=C2720.1:3mm
VTT THRM
GND PAD
4
57.6K
1
10
R7416
7
PGND GND
PLACE_NEAR=U7400.8:5mm
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.6 mm
10%
DIDT=TRUE
25V
X5R
402
DIDT=TRUE
C
VIN 1
0.1UF
1
2
DDRREG_VBST_RC
1/16W
2
DIDT=TRUE
10mA max load
1
0
DIDT=TRUE
GATE_NODE=TRUE
SWITCH_NODE=TRUE
402
5%
1
Q3D
C7425
R7425
MF-LF
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.17 mm
9
C
CSD58873Q3D
PGND
2
(DDRREG_DRVH)
1
10%
10V
CERM 2
402
R7460
(DDRREG_VDDQSNS)
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.17 mm
1
10
5%
1/20W
MF
201
2
DDRREG_VDDQSNS_R
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.17 mm
B
GND_DDRREG_SGND
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.15 mm
VOLTAGE=0V
A
SYNC_MASTER=J41_MLB
SYNC_DATE=02/09/2013
PAGE TITLE
LPDDR3 Supply
DRAWING NUMBER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
74 OF 121
SHEET
53 OF 76
1
A
8
7
6
5
4
3
2
1
D
D
SKIPSEL Strap
VREF2
VREG3
64 62 41
PPBUS_S5_HS_OTHER_ISNS
Auto Skip
(Higher Efficiency)
OOA Auto Skip (Lower Efficiency)
BYPASS=Q7520.1:1.5mm
62 53 36 PP5V_S5
C7541
C7500
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
1UF
10%
16V
X5R
402
402
L7520
2.2UH-20%-13A-0.012OHM
1
CRITICAL
20%
6.3V
ELEC
CASE-B2S
2
C7550 1
62UF
2
20%
6.3V
POLY-TANT
CASE-B2-SM
TGR
VSW
4
10UF
2
SM
20%
10V
X5R
603
1
CRITICAL
C7553
PLACE_NEAR=L7520.1:3mm
1
2
2
2
XW7522
10%
16V
X7R-CERM
0201
SM
1
PLACE_NEAR=L7520.1:1.5mm
P5V_S4RS3_VFB1_XW
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.1 mm
1
PLACE_NEAR=L7520.2:3mm
PLACE_NEAR=L7520.1:3mm
C7571
1000PF
2
SM
NOSTUFF
BG
P5V_S4RS3_LL
SWITCH_NODE=TRUE
32
P5V_S4RS3_DRVL
GATE_NODE=TRUE
30
DIDT=TRUE
P5V_S4RS3_CSP1
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
5
7
C7518
1
NOSTUFF
C7522
P5V_S4RS3_FUNC
0201
P5V_S4RS3_VFB1
P5V_S4RS3_COMP1
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.1 mm
P5VS4RS3_EN_R
10%
50V
X7R-CERM 2
0402
1.33K
2
1
1
9
10
4
VIN
10V
CERM
2
X5R-CERM
1
1%
201
MF
2
P5V_S4RS3_COMP1_R
12
SMC_PM_G2_EN
IN
26
37 38 59
24
P3V3_S5_DRVH
GATE_NODE=TRUE
SW2
25
P3V3_S5_LL
SWITCH_NODE=TRUE
MODE
VFB1
COMP1
P3V3_S5_DRVL
GATE_NODE=TRUE
DIDT=TRUE
RF
VFB2
COMP2
EN1
PGOOD1
EN2
PGOOD2
27
18
17
3
XW7500
1%
1/20W
MF
201
54
2
1000PF
10%
16V
X7R-CERM
0201
2
CSD58873Q3D
1
Q3D
0.1UF
10%
25V
X5R
3
4
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
TG
CRITICAL
TGR
VSW
CRITICAL
5
BG
2
P3V3_S5_VFB2
R7538
1
1
7.5K
R7506
R7539
1%
2
1/20W
PLACE_NEAR=U7501.28:1mm
1%
MF
1/20W
201
2
C7538
1
1
1
5%
25V
NP0-C0G
0201
2
1
22PF
10%
10V
X7R
201
2
P5VP3V3_VREF2
54
R7516
6.65K
201
C7539
4700PF
2
CRITICAL
150UF-0.018OHM-1.8A
XW7560
XW7561
SM
NOSTUFF
R75621
1 C7590
2
20%
SM
1
PLACE_NEAR=L7560.1:3mm
1
59
OUT
OUT
1000PF
10%
16V
X7R-CERM
0201
PLACE_NEAR=L7560.2:1.5mm
1
C7593
2
20%
6.3V
TANT
CASE-B2-SM
XW7562
SM
1%
1/20W
MF
201
C7562
2
1
P3V3_S5_VFB2_XW
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.1 mm
0.001UF
10%
50V
2 X7R-CERM
0402
1
R7563
10
5%
1/20W
MF
2 201
P3V3_S5_VFB2_R
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.1 mm
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.1 mm
1
P5VP3V3_VREF2
B
R7560
23.2K
2
S5_PWRGD
1%
1/20W
MF
201
C7572
CRITICAL
PLACE_NEAR=L7560.2:3mm
P5VS4RS3_PGOOD
59 37
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.1 mm
10K
2
150UF-0.018OHM-1.8A
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.1 mm
R7521
1
2
20%
6.3V
TANT
CASE-B2-SM
10V
X5R
603
2
PLACE_NEAR=L7560.2:3mm
P3V3_S5_CSP2_R
DIDT=TRUE
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.1 mm
2
1
C7592
10UF
NOSTUFF
P3V3_S5_COMP2_R
201
F=400KHZ
2
P3V3_S5_REG_SNUB
DIDT=TRUE
2
MF
MF
2
0201
1.54K
1%
1/20W
MF
201
20K
1%
1/20W
249K
2
1
5%
1/10W
MF-LF
603 2
R7546
1
1
2.2UH-20%-13A-0.012OHM
2.2
10%
16V
X7R-CERM
0402
20
353S3905
L7560
P3V3_S5_REG_L
DIDT=TRUE
2
C7588
1
C
6.5A MAX OUTPUT
PIME063T2R2MS-SM
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
P3V3_S5_COMP2
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.1 mm
P3V3S5_EN_R
6
7
8
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
P3V3_S5_RF
42
Vout = 3.3V
0.1UF
15
PP3V3_S5_REG_R
VIN 1
2
402
P5V_S4RS3_CSP1_R
DIDT=TRUE MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.1 mm
41.2K
2
10%
16V
X5R
402
152S1798
SM
1
C7583
1UF
Q7560
C7564
5%
1/16W
MF-LF
402
P3V3_S5_CSN2
16
21
DIDT=TRUE
P3V3_S5_CSP2
THRM_PAD
R7549
R7564
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
DIDT=TRUE
270PF
2
X5R
603
DRVH2
CSP2
CSN2
1/20W
10%
16V
X7R-CERM
0201-1
10V
DIDT=TRUE
MF
2
2
P3V3_S5_VBST
5%
C7537 1
4700PF
10%
10V
X7R
201
VBST2
CSP1
CSN1
0
201
C7536 1
P3V3_S5_VBST_R
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
DIDT=TRUE
20%
2
402
1
DRVL2
GND
1/20W
10UF
20%
402
EN
DRVL1
R7537
MF
2
DRVH1
SW1
20K
1%
2
VBST1
NO STUFF
1/20W
4.22K
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.1 mm 1 R7520
R7536
7.5K
R7556 1
1%
1/20W
MF
201
11
5
1%
1/20W
MF
201
1
P5V_S4RS3_VFB1_R
2
1/20W
R7547
1
0.001UF
10
1
5%
2
MF
P5V_S4RS3_REG_SNUB
5%
1/20W
MF
201 2
2
P5VP3V3_VREG3
10%
16V
X7R-CERM
0402
DIDT=TRUE
R7523
B
54
2
0
1
R7522
5%
1/10W
MF-LF
2 603
8
R7548
1
1
P5V_S4RS3_CSN1
NO STUFF
0.1UF
2.2
1
P5V_S4RS3_DRVH
GATE_NODE=TRUE
DIDT=TRUE
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
XW7521
31
DIDT=TRUE
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
CRITICAL
2
XW7520
1
150UF-0.035OHM
P5V_S4RS3_VBST
2
1
C7581
1 C7505
2.2UF
10%
10V
0
U7501
DIDT=TRUE
152S1798
1
1
20%
6.3V
POLY-TANT
CASE-B2-SM
7
8
C7503 1
1
0.22UF
QFN
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
PGND
C7554
2
C7501
CRITICAL
2
3
PIME063T2R2MS-SM
150UF-0.035OHM
C7552
TG
P5V_S4RS3_REG_L
DIDT=TRUE
6
14
SKIPSEL1
SKIPSEL2
OCSEL
1
BYPASS=Q7560.1:1.5mm
2
6
19
28
CRITICAL
7.2A MAX OUTPUT
2 0201
P5VP3V3_SKIPSEL
TPS51980A
X5R
Vout = 5.0V
CRITICAL
5%
1/16W
MF-LF
402
10%
25V
2
5%
1/20W
MF
0
0.1UF
1 VIN
0
2 0201
R7545 1
C7524
9
C
1
Q3D
R7501
5%
1/20W
MF
V5SW
Q7520
CSD58873Q3D
F=400KHZ
1
0
23
R7500
2
1
P5V_S4RS3_VBST_R
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
DIDT=TRUE
1
P5VP3V3_VREF2
54
2
NOSTUFF
58 55 54 49 47 35 32 PP5V_S4RS3
64 62
20%
11V
TANT-POLY
CASE-B2S-1
PGND
2
C7582
62UF-0.023OHM
20%
11V
TANT-POLY
CASE-B2S-1
9
2
1
62UF-0.023OHM
54 P5VP3V3_VREG3
1
13
2
10%
16V
X5R
402
C7584
1UF
10%
16V
X7R-CERM
0201
62 58 55 54 49 47 35 32 PP5V_S4RS3
64
VREF2
2
1
22
20%
11V
TANT-POLY
CASE-B2S-1
C7570
1000PF
62UF-0.023OHM
20%
11V
TANT-POLY
CASE-B2S-1
1
VREG3
62UF-0.023OHM
1
33
C7540
29
1
VREG5
C7542
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.1 mm
1
1%
1/20W
MF
201
R7561
10K
GND_P5VP3V3_SGND
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V
2
PLACE_NEAR=U7501.4:2mm
PLACE_NEAR=U7501.21:2mm
1
1
R7551
R7552
0
0
5%
1/20W
MF
2 0201
59
IN
P5VS4RS3_EN
1%
1/20W
MF
201
5%
1/20W
MF
2 0201
59
IN
S5_PWR_EN
Power
A
SYNC_MASTER=J41_MLB
SYNC_DATE=09/17/2012
PAGE TITLE
5V S4RS3 / 3.3V S5 Power Supply
DRAWING NUMBER
Apple Inc.
& lt; SCH_NUM & gt;
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
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BRANCH
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PAGE
75 OF 121
SHEET
54 OF 76
1
SIZE
D
A
8
7
6
5
4
3
2
1
D
D
1.05V S0 Regulator
PPBUS_S5_HS_COMPUTING_ISNS
64 62 53 52 51 41
C7620
51 42 38 27 17 16 15 11 8 6
64 62 59 58 55
PP1V05_S0
1
C7621
62UF-0.023OHM
20%
11V
TANT-POLY
CASE-B2S-1
20%
11V
TANT-POLY
CASE-B2S-1
P1V05S0_BOOT_RC
PP5V_S4RS3
C7601
1
10UF
C
C7600
10UF
1
2
R7630
2.2
BYPASS=U7600.2:1mm
603
TPS51916
FDPC1012S
10%
16V
X7R-CERM 2
0402
BYPASS=U7600.6:1mm
1
R7611
35.7K
P1V05S0_FB
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.1 mm
8 REFIN
P1V05S0_MODE 19 MODE
P1V05S0_TRIP 18 TRIP
1%
1/20W
MF
2 201
PLACE_NEAR=U7600.8:5mm
1%
1/20W
MF
2 201
PLACE_NEAR=U7600.8:5mm
C7616
0.01UF
10%
16V
0402
2 X7R-CERM
BYPASS=U7600.8:1mm
1
R7610
1K
1%
1/20W
MF
2 201
1
1
7
1
10
49.9K
P1V05S0_LL
1%
1/20W
MF
SW
L7630
1
NOSTUFF
R7632
2 PP1V05_S0_REG_R
FDSD0630-SM
CRITICAL
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
1
3
Vout = 1.05V
CRITICAL
OUT
59
C7650
C7623
20%
2.0V
POLY-TANT
CASE-B2-SM1
1
1000PF
74 42
C7632
1
OUT ISNS_1V05_S0_P
74 42
5%
25V
CERM
0402
OUT ISNS_1V05_S0_N
1
21A Max Output
f = 300 kHz
330UF
PLACE_NEAR=L7630.2:1.5mm
P1V05S0_LL_SNUB
DIDT=TRUE
NOSTUFF
62 64
38 42 51
6 8 11 15
16 17 27
55 58 59
PP1V05_S0
2
4
C7649
5%
1/10W
MF-LF
2 603
7 LSG
2
2
CRITICAL
1
10%
50V
X7R-CERM 2
0402
2
2
C7648
PLACE_NEAR=C7648.1:1mm
330UF
0.001UF
1%
1/20W
MF
XW7600
SM
1%
1w
CYN
0612-SHORT
1.0UH-20%-11A-0.011OHM
3
4
1
P1V05S0_VTTREF
2
0.003
2.2
P1V05S0_PGOOD
17.4K
1
2
402
VTT THRM
GND PAD
201
201
2 PLACE_NEAR=U7600.19:3mm 2 PLACE_NEAR=U7600.18:3mm
B
5%
1/16W
MF-LF
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
GATE_NODE=TRUE
DIDT=TRUE
R7613 R7614
47.5K
OMIT
R7640
HSG
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
GATE_NODE=TRUE
DIDT=TRUE
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
SWITCH_NODE=TRUE
DIDT=TRUE
VTTREF 5
1
9 V+
2 P1V05S0_DRVH_R
P1V05S0_DRVL
PGND GND
R7612
11
20
9
3 P1V05S0_VTT
1
0
GND
GND
GND
1
1
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
GATE_NODE=TRUE
DIDT=TRUE
21
0.1UF
DRVL
PGOOD
VDDQSNS
VTT
VTTSNS
8 V+
R7631
P1V05S0_DRVH
QFN
CRITICAL
4
C7615
1UF
C
2
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm
DIDT=TRUE
VBST 15
DRVH 14
SW 13
U7600
6 VREF
C7624
10%
2 16V
X5R
402
CRITICAL
10
6
59
20%
11V
TANT-POLY
CASE-B2S-1
P1V05S0_VBST
12 V5IN
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.1 mm
62UF-0.023OHM
LLP
VLDOIN
P1V05_S0_VREF
1
C7619
Q7630
2
BYPASS=U7600.12:1mm
17 S3
16 S5
2
10%
16V
X7R-CERM
0402
MF-LF
P1V05S3_EN
P1V05S0_EN
1
2
C7630
5%
1/10W
20%
10V 2
X5R
603
Scrub S3 & S5 pins connections!
1
0.1UF
20%
10V 2
X5R
603
1
5%
25V
CERM
0402
PLACE_NEAR=Q7630.8:1.5mm
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm
DIDT=TRUE
1
C7622
1000PF
2
5
64 62 58 54 49 47 35 32
1
62UF-0.023OHM
2
XW7610
SM
20%
2.0V
POLY-TANT
CASE-B2-SM1
1
1
0.22UF
1
B
10%
10V
CERM 2
402
P1V05S0_AGND
PLACE_NEAR=U7600.21:1mm
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V
R7641
P1V05S0_VDDQSNS
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.17 mm
1
10
5%
1/20W
MF
201
2
P1V05S0_VDDQSNS_R
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.17 mm
A
SYNC_MASTER=J41_MLB
SYNC_DATE=03/28/2013
PAGE TITLE
1.05V S0 Power Supply
DRAWING NUMBER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
76 OF 121
SHEET
55 OF 76
1
A
8
7
6
5
4
3
2
1
PPBUS S0 LCDBkLT FET
MOSFET
FDC638APZ
CHANNEL
P-TYPE
CRITICAL
RDS(ON)
43 mOhm @4.5V
Q7706
LOADING
0.65 A (EDP)
F7700
1 2 5 6
FDC638APZ_SBMS001
SSOT6-HF
PPVIN_S0SW_LCDBKLT_FET
1
PPBUS_G3H
D
2
PPVIN_S0SW_LCDBKLTFET
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.6V
603-HF
PLACE_SIDE=BOTTOM
R7788
0.1UF
301K
56 41
10%
16V
X7R-CERM 2
0402
1%
1/20W
MF
2 201
PLACE_NEAR=L7701.2:3mm
CRITICAL
L7701
C7782 1
1
41
THERE IS A SENSE RESISTOR BETWEEN
PPBUS_SW_LCDBKLT_PWR
CRITICAL
AND PPBUS_SW_BKL
ON THE SENSOR PAGE
15UH-2.8A
3
64 62 50 49 42 41 27
4
3AMP-32V-467
*C7797 AND C7799 SHOULD BE PLACED IN T-BONE FOR ACOUSTICS
*PPBUS_SW_LCDBKLT_PWR_SW SHOULD BE KEPT AS SHORT AS POSSIBLE.
*LCD_BKLT_PWM SHOULD BE AWAY FROM BOOST CIRCUIT
C7712 1
10UF
10%
25V 2
X5R
805
PLACE_NEAR=L7701.1:3mm
LCDBKLT_EN_DIV_L
1
R7789
1
PPVIN_S0SW_LCDBKLT
CRITICAL
2
PIMB053T-SM
1
C7713
0.1UF
PPHV_S0SW_LCDBKLT
D7701
SOD-123
A
LCDBKLT_BOOST
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.150 MM
VOLTAGE=50V
SWITCH_NODE=TRUE
DIDT=TRUE
RB160M-60G
10%
2 25V
X5R
402
PLACE_NEAR=L7701.1:3mm
10%
2 50V
X7R-CERM
0402
59 58 56 52 51 46 45 32 17 16
64 62 61
D 3
BYPASS=U7701.D1:5mm
1
DMN5L06VK-7
1
1UF
S 4
74 65 64 62
36 30 27 18 17 15 13 12 11 8
61 59 45 44 43 42 41 40 39 38
LCDBKLT_DISABLE
IN
G
C1
D1
VDDIO VLDO
S 1
BKL_FLTR
C2
FILTER
BKL_ISET
B3
ISET
BKL_FSET
B4
FSET
BKL_SCL
BKL_SDA
D3
D4
SCLK
BKLT:ENG
3
RES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM
R7720,R7721,R7722
BKLT:ENG
OUT1 E5
SDA
OUT2 D5
BKL_PWM
BKL_EN
A4
A3
PWM
EN
OUT3 C5
OUT4 E3
BKL_FAULT
C3
FAULT
OUT5 E2
OUT6 E1
PPVIN_S0SW_LCDBKLT
2
R7731
200K
1%
1/20W
MF
201
R7704
1
33
2
TP 1
TP7701 TP-P6
1
R7715
100K
Fpwm=9.62kHz
5%
1/20W
MF
201
1
I_LED=17.1mA
C7704
33PF
1
R7755
5%
2 25V
NPO-C0G
0201
10K
R77141
21.5K
1%
1/20W
MF
201 2
5%
1/20W
MF
2 201
see spec for others
R7718
BKL_ISEN1
BKL_ISEN2
BKL_ISEN3
BKL_ISEN4
BKL_ISEN5
BKL_ISEN6
R7719
1
LED_RETURN_2
2
5% 1/16W MF-LF 402
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
1
LED_RETURN_3
2
5% 1/16W MF-LF 402
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
OUT
60 64
OUT
60 64
OUT
60 64
OUT
60 64
OUT
60 64
BKLT:PROD
R7721
0
1
LED_RETURN_4
2
5% 1/16W MF-LF 402
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
BKLT:PROD
1
LED_RETURN_5
2
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
PLACE_NEAR=U7701.E2:10mm
5% 1/16W MF-LF 402
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
BKLT:PROD
0
1
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
PLACE_NEAR=U7701.E1:10mm
1%
1/20W
MF
2 201
60 64
BKLT:PROD
0
0
R7722
OUT
BKLT:PROD
0
R7720
90.9K
I_LED=369/Riset
5% 1/16W MF-LF 402
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
PLACE_NEAR=U7701.E3:10mm
R7716
LED_RETURN_1
2
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
PLACE_NEAR=U7701.C5:10mm
1
2
LED_RETURN_6
5% 1/16W MF-LF 402
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
XW7710
SM
GND_BKL_SGND
B
1
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
PLACE_NEAR=U7701.D5:10mm
CRITICAL
PLACE_SIDE=BOTTOM
1%
1/20W
MF
2 201
0
A5
GND_SW
GND_SW
1
GND_L
2
5%
1/20W
MF
0201
FB
R7717
BKLT:PROD
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
PLACE_NEAR=U7701.E5:10mm
A1
A2
0
2
5%
1/20W
MF
0201
VSYNC
LP8550
5%
1/20W
MF
201
SW_0 B1
SW_1 B2
E4
1
2
GND_S
SMBUS_PCH_DATA
BI
Addr: 0x58(Wr)/0x59(Rd)
BOM OPTION
C
BKL_VSYNC_R
10K
B5
0
1
69 40 25 19 16 14
CRITICAL
U7701
SMBUS_PCH_CLK
EDP_BKLT_PWM
R7717,R7718,R7719
25-BUMP-MICRO
R7757
IN
REFERENCE DES
RES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM
VIN
D2
R7753
13
DESCRIPTION
3
103S0198
1
56 41
QTY
103S0198
R7741
IN
2
PART NUMBER
10%
6.3V
CERM-X5R 2
0201
BKLT_PLT_RST_L
69 40 25 19 16 14
10UF
0.1UF
(GND_BKL_SGND)
18
C7799
10%
2 50V
X5R
1210-1
10.2 ohm resistors for current
measurement on LED strings.
C7711
SOT-563
2
10%
2 50V
X5R
1210-1
CRITICAL
1
0.01UF
BYPASS=U7701.C4:4mm
1
D 6
Q7707
C7714
1
PP3V3_S0
DMN5L06VK-7
C
10UF
PLACE_NEAR=C7797.1:5mm
10%
2 10V
X5R-CERM
0201
10%
25V
X5R 2
603-1
C4
G
VOLTAGE=50V
MIN_LINE_WIDTH=0.1 MM
MIN_NECK_WIDTH=0.1 MM
BYPASS=U7701.D1:3mm
C7710
SOT-563
5
C7797
XW7720
SM
PPVOUT_SW_LCDBKLT_FB
EDP_BKLT_EN
1
PP5V_S0
LCDBKLT_EN_L
IN
C7796
PLACE_NEAR=U7701.A5:3mm
PLACE_NEAR=D7701.2:5mm
PLACE_NEAR=D7701.2:3mm
1%
1/20W
MF
2 201
13
CRITICAL
1
220PF
147K
Q7707
D
60 62 64
K
1
2
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=0V
(EEPROM should set EN_I_RES=1)
B
PLACEMENT_NOTE=Keep away from noise nodes(E4, A1, A2, B1, B2 pins)
Keyboard Backlight Driver & Detection
CRITICAL
L7750
PP5V_S0
59 58 56 52 51 46 45 32 17 16
64 62 61
BYPASS=U7750.1:2:2 MM
C7750
Keyboard Backlight Connector
10UH-0.58A-0.35OHM
1
2
KBDLED_SW
1098AS-SM
1
2
1UF
10%
10V
X5R 2
402-1
CRITICAL
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.225 MM
SWITCH_NODE=TRUE
DIDT=TRUE
J7715
FF14A-4C-R11DL-B-3H
VIN
NC
U7750
SPN035007G
1
MLF
37
SMC_SYS_KBDLED
BI
64
KBDLED_FB
3 EN
2
SW 7
CRITICAL
6 FB
OUT 1 64
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM 5
VOLTAGE=40V
NC
NC
3
KBDLED_ANODE
1
THRM
C7755
0.22UF
PAD
10%
50V
2 X5R-CERM
0603-1
9
4
5%
1/16W
MF-LF
2 402
8
GND
4.7
A
4
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=40V
1
R7700
F-RT-SM
5
1
NC
C7756
6
0.22UF
10%
50V
2 X5R-CERM
0603-1
518S0793
SYNC_MASTER=J41_MLB
SYNC_DATE=02/06/2013
PAGE TITLE
LCD/KBD Backlight Driver
DRAWING NUMBER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
77 OF 121
SHEET
56 OF 76
1
A
8
7
6
5
4
3
2
1
1.05V SUS LDO
Cougar Point requires JTAG pull-ups to be powered at 1.05V when SUS suspend well is active.
Pull-ups (3) must be 51 ohms to support XDP (not required in production).
70mA is required to support pull-ups. Alternative is strong voltage
dividers (200/100) to 3.3V S5, which burns 100mW in all S-states.
D
D
CRITICAL
XDP
U7840
64 62 59 58 46 18 14 11 8
TPS720105
SON
PP3V3_SUS
4
PP1V05_SUS
C7840
1
1UF
C7824
10%
6.3V
CERM
402
CRITICAL
1
C7820
1000PF
20%
6.3V
X5R-CERM-1
603
2
NC
2
GND
5
Max Current = 0.35A
NC
XDP
THRM
PAD
1
C7841
2.2UF
7
2
2
10%
6.3V
X5R
402
1
1
VIN
22UF
10%
16V
X7R-CERM
0201
OUT
EN
XDP
1.8V S3 REGULATOR
PP3V3_S5
IN
Vout = 1.05V
1
3
59 58 57 42
16 15 13 11 8
34 29 28 18 17
74 64 62 60
16 62
BIAS
6
2
OMIT
152S1870
U7820
R7829
L7820
0.002
2.2UH-20%-2.0A-0.108OHM
ISL8009B
DFN
1%
1W
MF
0612-SHORT
2520-SM
59
IN
P1V8S3_EN
2 EN
59
OUT
P1V8S3_PGOOD
3 POR
VFB 6
4 SKIP
RSI 5
CRITICAL LX 8
GND
7
C
P1V8S3_SW
1
SWITCH_NODE=TRUE
DIDT=TRUE
1
3
PP1V8_S3_REG_R
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.2V
2
CRITICAL
P1V8S3_FB
CRITICAL
1
C7823
1
THRM_PAD
9
R7820 1
113K
1%
1/20W
MF
201
2
C7825
22UF
5%
25V
NP0-C0G-CERM
0201
20%
6.3V
X5R-CERM-1
603
2
NC
CRITICAL
C7821
47PF
2
4
20 21 22 23 57 62
NC
1
Vout = 1.794V
Max Current = 1.8A
Freq = 1 MHz
22UF
20%
6.3V
X5R-CERM-1
603
PP1V8_S3
2
C
2
& lt; Ra & gt;
CRITICAL
R7821 1
C7822
90.9K
1
22UF
1%
1/20W
MF
201 2
20%
6.3V
X5R-CERM-1
603
2
& lt; Rb & gt;
Vout = 0.8V * (1 + Ra / Rb)
B
B
1.5V S0 LDO
CRITICAL
U7870
TPS72015
SON
PP1V5_S0
PP3V3_S5
4 BIAS
6 IN
OUT 1
3 EN
NC 2
34 29 28 18 17 16 15 13 11 8
74 64 62 60 59 58 57 42
62 57 23 22 21 20
IN
PP1V8_S3
59 28
IN
PM_SLP_S3_BUF_L
C7870
1
C7871
1UF
A
10%
6.3V
CERM
402
1
1UF
10%
6.3V
CERM
402
2
2
GND
5
THRM
PAD
7
8 58 59 62 64
Vout = 1.5V
Max Current = 0.02A
NC
1
C7872
2.2UF
2
10%
6.3V
X5R
402
SYNC_MASTER=J41_MLB
SYNC_DATE=02/06/2013
PAGE TITLE
BYPASS=U7870.4:1mm
BYPASS=U7870.6:1mm
Misc Power Supplies
DRAWING NUMBER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
78 OF 121
SHEET
57 OF 76
1
A
8
7
6
5
1.5V S0 Audio Switch
4
3
2
1
Loading specs per J41/43_PowerBudget_Riviera_rev0.99e
NOSTUFF
1
0
2
5%
1/20W
MF
0201
NOSTUFF
0
TPS22924
CSP
A2
B2
2
D
VIN
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.17 mm
VOLTAGE=1.5V
MAKE_BASE=TRUE
PP1V5_S0SW_AUDIO
U8040
10K
5%
1/20W
MF
201
PP1V5_S0SW_AUDIO_HDA 8
2
5%
1/20W
MF
0201
1
R8040
PP1V5_S0SW_AUDIO_HDA
R8041
1
VOUT
PP1V5_S0SW_AUDIO
A1
B1
CRITICAL
59
P1V5S0SW_AUDIO_EN
IN
3.3V SUS Switch
OMIT
R8020
34 29 28 18 17 16 15 13 11 8
74 64 62 60 59 58 57 42
EDP: 35mA
59
P3V3SUS_EN
IN
NC
TPS22924C
Load Switch
R(on)
@ 1.8V
19.6 mOhm Typ
21.8 mOhm Max
Current
PP3V3_SUS
EDP: 112mA
8 11 14 18 46 57 59 62 64
D
NC
U8020
GND
Part
2A Max
Load Switch
R(on)
@ 2.5V
18.5 mOhm Typ
25.8 mOhm Max
Current
20%
6.3V 2
X5R
0201-1
TPS22924C
Type
1.0UF
20%
6.3V 2
X5R
0201-1
VOUT
C2 ON
C8020 1
Part
C1
VIN
PP3V3_SUS_FET_R
A1
B1
CRITICAL
Type
1.0UF
CSP
A2
B2
GND
C8040 1
1%
1W
MF
0612-SHORT
1
2
VOLTAGE=3.3V
4
MIN_LINE_WIDTH=0.50MM 3
MIN_NECK_WIDTH=0.20MM
TPS22924
PP3V3_S5
U8040
C2 ON
0.002
U8020
58 61 65
58 61 65
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.17 mm
VOLTAGE=1.5V
MAKE_BASE=TRUE
8 11 17 58
11 17 58
C1
R8042
PP1V5_S0
59 57 8
64 62
2A Max
1.05V PCH HSIO Switch
3.3V SSD Switch
3.3V S4 Switch
VIN
VOUT
CRITICAL
59 28 18
IN
S4_PWR_EN
A1
B1
NC
C2 ON
1
C1
SLG5AP1471V D
C8070
TDFN
10%
2 6.3V
CERM-X5R
0201
U8070
58 15
IN
PCH_HSIO_PWR_EN
9
Load Switch
P3V3S0SW_SSD_FET_RAMP
R(on)
@ 2.5V
18.5 mOhm Typ
25.8 mOhm Max
Current
C8071 1
2A Max
7
2
ON
TDFN
CAP
SSD_PWR_EN
30 15
64 59
IN
CRITICAL
4700PF
D
3
S
5
PP3V3_S0SW_SSD_FET_R
OMIT
PP1V05_S0SW_PCH_HSIO
EDP: 1.84A
6 8 11 15 16 17 27 38 42 51
55 58 59 62 64
8 11 58 62
U8005
C
SLG5AP1417V
Type
U8070
Load Switch
R(on)
@ 4V Vgs
9.8 mOhm Typ
TBD mOhm Max
Current
HSIO has turn-on requirement of
& lt; 0.1V/uS ramp rate and
& lt; 65uS from EN to 95% (1.05V)
Part
SLG5AP1453V
1
Type
6A Max
Load Switch
R(on)
@ 25C
7.8 mOhm Typ
8.5 mOhm Max
5.3A Max
0
2
5%
1/20W
MF
0201
R8011
PP1V05_S0
5
7
EDP: 5A
Sense R on sensor page
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
NOSTUFF
P3V3S0_EN
S
Part
Current
IN
CRITICAL
41
R8070
59 58
ON
2
3
GND
GND
10%
10V 2
X7R
201
D
S
SLG5AP1453V
TPS22924C
3.3V S3 Switch
U8005
0.1UF
VDD
Part
20%
6.3V 2
X5R
0201-1
VDD
10%
10V
X5R 2
402
NC
Type
1.0UF
C
1UF
29 33 36 38 39 62 64
U8000
GND
C8000 1
PP3V3_S4
EDP: 119mA
C8005 1
PP3V3_S5
8
CSP
A2
B2
34 29 28 18 17 16 15 13 11 8
74 64 62 60 59 58 57 42
1
PP3V3_S5
1%
1W
MF
0612-SHORT
1
2
PP3V3_S4_FET_R
VOLTAGE=3.3V
4
MIN_LINE_WIDTH=0.50MM 3
MIN_NECK_WIDTH=0.20MM
1
0.002
U8000
TPS22924
8
74 64
57 42 34 29
15 13 11 8
28 18 17 16
62 60 59 58
PP5V_S0
59 58 56 52 51 46 45 32 17 16
64 62 61
OMIT
R8000
0.002
U8010
TPS22924
PP3V3_S5
A2
B2
CSP
VIN
VOUT
A1
B1
1%
1W
MF
0612-SHORT
1
2
PP3V3_S3_FET_R
VOLTAGE=3.3V
3
4
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
NC
PP3V3_S3
EDP: 1.02A
15 18 19 33 36 40 41 62 64
NOSTUFF
Q8060 CRITICAL
IRFHM830DPBF
PQFN3.3X3.3
NC
CRITICAL
C2 ON
Part
64 62
51 42 38 27 17 16 15 11 8 6
59 58 55
TPS22924C
Type
Load Switch
R(on)
@ 2.5V
18.5 mOhm Typ
25.8 mOhm Max
Current
PP5V_S0
59 58 56 52 51 46 45 32 17 16
64 62 61
R8063
10K
2A Max
5%
1/20W
MF
201 2
59
28
11
16
42
64
58
18
8
15
34
62
A2
B2
CSP
VIN
VOUT
A1
B1
EDP: 1A
P3V3S0_EN
IN
2
U8030
58 15
Part
Type
R(on)
@ 2.5V
18.5 mOhm Typ
25.8 mOhm Max
SMC_SENSOR_PWR_EN
CSP
VIN
VOUT
PP3V3_S4SW_SNS_FET_R
A1
B1
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.5mm
MIN_NECK_WIDTH=0.2mm
1
1
C1
1
0
20%
6.3V 2
X5R
0201-1
8
S 4
HSIOFET_DRV_H
0.1UF
10%
2 16V
X5R-CERM
0201
U8080
5%
1/16W
MF-LF
402
2
PP3V3_S4SW_SNS
EDP: 50mA
41 42 43 62
C8081 1
P5VS0_FET_RAMP
59
IN
P5VS0_EN
7
CAP
2
ON
TDFN
CRITICAL
GND
10%
10V 2
X7R
201
U8050
OMIT
R8081
0.002
D
3
S
5
PP5V_S0_FET_R
VOLTAGE=5V
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
1%
1W
MF
0612-SHORT
1
2
3
4
NC
SYNC_MASTER=J41_MLB
PP5V_S0
EDP: 300mA?
NC
Power FETs
DRAWING NUMBER
U8080
Apple Inc.
Part
TPS22924C
Part
SLG5AP1438V
Type
Load Switch
Type
Load Switch
R(on)
@ 2.5V
18.5 mOhm Typ
25.8 mOhm Max
R(on)
15 mOhm Typ
17 mOhm Max
2A Max
Current
7
6
5
4
SYNC_DATE=02/06/2013
PAGE TITLE
16 17 32 45 46 51 52 56 58 59
61 62 64
Current
1.0UF
G
10%
10V
X5R-CERM 2
0201
C8080
SLG5AP1443V
4700PF
C2 ON
GND
C8050 1
S
8
TPS22924
CRITICAL
IN
G
4
5
1
0.01UF
PP5V_S4RS3
R8050
U8050
42 39 37
5
S 1
C8060
5V S0 Switch
VDD
A2
B2
G
PCH_HSIO_PWR_EN
SOT-563
2A Max
3.3V Sensor Switch
PP3V3_S5
IN
5%
1/20W
MF
201 2
DMN5L06VK-7
HSIOFET_EN
NOSTUFF
(HSIOFET_EN_L)
64 62 55 54 49 47 35 32
8
13
17
29
57
60
74
R80621
D 3
Load Switch
Current
A
D
Q8062
TPS22924C
20%
6.3V 2
X5R
0201-1
64
59
42
28
16
11
15
18
34
58
62
NOSTUFF
SOT-563
330
GND
1.0UF
3
DMN5L06VK-7
P-CHANNEL
C2 ON
C8030 1
1
B
NOSTUFF
5%
1/20W
MF
201 2
G
41
C1
59 58
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
HSIOFET_DISCHARGE
R8061
S
PP3V3_S0_FET_R
CRITICAL
2
D 6
Q8062
5%
1/16W
MF-LF
2 402
HSIOFET_DRV_L
NOSTUFF 1
330
NOSTUFF
Sense R on sensor page
U8030
TPS22924
PP3V3_S5
6
D
HSIOFET_EN_L
3.3V S0 Switch
R8060
SOT-963
N-CHANNEL
8 11 58 62
300
NTUD3169CZ
1
PP1V05_S0SW_PCH_HSIO
EDP: 1.84A
NOSTUFF
1
Q8061
NOSTUFF
B
60
29
13
17
57
74
PP1V05_S0
NOSTUFF
G
20%
6.3V 2
X5R
0201-1
4
C1
1.0UF
S
U8010
GND
C8010 1
D
P3V3S3_EN
IN
5
59
1 2 3
74 64
57 42 34 29
15 13 11 8
28 18 17 16
62 60 59 58
2.5A
3
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
80 OF 121
SHEET
58 OF 76
1
A
8
7
6
5
4
3
2
S5 Enables
S3 Enables
PLACE_NEAR=U7501.21:7mm
54 38 37
59
OUT
SMC_PM_G2_EN
IN
SMC_PM_G2_EN
1
59 37 36 29 18 13
R8140
54 38 37
59
MAKE_BASE=TRUE
100
34 29 28 18 17 16 15 13 11 8
74 64 62 60 59 58 57 42
2 59
54
S5_PWR_EN
S5_PWR_EN
OUT
MAKE_BASE=TRUE
5%
1/20W
MF
201
PP3V3_S5
C8170
NOSTUFF
S5 Power Good
38 37
PM_SLP_S5_L
IN
PLACE_NEAR=U7501.20:7mm
2
OUT
37 54 59
18 28 58 59
S4_PWR_EN
0
1
2
USB_PWR:STBY USB_PWR:S3
1
OUT
MAKE_BASE=TRUE
PM_SLP_S4_L
0
1
57 59
DDRREG_EN
DDRREG_EN
OUT
53 59
C8111
20%
10V
CERM
402
1
C8116
2
PLACE_NEAR=U7400.16:6mm
C8112
1
0.47UF
10%
6.3V
CERM-X5R
402
0.47UF
10%
6.3V
CERM-X5R
402
2
PLACE_NEAR=U7820.2:6mm
D
NO STUFF
PLACE_NEAR=U8010.D2:6mm
100
5%
1/20W
MF
2 201
5%
1/20W
MF
2 201
Mobile System Power State Table
State
USB_PWR_EN
35 59 61 65
OUT
MAKE_BASE=TRUE
SMC_ADAPTER_EN
SMC_PM_G2_ENABLE
SMC_S4_WAKESRC_EN
PM_SUS_EN
PM_SLP_S5_L
PM_SLP_S4_L
PM_SLP_S3_L
Run (S0)
PLACE_NEAR=U4600.4:6mm
USB_PWR_EN
65 61 59 35
X
1
1
1
1
1
1
NO STUFF
2
5%
1/20W
MF
0201
NO STUFF
1
1
1
1
1
1
0
C8114
Sleep (S3)
0
1
1
1
1
1
0
0.47UF
Deep Sleep (S4AC)
1
1
1
0
0
0
0
10%
2 6.3V
CERM-X5R
402
PLACE_NEAR=U7501.4:15mm
A
Sleep (S3AC)
1
P5VS4RS3_EN_RC
R8179
59 37 36 29 18 13
58 59
OUT
R8117
100
2
USB_PWR:S3
15 30 58 59 64
OUT
1
R8114
PLACE_NEAR=U4600.4:6mm
5%
1/20W
MF
0201
SSD_PWR_EN
1
2
R8177
SSD Enable
IN
OUT
5%
1/20W
MF
0201
59 58 28 18
SSD_PWR_EN
NO STUFF
USB_PWR:STBY
S5_PWRGD
MAKE_BASE=TRUE
64 59 58 30 15
0
1
S5_PWRGD-- & gt; SMC
SMC-- & gt; PM_DSW_PWRGD
P3V3S3_EN
P1V8S3_EN
MAKE_BASE=TRUE
18 28 58 59
R8115
100K
S5_PWRGD
OUT
0.1UF
R8141
59 54 37
59 53
S4_PWR_EN
S4_PWR_EN
1
P1V8S3_EN
MAKE_BASE=TRUE
3
NC
P3V3S3_EN
MAKE_BASE=TRUE
NC
5
PLACE_NEAR=U8010.D2:6mm
59 57
SOT891
S4_PWR_EN
4
MAKE_BASE=TRUE
PP3V42_G3H
5%
1/20W
MF
2 0201
59 58
74LVC1G32
1
0
PLACE_NEAR=U7820.2:6mm
U8170
2
SMC_S4_WAKESRC_EN
R8112
0
5%
1/20W
MF
2 0201
PLACE_NEAR=U7400.16:6mm
IN
1
R8116
NOSTUFF
6
37 13
1
20K
5%
1/20W
MF
2 201
BYPASS=U8170.6:2.3mm
PLACE_NEAR=U7501.21:7mm
5%
1/20W
MF
201
R8111
10%
6.3V
CERM-X5R 2
0201
0.47UF
D
1
1
0.1UF
C8142
1
PM_SLP_S4_L
IN
Standby Enables
NOSTUFF
54 59
10%
2 6.3V
CERM-X5R
402
61 59 50 49
36 35 30 17
46 40 38 37
65 64 62
1
D8175
SM-201
RB521ZS-30
NO STUFF
Deep Sleep (S4)
K
R8176
P5VS4RS3_EN_D
5V needs to be held up
so 1.05V can fall after 1.5V
1
240
1
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
toggle 3Hz
0
0
0
0
0
0
Battery Off (G3Hot)
0
1
1
Battery Off (G3HotAC)
5%
1/20W
MF
2 0201
R8175
0
Deep Sleep (S5AC)
Deep Sleep (S5)
1
1
0
0
0
0
0
0
PLACE_NEAR=U4600.4:6mm
PLACE_NEAR=U7501.4:15mm
2
P5VS4RS3_EN
NO STUFF
5%
1/20W
MF
201
1
PLACE_NEAR=U7501.4:15mm
C
54
OUT
C8175
2.2UF
10%
6.3V
2 X5R
402
34 29 28 18 17 16 15 13 11 8
74 64 62 60 59 58 57 42
C
PP3V3_S5
PLACE_NEAR=U7501.4:15mm
BYPASS=U8180.6:3mm
1
C8180
0.1UF
10%
6.3V
0201
S0 Rail PGOOD (BJT Version)
PP5V_S0
16 17 32 45 46 51 52 56 58 59
61 62 64
18 17 16 15 13 11 8
64 62 60 59 58 57 42 34 29 28
74
1
R8151
PM_SLP_S3_R_L
2
MC74VHC1G08
1
5%
1/20W
MF
201
2
SC70-HF
59
4
57 28
VMON_5V_DIV
1
330K
5%
1/20W
MF
2 201
C8159
10%
10V 2
X5R
402
2
5%
1/20W
MF
201
1
1UF
1%
1/20W
MF
2 201
2
Q1
59 61 62 64 65 74
30 36 38 39
8 11 12 13
15 17 18 27
40 41 42 43 44 45 56
R8154
1
R8158
15K
1K
2
65 61 13
AUD_PWR_EN
IN
ASMCC0179
1
A
100K 2
2
OUT
1K
5%
1/20W
MF
201
Q4
VMON_3V3_DIV
3.3V Divider: 1.07V
R8159
0
330
PLACE_NEAR=U7600.16:6mm
D8184
SM-201
PLACE_NEAR=U8030.2:6mm
P3V3S0_EN_D
2
R8187
20K
5%
1/20W
MF
2 201
K
PM_SLP_S3_BUF_L
OUT
PM_SLP_S3_BUF_L
OUT
1
R8186
28 57 59
28 57 59
0
5%
1/20W
MF
2 201
5%
1/20W
MF
2 0201
PLACE_NEAR=U8030.2:6mm
A
59 58
PLACE_NEAR=U8080.2:6mm
P5VS0_EN
P5VS0_EN
OUT
58 59
P3V3S0_EN
OUT
58 59
P1V05S0_EN
OUT
55 59
MAKE_BASE=TRUE
59 58
RB521ZS-30
P3V3S0_EN
MAKE_BASE=TRUE
PLACE_NEAR=U8030.2:6mm
59 55
MAKE_BASE=TRUE
1
NO STUFF
C8185
1
0.22UF
2
1
C8146
0.1UF
1
C8187
0.68UF
20%
10V
2 CERM
402
PLACE_NEAR=U7600.16:6mm
10%
25V
2 X5R
402
PLACE_NEAR=U8040.C2:7mm
C8186
0.1UF
10%
10V
2 CERM
402
10%
6.3V
2 CERM
402
PLACE_NEAR=U8030.2:6mm
PLACE_NEAR=U8080.2:6mm
B
3.3V SUS Detect
34 29 28 18 17 16 15 13 11 8
74 64 62 60 59 58 57 42
3
P1V05S0_EN
NO STUFF
PP3V3_S5
S0PGD_BJT_GND_R
5%
1/20W
MF
201
5%
1/20W
MF
201 2
VMON_Q4_BASE
Vbe 0.7V max @ 2mA
Vce(sat) 0.1V max @ 1mA
Q1 Vth 0.7~1V @Id 250uA
59 57 28
PM_SLP_S3_BUF_L
CRITICAL
R8167
5%
1/20W
MF
2 201
Thresholds:
VDD:
2.734V-3.010V
V2MON: 2.815V-3.099V
V3MON: 0.572V-0.630V
V4MON: 0.572V-0.630V
51 42 38 27 17 16 15 11 8 6
64 62 58 55
S0 Rail PGOOD Circuitry
PP3V3_S0
54
PP1V05_S0
S0PGOOD_ISL
R8170
15K
1%
1/20W
MF
2 201
S0PGOOD_ISL
1
R8161
15K
1%
1/20W
MF
2 201
8
S0PGOOD_ISL
1
R8171
15K
1%
1/20W
MF
2 201
S0PGOOD_ISL
1
10%
6.3V
CERM-X5R 2
0201
2
7
S0PGOOD_ISL
1
1.5V Divider:
0.718V @ 1.45Vmin
1.05V Divider:
0.723V @ 1.02Vmin
IN
P5VS4RS3_PGOOD
1
R8172
55
IN
U8160
1%
1/20W
MF
2 201
ISL88042IRTEZ
TDFN
P5V_DIV_VMON
P1V5_DIV_VMON
P1V05_DIV_VMON
S0PGOOD_ISL
1
15K
IN
DDRREG_PGOOD
353S2310
(IPU) 1
3 V2MON
MR*
CRITICAL
5 V3MON
6 V4MON
RST* 8
GND
R8173
53
S0PGOOD_ISL
NC
R8162
ALL_SYS_PWRGD_R
1
330
2
100
PP3V3_SUS
2 SENSE
5%
1/20W
MF
2 201
SUS_PGOOD_CT
NO STUFF
1
C8131
1000PF
2
U8130RESET*
6
PM_RSMRST_L
QFN
3 CT
GND
MR* 4
R81311
330K
OUT
5%
1/20W
MF
13 64
VFRQ Low: Fix Frequency
201 2
VFRQ High: Variable Frequency
TP_SUS_PGOOD_MR_L
THRM
PAD
Q8131
2
50
SYM_VER_2
PM_SLP_S3_R_L
S 2
SUS Enables
2
5%
1/20W
MF
201
59 42 13
IN
PM_SLP_SUS_L
PM_SLP_SUS_L
MAKE_BASE=TRUE
OUT
13 42 59
1
SYNC_MASTER=J41_MLB
Power Control
0
5%
1/20W
MF
2 0201
OUT
P3V3SUS_EN
59 58
16 17 37 59
DRAWING NUMBER
P3V3SUS_EN
MAKE_BASE=TRUE
NO STUFF
1
4
Apple Inc.
OUT
58 59
C8190
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
0.1UF
5
SYNC_DATE=02/06/2013
PAGE TITLE
R8190
5%
1/20W
MF
201
ALL_SYS_PWRGD
OUT
DFN1006H4-3
R8164
100
CHGR_VFRQ
D 3
DMN32D2LFB4
10%
25V
2 X5R
402
6
PP3V42_G3H
10%
2 16V
X7R-CERM
0201
1%
1/20W
MF
2 201
7
50 49 46 40 38 37 36 35 30 17
65 64 62 61 59
TPS3808G33
5%
1/20W
MF
201
THRM_PAD
100K
1 G
1
1
R8133
59
R8168
S0PGOOD_ISL
100
5%
1/20W
MF
201
2
P1V05S0_PGOOD
VDD
6.04K
100
5%
1/20W
MF
201
9
1%
1/20W
MF
2 201
1
0.1UF
4
6.04K
5V Divider:
3.19V @ 4.5Vmin
P1V8S3_PGOOD
C8160 1
PP5V_S0
R8160
IN
R8165
PP1V5_S0
S0PGOOD_ISL
1
R8166
(ISL version used for development)
74 65 64 62 61 59
36 30 27 18 17 15 13 12 11 8
56 45 44 43 42 41 40 39 38
64 62 59 58 57 46 18 14 11 8
CHGR VFRQ Generation
8 11 14 18 46 57 58 59 62 64
1
10%
6.3V
CERM-X5R 2
0201
VDD
1
10K
0.1UF
7
2
PP3V3_SUS
C8130 1
1
PP1V5_S0
1K
100
5
64 62 59 58 57 8
1
BYPASS=U8130.6:2.3mm
No stuff C8131, 12ms
Min delay time
U8130 Sense input
threhold is 3.07V
R81571
R8155
A
1
R8184
58
1
59
51
17
45
56
62
820
R8146
P1V5CODEC_EN_D 1
RB521ZS-30
PLACE_NEAR=U8040.2:C7mm
1%
1/20W
MF
2 201
1
1
5%
1/20W
MF
201
P1V5S0SW_AUDIO_EN
376S0854
Q3
7.15K
R8138
R8185
PLACE_NEAR=U7600.16:6mm
5%
1/20W
MF
201
D8146
SM-201
DFN2015H4-8
1
PLACE_NEAR=U7600.16:6mm
NO STUFF
1.5V Codec Enable
K
VMON_Q3_BASE
NC
Q2
7
5%
1/20W
MF
2 0201
P1V05_EN_D
R8145
Q8150
8
NC
5%
1/20W
MF
201
5
K
D8185
SM-201
1
PLACE_NEAR=U8040.2:C7mm
9ms RC delay
1
16 17 37 59
CRITICAL
VMON_Q2_BASE
PP3V3_S0
ALL_SYS_PWRGD
S0PGD_C
6
15K
1K
NO STUFF
RB521ZS-30
R8180
3
4
1%
1/20W
MF
201
A
1
150K
R8152
64 62 59 58 57 8
64
58
46
16
32
52
61
PM_SLP_S3_BUF_L
MAKE_BASE=TRUE
NOSTUFF
U8180
R8156
R8153
1
1%
1/20W
MF
2 201
100
1
5
1
5.0V Divider: 1.07V
B
PM_SLP_S3_L
IN
PP3V3_S5
54.9K
1%
1/20W
MF
2 201
37 18 17 13
S0 Enables
2 CERM-X5R
R8178
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
81 OF 121
SHEET
59 OF 76
1
A
8
7
6
5
4
3
2
1
D
D
LCD Connector
1
R8363
4.7K
1
R8364
Internal DP Connector: 518S0829
4.7K
5%
1/20W
MF
2 201
5%
1/20W
MF
2 201
CRITICAL
J8300
20525-130E-01
R8361
73 40 37
BI
0
1
SMBUS_SMC_0_S0_SDA
2
64
Pull-ups on panel side,
4.7 kOhm to 3.3V
I2C_TCON_SDA_R
64 62 56
F-RT-SM
31
PPHV_S0SW_LCDBKLT
1
5%
1/20W
MF
0201
NC
0
1
SMBUS_SMC_0_S0_SCL
2
64 56
64
64 56
C
U8300
PP3V3_S5
64 56
13
OUT
DP_INT_HPD
IN
L8304
MFET-2X2-8IN
1 ON
EDP_PANEL_PWR
FERR-120-OHM-1.5A
2 VIN_1
3 VIN_2
PP3V3_S0SW_LCD
1
VOUT_2 5
GND
1
PP3V3_S0SW_LCD_R
VOUT_1 4
Sense resistor on
43
43
sensor page
C8309
0.1UF
10%
6.3V
2 CERM-X5R
0201
6
THRM
PAD
7
OUT
OUT
9
C8311
0.1UF
10%
6.3V
CERM-X5R 2
0201
C8312
67 5
10UF
BI
20%
2 6.3V
X5R
603
67 5
BI
DP_INT_AUXCH_C_P
1
2
10%
16V
X5R-CERM
0201
0.1UF
67 5
IN
DP_INT_ML_C_P & lt; 0 & gt;
IN
DP_INT_ML_C_N & lt; 0 & gt;
B
1
DP_INT_HPD_CONN
13
14
DisplayPort I/F
17
64
PP3V3_S0SW_LCD_UF
18
MIN_LINE_WIDTH=0.30 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=3.3V
1
67 64
10%
16V
X7R-CERM 2
0201
67 64
19
20
DP_INT_AUX_CH_C_N
DP_INT_AUX_CH_C_P
21
22
23
C8325
67 64
0.1UF
DP_INT_ML_P & lt; 0 & gt;
DP_INT_ML_N & lt; 0 & gt;
24
25
26
2
(DP_INT_AUX_CH_C_P)
NC
NC
10%
16V
X5R-CERM
0201
PLACE_NEAR=J8300.24:1mm
PLACE_NEAR=J8300.25:1mm
R83181 R83171
1M
C8321
5%
1/20W
MF
2012
0.1UF
1
12
16
2
10%
16V
X5R-CERM
0201
C
11
15
67 64
1
C8320
67 5
(DP_INT_AUX_CH_C_N)
LED Backlight I/F
10
5%
1/20W
MF
0201
1000PF
0.1UF
DP_INT_AUXCH_C_N
64
0402-LF
C8324
1
2
6
8
NC
2
C8315
1
0
1
FPF1009
13
OUT
5
7
R8360
CRITICAL
34 29 28 18 17 16 15 13 11 8
74 64 62 59 58 57 42
OUT
64 56
5%
1/20W
MF
0201
OUT
64 56
I2C_TCON_SCL_R
NC
LED_RETURN_6
LED_RETURN_5
LED_RETURN_4
LED_RETURN_3
LED_RETURN_2
LED_RETURN_1
OUT
64 56
IN
3
4
R8362
73 40 37
2
2
27
28
29
30
33
1M
5%
1/20W
MF
2012
34
35
B
36
10%
16V
X5R-CERM
0201
37
38
39
40
41
PLACE_NEAR=J8300.14:2mm
R83501
100K
5%
1/20W
MF
201 2
A
1
R8380
1M
5%
1/20W
MF
2 201
32
1
R8370
1M
PLACE_NEAR=J8300.3:2mm
1
C8317
5%
1/20W
MF
2 201
1000PF
5%
50V
C0G-CERM 2
603
SYNC_MASTER=J41_MLB
SYNC_DATE=02/06/2013
PAGE TITLE
Internal DisplayPort Connector
DRAWING NUMBER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
83 OF 121
SHEET
60 OF 76
1
A
8
7
6
5
4
3
2
1
D
D
PP3V3_S0
74 65 64 62
36 30 27 18 17 15 13 12 11 8
59 56 45 44 43 42 41 40 39 38
50 49 46 40 38 37 36 35 30 17
65 64 62 59
PP3V42_G3H
CRITICAL
J9500
ON MLB SIDE AS LIO CAN’T FIT CAPS
DF40CG3.0-48DS-0.4V
F-ST-SM
49
50
C9521
GND_VOID=TRUE
(Right Speaker Enable)
50 38 37
65
IN
65 39
65 58
C
SMC_BC_ACOK
USB_PWR_EN
FINSTACKSNS_ALERT_L
IN
65 59 35
1
3
5
7
9
11
13
15
OUT
PP1V5_S0SW_AUDIO
73 65 40 37
SMBUS_SMC_2_S3_SDA
SMBUS_SMC_2_S3_SCL
BI
73 65 40 37
BI
2
4
6
8
10
12
14
16
1
68 65
GND_VOID=TRUE
GND_VOID=TRUE
65 16 14
OUT
69 65 12
IN
65 64 38 37 36
IN
65 47
69 65 12
OUT
IN
69 65 12
69 65 12
PLACE_NEAR=J9500.7:1.5mm
IN
IN
69 65 12
IN
C9520 1
0.1UF
HDA_SDIN0
HDA_BIT_CLK
HDA_SDOUT
NOSTUFF
1
C9510 1
10PF
10%
16V
X5R-CERM
0201
1
0.1UF
5%
50V
C0G-CERM
0402
2
36
38
40
42
44
46
48
51
HDA_SYNC
20
22
24
26
28
30
32
35
37
39
41
43
45
47
XDP_USB_EXTB_OC_L
HDA_RST_L
SMC_LID
SPKRAMP_SHDN_L
C9550
10%
16V
X5R-CERM 2
0201
19
21
23
25
27
29
31
SYS_ONEWIRE
BI
SPKRAMP_INR_N
SPKRAMP_INR_P
OUT
GND_VOID=TRUE
47 65 74
IN
47 65 74
CRITICAL
2
D9520
2
2
14 65 68
52
NOSTUFF
PP5V_S0_ALT_AUD_LDO_EN
MIN_LINE_WIDTH=0.1
AUD_PWR_EN
IN 13 59 MIN_NECK_WIDTH=0.1
65
VOLTAGE=5V
2
mm
mm
0
OUT
C
14 65 68
0.1UF
D9521
ESD0P2RF-02LS
TSSLP-2-1
1
1
GND_VOID=TRUE
R9510
0
1
1
2
1/20W5% MF
0201
5%
1/20W
MF
0201
NOSTUFF
GND_VOID=TRUE
USB_EXTB_P
USB_EXTB_N
BI
14 65 68
BI
14 65 68
PP5V_S0
16 17 32 45 46 51 52 56 58 59
62 64
68 65
GND_VOID=TRUE
GND_VOID=TRUE
USB3_EXTB_D2R_RC_N
68 65
GND_VOID=TRUE
CRITICAL
D9510
ESD0P2RF-02LS
10%
16V
X5R-CERM
0201
516S1036
USB3_EXTB_D2R_RC_P
2
25V
1
5%
0201
2
NP0-CERM
D9511
ESD0P2RF-02LS
TSSLP-2-1
USB3_EXTB_D2R_N
IN
14 65 68
IN
14 65 68
NOSTUFF
GND_VOID=TRUE
5%
1
25V
CRITICAL
1
TSSLP-2-1
C9531
15PF
C9532
15PF
GND_VOID=TRUE
2
1
C9500
PLACE_NEAR=J9500.21:1.5mm
PLACE_NEAR=J9500.9:1.5mm
B
OUT
X5R-CERM
10%
16V
0201
CRITICAL
R9501
0.1UF
2
C9522
1
2 USB3_EXTB_R2D_C_P
USB3_EXTB_R2D_P
GND_VOID=TRUE
TSSLP-2-1
65
USB3_EXTB_R2D_C_N
GND_VOID=TRUE
68 65
ESD0P2RF-02LS
65 37
USB3_EXTB_R2D_N
2
X5R-CERM
10%
0201
16V 0.1UF
2
NP0-CERM
0201
USB3_EXTB_D2R_P
GND_VOID=TRUE
R9520
0
1
B
2
1/20W5% MF
0201
IO Ports
A
SYNC_MASTER=CLEAN_J43
SYNC_DATE=11/13/2012
PAGE TITLE
Left I/O (LIO) Connector
DRAWING NUMBER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
95 OF 121
SHEET
61 OF 76
1
A
8
7
6
" G3Hot " (Always-Present) Rails
64 62
42 41 27
56 50 49
PPBUS_G3H
PPBUS_G3H
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=8.6V
MAKE_BASE=TRUE
PPBUS_G3H
PPBUS_G3H
PPBUS_G3H
PPBUS_G3H
PPBUS_G3H
64
52 51 41
62 55 53
PPBUS_S5_HS_COMPUTING_ISNS
PP3V3_S5
PP3V3_S5
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
27 41 42 49 50 56 62 64
27 41 42 49 50 56 62 64
27 41 42 49 50 56 62 64
27 41 42 49 50 56 62 64
PPBUS_S5_HS_COMPUTING_ISNS
PPBUS_S5_HS_COMPUTING_ISNS
PPBUS_S5_HS_COMPUTING_ISNS
PPBUS_S5_HS_OTHER_ISNS
PPBUS_S5_HS_OTHER_ISNS
41 51 52 53 55 62 64
50 49 42
64 62
PPDCIN_G3H_ISOL
PPDCIN_G3H_ISOL
PPDCIN_G3H
PPDCIN_G3H
PP3V42_G3H
PP3V42_G3H
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.42V
MAKE_BASE=TRUE
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
PP3V42_G3H
C
13 12 8
64 62 17
PPVRTC_G3H
41 54 62 64
41 54 62 64
42 49 50 62 64
42 49 50 62 64
64 62 58 39 38 36 33 29
42 49 50 62 64
PP3V3_S4
PPVRTC_G3H
PP5V_S5
PP5V_S5
B
55 54 49 47 35 32
64 62 58
PP5V_S4RS3
PP3V3_SUS
64 62 59 58 57 46 18 14 11 8
17 30 35 36 37 38 40 46 49 50
59 61 62 64 65
64
51 46 45 32 17 16
62 61 59 58 56 52
17
59
17
59
17
59
17
59
30
61
30
61
30
61
30
61
35
62
35
62
35
62
35
62
36
64
36
64
36
64
36
64
37
65
37
65
37
65
37
65
38 40 46 49 50
38 40 46 49 50
38 40 46 49 50
17 30 35 36 37 38 40 46 49 50
59 61 62 64 65
17 30 35 36 37 38 40 46 49 50
59 61 62 64 65
17 30 35 36 37 38 40 46
49 50 59 61 62 64 65
17
59
17
59
17
59
30
61
30
61
30
61
35
62
35
62
35
62
36
64
36
64
36
64
A
8
17 30 35 36 37 38 40 46 49 50
59 61 62 64 65
17 30 35 36 37 38 40 46 49 50
59 61 62 64 65
8 12 13 17 62 64
MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
D
25 26 27 28 62
VOLTAGE=3.3V
MAKE_BASE=TRUE
PP3V3_S4_TBTAPWR
25 26 27 28 62
TBT Rails (off when no cable)
1.8V/1.5V/1.2V/1.05V Rails
PP1V8_S3
8 11 13 15 16 17 18 28 29 34 42
57 58 59 60 62 64 74
8 11 13 15 16 17 18 28 29 34 42
57 58 59 60 62 64 74
8 11 13 15 16 17 18 28 29 34 42
57 58 59 60 62 64 74
20 21 22 23 57 62
64 62 28 27
PP15V_TBT
PP15V_TBT
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.2V
MAKE_BASE=TRUE
PP15V_TBT
PP1V8_S3
PP1V2_S3
20 21 22 23 57 62
64 62 27 26 25 17 15
PP3V3_TBTLC
PP3V3_TBTLC
PP1V2_S3
17 19 20 21 22 23 42 53 62 70
PP3V3_TBTLC
PP3V3_TBTLC
PP3V3_TBTLC
29 33 36 38 39 58 62 64
29 33 36 38 39 58 62 64
PP1V2_S3
PP1V2_S3
PP1V2_S3
8 11 14 18 46 57 58 59 62 64
17 19 20 21 22 23 42 53 62 70 26
64 62 27
8 11 14 18 46 57 58 59 62 64
15
62
15
62
PP1V05_TBTLC
PP1V05_TBTLC
17 25 26 27
64
17 25 26 27
64
26 27 62 64
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE
17 19 20 21 22 23 42 53 62 70
PP1V2_S3
PP1V2_S3
PP1V2_S3
PP1V2_S3
8 11 14 18 46 57 58 59 62 64
15 17 25 26 27
62 64
17 19 20 21 22 23 42 53 62 70
VOLTAGE=3.3V
MAKE_BASE=TRUE
8 11 14 18 46 57 58 59 62 64
15 17 25 26 27
62 64
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.1 MM
VOLTAGE=1.2V
MAKE_BASE=TRUE
29 33 36 38 39 58 62 64
27 28 62 64
20 21 22 23 57 62
PP1V8_S3
8 11 13 15 16 17 18 28 29 34 42
57 58 59 60 62 64 74
PP3V3_SUS
27 28 62 64
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=17.8V
MAKE_BASE=TRUE
29 33 36 38 39 58 62 64
70 62 53 42 23 22 21 20 19 17
29 33 36 38 39 58 62 64
56 60 62 64
30 41 62 64
PP3V3_S4_TBTAPWR
PP1V05_TBTLC
26 27 62 64
PP1V05_TBTCIO
17 19 20 21 22 23 42 53 62 70
26 27 62 64
17 19 20 21 22 23 42 53 62 70
17 19 20 21 22 23 42 53 62 70 26
64 62 27
PP1V05_TBTCIO
8 11 14 18 46 57 58 59 62 64
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE
8 11 14 18 46 57 58 59 62 64
PP1V05_TBTCIO
8 11 14 18 46 57 58 59 62 64
17 19 20 21 22 23 42 53 62 70
C
26 27 62 64
8 11 14 18 46 57 58 59 62 64
8 11 14 18 46 57 58 59 62 64
64 27
PP3V3_S0
15 18 19 33 36 40 41
58 62 64
PP1V05_SUS
62 57 16
PP1V05_SUS
15 18 19 33 36 40 41 58 62 64
32 35 47 49 54 55 58 62 64
16 17 32 45 46 51 52 56 58 59
61 62 64
16 17 32 45 46 51 52 56 58 59
61 62 64
16 17 32 45 46 51 52 56 58 59
61 62 64
16 17 32 45 46 51 52 56 58 59
61 62 64
16 17 32 45 46 51 52 56 58 59
61 62 64
16 17 32
62 58 43 42 41
45 46 51 52 56 58 59 61 62 64
PP3V3_S4SW_SNS
16 17 32 45 46 51 52 56 58 59
61 62 64
15 18 19 33 36 40 41 58 62 64
VOLTAGE=3.3V
MAKE_BASE=TRUE
16 17 32 45 46 51 52 56 58 59
61 62 64
16 17 32 45 46 51 52 56 58 59
61 62 64
16 17 32 45 46 51 52 56 58 59
61 62 64
6
64 62 52 42 10 8
PP1V5_S0
PP1V5_S0
62 64 65 74
8 11 12 13 15 17 18 27 30 36 38
39 40 41 42 43 44 45 56 59 61
62 64 65 74
8 11 12 13 15 17 18 27 30 36 38
39 40 41 42 43 44 45 56 59 61
62
8 11 12 13 15 17 18 27 30 36 38
39 40 41 42 43 44 45 56 59 61
64 65 74
8
38 39 40 41 42 43 44 45
64 11 12 13 15 17 18 27 30 36
39 56 59 61 62 64 65 74
8
11 12 13 15 17 18 27 30 36 38
40 41 42 43 44 45 56 59 61 62
65 74
62 64 65 74
8 11 12 13 15 17 18 27 30 36 38
39 40 41 42 43 44 45 56 59 61
PPVCC_S0_CPU
PPVCC_S0_CPU
PP0V6_S0_DDRVTT
8 10 42 52
62 64
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=1.8V
MAKE_BASE=TRUE
PPVCC_S0_CPU
PPVCC_S0_CPU
8 57 58 59 62 64
8 10 42 52
62 64
8 10 42 52
62 64
8 57 58 59 62 64
PP1V5_S0
8 11 12 13 15 17 18 27 30 36
38 39 40 41 42 43
62 53 24
44 45 56 59 61 62
64 65 74
62 64 65 74
8 11 12 13 15 17 18 27 30 36 38
39 40 41 42 43 44 45 56 59 61
62
8 11 12 13 15 17 18 27 30 36 38
39 40 41 42 43 44 45 56 59 61
64 65 74
8
38 39 40 41 42 43 44 45
11 12 13 15 17 18 27 30 36
56 59 61 62 64 65 74
8 57 58 59 62 64
PP0V6_S0_DDRVTT
24 53 62
B
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.17 mm
VOLTAGE=0.75V
MAKE_BASE=TRUE
PP0V6_S0_DDRVTT
PP0V6_S0_DDRVTT
24 53 62
24 53 62
45 56 59 61 62 64 65 74
8 11 12 13 15 17 18 27 30 36 38
39 40 41 42 43 44
62 64 65 74
8 11 12 13 15 17 18 27 30 36 38
39 40 41 42 43 44 45 56 59 61
51 42 38 27 17 16 15 11 8 6
64 62 59 58 55
PP1V05_S0
PP1V05_S0
6 8 11 15 16 17 27 38 42 51 55
58 59 62 64
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.175 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE
? mA
62 64 65 74
8 11 12 13 15 17 18 27 30 36 38
39 40 41 42 43 44 45 56 59 61
62
8 11 12 13 15 17 18 27 30 36 38
39 40 41 42 43 44 45 56 59 61
64 65 74
8
38 39 40 41 42 43 44 45
64 11 12 13 15 17 18 27 30 36
39 56 59 61 62 64 65 74
8
11 12 13 15 17 18 27 30 36 38
40 41 42 43 44 45 56 59 61 62
65 74
62 64 65 74
8 11 12 13 15 17 18 27 30 36 38
39 40 41 42 43 44 45 56 59 61
62
8 11 12 13 15 17 18 27 30 36 38
39 40 41 42 43 44 45 56 59 61
64 65 74
8
38 39 40 41 42 43 44 45
64 11 12 13 15 17 18 27 30 36
39 56 59 61 62 64 65 74
8
11 12 13 15 17 18 27 30 36 38
40 41 42 43 44 45 56 59 61 62
65 74
62 64 65 74
8 11 12 13 15 17 18 27 30 36 38
39 40 41 42 43 44 45 56 59 61
62
8 11 12 13 15 17 18 27 30 36 38
39 40 41 42 43 44 45 56 59 61
64 65 74
8
38 39 40 41 42 43 44 45
11 12 13 15 17 18 27 30 36
56 59 61 62 64 65 74
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
PP1V05_S0
41 42 43 58 62
VOLTAGE=3.3V
MAKE_BASE=TRUE
PP3V3_S4SW_SNS
PP3V3_S4SW_SNS
PP3V3_S4SW_SNS
PP3V3_S4SW_SNS
PP3V3_S4SW_SNS
PP3V3_S4SW_SNS
PP3V3_S4SW_SNS
PP3V3_S4SW_SNS
PP3V3_S4SW_SNS
PP3V3_S4SW_SNS
PP3V3_S4SW_SNS
PP3V3_S4SW_SNS
PP3V3_S4SW_SNS
PP3V3_S4SW_SNS
16 17 32 45 46 51 52 56 58 59
61 62 64
16 17 32 45 46 51 52 56 58 59
61 62 64
8 57 58 59 62 64
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.17 mm
VOLTAGE=1.5V
MAKE_BASE=TRUE
15 18 19 33 36 40 41 58 62 64
PP3V3_S4SW_SNS
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
16 57 62
PP1V5_S0
PP1V5_S0
15 18 19 33
64 62 59 58 57 8
36 40 41 58 62 64
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
32 35 47 49 54 55 58 62 64
CPU " VCORE " RAILS
PP1V05_SUS
15 18 19 33 36 40 41 58 62 64
15 18 19 33 36 40 41 58 62 64
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
PP3V3_S0
32 35 47 49 54 55 58 62 64
16 57 62
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE
15 18 19 33 36 40 41 58 62 64
PP3V3_S0
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.20MM
PPVIN_S4SW_TBTBST_FET
VOLTAGE=8.6V
15 18 19 33 36 40 41 58 62 64
VOLTAGE=3.3V
MAKE_BASE=TRUE
8 12 13 17 62 64
32 35 47 49 54 55 58 62 64
7
PP3V3_S4_TBTAPWR
2A max supply
VOLTAGE=3.3V
MAKE_BASE=TRUE
56 60 62 64
PPHV_S0SW_LCDBKLT
PP3V3_S0SW_SSD
PP1V8_S3
PP3V3_S3
PP3V3_S3
PP3V3_S3
PP3V3_S3
PP3V3_S3
PP3V3_S3
PP3V3_S3
PP3V3_S3
32 35 47 49 54 55 58 62 64
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PP5V_S0
PPHV_S0SW_LCDBKLT
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.375 MM
VOLTAGE=50V
MAKE_BASE=TRUE
30 41 62 64
VOLTAGE=3.3V
MAKE_BASE=TRUE
29 34 42
62 57 23 22 21 20
8 11 13 15 16 17 18 28 29 34 42
57 58 59 60 62 64 74
8 11 13 15 16 17 18 28 29 34 42
57 58 59 60 62 64 74
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
32 35 47 49 54 55 58 62 64
PP5V_S0
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.20MM
8 11 13 15 16 17 18 28 29 34 42
57 58 59 60 62 64 74
8 11 13 15 16 17 18 28 29 34 42
57 58 59 60 62 64 74
PP3V3_S3
PP3V3_S3
37 38 40 46 49 50
65
37 38 40 46 49 50
65
37 38 40 46 49 50
65
32 35 47 49 54 55 58 62 64
PP5V_S0
PP3V3_S0SW_SSD
PPHV_S0SW_LCDBKLT
17 30 35 36 37 38 40 46 49 50
59 61 62 64 65
36 53 54 62
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V
MAKE_BASE=TRUE
PP3V3_S0SW_SSD
8 11 13 15 16 17 18 28 29 34 42
57 58 59 60 62 64 74
8 11 13 15 16 17 18 28 29 34 42
57 58 59 60 62 64 74
8 11 13 15 16 17 18 28 29 34 42
57 58 59 60 62 64 74
PP3V3_SUS
PP3V3_SUS
PP3V3_SUS
PP3V3_SUS
PP3V3_SUS
PP3V3_SUS
PP3V3_SUS
PP3V3_SUS
38 40 46 49 50
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.175 MM
VOLTAGE=5V
MAKE_BASE=TRUE
PP5V_S0
29 34 42
62 41 30
29 34 42
8 11 13 15 16 17 18 28 29 34 42
57 58 59 60 62 64 74
8 11 13 15 16 17 18 28 29 34 42
57 58 59 60 62 64 74
8 11 13 15 16 17 18 28 29 34
42 57 58 59 60 62 64 74
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
36 53 54 62
PP5V_S4RS3
PP5V_S4RS3
PP5V_S4RS3
PP5V_S4RS3
PP5V_S4RS3
PP5V_S4RS3
1
LCDBKLT Rail
64 62 60 56
49 50 62 64
36 53 54 62
PP5V_S4RS3
2
8 11 13 15 16 17 18 28 29 34 42
57 58 59 60 62 64 74
8 11 13 15 16 17 18 28
57 58 59 60 62 64 74 64
8 11 13 15 16 17 18 28
57 58 59 60 62 64 74
8 11 13 15 16 17 18 28
57 58 59 60 62 64 74
PP3V3_S4
PP3V3_S4
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=5V
MAKE_BASE=TRUE
PP5V_S5
PP5V_S5
3
8 11 13 15 16 17 18 28 29 34 42
57 58 59 60 62 64 74
8 11 13 15 16 17 18 28 29 34 42
57 58 59 60 62 64 74
PP3V3_S4
PP3V3_S4
49 50 62 64
74 65 64 62 61
36 30 27 18 17 15 13 12 11 8
59 56 45 44 43 42 41 40 39 38
5V Rails
4
8 11 13 15 16 17 18 28 29 34 42
57 58 59 60 62 64 74
8 11 13 15 16 17 18 28 29 34 42
57 58 59 60 62 64 74
PP3V3_S4
MIN_LINE_WIDTH=0.60MM
MIN_NECK_WIDTH=0.20MM
MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3V
MAKE_BASE=TRUE
PPVRTC_G3H
62 54 53 36
41 51 52 53 55 62 64
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=18.5V
MAKE_BASE=TRUE
PPDCIN_G3H
65 64 62
49 46 40
35 30 17
38 37 36
61 59 50
41 51 52 53 55 62 64
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=18.5V
MAKE_BASE=TRUE
PPDCIN_G3H_ISOL
PPDCIN_G3H_ISOL
62 50 49
64
41 51 52 53 55 62 64
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=8.6V
MAKE_BASE=TRUE
PPBUS_S5_HS_OTHER_ISNS
VOLTAGE=3.3V
MAKE_BASE=TRUE
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
PP3V3_S5
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=8.6V
MAKE_BASE=TRUE
D
62 54 41
64
27 41 42 49 50 56 62 64
34 29 28 18 17 16 15 13 11 8
74 64 62 60 59 58 57 42
27 41 42 49 50 56 62 64
PPBUS_S5_HS_COMPUTING_ISNS
5
3.3V Rails
6 8 11 15 16 17 27 38 42 51 55
58 59 62 64
6 8 11 15 16 17 27 38 42 51 55
58 59 62 64
6 8 11 15 16 17 27 38 42 51 55
58 59 62 64
6 8 11 15 16 17 27 38 42 51 55
58 59 62 64
6 8 11 15 16 17 27 38 42 51 55
58 59 62 64
6 8 11 15 16 17 27 38 42 51 55
58 59 62 64
6 8 11 15 16 17 27 38 42 51 55
58 59 62 64
6 8 11 15 16 17 27 38 42 51 55
58 59 62 64
6 8 11 15 16 17 27 38 42 51 55
58 59 62 64
6 8 11 15 16 17 27 38 42 51 55
58 59 62 64
VOLTAGE=0V
MIN_NECK_WIDTH=0.075MM
MIN_LINE_WIDTH=0.6MM
6 8 11 15 16 17 27 38 42 51 55
58 59 62 64
6 8 11 15 16 17 27 38 42 51 55
58 59 62 64
41 42 43 58 62
SYNC_MASTER=J41_MLB
SYNC_DATE=01/30/2013
PAGE TITLE
41 42 43 58 62
41 42 43 58 62
62 58 11 8
PP1V05_S0SW_PCH_HSIO
PP1V05_S0SW_PCH_HSIO
Power Aliases
8 11 58 62
DRAWING NUMBER
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE
1.84A
41 42 43 58 62
41 42 43 58 62
Apple Inc.
PP1V05_S0SW_PCH_HSIO
PP1V05_S0SW_PCH_HSIO
41 42 43 58 62
8 11 58 62
8 11 58 62
41 42 43 58 62
41 42 43 58 62
41 42 43 58 62
41 42 43 58 62
41 42 43 58 62
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
41 42 43 58 62
5
GND
6 8 11 15 16 17 27 38 42 51 55
58 59 62 64
41 42 43 58 62
41 42 43 58 62
Digital Ground
6 8 11 15 16 17 27 38 42 51 55
58 59 62 64
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
100 OF 121
SHEET
62 OF 76
1
A
8
7
6
5
4
3
2
1
Memory Bit/Byte Swizzle
LPDDR3 Command/Address
7
7
7
7
D
7
7
70 63 24 20 7
7
7
7
7
7
7
7
7
7
70 63 24 21 7
7
7
7
70 63 24 21 20 7
63 7
63 7
=MEM_A_A & lt; 5 & gt;
=MEM_A_A & lt; 9 & gt;
=MEM_A_A & lt; 6 & gt;
=MEM_A_A & lt; 8 & gt;
=MEM_A_A & lt; 7 & gt;
=MEM_A_BA & lt; 2 & gt;
MEM_A_CAA & lt; 6 & gt;
=MEM_A_A & lt; 11 & gt;
=MEM_A_A & lt; 15 & gt;
=MEM_A_A & lt; 14 & gt;
MAKE_BASE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
MEM_A_CAA & lt; 0 & gt;
MEM_A_CAA & lt; 1 & gt;
MEM_A_CAA & lt; 2 & gt;
MEM_A_CAA & lt; 3 & gt;
MEM_A_CAA & lt; 4 & gt;
MEM_A_CAA & lt; 5 & gt;
MEM_A_CAA & lt; 6 & gt;
MEM_A_CAA & lt; 7 & gt;
MEM_A_CAA & lt; 8 & gt;
MEM_A_CAA & lt; 9 & gt;
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
MEM_A_CAB & lt; 0 & gt;
MEM_A_CAB & lt; 1 & gt;
MEM_A_CAB & lt; 2 & gt;
MEM_A_CAB & lt; 3 & gt;
MEM_A_CAB & lt; 4 & gt;
MEM_A_CAB & lt; 5 & gt;
MEM_A_CAB & lt; 6 & gt;
MEM_A_CAB & lt; 7 & gt;
MEM_A_CAB & lt; 8 & gt;
MEM_A_CAB & lt; 9 & gt;
MEM_A_ODT & lt; 0 & gt;
TP_LPDDR3_RSVD1
TP_LPDDR3_RSVD2
=MEM_B_A & lt; 5 & gt;
=MEM_B_A & lt; 9 & gt;
=MEM_B_A & lt; 6 & gt;
=MEM_B_A & lt; 8 & gt;
=MEM_B_A & lt; 7 & gt;
=MEM_B_BA & lt; 2 & gt;
MEM_B_CAA & lt; 6 & gt;
=MEM_B_A & lt; 11 & gt;
=MEM_B_A & lt; 15 & gt;
=MEM_B_A & lt; 14 & gt;
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
MEM_B_CAA & lt; 0 & gt;
MEM_B_CAA & lt; 1 & gt;
MEM_B_CAA & lt; 2 & gt;
MEM_B_CAA & lt; 3 & gt;
MEM_B_CAA & lt; 4 & gt;
MEM_B_CAA & lt; 5 & gt;
MEM_B_CAA & lt; 6 & gt;
MEM_B_CAA & lt; 7 & gt;
MEM_B_CAA & lt; 8 & gt;
MEM_B_CAA & lt; 9 & gt;
=MEM_B_A & lt; 13 & gt;
=MEM_B_CAS_L
=MEM_B_WE_L
=MEM_B_RAS_L
=MEM_B_BA & lt; 0 & gt;
=MEM_B_A & lt; 2 & gt;
MEM_B_CAB & lt; 6 & gt;
=MEM_B_A & lt; 10 & gt;
=MEM_B_A & lt; 1 & gt;
=MEM_B_A & lt; 0 & gt;
MEM_B_ODT & lt; 0 & gt;
TP_LPDDR3_RSVD3
TP_LPDDR3_RSVD4
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
MEM_B_CAB & lt; 0 & gt;
MEM_B_CAB & lt; 1 & gt;
MEM_B_CAB & lt; 2 & gt;
MEM_B_CAB & lt; 3 & gt;
MEM_B_CAB & lt; 4 & gt;
MEM_B_CAB & lt; 5 & gt;
MEM_B_CAB & lt; 6 & gt;
MEM_B_CAB & lt; 7 & gt;
MEM_B_CAB & lt; 8 & gt;
MEM_B_CAB & lt; 9 & gt;
MEM_B_ODT & lt; 0 & gt;
TP_LPDDR3_RSVD3
TP_LPDDR3_RSVD4
=MEM_A_A & lt; 13 & gt;
=MEM_A_CAS_L
=MEM_A_WE_L
=MEM_A_RAS_L
=MEM_A_BA & lt; 0 & gt;
=MEM_A_A & lt; 2 & gt;
MEM_A_CAB & lt; 6 & gt;
=MEM_A_A & lt; 10 & gt;
=MEM_A_A & lt; 1 & gt;
=MEM_A_A & lt; 0 & gt;
MEM_A_ODT & lt; 0 & gt;
TP_LPDDR3_RSVD1
TP_LPDDR3_RSVD2
20 24 70
20
20 24 70
20
20 24 70
20
20 24 70
20
20 24 70
20
20 24 70
20
7 20 24 63 70
20
20 24 70
20
20 24 70
20
20 24 70
20
20
21 24 70
20
21 24 70
20
21 24 70
20
21 24 70
20
21 24 70
20
21 24 70
20
7 21 24 63 70
20
21 24 70
20
21 24 70
20
21 24 70
20
7 20 21 24 63 70
20
7 63
20
7 63
20
7
7
7
7
7
7
C
70 63 24 22 7
7
7
7
7
7
7
7
7
7
70 63 24 23 7
7
7
7
70 63 24 23 22 7
63 7
63 7
22 24 70
20
22 24 70
20
22 24 70
20
22 24 70
20
22 24 70
20
22 24 70
20
7 22 24 63 70
20
22 24 70
20
22 24 70
21
22 24 70
21
21
23 24 70
21
23 24 70
21
23 24 70
21
23 24 70
21
23 24 70
21
23 24 70
21
7 23 24 63 70
21
23 24 70
21
23 24 70
21
23 24 70
70 63 21 7
7 22 23 24 63 70
21
7 63
21
7 63
21
21
21
21
21
21
21
21
21
21
B
21
21
21
21
21
21
21
20
20
20
20
20
20
20
20
21
21
21
21
70 63 21 7
70 63 21 7
21
21
=MEM_A_DQ & lt; 0 & gt;
=MEM_A_DQ & lt; 1 & gt;
=MEM_A_DQ & lt; 2 & gt;
=MEM_A_DQ & lt; 3 & gt;
=MEM_A_DQ & lt; 4 & gt;
=MEM_A_DQ & lt; 5 & gt;
=MEM_A_DQ & lt; 6 & gt;
=MEM_A_DQ & lt; 7 & gt;
=MEM_A_DQ & lt; 8 & gt;
=MEM_A_DQ & lt; 9 & gt;
=MEM_A_DQ & lt; 10 & gt;
=MEM_A_DQ & lt; 11 & gt;
=MEM_A_DQ & lt; 12 & gt;
=MEM_A_DQ & lt; 13 & gt;
=MEM_A_DQ & lt; 14 & gt;
=MEM_A_DQ & lt; 15 & gt;
=MEM_A_DQ & lt; 16 & gt;
=MEM_A_DQ & lt; 17 & gt;
=MEM_A_DQ & lt; 18 & gt;
=MEM_A_DQ & lt; 19 & gt;
=MEM_A_DQ & lt; 20 & gt;
=MEM_A_DQ & lt; 21 & gt;
=MEM_A_DQ & lt; 22 & gt;
=MEM_A_DQ & lt; 23 & gt;
=MEM_A_DQ & lt; 24 & gt;
=MEM_A_DQ & lt; 25 & gt;
=MEM_A_DQ & lt; 26 & gt;
=MEM_A_DQ & lt; 27 & gt;
=MEM_A_DQ & lt; 28 & gt;
=MEM_A_DQ & lt; 29 & gt;
=MEM_A_DQ & lt; 30 & gt;
=MEM_A_DQ & lt; 31 & gt;
=MEM_A_DQ & lt; 32 & gt;
=MEM_A_DQ & lt; 33 & gt;
=MEM_A_DQ & lt; 34 & gt;
=MEM_A_DQ & lt; 35 & gt;
=MEM_A_DQ & lt; 36 & gt;
=MEM_A_DQ & lt; 37 & gt;
=MEM_A_DQ & lt; 38 & gt;
=MEM_A_DQ & lt; 39 & gt;
=MEM_A_DQ & lt; 40 & gt;
=MEM_A_DQ & lt; 41 & gt;
=MEM_A_DQ & lt; 42 & gt;
=MEM_A_DQ & lt; 43 & gt;
MEM_A_DQ & lt; 32 & gt;
=MEM_A_DQ & lt; 45 & gt;
=MEM_A_DQ & lt; 46 & gt;
=MEM_A_DQ & lt; 47 & gt;
=MEM_A_DQ & lt; 48 & gt;
=MEM_A_DQ & lt; 49 & gt;
=MEM_A_DQ & lt; 50 & gt;
=MEM_A_DQ & lt; 51 & gt;
=MEM_A_DQ & lt; 52 & gt;
=MEM_A_DQ & lt; 53 & gt;
=MEM_A_DQ & lt; 54 & gt;
=MEM_A_DQ & lt; 55 & gt;
=MEM_A_DQ & lt; 56 & gt;
=MEM_A_DQ & lt; 57 & gt;
=MEM_A_DQ & lt; 58 & gt;
=MEM_A_DQ & lt; 59 & gt;
=MEM_A_DQ & lt; 60 & gt;
=MEM_A_DQ & lt; 61 & gt;
=MEM_A_DQ & lt; 62 & gt;
=MEM_A_DQ & lt; 63 & gt;
=MEM_A_DQS_P & lt; 0 & gt;
=MEM_A_DQS_N & lt; 0 & gt;
=MEM_A_DQS_P & lt; 1 & gt;
=MEM_A_DQS_N & lt; 1 & gt;
=MEM_A_DQS_P & lt; 2 & gt;
=MEM_A_DQS_N & lt; 2 & gt;
=MEM_A_DQS_P & lt; 3 & gt;
=MEM_A_DQS_N & lt; 3 & gt;
=MEM_A_DQS_P & lt; 4 & gt;
=MEM_A_DQS_N & lt; 4 & gt;
=MEM_A_DQS_P & lt; 5 & gt;
=MEM_A_DQS_N & lt; 5 & gt;
MEM_A_DQS_P & lt; 6 & gt;
MEM_A_DQS_N & lt; 6 & gt;
=MEM_A_DQS_P & lt; 7 & gt;
=MEM_A_DQS_N & lt; 7 & gt;
MAKE_BASE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
MEM_A_DQ & lt; 9 & gt;
MEM_A_DQ & lt; 12 & gt;
MEM_A_DQ & lt; 10 & gt;
MEM_A_DQ & lt; 11 & gt;
MEM_A_DQ & lt; 8 & gt;
MEM_A_DQ & lt; 13 & gt;
MEM_A_DQ & lt; 14 & gt;
MEM_A_DQ & lt; 15 & gt;
MEM_A_DQ & lt; 0 & gt;
MEM_A_DQ & lt; 1 & gt;
MEM_A_DQ & lt; 2 & gt;
MEM_A_DQ & lt; 7 & gt;
MEM_A_DQ & lt; 4 & gt;
MEM_A_DQ & lt; 5 & gt;
MEM_A_DQ & lt; 3 & gt;
MEM_A_DQ & lt; 6 & gt;
MEM_A_DQ & lt; 29 & gt;
MEM_A_DQ & lt; 28 & gt;
MEM_A_DQ & lt; 27 & gt;
MEM_A_DQ & lt; 31 & gt;
MEM_A_DQ & lt; 24 & gt;
MEM_A_DQ & lt; 25 & gt;
MEM_A_DQ & lt; 26 & gt;
MEM_A_DQ & lt; 30 & gt;
MEM_A_DQ & lt; 18 & gt;
MEM_A_DQ & lt; 21 & gt;
MEM_A_DQ & lt; 16 & gt;
MEM_A_DQ & lt; 23 & gt;
MEM_A_DQ & lt; 20 & gt;
MEM_A_DQ & lt; 19 & gt;
MEM_A_DQ & lt; 22 & gt;
MEM_A_DQ & lt; 17 & gt;
MEM_A_DQ & lt; 41 & gt;
MEM_A_DQ & lt; 44 & gt;
MEM_A_DQ & lt; 46 & gt;
MEM_A_DQ & lt; 47 & gt;
MEM_A_DQ & lt; 40 & gt;
MEM_A_DQ & lt; 45 & gt;
MEM_A_DQ & lt; 42 & gt;
MEM_A_DQ & lt; 43 & gt;
MEM_A_DQ & lt; 36 & gt;
MEM_A_DQ & lt; 37 & gt;
MEM_A_DQ & lt; 34 & gt;
MEM_A_DQ & lt; 39 & gt;
MEM_A_DQ & lt; 32 & gt;
MEM_A_DQ & lt; 33 & gt;
MEM_A_DQ & lt; 35 & gt;
MEM_A_DQ & lt; 38 & gt;
MEM_A_DQ & lt; 52 & gt;
MEM_A_DQ & lt; 51 & gt;
MEM_A_DQ & lt; 48 & gt;
MEM_A_DQ & lt; 49 & gt;
MEM_A_DQ & lt; 53 & gt;
MEM_A_DQ & lt; 50 & gt;
MEM_A_DQ & lt; 54 & gt;
MEM_A_DQ & lt; 55 & gt;
MEM_A_DQ & lt; 58 & gt;
MEM_A_DQ & lt; 62 & gt;
MEM_A_DQ & lt; 60 & gt;
MEM_A_DQ & lt; 61 & gt;
MEM_A_DQ & lt; 59 & gt;
MEM_A_DQ & lt; 63 & gt;
MEM_A_DQ & lt; 57 & gt;
MEM_A_DQ & lt; 56 & gt;
MEM_A_DQS_P & lt; 1 & gt;
MEM_A_DQS_N & lt; 1 & gt;
MEM_A_DQS_P & lt; 0 & gt;
MEM_A_DQS_N & lt; 0 & gt;
MEM_A_DQS_P & lt; 3 & gt;
MEM_A_DQS_N & lt; 3 & gt;
MEM_A_DQS_P & lt; 2 & gt;
MEM_A_DQS_N & lt; 2 & gt;
MEM_A_DQS_P & lt; 5 & gt;
MEM_A_DQS_N & lt; 5 & gt;
MEM_A_DQS_P & lt; 4 & gt;
MEM_A_DQS_N & lt; 4 & gt;
MEM_A_DQS_P & lt; 6 & gt;
MEM_A_DQS_N & lt; 6 & gt;
MEM_A_DQS_P & lt; 7 & gt;
MEM_A_DQS_N & lt; 7 & gt;
7 70
22
7 70
22
7 70
22
7 70
22
7 70
22
7 70
22
7 70
22
7 70
22
7 70
22
7 70
22
7 70
22
7 70
22
7 70
22
7 70
22
7 70
22
7 70
22
7 70
22
7 70
22
7 70
22
7 70
22
7 70
22
7 70
22
7 70
22
7 70
22
7 70
22
7 70
22
7 70
22
7 70
22
7 70
22
7 70
22
7 70
22
7 70
22
7 70
23
7 70
23
7 70
23
7 70
23
7 70
23
7 70
23
7 70
23
7 70
23
7 70
23
7 70
70 63 23 7
7 70
23
7 70
23
7 21 63 70
23
7 70
23
7 70
23
7 70
23
7 70
23
7 70
23
7 70
23
7 70
23
7 70
23
7 70
23
7 70
23
7 70
23
7 70
23
7 70
23
7 70
23
7 70
23
7 70
23
7 70
23
7 70
23
7 70
23
7 70
22
7 70
22
7 70
22
7 70
22
7 70
22
7 70
22
7 70
22
7 70
22
7 70
23
7 70
23
7 70
23
7 70
23
7 21 63 70
23
7 21 63 70
23
7 70
70 63 23 7
7 70
70 63 23 7
=MEM_B_DQ & lt; 0 & gt;
=MEM_B_DQ & lt; 1 & gt;
=MEM_B_DQ & lt; 2 & gt;
=MEM_B_DQ & lt; 3 & gt;
=MEM_B_DQ & lt; 4 & gt;
=MEM_B_DQ & lt; 5 & gt;
=MEM_B_DQ & lt; 6 & gt;
=MEM_B_DQ & lt; 7 & gt;
=MEM_B_DQ & lt; 8 & gt;
=MEM_B_DQ & lt; 9 & gt;
=MEM_B_DQ & lt; 10 & gt;
=MEM_B_DQ & lt; 11 & gt;
=MEM_B_DQ & lt; 12 & gt;
=MEM_B_DQ & lt; 13 & gt;
=MEM_B_DQ & lt; 14 & gt;
=MEM_B_DQ & lt; 15 & gt;
=MEM_B_DQ & lt; 16 & gt;
=MEM_B_DQ & lt; 17 & gt;
=MEM_B_DQ & lt; 18 & gt;
=MEM_B_DQ & lt; 19 & gt;
=MEM_B_DQ & lt; 20 & gt;
=MEM_B_DQ & lt; 21 & gt;
=MEM_B_DQ & lt; 22 & gt;
=MEM_B_DQ & lt; 23 & gt;
=MEM_B_DQ & lt; 24 & gt;
=MEM_B_DQ & lt; 25 & gt;
=MEM_B_DQ & lt; 26 & gt;
=MEM_B_DQ & lt; 27 & gt;
=MEM_B_DQ & lt; 28 & gt;
=MEM_B_DQ & lt; 29 & gt;
=MEM_B_DQ & lt; 30 & gt;
=MEM_B_DQ & lt; 31 & gt;
=MEM_B_DQ & lt; 32 & gt;
=MEM_B_DQ & lt; 33 & gt;
=MEM_B_DQ & lt; 34 & gt;
=MEM_B_DQ & lt; 35 & gt;
=MEM_B_DQ & lt; 36 & gt;
=MEM_B_DQ & lt; 37 & gt;
=MEM_B_DQ & lt; 38 & gt;
=MEM_B_DQ & lt; 39 & gt;
=MEM_B_DQ & lt; 40 & gt;
MEM_B_DQ & lt; 33 & gt;
=MEM_B_DQ & lt; 42 & gt;
=MEM_B_DQ & lt; 43 & gt;
=MEM_B_DQ & lt; 44 & gt;
=MEM_B_DQ & lt; 45 & gt;
=MEM_B_DQ & lt; 46 & gt;
=MEM_B_DQ & lt; 47 & gt;
=MEM_B_DQ & lt; 48 & gt;
=MEM_B_DQ & lt; 49 & gt;
=MEM_B_DQ & lt; 50 & gt;
=MEM_B_DQ & lt; 51 & gt;
=MEM_B_DQ & lt; 52 & gt;
=MEM_B_DQ & lt; 53 & gt;
=MEM_B_DQ & lt; 54 & gt;
=MEM_B_DQ & lt; 55 & gt;
=MEM_B_DQ & lt; 56 & gt;
=MEM_B_DQ & lt; 57 & gt;
=MEM_B_DQ & lt; 58 & gt;
=MEM_B_DQ & lt; 59 & gt;
=MEM_B_DQ & lt; 60 & gt;
=MEM_B_DQ & lt; 61 & gt;
=MEM_B_DQ & lt; 62 & gt;
=MEM_B_DQ & lt; 63 & gt;
=MEM_B_DQS_P & lt; 0 & gt;
=MEM_B_DQS_N & lt; 0 & gt;
=MEM_B_DQS_P & lt; 1 & gt;
=MEM_B_DQS_N & lt; 1 & gt;
=MEM_B_DQS_P & lt; 2 & gt;
=MEM_B_DQS_N & lt; 2 & gt;
=MEM_B_DQS_P & lt; 3 & gt;
=MEM_B_DQS_N & lt; 3 & gt;
=MEM_B_DQS_P & lt; 4 & gt;
=MEM_B_DQS_N & lt; 4 & gt;
=MEM_B_DQS_P & lt; 5 & gt;
=MEM_B_DQS_N & lt; 5 & gt;
=MEM_B_DQS_P & lt; 6 & gt;
=MEM_B_DQS_N & lt; 6 & gt;
MEM_B_DQS_P & lt; 6 & gt;
MEM_B_DQS_N & lt; 6 & gt;
MAKE_BASE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
MEM_B_DQ & lt; 12 & gt;
MEM_B_DQ & lt; 9 & gt;
MEM_B_DQ & lt; 10 & gt;
MEM_B_DQ & lt; 11 & gt;
MEM_B_DQ & lt; 13 & gt;
MEM_B_DQ & lt; 8 & gt;
MEM_B_DQ & lt; 14 & gt;
MEM_B_DQ & lt; 15 & gt;
MEM_B_DQ & lt; 0 & gt;
MEM_B_DQ & lt; 1 & gt;
MEM_B_DQ & lt; 2 & gt;
MEM_B_DQ & lt; 7 & gt;
MEM_B_DQ & lt; 4 & gt;
MEM_B_DQ & lt; 5 & gt;
MEM_B_DQ & lt; 6 & gt;
MEM_B_DQ & lt; 3 & gt;
MEM_B_DQ & lt; 28 & gt;
MEM_B_DQ & lt; 29 & gt;
MEM_B_DQ & lt; 30 & gt;
MEM_B_DQ & lt; 27 & gt;
MEM_B_DQ & lt; 24 & gt;
MEM_B_DQ & lt; 25 & gt;
MEM_B_DQ & lt; 31 & gt;
MEM_B_DQ & lt; 26 & gt;
MEM_B_DQ & lt; 20 & gt;
MEM_B_DQ & lt; 16 & gt;
MEM_B_DQ & lt; 23 & gt;
MEM_B_DQ & lt; 22 & gt;
MEM_B_DQ & lt; 21 & gt;
MEM_B_DQ & lt; 17 & gt;
MEM_B_DQ & lt; 18 & gt;
MEM_B_DQ & lt; 19 & gt;
MEM_B_DQ & lt; 44 & gt;
MEM_B_DQ & lt; 41 & gt;
MEM_B_DQ & lt; 42 & gt;
MEM_B_DQ & lt; 43 & gt;
MEM_B_DQ & lt; 45 & gt;
MEM_B_DQ & lt; 40 & gt;
MEM_B_DQ & lt; 46 & gt;
MEM_B_DQ & lt; 47 & gt;
MEM_B_DQ & lt; 32 & gt;
MEM_B_DQ & lt; 33 & gt;
MEM_B_DQ & lt; 34 & gt;
MEM_B_DQ & lt; 39 & gt;
MEM_B_DQ & lt; 36 & gt;
MEM_B_DQ & lt; 37 & gt;
MEM_B_DQ & lt; 38 & gt;
MEM_B_DQ & lt; 35 & gt;
MEM_B_DQ & lt; 57 & gt;
MEM_B_DQ & lt; 56 & gt;
MEM_B_DQ & lt; 60 & gt;
MEM_B_DQ & lt; 59 & gt;
MEM_B_DQ & lt; 63 & gt;
MEM_B_DQ & lt; 62 & gt;
MEM_B_DQ & lt; 58 & gt;
MEM_B_DQ & lt; 61 & gt;
MEM_B_DQ & lt; 49 & gt;
MEM_B_DQ & lt; 51 & gt;
MEM_B_DQ & lt; 48 & gt;
MEM_B_DQ & lt; 53 & gt;
MEM_B_DQ & lt; 52 & gt;
MEM_B_DQ & lt; 55 & gt;
MEM_B_DQ & lt; 50 & gt;
MEM_B_DQ & lt; 54 & gt;
MEM_B_DQS_P & lt; 1 & gt;
MEM_B_DQS_N & lt; 1 & gt;
MEM_B_DQS_P & lt; 0 & gt;
MEM_B_DQS_N & lt; 0 & gt;
MEM_B_DQS_P & lt; 3 & gt;
MEM_B_DQS_N & lt; 3 & gt;
MEM_B_DQS_P & lt; 2 & gt;
MEM_B_DQS_N & lt; 2 & gt;
MEM_B_DQS_P & lt; 5 & gt;
MEM_B_DQS_N & lt; 5 & gt;
MEM_B_DQS_P & lt; 4 & gt;
MEM_B_DQS_N & lt; 4 & gt;
MEM_B_DQS_P & lt; 7 & gt;
MEM_B_DQS_N & lt; 7 & gt;
MEM_B_DQS_P & lt; 6 & gt;
MEM_B_DQS_N & lt; 6 & gt;
7 70
7 70
7 70
7 70
D
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
C
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 23 63 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
B
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 70
7 23 63 70
7 23 63 70
A
SYNC_MASTER=J41_MLB
SYNC_DATE=08/30/2012
PAGE TITLE
Signal Aliases
DRAWING NUMBER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
102 OF 121
SHEET
63 OF 76
1
A
8
7
6
5
4
3
2
Functional Test Points
J3501: AirPort / BT Connector
D
FUNC_TEST
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
(Need
PP3V3_WLAN
WIFI_EVENT_L
PCIE_AP_R2D_N
PCIE_AP_R2D_P
PCIE_CLK100M_AP_N
PCIE_CLK100M_AP_P
PCIE_AP_D2R_P
PCIE_AP_D2R_N
PCIE_WAKE_L
AP_RESET_CONN_L
AP_CLKREQ_Q_L
USB_BT_CONN_P
USB_BT_CONN_N
PP3V3_S4
6 TPs)
29 37 38 39 41
29 37 38
29 69
PP5V_S0
FAN_RT_TACH
FAN_RT_PWM
16 17 32 45 46 51 52
56 58 59 61 62 64
45
45
12 29 69
J4800: IPD Flex Connector
12 29 69
FUNC_TEST
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
14 29 69
14 29 69
13 29 31
29
29
29 68
29 68
29 33 36 38 39 58 62
64
J3700: SSD Connector
C
Misc Voltages & Control Signals
(Need to add 1 GND TP)
29 69
(Need to add 8 GND TPs)
FUNC_TEST
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
NO_TEST Nets
J6000: Fan Connector
FUNC_TEST
TRUE
TRUE
TRUE
(Need 5 TPs)
PP3V3_S0SW_SSD_FLT
PCIE_SSD_R2D_N & lt; 3..0 & gt;
PCIE_SSD_R2D_P & lt; 3..0 & gt;
PP3V3_S0
SSD_RESET_CONN_L
SSD_CLKREQ_CONN_L
SMC_OOB1_R2D_CONN_L
SMC_OOB1_D2R_CONN_L
SSD_PCIE_SEL_L
SSD_DEVSLP
SSD_PWRFAIL_WARN_L
SSD_PWR_EN
PCIE_SSD_D2R_N & lt; 3..0 & gt;
PCIE_SSD_D2R_P & lt; 3..0 & gt;
PCIE_CLK100M_SSD_N
PCIE_CLK100M_SSD_P
(Need to add 6 GND TPs)
30
30 67
30 67
42 43 44 45 56 59 61
8 11 12 13 15 17 18
27 30 36 38 39 40 41
62 64 65 74
30
30
30
SMC_LID
TPAD_SPI_MISO_R
USB_TPAD_P
USB_TPAD_N
TPAD_SPI_CLK_R
TPAD_WAKE_L
TPAD_SPI_MOSI_R
PP3V3_S4_IPD
TPAD_SPI_CS_R_L
TPAD_SPI_IF_EN_CONN
TPAD_SPI_INT_S4_WAKE_L_CONN
PP5V_S4_IPD
TPAD_USB_IF_EN_CONN
SMBUS_SMC_3_SDA
SMBUS_SMC_3_SCL
SMC_LSOC_RST_L
PP3V42_G3H
SMC_ONOFF_L
(Need to add 5 GND TPs)
36 37 38 61 65
36
14 36 68
14 36 68
36
36
36
36
36
36
36
36
36
36 37 40 44 73
FUNC_TEST
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
PPBUS_G3H
PPVIN_S4SW_TBTBST_FET
PPBUS_S5_HS_COMPUTING_ISNS
PPDCIN_G3H
PP3V42_G3H
PPVRTC_G3H
PP3V3_S5
PP3V3_SUS
PP3V3_S3
PP3V3_S0
PP3V3_S0SW_SSD
PP1V5_S0
PP1V05_S0
PP15V_TBT
PP3V3_TBTLC
PP1V05_TBTLC
PPVCC_S0_CPU
PP1V05_TBTCIO
PPBUS_S5_HS_OTHER_ISNS
PPDCIN_G3H_ISOL
PP3V3_S4
(Need to add 27 GND TPs)
27 41 42 49 50 56 62
64
27 62
64
41 51 52 53 55 62
64 12
49 50 62 64
64 12
17 30 35 36 37 38 40 46 49 50
59 61 62 64 65
64 14
8 12 13 17 62
64 14
8 11 13 15 16 17 18 28 29 34 42
57 58 59 60 62 74
8 11 14 18 46 57 58 59 62
64 14
64 14
15 18 19 33 36 40 41 58 62
64 14
62 64 65 74
8 11 12 13 15 17 18 27 30 36 38
39 40 41 42 43 44 45 56 59 61
30 41 62
64 14
64 14
8 57 58 59 62
64 14
6 8 11 15 16 17 27 38 42 51 55
58 59 62 64
27 28 62
64 14
64 14
15 17 25 26 27 62
67
26 27 62
67
8 10 42 52 62
64 12
26 27 62
64 13
41 54 62
64 14
42 49 50 62
64 14
29 33 36 38 39 58 62 64
64 14
64 37
36 38
17 30 35 36 37 38 40 46 49 50
59 61 62 64 65
64
36 37 38
64
64
64 37
J7000: DC-In Connector
15 30
FUNC_TEST
TRUE
TRUE
15 30 58 59
12 30 67
64 37
(Need 4 TPs)
49 50
(Need 3 TPs)
PPDCIN_G3H
PP5V_S4RS3
64 37
62 64
64 37
32 35 47 49 54 55 58 62
64 37
(Need to add 5 GND TPs)
12 30 67
64
12 30 67
64
J6404: Speaker Connector
12 30 67
FUNC_TEST
TRUE
TRUE
J4002: Camera Connector
64
64 37
SPKRAMP_ROUT_P
SPKRAMP_ROUT_N
47 74
64 37
47 74
64 37
FUNC_TEST
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
MIPI_CLK_CONN_N
32 72
MIPI_CLK_CONN_P
32 72
CAM_SENSOR_WAKE_L_CONN 32
MIPI_DATA_CONN_N
32 72
MIPI_DATA_CONN_P
32 72
SMBUS_SMC_1_S0_SDA
14 32 37 40 43
73
SMBUS_SMC_1_S0_SCL
14 32 37 40 43
73
I2C_CAM_SCK
31 32
I2C_CAM_SDA
31 32
(Need TBD TPs)
PP5V_S3RS0_ALSCAM_F
32
(Need to add 3 GND TPs)
64 37
64 37
J6950: Battery Connector
FUNC_TEST
TRUE
TRUE
TRUE
TRUE
44 69
44 69
71
PPVBAT_G3H_CONN
SMBUS_SMC_5_G3_SCL
SMBUS_SMC_5_G3_SDA
SYS_DETECT_L
(Need 4 TPs)
71
48 50
71
37 40 48 50 73
71
37 40 48 50 73
64 25
48
71 64
(Need to add 4 GND TPs near
J7050 and 1 for shield)
71 64
71 64 25
(Need to add TBD GND TPs)
71 64 25
J8300: Internal DP Connector
FUNC_TEST
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
J6100: LPC+SPI Connector
FUNC_TEST
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
B
PP3V42_G3H
PP5V_S0
LPC_CLK24M_LPCPLUS
LPC_AD & lt; 3..0 & gt;
SPI_ALT_MOSI
XDP_LPCPLUS_GPIO
LPCPLUS_RESET_L
SMC_TDO
TP_SMC_TRST_L
TP_SMC_MD1
SMC_TX_L
SPI_ALT_MISO
LPC_FRAME_L
SPIROM_USE_MLB
PM_CLKRUN_L
SPI_ALT_CLK
SPI_ALT_CS_L
LPC_SERIRQ
LPC_PWRDWN_L
SMC_TDI
SMC_TCK
SMC_RESET_L
SMC_ROMBOOT
SMC_RX_L
SMC_TMS
(Need to add 6 GND TPs)
A
65
17
46
16
56
30
49
17
58
35
50
32
59
36
59
45
61
37
61
46
62
38 40
62 64
51 52
64
17 46 69
14 37 46 69
46
15 16 46
18 46 69
37 38 46
46
25
PPHV_S0SW_LCDBKLT
LED_RETURN_6
LED_RETURN_5
LED_RETURN_4
LED_RETURN_3
LED_RETURN_2
LED_RETURN_1
DP_INT_HPD_CONN
I2C_TCON_SDA_R
I2C_TCON_SCL_R
PP3V3_S0SW_LCD_UF
DP_INT_AUX_CH_C_N
DP_INT_AUX_CH_C_P
DP_INT_ML_P & lt; 0 & gt;
DP_INT_ML_N & lt; 0 & gt;
(Need 2 TPs)
25
56 60 62
25
56 60
25
56 60
64 25
56 60
64 25
56 60
25
56 60
25
56 60
64 25
60
TRUE
64 25
NC_PCIE_CLK100M_SDP
NC_PCIE_CLK100M_SDN
NC_PCIE_CLK100M_FWP
NC_PCIE_CLK100M_FWN
NC_PCIE_FW_D2RP
NC_PCIE_FW_D2RN
NC_PCIE_FW_R2D_CP
NC_PCIE_FW_R2D_CN
NC_USB_IRP
NC_USB_IRN
NC_USB_CAMERAP
NC_USB_CAMERAN
NC_USB_SDP
NC_USB_SDN
NC_INT_ML_CP & lt; 3..1 & gt;
NC_INT_ML_CN & lt; 3..1 & gt;
NC_HDA_SDIN1
NC_PCI_PME_L
NC_CLINK_CLK
NC_CLINK_DATA
NC_CLINK_RESET_L
64
64
12 64
12 64
14 64
14 64
14 64
D
14 64
14 64
14 64
CPU/PCH
14 64
14 64
14 64
14 64
5
5
12 64
13 64
14 64
14 64
14 64
NC_SMC_SYS_LED
NC_IR_RX_OUT_RC
NC_USB_SMCP
NC_USB_SMCN
NC_SMC_GFX_OVERTEMP
NC_SMC_GFX_THROTTLE_L
NC_SMC_FAN_1_CTL
NC_SMC_FAN_1_TACH
NC_SMC_FAN_5_CTL
NC_ENET_ASF_GPIO
NC_SMC_MPM5_LED_PWR
NC_SMC_MPM5_LED_CHG
NC_SMC_T25_EN_L
NC_SMC_DP_HPD_L
NC_SMBUS_SMC_4_ASF_SCL
NC_SMBUS_SMC_4_ASF_SDA
NC_BDV_BKL_PWM
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
NC_SMC_SYS_LED
NC_IR_RX_OUT_RC
NC_USB_SMCP
NC_USB_SMCN
NC_SMC_GFX_OVERTEMP
NC_SMC_GFX_THROTTLE_L
NC_SMC_FAN_1_CTL
NC_SMC_FAN_1_TACH
NC_SMC_FAN_5_CTL
NC_ENET_ASF_GPIO
NC_SMC_MPM5_LED_PWR
NC_SMC_MPM5_LED_CHG
NC_SMC_T25_EN_L
NC_SMC_DP_HPD_L
NC_SMBUS_SMC_4_ASF_SCL
NC_SMBUS_SMC_4_ASF_SDA
NC_BDV_BKL_PWM
TBT_B_R2D_C_P & lt; 1..0 & gt;
TBT_B_R2D_C_N & lt; 1..0 & gt;
TBT_B_D2R_P & lt; 1..0 & gt;
TBT_B_D2R_N & lt; 1..0 & gt;
NC_TBT_B_LSTX
NC_DP_TBTPB_ML_CP & lt; 3..1:2 & gt;
NC_DP_TBTPB_ML_CN & lt; 3..1:2 & gt;
NC_DP_TBTPB_AUXCH_CP
NC_DP_TBTPB_AUXCH_CN
TP_DP_TBTSRC_ML_CP & lt; 3 & gt;
TP_DP_TBTSRC_ML_CN & lt; 3 & gt;
TP_DP_TBTSRC_ML_CP & lt; 2 & gt;
TP_DP_TBTSRC_ML_CN & lt; 2 & gt;
NC_DP_TBTSRC_ML_CP & lt; 1 & gt;
NC_DP_TBTSRC_ML_CN & lt; 1 & gt;
TP_DP_TBTSRC_ML_CP & lt; 0 & gt;
TP_DP_TBTSRC_ML_CN & lt; 0 & gt;
NC_DP_TBTSRC_AUXCH_CP
NC_DP_TBTSRC_AUXCH_CN
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
NC_TBT_B_R2D_CP & lt; 1..0 & gt;
NC_TBT_B_R2D_CN & lt; 1..0 & gt;
NC_TBT_B_D2RP & lt; 1..0 & gt;
NC_TBT_B_D2RN & lt; 1..0 & gt;
NC_TBT_B_LSTX
NC_DP_TBTPB_ML_CP & lt; 3..1:2 & gt;
NC_DP_TBTPB_ML_CN & lt; 3..1:2 & gt;
NC_DP_TBTPB_AUXCH_CP
NC_DP_TBTPB_AUXCH_CN
NC_DP_TBTSRC_ML_CP & lt; 3 & gt;
NC_DP_TBTSRC_ML_CN & lt; 3 & gt;
NC_DP_TBTSRC_ML_CP & lt; 2 & gt;
NC_DP_TBTSRC_ML_CN & lt; 2 & gt;
NC_DP_TBTSRC_ML_CP & lt; 1 & gt;
NC_DP_TBTSRC_ML_CN & lt; 1 & gt;
NC_DP_TBTSRC_ML_CP & lt; 0 & gt;
NC_DP_TBTSRC_ML_CN & lt; 0 & gt;
NC_DP_TBTSRC_AUXCH_CP
NC_DP_TBTSRC_AUXCH_CN
37 64
64
64
64
37 64
37 64
37 64
37 64
37 64
SMC
64
64
64
C
37 64
37 64
37 64
37 64
37 64
25
25
25
25
25 64
64 71
64 71
25 64 71
25 64
71
TBT
25 64
25 64
25 64
25 64
60
(Need 2 TPs)
B
60
60 67
60 67
60 67
60 67
(Need to add 5 GND TPs)
46
37 38 46
46
J7715: KB BKLT Connector
14 37 46 69
FUNC_TEST
TRUE
TRUE
15 46
13 37 46
46
KBDLED_ANODE
KBDLED_FB
56
56
(Need to add 2 GND TPs)
46
15 37 46
J1800: XDP Connector
13 37 46
37 38 46
37 38 46
37 38 46 50
38 46
37 38 46
37 38 46
FUNC_TEST
TRUE
I776
TRUE
I777
TRUE
I778
TRUE
I779
TRUE
I780
TRUE
I781
TRUE
I782
TRUE
I783
TRUE
I784
TRUE
I785
TRUE
I786
TRUE
I787
TRUE
I788
TRUE
I789
TRUE
I790
TRUE
I791
TRUE
I792
(Only a subset are needed
for FCT HVM test fixture)
XDP_CPU_TCK
XDP_PCH_TCK
XDP_CPU_TDI
XDP_CPU_TDO
XDP_CPUPCH_TRST_L
XDP_CPU_TMS
XDP_PCH_TMS
XDP_PCH_TDI
XDP_PCH_TDO
XDP_CPU_PREQ_L
XDP_CPU_PRDY_L
XDP_CPU_VCCST_PWRGD
PM_RSMRST_L
XDP_SYS_PWROK
PM_SYSRST_L
CPU_CFG & lt; 3 & gt;
PP1V05_S0
6 16 67
12 16 69
6 16 67
6 16 67
6 12 16 67
Unused nets with offpage
6 16 67
12 16 69
(Nets with offpages not used on this project)
12 16 69
12 16 69
HDD_PWR_EN
WOL_EN
BT_PWRRST_L
HDMITBTMUX_FLAG_L
FW_PWR_EN
FW_PME_L
ENET_MEDIA_SENSE
LCD_PSR_EN
LCD_IRQ_L
ODD_PWR_EN_L
ENET_LOW_PWR
AUD_IP_PERIPHERAL_DET
AUD_I2C_INT_L
AUD_IPHS_SWITCH_EN
6 16 67
6 16 67
16
13 59
16
13 17 37
6 16 67
6 8 11 15 16 17 27 38 42 51 55
58 59 62 64
GND
8
NO_TEST
MAKE_BASE
TRUE TRUE
TRUE TRUE
TRUE TRUE
TRUE TRUE
TRUE TRUE
TRUE TRUE
TRUE TRUE
TRUE TRUE
TRUE TRUE
TRUE TRUE
TRUE TRUE
TRUE TRUE
TRUE TRUE
TRUE TRUE
TRUE TRUE
TRUE TRUE
TRUE TRUE
TRUE TRUE
TRUE TRUE
TRUE TRUE
TRUE TRUE
60
(Need to add 2 GND TPs)
I793
NC_PCIE_CLK100M_SDP
NC_PCIE_CLK100M_SDN
NC_PCIE_CLK100M_FWP
NC_PCIE_CLK100M_FWN
NC_PCIE_FW_D2RP
NC_PCIE_FW_D2RN
NC_PCIE_FW_R2D_CP
NC_PCIE_FW_R2D_CN
NC_USB_IRP
NC_USB_IRN
NC_USB_CAMERAP
NC_USB_CAMERAN
NC_USB_SDP
NC_USB_SDN
DP_INT_ML_C_P & lt; 3..1 & gt;
DP_INT_ML_C_N & lt; 3..1 & gt;
NC_HDA_SDIN1
NC_PCI_PME_L
NC_CLINK_CLK
NC_CLINK_DATA
NC_CLINK_RESET_L
36 37 40 44 73
30
16 30
1
7
6
5
4
3
15
14
15
15
SYNC_MASTER=J41_MLB
SYNC_DATE=02/01/2013
PAGE TITLE
Func Test / No Test
15
DRAWING NUMBER
15
15
Apple Inc.
15
R
& lt; E4LABEL & gt;
15
13
13
13
13
13
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
2
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64 OF 76
1
A
8
7
6
5
4
3
2
1
D
D
Functional Test Points
SD Card Aliases
J9500: LIO Connector
FUNC_TEST
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
C
68 65 34 14
PP3V42_G3H
PP3V3_S0
PP1V5_S0SW_AUDIO
SYS_ONEWIRE
SMC_BC_ACOK
USB_PWR_EN
SMBUS_SMC_2_S3_SDA
SMBUS_SMC_2_S3_SCL
SPKRAMP_SHDN_L
17 30 35 36 37 38 40 46 49 50
59 61 62 64
62 64 74
8 11 12 13 15 17 18 27 30 36 38
39 40 41 42 43 44 45 56 59 61
68 65 34 14
58 61
68 65 34 14
68 65 34 14
MAKE_BASE
TRUE
TRUE
TRUE
TRUE
USB3_SD_D2R_P
USB3_SD_D2R_N
USB3_SD_R2D_C_P
USB3_SD_R2D_C_N
USB3_SD_D2R_P
USB3_SD_D2R_N
USB3_SD_R2D_C_P
USB3_SD_R2D_C_N
14 34 65 68
14 34 65 68
14 34 65 68
14 34 65 68
37 61
37 38 50 61
65 39 37 34 15
PP3V3_S0SW_SD
PP3V3_S0SW_SD
(MAKE_BASE=TRUE on page 45)
35 59 61
15 34 37 39 65
37 40 61 73
37 40 61 73
47 61
FINSTACKSNS_ALERT_L
39 61
SPKRAMP_INR_N
47 61
SPKRAMP_INR_P
47 61
USB_EXTB_N
14 61
USB_EXTB_P
14 61
PP5V_S0_ALT_AUD_LDO_EN 61
SMC_lID
36 37
HDA_SDOUT
12 61
HDA_BIT_CLK
12 61
HDA_SDIN0
12 61
XDP_USB_EXTB_OC_L
14 16
HDA_RST_L
12 61
HDA_SYNC
12 61
USB3_EXTB_D2R_RC_P
61 65
USB3_EXTB_D2R_RC_N
61 65
USB3_EXTB_R2D_P
61 65
USB3_EXTB_R2D_N
61 65
AUD_PWR_EN
13 59
74
74
C
68
68
38 61 64
69
69
69
61
69
69
68
68
68
68
61
(Need to add 5 GND TPs)
B
B
Bead Probes
68 61 14
68 61 14
68 65 61
68 65 61
68 61 14
68 61 14
68 65 61
68 65 61
USB3_EXTB_D2R_N
USB3_EXTB_D2R_P
USB3_EXTB_D2R_RC_N
USB3_EXTB_D2R_RC_P
USB3_EXTB_R2D_C_N
USB3_EXTB_R2D_C_P
USB3_EXTB_R2D_N
USB3_EXTB_R2D_P
1 TP
1 TP
1 TP
1 TP
1 TP
1 TP
1 TP
1 TP
BEAD-PROBE
BEAD-PROBE
BEAD-PROBE
BEAD-PROBE
BEAD-PROBE
BEAD-PROBE
BEAD-PROBE
BEAD-PROBE
BPA511
BPA510
BPA520
BPA521
BPA513
BPA512
BPA523
BPA522
A
SYNC_MASTER=J41_MLB
SYNC_DATE=09/13/2012
PAGE TITLE
Project FCT/NC/Aliases
DRAWING NUMBER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
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REVISION
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BRANCH
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PAGE
105 OF 121
SHEET
65 OF 76
1
A
8
7
6
5
4
3
2
1
J41/J43 Board-Specific Spacing & Physical Constraints
TABLE_BOARD_INFO
BOARD LAYERS
BOARD AREAS
BOARD UNITS
(MIL or MM)
ALLEGRO
VERSION
TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM
NO_TYPE,BGA,MEM_TERM
MM
16.2
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
DEFAULT
TOP,BOTTOM
Y
=50_OHM_SE
=50_OHM_SE
DEFAULT
ISL2,ISL11
Y
=45_OHM_SE
=45_OHM_SE
DEFAULT
ISL3,ISL10
Y
=45_OHM_SE
=45_OHM_SE
DEFAULT
ISL4,ISL9
Y
=45_OHM_SE
=45_OHM_SE
DEFAULT
*
N
100 MM
100 MM
10 MM
0 MM
0 MM
STANDARD
*
=DEFAULT
=DEFAULT
=DEFAULT
=DEFAULT
=DEFAULT
=DEFAULT
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
D
D
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
Single-ended Physical Constraints
Spacing Constraints
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
0.100 MM
?
TABLE_PHYSICAL_RULE_ITEM
27P4_OHM_SE
TOP,BOTTOM
Y
0.310 MM
0.310 MM
TABLE_SPACING_RULE_ITEM
1:1_SPACING
*
TABLE_PHYSICAL_RULE_ITEM
27P4_OHM_SE
ISL2,ISL11
Y
0.182 MM
27P4_OHM_SE
ISL3,ISL10
Y
0.182 MM
0.182 MM
0.182 MM
27P4_OHM_SE
ISL4,ISL9
Y
0.182 MM
0.182 MM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LINE-TO-LINE SPACING
WEIGHT
1x_DIELECTRIC
TOP,BOTTOM
LAYER
0.071 MM
?
1x_DIELECTRIC
ISL3,ISL10
0.053 MM
?
1x_DIELECTRIC
ISL4,ISL9
0.050 MM
?
1x_DIELECTRIC
*
0.090 MM
?
LINE-TO-LINE SPACING
WEIGHT
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
27P4_OHM_SE
*
N
100 MM
100 MM
=STANDARD
=STANDARD
=STANDARD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
35_OHM_SE
TOP,BOTTOM
Y
0.195 MM
0.195 MM
35_OHM_SE
ISL2,ISL11
Y
0.125 MM
0.125 MM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
TABLE_PHYSICAL_RULE_ITEM
35_OHM_SE
ISL3,ISL10
Y
0.125 MM
0.125 MM
35_OHM_SE
ISL4,ISL9
Y
0.125 MM
0.125 MM
35_OHM_SE
*
N
100 MM
100 MM
=STANDARD
=STANDARD
=STANDARD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
*
*
BGA
BGA_P075MM
TABLE_SPACING_RULE_ITEM
DEFAULT
STANDARD
BGA_P075MM
*
*
*
0.1 MM
=DEFAULT
0.075 MM
?
?
?
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_ASSIGNMENT_HEAD
NET_PHYSICAL_TYPE
AREA_TYPE
PHYSICAL_RULE_SET
*
BGA
P070MM_BGA
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_ASSIGNMENT_ITEM
C
C
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
P070MM_BGA
40_OHM_SE
TOP,BOTTOM
Y
0.170 MM
0.170 MM
40_OHM_SE
ISL2,ISL11
Y
0.096 MM
40_OHM_SE
ISL3,ISL10
Y
0.096 MM
ISL4,ISL9
Y
0.099 MM
*
N
100 MM
100 MM
=STANDARD
=STANDARD
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
45_OHM_SE
TOP,BOTTOM
Y
0.135 MM
0.135 MM
45_OHM_SE
ISL2,ISL11
Y
0.075 MM
0.075 MM
=STANDARD
PHYSICAL_RULE_SET
5 MM
0.099 MM
40_OHM_SE
0.070 MM
0.096 MM
40_OHM_SE
*
0.096 MM
0.075 MM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
45_OHM_SE
ISL3,ISL10
Y
0.075 MM
0.075 MM
45_OHM_SE
ISL4,ISL9
Y
0.080 MM
0.080 MM
45_OHM_SE
*
N
100 MM
100 MM
=STANDARD
=STANDARD
=STANDARD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
50_OHM_SE
TOP,BOTTOM
Y
0.110 MM
0.110 MM
50_OHM_SE
*
N
100 MM
100 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
55_OHM_SE
TOP,BOTTOM
Y
0.090 MM
0.090 MM
55_OHM_SE
*
N
100 MM
100 MM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
B
=STANDARD
=STANDARD
=STANDARD
B
TABLE_PHYSICAL_RULE_HEAD
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
=STANDARD
=STANDARD
=STANDARD
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
Differential Pair Physical Constraints
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
73_OHM_DIFF
TOP,BOTTOM
Y
0.165 MM
73_OHM_DIFF
ISL2,ISL11
Y
73_OHM_DIFF
ISL3,ISL10
73_OHM_DIFF
73_OHM_DIFF
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
0.165 MM
0.150 MM
0.150 MM
0.106 MM
0.106 MM
0.150 MM
0.150 MM
Y
0.106 MM
0.106 MM
0.150 MM
0.150 MM
ISL4,ISL9
Y
0.110 MM
0.110 MM
0.150 MM
0.150 MM
*
N
100 MM
100 MM
=STANDARD
=STANDARD
=STANDARD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
85_OHM_DIFF
TOP,BOTTOM
Y
0.120 MM
0.120 MM
0.150 MM
0.150 MM
85_OHM_DIFF
ISL2,ISL11
Y
0.078 MM
0.078 MM
0.160 MM
0.160 MM
85_OHM_DIFF
ISL3,ISL10
Y
0.078 MM
0.078 MM
0.160 MM
0.160 MM
85_OHM_DIFF
ISL4,ISL9
Y
0.082 MM
0.082 MM
0.140 MM
0.140 MM
85_OHM_DIFF
*
N
100 MM
100 MM
=STANDARD
=STANDARD
TABLE_PHYSICAL_RULE_ITEM
70_OHM_DIFF
TOP,BOTTOM
Y
0.165 MM
0.165 MM
0.110 MM
0.110 MM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
70_OHM_DIFF
ISL2,ISL11
Y
0.105 MM
0.105 MM
0.100 MM
0.100 MM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
70_OHM_DIFF
ISL3,ISL10
Y
0.105 MM
0.105 MM
0.100 MM
0.100 MM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
70_OHM_DIFF
ISL4,ISL9
Y
0.110 MM
0.110MM
0.095 MM
0.095 MM
70_OHM_DIFF
*
N
100 MM
100 MM
=STANDARD
=STANDARD
=STANDARD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
80_OHM_DIFF
TOP,BOTTOM
Y
0.132 MM
0.132 MM
0.130 MM
0.130 MM
80_OHM_DIFF
ISL2,ISL11
Y
0.081 MM
0.081 MM
0.115 MM
0.115 MM
80_OHM_DIFF
ISL3,ISL10
Y
0.081 MM
0.081 MM
0.115 MM
0.115 MM
80_OHM_DIFF
ISL4,ISL9
Y
0.088 MM
0.088 MM
0.110 MM
0.110 MM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
A
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
SYNC_MASTER=CONSTRAINTS
SYNC_DATE=10/24/2012
TABLE_PHYSICAL_RULE_ITEM
80_OHM_DIFF
*
N
100 MM
100 MM
=STANDARD
=STANDARD
=STANDARD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
PAGE TITLE
DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM
=STANDARD
PCB Rule Definitions
DRAWING NUMBER
TABLE_PHYSICAL_RULE_HEAD
Apple Inc.
TABLE_PHYSICAL_RULE_ITEM
90_OHM_DIFF
TOP,BOTTOM
Y
0.115 MM
0.115 MM
0.200 MM
0.200 MM
90_OHM_DIFF
ISL2,ISL11
Y
0.070 MM
0.070 MM
0.180 MM
0.180 MM
R
& lt; E4LABEL & gt;
TABLE_PHYSICAL_RULE_ITEM
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
TABLE_PHYSICAL_RULE_ITEM
90_OHM_DIFF
ISL3,ISL10
Y
0.070 MM
0.070 MM
0.180 MM
0.180 MM
90_OHM_DIFF
ISL4,ISL9
Y
0.076 MM
0.076 MM
0.180 MM
0.180 MM
90_OHM_DIFF
*
N
100 MM
100 MM
=STANDARD
=STANDARD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
8
7
=STANDARD
6
5
4
3
2
SIZE
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& lt; BRANCH & gt;
PAGE
110 OF 121
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66 OF 76
1
A
8
7
6
5
CPU Signal Constraints
4
3
2
1
CPU Net Properties
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
CPU_45S
*
=45_OHM_SE
=45_OHM_SE
=45_OHM_SE
=45_OHM_SE
=STANDARD
NET_TYPE
PHYSICAL
=STANDARD
ELECTRICAL_CONSTRAINT_SET
SPACING
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
CPU_27P4S
*
=27P4_OHM_SE
=27P4_OHM_SE
=27P4_OHM_SE
0.100 MM
SPACING_RULE_SET
LINE-TO-LINE SPACING
TOP,BOTTOM
LAYER
=2x_DIELECTRIC
?
CPU_AGTL
*
=STANDARD
CPU_PECI
PM_SYNC
PM_MEM_PWRGD
CPU_ITP
CPU_ITP
CPU_ITP
XDP_DBRESET_L
XDP_CPU_PRDY_L
XDP_CPU_PREQ_L
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_45S
CPU_45S
CPU_45S
CPU_45S
CPU_45S
CPU_45S
CLK_PCIE_80D
CLK_PCIE_80D
CLK_PCIE_80D
CLK_PCIE_80D
CLK_PCIE_80D
CLK_PCIE_80D
CLK_PCIE_80D
CLK_PCIE_80D
CLK_PCIE_80D
CLK_PCIE_80D
CPU_45S
CPU_45S
CPU_45S
CPU_45S
CPU_45S
CPU_45S
CPU_45S
CPU_45S
CPU_45S
CPU_45S
CPU_COMP
CPU_COMP
CPU_COMP
CPU_COMP
CPU_COMP
CPU_ITP
CPU_AGTL
CPU_AGTL
CPU_AGTL
CPU_AGTL
CPU_8MIL
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CPU_ITP
CPU_ITP
CPU_ITP
CPU_ITP
CPU_ITP
CPU_ITP
CPU_ITP
CPU_ITP
CPU_ITP
CPU_ITP
EDP_COMP
CPU_PEG_COMP
CPU_SM_RCOMP & lt; 0 & gt;
CPU_SM_RCOMP & lt; 1 & gt;
CPU_SM_RCOMP & lt; 2 & gt;
CPU_CFG & lt; 11..0 & gt;
CPU_CATERR_L
CPU_VCCIO_SEL
CPU_PROCHOT_L
CPU_PWRGD
PM_THRMTRIP_L
DMI_CLK100M_CPU_P
DMI_CLK100M_CPU_N
DPLL_REF_CLKP
DPLL_REF_CLKN
ITPCPU_CLK100M_P
ITPCPU_CLK100M_N
ITPXDP_CLK100M_P
ITPXDP_CLK100M_N
XDP_CPU_CLK100M_P
XDP_CPU_CLK100M_N
XDP_CPU_TDI
XDP_CPU_TDO
XDP_CPU_TMS
XDP_CPU_TCK
XDP_CPUPCH_TRST_L
XDP_BPM_L & lt; 1..0 & gt;
XDP_BPM_L & lt; 7..2 & gt;
XDP_OBSDATA_B & lt; 3..0 & gt;
CPU_CFG & lt; 15..12 & gt;
XDP_CPURST_L
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCIOSENSE
CPU_VCCIOSENSE
CPU_AXG_SENSE
CPU_AXG_SENSE
CPU_VALSENSE
CPU_VALSENSE
CPU_VALSENSE
CPU_VALSENSE
CPU_VALSENSE
CPU_VALSENSE
SENSE_1TO1_P2MM
SENSE_1TO1_P2MM
SENSE_1TO1_P2MM
SENSE_1TO1_P2MM
SENSE_1TO1_P2MM
SENSE_1TO1_P2MM
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE_P
CPU_VCCSENSE_N
CPU_VCCIOSENSE_P
CPU_VCCIOSENSE_N
CPU_AXG_SENSE_P
CPU_AXG_SENSE_N
CPU_VDDQ_SENSE_P
CPU_VDDQ_SENSE_N
CPU_AXG_VALSENSE_P
CPU_AXG_VALSENSE_N
CPU_VCC_VALSENSE_P
CPU_VCC_VALSENSE_N
CPU_SVIDALERT_L
CPU_SVIDSCLK
CPU_SVIDSOUT
CPU_45S
CPU_45S
CPU_45S
CPU_COMP
CPU_COMP
CPU_COMP
CPU_VIDALERT_L
CPU_VIDSCLK
CPU_VIDSOUT
PCIE_CPU_SSD_R2D
PCIE_CPU_SSD_R2D
PCIE_80D
PCIE_80D
PCIE_80D
PCIE_80D
PCIE_80D
PCIE_80D
PCIE_80D
PCIE_80D
CLK_PCIE_80D
CLK_PCIE_80D
PCIE_CPU_TX
PCIE_CPU_TX
PCIE_CPU_TX
PCIE_CPU_TX
PCIE_CPU_RX
PCIE_CPU_RX
PCIE_CPU_RX
PCIE_CPU_RX
CLK_PCIE
CLK_PCIE
PCIE_SSD_R2D_C_P & lt; 3..0 & gt;
PCIE_SSD_R2D_C_N & lt; 3..0 & gt;
PCIE_SSD_R2D_P & lt; 3..0 & gt;
PCIE_SSD_R2D_N & lt; 3..0 & gt;
PCIE_SSD_D2R_C_P & lt; 3..0 & gt;
PCIE_SSD_D2R_C_N & lt; 3..0 & gt;
PCIE_SSD_D2R_P & lt; 3..0 & gt;
PCIE_SSD_D2R_N & lt; 3..0 & gt;
PCIE_CLK100M_SSD_P
PCIE_CLK100M_SSD_N
DP_80D
DP_80D
DP_80D
DP_80D
DP_80D
DP_80D
DP_80D
DP_80D
DP_TX
DP_TX
DP_TX
DP_TX
DP_AUX
DP_AUX
DP_AUX
DP_AUX
DP_TBTSNK0_ML_P & lt; 3..0 & gt;
DP_TBTSNK0_ML_N & lt; 3..0 & gt;
DP_TBTSNK0_ML_C_P & lt; 3..0 & gt;
DP_TBTSNK0_ML_C_N & lt; 3..0 & gt;
DP_TBTSNK0_AUXCH_P
DP_TBTSNK0_AUXCH_N
DP_TBTSNK0_AUXCH_C_P
DP_TBTSNK0_AUXCH_C_N
DP_80D
DP_80D
DP_80D
DP_80D
DP_80D
DP_80D
DP_80D
DP_80D
DP_TX
DP_TX
DP_TX
DP_TX
DP_AUX
DP_AUX
DP_AUX
DP_AUX
DP_TBTSNK1_ML_P & lt; 3..0 & gt;
DP_TBTSNK1_ML_N & lt; 3..0 & gt;
DP_TBTSNK1_ML_C_P & lt; 3..0 & gt;
DP_TBTSNK1_ML_C_N & lt; 3..0 & gt;
DP_TBTSNK1_AUXCH_P
DP_TBTSNK1_AUXCH_N
DP_TBTSNK1_AUXCH_C_P
DP_TBTSNK1_AUXCH_C_N
DP_80D
DP_80D
DP_80D
DP_80D
DP_TX
DP_TX
DP_TX
DP_TX
DP_INT_ML_P & lt; 3..0 & gt;
DP_INT_ML_N & lt; 3..0 & gt;
DP_INT_ML_C_P & lt; 3..0 & gt;
DP_INT_ML_C_N & lt; 3..0 & gt;
DP_80D
DP_80D
DP_80D
DP_80D
DP_80D
DP_80D
DP_AUX
DP_AUX
DP_AUX
DP_AUX
DP_AUX
DP_AUX
DP_INT_AUX_CH_C_P
DP_INT_AUX_CH_C_N
DP_INT_AUXCH_C_P
DP_INT_AUXCH_C_N
DP_INT_AUXCH_P
DP_INT_AUXCH_N
CPU_PECI
PM_SYNC
PM_MEM_PWRGD
Note: CPU_8MIL and CPU_ITP can be converted
back to TABLE_SPACING_RULE
once rdar://10308147 is resolved
WEIGHT
CPU_AGTL
CPU_COMP
CPU_AGTL
CPU_AGTL
CPU_45S
CPU_45S
CPU_45S
0.100 MM
CPU_45S
CPU_45S
CPU_45S
(FSB_CPURST_L)
=27P4_OHM_SE
TABLE_SPACING_RULE_HEAD
?
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
D
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
*
*
SPACING_RULE_SET
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_ITEM
CPU_8MIL_2ANY
CPU_8MIL_2ANY
*
8 MIL
?
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_ASSIGNMENT_ITEM
*
*
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
CPU_COMP
CPU_COMP
*
TABLE_SPACING_RULE_ITEM
CPU_ITP_2ANY
NET_SPACING_TYPE1
CPU_ITP_2ANY
CPU_COMP_2SELF
*
=4x_DIELECTRIC
?
LINE-TO-LINE SPACING
WEIGHT
=6x_DIELECTRIC
?
TABLE_SPACING_ASSIGNMENT_HEAD
LAYER
*
CPU_PROCHOT_L
CPU_PWRGD
PM_THRMTRIP_L
DMI_CLK100M
DMI_CLK100M
DPLL_REF_CLK120M
DPLL_REF_CLK120M
ITPCPU_CLK100M
ITPCPU_CLK100M
ITPCPU_CLK100M
ITPCPU_CLK100M
ITPCPU_CLK100M
ITPCPU_CLK100M
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TCK
XDP_TRST_L
XDP_BPM_L
TABLE_SPACING_RULE_ITEM
CPU_COMP_2SELF
TOP,BOTTOM
TABLE_SPACING_ASSIGNMENT_ITEM
*
CPU_CATERR_L
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM
CPU_COMP
CPU_SM_RCOMP
CPU_SM_RCOMP
CPU_SM_RCOMP
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
CPU_ITP
TABLE_SPACING_RULE_ITEM
CPU_COMP_2OTHER
CPU_COMP_2OTHER
TOP,BOTTOM
=10x_DIELECTRIC
?
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
TABLE_SPACING_RULE_ITEM
CPU_COMP_2SELF
*
=4x_DIELECTRIC
?
CPU_COMP_2OTHER
*
=6x_DIELECTRIC
?
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
SPACING_RULE_SET
LAYER
TABLE_SPACING_ASSIGNMENT_ITEM
CPU_VCCSENSE
CPU_VCCSENSE
*
TABLE_SPACING_RULE_ITEM
CPU_VCCSENSE_2SELF
TOP,BOTTOM
=6x_DIELECTRIC
?
CPU_VCCSENSE_2OTHER
CPU_VCCSENSE_2SELF
TOP,BOTTOM
=10x_DIELECTRIC
?
TABLE_SPACING_ASSIGNMENT_ITEM
CPU_VCCSENSE
*
*
16 17
6 16 64
6 16 64
D
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
CPU_8MIL
6 38
TABLE_SPACING_RULE_ITEM
CPU_VCCSENSE_2OTHER
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
C
LAYER
LINE-TO-LINE SPACING
WEIGHT
=4x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
CPU_VCCSENSE_2SELF
*
TABLE_SPACING_RULE_ITEM
CPU_VCCSENSE_2OTHER
*
=6x_DIELECTRIC
?
PCI-Express Interface Constraints
6
6
6
6 16 64
6 37
6 37 38 51
6
15 38
6 16 64
6 16 64
6 16 64
6 16 64
C
6 12 16 64
6 16
6 16
6 16
16
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
PCIE_80D
*
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
CLK_PCIE_80D
*
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
PCIE Clock Spacing
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_ASSIGNMENT_ITEM
CLK_PCIE
CLK_PCIE
*
CLK_PCIE_2SELF
TABLE_SPACING_RULE_ITEM
CLK_PCIE_2SELF
TOP,BOTTOM
=6x_DIELECTRIC
?
CLK_PCIE_2OTHER
TOP,BOTTOM
=10x_DIELECTRIC
?
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_ASSIGNMENT_ITEM
CLK_PCIE
*
*
CLK_PCIE_2OTHER
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
8 51
9 51
TABLE_SPACING_RULE_ITEM
CLK_PCIE_2SELF
*
=4x_DIELECTRIC
?
CLK_PCIE_2OTHER
*
=6x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
CPU PCIE Spacing
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
PCIE_CPU_TX
PCIE_CPU_TX
*
PCIE_TX2TX
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
=5x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
PCIE_TX2TX
TOP,BOTTOM
TABLE_SPACING_ASSIGNMENT_ITEM
PCIE_CPU_RX
PCIE_CPU_RX
*
PCIE_RX2RX
TABLE_SPACING_RULE_ITEM
PCIE_RX2RX
TOP,BOTTOM
=5x_DIELECTRIC
?
TABLE_SPACING_ASSIGNMENT_ITEM
PCIE_CPU_TX
*_CPU_TX
*
PCIE_TX2OTHERTX
TABLE_SPACING_RULE_ITEM
PCIE_TX2OTHERTX
TOP,BOTTOM
=5x_DIELECTRIC
?
TABLE_SPACING_ASSIGNMENT_ITEM
PCIE_CPU_RX
*_CPU_RX
*
PCIE_RX2OTHERRX
PCIE_CPU_TX
*_CPU_RX
*
PCIE_TX2RX
TABLE_SPACING_RULE_ITEM
PCIE_RX2OTHERRX
TOP,BOTTOM
=5x_DIELECTRIC
?
PCIE_TX2RX
TOP,BOTTOM
=7x_DIELECTRIC
?
TABLE_SPACING_ASSIGNMENT_ITEM
*_CPU_TX
*
PCIE_RX2TX
PCIE_CPU_TX
*_TX
*
PCIE_2OTHERHS
TABLE_SPACING_RULE_ITEM
PCIE_RX2TX
TOP,BOTTOM
=7x_DIELECTRIC
?
PCIE_2OTHERHS
TOP,BOTTOM
=6x_DIELECTRIC
?
TABLE_SPACING_ASSIGNMENT_ITEM
*_TX
*
PCIE_2OTHERHS
PCIE_CPU_TX
*_RX
*
I212
TABLE_SPACING_RULE_ITEM
PCIE_2OTHER
TOP,BOTTOM
?
PCIE_2OTHERHS
=5x_DIELECTRIC
I211
DP_TBT_ML
DP_TBT_ML
TABLE_SPACING_ASSIGNMENT_ITEM
I210
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
PCIE_CPU_RX
*_RX
*
PCIE_2OTHERHS
PCIE_CPU_TX
*
*
PCIE_2OTHER
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
=2.5x_DIELECTRIC
I209
?
I208
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
PCIE_TX2TX
*
I206
DP_TBT_AUXCH
DP_TBT_AUXCH
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
PCIE_CPU_RX
*
*
PCIE_2OTHER
PCIE_RX2RX
*
=2.5x_DIELECTRIC
I207
?
TABLE_SPACING_RULE_ITEM
PCIE_RX2OTHERRX
*
*
=4x_DIELECTRIC
=4x_DIELECTRIC
I205
TABLE_SPACING_RULE_ITEM
PCIE_TX2OTHERTX
PCH PCIE Spacing
I204
?
?
I203
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
DP_TBT_ML
DP_TBT_ML
TABLE_SPACING_RULE_ITEM
PCIE_TX2RX
*
=6x_DIELECTRIC
?
PCIE_RX2TX
*
=6x_DIELECTRIC
I202
?
TABLE_SPACING_ASSIGNMENT_ITEM
PCIE_PCH_TX
PCIE_PCH_TX
*
PCIE_TX2TX
PCIE_PCH_RX
PCIE_PCH_RX
*
PCIE_RX2RX
I201
TABLE_SPACING_RULE_ITEM
I200
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
PCIE_2OTHERHS
*
=4x_DIELECTRIC
I199
?
DP_TBT_AUXCH
DP_TBT_AUXCH
TABLE_SPACING_ASSIGNMENT_ITEM
PCIE_PCH_TX
*_PCH_TX
*
PCIE_TX2OTHERTX
PCIE_PCH_RX
*_PCH_RX
*
I198
12 30
12 30
30 64
B
30 64
12 30 64
12 30 64
12 30 64
PCIe SSD
12 30 64
25
25
5 25
5 25
25
25
13 25
13 25
25
25
5 18 25
5 18 25
25
25
13 18 25
PCIE_RX2OTHERRX
TABLE_SPACING_RULE_ITEM
PCIE_2OTHER
*
=3x_DIELECTRIC
?
I197
TABLE_SPACING_ASSIGNMENT_ITEM
A
8 51
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
PCIE_CPU_RX
PCIE_CPU_SSD_D2R
PCIE_CPU_SSD_D2R
PCIE_CLK100M_SSD
PCIE_CLK100M_SSD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
PCIE_CPU_RX
8 51
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
B
8 51
DP_INT_ML
DP_INT_ML
TABLE_SPACING_ASSIGNMENT_ITEM
PCIE_PCH_TX
*_PCH_RX
*
PCIE_TX2RX
PCIE_PCH_RX
*_PCH_TX
*
PCIE_RX2TX
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
PCIE_PCH_TX
*_TX
*
PCIE_2OTHERHS
PCIE_PCH_RX
*_TX
*
PCIE_2OTHERHS
13 18 25
60 64
SYNC_MASTER=CONSTRAINTS
60 64
SYNC_DATE=09/25/2012
PAGE TITLE
5 60 64
CPU Constraints
5 60 64
DRAWING NUMBER
TABLE_SPACING_ASSIGNMENT_ITEM
I215
TABLE_SPACING_ASSIGNMENT_ITEM
PCIE_PCH_TX
*_RX
*
*_RX
*
Note: DisplayPort tables are on Page 113
PCIE_2OTHERHS
PCIE_PCH_RX
PCIE_2OTHERHS
TABLE_SPACING_ASSIGNMENT_ITEM
I214
DP_INT_AUXCH
DP_INT_AUXCH
DP_INT_AUXCH
DP_INT_AUXCH
TABLE_SPACING_ASSIGNMENT_ITEM
PCIE_PCH_TX
*
*
PCIE_2OTHER
PCIE_PCH_RX
*
*
PCIE_2OTHER
TABLE_SPACING_ASSIGNMENT_ITEM
SOURCE: 471984_Chief_River_MS_PDG_1.0 and the spacing rule is adjusted per SI team feedback.
8
7
6
5
4
3
60 64
Apple Inc.
DP
60 64
5 60
R
NOTICE OF PROPRIETARY PROPERTY:
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
5 60
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
PAGE
111 OF 121
SHEET
67 OF 76
1
A
8
7
6
5
SATA Interface Constraints
4
3
2
1
PCH Net Properties
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
SATA_80D
*
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
SPACING_RULE_SET
LAYER
NET_TYPE
PHYSICAL
SPACING
=80_OHM_DIFF
ELECTRICAL_CONSTRAINT_SET
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_HEAD
LINE-TO-LINE SPACING
WEIGHT
=4x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
SATA_ICOMP
*
D
D
SATA_ICOMP
PCH_SATAICOMP
USB_80D
USB_80D
USB_80D
USB_80D
USB_80D
USB_80D
USB_80D
USB_80D
USB_80D
USB_80D
USB_80D
USB_80D
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB_HUB_UP_P
USB_HUB_UP_N
USB_BT_P
USB_BT_N
USB_BT_CONN_P
USB_BT_CONN_N
USB_BT_WAKE_P
USB_BT_WAKE_N
USB_TPAD_P
USB_TPAD_N
USB_TPAD_CONN_P
USB_TPAD_CONN_N
USB_80D
USB_80D
USB_80D
USB_80D
USB_80D
USB_80D
USB
USB
USB
USB
USB
USB
TPAD_SPI_MOSI_USB_P
TPAD_SPI_MISO_USB_N
USB_TPAD_M_P
USB_TPAD_M_N
USB_SDCARD_P
USB_SDCARD_N
SPI_45S
SPI_45S
SPI_45S
SPI
SPI
SPI
TPAD_SPI_MOSI
TPAD_SPI_MISO
TPAD_SPI_CLK
PCH_SATA_ICOMP
USB_HUB1_UP
USB_HUB1_UP
USB_BT
USB_BT
USB_TPAD
USB_TPAD
USB_TPAD_M
USB_TPAD_M
USB_SDCARD
USB_SDCARD
C
SOURCE: 471984_Chief_River_MS_PDG_1.0 and the spacing rule is adjusted per SI team feedback.
UART Interface Constraints
14 29
14 29
29 64
29 64
14 36 64
USB Hucopyb nets
14 36 64
C
15 36
15 36
15 36
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
UART_45S
*
=45_OHM_SE
=45_OHM_SE
=45_OHM_SE
=45_OHM_SE
=45_OHM_SE
=45_OHM_SE
SPACING_RULE_SET
LAYER
TP SPI nets
TABLE_PHYSICAL_RULE_ITEM
=2x_DIELECTRIC
USB2_EXTA
USB2_EXTA
USB2_EXTA
USB2_EXTA
USB3_EXTA_RX
USB3_EXTA_RX
USB3_EXTA_TX
USB3_EXTA_TX
USB 2.0 Interface Constraints
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM
PCH_USB_RBIAS
*
=STANDARD
8 MIL
8 MIL
=STANDARD
=STANDARD
=STANDARD
USB_80D
*
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
SPACING_RULE_SET
LAYER
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_HEAD
LINE-TO-LINE SPACING
=2x_DIELECTRIC
TABLE_SPACING_RULE_HEAD
WEIGHT
SPACING_RULE_SET
?
LAYER
LINE-TO-LINE SPACING
WEIGHT
=4x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
USB
*
TABLE_SPACING_RULE_ITEM
USB
TOP,BOTTOM
SOURCE: Calpella Platform Design Guide for Ibex Peak M (DG-398905-398905_v1.5), Section 3.8
USB 3.0 Interface Constraints
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
USB3_PCH_TX
USB3_PCH_TX
*
USB3_TX2TX
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
USB3_PCH_RX
*
USB3_RX2RX
TOP,BOTTOM
?
TABLE_SPACING_RULE_ITEM
USB3_RX2RX
TOP,BOTTOM
=5x_DIELECTRIC
?
TABLE_SPACING_ASSIGNMENT_ITEM
USB3_PCH_TX
*_PCH_TX
*
USB3_TX2OTHERTX
USB3_PCH_RX
*_PCH_RX
*
USB3_RX2OTHERRX
TABLE_SPACING_RULE_ITEM
USB3_TX2OTHERTX
TOP,BOTTOM
=5x_DIELECTRIC
?
USB3_RX2OTHERRX
TOP,BOTTOM
=5x_DIELECTRIC
?
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
USB3_PCH_TX
*_PCH_RX
*
USB3_TX2RX
USB3_PCH_RX
*_PCH_TX
*
USB3_RX2TX
USB3_TX2RX
TOP,BOTTOM
=7x_DIELECTRIC
?
USB3_RX2TX
TOP,BOTTOM
=7x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
*_TX
*
USB3_2OTHERHS
USB3_PCH_RX
*_TX
*
USB3_2OTHERHS
USB3_EXTB_TX
USB3_EXTB_TX
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
USB3_PCH_TX
USB_EXTB
USB_EXTB
USB3_EXTB_RX
USB3_EXTB_RX
WEIGHT
=5x_DIELECTRIC
TABLE_SPACING_RULE_ITEM
USB3_TX2TX
TABLE_SPACING_ASSIGNMENT_ITEM
USB3_PCH_RX
USB3_2OTHERHS
TOP,BOTTOM
=6x_DIELECTRIC
*
TOP,BOTTOM
=5x_DIELECTRIC
?
USB3_SD_RX
USB3_SD_RX
USB3_SD_TX
USB3_SD_TX
TABLE_SPACING_RULE_ITEM
USB3_2OTHERHS
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
USB3_PCH_RX
*_RX
*
USB3_2OTHERHS
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
USB3_PCH_TX
*
*
USB3_2OTHER
USB3_TX2TX
*
=2.5x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
USB3_PCH_RX
*
*
USB3_2OTHER
USB3_RX2RX
*
=2.5x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
USB3_TX2OTHERTX
*
=4x_DIELECTRIC
?
PCH_USB_RBIAS
PCH_DIFFCLK_UNUSED_
PCH_DIFFCLK_UNUSED_
PCH_DIFFCLK_UNUSED_
PCH_DIFFCLK_UNUSED_
PCH_DIFFCLK_UNUSED_
PCH_DIFFCLK_UNUSED_
TABLE_SPACING_RULE_ITEM
USB3_RX2OTHERRX
*
=4x_DIELECTRIC
?
USB3_TX2RX
*
=6x_DIELECTRIC
?
USB3_RX2TX
*
=6x_DIELECTRIC
?
USB3_2OTHERHS
*
=4x_DIELECTRIC
?
USB3_2OTHER
*
=3x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
A
USB3_SD_D2R_P
USB3_SD_D2R_N
USB3_SD_R2D_C_P
USB3_SD_R2D_C_N
USB3_SD_D2R_C_P
USB3_SD_D2R_C_N
USB3_SD_R2D_P
USB3_SD_R2D_N
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
PCH_USB_RBIAS
PCIE_CLK100M_PCH_P
PCIE_CLK100M_PCH_N
PCH_CLK96M_DOT_P
PCH_CLK96M_DOT_N
PCH_CLK100M_SATA_P
PCH_CLK100M_SATA_N
PCH_CLK14P3M_REFCLK
35 37 38
35 37 38
35
35
35
35
14 35
USB EXTA nets (Right USB port)
14 35
35
35
14 35
14 35
14 61 65
14 61 65
B
14 61 65
14 61 65
61 65
61 65
61 65
61 65
USB EXTB nets (Left USB port)
14 61 65
14 61 65
?
USB3_2OTHER
TABLE_SPACING_ASSIGNMENT_ITEM
*_RX
USB3_PCH_RX
USB3_PCH_RX
USB3_PCH_TX
USB3_PCH_TX
USB3_PCH_RX
USB3_PCH_RX
USB3_PCH_TX
USB3_PCH_TX
14 35
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
USB3_PCH_TX
USB
USB
USB3_PCH_RX
USB3_PCH_RX
USB3_PCH_RX
USB3_PCH_RX
USB3_PCH_TX
USB3_PCH_TX
USB3_PCH_TX
USB3_PCH_TX
14 35
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
B
USB_EXTB_P
USB_EXTB_N
USB3_EXTB_D2R_P
USB3_EXTB_D2R_N
USB3_EXTB_D2R_RC_P
USB3_EXTB_D2R_RC_N
USB3_EXTB_R2D_P
USB3_EXTB_R2D_N
USB3_EXTB_R2D_C_P
USB3_EXTB_R2D_C_N
USB_80D
USB_80D
USB_80D
USB_80D
USB_80D
USB_80D
USB_80D
USB_80D
?
*
USB_EXTA_P
USB_EXTA_N
SMC_DEBUGPRT_TX_L
SMC_DEBUGPRT_RX_L
USB2_EXTA_MUXED_P
USB2_EXTA_MUXED_N
USB2_EXTA_MUXED_F_P
USB2_EXTA_MUXED_F_N
USB3_EXTA_D2R_P
USB3_EXTA_D2R_N
USB3_EXTA_R2D_P
USB3_EXTA_R2D_N
USB3_EXTA_D2R_F_P
USB3_EXTA_D2R_F_N
USB3_EXTA_R2D_F_P
USB3_EXTA_R2D_F_N
USB3_EXTA_R2D_C_P
USB3_EXTA_R2D_C_N
USB_80D
USB_80D
UART_45S
UART_45S
USB_80D
USB_80D
USB_80D
USB_80D
USB_80D
USB_80D
USB_80D
USB_80D
USB_80D
USB_80D
USB_80D
USB_80D
USB_80D
USB_80D
WEIGHT
TABLE_SPACING_RULE_ITEM
UART
USB
USB
UART
UART
USB
USB
USB
USB
USB3_PCH_RX
USB3_PCH_RX
USB3_PCH_TX
USB3_PCH_TX
USB3_PCH_RX
USB3_PCH_RX
USB3_PCH_TX
USB3_PCH_TX
USB3_PCH_TX
USB3_PCH_TX
USB_80D
USB_80D
USB_80D
USB_80D
USB_80D
USB_80D
USB_80D
USB_80D
USB_80D
USB_80D
USB_EXTA
USB_EXTA
TABLE_SPACING_RULE_HEAD
LINE-TO-LINE SPACING
PCH_USB_RBIAS
CLK_PCIE_80D
CLK_PCIE_80D
CLK_PCIE_80D
CLK_PCIE_80D
CLK_PCIE_80D
CLK_PCIE_80D
CPU_45S
14 34 65
14 34 65
14 34 65
14 34 65
34
34
34
34
14
SYNC_MASTER=CLEAN_J43
SOURCE: 471984_Cheif_River_MS_PDG_1.0 and the spacing rule is adjusted per SI team feedback.
SYNC_DATE=11/13/2012
PAGE TITLE
PCH Constraints 1
DRAWING NUMBER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
112 OF 121
SHEET
68 OF 76
1
A
8
7
6
5
LPC Bus Constraints
4
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
ALLOW ROUTE
ON LAYER?
LAYER
3
2
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
ELECTRICAL_CONSTRAINT_SET
NET_TYPE
PHYSICAL
SPACING
Clock Net Properties
TABLE_PHYSICAL_RULE_ITEM
LPC_45S
*
=45_OHM_SE
=45_OHM_SE
=45_OHM_SE
=45_OHM_SE
=STANDARD
=STANDARD
CLK_LPC_45S
*
=45_OHM_SE
=45_OHM_SE
=45_OHM_SE
=45_OHM_SE
=STANDARD
=STANDARD
SPACING_RULE_SET
LAYER
LPC_AD
LPC_FRAME_L
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_HEAD
LINE-TO-LINE SPACING
=3x_DIELECTRIC
LPC_CLK33M
WEIGHT
?
TABLE_SPACING_RULE_ITEM
LPC
*
LPC_CLK33M
TABLE_SPACING_RULE_ITEM
CLK_LPC
D
*
=4x_DIELECTRIC
?
LPC_45S
LPC_45S
LPC_45S
CLK_LPC_45S
CLK_LPC_45S
CLK_LPC_45S
CLK_LPC_45S
LPC
LPC
LPC
CLK_LPC
CLK_LPC
CLK_LPC
CLK_LPC
LPC_AD & lt; 3..0 & gt;
LPC_FRAME_L
LPCPLUS_RESET_L
LPC_CLK24M_SMC
LPC_CLK24M_SMC_R
LPC_CLK24M_LPCPLUS
LPC_CLK24M_LPCPLUS_R
ELECTRICAL_CONSTRAINT_SET
SMBus Interface Constraints
14 37 46 64
SYSCLK_CLK32K_RTC
CLK_SLOW_45S
CLK_SLOW
SYSCLK_CLK32K_RTCX1
SYSCLK_CLK25M_SB
CLK_25M_45S
CLK_25M_45S
CLK_25M_45S
CLK_25M_45S
CLK_25M_45S
CLK_25M_45S
CLK_25M
CLK_25M
CLK_25M
CLK_25M
CLK_25M
CLK_25M
SYSCLK_CLK25M_CAMERA
CLK25M_CAM_CLKP
CLK25M_CAM_XTALP_R
CLK25M_CAM_XTALP
CLK25M_CAM_XTALN
CLK25M_CAM_CLKN
CLK_25M_45S
CLK_25M_45S
CLK_25M
CLK_25M
SYSCLK_CLK25M_TBT
SYSCLK_CLK25M_TBT_R
CLK_25M
CLK_25M
CLK_25M
CLK_25M
CLK_25M
CLK_25M
SYSCLK_CLK25M_X1
SYSCLK_CLK25M_X2
SYSCLK_CLK25M_X2_R
SDCLK_CLK25M_X2
SDCLK_CLK25M_X2_R
SDSCLK_CLK25M_X1
18 46 64
17 37
12 17
17 46 64
12 17
SMBUS_PCH_CLK
SMBUS_PCH_DATA
SMBUS_PCH_0_CLK
SMBUS_PCH_0_DATA
SMBUS_SMC_1_S0_SCL
SMBUS_SMC_1_S0_SDA
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
SMB_45S_R_50S
TOP,BOTTOM
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
SMB_45S_R_50S
*
=45_OHM_SE
=45_OHM_SE
=45_OHM_SE
=45_OHM_SE
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
=STANDARD
=STANDARD
HDA_45S
HDA_45S
HDA_45S
HDA_45S
HDA_45S
HDA_45S
HDA_45S
HDA_45S
HDA_45S
HDA
HDA
HDA
HDA
HDA
HDA
HDA
HDA
HDA
HDA_BIT_CLK
HDA_BIT_CLK_R
HDA_SYNC
HDA_SYNC_R
HDA_RST_R_L
HDA_RST_L
HDA_SDIN0
HDA_SDOUT
HDA_SDOUT_R
CLK_SLOW_45S
CLK_SLOW_45S
SPI_45S
SPI_45S
SPI_45S
SPI_45S
SPI_45S
SPI_45S
SPI_45S
SPI_45S
SPI_45S
SPI_45S
SPI_45S
SPI_45S
SPI_45S
SPI_45S
SPI_45S
SPI_45S
CLK_SLOW
CLK_SLOW
SPI
SPI
SPI
SPI
SPI
SPI
SPI
SPI
SPI
SPI
SPI
SPI
SPI
SPI
SPI
SPI
PM_CLK32K_SUSCLK_R
SMC_CLK32K
SPI_CLK_R
SPI_CLK
SPI_MOSI_R
SPI_MOSI
SPI_MISO
SPI_MISO_R
SPI_CS0_R_L
SPI_CS0_L
SPI_SMC_CLK
SPI_SMC_MOSI
SPI_SMC_MISO
SPI_SMC_CS_L
SPI_MLB_CLK
SPI_MLB_MOSI
SPI_MLB_MISO
SPI_MLB_CS_L
PCIE_80D
PCIE_80D
PCIE_80D
PCIE_80D
PCIE_80D
PCIE_80D
CLK_PCIE_80D
CLK_PCIE_80D
PCIE_PCH_TX
PCIE_PCH_TX
PCIE_PCH_TX
PCIE_PCH_TX
PCIE_PCH_RX
PCIE_PCH_RX
CLK_PCIE
CLK_PCIE
PCIE_AP_R2D_P
PCIE_AP_R2D_N
PCIE_AP_R2D_C_P
PCIE_AP_R2D_C_N
PCIE_AP_D2R_P
PCIE_AP_D2R_N
PCIE_CLK100M_AP_P
PCIE_CLK100M_AP_N
PCIE_80D
PCIE_80D
PCIE_80D
PCIE_80D
PCIE_80D
PCIE_80D
PCIE_80D
PCIE_80D
CLK_PCIE_80D
CLK_PCIE_80D
PCIE_PCH_TX
PCIE_PCH_TX
PCIE_PCH_TX
PCIE_PCH_TX
PCIE_PCH_RX
PCIE_PCH_RX
PCIE_PCH_RX
PCIE_PCH_RX
CLK_PCIE
CLK_PCIE
PCIE_TBT_R2D_P & lt; 3..0 & gt;
PCIE_TBT_R2D_N & lt; 3..0 & gt;
PCIE_TBT_R2D_C_P & lt; 3..0 & gt;
PCIE_TBT_R2D_C_N & lt; 3..0 & gt;
PCIE_TBT_D2R_P & lt; 3..0 & gt;
PCIE_TBT_D2R_N & lt; 3..0 & gt;
PCIE_TBT_D2R_C_P & lt; 3..0 & gt;
PCIE_TBT_D2R_C_N & lt; 3..0 & gt;
PCIE_CLK100M_TBT_P
PCIE_CLK100M_TBT_N
CLK_PCIE
CLK_PCIE
PCH_45S
PCH_45S
PCH_45S
PCH_45S
PCH_ITP
PCH_ITP
PCH_ITP
PCH_ITP
XDP_PCH_TDI
XDP_PCH_TDO
XDP_PCH_TMS
XDP_PCH_TCK
PCIE_80D
PCIE_80D
PCIE_80D
PCIE_80D
PCIE_80D
PCIE_80D
PCIE_80D
PCIE_80D
CLK_PCIE_80D
CLK_PCIE_80D
CLK_PCIE_80D
CLK_PCIE_80D
PCIE_PCH_TX
PCIE_PCH_TX
PCIE_PCH_TX
PCIE_PCH_TX
PCIE_PCH_RX
PCIE_PCH_RX
PCIE_PCH_RX
PCIE_PCH_RX
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
PCIE_CAMERA_R2D_P
PCIE_CAMERA_R2D_N
PCIE_CAMERA_R2D_C_P
PCIE_CAMERA_R2D_C_N
PCIE_CAMERA_D2R_P
PCIE_CAMERA_D2R_N
PCIE_CAMERA_D2R_C_P
PCIE_CAMERA_D2R_C_N
PCIE_CLK100M_CAMERA_P
PCIE_CLK100M_CAMERA_N
PCIE_CLK100M_CAMERA_C_P
PCIE_CLK100M_CAMERA_C_N
14 16 19 25 40 56
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_ITEM
SMB
*
=2x_DIELECTRIC
?
HDA_SYNC
HD Audio Interface Constraints
HDA_RST_L
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM
HDA_45S
*
=45_OHM_SE
=45_OHM_SE
=45_OHM_SE
=45_OHM_SE
=STANDARD
=STANDARD
HDA_SDIN0
HDA_SDOUT
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
SYSCLK_CLK25M_TBT
14 16 19 25 40 56
31 32
32
32
32
D
31 32
17 25
25
14 40
14 40
14 32 37 40 43 44 64
73
14 32 37 40 43 44 64
73
TABLE_SPACING_RULE_HEAD
LAYER
17 32
PEG_CLK100M_P
PEG_CLK100M_N
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TCK
DIFFPAIR NECK GAP
SMBUS_PCH_CLK
SMBUS_PCH_DATA
SML_PCH_0_CLK
SML_PCH_0_DATA
SMBUS_SMC_1_S0_SCL
SMBUS_SMC_1_S0_SDA
CLK_PCIE_80D
CLK_PCIE_80D
=50_OHM_SE
DIFFPAIR PRIMARY GAP
SMB
SMB
SMB
SMB
SMB
SMB
PCIE_CAM
PCIE_CAM
LAYER
SMB_45S_R_50S
SMB_45S_R_50S
SMB_45S_R_50S
SMB_45S_R_50S
SMB_45S_R_50S
SMB_45S_R_50S
HDA_BIT_CLK
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
NET_TYPE
PHYSICAL
SPACING
14 37 46 64
SOURCE: Calpella Platform Design Guide for Ibex Peak M (DG-398905-398905_v1.5), Section 3.15
SPACING_RULE_SET
1
PCH Net Properties
12 61 65
12
SYSCLK_CLK25M_XTAL
CLK_25M_45S
CLK_25M_45S
CLK_25M_45S
CLK_25M_45S
CLK_25M_45S
CLK_25M_45S
17
17
17
34
34 75
34
12 61 65
12
12
12 61 65
12 61 65
12 61 65
12 17
WEIGHT
TABLE_SPACING_RULE_ITEM
HDA
*
=2x_DIELECTRIC
?
PM_SUS_CLK
SOURCE: Calpella Platform Design Guide for Ibex Peak M (DG-398905-398905_v1.5), Section 3.15
SPI_CLK
SIO Signal Constraints
SPI_MOSI
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
SPI_MISO
TABLE_PHYSICAL_RULE_ITEM
C
CLK_SLOW_45S
*
=45_OHM_SE
=45_OHM_SE
=45_OHM_SE
=45_OHM_SE
=STANDARD
=STANDARD
SPI_CS0
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_ITEM
CLK_SLOW
*
=4x_DIELECTRIC
?
SPI Interface Constraints
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
SPI_45S
*
=45_OHM_SE
=45_OHM_SE
=45_OHM_SE
=45_OHM_SE
=STANDARD
=STANDARD
TABLE_PHYSICAL_RULE_ITEM
13 38
37 38
14 46
46
14 46
46
14 46
C
46
14 46
46
37 46
37 46
37 46
37 46
46
46
46
46
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
=4x_DIELECTRIC
?
PCIE_AP_R2D
PCIE_AP_R2D
TABLE_SPACING_RULE_ITEM
SPI
*
XDP Constraints
PCIE_AP_D2R
PCIE_AP_D2R
PCIE_CLK100M_AP
PCIE_CLK100M_AP
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM
PCH_45S
*
=45_OHM_SE
=45_OHM_SE
=45_OHM_SE
=45_OHM_SE
=STANDARD
=STANDARD
29 64
29 64
14 29
14 29
14 29 64
14 29 64
12 29 64
12 29 64
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
PCIE_TBT_R2D
PCIE_TBT_R2D
WEIGHT
=2:1_SPACING
?
TABLE_SPACING_RULE_ITEM
PCH_ITP
*
DisplayPort
PCIE_TBT_D2R
PCIE_TBT_D2R
TABLE_PHYSICAL_RULE_HEAD
B
PHYSICAL_RULE_SET
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM
DP_80D
*
SPACING_RULE_SET
LAYER
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
TABLE_SPACING_RULE_HEAD
LINE-TO-LINE SPACING
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
DP_2DP
*
=3x_DIELECTRIC
=4x_DIELECTRIC
?
DP_2OTHER
*
=3x_DIELECTRIC
?
DP_AUX
*
=3x_DIELECTRIC
14 25
14 25
14 25
14 25
B
25
25
12 25
12 25
TABLE_SPACING_RULE_ITEM
?
*
25
WEIGHT
TABLE_SPACING_RULE_ITEM
DP_2OTHERHS
PCIE_CLK100M_TBT
PCIE_CLK100M_TBT
TABLE_SPACING_RULE_HEAD
WEIGHT
25
DP_2DP
?
TOP,BOTTOM
=4x_DIELECTRIC
?
DP_2OTHERHS
TOP,BOTTOM
=6x_DIELECTRIC
?
DP_2OTHER
TOP,BOTTOM
=4x_DIELECTRIC
?
DP_AUX
TOP,BOTTOM
=4x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
12 16 64
12 16 64
12 16 64
12 16 64
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM
DP_TX
DP_TX
*
DP_2DP
DP_TX
*_TX
*
DP_2OTHERHS
DP_TX
*_RX
*
DP_2OTHERHS
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
PCIE_CAM
PCIE_CAM
TABLE_SPACING_ASSIGNMENT_ITEM
DP_TX
*
*
DP_2OTHER
PCIE_CLK100M_CAM
PCIE_CLK100M_CAM
A
31 32
31 32
14 32
14 32
14 32
14 32
31 32
31 32
12 32
12 32
31 32
31 32
SYNC_MASTER=J41_MLB
System Clock Signal Constraints
SYNC_DATE=12/14/2012
PAGE TITLE
PCH Constraints 2
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
CLK_SLOW_45S
*
=45_OHM_SE
=45_OHM_SE
=45_OHM_SE
=45_OHM_SE
=STANDARD
=STANDARD
CLK_25M_45S
*
=45_OHM_SE
=45_OHM_SE
=45_OHM_SE
=45_OHM_SE
=STANDARD
=STANDARD
DRAWING NUMBER
TABLE_PHYSICAL_RULE_ITEM
Apple Inc.
TABLE_PHYSICAL_RULE_ITEM
R
NOTICE OF PROPRIETARY PROPERTY:
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
=2x_DIELECTRIC
?
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
TABLE_SPACING_RULE_ITEM
CLK_25M
*
8
& lt; E4LABEL & gt;
BRANCH
WEIGHT
TABLE_SPACING_RULE_ITEM
*
CLK_SLOW
=5x_DIELECTRIC
?
NOTE: 25MHz system clocks very sensitive to noise.
7
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; BRANCH & gt;
PAGE
113 OF 121
SHEET
69 OF 76
1
A
8
7
Memory Bus Constraints
6
5
4
3
2
Memory Net Properties
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
MEM_40S
*
=40_OHM_SE
=40_OHM_SE
=40_OHM_SE
=40_OHM_SE
=40_OHM_SE
=40_OHM_SE
MEM_50S
*
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
ELECTRICAL_CONSTRAINT_SET
1
NET_TYPE
PHYSICAL
SPACING
TABLE_PHYSICAL_RULE_ITEM
MEM_A_CLK0
MEM_A_CLK0
MEM_A_CLK1
MEM_A_CLK1
MEM_A_CTRL
MEM_A_CTRL
MEM_A_CKE0
MEM_A_CKE1
MEM_A_CMD0
MEM_A_CMD1
MEM_A_DQ_BYTE0
MEM_A_DQ_BYTE1
MEM_A_DQ_BYTE2
MEM_A_DQ_BYTE3
MEM_A_DQ_BYTE4
MEM_A_DQ_BYTE5
MEM_A_DQ_BYTE6
MEM_A_DQ_BYTE7
MEM_A_DQS0
MEM_A_DQS0
MEM_A_DQS1
MEM_A_DQS1
MEM_A_DQS2
MEM_A_DQS2
MEM_A_DQS3
MEM_A_DQS3
MEM_A_DQS4
MEM_A_DQS4
MEM_A_DQS5
MEM_A_DQS5
MEM_A_DQS6
MEM_A_DQS6
MEM_A_DQS7
MEM_A_DQS7
MEM_70D
*
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
=70_OHM_DIFF
MEM_73D
*
=73_OHM_DIFF
=73_OHM_DIFF
=73_OHM_DIFF
=73_OHM_DIFF
=73_OHM_DIFF
=73_OHM_DIFF
TABLE_PHYSICAL_RULE_ITEM
D Spacing Rule Sets
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_ITEM
MEM_DATA2SELF
*
=2x_DIELECTRIC
?
MEM_DATA2OTHERMEM
*
=8x_DIELECTRIC
?
MEM_DQS2OWNDATA
*
=3x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
MEM_CMD2CMD
*
=3x_DIELECTRIC
?
MEM_CMD2CTRL
*
=3x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
*
MEM_CTRL2CTRL
=3x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
MEM_CLK2CLK
*
=6x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
*
MEM_2OTHERMEM
=4x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
MEM_2PWR
*
=2x_DIELECTRIC
10000
TABLE_SPACING_RULE_ITEM
MEM_2GND
*
=2x_DIELECTRIC
10000
MEM_2OTHER
*
=6x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
Memory to Power Spacing
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
TABLE_PHYSICAL_ASSIGNMENT_HEAD
NET_PHYSICAL_TYPE
AREA_TYPE
PHYSICAL_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_PWR
MEM_*
*
MEM_2PWR
MEM_PWR
*
*
DEFAULT
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_PHYSICAL_ASSIGNMENT_ITEM
MEM_70D
MEM_40S
MEM_TERM
MEM_73D
MEM_50S
TABLE_PHYSICAL_ASSIGNMENT_ITEM
MEM_TERM
C Memory to GND Spacing
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
GND
MEM_*
*
MEM_2GND
TABLE_SPACING_ASSIGNMENT_ITEM
Memory Bus Spacing Group Assignments
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_A_DQS_0 MEM_A_DATA_0
*
MEM_DQS2OWNDATA
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_A_DQS_0
*
*
MEM_2OTHER
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_A_DQS_1 MEM_A_DATA_1
*
MEM_DQS2OWNDATA
MEM_A_DQS_2 MEM_A_DATA_2
*
MEM_DQS2OWNDATA
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_A_DQS_1
*
*
MEM_2OTHER
MEM_A_DQS_2
*
*
MEM_2OTHER
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_A_DQS_3 MEM_A_DATA_3
*
MEM_DQS2OWNDATA
MEM_A_DQS_4 MEM_A_DATA_4
*
MEM_DQS2OWNDATA
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_A_DQS_3
*
*
MEM_2OTHER
MEM_A_DQS_4
*
*
MEM_2OTHER
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_A_DQS_5 MEM_A_DATA_5
*
MEM_DQS2OWNDATA
MEM_A_DQS_6 MEM_A_DATA_6
*
MEM_DQS2OWNDATA
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_A_DQS_5
*
*
MEM_2OTHER
MEM_A_DQS_6
*
*
MEM_2OTHER
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_A_DQS_7 MEM_A_DATA_7
*
MEM_DQS2OWNDATA
MEM_B_DQS_0 MEM_B_DATA_0
*
MEM_DQS2OWNDATA
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_A_DQS_7
*
*
MEM_2OTHER
MEM_B_DQS_0
*
*
MEM_2OTHER
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_B_DQS_1 MEM_B_DATA_1
*
MEM_DQS2OWNDATA
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_B_DQS_1
*
*
MEM_2OTHER
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_B_DQS_2 MEM_B_DATA_2
*
MEM_DQS2OWNDATA
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_B_DQS_2
*
*
MEM_2OTHER
TABLE_SPACING_ASSIGNMENT_ITEM
B
MEM_B_DQS_3 MEM_B_DATA_3
*
MEM_DQS2OWNDATA
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_B_DQS_3
*
*
MEM_2OTHER
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_B_DQS_4 MEM_B_DATA_4
*
MEM_DQS2OWNDATA
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_B_DQS_4
*
*
MEM_2OTHER
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_B_DQS_5 MEM_B_DATA_5
*
MEM_DQS2OWNDATA
MEM_B_DQS_6 MEM_B_DATA_6
*
MEM_DQS2OWNDATA
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_B_DQS_5
*
*
MEM_2OTHER
MEM_B_DQS_6
*
*
MEM_2OTHER
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_B_DQS_7 MEM_B_DATA_7
*
SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_B_DQS_7
*
*
MEM_2OTHER
MEM_A_DATA_0
MEM_DQS2OWNDATA
*
*
MEM_2OTHER
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CLK
MEM_CLK
MEM_CLK
MEM_CLK
MEM_CTRL
MEM_CTRL
MEM_CMD
MEM_CMD
MEM_CMD
MEM_CMD
MEM_A_DATA_0
MEM_A_DATA_1
MEM_A_DATA_2
MEM_A_DATA_3
MEM_A_DATA_4
MEM_A_DATA_5
MEM_A_DATA_6
MEM_A_DATA_7
MEM_A_DQS_0
MEM_A_DQS_0
MEM_A_DQS_1
MEM_A_DQS_1
MEM_A_DQS_2
MEM_A_DQS_2
MEM_A_DQS_3
MEM_A_DQS_3
MEM_A_DQS_4
MEM_A_DQS_4
MEM_A_DQS_5
MEM_A_DQS_5
MEM_A_DQS_6
MEM_A_DQS_6
MEM_A_DQS_7
MEM_A_DQS_7
MEM_A_CLK_P & lt; 0 & gt;
MEM_A_CLK_N & lt; 0 & gt;
MEM_A_CLK_P & lt; 1 & gt;
MEM_A_CLK_N & lt; 1 & gt;
MEM_A_CS_L & lt; 1..0 & gt;
MEM_A_ODT & lt; 0 & gt;
MEM_A_CKE & lt; 1..0 & gt;
MEM_A_CKE & lt; 3..2 & gt;
MEM_A_CAA & lt; 9..0 & gt;
MEM_A_CAB & lt; 9..0 & gt;
MEM_A_DQ & lt; 7..0 & gt;
MEM_A_DQ & lt; 15..8 & gt;
MEM_A_DQ & lt; 23..16 & gt;
MEM_A_DQ & lt; 31..24 & gt;
MEM_A_DQ & lt; 39..32 & gt;
MEM_A_DQ & lt; 47..40 & gt;
MEM_A_DQ & lt; 55..48 & gt;
MEM_A_DQ & lt; 63..56 & gt;
MEM_A_DQS_P & lt; 0 & gt;
MEM_A_DQS_N & lt; 0 & gt;
MEM_A_DQS_P & lt; 1 & gt;
MEM_A_DQS_N & lt; 1 & gt;
MEM_A_DQS_P & lt; 2 & gt;
MEM_A_DQS_N & lt; 2 & gt;
MEM_A_DQS_P & lt; 3 & gt;
MEM_A_DQS_N & lt; 3 & gt;
MEM_A_DQS_P & lt; 4 & gt;
MEM_A_DQS_N & lt; 4 & gt;
MEM_A_DQS_P & lt; 5 & gt;
MEM_A_DQS_N & lt; 5 & gt;
MEM_A_DQS_P & lt; 6 & gt;
MEM_A_DQS_N & lt; 6 & gt;
MEM_A_DQS_P & lt; 7 & gt;
MEM_A_DQS_N & lt; 7 & gt;
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_CLK
MEM_CLK
MEM_CLK
MEM_CLK
MEM_CTRL
MEM_CTRL
MEM_CMD
MEM_CMD
MEM_CMD
MEM_CMD
MEM_B_DATA_0
MEM_B_DATA_1
MEM_B_DATA_2
MEM_B_DATA_3
MEM_B_DATA_4
MEM_B_DATA_5
MEM_B_DATA_6
MEM_B_DATA_7
MEM_B_DQS_0
MEM_B_DQS_0
MEM_B_DQS_1
MEM_B_DQS_1
MEM_B_DQS_2
MEM_B_DQS_2
MEM_B_DQS_3
MEM_B_DQS_3
MEM_B_DQS_4
MEM_B_DQS_4
MEM_B_DQS_5
MEM_B_DQS_5
MEM_B_DQS_6
MEM_B_DQS_6
MEM_B_DQS_7
MEM_B_DQS_7
MEM_B_CLK_P & lt; 0 & gt;
MEM_B_CLK_N & lt; 0 & gt;
MEM_B_CLK_P & lt; 1 & gt;
MEM_B_CLK_N & lt; 1 & gt;
MEM_B_CS_L & lt; 1..0 & gt;
MEM_B_ODT & lt; 0 & gt;
MEM_B_CKE & lt; 1..0 & gt;
MEM_B_CKE & lt; 3..2 & gt;
MEM_B_CAA & lt; 9..0 & gt;
MEM_B_CAB & lt; 9..0 & gt;
MEM_B_DQ & lt; 7..0 & gt;
MEM_B_DQ & lt; 15..8 & gt;
MEM_B_DQ & lt; 23..16 & gt;
MEM_B_DQ & lt; 31..24 & gt;
MEM_B_DQ & lt; 39..32 & gt;
MEM_B_DQ & lt; 47..40 & gt;
MEM_B_DQ & lt; 55..48 & gt;
MEM_B_DQ & lt; 63..56 & gt;
MEM_B_DQS_P & lt; 0 & gt;
MEM_B_DQS_N & lt; 0 & gt;
MEM_B_DQS_P & lt; 1 & gt;
MEM_B_DQS_N & lt; 1 & gt;
MEM_B_DQS_P & lt; 2 & gt;
MEM_B_DQS_N & lt; 2 & gt;
MEM_B_DQS_P & lt; 3 & gt;
MEM_B_DQS_N & lt; 3 & gt;
MEM_B_DQS_P & lt; 4 & gt;
MEM_B_DQS_N & lt; 4 & gt;
MEM_B_DQS_P & lt; 5 & gt;
MEM_B_DQS_N & lt; 5 & gt;
MEM_B_DQS_P & lt; 6 & gt;
MEM_B_DQS_N & lt; 6 & gt;
MEM_B_DQS_P & lt; 7 & gt;
MEM_B_DQS_N & lt; 7 & gt;
MEM_PWR
MEM_PWR
MEM_PWR
MEM_PWR
MEM_PWR
TABLE_PHYSICAL_RULE_ITEM
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_70D
MEM_B_CLK0
MEM_B_CLK0
MEM_B_CLK1
MEM_B_CLK1
MEM_B_CTRL
MEM_B_CTRL
MEM_B_CKE0
MEM_B_CKE1
MEM_B_CMD0
MEM_B_CMD1
MEM_B_DQ_BYTE0
MEM_B_DQ_BYTE1
MEM_B_DQ_BYTE2
MEM_B_DQ_BYTE3
MEM_B_DQ_BYTE4
MEM_B_DQ_BYTE5
MEM_B_DQ_BYTE6
MEM_B_DQ_BYTE7
MEM_B_DQS0
MEM_B_DQS0
MEM_B_DQS1
MEM_B_DQS1
MEM_B_DQS2
MEM_B_DQS2
MEM_B_DQS3
MEM_B_DQS3
MEM_B_DQS4
MEM_B_DQS4
MEM_B_DQS5
MEM_B_DQS5
MEM_B_DQS6
MEM_B_DQS6
MEM_B_DQS7
MEM_B_DQS7
TABLE_PHYSICAL_RULE_ITEM
PP1V2_S3
PP0V6_S3_MEM_VREFCA_A
PP0V6_S3_MEM_VREFDQ_A
PP0V6_S3_MEM_VREFCA_B
PP0V6_S3_MEM_VREFDQ_B
7 20 24
7 20 24
7 21 24
7 21 24
7 20 21 24
7 20 21 24 63
7 20 24
7 21 24
D
7 20 24 63
7 21 24 63
7 63
7 63
7 63
7 63
7 21 63
7 63
7 63
7 63
7 63
7 63
7 63
7 63
7 63
7 63
7 63
7 63
7 63
7 63
7 63
7 63
7 21 63
7 21 63
7 63
7 63
C
7 22 24
7 22 24
7 23 24
7 23 24
7 22 23 24
7 22 23 24 63
7 22 24
7 23 24
7 22 24 63
7 23 24 63
7 63
7 63
7 63
7 63
7 23 63
7 63
7 63
7 63
7 63
7 63
7 63
7 63
7 63
7 63
7 63
7 63
B
7 63
7 63
7 63
7 63
7 23 63
7 23 63
7 63
7 63
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_A_DATA_1
*
*
MEM_2OTHER
MEM_A_DATA_2
*
*
MEM_2OTHER
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_*_DATA_*
=SAME
*
MEM_DATA2SELF
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_A_DATA_0 MEM_*_DATA_*
*
MEM_2OTHERMEM
MEM_A_DATA_1 MEM_*_DATA_*
*
MEM_2OTHERMEM
MEM_A_DATA_2 MEM_*_DATA_*
*
MEM_2OTHERMEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_A_DATA_3
*
*
MEM_2OTHER
MEM_A_DATA_4
*
*
MEM_2OTHER
MEM_A_DATA_5
*
*
MEM_2OTHER
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_A_DATA_6
*
*
MEM_2OTHER
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_*_DATA_*
MEM_*
*
MEM_DATA2OTHERMEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_A_DATA_3 MEM_*_DATA_*
*
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_A_DATA_7
*
*
MEM_2OTHER
MEM_B_DATA_0
*
*
MEM_2OTHER
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
*
MEM_CMD2CMD
MEM_A_DATA_4 MEM_*_DATA_*
*
MEM_2OTHERMEM
MEM_A_DATA_5 MEM_*_DATA_*
*
MEM_2OTHERMEM
MEM_A_DATA_6 MEM_*_DATA_*
*
MEM_2OTHERMEM
MEM_A_DATA_7 MEM_*_DATA_*
*
MEM_2OTHERMEM
MEM_B_DATA_0 MEM_*_DATA_*
*
MEM_2OTHERMEM
MEM_B_DATA_1 MEM_*_DATA_*
*
MEM_2OTHERMEM
MEM_B_DATA_2 MEM_*_DATA_*
*
MEM_2OTHERMEM
MEM_B_DATA_3 MEM_*_DATA_*
*
MEM_2OTHERMEM
MEM_B_DATA_4 MEM_*_DATA_*
*
MEM_2OTHERMEM
MEM_B_DATA_5 MEM_*_DATA_*
*
MEM_2OTHERMEM
MEM_B_DATA_6 MEM_*_DATA_*
*
MEM_2OTHERMEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_B_DATA_1
*
*
MEM_2OTHER
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CMD
MEM_CTRL
*
MEM_CMD2CTRL
MEM_B_DATA_2
*
*
MEM_2OTHER
MEM_B_DATA_3
*
*
MEM_2OTHER
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CTRL
MEM_CTRL
*
MEM_CTRL2CTRL
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_B_DATA_4
A
*
*
MEM_2OTHER
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_CLK
MEM_CLK
*
MEM_CLK2CLK
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_B_DATA_5
*
*
MEM_2OTHER
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_B_DATA_6
*
*
MEM_2OTHER
MEM_B_DATA_7
*
*
MEM_2OTHER
MEM_CMD
*
*
MEM_2OTHER
MEM_CTRL
*
*
MEM_2OTHER
SYNC_MASTER=CONSTRAINTS
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
Memory Constraints
DRAWING NUMBER
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
Apple Inc.
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_*
*
MEM_2OTHERMEM
MEM_CLK
7
*
*
MEM_2OTHER
6
& lt; E4LABEL & gt;
TABLE_SPACING_ASSIGNMENT_ITEM
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_B_DATA_7 MEM_*_DATA_*
5
*
MEM_2OTHERMEM
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
R
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
8
SYNC_DATE=09/25/2012
PAGE TITLE
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_HEAD
MEM_*
18 19 22 23
MEM_2OTHERMEM
SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CMD
18 19 22 23
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CMD
18 19 20 21
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_HEAD
17 19 20 21 22 23 42
53 62
18 19 20 21
& lt; BRANCH & gt;
PAGE
114 OF 121
SHEET
70 OF 76
1
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8
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6
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DisplayPort Signal Constraints
4
ELECTRICAL_CONSTRAINT_SET
Thunderbolt SPI Signal Constraints
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
TBTDP_TX
TBTDP_TX
TBTDP_TX
TBTDP_TX
TBT_A_R2D_C_P & lt; 1..0 & gt;
TBT_A_R2D_C_N & lt; 1..0 & gt;
TBT_A_R2D_P & lt; 1..0 & gt;
TBT_A_R2D_N & lt; 1..0 & gt;
DP_80D
DP_80D
DP_80D
DP_80D
DP_80D
DP_80D
DP_80D
DP_80D
DP_TX
DP_TX
DP_TX
DP_TX
DP_TX
DP_TX
DP_TX
DP_TX
DP_TBTPA_ML_C_P & lt; 1 & gt;
DP_TBTPA_ML_C_N & lt; 1 & gt;
DP_TBTPA_ML_C_P & lt; 3 & gt;
DP_TBTPA_ML_C_N & lt; 3 & gt;
DP_TBTPA_ML_P & lt; 3..1:2 & gt;
DP_TBTPA_ML_N & lt; 3..1:2 & gt;
DP_A_LSX_ML_P & lt; 1 & gt;
DP_A_LSX_ML_N & lt; 1 & gt;
TBTDP_80D
TBTDP_80D
TBTDP_80D
TBTDP_80D
TBTDP_80D
TBTDP_80D
TBTDP_RX
TBTDP_RX
TBTDP_RX
TBTDP_RX
TBTDP_RX
TBTDP_RX
TBT_A_D2R_C_P & lt; 1..0 & gt;
TBT_A_D2R_C_N & lt; 1..0 & gt;
TBT_A_D2R_P & lt; 1 & gt;
TBT_A_D2R_N & lt; 1 & gt;
TBT_A_D2R_P & lt; 0 & gt;
TBT_A_D2R_N & lt; 0 & gt;
DP_80D
DP_80D
DP_80D
DP_80D
DP_80D
DP_80D
TBTDP_80D
TBTDP_80D
DP_AUX
DP_AUX
DP_AUX
DP_AUX
DP_AUX
DP_AUX
TBTDP_RX
TBTDP_RX
DP_TBTPA_AUXCH_C_P
DP_TBTPA_AUXCH_C_N
DP_TBTPA_AUXCH_P
DP_TBTPA_AUXCH_N
DP_A_AUXCH_DDC_P
DP_A_AUXCH_DDC_N
TBT_A_D2R1_AUXDDC_P
TBT_A_D2R1_AUXDDC_N
TBT_B_R2D
TBT_B_R2D
TBTDP_80D
TBTDP_80D
TBTDP_80D
TBTDP_80D
TBTDP_TX
TBTDP_TX
TBTDP_TX
TBTDP_TX
TBT_B_R2D_C_P & lt; 1..0 & gt;
TBT_B_R2D_C_N & lt; 1..0 & gt;
TBT_B_R2D_P & lt; 1..0 & gt;
TBT_B_R2D_N & lt; 1..0 & gt;
DP_TBTPB_ML
DP_TBTPB_ML
DIFFPAIR NECK GAP
DP_80D
DP_80D
DP_80D
DP_80D
DP_80D
DP_80D
DP_TX
DP_TX
DP_TX
DP_TX
DP_TX
DP_TX
NC_DP_TBTPB_ML_CP & lt; 3..1:2 & gt;
NC_DP_TBTPB_ML_CN & lt; 3..1:2 & gt;
DP_TBTPB_ML_P & lt; 3..1:2 & gt;
DP_TBTPB_ML_N & lt; 3..1:2 & gt;
DP_B_LSX_ML_P & lt; 1 & gt;
DP_B_LSX_ML_N & lt; 1 & gt;
TBTDP_80D
TBTDP_80D
TBTDP_80D
TBTDP_80D
TBTDP_RX
TBTDP_RX
TBTDP_RX
TBTDP_RX
TBT_B_D2R_C_P & lt; 1..0 & gt;
TBT_B_D2R_C_N & lt; 1..0 & gt;
TBT_B_D2R_P & lt; 1..0 & gt;
TBT_B_D2R_N & lt; 1..0 & gt;
DP_80D
DP_80D
DP_80D
DP_80D
DP_80D
DP_80D
TBTDP_80D
TBTDP_80D
DP_AUX
DP_AUX
DP_AUX
DP_AUX
DP_AUX
DP_AUX
TBTDP_RX
TBTDP_RX
NC_DP_TBTPB_AUXCH_CP
NC_DP_TBTPB_AUXCH_CN
DP_TBTPB_AUXCH_P
DP_TBTPB_AUXCH_N
DP_B_AUXCH_DDC_P
DP_B_AUXCH_DDC_N
TBT_B_D2R1_AUXDDC_P
TBT_B_D2R1_AUXDDC_N
TABLE_PHYSICAL_RULE_ITEM
TBT_SPI_45S
*
=45_OHM_SE
=45_OHM_SE
=45_OHM_SE
=45_OHM_SE
=STANDARD
=STANDARD
DP_TBTPA_ML1
DP_TBTPA_ML1
DP_TBTPA_ML3
DP_TBTPA_ML3
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
=2x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
TBT_SPI
D
*
Thunderbolt/DP Connector Signal Constraints
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TBTDP_80D
*
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_ASSIGNMENT_ITEM
TBTDP_TX
TBTDP_TX
*
TBTDP_TX2TX
TBTDP_RX
*
TBTDP_TX2TX
TBTDP_RX2RX
TOP,BOTTOM
=6x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
TBTDP_RX2RX
TOP,BOTTOM
=6x_DIELECTRIC
?
TABLE_SPACING_ASSIGNMENT_ITEM
TBTDP_TX
TBTDP_RX
*
TBTDP_TX2RX
TBTDP_TX2RX
TOP,BOTTOM
=10x_DIELECTRIC
*
TBTDP_TX2RX
*_TX
*
TBTDP_2OTHERHS
TBT_A_AUXCH
TBT_A_AUXCH
TABLE_SPACING_RULE_ITEM
TOP,BOTTOM
=10x_DIELECTRIC
?
TBTDP_2OTHER
TOP,BOTTOM
=6x_DIELECTRIC
?
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TBTDP_RX
*_TX
*
TBTDP_2OTHERHS
TBTDP_TX
*_RX
*
TBTDP_2OTHERHS
TBTDP_RX
*_RX
*
TBTDP_2OTHERHS
TBTDP_TX
*
*
TBTDP_2OTHER
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
TBTDP_TX2TX
*
=4x_DIELECTRIC
?
TBTDP_RX2RX
*
=4x_DIELECTRIC
?
TABLE_SPACING_ASSIGNMENT_ITEM
*
*
TBTDP_2OTHER
28
28
25 28
25 28
25 28
D
25 28
28
28
28
28
28
28
25 28
25 28
25 28
25 28
25 28
25 28
28
28
28
28
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TBTDP_RX
25 28
?
TBTDP_2OTHERHS
TBTDP_TX
TBTDP_TX
25 28
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TBTDP_RX
TBT_A_D2R1
TBT_A_D2R1
TBT_A_D2R0
TBT_A_D2R0
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TBTDP_RX
1
NET_TYPE
PHYSICAL
SPACING
TBTDP_80D
TBTDP_80D
TBTDP_80D
TBTDP_80D
TBT_A_R2D
TBT_A_R2D
TABLE_PHYSICAL_RULE_HEAD
ALLOW ROUTE
ON LAYER?
LAYER
2
Thunderbolt/DP Net Properties
NOTE: DisplayPort Physical/Spacing Constraints provided by Chipset or GPU page.
PHYSICAL_RULE_SET
3
TABLE_SPACING_RULE_ITEM
TBTDP_TX2RX
*
=6x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
TBTDP_2OTHERHS
*
=6x_DIELECTRIC
?
TBTDP_2OTHER
*
=4x_DIELECTRIC
?
64
64
TABLE_SPACING_RULE_ITEM
C
TBT_B_D2R
TBT_B_D2R
TBT_B_AUXCH
TBT_B_AUXCH
64
C
64
Only used on dual-port hosts.
64
64
25 64
25 64
Thunderbolt IC Net Properties
ELECTRICAL_CONSTRAINT_SET
NET_TYPE
SPACING
PHYSICAL
DP_80D
DP_80D
DP_80D
DP_80D
TBT_SPI_CLK
TBT_SPI_MOSI
TBT_SPI_MISO
TBT_SPI_CS_L
DP_TBTSRC_ML_C_P & lt; 3..0 & gt;
DP_TBTSRC_ML_C_N & lt; 3..0 & gt;
DP_TBTSRC_AUXCH_C_P
DP_TBTSRC_AUXCH_C_N
TBT_SPI_45S
TBT_SPI_45S
TBT_SPI_45S
TBT_SPI_45S
B
DP_TX
DP_TX
DP_AUX
DP_AUX
TBT_SPI
TBT_SPI
TBT_SPI
TBT_SPI
TBT_SPI_CLK
TBT_SPI_MOSI
TBT_SPI_MISO
TBT_SPI_CS_L
A
B
Only used on hosts supporting Thunderbolt video-in
25
25
25
25
SYNC_MASTER=CONSTRAINTS
SYNC_DATE=09/25/2012
PAGE TITLE
Thunderbolt Constraints
DRAWING NUMBER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
& lt; SCH_NUM & gt; D
REVISION
& lt; E4LABEL & gt;
BRANCH
& lt; BRANCH & gt;
PAGE
115 OF 121
SHEET
71 OF 76
1
A
8
7
6
5
4
3
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1
Camera Net Properties
ELECTRICAL_CONSTRAINT_SET
NET_TYPE
PHYSICAL
SPACING
S2_MEM_CLK
S2_MEM_CLK
S2_MEM_85D
S2_MEM_85D
S2_MEM_CLK
S2_MEM_CLK
MEM_CAM_CLK_P
MEM_CAM_CLK_N
S2_MEM_CNTL
S2_MEM_CNTL
S2_MEM_CMD
S2_MEM_CMD
S2_MEM_CMD
S2_MEM_CMD
S2_MEM_CMD
S2_MEM_CMD
S2_MEM_DQS0
S2_MEM_DQS0
S2_MEM_DQS1
S2_MEM_DQS1
S2_MEM_DATA_0
S2_MEM_DATA_1
S2_MEM_A
S2_MEM_45S
S2_MEM_45S
S2_MEM_45S
S2_MEM_45S
S2_MEM_45S
S2_MEM_45S
S2_MEM_45S
S2_MEM_45S
S2_MEM_45S
S2_MEM_85D
S2_MEM_85D
S2_MEM_85D
S2_MEM_85D
S2_MEM_45S
S2_MEM_45S
S2_MEM_45S
S2_MEM_CTRL
S2_MEM_CTRL
S2_MEM_CTRL
S2_MEM_CTRL
S2_MEM_CTRL
S2_MEM_CMD
S2_MEM_CMD
S2_MEM_CMD
S2_MEM_CMD
S2_MEM_DQS0
S2_MEM_DQS0
S2_MEM_DQS1
S2_MEM_DQS1
S2_MEM_DATA0
S2_MEM_DATA1
S2_MEM_CMD
MEM_CAM_CKE
MEM_CAM_CS_L
MEM_CAM_ODT
MEM_CAM_CAS_L
MEM_CAM_RAS_L
MEM_CAM_WE_L
MEM_CAM_BA & lt; 0 & gt;
MEM_CAM_BA & lt; 1 & gt;
MEM_CAM_BA & lt; 2 & gt;
MEM_CAM_DQS_P & lt; 0 & gt;
MEM_CAM_DQS_N & lt; 0 & gt;
MEM_CAM_DQS_P & lt; 1 & gt;
MEM_CAM_DQS_N & lt; 1 & gt;
MEM_CAM_DM & lt; 0 & gt;
MEM_CAM_DM & lt; 1 & gt;
MEM_CAM_A & lt; 14..0 & gt;
S2_MEM_DATA_0
S2_MEM_DATA_1
MIPI Interface Constraints
S2_MEM_45S
S2_MEM_45S
S2_MEM_DATA0
S2_MEM_DATA1
MEM_CAM_DQ & lt; 7..0 & gt;
MEM_CAM_DQ & lt; 15..8 & gt;
MIPI_DATA_S2
MIPI_DATA_S2
MIPI_85D
MIPI_85D
MIPI_85D
MIPI_85D
MIPI_DATA
MIPI_DATA
MIPI_DATA
MIPI_DATA
MIPI_DATA_P
MIPI_DATA_N
MIPI_DATA_CONN_P
MIPI_DATA_CONN_N
CLK_MIPI
CLK_MIPI
CLK_MIPI
CLK_MIPI
MIPI_CLK_P
MIPI_CLK_N
MIPI_CLK_CONN_P
MIPI_CLK_CONN_N
S2_MEM_PWR
S2_MEM_PWR
S2_MEM_PWR
S2_MEM_PWR
PP1V35_CAM
31 32
PP0V675_CAM_VREF
31 32
PP0V675_MEM_CAM_VREFCA 32
PP0V675_MEM_CAM_VREFDQ 32
31 32
31 32
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
MIPI_85D
*
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
TABLE_PHYSICAL_RULE_ITEM
D
I101
I102
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
=4X_DIELECTRIC
SPACING_RULE_SET
?
LAYER
LINE-TO-LINE SPACING
WEIGHT
=6X_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
MIPI_2OTHER
*
*
TOP,BOTTOM
TABLE_SPACING_RULE_ITEM
?
=6X_DIELECTRIC
MIPI_2CLK
TOP,BOTTOM
?
=8X_DIELECTRIC
TABLE_SPACING_RULE_ITEM
MIPICLK_2OTHER
*
TABLE_SPACING_RULE_ITEM
?
=7X_DIELECTRIC
I104
TABLE_SPACING_RULE_ITEM
MIPI_2OTHER
TABLE_SPACING_RULE_ITEM
MIPI_2CLK
I103
TABLE_SPACING_RULE_HEAD
WEIGHT
MIPICLK_2OTHER
TOP,BOTTOM
?
=10X_DIELECTRIC
I106
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
I108
TABLE_SPACING_ASSIGNMENT_ITEM
MIPI_DATA
*
*
I107
MIPI_2OTHER
I109
TABLE_SPACING_ASSIGNMENT_ITEM
MIPI_DATA
CLK_MIPI
*
MIPI_2CLK
I110
TABLE_SPACING_ASSIGNMENT_ITEM
CLK_MIPI
*
*
I147
MIPICLK_2OTHER
Memory Bus Constraints
I127
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
I128
TABLE_PHYSICAL_RULE_ITEM
S2_MEM_45S
*
=45_OHM_SE
=45_OHM_SE
=45_OHM_SE
=STANDARD
=45_OHM_SE
I129
=STANDARD
I130
TABLE_PHYSICAL_RULE_ITEM
S2_MEM_85D
*
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
I133
Spacing Rule Sets
LAYER
I131
LINE-TO-LINE SPACING
WEIGHT
S2_DATA2SELF
*
=2x_DIELECTRIC
?
S2_DQS2OWNDATA
*
=2x_DIELECTRIC
?
S2_CMD2CMD
*
=2x_DIELECTRIC
?
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
S2_DATA2SELF
TOP,BOTTOM
=4x_DIELECTRIC
?
S2_DQS2OWNDATA
TOP,BOTTOM
=4x_DIELECTRIC
?
S2_CMD2CMD
TOP,BOTTOM
=4x_DIELECTRIC
=2x_DIELECTRIC
?
*
=2x_DIELECTRIC
?
S2_CMD2CTRL
TOP,BOTTOM
=4x_DIELECTRIC
TOP,BOTTOM
=4x_DIELECTRIC
*
=2x_DIELECTRIC
TOP,BOTTOM
=6x_DIELECTRIC
S2MEM_2GND
*
=2x_DIELECTRIC
TOP,BOTTOM
=4x_DIELECTRIC
=6x_DIELECTRIC
S2MEM_2GND
?
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
31 32
32 64
32 64
MIPI_85D
MIPI_85D
MIPI_85D
MIPI_85D
31 32
31 32
32 64
C
32 64
I149
?
TOP,BOTTOM
=4x_DIELECTRIC
?
S2MEM_2OTHER
?
*
31 32
TOP,BOTTOM
=10x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
S2MEM_2OTHER
31 32
?
S2MEM_2PWR
?
31 32
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
S2MEM_2PWR
31 32
?
S2_2OTHERMEM
?
31 32
?
S2_CTRL2CTRL
TABLE_SPACING_RULE_ITEM
=4x_DIELECTRIC
31 32
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
*
I148
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
*
31 32
?
I146
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
S2_CMD2CTRL
I145
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
S2_CTRL2CTRL
D
32
TABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
S2_2OTHERMEM
MIPI_CLK_S2
MIPI_CLK_S2
I132
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
31 32
=85_OHM_DIFF
I134
C
31 32
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
Memory Bus Spacing Group Assignments
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
S2_MEM_DQS1
S2_MEM_DATA1
*
S2_DQS2OWNDATA
S2_MEM_DQS0
S2_MEM_DATA0
*
S2_DQS2OWNDATA
TABLE_SPACING_ASSIGNMENT_ITEM
S2_MEM_DATA*
*
*
S2MEM_2OTHER
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
S2_MEM_DQS*
*
*
S2MEM_2OTHER
S2_MEM_CMD
*
*
S2_MEM_CTRL
*
*
S2MEM_2OTHER
S2_MEM_CLK
*
*
S2MEM_2OTHER
S2_MEM_DATA*
=SAME
*
S2_DATA2SELF
S2_MEM_CMD
S2_MEM_CMD
*
S2_CMD2CMD
S2_MEM_CMD
S2_MEM_CTRL
*
S2_CMD2CTRL
S2_MEM_CTRL
S2_MEM_CTRL
*
S2_CTRL2CTRL
TABLE_SPACING_ASSIGNMENT_ITEM
S2MEM_2OTHER
TABLE_SPACING_ASSIGNMENT_ITEM
B
B
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
Memory to Power Spacing
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
S2_MEM_PWR
S2_MEM_*
*
S2MEM_2PWR
S2_MEM_PWR
*
*
DEFAULT
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
S2_MEM_*
S2_MEM_*
*
S2_2OTHERMEM
Memory to GND Spacing
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
GND
S2_MEM_*
*
S2MEM_2GND
TABLE_SPACING_ASSIGNMENT_ITEM
A
SYNC_MASTER=J41_MLB
SYNC_DATE=01/30/2013
PAGE TITLE
Camera Constraints
DRAWING NUMBER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
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8
7
6
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D
D
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
1TO1_DIFFPAIR
*
=STANDARD
=STANDARD
=STANDARD
=STANDARD
0.1 MM
0.1 MM
2TO1_DIFFPAIR
*
=STANDARD
0.2 MM
0.1 MM
=STANDARD
0.1 MM
0.1 MM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
C
C
SMC SMBus Net Properties
ELECTRICAL_CONSTRAINT_SET
SMBUS_SMC_0_S0_SCL
SMBUS_SMC_0_S0_SDA
SMBUS_SMC_1_S0_SCL
SMBUS_SMC_1_S0_SDA
SMBUS_SMC_2_S3_SCL
SMBUS_SMC_2_S3_SDA
SMBUS_SMC_3_SCL
SMBUS_SMC_3_SDA
SMBUS_SMC_5_G3_SCL
SMBUS_SMC_5_G3_SDA
NET_TYPE
PHYSICAL
SPACING
SMB_45S_R_50S
SMB_45S_R_50S
SMB_45S_R_50S
SMB_45S_R_50S
SMB_45S_R_50S
SMB_45S_R_50S
SMB_45S_R_50S
SMB_45S_R_50S
SMB_45S_R_50S
SMB_45S_R_50S
SMB
SMB
SMB
SMB
SMB
SMB
SMB
SMB
SMB
SMB
SMBUS_SMC_0_S0_SCL
SMBUS_SMC_0_S0_SDA
SMBUS_SMC_1_S0_SCL
SMBUS_SMC_1_S0_SDA
SMBUS_SMC_2_S3_SCL
SMBUS_SMC_2_S3_SDA
SMBUS_SMC_3_SCL
SMBUS_SMC_3_SDA
SMBUS_SMC_5_G3_SCL
SMBUS_SMC_5_G3_SDA
37 40 60
37 40 60
14 32 37 40 43 44 64 69
14 32 37 40 43 44 64 69
37 40 61 65
37 40 61 65
36 37 40 44 64
36 37 40 44 64
37 40 48 50 64
37 40 48 50 64
SMBus Charger Net Properties
ELECTRICAL_CONSTRAINT_SET
SENSE_DIFFPAIR
SENSE_DIFFPAIR
B
SENSE_DIFFPAIR
SENSE_DIFFPAIR
NET_TYPE
PHYSICAL
SPACING
2TO1_DIFFPAIR
2TO1_DIFFPAIR
2TO1_DIFFPAIR
CHGR_CSI_P
CHGR_CSI_N
CHGR_CSI_R_P
CHGR_CSI_R_N
2TO1_DIFFPAIR
2TO1_DIFFPAIR
2TO1_DIFFPAIR
2TO1_DIFFPAIR
CHGR_CSO_P
CHGR_CSO_N
CHGR_CSO_R_P
CHGR_CSO_R_N
50
B
50
50
50
50
50
43 50
43 50
A
SYNC_MASTER=CONSTRAINTS
SYNC_DATE=09/25/2012
PAGE TITLE
SMC Constraints
DRAWING NUMBER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
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J11/J13 Specific Net Properties
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
SENSE_1TO1_45S
*
=1TO1_DIFFPAIR
=45_OHM_SE
=45_OHM_SE
=45_OHM_SE
=1TO1_DIFFPAIR
SENSE_1TO1_P2MM
*
=1TO1_DIFFPAIR
0.200 MM
0.100 MM
=1TO1_DIFFPAIR
=1TO1_DIFFPAIR
=1TO1_DIFFPAIR
THERM_1TO1_45S
*
=1TO1_DIFFPAIR
=45_OHM_SE
=45_OHM_SE
=45_OHM_SE
=1TO1_DIFFPAIR
NET_TYPE
PHYSICAL
SPACING
=1TO1_DIFFPAIR
=1TO1_DIFFPAIR
ELECTRICAL_CONSTRAINT_SET
TABLE_PHYSICAL_RULE_ITEM
SENSE_DIFFPAIR
SENSE_DIFFPAIR
TABLE_PHYSICAL_RULE_ITEM
THERM_1TO1_45S
THERM_1TO1_45S
THERM
THERM
INLET_THMSNS_D1_P
INLET_THMSNS_D1_N
44
44
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
SPKR_DIFFPAIR
*
SPACING_RULE_SET
LAYER
=1TO1_DIFFPAIR
0.300 MM
0.100 MM
=1TO1_DIFFPAIR
=1TO1_DIFFPAIR
=1TO1_DIFFPAIR
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
TABLE_SPACING_RULE_ITEM
*
=2:1_SPACING
*
=2:1_SPACING
CPU_COMP
?
GND
*
CPU_VCCSENSE
GND
*
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
AUDIO
*
=2:1_SPACING
?
SENSE_1TO1_45S
SENSE_1TO1_45S
SENSE
SENSE
TBDTHMSNS_D2_P
TBDTHMSNS_D2_N
SENSE_1TO1_45S
SENSE_1TO1_45S
SENSE
SENSE
CPUTHMSNS_D2_P
CPUTHMSNS_D2_N
SENSE_1TO1_P2MM SENSE
SENSE_1TO1_P2MM SENSE
CPUVCCIOS0_CS_N
CPUVCCIOS0_CS_P
SENSE_DIFFPAIR
SENSE_DIFFPAIR
SENSE_DIFFPAIR
SENSE_DIFFPAIR
GND_P2MM
TABLE_SPACING_RULE_ITEM
TBTTHMSNS_D2_R_P
TBTTHMSNS_D2_R_N
TBTTHMSNS_D2_P
TBTTHMSNS_D2_N
TBT_MLBBOT_THMSNS_P
TBT_MLBBOT_THMSNS_N
MLBBOT_THMSNS_D3_P
MLBBOT_THMSNS_D3_N
SENSE_DIFFPAIR
SENSE_DIFFPAIR
GND_P2MM
THERM
THERM
THERM
THERM
THERM
THERM
THERM
THERM
SENSE_DIFFPAIR
SENSE_DIFFPAIR
TABLE_SPACING_ASSIGNMENT_ITEM
?
THERM
SPACING_RULE_SET
THERM_1TO1_45S
THERM_1TO1_45S
THERM_1TO1_45S
THERM_1TO1_45S
THERM_1TO1_45S
THERM_1TO1_45S
THERM_1TO1_45S
THERM_1TO1_45S
SENSE_DIFFPAIR
SENSE_DIFFPAIR
TABLE_SPACING_ASSIGNMENT_HEAD
WEIGHT
SENSE
SENSE_DIFFPAIR
SENSE_DIFFPAIR
SENSE_DIFFPAIR
SENSE_DIFFPAIR
SENSE_DIFFPAIR
SENSE_DIFFPAIR
SENSE_DIFFPAIR
SENSE_DIFFPAIR
SENSE_1TO1_P2MM
SENSE_1TO1_P2MM
SENSE_1TO1_45S
SENSE_1TO1_45S
SENSE
SENSE
SENSE
SENSE
CPUVR_ISNS1_P
CPUVR_ISNS1_N
CPUVR_ISNS2_P
CPUVR_ISNS2_N
SENSE_1TO1_P2MM
SENSE_1TO1_P2MM
SENSE_1TO1_45S
SENSE_1TO1_45S
D
TABLE_SPACING_RULE_HEAD
LINE-TO-LINE SPACING
SENSE
SENSE
SENSE
SENSE
CPUVR_ISNS1_P_R
CPUVR_ISNS1_N_R
CPUVR_ISUM_R_P
CPUVR_ISUM_R_N
44
D
44
44
44
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
GND
CLK_PCIE
*
GND_P2MM
GND
PCIE*
*
GND_P2MM
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
TABLE_SPACING_ASSIGNMENT_ITEM
WEIGHT
TABLE_SPACING_RULE_ITEM
GND
*
=STANDARD
44
44
TABLE_SPACING_ASSIGNMENT_ITEM
?
TABLE_SPACING_ASSIGNMENT_ITEM
GND
SATA*
*
GND_P2MM
44
44
TABLE_SPACING_ASSIGNMENT_ITEM
GND
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
USB*
*
GND_P2MM
WEIGHT
TABLE_SPACING_ASSIGNMENT_ITEM
GND
0.20 MM
10000
*
GND_P2MM
CLK_PCIE
*
PWR_P2MM
SB_POWER
*
LVDS*
SB_POWER
TABLE_SPACING_RULE_ITEM
GND_P2MM
SATA*
*
PWR_P2MM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
PWR_P2MM
*
0.20 MM
10000
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
SB_POWER
SATA*
*
PWR_P2MM
C
SENSE_DIFFPAIR
SENSE_DIFFPAIR
SENSE_DIFFPAIR
SENSE_DIFFPAIR
SENSE_1TO1_P2MM
SENSE_1TO1_P2MM
SENSE_1TO1_45S
SENSE_1TO1_45S
SENSE
SENSE
SENSE
SENSE
ISNS_CPUDDR_P
ISNS_CPUDDR_N
ISNS_P3V3S5_N
ISNS_P3V3S5_P
SENSE_DIFFPAIR
SENSE_DIFFPAIR
SENSE_DIFFPAIR
SENSE_DIFFPAIR
SENSE_1TO1_45S
SENSE_1TO1_45S
SENSE_1TO1_45S
SENSE_1TO1_45S
SENSE
SENSE
SENSE
SENSE
ISNS_3V3_S0_P
ISNS_3V3_S0_N
ISNS_CAMERA_P
ISNS_CAMERA_N
SENSE_DIFFPAIR
SENSE_DIFFPAIR
SENSE_1TO1_45S
SENSE_1TO1_45S
SENSE
SENSE
ISNS_P3V3_S0_N
ISNS_P3V3_S0_P
SENSE_DIFFPAIR
SENSE_DIFFPAIR
SENSE_1TO1_P2MM SENSE
SENSE_1TO1_P2MM SENSE
ISNS_1V05_S0_P
ISNS_1V05_S0_N
SENSE_DIFFPAIR
SENSE_DIFFPAIR
SENSE_1TO1_45S
SENSE_1TO1_45S
SENSE
SENSE
SENSE_1TO1_45S
SENSE_1TO1_45S
SENSE
SENSE
ISNS_HS_COMPUTING_N
ISNS_HS_COMPUTING_P
SENSE_DIFFPAIR
SENSE_DIFFPAIR
SENSE_1TO1_45S
SENSE_1TO1_45S
SENSE
SENSE
ISNS_1V2_S3_N
ISNS_1V2_S3_P
SENSE_1TO1_45S
SENSE_1TO1_45S
SENSE
SENSE
ISNS_AIRPORT_N
ISNS_AIRPORT_P
SENSE_DIFFPAIR
SENSE_DIFFPAIR
SENSE_1TO1_45S
SENSE_1TO1_45S
SENSE
SENSE
ISNS_SSD_N
ISNS_SSD_P
SENSE_DIFFPAIR
SENSE_DIFFPAIR
SENSE_1TO1_45S
SENSE_1TO1_45S
SENSE
SENSE
ISNS_LCDBKLT_N
ISNS_LCDBKLT_P
SENSE_DIFFPAIR
SENSE_DIFFPAIR
SENSE_1TO1_45S
SENSE_1TO1_45S
SENSE
SENSE
ISNS_PANEL_N
ISNS_PANEL_P
SENSE_DIFFPAIR
SENSE_DIFFPAIR
SENSE_1TO1_45S
SENSE_1TO1_45S
SENSE
SENSE
ISNS_HS_GAIN_N
ISNS_HS_GAIN_P
AUD_DIFF
AUD_DIFF
1TO1_DIFFPAIR
1TO1_DIFFPAIR
1TO1_DIFFPAIR
1TO1_DIFFPAIR
SPKR_DIFFPAIR
SPKR_DIFFPAIR
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
SPKRAMP_INR_P
SPKRAMP_INR_N
MAX98300_R_P
MAX98300_R_N
SPKRAMP_ROUT_P
SPKRAMP_ROUT_N
SB_POWER
SB_POWER
I349
SENSE
SENSE
SENSE_DIFFPAIR
SENSE_DIFFPAIR
I348
SENSE_1TO1_45S
SENSE_1TO1_45S
ISNS_HS_OTHER_N
ISNS_HS_OTHER_P
SENSE_DIFFPAIR
SENSE_DIFFPAIR
B
42 52
42 52
42 52
42 43
42 43
42
42
C
ISNS_BMON_GAIN_P
ISNS_BMON_GAIN_N
SENSE_DIFFPAIR
SENSE_DIFFPAIR
42 52
PP3V3_S5
PP3V3_S0
SPKR_OUT
SPKR_OUT
A
GND
42
42
42
42
41
41
41
41
42 55
42 55
41 43
41 43
41
41
41 53
41 53
B
41
41
41
41
41
41
43
43
43 44
43 44
47 61 65
47 61 65
47
47
47 64
47 64
8 11 13 15 16 17 18 28 29 34 42
57 58 59 60 62 64
62 64 65
8 11 12 13 15 17 18 27 30 36 38
39 40 41 42 43 44 45 56 59 61
GND
SYNC_MASTER=J41_MLB
SYNC_DATE=12/07/2012
PAGE TITLE
Project Specific Constraints
DRAWING NUMBER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
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D
D
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
SD_45SE
*
=45_OHM_SE
=45_OHM_SE
=45_OHM_SE
=45_OHM_SE
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM
C
C
SD Card Net Properties
ELECTRICAL_CONSTRAINT_SET
I347
I346
I348
I349
I350
I351
I352
I353
I354
I355
I356
SDDATA
SDCLK
NET_TYPE
PHYSICAL
SPACING
SD_45SE
SD_45SE
SDCONN_DATA & lt; 0..3 & gt;
SDCONN_CLK
SD_45SE
SD_45SE
SD_45SE
SD_45SE
SD_45SE
SD_45SE
SD_45SE
CLK_25M_45S
CLK_25M_45S
SDCONN_WP
SDCONN_CMD
SDCONN_DETECT_L
SD_SPI_CLK
SD_SPI_CS_L
SD_SPI_MOSI
SD_SPI_MISO
SDSCLK_CLK_25M_X1
SDCLK_CLK25M_X2_R
SPI
SPI
SPI
SPI
33 34
33 34
33 34
33 34
33 34
34
34
34
34
34 69
B
B
A
SYNC_MASTER=CONSTRAINTS
SYNC_DATE=09/25/2012
PAGE TITLE
Project Specific Constraints
DRAWING NUMBER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
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8
7
6
5
4
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1
D
D
C
C
EMPTY
B
B
A
SYNC_MASTER=J41_MLB
SYNC_DATE=07/03/2012
PAGE TITLE
Reference
DRAWING NUMBER
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
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III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
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