There are schematic and boardview.
8
7
6
5
4
3
2
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
REV
1
ECN
DESCRIPTION OF REVISION
CK
APPD
DATE
2012-02-15
SCHEM,MLB_KEPLER_2PHASE,J31
www.qdzbwx.com
FRB & RISK RAMP 02/15/12
(.csa)
D
Date
Page
Contents
TABLE_TABLEOFCONTENTS_HEAD
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
C
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
B
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
Sync
MASTER
TABLE_TABLEOFCONTENTS_ITEM
MASTER
TABLE_TABLEOFCONTENTS_ITEM
MASTER
Revision History
TABLE_TABLEOFCONTENTS_ITEM
06/30/2009
Table of Contents
TABLE_TABLEOFCONTENTS_HEAD
04/19/2011
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
(.csa)
J31_MLB
2
3
Power Block Diagram
K17_REF
Revision History
MASTER
4
05/28/2009
TABLE_TABLEOFCONTENTS_ITEM
08/29/2011
TABLE_TABLEOFCONTENTS_ITEM
04/27/2010
TABLE_TABLEOFCONTENTS_ITEM
03/11/2011
BOM Configuration
TABLE_TABLEOFCONTENTS_ITEM
04/27/2010
5
TABLE_TABLEOFCONTENTS_ITEM
K17_REF
7
Functional / ICT Test
K18_MLB
8
Power Aliases
J31_MLB
9
Signal Aliases
K18_MLB
CPU DMI/PEG/FDI/RSVD
J5_MLB
10
08/03/2010
TABLE_TABLEOFCONTENTS_ITEM
08/03/2010
TABLE_TABLEOFCONTENTS_ITEM
06/15/2010
TABLE_TABLEOFCONTENTS_ITEM
08/19/2010
TABLE_TABLEOFCONTENTS_ITEM
08/19/2010
TABLE_TABLEOFCONTENTS_ITEM
06/02/2011
CPU CLOCK/MISC/JTAG
TABLE_TABLEOFCONTENTS_ITEM
06/15/2010
11
TABLE_TABLEOFCONTENTS_ITEM
K92_MLB
12
CPU DDR3 INTERFACES
K92_SUMA
13
CPU POWER
K92_MLB
14
CPU POWER AND GND
K92_SUMA
16
CPU DECOUPLING-I
K92_MLB
17
CPU DECOUPLING-II
K92_MLB
PCH SATA/PCIe/CLK/LPC/SPI
J31_ANNE
PCH DMI/FDI/PM/Graphics
J5_MLB
18
05/26/2011
TABLE_TABLEOFCONTENTS_ITEM
03/21/2011
TABLE_TABLEOFCONTENTS_ITEM
03/21/2011
TABLE_TABLEOFCONTENTS_ITEM
05/26/2011
TABLE_TABLEOFCONTENTS_ITEM
06/09/2011
PCH PCI/USB/TP/RSVD
TABLE_TABLEOFCONTENTS_ITEM
06/02/2011
20
TABLE_TABLEOFCONTENTS_ITEM
06/02/2011
19
TABLE_TABLEOFCONTENTS_ITEM
J31_ANNE
21
PCH GPIO/MISC/NCTF
J31_ANNE
22
PCH POWER
J5_MLB
23
PCH GROUNDS
J5_MLB
24
PCH DECOUPLING
J5_MLB
CPU & PCH XDP
J31_ANNE
25
07/06/2010
TABLE_TABLEOFCONTENTS_ITEM
04/27/2010
TABLE_TABLEOFCONTENTS_ITEM
06/23/2010
TABLE_TABLEOFCONTENTS_ITEM
05/10/2010
TABLE_TABLEOFCONTENTS_ITEM
06/23/2010
TABLE_TABLEOFCONTENTS_ITEM
10/25/2011
Chipset Support
TABLE_TABLEOFCONTENTS_ITEM
09/16/2011
26
TABLE_TABLEOFCONTENTS_ITEM
K92_MLB
27
USB HUB & MUX
J31_LINDA
28
CPU Memory S3 Support
K18_MLB
29
DDR3 SO-DIMM Connector A
K92_SUMA
30
DDR3 Byte/Bit Swaps
K92_SUMA
31
DDR3 SO-DIMM Connector B
K92_SUMA
SD Card Connector
J31_YONAS
33
06/09/2011
TABLE_TABLEOFCONTENTS_ITEM
06/14/2011
TABLE_TABLEOFCONTENTS_ITEM
06/14/2011
TABLE_TABLEOFCONTENTS_ITEM
06/22/2011
TABLE_TABLEOFCONTENTS_ITEM
10/11/2010
TABLE_TABLEOFCONTENTS_ITEM
05/26/2010
TABLE_TABLEOFCONTENTS_ITEM
04/27/2010
TABLE_TABLEOFCONTENTS_ITEM
06/17/2011
TABLE_TABLEOFCONTENTS_ITEM
06/10/2010
TABLE_TABLEOFCONTENTS_ITEM
11/17/2011
TABLE_TABLEOFCONTENTS_ITEM
09/21/2011
DDR3/FRAMEBUF VREF MARGINING
TABLE_TABLEOFCONTENTS_ITEM
11/11/2011
34
TABLE_TABLEOFCONTENTS_ITEM
J31_ANNE
35
X19/ALS/CAMERA CONNECTOR
J30_MLB
36
Thunderbolt Host (1 of 2)
T29_REF
37
Thunderbolt Host (2 of 2)
T29_REF
38
Thunderbolt Power Support
T29_REF
39
ETHERNET PHY (CAESAR IV)
K91_ERIC
Ethernet Connector
K91_TRINHNI
40
41
FireWire LLC/PHY (FW643)
K18_MLB
42
FireWire Port & PHY Power
K91_MLB
43
FireWire Connector
T27_REF
45
SATA Redriver/Conn, IR, SIL
J31_YONAS
External A USB3 Connector
J31_LINDA
46
08/04/2011
TABLE_TABLEOFCONTENTS_ITEM
12/19/2011
External B USB3 Connector
TABLE_TABLEOFCONTENTS_ITEM
04/27/2010
47
TABLE_TABLEOFCONTENTS_ITEM
J30_MLB
48
Front Flex Support
K18_MLB
49
SMC
J31_YONAS
TABLE_TABLEOFCONTENTS_ITEM
Date
Page
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
Contents
Sync
(.csa)
01/19/2012
TABLE_TABLEOFCONTENTS_ITEM
04/27/2010
TABLE_TABLEOFCONTENTS_ITEM
01/19/2012
SMC Support
TABLE_TABLEOFCONTENTS_ITEM
J31_YONAS
LPC+SPI Debug Connector
TABLE_TABLEOFCONTENTS_HEAD
05/26/2011
50
J5_MLB
51
52
SMBus Connections
K18_MLB
Power Sensors: Load Side
J31_YONAS
53
10/25/2011
TABLE_TABLEOFCONTENTS_ITEM
04/27/2010
TABLE_TABLEOFCONTENTS_ITEM
06/10/2011
TABLE_TABLEOFCONTENTS_ITEM
07/01/2011
Power Sensors: High Side, CPU, AXG
TABLE_TABLEOFCONTENTS_ITEM
09/08/2011
54
TABLE_TABLEOFCONTENTS_ITEM
J31_YONAS
55
Thermal Sensors
J31_YONAS
56
Fan Connectors
K18_MLB
57
WELLSPRING 1
J30_MLB
WELLSPRING 2
J31_LINDA
58
08/11/2011
TABLE_TABLEOFCONTENTS_ITEM
10/26/2011
TABLE_TABLEOFCONTENTS_ITEM
10/26/2011
TABLE_TABLEOFCONTENTS_ITEM
10/26/2011
TABLE_TABLEOFCONTENTS_ITEM
10/26/2011
TABLE_TABLEOFCONTENTS_ITEM
10/26/2011
Digital Accelerometer
TABLE_TABLEOFCONTENTS_ITEM
06/08/2010
59
SPI ROM
K91_BEN
62
AUDIO: CODEC/REGULATOR
J31_AUDIO
63
AUDIO: LINE INPUT FILTER
J31_AUDIO
64
AUDIO: DETECT/MIC BIAS
J31_AUDIO
65
AUDIO: HEADPHONE FILTER
J31_AUDIO
AUDIO: SPEAKER AMP
J31_JACK
J31_SREE
09/19/2011
100
08/09/2010
CPU Constraints
K92_MLB
Memory Constraints
K91_MLB
PCH Constraints 1
K92_MLB
PCH Constraints 2
J31_YONAS
Ethernet/FW Constraints
K91_ERIC
101
06/25/2011
102
08/09/2010
103
05/05/2011
104
08/03/2010
105
06/14/2011
Thunderbolt Constraints
T29_REF
SMC Constraints
J31_YONAS
GPU (Kepler) CONSTRAINTS
K92_MLB
Project Specific Constraints
K18_MLB
PCB Rule Definitions
K18_MLB
Power Sensors: SMC Extended
J31_YONAS
Power Sensors: Debug ADC
J31_YONAS
Power Sensors: CPU Ripple
J31_YONAS
106
08/11/2011
107
08/09/2010
108
04/27/2010
109
04/27/2010
130
09/12/2011
131
09/12/2011
132
08/24/2011
J31_JACK
System Agent Supply
PCH VCCIO (1.05V) POWER SUPPLY
Power Sequencing EG/PCH S0
99
J31_JACK
PBus Supply & Battery Charger
09/16/2011
J31_AUDIO
DC-In & Battery Connectors
98
J31_AUDIO
AUDIO: JACK TRANSLATORS
Sync
J31_AUDIO
AUDIO: JACKS
Contents
TABLE_TABLEOFCONTENTS_ITEM
J31_YONAS
61
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
D
Date
Page
J31_JACK
66
67
C
10/26/2011
68
10/26/2011
69
09/02/2011
70
11/14/2011
71
09/14/2011
72
11/09/2011
5V / 3.3V Power Supply
J31_JACK
1.5V DDR3 Supply
J31_JACK
CPU IMVP7 & AXG VCore Regulator
J31_JACK
CPU IMVP7 & AXG VCore Output
J31_JACK
CPU VCCIO (1V0R1V05 S0) POWER SUPPLY
J31_JACK
Misc Power Supplies
J31_JACK
Power FETs
J31_MARY
73
07/07/2011
74
11/11/2011
75
11/11/2011
76
09/19/2011
77
06/10/2011
78
05/05/2011
79
06/06/2011
Power Control 1/ENABLE
J31_MARY
KEPLER PCI-E
J31_SREE
KEPLER CORE/FB POWER
D2_MLB_2P
KEPLER FRAME BUFFER I/F
J31_SREE
1V05 GPU / 1V35 FB POWER SUPPLY
J31_JACK
GDDR5 Frame Buffer A
J31_SREE
GDDR5 Frame Buffer B
J31_SREE
80
10/25/2011
81
01/18/2012
82
10/25/2011
83
11/16/2011
84
10/25/2011
85
B
10/25/2011
86
10/25/2011
KEPLER LVDS/DP/GPIO
J31_SREE
KEPLER GPIOS,CLK & STRAPS
J31_SREE
KEPLER PEX PWR/GNDS
J31_SREE
GFX IMVP VCore Regulator
D2_MLB_2P
LVDS Display Connector
K18_MLB
87
11/16/2011
88
10/31/2011
89
01/18/2012
90
04/27/2010
92
11/21/2010
Muxed Graphics Support
K92_MLB
Thunderbolt MUXing A
J31_WILL
Thunderbolt Connector A
T29_REF
Graphics MUX (GMUX)
K91_MARY
LCD Backlight Driver
J31_KIRAN
93
06/20/2011
94
06/14/2011
96
08/03/2010
97
03/21/2011
TABLE_TABLEOFCONTENTS_ITEM
A
A
DRAWING TITLE
SCHEM,MLB_KEPLER,J31
DRAWING NUMBER
Schematic / PCB #’s
PART NUMBER
QTY
Apple Inc.
DESCRIPTION
REFERENCE DES
CRITICAL
051-9585
1
SCHEM,MLB_KEPLER_2PHASE,J31
SCH
1
PCBF,MLB_KEPLER_2PHASE,J31
PCB
R
NOTICE OF PROPRIETARY PROPERTY:
CRITICAL
820-3330
BOM OPTION
CRITICAL
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
DRAWING
ABBREV=DRAWING
TITLE=MLB
LAST_MODIFIED=Wed Feb 15 20:30:03 2012
8
7
6
051-9585
REVISION
5
4
3
2
3.0.0
BRANCH
PAGE
1 OF 132
SHEET
1 OF 105
1
SIZE
D
8
7
6
5
4
3
2
1
J2500,J2550
INTEL CPU
U8000
GRAPHICS
XDP CONN
2.X GHZ
PG 23
NVIDIA KEPLER
IVY BRIDGE
J2900
PG 9
J3100
2 DIMMS
PG 73
DDR3-1067/1333MHZ
DIMM
D
D
J6950
POWER SUPPLY
DC/BATT
PG 27,29
PG 63
GPIO
FDI
DMI
RTC
PG 19
PG 17
PG 17
PG 16
ALS SENSOR
PG 32
U6100
SPI
U5920
SMS SENSOR
PG 50
Boot ROM
U3600
Misc
THERMAL SENSOR
PG 55
PG 50
CLK
T29
PG 19
BUFFER
PG 33/34
POWER SENSE
PG 48
PG 16
J5650,5660
SPI
FAN CONN AND CONTROL
J4500
PG 51
5
ODD
PG 16
SATA
4
CONN
PG 41
INTEL
SATA
J5100
J4501
PANTHER-POINT
C
HDD
I2C I2C ADC
BSB
Fan
SMC
PG 46
PG 44
U4900
C
PG 16
1
CONN
LPC
MOBILE
SATA
B,0
Prt
Port80,serial
PG 16
2
PG 85
Ser
LPC + SPI CONN
3
DP/T29
MUX
U1800
0
PG 41
PWR
CTRL
PG 17
U9220
U2700
LVDS
PCI
J5713/U5701
PG 52
8 9
J4600
7
SMC DEBUG PORT
PG 42
5
6
PG 25
EXTERNAL A
J4600
PG 42
J4610
PG 42
EXTERNAL B
U9270
B
0
B
PG 41/43
TRACKPAD/KEYBOARD
1 2
PG 18
IR
USB HUB
4
MINI DP PORT
PG 32
J4501/U4800
3
PG 17
PG 18
USB
J9400
(UP TO 14 DEVICES)
PG 84
PG 84
J3501
BLUETOOTH
10 11 12 13
DP DDC MUX
JTAG
SMB
LVDS DDC MUX
SMBUS
PG 16
PG 16
PG 84
CONNECTION
PCI-E
PEG
PG 47
HDA
(UP TO 16 LINES)
PG 16
PG 16
PG 16
DIMM
J9000
LVDS CONN
PG 27,29
PG 83
U9600
U6201
AUDIO
GMUX
CODEC
PG 86
PG 56
www.qdzbwx.com
U6610,6620,6630
U4100
A
U3900
FW643
LINE INPUT
ETHERNET
HEADPHONE
SPEATKER
FILTER
AMP
SYNC_MASTER=J31_MLB
FILTER
J3501
PG 57
PG 38
PG 58
SYNC_DATE=04/19/2011
PAGE TITLE
BCM57765B0
Revision History
PG 59
PG 36
DRAWING NUMBER
AirPort
Apple Inc.
J4310
J4000
PG 32
J3300
R
ETHERNET
CONN
CONN
SDCARD READER
J6700,J6750
NOTICE OF PROPRIETARY PROPERTY:
AUDIO
CONN
SPEATKER
CONN
PG 40
PG 37
PG 30
PG 60
7
3.0.0
J6781,J6782
FIREWIRE
8
051-9585
REVISION
6
5
4
PG 60
3
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
2
BRANCH
PAGE
2 OF 132
SHEET
2 OF 105
1
SIZE
D
A
8
7
6
5
4
VIN
J6900
AC
PP18V5_DCIN_CONN
PPBUS_G3H
V
IN
DCIN(18.5V)
U7000
Q5300
SMC_PBUS_VSENSE
PP3V42_G3H
SMC_ONOFF_L
MR2
ISL6259HRTZ
PPVBAT_G3H_CONN
1V05 T29
VOUT
PPBUS_G3H
PPVBUS_G3H
(R7640)
CPU VCCIO
VOUT
D
A
1V0 /
U5400
SMC_BMON_ISENSE
TBT_PWR_EN
PPCPUVCCIO_S0_REG
VIN
A
A
SMB_RST_N
(PAGE 64)
PP1V05_T29_FET
VOUT
SWITCH
(PAGE 35)
EN
U5310
PP5V_S0_CPUVCCIOS0
PPBUS_G3H
8A FUSE
1.05V
SMC_CPU_HI_ISENSE
3S2P
U3815 & U3816
V
R7050
Q7055
(PAGE 46)
(PAGE 63)
BATTERY CHARGER
SMC_RESET_L
PP3V3_S5_AVREF_SMC
REFOUT
VIN
PBUS SUPPLY/
SMC_DCIN_ISENSE
U5010
U6990
SMC_DCIN_VSENSE
VIN
A
(9 TO 12.6V)
1
SMC_RESET_L
RESET
SMC AVREF SUPPLY
MR1
SN0903048
F7040
Q5310
R7020
SMC_TPAD_RST_L
ENABLE
3.425V G3HOT
PM6640
R6990
ADAPTER
J6950
2
SMC RESET
F6905
6A FUSE
D
3
D6990
J31 POWER SYSTEM ARCHITECTURE
TPS22924
SMC_CPUVCCIO_ISENSE
ISL95870
PPVBAT_G3H_CHGR_R
U7600
CPUVCCIOS0_EN
PPBUS_G3H
U4202
VIN
VOUT
CPUVCCIOS0_PGOOD
PGOOD
PP1V0_FW_FET_R
(PAGE 39)
EN
EN
PM_S0_PGOOD
(PAGE 70)
Q7840
FW_PWR_EN
CHGR_BGATE
A
PP5V_SUS_FET
PP5V_S5_P5VSUSFET
U5450
U9950
V
U5410
SMC_GPU_HI_ISENSE
PM_PCH_SYS_PWROK
SMC_CPU_VSENSE
PPVCORE_S0_CPU
CPU/AXG VCORE
A
PP5V_S5_LDO
CPU VOUT
PPDDR_S3_REG
VIN
P5VS3_EN
EN1
VREG5
VOUT1
Q7801
P1V5CPU_EN
PP5V_S3_REG
5V
(L/H)
P3V3S5_EN
VOUT2
3.3V
(R/H)
EN2
P5VSUS_EN
VIN
ON
G
SLG5AP020
U7801
(PAGE 72)
USB PORT
POWER SWITCH
PP5V_S3_RTUSB_A_ILIM
5V
VOUT1
VIN
PP5V_S3_RTUSB_B_ILIM
U4600
(PAGE 42) VOUT2
PP18V5_S4
VIN
VOUT
TPS61045
U5805
(PAGE 66)
PGOOD1
PGOOD2
P3V3S5_PGOOD
EN1
USB_PWR_EN
SMC_SYS_KBDLED
PP3V3_S5
PP3V3_S0GPU_FET
VIN
DELAY
RC
P3V3S3_EN
S5
PM_SLP_SUS_L
P3V3S4_EN
SLP_S5*(D10) PM_SLP_S5_L
$CDS_IMAGE|R.jpg|272|166
R2526
(V13)
WOL_EN
U2150
(A2)
(Y2)
B
U2152
(A2)
(Y1)
TBT_PWR_EN
PM_SLP_S3_L
PM_SLP_S3_R_L
$CDS_IMAGE|R.jpg|272|166
PM_SLP_SUS_L
RC
DELAY
P5VSUS_EN
P1V2S0_EN
CPUVCCIOS0_EN
PB7A
VOUT
P3V3GPU_EN
RC
DELAY
EG_RAIL2_EN
GPUVCORE_EN
EG_RAIL3_EN
PVCCSA_EN
RC
DELAY
PCHVCCIOS0_EN
3A 32V FUSE
VIN
PB17A
XP25-5
PB17B
EG_RAIL4_EN
PB18A
(PAGE 88)
PL25A
P1V8GPU_EN
ALL_EG_PGOOD
PM_ALL_GPU_PGOOD
SMC_ONOFF_L
SMC_GPU_1V0_ISENSE
SSIOFSS/PA3
ISL6236
(H4)
POK1
(PAGE 77)
P1V0GPU_PGOOD
POK2
P1V5FB_PGOOD
PQ6/IRQ130(M6)
PM_SLP_S4_L
PM_SLP_S3_L
PQ4/IRQ128(N6)
PM_ALL_GPU_PGOOD
P1V5FB_PGOOD
U9701
VOUT
(PAGE 89)
VOUT
ALL_EG_PGOOD
V
VIN
ISL8014A
U7720
VOUT
U5310
PP1V8_S0_REG
PP5V_S3_GPUVCORE
P1V8S0_PGOOD
VDD/PVCC
P1V8GPU_EN
SMC_GPU_VSENSE
PPVCORE_GPU_REG
VOUT
GPU VCORE
A
A
SMC_GPU_ISENSE
SYNC_MASTER=K17_REF
ISL6263C
UD180
(RD186)
U9600
(PAGE 88)
V
VIN
PGOOD
$CDS_IMAGE|O.jpg|416|272
P5VS0_EN
P1V5CPU_EN
PM_SLP_S4_L
U8900
GPUVCORE_EN
Power Block Diagram
VR_ON
PGOOD
DRAWING NUMBER
GPUVCORE_PGOOD
Apple Inc.
(PAGE 83)
R
NOTICE OF PROPRIETARY PROPERTY:
MEMVTT_EN
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
www.qdzbwx.com
PBUSVSENS_EN
PM_SLP_S3_L
CPU_MEM_RESET_L
$CDS_IMAGE|O_1.jpg|416|272
MEM_RESET_L
8
7
051-9585
REVISION
3.0.0
R5388/U5388
P3V3S0_EN
PLT_RST_L $CDS_IMAGE|O_0.jpg|416|272
SYNC_DATE=06/30/2009
PAGE TITLE
VIN
PP1V8_GPU_FET
1V8GPU FET
PP1V8_S0GPU_ISNS
NCP4543IMN5RG-A
U7880
VOUT
A
(PAGE 72)
SMC_GPU_1V8_ISENSE
EN
PM_SLP_S3_L
SMC_RESET_L
GRAPHICS MUX
PL25A
(N1)
SMC_LCDBKLT_VSENSE
(PAGE 71)
RST*
(G10)
PWRGOOD
(AH16)
U8000
(PAGE 74)
P1V0GPU_PGOOD
PP1V05_SUS_LDO
PP3V3_S5_AVREF_SMC
LM4FSXAH5BB
U4900
(PAGE 44)
WHISTLER PCI-E
PPVOUT_SW_LCDBKLT
VREFA+
(D2)
PM_PWRBTN_L
PQ5/IRQ129(K5)
R9990
EN
PM_SYSRST_L
(J3)
PM_SLP_S5_L
VIN
B
WT3CCP0/PH4
BKLT_PLT_RST_L
PP3V3_SUS_P1V05SUSLDO
(M3) PM_DSW_PWRGD
PQ7/IRQ131(L6)
WT3CCP1/PH5
PP1V5_GPU_REG
U8300
LP8550
VIN
EN TPS720105
U7740
SMC_ADAPTER_EN
(B9)
S5_PWRGD(L9)
GPUVCORE_PGOOD
(PAGE 71)
ISOLATE_CPU_MEM_L
WT2CCP0/PH0(K3)
S5_PWRGD
A
Q7820
EN
ALL_SYS_PWRGD
PP3V3_S0_PWRCTL
& &
EN
P1V8S0_EN
SMC
EN2
SMC_LCDBKLT_ISENSE
PP3V3_SUS_FET
P1V5FB_EN
RESET*
(K51)
T1CCP1/PJ1
P3V3SUS_EN
U9600
(PAGE 9~13)
(PAGE 73)
VOUT1
VOUT2
P1V5FB_EN
LCD_BKLT_EN
PPBUS_SW_LCDBKLT_PWR
P1V0GPU_EN
V4MON
TRST = 200mS
A
VIN
1V2_S0(GMUX)
PP1V2_S0_REG
TPS62201 VOUT
U7760
(PAGE 71)
P1V5S0_EN
EN1
1.003V(L/H)
UD120
PPBUS_SW_BKL
LCD_BKLT_EN
EG_RAIL1_EN
PP1V05_S0_VMON
ISL88042IRTEZ
V3MON
RST*
1.503V(R/H)
U7710
(PAGE 71)
P1V2S0_EN
PVDDCI_PGOOD
1V0GPU/1V5 FB
PP1V5_S0_REG
P3V3SUS_EN
PB16B
GMUX
RC
DELAY
RC
DELAY
3.3V/5.0V
(A)
(Y)
SUS ENABLE
(C) U7940
(PAGE 73)
P1V8S0_EN
PGOOD
P1V0GPU_EN
F9700
T29_A_HV_EN
PP1V5_S3RS0_VMON
PP1V0_S0GPU_REG
Q9706
VIN
EN TPS62201
P1V5S0_EN
RC
DELAY
SMC_BATLOW_L
U9800
(PAGE 90)
PPVDDCI_S0_REG
UD141
(RD145)
(PAGE 88)
T29_A_HV_EN_R
R9334
EN
VOUT
CPU_RESET_L
U1000
U7960
GPU VDDCI
0V9~1V15
ISL95870A
PP3V3_S4_FET
R7978
PORT A MCU
U9330
(18)
(PAGE 86)
V2MON
VIN
LCD_PWR_EN
GMUX
LCD_PWR_EN
U9600(N8)
CPU_PWRGD
UNCOREPWRGOOD
(C60)
VCC
PP5V_S0_VMON
EN
PM_MEM_PWRGD
CPU
SM_DRAMPWROK
(AY25)
PVCCSA_PGOOD
(PAGE 65)
EN
(PAGE 16~21)
A
PP3V3_S0_VMON
PGOOD
VOUT
FPF1009
VIN U9000
VOUT PP3V3_SW_LCD_UF
(PAGE 84)
EN
FW_PWR_EN
(PAGE 24)
SLP_S3#(F4)
FWPORT_PWR_EN
U4260
(PAGE 39)
(PAGE 73)
SMC_CPUVCCSA_ISENSE
U7100
P3V3S4_EN
(PAGE 39)
AUD_IPHS_SWITCH_EN_PCH
VIN
TPS22924
PP3V3_FW_FET
VIN U4201
VOUT
(PAGE 24)
(U2)
VOUT
PVCCSA_EN
PPBUS_FW_FET
PVDDCI_EN
FW_PWR_EN
PM_RSMRST_L
RESET
U7930
PPVCCSA_S0_REG
ISL95870A
FIREWIRE PORT
EN
$CDS_IMAGE|R.jpg|272|166
FW_PWR_EN_PCH
SYSTEM AGENT
VOUT
POWER SWITCH
3.3V
PP3V3_T29_FET
TPS22924
VIN U3810 VOUT
P3V3S0_EN
(PAGE 35)
Q7800
TBT_PWR_EN
EN
PM_MEM_PWRGD
3V3 SUS DETECT
ALL_SYS_PWRGD_R
U5360
(R7140)
(PAGE 67)
VIN
EN
T29_A_HV_EN
T29 SWITCH
PP3V3_S0_FET
R7916
C
CPU_PWRGD
(AY11)
(C21)
U1800
(PAGE 16~21)
PCHVCCIOS0_PGOOD
Q7830
SLP_SUS
PLT RESET L
DRAMPWROK
RSMRST#
CPUVCCIOS0_PGOOD
PPVTT_S0_DDR_LDO
TPS51916
DDRREG_PGOOD
U7300
PGOOD
PP15V_T29_REG
LT3957
VIN U3890
(PAGE 35)
P5VS3_EN
XDP_DB2_WOL_EN
VOUT2
SMC_ADAPTER_EN
PVCCSA_PGOOD
T29 15V BOOST
P3V3S3_EN
PM_SLP_S3_L & WOL_EN & SMC_ADAPTER_EN
PROCPWRGD
SMC_DDR3_ISENSE
0.75V
(PAGE 57)
DELAY
(D14)
VOUT1
DDRVTT_EN
S3
PP3V3_ENET_FET
PM_SLP_S4_L
P1V8S0_PGOOD
P5VS3_PGOOD
PP1V5_S3
PPDDR_S3_REG
A
PP4V5_AUDIO_ANALOG
Q7922
DDRREG_EN
U5360
(R7350)
VLDOIN
PM_SYSRST_L
PM_DSW_PWRGD
ACPRESENT/GPIQ31
(H20)
PLTRST#
(C6)
SYS_PWROK
P1V5S0_PGOOD
VIN
1.5V
PM_PWRBTN_L
(K3)
DPWROK
(E22)
PP5V_S3_DDRREG
VOUT
U1800
SLP_S4#(H4)
CPUIMVP_AXG_PGOOD
PGOKB
Q7810
PP3V3_S3_FET
RC
U6200
SHND
DELAY
MOBILE
CPUIMVP_PGOOD
PGOKA
MAX8840
PP3V3_S0_AUDIO
P3V3GPU_EN
COUGAR-POINT
EN
EN2
4.5V AUDIO
P5VS0_EN
P3V3S5_EN
RC
COUGAR_POINT
PWRBTN#
(E20)
SYS_RERST#
SMC_AXG_ISENSE
DDRREG_EN
U4900
M2 SMC_PM_G2_EN
CPUIMVP_VR_ON
A
CPUIMVP_VR_ON
VIN
CTRL
LED
KB_BL
LT3491
U5850
(PAGE 54)
PP5V_S0_FET
Q7870
H10 SMC_BATLOW_L
(PAGE 45)
PPVCORE_S0_AXG_REG
(PAGE 68)
Q7860
SMC
U9950
V
(PAGE 54)
P5VS3_PGOOD
C
PM_PCH_PWROK
SMC_AXG_VSENSE
U5460
U7400
P1V5S3RS0FET_GATE
TPS51980
U7201
VIN
PP1V5_S3RS0_FET
PP5V_S5_LDO
PP3V3_S5_REG
MAX15119GTM
SMC_CPU_ISENSE
6
5
4
3
2
BRANCH
PAGE
3 OF 132
SHEET
3 OF 105
1
SIZE
D
A
8
7
6
5
4
3
2
1
D
D
C
C
B
B
A
SYNC_MASTER=MASTER
SYNC_DATE=MASTER
PAGE TITLE
Revision History
DRAWING NUMBER
Apple Inc.
051-9585
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
3.0.0
BRANCH
PAGE
4 OF 132
SHEET
4 OF 105
1
SIZE
D
A
8
7
6
5
4
3
2
1
BOM VARIANTS - FSB
TABLE_BOMGROUP_HEAD
BOM NUMBER
BOM NAME
BOM OPTIONS
Bar Code Labels
-
/ EEEE #’s
|
TABLE_BOMGROUP_ITEM
PART NUMBER
639-3860
PCBA,MLB_2P,FSB,2.3,FOX,512_HYN,REN,J31,F327
J31_CMNPTS,SODIMM:FOXCONN,CPU:2_3GHZ,FB_512_HYNIX,FET:REN,DEVEL_BOM,GPUDEC:EXP,EEEE:F327
639-3861
PCBA,MLB_2P,FSB,2.3,MOL,512_SAM,FAIR,J31,F32C
J31_CMNPTS,SODIMM:MOLEX,CPU:2_3GHZ,FB_512_SAMSUNG,FET:FAIR,DEVEL_BOM,GPUDEC:EXP,EEEE:F32C
QTY
DESCRIPTION
REFERENCE DES
CRITICAL
BOM OPTION
TABLE_BOMGROUP_ITEM
826-4393
1
LBL,P/N LABEL,PCB,28MM X 6 MM
[EEEE_F327]
CRITICAL
EEEE:F327
826-4393
1
LBL,P/N LABEL,PCB,28MM X 6 MM
[EEEE_F32C]
CRITICAL
EEEE:F32C
826-4393
1
LBL,P/N LABEL,PCB,28MM X 6 MM
[EEEE_F325]
CRITICAL
EEEE:F325
826-4393
1
LBL,P/N LABEL,PCB,28MM X 6 MM
[EEEE_F324]
CRITICAL
EEEE:F324
826-4393
1
LBL,P/N LABEL,PCB,28MM X 6 MM
[EEEE_F328]
CRITICAL
EEEE:F328
826-4393
1
LBL,P/N LABEL,PCB,28MM X 6 MM
[EEEE_F329]
CRITICAL
EEEE:F329
TABLE_BOMGROUP_ITEM
639-3862
PCBA,MLB_2P,FSB,2.6,MOL,1G_HY,FAIR,J31,F325
J31_CMNPTS,SODIMM:MOLEX,CPU:2_6GHZ,FB_1G_HYNIX_A_DIE,FET:FAIR,DEVEL_BOM,GPUDEC:EXP,EEEE:F325
639-3863
PCBA,MLB_2P,FSB,2.6,FOX,1G_SAM,REN,J31,F324
J31_CMNPTS,SODIMM:FOXCONN,CPU:2_6GHZ,FB_1G_SAMSUNG,FET:REN,DEVEL_BOM,GPUDEC:EXP,EEEE:F324
639-3864
PCBA,MLB_2P,FSB,2.7,FOX,1G_HY,REN,J31,F328
J31_CMNPTS,SODIMM:FOXCONN,CPU:2_7GHZ,FB_1G_HYNIX_A_DIE,FET:REN,DEVEL_BOM,GPUDEC:EXP,EEEE:F328
639-3865
PCBA,MLB_2P,FSB,2.7,MOL,1G_SAM,FAIR,J31,F329
J31_CMNPTS,SODIMM:MOLEX,CPU:2_7GHZ,FB_1G_SAMSUNG,FET:FAIR,DEVEL_BOM,GPUDEC:EXP,EEEE:F329
607-9557
CMN PTS,PCBA,MLB_KEPLER,J31
J31_COMMON
085-4620
J31 MLB_KEP_2P DEVELOPMENT BOM
J31_DEVEL:PVT
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
D
D
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
SUB BOMS
PART NUMBER
DESCRIPTION
REFERENCE DES
085-4620
QTY
1
J31 MLB_KEP_2P DEVELOPMENT BOM
DEVEL
CRITICAL
CRITICAL
BOM OPTION
DEVEL_BOM
607-9557
1
CMN PTS,PCBA,MLB_KEP_2P,J31
CMNPTS
CRITICAL
J31_CMNPTS
BOM GROUPS
TABLE_BOMGROUP_HEAD
BOM GROUP
BOM OPTIONS
J31_COMMON
ALTERNATE,COMMON,J31_COMMON1,J31_COMMON2,J31_PROGPARTS,J31_PROGPARTS1,UVGLUE_J31,J31_PVT
J31_COMMON1
CPUMEM_S0,RAMCFG_SLOT,USBHUB2513B,HUB_3NONREM,SMC_PACKAGE:PROD,MOJO:YES,TBTHV:P15V,SKIP_5V3V3:AUDIBLE
J31_COMMON2
BTPWR:S4,TPAD:Z2,T29:YES,TBTBST:Y,SDRV_PD,SDRVI2C:MCU,T29_DP_HPD:ALL_OR,LPCPLUS_R:YES,MEM_VDD_SEL:GPIO15,GPU:2P
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
Alternate Parts
TABLE_BOMGROUP_ITEM
(Alternate)
(Primary)
TABLE_BOMGROUP_ITEM
J31_PROGPARTS
J31_PROGPARTS1
TABLE_ALT_HEAD
GMUX_PROG,IR_PROG,TPAD_PROG:FSB,ENETROM_PROG:FSB,T29ROM:PROG,T29MCU:PROG
SMC_PROG:RR,BOOTROM_PROG:FSB
PART NUMBER
ALTERNATE FOR
PART NUMBER
157S0058
157S0055
BOM OPTION
REF DES
COMMENTS:
ALL
Delta alt to TDK Magnetics
Programmables - All Builds
TABLE_BOMGROUP_ITEM
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
J31_PVT
VREF:PROD,XDP,XDP_CPU:BPM,BKLT:PROD,LOADISNS:NO,XWLOADISNS:NO
J31_DEVEL:ENG
DDRVREF_DAC,VREF:ENG_M3,IVB_PPT_XDP,GMUX_JTAG_CONN,LPCPLUS_CONN:YES,BKLT:ENG,S0PGOOD_ISL,CPURIPPLE_ENG,LOADISNS:YES,XWLOADISNS:YES,DEBUG_ADC
TABLE_ALT_ITEM
152S0896
152S0518
ALL
MAG LAYERS ALT TO CYNTEC
155S0457
155S0329
ALL
MAG LAYERS ALT TO MURATA
353S2805
353S2603
ALL
Fairchild wafer option
TABLE_BOMGROUP_ITEM
TABLE_ALT_ITEM
PSOC
TABLE_BOMGROUP_ITEM
J31_DEVEL:FSB
DDRVREF_DAC,VREF:ENG_M3,IVB_PPT_XDP,LPCPLUS_CONN:YES,BKLT:PROD,S0PGOOD_ISL,LOADISNS:YES,XWLOADISNS:NO
TABLE_ALT_ITEM
341S3099
1
IC,TP PSOC,K9x,DVT,PVT,J31
U5701
CRITICAL
TPAD_PROG:PROTO0
TABLE_ALT_ITEM
341S3351
1
IC,TP PSOC,PROTO1,J31
U5701
CRITICAL
TPAD_PROG:PROTO1
341S3227
1
IC,TP PSOC,PROTO2,PROTO3-Z2,J31
U5701
CRITICAL
TPAD_PROG:PROTO3
TABLE_BOMGROUP_ITEM
C
J31_DEVEL:PVT
LPCPLUS_CONN:YES,XDP_CONN_CPU
IVB_PPT_XDP
XDP,XDP_CONN_PCH,XDP_CONN_CPU,XDP_CPU:BPM,XDP_PCH
128S0264
128S0257
ALL
128S0282
ALL
C
Sanyo alt to Kemet
128S0303
Panasonic alt to Sanyo
TABLE_BOMGROUP_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
353S1658
ALL
376S0612
ALL
1
IC,TP PSOC,PIB,J31
U5701
CRITICAL
TPAD_PROG:PIB
341S3522
1
IC,TP PSOC,FSB,J31
U5701
CRITICAL
TPAD_PROG:FSB
ST Micro alt to LT
376S0972
341S3489
TABLE_ALT_ITEM
353S3085
ROHM alt to Toshiba N-FET
TABLE_ALT_ITEM
376S0855
376S0613
ALL
Diodes alt to Toshiba dual N-FET
138S0676
138S0691
ALL
Murata alt to Samsung cap
138S0652
138S0648
ALL
Samsung / Murata alt for Taiyo Yuden
138S0681
138S0638
ALL
Taiyo Yuden alt for Samsung
152S0685
152S0796
ALL
Dale/Vishay/TDK
376S0977
376S0859
ALL
Diodes alt for Rohm
353S2592
353S3199
ALL
U6201 AUDIO CODEC OLD REV IS ALTERNATE FOR NEW REV
335S0550
335S0777
ALL
add 4K byte as alternative to 2K
371S0709
371S0652
ALL
NXP alternate for pin diodes
138S0671
138S0673
ALL
Taiyo Yuden alt for Murata 10 uF caps
514-0788
514-0671
ALL
Acon (with liteon) alt to Acon
155S0578
155S0367
ALL
Tayo Yuden alt to Murata inductors
TABLE_ALT_ITEM
TABLE_ALT_ITEM
341S2830
1
IC,CPLD,LATTICE,GMUX,K91/K91F,J31
U9600
CRITICAL
GMUX_PROG
336S0042
1
IC,PLD,LATTICE,LFXP2-5E-5,132 BALL CSBGA
U9600
CRITICAL
GMUX_BLANK
341S2384
1
IR,ENCORE II,CY7C63833-LFXC
U4800
CRITICAL
IR_PROG
341S3430
1
IC,T29 EEPROM,LR,J30/J31
U3690
CRITICAL
T29ROM:PROG
T29ROM:BLANK
TABLE_ALT_ITEM
TABLE_BOMGROUP_HEAD
BOM GROUP
BOM OPTIONS
VREF:PROD
VREFDQ:M1_M3,VREFCA:LDO
TABLE_ALT_ITEM
alt for Cyntec
TABLE_BOMGROUP_ITEM
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
VREF:ENG_M3
VREFDQ:M1_M3,VREFCA:LDO_DAC
VREF:ENG_LDO
VREFDQ:M1_DAC,VREFCA:LDO_DAC
TABLE_ALT_ITEM
335S0777
1
IC,EEPROM,SERIAL,8KB,SOIC
U3690
CRITICAL
341S3365
1
IC,PROGRMD,LPC1112A,T29 PORT MCU,PVT,HVQFN25,J31
U9330
CRITICAL
T29MCU:PROG
337S3997
1
IC,MCU,32B,LPC1112A,16KB/2KB,HVQFN25
U9330
CRITICAL
T29MCU:BLANK
335S0852
1
IC,GPUROM,J31,BLANK
U8701
CRITICAL
GPUROM:BLANK
TABLE_BOMGROUP_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
Module Parts
PART NUMBER
QTY
TABLE_ALT_ITEM
DESCRIPTION
REFERENCE DES
CRITICAL
BOM OPTION
TABLE_ALT_ITEM
TABLE_ALT_ITEM
337S4266
1
IC,CPU,IVB,S,R0MP,PRQ,E1,2.3,45W,4+2,1.2,6M,BGA
U1000
CRITICAL
CPU:2_3GHZ
337S4267
1
IC,CPU,IVB,S,R0MM,PRQ,E1,2.6,45W,4+2,1.25,6M,BGA
U1000
CRITICAL
CPU:2_6GHZ
337S4268
1
IC,CPU,IVB,S,R0MK,PRQ,E1,2.7,45W,4+2,1.25,8M,BGA
U1000
CRITICAL
CPU:2_7GHZ
1
IC,PCH,PPT,C1,SLJ8C,PRQ,BD82HM77
U1800
1
IC,GPU,NV GK107-GTX-QS-A2
U8000
1
IC,ASSP,LIGHTRIDGE,PRQ,S LJJY,FCBGA,15X15MM,C1
U3600
CRITICAL
IC,FW643-E,1394B PHY/OHCI LINK/PCI-E,12
U4100
1
IC,PI3VEDP212,X2 DISPLAYPORT 2:1 MUX,QFN
U9390
376S0761
ALL
ALL
4
IC,SGRAM,GDDR5,32MX32.1.25GHz,G-DIE,HF
U8400,U8450,U8500,U8550
CRITICAL
CRITICAL
ENETROM_PROG:FSB
333S0620
4
IC,SDRAM,GDDR5,32MX32,1.5GHz,VEGA 44NM,B-DIE
U8400,U8450,U8500,U8550
CRITICAL
ALL
376S1053
376S0604
ALL
371S0558
ALL
128S0311
U8400,U8450,U8500,U8550
CRITICAL
4
IC,SGRAM,GDDR5,64MX32,4.2GBPS,M-DIE,HF
U8400,U8450,U8500,U8550
CRITICAL
CRITICAL
SMC_BLANK
U4900
CRITICAL
SMC_PROG:PROTO0
341S3294
1
IC,SMC,DEVELOPMENT-PROTO1,J31
U4900
CRITICAL
SMC_PROG:PROTO1
341S3401
1
IC,EXTERNAL,PROTO2,PROTO3,J31
U4900
CRITICAL
SMC_PROG:PROTO3
341S3481
1
IC,SMC,EXTERNAL,PIB,V2.1A83,A3,J31
U4900
CRITICAL
128S0329
ALL
SMC_PROG:A3_PIB
341S3296
1
IC,SMC,EXTERNAL,FSB,V2.1A143,J31
U4900
CRITICAL
SMC_PROG:FSB
341S3297
1
IC,SMC,EXTERNAL,RISKRAMP,J31
U4900
CRITICAL
SMC_PROG:RR
Radar 10257464
TABLE_ALT_ITEM
TABLE_ALT_ITEM
FB_1G_HYNIX_A_DIE
333S0609
U4900
IC,SMC,DEVELOPMENT-PROTO0,J31
Radar 10562508
FB_1G_SAMSUNG
IC,SGRAM,GDDR5,64MX32,5GBPS,A-DIE,HF
IC,SMC,HS8/2117,9MMX9MM,TLP
1
Radar 10562726
371S0713
4
1
341S3258
For Q7260, Fairchild alt to Ren.
FB_512_HYNIX
333S0630
B
NXP alternate to Pericom DP mux
ALL
338S0895
TABLE_ALT_ITEM
353S3055
376S0953
FB_512_SAMSUNG
CRITICAL
U3990
TABLE_ALT_ITEM
333S0619
U8400,U8450,U8500,U8550
IC,PRGRMD,ENET,SPI ROM,FSB,J30/J31
TABLE_ALT_ITEM
353S3312
IC,SGRAM,GDDR5,64MX32,5GBPS,D-DIE,HF
1
TABLE_ALT_ITEM
376S0958
4
341S3492
SMC
TDK alternate for ethernet transformer
CRITICAL
333S0631
ENETROM_PROG:PROTO3
AON alternate to Siliconix
157S0055
T29:YES
CRITICAL
353S3055
ENETROM_BLANK
CRITICAL
TABLE_ALT_ITEM
157S0084
1
CRITICAL
U3990
TABLE_ALT_ITEM
376S0777
338S0753
U3990
IC,ENET ROM,1MBIT,DVT,PVT,K90i/K91x,J31
Murata alt to TDK cm mode filter
CRITICAL
338S1072
ALL
IC,FLASH,SERIAL,SPI,1MBIT,2V7,8P,SOIC
1
Tayo Yuden alt to Murata caps
155S0559
1
341S3096
Tayo Yuden alt to Samsung caps
ALL
CRITICAL
337S4239
ALL
138S0673
155S0625
337S4269
138S0638
138S0671
335S0663
TABLE_ALT_ITEM
138S0681
B
ETHERNET ROM
TABLE_ALT_ITEM
FB_1G_HYNIX_M_DIE
TABLE_ALT_ITEM
127S0134
127S0111
ALL
Radar 10360888
127S0127
127S0090
ALL
Radar 10382328
197S0431
197S0432
ALL
RADAR 10670230
EFI ROM
TABLE_ALT_ITEM
335S0740
SODIMM:FOXCONN
516-0246
1
CONN,204P,SODIMM,SOCKET,DDR3,p=0.6M,FOXCONN
J2900
CRITICAL
SODIMM:FOXCONN
1
CONN,204P,SODIMM,SOCKET,DDR3,RAM,BGA,MOLEX
J3100
CRITICAL
CONN,204P,SODIMM,SOCKET,DDR3,p=0.6M,MOLEX
J2900
CRITICAL
ALL
1
IC,EFI,ROM,PROTO1, J31
U6100
CRITICAL
BOOTROM_PROG:PROTO1
1
IC,EFI,ROM,PROTO2,J31
U6100
CRITICAL
BOOTROM_PROG:PROTO2
1
IC,EFI,ROM,PROTO3,J31
U6100
CRITICAL
BOOTROM_PROG:PROTO3
1
IC,EFI,ROM,POST-PIB,J31
U6100
CRITICAL
BOOTROM_PROG:PIB2
1
IC,EFI,ROM,FSB,J31
U6100
CRITICAL
BOOTROM_PROG:FSB
RADAR 10739227
197S0343
ALL
RADAR 10739227
TABLE_ALT_ITEM
SODIMM:MOLEX
516S0805
1
CONN,204P,SODIMM,SOCKET,DDR3,RAM,BGA,MOLEX
J3100
CRITICAL
SODIMM:HYBRID
516-0246
A
197S0343
SODIMM:MOLEX
1
BOOTROM_PROG:PROTO0
TABLE_ALT_ITEM
197S0435
516S0805
BOOTROM_BLANK
CRITICAL
TABLE_ALT_ITEM
197S0434
516-0245
CRITICAL
U6100
341S3476
UVGLUE_J31
CRITICAL
U6100
341S3510
CRITICAL
J3100
IC,EFI,ROM,PROTO0, J31
341S3454
UV_GLUE_J31
CONN,204P,SODIMM,SOCKET,DDR3,RAM,BGA,FOXCONN
64 MBIT SPI SERIAL DUAL I/O FLASH
341S3419
MLB LOCTITE UV EB CPU,PCH,T29,GPU,K91
1
1
341S3344
1
516S0806
1
341S3257
725-1479
1
CONN,204P,SODIMM,SOCKET,DDR3,p=0.6M,FOXCONN
J2900
CRITICAL
SODIMM:HYBRID
PD Parts
376S0964
2
RJK0225
Q7330,Q8360
CRITICAL
FET:REN
376S0965
2
RJK0225
Q7335,Q8361
CRITICAL
FET:REN
SYNC_MASTER=K17_REF
PART NUMBER
QTY
DESCRIPTION
REFERENCE DES
CRITICAL
BOM OPTION
SYNC_DATE=05/28/2009
PAGE TITLE
BOM Configuration
376S0979
2
FDMC0225
Q7330,Q8360
CRITICAL
FET:FAIR
452-1708
2
SCR,M1.6X0.35X6.0,D4,HO.3,BLK,M97
SODIMM_SCREW1,SODIMM_SCREW2
CRITICAL
376S0874
2
FDMC0202S
Q7335,Q8361
CRITICAL
FET:FAIR
452-1708
2
SCR,M1.6X0.35X6.0,D4,HO.3,BLK,M97
SODIMM_SCREW3,SODIMM_SCREW4
CRITICAL
DRAWING NUMBER
376S0826
1
376S0617
376S0917
Q7030
CRITICAL
1
FET,N-CH,30V,30A,6.7MOHM,RJK0305DPB
Q7035
CRITICAL
FET:REN
1
376S1018
FET,N-CH,30V,3.6MOHM,LF,HF,FDMS0355S
Q7030
CRITICAL
FET:FAIR
1
8
FET,N-CH,30V,3.6MOHM,LF,HF,RJK0332DPB
FET,N-CH,30V,14A,13MOHM,FDMS0349
Q7035
CRITICAL
FET:FAIR
7
FET:REN
6
725-1607
1
GPU_INSULATOR
Apple Inc.
INSULATOR,GPU,J31
CRITICAL
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
5
4
051-9585
REVISION
3
2
3.0.0
BRANCH
PAGE
5 OF 132
SHEET
5 OF 105
1
SIZE
D
A
8
7
6
5
I1102
I1104
TRUE
I1105
TRUE
I1107
Functional Test Points
J5713 (KEY BOARD CONN)
PP3V3_S4
TRUE
PP3V42_G3H
TRUE
TRUE
I1103
J5650 (LEFT FAN CONN)
FUNC_TEST
TRUE
PP5V_S0
I1106
TRUE
FAN_LT_PWM
52
I1108
TRUE
TRUE
FAN_LT_TACH
GND
52
I1109
TRUE
I1110
TRUE
I1111
TRUE
TRUE
I1112
D
6 7
FAN_RT_PWM
FAN_RT_TACH
52
TRUE
52
TRUE
TRUE
I1117
PP5V_S0
TRUE
I1114
I1115
TRUE
I1493
TRUE
I1116
J3501 & J3502 (AIRPORT/BT/CAMERA CONN)
I557
TRUE
TRUE
I1120
I1122
TRUE
I1121
TRUE
I1053
GND
TRUE
TRUE
TRUE
TRUE
I1058
6 7
TRUE
PCIE_WAKE_L
TRUE
WIFI_EVENT_L
AP_RESET_CONN_L
I1057
I989
I990
TRUE
I991
TRUE
I994
TRUE
I993
TRUE
C
TRUE
I1063
TRUE
I1062
TRUE
I1064
61 62 101
SPKRCONN_S_OUT_P
SPKRCONN_S_OUT_N
TRUE
I992
SPKRCONN_L_OUT_P
SPKRCONN_L_OUT_N
SPKRCONN_R_OUT_P
SPKRCONN_R_OUT_N
TRUE
TRUE
I1060
J6781 & J6782 (SPEAKERS CONN)
TRUE
I1061
6 7
TRUE
I1059
I1671
PCIE_CLK100M_AP_CONN_N
AP_CLKREQ_Q_L
I1496
6 TPs
PP5V_S0
PP3V42_G3H
TRUE
I1672
TRUE
I1055
J5100
TRUE
I1056
2 TPs
TRUE
I1052
62 63 101
GND
TRUE
PCIE_AP_R2D_P
PCIE_AP_R2D_N
PCIE_CLK100M_AP_CONN_P
TRUE
I1123
TRUE
32 96
I1124
TRUE
32 101
I1125
TRUE
32 101
I1127
TRUE
32
I1126
61 62 101
TRUE
I728
TRUE
I730
TRUE
LPC_PWRDWN_L
I731
TRUE
PM_CLKRUN_L
17 24 45
I995
I996
TRUE
I997
PP3V3_SW_LCD
PP3V3_S0
PPVOUT_S0_LCDBKLT
I734
TRUE
I998
TRUE
LVDS_DDC_CLK
I1000
TRUE
I1001
TRUE
LVDS_DDC_DATA
LVDS_CONN_A_DATA_P & lt; 0 & gt;
I1002
TRUE
I1004
TRUE
I1003
TRUE
I1005
TRUE
I1007
TRUE
I1006
TRUE
I1009
TRUE
I1010
LVDS_CONN_A_DATA_N & lt; 1 & gt;
LVDS_CONN_A_DATA_P & lt; 2 & gt;
LVDS_CONN_A_DATA_N & lt; 2 & gt;
LVDS_CONN_A_CLK_F_P
LVDS_CONN_A_CLK_F_N
TRUE
I1008
LVDS_CONN_A_DATA_N & lt; 0 & gt;
LVDS_CONN_A_DATA_P & lt; 1 & gt;
TRUE
I1011
TRUE
I1012
TRUE
I1014
TRUE
I1013
LVDS_CONN_B_DATA_P & lt; 0 & gt;
LVDS_CONN_B_DATA_N & lt; 0 & gt;
LVDS_CONN_B_DATA_P & lt; 1 & gt;
LVDS_CONN_B_DATA_N & lt; 1 & gt;
LVDS_CONN_B_DATA_P & lt; 2 & gt;
TRUE
I1015
TRUE
I1016
TRUE
I1017
TRUE
I1018
LVDS_CONN_B_DATA_N & lt; 2 & gt;
LVDS_CONN_B_CLK_F_P
LVDS_CONN_B_CLK_F_N
TRUE
I1019
TRUE
I1020
TRUE
I1022
TRUE
I1021
LED_RETURN_1
LED_RETURN_2
LED_RETURN_3
TRUE
LED_RETURN_4
LED_RETURN_5
LED_RETURN_6
I739
TRUE
SMC_RX_L
45 46 47
I738
TRUE
53
I741
TRUE
53
I742
TRUE
53
I743
TRUE
SMC_TDO
SMC_TMS
SMC_ROMBOOT
2 TP needed
TRUE
USB_BT_CONN_P
USB_BT_CONN_N
53
I744
TRUE
SMC_TX_L
I751
TRUE
I752
TRUE
SPIROM_USE_MLB
SPI_ALT_CLK
I760
TRUE
SPI_ALT_CS_L
47
I756
TRUE
SPI_ALT_MISO
47
53
53
53
TRUE
TRUE
SPI_ALT_MOSI
TRUE
SYS_LED_ANODE_R
41
6 45 48 99
17
16
TRUE
PP5V_S3_IR_R
I1149
TRUE
41 46
TRUE
TRUE
16
SYS_LED_ANODE
6 64
16
I1025
I1028
I1027
I1029
33 6
33 6
TRUE
TRUE
TRUE
I1509
TRUE
I1086
TRUE
85 86 100
I1508
TRUE
85 86 100
I1273
TRUE
TRUE
I1033
TRUE
I1035
I1034
TRUE
I640
TRUE
I602
TRUE
TRUE
TBT_R2D_C_P & lt; 1..0 & gt;
TBT_R2D_C_N & lt; 1..0 & gt;
33 6
33 6
TRUE
I1485
I1089
TRUE
I1088
85 86 100
I1090
TRUE
85 86 100
I1464
TRUE
85 100
I1098
TRUE
I606
TRUE
TRUE
85 100
I1097
TRUE
I610
TRUE
I612
TRUE
I611
TRUE
I1487
TRUE
I1095
TRUE
I1096
TRUE
I1092
TRUE
85 90
I1093
TRUE
85 90
I1094
TRUE
85 90
I1099
TRUE
I1100
TRUE
I623
TRUE
TRUE
I621
TRUE
DP_TBTSNK0_AUXCH_C_N
DP_TBTSNK0_AUXCH_P
I1491
TRUE
DP_TBTSNK0_AUXCH_N
33 98
33 6
I1490
TRUE
DP_TBTSNK0_ML_C_P & lt; 3..0 & gt;
33 81 98
33 6
I1492
TRUE
DP_TBTSNK0_ML_C_N & lt; 3..0 & gt;
7
I1563
TRUE
DP_TBTSNK0_ML_P & lt; 3..0 & gt;
7
I1562
TRUE
DP_TBTSNK0_ML_N & lt; 3..0 & gt;
I1564
TRUE
I618
TRUE
53 54
33 81 98
33
33 98
33
I1567
TRUE
I1569
TRUE
DP_TBTSNK1_ML_C_P & lt; 3..0 & gt;
6 7 101
I1568
TRUE
DP_TBTSNK1_ML_C_N & lt; 3..0 & gt;
TRUE
I1639
A
I1690
I1691
I1692
TRUE
TRUE
TRUE
I1573
TRUE
TP_DP_TBTSRC_AUXCH_CP
6 33
I1574
TRUE
TP_DP_TBTSRC_ML_CP & lt; 3..0 & gt;
6 33
I1575
TRUE
TP_DP_TBTSRC_ML_CN & lt; 3..0 & gt;
6 33
45 46
6 7
6 7
TRUE
PP5V_S3
I639
TRUE
DP_SDRVA_ML_C_P & lt; 0 & gt;
DP_SDRVA_ML_C_N & lt; 0 & gt;
TRUE
I636
TRUE
TRUE
I709
TRUE
TRUE
I1161
TRUE
TRUE
DP_SDRVA_ML_C_P & lt; 2 & gt;
87 98
I1579
TRUE
DP_SDRVA_ML_C_N & lt; 2 & gt;
87 98
TRUE
DP_SDRVA_ML_P & lt; 0 & gt;
18
16
7
I1580
87 98
16
PPVCORE_S0_CPU
I1160
GND
I714
I1578
7
PPVCORE_GPU
6 45 48 99
6 45 48 99
7
PPBUS_G3H
PPDCIN_G3H
18
PPVP_FW
PPVTTDDR_S3
I1581
TRUE
DP_SDRVA_ML_N & lt; 0 & gt;
87 98
7
I1583
TRUE
DP_SDRVA_ML_P & lt; 2 & gt;
87 98
7
I1582
TRUE
DP_SDRVA_ML_N & lt; 2 & gt;
87 98
TP_TBT_PCIE_RESET0_L
6 33
7
16
16
I1588
TRUE
TP_TBT_PCIE_RESET3_L
6 33
I1589
TRUE
41 95
I1590
J6900 (DC POWER CONN)
ADAPTER_SENSE
TRUE
PP18V5_DCIN_FUSE
TRUE
TRUE
PEG_D2R_C_P & lt; 7..0 & gt;
PEG_D2R_C_N & lt; 7..0 & gt;
PEG_R2D_P & lt; 7..0 & gt;
I1833
41 95
TRUE
PEG_R2D_N & lt; 7..0 & gt;
I1586
TRUE
64
2 TPs
64
NC NO_TESTs
GND
2 TPs
4 TPs
53
75 93
75 93
75 92 93
75 92 93
NO_TEST
16
41
16
J6950 (MAIN BATT CONN)
PPVBAT_G3H_CONN
TRUE
SMBUS_SMC_5_G3_SCL
TRUE
SMBUS_SMC_5_G3_SDA
TRUE
SYS_DETECT_L
3 TPs
16
64
65
6 45 48 99
I1598
TRUE
TP_FW643_VAUX_ENABLE
38
16
I1600
TRUE
TP_FW643_VBUF
6 45 48 99
I1613
TRUE
TP_FW643_SCIFCLK
38
I1601
TRUE
TP_FW643_TCK
38
6 64
I1612
TRUE
TP_FW643_SCIFDAIN
38
I1602
TRUE
TP_FW643_TDO
TRUE
TRUE
TRUE
IR_RX_OUT
PP5V_S3_IR_R
SSD_OOBD2R_L
SSD_OOBR2D_L
38
38
16
16
16
GND
TRUE
TP_FW643_SCIFDOUT
38
I1599
TRUE
TRUE
TP_FW643_SCIFMC
38
I1603
TRUE
TP_SMC_P10
I1592
TRUE
TP_FW643_SDA
38
I1605
TRUE
TP_P7_7
53
I1591
TRUE
TP_FW643_SE
38
I1604
TRUE
TP_PSOC_SCL
53
I1593
TRUE
TP_FW643_SM
38
I1606
TRUE
TP_PSOC_SDA
53
TRUE
TP_FW643_CE
38
I1595
TRUE
TP_FW643_FW620_L
38
I1631
TRUE
I1596
7 TPs
I1614
I1615
TRUE
TP_FW643_TMS
TRUE
TP_FW643_JASI_EN
38
I1630
I1624
38
6 41 44
16
6 41
41
41
I1142
J6955 (BAT LED CONN)
PP3V42_G3H
TRUE
SMBUS_SMC_5_G3_SDA
TRUE
I1141
TRUE
SMBUS_SMC_5_G3_SCL
I1143
TRUE
I1673
TRUE
SMC_BIL_BUTTON_L
SMC_LID_R
I1140
3 TPs
6
7
6 45 48 99
I1617
TRUE
DMI_S2N_N & lt; 1 & gt;
6 45 48 99
I1616
TRUE
DMI_S2N_P & lt; 1 & gt;
45 46 64
I1618
TRUE
FDI_DATA_N & lt; 1 & gt;
I1607
I1621
I1146
KBDLED_ANODE
SMC_KDBLED_PRESENT_L
TRUE
TRUE
TRUE
8
2 TPs
54
TRUE
FDI_INT
TRUE
FDI_DATA_N & lt; 7..4 & gt;
TRUE
FDI_DATA_P & lt; 7..4 & gt;
TRUE
7
GND
FDI_DATA_P & lt; 1 & gt;
TRUE
FDI_FSYNC & lt; 1..0 & gt;
TRUE
FDI_LSYNC & lt; 1..0 & gt;
I1619
7 TPs
6
16
16
TP_SMC_P24
DC_TEST_BH1_BG2
TRUE
DC_TEST_BH3_BJ2
TP_USB_HUB1_PRTPWR1
TRUE
TP_SMC_P41
TP_USB_HUB1_OCS1
TRUE
TP_SATA_E_D2RN
TP_SATA_E_D2RP
TP_SATA_E_R2D_CN
TP_SATA_E_R2D_CP
TP_SATA_F_D2RN
TP_SATA_F_D2RP
TP_SATA_F_R2D_CN
TP_SATA_F_R2D_CP
12
TRUE
TRUE
MAKE_BASE=TRUE
TP_SATA_B_R2D_CP
TP_SATA_D_D2RN
TP_SATA_D_D2RP
TP_SATA_D_R2D_CN
TP_SATA_D_R2D_CP
12
TP_USB_HUB2_OCS1
5
TRUE
TRUE
TRUE
TRUE
I1535
TRUE
I1534
TRUE
I1537
TRUE
I1539
TRUE
I1558
TRUE
I1540
NC_PCIE_CLK100M_PE7N
NC_PCIE_CLK100M_PE7P
TRUE
TRUE
I1541
TRUE
I1542
TRUE
I1543
TRUE
I1544
NC_PSOC_P1_3
NC_SATA_B_D2RN
NC_SATA_B_D2RP
NC_SATA_B_R2D_CN
TRUE
TRUE
TP_DC_TEST_A62
TP_DC_TEST_D65
12
TP_CLINK_CLK
TP_CLINK_DATA
TP_CLINK_RESET_L
12
TRUE
TRUE
I1525
TRUE
MEM_B_CLK_N & lt; 1..0 & gt;
MEM_B_CLK_P & lt; 1..0 & gt;
I1526
TRUE
MEM_B_CS_L & lt; 1..0 & gt;
MEM_B_ODT & lt; 1..0 & gt;
I1527
TRUE
MEM_B_SA & lt; 1..0 & gt;
I1528
TRUE
I1531
TRUE
I1532
TRUE
MEM_B_DQ & lt; 63..0 & gt;
MEM_B_DQS_N & lt; 7..0 & gt;
MEM_B_DQS_P & lt; 7..0 & gt;
11 28 94
77 79 100
I1546
TRUE
77 79 100
I1547
TRUE
I1746
TRUE
CPUIMVP_UGATE1
CPUIMVP_LGATE1G
CPUIMVP_LGATE2
I1749
TRUE
I1748
TRUE
CPUIMVP_UGATE1G
CPUIMVP_UGATE2
CPUIMVP_LGATE2G
CPUIMVP_LGATE3
I1750
TRUE
I1751
TRUE
I1752
TRUE
I1753
TRUE
I1754
TRUE
I1755
TRUE
I1756
TRUE
I1757
TRUE
I1759
TRUE
CPUIMVP_PH1_SNUB
CPUIMVP_PH2_SNUB
CPUIMVP_PH3_SNUB
CPUIMVP_PHASE1
CPUIMVP_PHASE1G
CPUIMVP_PHASE2
16
16
16
4
TP_PCIE_CLK100M_PEBN
TP_PCIE_CLK100M_PEBP
CPUIMVP_UGATE2G
CPUIMVP_UGATE3
DDRREG_TRIP
GFXIMVP_LGATE
TRUE
CPUIMVP_SKIP
TRUE
I1719
GFXIMVP_VBST_R
CPUIMVP_SLEW
CPUIMVP_TONA
TRUE
TRUE
I1760
I1720
I1762
TRUE
GPUFB_BOOT_RC
GPUFB_DRVH
TRUE
I1717
TRUE
I1718
TRUE
CPUIMVP_PHASE2G
CPUIMVP_PHASE3
I1721
TRUE
TRUE
I1761
TRUE
I1722
CPUIMVP_VSWG1
TRUE
TRUE
I1764
I1723
CPUIMVP_VSWG2
TRUE
TRUE
I1763
I1724
GPUFB_VBST
CPUVCCIOS0_BOOT_RC
TRUE
TRUE
I1765
I1725
P1V05_GPU_DRVL
CPUVCCIOS0_DRVH
TRUE
TRUE
I1767
I1726
P1V05_GPU_DRVH
CPUVCCIOS0_DRVL
TRUE
TRUE
I1766
I1727
CPUVCCIOS0_FB
I1768
TRUE
TRUE
I1770
P1V05_GPU_VBST
CPUVCCIOS0_LL
TRUE
TRUE
I1769
TRUE
P1V05_GPU_BOOT_RC
I1729
TRUE
CPUVCCIOS0_OCSET
TRUE
TRUE
CPUVCCIOS0_RTN
I1772
I1731
CPUVCCIOS0_VBST
I1771
TRUE
TRUE
TRUE
P3V3S5_CSP2_R
P3V3S5_DRVH
CPUIMVP_TONB
GPUFB_DRVL
GPUFB_LL
P1V05_GPU_LL
P1V8S0_FB
P1V8S0_SW
TRUE
DC_TEST_B3_C2
I1773
TRUE
TRUE
DDRREG_DRVH
I1775
I1735
TRUE
TRUE
DDRREG_DRVL
I1774
I1736
TRUE
P3V3S5_LL
TRUE
DDRREG_FB
I1776
I1733
TRUE
P3V3S5_SNUBR
P3V3S5_DRVL
I1737
TRUE
DDRREG_LL
I1777
P3V3S5_VBST
TRUE
TRUE
I1778
I1779
P5V5G3H_BOOST
P3V3S5_VFB2
TRUE
TRUE
I1805
I1785
P5V5G3H_SW
TRUE
I1806
TRUE
TRUE
P5VS3_CSP1_R
I1789
TRUE
P5VS3_DRVH
P5VS3_DRVL
TRUE
TRUE
I1807
I1788
DMI_S2N_P & lt; 3 & gt;
P5VS3_LL
TRUE
TRUE
I1809
I1784
DMI_S2N_N & lt; 1..0 & gt;
P5VS3_SNUBR
TRUE
TRUE
I1808
I1782
TRUE
DMI_S2N_P & lt; 1..0 & gt;
P3V42G3H_SW
P3V3S5_TG
DMI_S2N_N & lt; 3 & gt;
TRUE
P5VS3_TG
I1810
I1812
DMI_N2S_N & lt; 3..1 & gt;
P5VS3_VBST
TRUE
TRUE
TRUE
DMI_N2S_P & lt; 3..1 & gt;
TRUE
P5VS3_VFB1
I1811
I1780
I1790
TRUE
11 29 94
I1793
TRUE
11 29 94
I1792
TRUE
PCHVCCIOS0_DRVL
11 29 94
I1794
TRUE
PCHVCCIOS0_FB
TRUE
PCHVCCIOS0_LL
I1548
TRUE
77 79 100
I1549
TRUE
77 79 100
I1550
TRUE
77 79 100
I1551
TRUE
77 79 100
I1559
TRUE
I1552
TRUE
77 79 100
77 79 100
TRUE
I1560
TRUE
FB_A1_DBI_L & lt; 3..0 & gt;
I1554
TRUE
77 79 100
I1553
TRUE
77 79 100
FB_A1_ABI_L
FB_A1_EDC & lt; 3..0 & gt;
FB_A1_WCLK_N & lt; 1..0 & gt;
FB_A1_WCLK_P & lt; 1..0 & gt;
I1555
TRUE
I1557
TRUE
11 29 94
I1795
29
I1796
TRUE
11 28 94
I1797
TRUE
I1798
TRUE
PPVCORE_S0_CPU_PH1_L
I1800
TRUE
PPVCORE_S0_CPU_PH2_L
I1799
TRUE
PPVCORE_S0_CPU_PH3_L
I1801
TRUE
VCCSAS0_B00T_RC
I1803
TRUE
VCCSAS0_DRVL
I1802
TRUE
VCCSAS0_LL
I1804
TRUE
VCCSAS0_VBST
11 28 94
11 28 94
FB_B1_DQ & lt; 31..0 & gt;
FB_B1_A & lt; 8..0 & gt;
77 79 100
I1556
TRUE
77 79 100
I1561
TRUE
FB_B1_DBI_L & lt; 3..0 & gt;
I1436
TRUE
I1437
TRUE
I1438
TRUE
I1439
TRUE
I1440
TRUE
77 80 100
77 80 100
77 80 100
77 80 100
TRUE
I1813
TRUE
USB3_EXTA_RX_N
I1823
77 80 100
TRUE
I1814
TRUE
USB3_EXTA_RX_P
USB3_EXTA_RX_F_N
I1825
77 80 100
I1824
TRUE
USB3_EXTA_RX_F_P
USB3_EXTA_TX_N
USB3_EXTA_TX_C_N
USB3_EXTA_TX_F_N
I1826
TRUE
I1827
TRUE
I1828
TRUE
I1830
TRUE
USB3_EXTA_TX_P
USB3_EXTA_TX_C_P
USB3_EXTA_TX_F_P
I1829
TRUE
I1831
TRUE
I1832
TRUE
77 80 100
I1815
TRUE
77 80 100
I1816
TRUE
77 80 100
I1818
TRUE
I1817
TRUE
77 80 100
77 80 100
I1819
TRUE
77 80 100
I1820
TRUE
I1441
TRUE
I1442
TRUE
I1443
TRUE
11 27 94
11 27 94
11 27 94
11 27 94
MEM_B_A & lt; 15..0 & gt;
MEM_B_CAS_L
MEM_B_RAS_L
MEM_B_WE_L
11 29 94
11 29 94
11 29 94
11 29 94
SYNC_MASTER=K18_MLB
SYNC_DATE=04/27/2010
PAGE TITLE
Functional / ICT Test
16
Apple Inc.
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
3
NC_CLINK_CLK
NC_CLINK_DATA
NC_CLINK_RESET_L
NC_PCIE_CLK100M_PEBN
NC_PCIE_CLK100M_PEBP
051-9585
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
2
3.0.0
BRANCH
PAGE
7 OF 132
SHEET
6 OF 105
1
PCHVCCIOS0_VBST
77 80 100
SIZE
D
A
TRUE
I1822
MEM_A_A & lt; 15..0 & gt;
MEM_A_CAS_L
MEM_A_RAS_L
MEM_A_WE_L
PCHVCCIOS0_OCSET
77 80 100
DRAWING NUMBER
TP_LPC_DREQ0_L
B
I1821
NC_SATA_D_R2D_CP
NC_SATA_E_D2RN
NC_SATA_E_D2RP
NC_SATA_E_R2D_CN
NC_SATA_E_R2D_CP
NC_SATA_F_D2RN
NC_SATA_F_D2RP
NC_SATA_F_R2D_CN
NC_SATA_F_R2D_CP
PCHVCCIOS0_DRVH
11 29 94
FB_B1_ABI_L
FB_B1_EDC & lt; 3..0 & gt;
FB_B1_WCLK_N & lt; 1..0 & gt;
FB_B1_WCLK_P & lt; 1..0 & gt;
77 79 100
PCHVCCIOS0_BOOT_RC
11 29 94
FB_B0_DQ & lt; 31..0 & gt;
FB_B0_A & lt; 8..0 & gt;
FB_B0_ABI_L
FB_B0_EDC & lt; 3..0 & gt;
FB_B0_WCLK_N & lt; 1..0 & gt;
FB_B0_WCLK_P & lt; 1..0 & gt;
FB_B0_DBI_L & lt; 3..0 & gt;
PCH ALIASES
TP_USB_HUB2_PRTPWR1
TRUE
TRUE
I1521
77 79 100
I1545
NC_SATA_B_R2D_CP
NC_SATA_D_D2RN
NC_SATA_D_D2RP
NC_SATA_D_R2D_CN
I1522
MEM_B_BA & lt; 2..0 & gt;
MEM_B_CKE & lt; 1..0 & gt;
11 28 94
FB_A1_DQ & lt; 31..0 & gt;
FB_A1_A & lt; 8..0 & gt;
MAKE_BASE=TRUE
16
TRUE
I1732
11 28 94
FB_A0_DQ & lt; 31..0 & gt;
FB_A0_A & lt; 8..0 & gt;
FB_A0_ABI_L
FB_A0_EDC & lt; 3..0 & gt;
FB_A0_WCLK_N & lt; 1..0 & gt;
FB_A0_WCLK_P & lt; 1..0 & gt;
FB_A0_DBI_L & lt; 3..0 & gt;
NC_SMC_P41
NC_LPC_DREQ0_L
16
TRUE
I1738
I1758
TRUE
I1715
C
11 27 94
MEM_A_DQ & lt; 63..0 & gt;
MEM_A_DQS_N & lt; 7..0 & gt;
MEM_A_DQS_P & lt; 7..0 & gt;
I1533
TRUE
11 27 94
MEM_A_SA & lt; 1..0 & gt;
TRUE
I1536
NC_PCIE_CLK100M_PE4N
NC_PCIE_CLK100M_PE4P
NC_PCIE_CLK100M_PE5N
NC_PCIE_CLK100M_PE5P
NC_PCIE_CLK100M_PE6N
NC_PCIE_CLK100M_PE6P
9 17 93
TRUE
I1620
I1622
6 64
54
GND
16
TP_PSOC_P1_3
TP_SATA_B_D2RN
TP_SATA_B_D2RP
TP_SATA_B_R2D_CN
TRUE
I1739
I1730
27
TRUE
I1530
NC_PCI_PME_L
NC_PCI_CLK33M_OUT3
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
9 17 93
I1835
I1145
93
6 9 I1623
17
9
I1625
17
93
I1626
93
17
9
I1627
93
9
I1629
17
9 17 93
I1834
J5815 (KBD BACKLIGHT CONN)
TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
I1523
11 27 94
MEM_A_CS_L & lt; 1..0 & gt;
MEM_A_ODT & lt; 1..0 & gt;
I1524
TRUE
11 27 94
MEM_A_CLK_N & lt; 1..0 & gt;
MEM_A_CLK_P & lt; 1..0 & gt;
I1520
20
TP_PCIE_CLK100M_PE4N
TP_PCIE_CLK100M_PE4P
TP_PCIE_CLK100M_PE5N
TP_PCIE_CLK100M_PE5P
TP_PCIE_CLK100M_PE6N
TP_PCIE_CLK100M_PE6P
TP_PCIE_CLK100M_PE7N
TP_PCIE_CLK100M_PE7P
I1745
CPUIMVP_BOOT2
CPUIMVP_BOOT2_RC
CPUIMVP_BOOT2G
CPUIMVP_BOOT2G_RC
CPUIMVP_BOOT3
CPUIMVP_BOOT3_RC
I1734
11 27 94
I1519
6 69 70
TP_1V05_S0_PCH_VCCAPLLEXP
TP_PCI_PME_L
TP_PCI_CLK33M_OUT3
TRUE
I1728
11 27 94
I1529
87 98
TRUE
MEM_A_BA & lt; 2..0 & gt;
MEM_A_CKE & lt; 1..0 & gt;
I1518
6 69 70
CPUIMVP_UGATE2
TRUE
87 98
I1577
I637
53 54
53 54
CPUIMVP_BOOT2
TRUE
I1645
53 54
53 54
TRUE
6 69 70
I1643
I1576
7
CPUIMVP_BOOT1
I1644
I1594
TRUE
89
I1517
16
I1689
TP_GMUX_PL6B
I1516
6 33
TRUE
TRUE
I1515
6 33
I1135
23
I1641
TRUE
23
TP_XDPPCH_HOOK3
TRUE
I1514
TP_XDPPCH_HOOK2
TRUE
TRUE
TRUE
I1744
I1781
I1513
TRUE
I1642
TRUE
I1742
GFXIMVP_LL_RC
GFXIMVP_PHASE
GFXIMVP_PHASE_L
GFXIMVP_UGATE
GFXIMVP_UGATE_R
GFXIMVP_VBST
TRUE
I1716
90
6 33
PP3V42_G3H
TRUE
I1714
TP_SPI_DESCRIPTOR_OVERRIDE_L
I1638
TP_TBT_PCIE_RESET2_L
I1136
TP_BKL_FAULT
TRUE
33 98
PP5V_S0
TRUE
I1712
NC_LVDS_EG_BKL_PWM
TRUE
MAKE_BASE=TRUE
NC_LVDS_IG_B_CLKN
TRUE
MAKE_BASE=TRUE
NC_LVDS_IG_B_CLKP
TRUE
MAKE_BASE=TRUE NC_LVDS_IG_BKL_PWM
TRUE
MAKE_BASE=TRUE
TP_AUD_LO1_L_P
TRUE
I1637
33 98
TRUE
TRUE
I1713
CPUIMVP_BOOT1_RC
CPUIMVP_BOOT1G
CPUIMVP_BOOT1G_R
CPUIMVP_LGATE1
I1743
I1783
TRUE
I1635
TP_TBT_PCIE_RESET1_L
I1669
8
TP_DP_TBTSRC_AUXCH_CN
TRUE
TRUE
33 98
TRUE
8 TPs
8
DP_TBTSNK1_ML_N & lt; 3..0 & gt;
TRUE
TRUE
CPUIMVP_AXG1_SNUB
CPUIMVP_AXG2_SNUB
CPUIMVP_BOOT1
33 98
TRUE
41 95
8
TP_AUD_LO1_L_N
DP_TBTSNK1_ML_P & lt; 3..0 & gt;
I626
53 54
TRUE
I1711
NC_GPU_BUFRST_L
TRUE
MAKE_BASE=TRUE
NC_GPU_GSTATE & lt; 0 & gt;
TRUE
MAKE_BASE=TRUE
NC_GPU_GSTATE & lt; 1 & gt;
TRUE
MAKE_BASE=TRUE
NC_GPU_MIOA_D & lt; 9..0 & gt;
TRUE
MAKE_BASE=TRUE
NC_GPU_MIOA_DE
TRUE
MAKE_BASE=TRUE
TP_LVDS_EG_BKL_PWM
TP_LVDS_IG_B_CLKN
TP_LVDS_IG_B_CLKP
TP_LVDS_IG_BKL_PWM
TRUE
I627
53 54
TRUE
I1709
NC_SDVO_INTN
NC_SDVO_INTP
TRUE
I614
53 54
TRUE
I1710
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
PP3V3_S5_AVREF_SMC
53 54
TRUE
I1708
TP_SDVO_INTN
TP_SDVO_INTP
I1572
PP3V3_S3
PP3V3_S5
TRUE
I1706
NC_SDVO_STALLN
NC_SDVO_STALLP
33 81 98
I1587
41 95
TP_AUD_GPIO_1
TRUE
I1636
I1704
I1707
40
TRUE
I1705
D
40
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
I1571
TRUE
I1703
40
TP_SDVO_STALLN
TP_SDVO_STALLP
7 101
TRUE
I616
TRUE
NC_SDVO_TVCLKINN
NC_SDVO_TVCLKINP
7
I615
TRUE
I1701
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
I1570
54
53 54
I1702
CHGR_LGATE
CHGR_PHASE
CHGR_UGATE
CHGR_VCOMP
CPU_VCCSASENSE_DIV
I1786
TRUE
33 81 98
I1565
7
TRUE
CHGR_BOOT
CHGR_ICOMP_RC
I1787
TRUE
33 81 98
7
TP_AUD_GPIO_2
TRUE
I1700
TP_SDVO_TVCLKINN
TP_SDVO_TVCLKINP
TP_GPU_MIOA_D & lt; 9..0 & gt;
TP_GPU_MIOA_DE
I1633
I1585
I1134
TP_TBT_MONOBSP
TP_TBT_MONOBSN
TP_DP_TBTSRC_ML_CP & lt; 0..3 & gt;
TP_DP_TBTSRC_ML_CN & lt; 0..3 & gt;
TRUE
I1698
NC_DP_IG_D_HPD
TRUE
MAKE_BASE=TRUE
NC_DP_IG_D_CTRL_CLK
TRUE
MAKE_BASE=TRUE
NC_DP_IG_D_CTRL_DATA
TRUE
MAKE_BASE=TRUE
NC_DP_IG_D_MLP & lt; 3..0 & gt;
TRUE
MAKE_BASE=TRUE
NC_DP_IG_D_MLN & lt; 3..0 & gt;
TRUE
MAKE_BASE=TRUE
NC_DP_IG_D_AUXP
TRUE
MAKE_BASE=TRUE
NC_DP_IG_D_AUXN
TRUE
MAKE_BASE=TRUE
TP_GPU_BUFRST_L
TP_GPU_GSTATE & lt; 0 & gt;
TP_GPU_GSTATE & lt; 1 & gt;
NC_TBT_MONDC0
TRUE
MAKE_BASE=TRUE
NC_TBT_MONDC1
TRUE
MAKE_BASE=TRUE
NC_TBT_MONOBSP
TRUE
MAKE_BASE=TRUE
NC_TBT_MONOBSN
TRUE
MAKE_BASE=TRUE
NC_DP_TBTSRC_ML_CP & lt; 0..3 & gt;
TRUE
MAKE_BASE=TRUE
NC_DP_TBTSRC_ML_CN & lt; 0..3 & gt;
TRUE
MAKE_BASE=TRUE
I1634
I1584
41 95
17
17
I1632
7
TRUE
4 TPs
41 95
6 33
17
33 98
41 95
I1131
17
33 98
41 45
7 TPs
17
6 33
33 81 98
TRUE
41 95
TP_TBT_MONDC0
TP_TBT_MONDC1
17
I1699
40
NC_DP_IG_C_HPD
TRUE
MAKE_BASE=TRUE
NC_DP_IG_C_CTRL_CLK
TRUE
MAKE_BASE=TRUE
NC_DP_IG_C_CTRL_DATA
TRUE
MAKE_BASE=TRUE
NC_DP_IG_C_MLP & lt; 3..0 & gt;
TRUE
MAKE_BASE=TRUE
NC_DP_IG_C_MLN & lt; 3..0 & gt;
TRUE
MAKE_BASE=TRUE
NC_DP_IG_C_AUXP
TRUE
MAKE_BASE=TRUE
NC_DP_IG_C_AUXN
TRUE
MAKE_BASE=TRUE
TP_DP_IG_D_AUXN
NO_TEST
DP_TBTSNK1_AUXCH_C_P
DP_TBTSNK1_AUXCH_C_N
DP_TBTSNK1_AUXCH_P
DP_TBTSNK1_AUXCH_N
53 54
2 TPs needed
41
17
17
40
NC_FW643_AVREG
TRUE
MAKE_BASE=TRUE
NC_FW643_TDI
TRUE
MAKE_BASE=TRUE
TP_DP_IG_D_CTRL_DATA
TP_DP_IG_D_MLP & lt; 3..0 & gt;
TP_DP_IG_D_MLN & lt; 3..0 & gt;
TP_DP_IG_D_AUXP
33 81 98
7
PP3V3_ENET
PP3V3_FW_FWPHY
PP3V3_S0
53 54
33
33
33 81 98
7
PP1V8_S0
I620
53 54
PSOC_MISO
PSOC_MOSI
PSOC_SCLK
SMBUS_SMC_2_S3_SCL
SMBUS_SMC_2_S3_SDA
TRUE
TP_FW643_AVREG
TP_FW643_TDI
TP_DP_IG_D_CTRL_CLK
17
TRUE
NC_ALS_GAIN
TP_DP_IG_D_HPD
17
NC_HDA_SDIN2
NC_HDA_SDIN3
TP_DP_TBTSRC_AUXCH_CP
TRUE
MAKE_BASE=TRUE
TP_DP_TBTSRC_AUXCH_CN
TRUE
MAKE_BASE=TRUE
NC_TBT_PCIE_RESET0_L
TRUE
MAKE_BASE=TRUE
NC_TBT_PCIE_RESET1_L
TRUE
MAKE_BASE=TRUE
NC_TBT_PCIE_RESET2_L
TRUE
MAKE_BASE=TRUE
NC_TBT_PCIE_RESET3_L
TRUE
MAKE_BASE=TRUE
TP_TBT_PCIE_RESET0_L
TP_TBT_PCIE_RESET1_L
TP_TBT_PCIE_RESET2_L
6 TP_TBT_PCIE_RESET3_L
TRUE
I1566
53 54
TBTDPA_ML_P & lt; 3..0 & gt;
TBTDPA_ML_N & lt; 3..0 & gt;
DP_TBTSNK0_AUXCH_C_P
TP_DP_TBTSRC_AUXCH_CP
TP_DP_TBTSRC_AUXCH_CN
7
PP1V5_S3
6 7
Z2_RESET
PSOC_F_CS_L
PICKB_L
TRUE
85 90
85 90
TRUE
TP_DP_IG_C_AUXN
NC_HDA_SDIN1
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TP_HDA_SDIN2
TP_HDA_SDIN3
I1489
17 26 45
74
7
54
Z2_SCLK
Z2_CLKIN
Z2_KEY_ACT_L
TRUE
TP_HDA_SDIN1
7
PM_SLP_S3_L
PP0V75_S0_DDRVTT
PP1V05_S0
PP1V05_S0GPU
PP1V0_FW_FWPHY
PP1V2_ENET
PP1V2_S0
54
Z2_MOSI
Z2_CS_L
Z2_DEBUG3
Z2_MISO
Z2_BOOST_EN
TRUE
GND
I1031
TRUE
I1486
POWER RAILS
6 64
PP18V5_Z2
PP3V3_S4
PP5V_S5_CUMULUS
Z2_HOST_INTN
TRUE
I1660
TRUE
I1032
32 95
I605
I1132
PP5V_S0_HDD_FLT
SATA_HDD_R2D_P
SATA_HDD_R2D_N
SATA_HDD_D2R_C_N
SATA_HDD_D2R_C_P
TRUE
33
I604
J4501 (SATA HDD CONN)
TRUE
NO_TEST=TRUE
GND
32
J5800 (IPD FLEX CONN)
I1659
TRUE
17
NC_LVDS_IG_CTRL_CLK
TRUE
MAKE_BASE=TRUE
NC_LVDS_IG_CTRL_DATA
TRUE
MAKE_BASE=TRUE
NC_PCH_LVDS_VBG
TRUE
MAKE_BASE=TRUE
6 41 44
I1151
6 41
SMC_LID_R
IR_RX_OUT
85 86 100
85 86 100
TP_PCH_LVDS_VBG
53
I1150
85 86 100
85 86 100
17
NC_CRT_IG_HSYNC
NC_CRT_IG_VSYNC
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TP_LVDS_IG_CTRL_CLK
TP_LVDS_IG_CTRL_DATA
17
GND
TRUE
85 86 100
85 100
TP_CRT_IG_HSYNC
TP_CRT_IG_VSYNC
47
I1288
32 95
SYS_DETECT_L
17
NC_CRT_IG_DDC_CLK
TRUE
MAKE_BASE=TRUE
NC_CRT_IG_DDC_DATA
TRUE
MAKE_BASE=TRUE
TRUE
TP_DP_IG_C_HPD
TP_DP_IG_C_CTRL_CLK
TP_DP_IG_C_CTRL_DATA
TP_DP_IG_C_MLP & lt; 3..0 & gt;
TP_DP_IG_C_MLN & lt; 3..0 & gt;
TP_DP_IG_C_AUXP
J6950 (BIL CABLE CONN)
6 45 48 99
J6950 (BAT CONN)
TRUE
TP_CRT_IG_DDC_CLK
TP_CRT_IG_DDC_DATA
TRUE
17
I1292
FUNC_TEST
I1510
8 TPs
17
17
53
85 86
85 90
17
47
32
85 86
85 86 100
17
19 47 56
53
I1488
85 86 100
45 46 47
33 6
I1665
85 100
17
46 47
TRUE
I1697
NC_FW0_TPBP
NC_FW0_TPBN
NC_FW0_TPAP
NC_ESTARLDO_EN
17
TRUE
6 TPs
32 46
3 TP needed
85 86 100
17
45 46 47
38
TRUE
I774
NC_CRT_IG_BLUE
NC_CRT_IG_GREEN
NC_CRT_IG_RED
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
I1696
40
I771
38
TP_CRT_IG_BLUE
TP_CRT_IG_GREEN
TP_CRT_IG_RED
17
I1130
6 7 101
8 85 104
45 46 47
53
WS_KBD23
WS_KBD_ONOFF_L
NC NO_TESTs
17
TRUE
40
I772
NC_TP_CPU_RSVD_NCTF & lt; 8..5 & gt;
TRUE
MAKE_BASE=TRUE
NO_TEST
45 46 47
TRUE
TRUE
I1695
40
I770
45 46 47
TRUE
SMC_TCK
SMC_TDI
I740
TRUE
TRUE
I1694
NC_FW2_TPBIAS
NC_FW2_TPAP
NC_FW2_TPAN
I768
TRUE
MAKE_BASE=TRUE
TP_CPU_RSVD_NCTF & lt; 8..5 & gt;
TRUE
I769
NC_TP_CPU_RSVD & lt; 2..1 & gt;
45 46 47 65
53
WS_LEFT_OPTION_KBD
WS_CONTROL_KBD
10 TPs
I1664
TRUE
I1026
45 46 53
SMC_RESET_L
I1483
TRUE
I1024
SMC_ONOFF_L
TRUE
I1481
I1101
J4500 (SATA ODD CONN)
PP5V_SW_ODD
SMC_ODD_DETECT
TRUE
SATA_ODD_D2R_C_P
TRUE
SATA_ODD_D2R_C_N
TRUE
SATA_ODD_R2D_P
TRUE
SATA_ODD_R2D_N
TRUE
GND
TRUE
TRUE
53
TRUE
GND
TRUE
TRUE
I737
4 TPs
85
TP_CPU_RSVD & lt; 2..1 & gt;
TRUE
I766
NC_TP_CPU_RSVD & lt; 24..15 & gt;
TRUE
MAKE_BASE=TRUE
17 45 47
PM_SYSRST_L
I1668
J9000 (LVDS CONN)
TRUE
TP_CPU_RSVD & lt; 24..15 & gt;
TRUE
I1693
NC_SMC_FAN_3_CTL
NC_SMC_FAN_2_TACH
NC_SMC_FAN_2_CTL
NC_FW2_TPBP
NC_FW2_TPBN
I767
NC_TP_CPU_RSVD & lt; 27..26 & gt;
TRUE
MAKE_BASE=TRUE
TRUE
I765
NC_TP_CPU_RSVD & lt; 43..32 & gt;
TRUE
MAKE_BASE=TRUE
TP_CPU_RSVD & lt; 27..26 & gt;
16 45 47
53
WS_LEFT_SHIFT_KBD
32 95
PP3V3_S3RS4_BT_F
TP_CPU_RSVD & lt; 43..32 & gt;
17 45 47
TRUE
I764
NC_TP_CPU_RSVD & lt; 58..45 & gt;
TRUE
MAKE_BASE=TRUE
TRUE
I763
NC_TP_CPU_RSVD & lt; 65..62 & gt;
TRUE
MAKE_BASE=TRUE
TP_CPU_RSVD & lt; 58..45 & gt;
16 45 47 89 96
LPC_SERIRQ
53
TRUE
32 95
TRUE
TP_CPU_RSVD & lt; 65..62 & gt;
16 45 47 89 96
24 47 96
TRUE
I762
24 47
TRUE
53
I1297
NO_TEST
19 47
I732
53
TRUE
61 62 101
GND
TRUE
TRUE
NC NO_TESTs
NC_SMC_FAN_3_TACH
I761
53
I1129
GND
TRUE
TRUE
I729
NO_TEST
CPU NO_TESTs
53
I1128
32
USB_CAMERA_CONN_P
USB_CAMERA_CONN_N
TRUE
I727
LPCPLUS_GPIO
LPCPLUS_RESET_L
LPC_AD & lt; 0..3 & gt;
LPC_CLK33M_LPCPLUS
LPC_FRAME_L
53
I1152
61 62 101
I726
53
61 62 101
61 62 101
LCD_BKLT_PWM
TRUE
53
32 45 46
PP3V3_WLAN
PP5V_S3_ALSCAMERA_F
SMBUS_SMC_2_S3_SDA
SMBUS_SMC_2_S3_SCL
TRUE
I725
53
17 24 32
I1663
B
32 96
I723
53
WS_KBD17
WS_KBD18
WS_KBD19
WS_KBD20
WS_KBD21
WS_KBD22
TRUE
62 63 101
I1054
I559
TRUE
62 63
BI_MIC_N
BI_MIC_SHIELD
BI_MIC_P
TRUE
I558
89 90
53
1
NO_TEST=TRUE
8
WS_KBD15_CAP
WS_KBD16_NUM
TRUE
I1119
J6780 (MIC CONN)
ISSP_SDATA_P1_0
2
ICT Test Points
WS_KBD13
WS_KBD14
TRUE
I1118
GND
TRUE
TRUE
53
WS_KBD9
WS_KBD10
WS_KBD11
WS_KBD12
TRUE
I724
3
8
53
WS_KBD6
WS_KBD7
WS_KBD8
TRUE
I1113
J5660 (RIGHT FAN CONN)
6 7
6 7
WS_KBD1
WS_KBD2
WS_KBD3
WS_KBD4
WS_KBD5
6 7
TRUE
4
FUNC_TEST
BKLT_EN
TRUE
I720
ISSP_SCLK_P1_1
TRUE
I722
TRUE
USB3_EXTB_RX_N
USB3_EXTB_RX_P
USB3_EXTB_RX_F_N
USB3_EXTB_RX_F_P
USB3_EXTB_TX_N
USB3_EXTB_TX_C_N
USB3_EXTB_TX_F_N
USB3_EXTB_TX_P
USB3_EXTB_TX_C_P
USB3_EXTB_TX_F_P
8
=PPBUS_G3H
65 64
7
6
PPBUS_G3H
G3H Rails
6
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
67
=PPBUS_S0_LCDBKLT
=PPBUS_S5_FWPWRSW
=PPVIN_S5_HS_OTHER_ISNS_R
39
=PPVIN_S5_HS_COMPUTING_ISNS_R
=PPVIN_S5_HS_COMPUTING_ISNS
50
MIN_NECK_WIDTH=0.25 mm
50
49
MAKE_BASE=TRUE
=PPVIN_S0_CPUIMVP
68
=PPVIN_S0_CPUVCCIOS0
71
=PPVIN_S0_CPUAXG
70
=PPVIN_S0_VCCSAS0
D
69 70
=PPVIN_S3_DDRREG
66
=PP1V8_S0_REG
72
73
24
85
17
=PP1V8_S0_CPU_VCCPLL_R
14 12
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
92
19
=PPDDR_S3_REG
68
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
=PP3V3_S5_XDP
=PP1V5_S3_ISNS
23
=PP3V3_S5_P3V3SUSFET
VOLTAGE=12.8V
MAKE_BASE=TRUE
73
=PP3V3_S5_PWRCTL
=PPVIN_S0GPU_P1V5
=PPVIN_S0_GFXIMVP
=PPVIN_S0GPU_P1V05
50
=PPVIN_S5_HS_OTHER_ISNS
78
78
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
64
=PP18V5_DCIN_CONN
64
=PP3V42_G3H_REG
VOLTAGE=12.8V
MAKE_BASE=TRUE
=PPVIN_S5_P5VP3V3
PPDCIN_G3H
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
For PCH RTC Power
=PPVRTC_G3_OUT
24
5V Rails
=PP5V_S5_LDO
6
=PP3V3_S5_LPCPLUS
=PP3V3_S5_SMC
=PP3V42_G3H_BIL
=PP3V42_G3H_CHGR
=PP3V42_G3H_ONEWIREPROT
=PP3V42_G3H_PWRCTL
=PP3V42_G3H_SMBUS_SMC_5
=PP3V42_G3H_SMCUSBMUX
=PP3V42_G3H_TPAD
=PPVIN_S5_SMCVREF
=PPVBAT_G3_SYSCLK
=PP3V42_G3H_AUDIO
47
45 46 82
64
65 74
64
74
48
42
53
46
24
59
PPVRTC_G3H
73
16 17 20
VOLTAGE=5V
MAKE_BASE=TRUE
73
73
54
PP5V_SUS
VOLTAGE=5V
MAKE_BASE=TRUE
22
6
VOLTAGE=5V
MAKE_BASE=TRUE
=PP5V_S3_ALSCAMERA
=PP5V_S3_DDRREG
32
68
=PP5V_S5_DEBUG_ADC_AVDD
=PP5V_S5_DEBUG_ADC_DVDD
=PP5V_S3_AUDIO
=PP5V_S3_IR
=PP5V_S3_MEMRESET
104
104
41 44
26
=PP5V_S3_ODD
=PP5V_S3_P5VS0FET
=PP5V_S3_USB
=PP5V_S3_SYSLED
41
73
42
46
=PP5V_S3_P5VS0SW
=PP5V_S3_P3V3S0SW
=PP5V_S3_GFXIMVP
73
=PP5V_S0_FET
103
=PP5V_S0_ISNS
3.3V Rails
A
73
30
32
=PP3V3_S4_FET
=PP3V3_S4_SD_HPD
=PP3V3_S4_BT
84
PP5V_S0
6
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=5V
MAKE_BASE=TRUE
=PP5V_S0_BKL
=PP5V_S0_CPUIMVP
=PP5V_S0_CPUVCCIOS0
=PP5V_S0_FAN_LT
=PP5V_S0_FAN_RT
=PP5V_S0_VCCSAS0
=PP5V_S0_VMON
=PP5V_S0_HDD
=PP5V_S0_KBDLED
=PP5V_S0_LPCPLUS
=PP5V_S0_PCH
=PP5V_S0GPU_P1V05
=PP5V_S0_AUDIO_XW
=PP5V_S0_RMC
=PP5V_S0GPU_P1V5
PP3V3_S4
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
=PP3V3_SUS_FET
69 70
71
52
52
66
74
41
54
78
8
105
78
6
MAKE_BASE=TRUE
VOLTAGE=3.3V
53 54
35
=PP3V3_TBT_FET
VOLTAGE=3.3V
=PP3V3_SUS_P1V05SUSLDO
=PP3V3_T29_PCH_GPIO
72
=PP3V3_SUS_PCH_VCCSUS
20 22
=PP3V3_SUS_PCH_VCCSUS_GPIO
20 22
=PP3V3_SUS_PCH_GPIO
16 17 18 19
=PP3V3_SUS_PCH_VCCSUS_USB
20 22
=PP3V3_SUS_CNTRL
=PP3V3_SUS_SMC
=PP3V3_SUS_ROM
=PP3V3_SUS_PCH_VCC_SPI
7
35
=PP1V05_TBT_FET
46
35 8
=PP15V_TBT_REG
6
26
27
29
68
31
103 78
PPGPUFB_S0
=PP1V5R1V35_GPU_REG
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.5V
MAKE_BASE=TRUE
=PP1V35_GPU_FBVDDQ
=PP1V35_GPU_S0_FB
77
20 22 24
=PP1V5_S0_VMON
76 79 80
57
=PP3V3R1V5_S0_PCH_VCCSUSHDA
41
74
78
68 31
=PPVTT_S3_DDR_BUF
PPVTTDDR_S3
=PP1V05_S0GPU_REG
PP1V05_S0GPU
MIN_LINE_WIDTH=0.9 MM
MIN_NECK_WIDTH=0.2 MM
6
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=0.75V
MAKE_BASE=TRUE
31
32
18 24
68
=PPVTT_S0_DDR_LDO
PP0V75_S0_DDRVTT
24
=PP0V75_S0_MEM_VTT_A
=PP0V75_S0_MEM_VTT_B
=PPVTT_S0_VTTCLAMP
6 101
VOLTAGE=3.3V
MAKE_BASE=TRUE
23
72
=PP1V2_S0_REG
77 83
26
84
=PPVCORE_S0_GFX_REG
6
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.2V
MAKE_BASE=TRUE
87
6
81
29
PP1V2_S0
90
81
27
36
57 62 63
81 83
PPVCORE_GPU
6
C
81
=PP1V05_GPU_IFPCD_IOVDD
=PP1V05_GPU_IFPEF_IOVDD
=PP1V05_GPU_PEX_IOVDD
=PP1V05_GPU_PEX_PLLVDD
MIN_LINE_WIDTH=2 mm
MIN_NECK_WIDTH=0.17 mm
VOLTAGE=0.75V
MAKE_BASE=TRUE
25
6
VOLTAGE=1.05V
MAKE_BASE=TRUE
=PP1V05_GPU_IFPAB_PLLVDD
7 49 103 104
VOLTAGE=1.0V
MAKE_BASE=TRUE
=PPVCORE_GPU
=PPVCORE_GPU_REG
=PP1V2_S0_GMUX
76 83
49
89
51
72
85
=PP1V05_SUS_LDO
PP1V05_SUS
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE
49 50 103 104
35
=PP1V05_SUS_PCH_JTAG
23
PP1V05_S0
86
6
52
52
71
=PPCPUVCCIO_S0_REG
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
39
VOLTAGE=1.05V
MAKE_BASE=TRUE
=PP1V05_S0_CPU_VCCIO
39 40
86 89
35
51
86
41
16 22
16 17 18 19 30
22
20 22
20 22
20 22
20 22
22
20
74 92
24
24 92
30
48
48
48
41
74
27
29
Chipset " VCore " Rails
9 10 12 13 14
=PPVCCIO_S0_XDP
=PPVCCIO_S0_CPUIMVP
=PPVCCIO_S0_SMC
=PP1V05_S0_RMC
=PP1V05_S0_FWPWRCTL
=PP1V05_FW_P1V0FWFET
=PP1V05_S0_VMON
=PP1V05_S0_P1V05TBTFET
=PP1V05_S0_PCH_VCCIO_PLLPCIE
=PP1V05_S0_PCH_VCCADPLL
=PP1V05_S0_PCH_VCCIO
=PP1V05_S0_PCH_VCCIO_PCIE
=PP1V05_S0_PCH_VCCIO_SATA
=PP1V05_S0_PCH_VCCIO_CLK
=PP1V05_S0_PCH_VCCIO_USB
=PP1V05_S0_PCH_VCC_CORE
=PP1V05_S0_PCH_VCCASW
=PP1V05_S0_PCH_VCCIO_CLK
=PP1V05_S0_PCH_VCCDIFFCLK
=PP1V05_S0_PCH
=PP1V05_S0_PCH_VCCSSC
=PP1V05_S0_PCH_V_PROC_IO
=PP1V05_S0_PCH_VCCIO_PLLUSB
=PP1V05_S0_PCH_VCC_DMI
=PP1V05_S0_PCH_VCCIO_PLLFDI
=PP1V05_S0_PCH_VCCDMI_FDI
12
54
23
70
PPVCORE_S0_CPU
73
6
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
MAKE_BASE=TRUE
VOLTAGE=1.25V
=PPVCORE_S0_CPU
46
105
70 49
=PPVCORE_S0_AXG_REG
12 14 49
105
PPVCORE_S0_AXG
39
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
39
B
MAKE_BASE=TRUE
VOLTAGE=1.05V
=PPVCORE_S0_CPU_VCCAXG
12 13 15
74
35
15 12
=PP1V5_S3_CPU_VCCDQ
PP1V5_S3_CPU_VCCDQ
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
20
22
14 12 8
=PP1V05_S0_CPU_VCCPQE
MAKE_BASE=TRUE
VOLTAGE=1.5V
PP1V05_S0_CPU_VCCPQE
20 22
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
17
66 49
VOLTAGE=1.05V
MAKE_BASE=TRUE
PPVCCSA_S0_REG
=PPVCCSA_S0_REG
16 20 22
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
7 20 22
VOLTAGE=0.9V
MAKE_BASE=TRUE
=PPVCCSA_S0_CPU
12 15
20 22
FireWire Rails
20 22
20 22
39
PPVP_FW
=PPBUS_FW_FET
7 20 22
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
6
VOLTAGE=12.8V
MAKE_BASE=TRUE
16 20 22
=PPVP_FW_PORT1
=PPVP_FW_PHY_CPS_FET
40
PP3V3_FW_FWPHY
16 22
6
20 22
40
20 22
39
=PP3V3_FW_FET
20
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
20 22
VOLTAGE=3.3V
MAKE_BASE=TRUE
=PP3V3_FW_FWPHY
38 39 40
20
20
39
=PPPCHVCCIO_S0_REG
=PPVCORE_S0_CPU_REG
69
PP1V0_FW_FWPHY
=PP1V0_FW_FET_R
91
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
41
Backlight Rails
6
VOLTAGE=1.0V
MAKE_BASE=TRUE
=PP1V0_FW_FWPHY
38 39
50
48
104 90
=PPBUS_SW_BKL
PPBUS_SW_BKL
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
=PPVDDIO_T29_CLK
=PP3V3_TBT_RTR
=PP3V3_T29_JTAG
PP1V05_TBT
=PP3V3_ENET_FET
ENET Rails
33 34 35
72
=PP1V2_S3_ENET_PHY
=PP1V05_TBT_RTR_R
PP15V_TBT
104
VOLTAGE=15V
MAKE_BASE=TRUE
5
104 34
PPVIN_SW_TBTBST
35
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
6
36
VOLTAGE=1.05V
MAKE_BASE=TRUE
3
051-9585
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
VOLTAGE=1.2V
MAKE_BASE=TRUE
VOLTAGE=12.8V
4
Apple Inc.
24
PP1V05_TBT_RTR
=PP1V05_TBT_RTR
I1658
88
DRAWING NUMBER
24 36 72
=PP1V2_ENET_PHY
TBT Rails
Power Aliases
24
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
35
VOLTAGE=1.05V
MAKE_BASE=TRUE
SYNC_DATE=08/29/2011
PAGE TITLE
6
VOLTAGE=3.3V
MAKE_BASE=TRUE
=PP3V3_ENET_PHY
=PPVDDIO_ENET_CLK
=PP3V3_ENET_SYSCLK
PP1V2_ENET
24
89
SYNC_MASTER=J31_MLB
MAKE_BASE=TRUE
VOLTAGE=12.8V
PP3V3_ENET
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.2 MM
MAKE_BASE=TRUE
16 19
=PPHV_SW_TBTAPWRSW
20 22
81
VOLTAGE=1.5V
MAKE_BASE=TRUE
55
25
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
56
=PP1V8_GPU_IFPAB_IOVDD
10 13 15 26
25
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
74
101
48
74
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.2 MM
D
PP1V8_S0GPU
VOLTAGE=1.5V
MAKE_BASE=TRUE
=PP1V5_S0_RDRVR
=PP1V5_S0_AUDIO
48
PP3V3_TBT
VOLTAGE=3.3V
86
75 81 82 83
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.15 MM
VOLTAGE=1.8V
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.5V
MAKE_BASE=TRUE
74
=PP3V3_S0_HDD
=PP3V3_S0_P1V8GPUFET
=PP3V3_S0_IMVPISNS
=PP3V3_S0_T29I2C
=PP3V3_S0_TBT_HPD_GPU
MIN_LINE_WIDTH=0.4 MM
MIN_LINE_WIDTH=0.6 MM
8
T29 Rails
46
PP3V3_SUS
=PP1V8_GPU_FET
73
PP1V5_S0
26
=PP3V3_S0_TPAD
=PP3V3_S0_VMON
=PPSPD_S0_MEM_A
=PPSPD_S0_MEM_B
47
22 24
=PP3V3_S4_TPAD
=PP3V3_S4_SMC
73
90
=PP1V5_S0_REG
72
89
=PP3V3_S3_USB_HUB
=PP3V3_S3_USB_RESET
=PP3V3_S3_VREFMRGN
=PP3V3_S3_WLAN
=PP3V3_S3_ISNS
=PP3V3_S3_PCH_GPIO
=PP3V3_S3_USBMUX
=PP3V3_S3_SDBUF
PP3V3_S0
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.075 mm
PP5V_S3
VOLTAGE=3.3V
MAKE_BASE=TRUE
=PP3V3_S0_XDP
=PP3V3_S0_ENETPHY
=PP3V3_S0_AUDIO
=PP3V3_S0_BKL_VDDIO
=PP3V3_S0_DPSDRVA
=PP3V3_S0_HS_ISNS
=PP3V3_S0_CPUTHMSNS
=PP3V3_S0_DDC_LCD
=PP3V3_S0_ISNS
=PP3V3_S0_TBTPWRCTL
=PP3V3_S0_DPMUX
=PP3V3_S0_FAN_LT
=PP3V3_S0_FAN_RT
=PP3V3_S0_FWPWRCTL
=PP3V3_S0_FWLATEVG
=PP3V3_S0_CPU_VCCIO_SEL
=PP3V3_S0_GMUX
=PP3V3_S0_P3V3TBTFET
=PP3V3_S0_GPUTHMSNS
=PP3V3_S0_LVDSDDCMUX
=PP3V3_S0_ODD
=PP3V3_S0_PCH
=PP3V3_S0_PCH_GPIO
=PP3V3_S0_PCH_VCC3_3_CLK
=PP3V3_S0_PCH_VCC3_3_GPIO
=PP3V3_S0_PCH_VCC3_3_HVCMOS
=PP3V3_S0_PCH_VCC3_3_PCI
=PP3V3_S0_PCH_VCC3_3_SATA
=PP3V3_S0_PCH_VCCADAC
=PP3V3_S0_PCH_VCCA_LVDS
=PP3V3_S0_PWRCTL
=PP3V3_S0_RSTBUF
=PP3V3_S0_SB_PM
=PP3V3_S0_SDCARD
=PP3V3_S0_SMBUS_PCH
=PP3V3_S0_SMBUS_SMC_0_S0
=PP3V3_S0_SMBUS_SMC_1_S0
=PP3V3_S0_SMC
PP5V_S5
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm
B
=PP3V3_S0_FET
VOLTAGE=3.42V
MAKE_BASE=TRUE
=PPVRTC_G3_PCH
=PP5V_SUS_PCH
=PP5V_S3_REG
6
=PP3V3_S3_BT
=PP3V3_S3_GMUX
=PP3V3_S3_MEMRESET
=PP3V3_S3_P3V3ENETFET
=PP3V3_S3_SMBUS_SMC_2_S3
=PP3V3_S3_SMBUS_SMC_3
=PP3V3_S3_SMS
49
73
49
=PP1V5_S3_MEMRESET
=PP1V5_S3_MEM_A
=PP1V5_S3_MEM_B
=PPVIN_S0_DDRREG_LDO
=PPDDR_S3_MEMVREF
104
PP3V3_S3
81
84
6
VOLTAGE=1.5V
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
65
VOLTAGE=3.42V
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
67
=PP3V3_S3_ISNS
=PP3V3_GPU_IFPX_PLLVDD
=PP3V3_GPU_LVDS_DDC
=PP3V3_S0_GFX3V3BIAS
=PP3V3_GPU_VDD33
=PP3V3_GPU_OSC
PP1V5_S3_DDR
=PP1V5_S3_DDR_ISNS
VOLTAGE=3.3V
MAKE_BASE=TRUE
=PP3V3_S3_ISNS_R
104 103 49 7
=PP5V_S5_P1V5S3RS0FET
=PP5V_S5_P5VSUSFET
=PP5V_S5_TPAD
=PP5V_S5_ISNS
=PP5V_SUS_FET
88
PP3V3_S3_FET
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
67
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
73
=PP3V3_S3_FET
20
=PP1V5_S3_CPU_VCCDDR
46
104
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.10MM
VOLTAGE=3.3V
MAKE_BASE=TRUE
103
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
6
=PPDCIN_S5_CHGR
=PPDCIN_S5_VSENSE
PP3V42_G3H
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
67
73
VOLTAGE=18.5V
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
C
=PP1V5_S3RS0_FET
73
=PP3V3_S0GPU_ISNS_R
PP3V3_S0GPU
=PP3V3_S0GPU_ISNS
24
=PP1V5_S3_DDR_ISNS_R
=PPVIN_S3_P1V5S3RS0_FET
PP1V5_S3RS0
72
49
PPVIN_S5_HS_OTHER_ISNS
104
14
VOLTAGE=1.5V
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.8 MM
MIN_NECK_WIDTH=0.1 MM
74
=PP3V3_S5_P1V5S0
=PP3V3_S5_SMCBATLOW
=PP3V3_S4_TBTAPWRSW
84
22
19 20 22
=PP1V5_S3_ISNS_R
PP1V5_S3
74
103
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.10MM
VOLTAGE=3.3V
MAKE_BASE=TRUE
PP1V5_S3_REG
26
20 22
PP3V3_S0GPU_FET
89
VOLTAGE=1.8V
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.8 MM
MIN_NECK_WIDTH=0.1 MM
=PP3V3_S5_VMON
=PP3V3_S0GPU_FET
73
=PPVDDIO_S0_SBCLK
PP1V8_S0_CPU_VCCPLL_R
72
" GPU " Rails
73
=PP1V8R1V5_S0_PCH_VCCVRM
39
=PP3V3_S5_PCH_VCCDSW
PPVIN_S5_HS_GPU_ISNS
1
6
VOLTAGE=1.5V
MAKE_BASE=TRUE
=PP1V8_S0_GMUX
=PP1V8_S0_GPUFET
=PP1V8_S0_PCH_VCCTX_LVDS
=PP1V8_S0_PCH_VCC_DFTERM
=PP1V8_S0_CPU_VCCPLL
73
=PPVIN_S0_PCHVCCIOS0
=PPVIN_S5_HS_GPU_ISNS
50
2
PP1V8_S0
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
2A max supply
73
=PP3V3_S4_P3V3S4FET
8 35
3
1.8V/1.5V/1.2V/1.05V Rails
73
=PP3V3_S5_SYSCLK
=PP3V3_S5_LCD
=PP3V3_FW_P3V3FWFET
=PP3V3_S5_P1V2P1V8
=PP3V3_S5_PCH
=PP3V3_S5_PCHPWRGD
=PP3V3_S5_PCH_GPIO
=PP3V3_S5_CPU_VCCDDR
=PP3V3_S5_MEMVDDSEL
50
VOLTAGE=12.8V
4
6 101
VOLTAGE=3.3V
MAKE_BASE=TRUE
=PP3V3_GPU_P3V3GPUFET
=PP3V3_S0_P3V3S0FET
=PP3V3_S3_P3V3S3FET
90
PPVIN_S5_HS_COMPUTING_ISNS
MIN_LINE_WIDTH=0.6 mm
5
PP3V3_S5
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
=PPVIN_S5_HS_GPU_ISNS_R
=PPVIN_SW_TBTBST
=PPBUS_S0_VSENSE
50
=PP3V3_S5_REG
VOLTAGE=12.8V
MAKE_BASE=TRUE
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
2
3.0.0
BRANCH
PAGE
8 OF 132
SHEET
7 OF 105
1
SIZE
D
A
8
7
6
Thermal Module Holes
ZT0984
5
STDOFF-4.5OD.98H-1.1-3.48-TH
ZT0981
1
ZT0987
ZT0988
STDOFF-4.5OD.98H-1.1-3.48-TH
JTAG_ISP_TDI
STDOFF-4.5OD.98H-1.1-3.48-TH
89 19
NC_USB_EXTD_EHCIP
MAKE_BASE=TRUE
JTAG_TBT_TDI
19 33
JTAG_TBT_TDO
33
ZT0980
STDOFF-4.5OD.98H-1.1-3.48-TH
ZT0986
ZT0989
STDOFF-4.5OD.98H-1.1-3.48-TH
STDOFF-4.5OD.98H-1.1-3.48-TH
T29_LSEO_LSOE3
TBT_LSOE & lt; 2 & gt;
MAKE_BASE=TRUE
Frame Holes
33
MAKE_BASE=TRUE
MAKE_BASE=TRUE
DPMUX_UC_IRQ
GND_BATT_CHGND
1
MAKE_BASE=TRUE
PM_ALL_GPU_PGOOD
92
ALL_EG_PGOOD
3R2P5
GND_CHASSIS_LVDS
MAKE_BASE=TRUE
ZT0950
LVDS_MUX_SEL_EG
Left Speaker Holes
GND_CHASSIS_FAN
1
GPU_RESET_L
75 82
17
LVDS_IG_PANEL_PWR
104 85 6
PPVOUT_S0_LCDBKLT
ZT0934
96 33
PCIE_TBT_D2R_N & lt; 3..0 & gt;
96 33
96 33
9
PCIE_TBT_R2D_C_N & lt; 3..0 & gt;
90
GND_CHASSIS_BATTCONN
EG_CLKREQ_IN_L
16
EG_CLKREQ_OUT_L
=PEG_R2D_C_N & lt; 11..8 & gt;
Tall EMI pogo pins
9
Unused eDP signals
93 75
MAKE_BASE=TRUE
SM
DP_INT_IG_ML_N & lt; 3..0 & gt;
DP_INT_IG_AUX_P
MAKE_BASE=TRUE
SH0935
TBT_D2R_N & lt; 3..2 & gt;
NC_DP_INT_IG_AUXN
DP_INT_IG_HPD
NC_DP_INT_IG_HPD
POGO-2.0OD-3.5H-K86-K87
SH0933 NOSTUFF
POGO-2.0OD-3.5H-K86-K87
98 33
TBT_R2D_C_P & lt; 3..2 & gt;
MAKE_BASE=TRUE
98 33
TBT_R2D_C_N & lt; 3..2 & gt;
NC_T29_R2D_CN & lt; 3..2 & gt;
MAKE_BASE=TRUE
1
FW_PLUG_DET_L
SH0900
39
POGO-2.0OD-3.5H-K86-K87
ZT0952
SM
1
NO_TEST=TRUE
MAKE_BASE=TRUE
19 39
FW643_WAKE_L
26
=FW_PME_L
MEMVTT_EN
MAKE_BASE=TRUE
26 68
MAKE_BASE=TRUE
38 39
1
MAKE_BASE=TRUE
1
USB3_EXTD_RX_P
18
USB3_EXTD_TX_N
18
USB3_EXTD_TX_P
18
NO_TEST=TRUE
NC_USB3_EXTD_TXP
MAKE_BASE=TRUE
18
NO_TEST=TRUE
NC_USB3_EXTD_TXN
=DDRVTT_EN
4.0OD1.85H-M1.6X0.35
TP_SMC_EXCARD_PWR_EN
USB3_EXTD_RX_N
NO_TEST=TRUE
NC_USB3_EXTD_RXP
CPU signals
FW_PME_L
C
NC_USB3_EXTD_RXN
NO_TEST=TRUE
MAKE_BASE=TRUE
Keyboard / IPD Conn Protect
18 95
NO_TEST=TRUE
MAKE_BASE=TRUE
SH0902
18 95
USB_EXTC_P
MAKE_BASE=TRUE
POGO-2.0OD-3.5H-K86-K87
SM
USB_EXTC_N
NO_TEST=TRUE
NC_USB_EXTCP
NC_T29_R2D_CP & lt; 3..2 & gt;
NO_TEST=TRUE
MAKE_BASE=TRUE
9
NC_USB_EXTCN
MAKE_BASE=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
SM
1
SM
NO_TEST=TRUE
NC_T29_D2RN & lt; 3..2 & gt;
MAKE_BASE=TRUE
DP_INT_IG_AUX_N
93 9
17
NO_TEST=TRUE
9
MAKE_BASE=TRUE
SH0931
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
98 33
NO_TEST=TRUE
MAKE_BASE=TRUE
NOSTUFF
17
LVDS_IG_B_DATA_N & lt; 3 & gt;
NO_TEST=TRUE
NC_LVDS_IG_B_DATAN & lt; 3 & gt;
9
98 33
NC_DP_INT_IG_AUXP
1
17 95
LVDS_IG_B_DATA_P & lt; 3 & gt;
NC_LVDS_IG_B_DATAP & lt; 3 & gt;
MAKE_BASE=TRUE
=PEG_R2D_C_N & lt; 7..0 & gt;
17 95
LVDS_IG_A_DATA_N & lt; 3 & gt;
NO_TEST=TRUE
Unused T29 Ports
TBT_D2R_P & lt; 3..2 & gt;
NC_T29_D2RP & lt; 3..2 & gt;
NC_DP_INT_IG_MLN & lt; 3..0 & gt;
93 9
1
SM
9
=PEG_R2D_C_P & lt; 7..0 & gt;
PEG_R2D_C_N & lt; 7..0 & gt;
NO_TEST=TRUE
93 9
POGO-2.0OD-3.5H-K86-K87
1
LVDS_IG_A_DATA_P & lt; 3 & gt;
NO_TEST=TRUE
NO_TEST=TRUE
NC_DP_INT_IG_MLP & lt; 3..0 & gt;
DP_INT_IG_ML_P & lt; 3..0 & gt;
93 9
9
=PEG_D2R_N & lt; 7..0 & gt;
PEG_R2D_C_P & lt; 7..0 & gt;
MAKE_BASE=TRUE
POGO-2.0OD-3.5H-K86-K87
SH0932
93 75
=PEG_D2R_P & lt; 7..0 & gt;
NO_TEST=TRUE
MAKE_BASE=TRUE
SH0934
NOSTUFF
POGO-2.0OD-3.5H-K86-K87
SM
NOSTUFF
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
=P1V2ENET_EN
17
GPU_XTALOUT
NC_LVDS_IG_A_DATAP & lt; 3 & gt;
MAKE_BASE=TRUE
PEG_D2R_N & lt; 7..0 & gt;
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NOSTUFF
1
LVDS_IG_BKL_PWM
NC_GPU_XTALOUT
MAKE_BASE=TRUE
PEG_D2R_P & lt; 7..0 & gt;
93 75
PM_ENET_EN
SM
89
MAKE_BASE=TRUE
17
MAKE_BASE=TRUE
9
NO_TEST=TRUE
93 75
PEG_CLKREQ_L
1
SH0930
82 89
MAKE_BASE=TRUE
STDOFF-4.0OD3.0H-TH
POGO-2.0OD-3.5H-K86-K87
TP_LVDS_IG_BKL_PWM
6
=PEG_R2D_C_P & lt; 11..8 & gt;
NO_TEST=TRUE
MAKE_BASE=TRUE
PEX_CLKREQ_L
17
LVDS_IG_B_CLK_N
NO_TEST=TRUE
MAKE_BASE=TRUE
PPVOUT_SW_LCDBKLT
LVDS_IG_B_CLK_P
NC_LVDS_IG_A_DATAN & lt; 3 & gt;
ZT0935
1
TP_LVDS_IG_B_CLKN
MAKE_BASE=TRUE
GPU signals
3R2P5
NO_TEST=TRUE
TP_LVDS_IG_B_CLKP
9
PCIE_TBT_R2D_C_P & lt; 3..0 & gt;
MAKE_BASE=TRUE
104
MAKE_BASE=TRUE
=PEG_D2R_N & lt; 11..8 & gt;
89
89
1
ZT0990
C
MAKE_BASE=TRUE
6
=PEG_D2R_P & lt; 11..8 & gt;
IG_BKLT_EN
MAKE_BASE=TRUE
GND_CHASSIS_SATA
1
9
NO_TEST=TRUE
IG_LCD_PWR_EN
MAKE_BASE=TRUE
STDOFF-4.0OD3.0H-TH
3R2P5
=PEG_R2D_C_N & lt; 15..12 & gt;
NO_TEST=TRUE
MAKE_BASE=TRUE
LVDS_IG_BKL_ON
17
D
104
ADC_CH7
NO_TEST=TRUE
NC_ADC_CH7
NO_TEST=TRUE
PCIE_TBT_D2R_P & lt; 3..0 & gt;
96 33
25
ADC_CH6
MAKE_BASE=TRUE
9
T29 Signals Through PEG
MAKE_BASE=TRUE
ZT0960
NC_ADC_CH6
9
=PEG_R2D_C_P & lt; 15..12 & gt;
89
MAKE_BASE=TRUE
SL-3.1X2.7-6CIR-NSP
=PEG_D2R_N & lt; 15..12 & gt;
NO_TEST=TRUE
EG_RESET_L
89
TH
25
USBHUB_DN4_P
USB_SMC_P
MAKE_BASE=TRUE
6
MAKE_BASE=TRUE
TP_LVDS_MUX_SEL_EG
1
USBHUB_DN4_N
MAKE_BASE=TRUE
95
9
NO_TEST=TRUE
NC_PEG_R2D_CN & lt; 15..12 & gt;
89
MAKE_BASE=TRUE
25
USB_SMC_N
NO_TEST=TRUE
NC_PEG_R2D_CP & lt; 15..12 & gt;
19
MAKE_BASE=TRUE
1
ZT0940
USB_IR_P
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PEG_D2RN & lt; 15..12 & gt;
GMUX_INT
89
25
USBHUB_DN2_P
MAKE_BASE=TRUE
95 44
Unused PEG signals
NC_PEG_D2RP & lt; 15..12 & gt;
=PEG_D2R_P & lt; 15..12 & gt;
GMUX ALIASES
ZT0991
STDOFF-4.5OD.98H-1.1-3.48-TH
3R2P5
TBT_LSEO & lt; 2 & gt;
25
USBHUB_DN2_N
USB_IR_N
95 44
18
95
MAKE_BASE=TRUE
NO_TEST=TRUE
25
USBHUB_DN3_P
MAKE_BASE=TRUE
18
USB3_EXTC_TX_P
USBHUB_DN3_N
USB_TPAD_P
95 53
33
NO_TEST=TRUE
T29_LSEO_LSOE2
1
1
USB_TPAD_N
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
TBT_LSEO & lt; 3 & gt;
18
USB3_EXTC_TX_N
25
MAKE_BASE=TRUE
95 53
NO_TEST=TRUE
NC_USB3_EXTC_TXP
TBT_LSOE & lt; 3 & gt;
33
1
33
USB3_EXTC_RX_P
NC_USB3_EXTC_TXN
MAKE_BASE=TRUE
MAKE_BASE=TRUE
18
18
NO_TEST=TRUE
NC_USB3_EXTC_RXP
MAKE_BASE=TRUE
JTAG_ISP_TDO
89 19
USB_EXTD_EHCI_P
25
USBHUB_DN1_P
USB_BT_P
95 32
USB3_EXTC_RX_N
USBHUB_DN1_N
MAKE_BASE=TRUE
18
NO_TEST=TRUE
NC_USB3_EXTC_RXN
MAKE_BASE=TRUE
1
1
USB_EXTD_EHCI_N
1
USB_BT_N
95 32
NO_TEST=TRUE
MAKE_BASE=TRUE
ZT0985
1
ZT0915
33
MAKE_BASE=TRUE
STDOFF-4.5OD.98H-1.1-3.48-TH
D
NC_USB_EXTD_EHCIN
MAKE_BASE=TRUE
89
JTAG_TBT_TCK
JTAG_ISP_TCK
23 19
2
USB Signals
JTAG_GMUX_TCK
STDOFF-4.5OD.98H-1.1-3.48-TH
1
3
T29 / GMUX JTAG Signals
ZT0930
STDOFF-4.5OD.98H-1.1-3.48-TH
1
4
Fan Holes
NO_TEST=TRUE
SMC_EXCARD_PWR_EN
TALL POGO PINS for BT NF
MAKE_BASE=TRUE
SH0903
POGO-2.0OD-3.5H-K86-K87
PCIE_EXCARD_D2R_N
PCIE_EXCARD_D2R_P
PCIE_EXCARD_R2D_C_N
PCIE_EXCARD_R2D_C_P
16
4.0OD1.85H-M1.6X0.35
POGO-2.0OD-3.5H-K86-K87
1
16
ZT0953
SH0916
SM
16
SM
1
16
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
1
NC_PCIE_EXCARD_D2RN
NC_PCIE_EXCARD_D2RP
NC_PCIE_EXCARD_R2D_CN
NC_PCIE_EXCARD_R2D_CP
DP_EG_AUXCH_N
NOSTUFF
SH0937
POGO-2.0OD-3.5H-K86-K87
SM
1
R0921
SM
8
1
1
SH0936 NOSTUFF
POGO-2.0OD-3.5H-K86-K87
TBT_A_BIAS0P
2
5%
1/20W
MF
201
1
1
NC_PEG_B_CLKRQ_L_GPIO56
TRUE
MAKE_BASE=TRUE
SH0910
SM
1
C0902
89
0.01UF
1
SM
ISSP_SCLK_P1_1
NO_TEST=TRUE
DPB_EG_ML_P & lt; 3..0 & gt;
NO_TEST=TRUE
R0926
6
ISSP_SDATA_P1_0
10%
10V
X5R
201
2
89
89
1
89
R0927
6
8
51
T29_A_BIAS_R
1
2
5%
1/20W
MF
201
TP_GMUX_PT20A
TP_GMUX_PT20B
TP_GMUX_PT32A
TP_GMUX_PT32B
TBT_A_BIAS1P
1
0.01UF
2
8
10%
10V
X5R
201
T29_A_BIAS_R
1
10%
10V
X5R
201
2
SH0918
16
TP_PCH_GPIO64_CLKOUTFLEX0
TP_PCH_GPIO65_CLKOUTFLEX1
TP_PCH_GPIO66_CLKOUTFLEX2
R0924
1.4DIA-SHORT-SILVER-K99
SM
8
T29_A_BIAS_R
51
1
1
5%
1/20W
MF
201
1.4DIA-SHORT-SILVER-K99
SM
2
2
NC_FSB_CLK133M_PCHP
C0904
MAKE_BASE=TRUE
1
51
T29_A_BIAS_R
C9490
0.1UF
=TBT_A_BIAS
2
10%
6.3V
X5R
201
5%
1/20W
MF
201
R0941
1
1K
8
2
2
10 DPLL_REF_CLK_N
Unused eDP CLK
=PPVIN_SW_TBTBST
6
1
87
DP_A_BIAS0
MAKE_BASE=TRUE
4.7K
5%
1/16W
MF-LF
402
2
86
17
DPA_IG_DDC_CLK
17
DPA_IG_DDC_DATA
17
DPA_IG_HPD
DP_IG_DDC_CLK
17
GND
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.095 mm
VOLTAGE=0V
DP_IG_DDC_DATA
MAKE_BASE=TRUE
86
DP_IG_HPD
Digital Ground
MAKE_BASE=TRUE
1
2
SYNC_MASTER=K18_MLB
NC_DPB_IG_AUX_CHP
=PP5V_S0_AUDIO
MAKE_BASE=TRUE
57
XW0902
93
MAKE_BASE=TRUE
SYNC_DATE=04/27/2010
PAGE TITLE
PP5V_S0_AUDIO
MAKE_BASE=TRUE
DPB_IG_AUX_CH_P
17
DPB_IG_AUX_CH_N
17
DRAWING NUMBER
TRUE
NC_DPB_IG_AUX_CHN
MAKE_BASE=TRUE
Signal Aliases
Apple Inc.
TRUE
SM
1
1
2
2
2
XW0903
=PP15V_TBT_REG
10%
10V
X5R
201
17
DPA_IG_AUX_CH_N
DP_IG_AUX_CH_N
SM
0
10%
10V
X5R
201
NO_TEST=TRUE
=PP5V_S0_AUDIO_XW
DPLL_REF_CLKN
17
TP_DP_IG_B_MLN & lt; 3..0 & gt;
DPA_IG_AUX_CH_P
2
0.01UF
NO_TEST=TRUE
XW0901
7
17
NO_TEST=TRUE
DP_IG_AUX_CH_P
C0908
0.01UF
C0905
MAKE_BASE=TRUE
86
SW_GAIN_TP
R0940
5%
1/16W
MF-LF
402
1
MAKE_BASE=TRUE
NO_TEST=TRUE
PP5V_S0_AUDIO_AMP_L
61
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.30MM
VOLTAGE=5V
7 35
1
2
NC_DPB_IG_DDC_CLK
MAKE_BASE=TRUE
DPB_IG_DDC_CLK
PP5V_S0_AUDIO_AMP_R
61
MAKE_BASE=TRUE
4
NOTICE OF PROPRIETARY PROPERTY:
DPB_IG_DDC_DATA
TRUE
3
3.0.0
17
BRANCH
17
DPB_IG_HPD
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.30MM
VOLTAGE=5V
5
R
TRUE
NC_DPB_IG_HPD
051-9585
REVISION
17
TRUE
NC_DPB_IG_DDC_DATA
MAKE_BASE=TRUE
SM
5%
1/8W
MF-LF
805
7
95 86
R0901
RT_GAIN_TP
NC_SW_GAIN_TP
R0950
8
DP_A_BIAS2
MAKE_BASE=TRUE
1
TBTBST:N
35 7
95 86
LCD_BKLT_EN
LT_GAIN_TP
1K
5%
1/16W
MF-LF
402
PLACE_NEAR=C9490.1:2 mm
87
TP_DP_IG_B_MLP & lt; 3..0 & gt;
NC_DP_IG_MLN & lt; 3..0 & gt;
90 89
NO_TEST=TRUE
MAKE_BASE=TRUE
14
7
12
=PP1V05_S0_CPU_VCCPQE
VOLTAGE=3.3V
1
87
2
MAKE_BASE=TRUE
FSB_CLK133M_PCH_N
NC_RT_GAIN_TP
DPLL_REF_CLKP
R9490
T29_A_BIAS
MAKE_BASE=TRUE
NC_DP_IG_MLP & lt; 3..0 & gt;
NO_TEST=TRUE
NC_LT_GAIN_TP
DPLL_REF_CLK_P
1
51
1
1
NO_TEST=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
A
FSB_CLK133M_PCH_P
NC_FSB_CLK133M_PCHN
10%
10V
X5R
201
MAKE_BASE=TRUE
93
10%
10V
X5R
201
5%
1/20W
MF
201
5%
1/20W
MF
201
87
0.01UF
62
R9362
=DP_A_BIAS
MAKE_BASE=TRUE
TBT_A_BIAS2N
1
87
NC_PCH_GPIO64_CLKOUTFLEX0
TRUE
MAKE_BASE=TRUE
NC_PCH_GPIO65_CLKOUTFLEX1
TRUE
MAKE_BASE=TRUE
NC_PCH_GPIO66_CLKOUTFLEX2
TRUE
MAKE_BASE=TRUE
NC_PCH_GPIO67_CLKOUTFLEX3
TRUE
MAKE_BASE=TRUE
TP_PCH_GPIO67_CLKOUTFLEX3
16
10
NC_PCH_CLKOUT_DPP
TRUE
MAKE_BASE=TRUE
2
16
GND_CHASSIS_AUDIO_JACK
B
0.01UF
PLACE_NEAR=C9361.1:2 mm
16
1
DP_A_BIAS
MAKE_BASE=TRUE
TP_PCH_CLKOUT_DPP
16
0.01UF
1
1
51
NC_PCH_CLKOUT_DPN
TRUE
MAKE_BASE=TRUE
87
C0903
1
SM
SH0914
88
C0907
R9363
TP_PCH_CLKOUT_DPN
16
TBT_A_BIAS2P
2
5%
1/20W
MF
201
SH0917
1.4DIA-SHORT-SILVER-K99
SM
1
2
2
51
1
1.4DIA-SHORT-SILVER-K99
TBT_A_BIAS1N
2
5%
1/20W
MF
201
R0923
1
SH0901
1
C0906
=PP1V05_S0M_PCH_VCC_LAN
SM
SM
51
T29_A_BIAS_R
PLACE_NEAR=C9361.1:2 mm
1.4DIA-SHORT-SILVER-K99
1.4DIA-SHORT-SILVER-K99
8
88
SH0913
SH0912
SM
1
NC_DPB_EG_MLP & lt; 3..0 & gt;
MAKE_BASE=TRUE
5%
1/20W
MF
201
1.4DIA-SHORT-SILVER-K99
1.4DIA-SHORT-SILVER-K99
TP_ISSP_SDATA_P1_0
POGO-2.0OD-3.5H-K86-K87
1
DPB_EG_ML_N & lt; 3..0 & gt;
MAKE_BASE=TRUE
SH0911
Short (IO Row) EMI pogo pins
TP_ISSP_SCLK_P1_1
53
87
SH0942
SM
DPB_EG_DDC_DATA
NO_TEST=TRUE
MAKE_BASE=TRUE
53
TBT_A_BIAS0N
2
POGO-2.0OD-3.5H-K86-K87
DPB_EG_DDC_CLK
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PCIECLKRQ4_L_GPIO26
TRUE
MAKE_BASE=TRUE
SH0940
NO_TEST=TRUE
NC_DPB_EG_DDC_DATA
TP_PCIECLKRQ4_L_GPIO26
R0922
51
1
DPB_EG_AUX_CH_P
NC_DPB_EG_DDC_CLK
TP_PEG_B_CLKRQ_L_GPIO56
SM
1
DPB_EG_AUX_CH_N
NC_DPB_EG_MLN & lt; 3..0 & gt;
1
1
MAKE_BASE=TRUE
MAKE_BASE=TRUE
10%
10V
X5R
201
2
T29_A_BIAS_R
MAKE_BASE=TRUE
NC_PCIE_CLK100M_EXCARDP
TRUE
MAKE_BASE=TRUE
C0901
SM
8
NC_PCIE_CLK100M_EXCARDN
TRUE
MAKE_BASE=TRUE
PCIE_CLK100M_EXCARD_P
96 16
0.01UF
SH0938 NOSTUFF
POGO-2.0OD-3.5H-K86-K87
SM
87
SH0939
POGO-2.0OD-3.5H-K86-K87
SH0941
SM
POGO-2.0OD-3.5H-K86-K87
NO_TEST=TRUE
NC_DPB_EG_AUX_CHP
PCIE_CLK100M_EXCARD_N
96 16
51
T29_A_BIAS_R
81 86 100
NC_DPB_EG_AUX_CHN
MAKE_BASE=TRUE
POGO-2.0OD-3.5H-K86-K87
81 86 100
DP_EG_AUX_CH_P
DP_EG_AUXCH_P
MAKE_BASE=TRUE
SH0904
B
DP_EG_AUX_CH_N
MAKE_BASE=TRUE
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
2
PAGE
9 OF 132
SHEET
8 OF 105
1
SIZE
D
A
8
7
6
5
4
=PP1V05_S0_CPU_VCCIO
1
U1000
IN
R8
93 17 6
IN
DMI_S2N_N & lt; 3 & gt;
U10
N8
93 17 6
IN
DMI_S2N_P & lt; 0 & gt;
93 17 6
IN
DMI_S2N_P & lt; 1 & gt;
T9
93 17
IN
DMI_S2N_P & lt; 2 & gt;
R6
93 17 6
IN
DMI_S2N_P & lt; 3 & gt;
U8
D
93 17
OUT
DMI_N2S_N & lt; 0 & gt;
N4
93 17 6
OUT
DMI_N2S_N & lt; 1 & gt;
R4
93 17 6
OUT
DMI_N2S_N & lt; 2 & gt;
OUT
DMI_N2S_N & lt; 3 & gt;
93 17 6
P1
U6
N2
OUT
DMI_N2S_P & lt; 0 & gt;
OUT
DMI_N2S_P & lt; 1 & gt;
93 17 6
OUT
DMI_N2S_P & lt; 2 & gt;
P3
93 17 6
OUT
DMI_N2S_P & lt; 3 & gt;
T5
93 17
93 17 6
R2
OUT
FDI_DATA_N & lt; 0 & gt;
V7
OUT
FDI_DATA_N & lt; 1 & gt;
W8
93 17
OUT
FDI_DATA_N & lt; 2 & gt;
AA8
93 17
OUT
FDI_DATA_N & lt; 3 & gt;
AC10
93 17
93 17 6
U4
93 17 6
OUT
FDI_DATA_N & lt; 4 & gt;
93 17 6
OUT
FDI_DATA_N & lt; 5 & gt;
W2
93 17 6
OUT
FDI_DATA_N & lt; 6 & gt;
V1
93 17 6
OUT
FDI_DATA_N & lt; 7 & gt;
Y5
W6
OUT
FDI_DATA_P & lt; 0 & gt;
93 17 6
OUT
FDI_DATA_P & lt; 1 & gt;
93 17
OUT
FDI_DATA_P & lt; 2 & gt;
Y9
93 17
OUT
FDI_DATA_P & lt; 3 & gt;
AA10
93 17
C
93 17 6
W10
FDI_DATA_P & lt; 4 & gt;
OUT
U2
W4
93 17 6
OUT
FDI_DATA_P & lt; 5 & gt;
93 17 6
OUT
FDI_DATA_P & lt; 6 & gt;
V3
OUT
FDI_DATA_P & lt; 7 & gt;
AA6
93 17 6
93 17 6
IN
FDI_FSYNC & lt; 0 & gt;
AC8
93 17 6
IN
FDI_FSYNC & lt; 1 & gt;
AA2
93 17 6
IN
FDI_INT
AD9
93 17 6
IN
FDI_LSYNC & lt; 1 & gt;
AB3
93 17 6
IN
FDI_LSYNC & lt; 0 & gt;
AB7
93 8
OUT
DP_INT_IG_ML_N & lt; 0 & gt;
AG2
93 8
OUT
DP_INT_IG_ML_N & lt; 1 & gt;
AF1
93 8
OUT
DP_INT_IG_ML_N & lt; 2 & gt;
AE6
93 8
OUT
DP_INT_IG_ML_N & lt; 3 & gt;
AG6
93 8
OUT
DP_INT_IG_ML_P & lt; 0 & gt;
AG4
93 8
OUT
DP_INT_IG_ML_P & lt; 1 & gt;
AF3
93 8
OUT
DP_INT_IG_ML_P & lt; 2 & gt;
AF7
93 8
OUT
DP_INT_IG_ML_P & lt; 3 & gt;
AG8
93 8
BI
DP_INT_IG_AUX_P
AE4
93 8
BI
DP_INT_IG_AUX_N
AE2
14 13 12 10 9 7 =PP1V05_S0_CPU_VCCIO
1
OMIT_TABLE
1K
5%
2
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
AB1
DMI_TX0*
DMI_TX1*
DMI_TX2*
DMI_TX3*
DMI_TX0
DMI_TX1
DMI_TX2
DMI_TX3
FDI0_TX0*
FDI0_TX1*
FDI0_TX2*
FDI0_TX3*
FDI1_TX0*
FDI1_TX1*
FDI1_TX2*
FDI1_TX3*
FDI0_TX0
FDI0_TX1
FDI0_TX2
FDI0_TX3
FDI1_TX0
FDI1_TX1
FDI1_TX2
FDI1_TX3
FDI0_FSYNC
FDI1_FSYNC
FDI_INT
D
IN
EDP_TX0
EDP_TX1
EDP_TX2
EDP_TX3
EDP_AUX
EDP_AUX*
EDP_ICOMPO
EDP_COMPIO
CPU_CFG & lt; 6 & gt;
CPU_CFG & lt; 2 & gt;
A54
(IPU)
CPU_CFG & lt; 4 & gt;
A58
(IPU)
BB15
93 23 9
CPU_CFG & lt; 5 & gt;
D55
(IPU)
BB13
93 23 9
CPU_CFG & lt; 6 & gt;
C56
(IPU)
BA48
93 23 9
CPU_CFG & lt; 7 & gt;
E54
(IPU)
BA16
93 23
CPU_CFG & lt; 8 & gt;
J54
(IPU)
AY45
93 23
CPU_CFG & lt; 9 & gt;
G56
(IPU)
AY41
93 23
CPU_CFG & lt; 10 & gt;
F55
(IPU)
AY17
93 23
CPU_CFG & lt; 11 & gt;
K55
(IPU)
AY15
93 23
CPU_CFG & lt; 12 & gt;
F57
(IPU)
AY13
93 23
CPU_CFG & lt; 13 & gt;
E58
(IPU)
AW50
93 23
CPU_CFG & lt; 14 & gt;
H57
(IPU)
AW46
93 23
CPU_CFG & lt; 15 & gt;
H55
(IPU)
AW42
93 23 9
CPU_CFG & lt; 16 & gt;
D53
(IPU)
AW14
93 23
CPU_CFG & lt; 17 & gt;
K57
(IPU)
8
=PEG_D2R_N & lt; 2 & gt;
IN
8
H19
=PEG_D2R_N & lt; 3 & gt;
IN
8
J20
=PEG_D2R_N & lt; 4 & gt;
IN
8
G18
=PEG_D2R_N & lt; 5 & gt;
IN
8
K17
=PEG_D2R_N & lt; 6 & gt;
IN
8
F15
=PEG_D2R_N & lt; 7 & gt;
IN
8
IN
8
H15
=PEG_D2R_N & lt; 8 & gt;
H13
=PEG_D2R_N & lt; 9 & gt;
IN
8
H11
=PEG_D2R_N & lt; 10 & gt;
IN
8
J12
=PEG_D2R_N & lt; 11 & gt;
IN
8
IN
8
E8
=PEG_D2R_N & lt; 12 & gt;
G10
=PEG_D2R_N & lt; 13 & gt;
IN
8
J8
=PEG_D2R_N & lt; 14 & gt;
IN
8
=PEG_D2R_N & lt; 15 & gt;
IN
8
F7
=PEG_D2R_P & lt; 1 & gt;
IN
8
=PEG_D2R_P & lt; 2 & gt;
IN
8
G6
=PEG_D2R_P & lt; 15 & gt;
A22
=PEG_R2D_C_N & lt; 0 & gt;
B23
=PEG_R2D_C_N & lt; 1 & gt;
C18
PEG_TX0
PEG_TX1
PEG_TX2
PEG_TX3
PEG_TX4
PEG_TX5
PEG_TX6
PEG_TX7
PEG_TX8
PEG_TX9
PEG_TX10
PEG_TX11
PEG_TX12
PEG_TX13
PEG_TX14
PEG_TX15
F19
=PEG_D2R_P & lt; 3 & gt;
IN
K19
=PEG_D2R_P & lt; 4 & gt;
IN
8
IN
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
8
8
H17
=PEG_D2R_P & lt; 5 & gt;
K15
=PEG_D2R_P & lt; 6 & gt;
IN
8
G14
=PEG_D2R_P & lt; 7 & gt;
IN
8
J16
=PEG_D2R_P & lt; 8 & gt;
IN
8
=PEG_D2R_P & lt; 9 & gt;
IN
8
K13
F11
=PEG_D2R_P & lt; 10 & gt;
IN
8
K11
=PEG_D2R_P & lt; 11 & gt;
IN
=PEG_D2R_P & lt; 12 & gt;
IN
NOTE:
8
F9
8
H9
=PEG_D2R_P & lt; 13 & gt;
IN
H7
=PEG_D2R_P & lt; 14 & gt;
IN
8
IN
8
OUT
8
OUT
8
=PEG_R2D_C_N & lt; 2 & gt;
OUT
8
D21
=PEG_R2D_C_N & lt; 3 & gt;
OUT
8
B19
=PEG_R2D_C_N & lt; 4 & gt;
OUT
8
E20
=PEG_R2D_C_N & lt; 5 & gt;
OUT
8
A14
=PEG_R2D_C_N & lt; 6 & gt;
OUT
8
D17
=PEG_R2D_C_N & lt; 7 & gt;
OUT
Intel is investigating processor driven VREF_DQ generation.
This connection is to support the same.
8
8
93 31
(IPU)
OMIT_TABLE
(5 OF 11)
RESERVED
BB17
CFG
AJ10
=PEG_R2D_C_N & lt; 8 & gt;
OUT
E16
=PEG_R2D_C_N & lt; 9 & gt;
OUT
8
D13
=PEG_R2D_C_N & lt; 10 & gt;
OUT
=PEG_R2D_C_N & lt; 11 & gt;
OUT
8
B11
=PEG_R2D_C_N & lt; 12 & gt;
OUT
8
D9
=PEG_R2D_C_N & lt; 13 & gt;
OUT
8
B7
=PEG_R2D_C_N & lt; 14 & gt;
OUT
8
E12
=PEG_R2D_C_N & lt; 15 & gt;
OUT
8
C22
=PEG_R2D_C_P & lt; 0 & gt;
OUT
8
D23
=PEG_R2D_C_P & lt; 1 & gt;
OUT
8
A18
=PEG_R2D_C_P & lt; 2 & gt;
OUT
=PEG_R2D_C_P & lt; 3 & gt;
OUT
=PEG_R2D_C_P & lt; 4 & gt;
OUT
=PEG_R2D_C_P & lt; 5 & gt;
OUT
=PEG_R2D_C_P & lt; 6 & gt;
OUT
=PEG_R2D_C_P & lt; 7 & gt;
OUT
=PEG_R2D_C_P & lt; 8 & gt;
OUT
=PEG_R2D_C_P & lt; 9 & gt;
OUT
=PEG_R2D_C_P & lt; 10 & gt;
OUT
=PEG_R2D_C_P & lt; 11 & gt;
OUT
=PEG_R2D_C_P & lt; 12 & gt;
OUT
=PEG_R2D_C_P & lt; 13 & gt;
OUT
=PEG_R2D_C_P & lt; 14 & gt;
OUT
=PEG_R2D_C_P & lt; 15 & gt;
OUT
L2
BG22
K49
(DDR_VREF1)
(THERMDA)
K47
BF63
K9
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
BE32
G52
BE16
G48
K7
BF43
BF41
K5
RSVD
BF35
J50
BF25
J4
BF23
J2
BF21
H49
BF19
H47
(THERMDC)
H5
(DDR_VREF0)
BE6
G4
BD33
F5
BD29
D49
BD19
D25
BD15
D3
BD13
C52
BC42
C24
BC30
C4
BC14
B53
C
8
F13
L4
BG26
8
D7
L6
BG34
8
B9
BG62
8
D11
M5
L10
8
C10
M9
BH19
8
B13
N6
BH21
8
F17
BH23
8
D15
BH25
8
B17
P7
RSVD
8
C14
AA4
BH35
D
8
F21
AC4
BH43
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
8
D19
AC6
BJ22
8
B21
AD5
BF3
8
A10
AH5
BJ34
NC
NC
NC
NC
NC
NC
NC
NC
PPCPU_MEM_VREFDQ_A
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.75V
8
G64
BJ42
BG4
PPCPU_MEM_VREFDQ_B
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.75V
93 31
B15
8
93 23 9 CPU_CFG & lt; 1 & gt;
93 23 9
CPU_CFG & lt; 3 & gt;
93 23 9
IN
H21
(IPU)
(IPU)
93 23 9 CPU_CFG & lt; 0 & gt;
B25
B
93 23 9 CPU_CFG & lt; 3 & gt;
CPU_CFG & lt; 4 & gt;
BB25
93 23 9
=PEG_D2R_N & lt; 1 & gt;
93 23 9 CPU_CFG & lt; 16 & gt;
CPU_CFG & lt; 5 & gt;
93 23 9
BB43
CPU_CFG & lt; 2 & gt;
B55
CPU_CFG & lt; 7 & gt;
93 23 9
BB57
BGA
D57
93 23 9
H23
K21
EDP_HPD*
93 23 9
U1000
IVY-BRIDGE
B57
CPU_CFG & lt; 1 & gt;
8
PEG_TX0*
PEG_TX1*
PEG_TX2*
PEG_TX3*
PEG_TX4*
PEG_TX5*
PEG_TX6*
PEG_TX7*
PEG_TX8*
PEG_TX9*
PEG_TX10*
PEG_TX11*
PEG_TX12*
PEG_TX13*
PEG_TX14*
PEG_TX15*
EDP_TX0*
EDP_TX1*
EDP_TX2*
EDP_TX3*
93 23 9
IN
K23
EDP:YES
2
=PEG_D2R_N & lt; 0 & gt;
CPU_CFG & lt; 0 & gt;
93 23 9
F23
8
SOT-523-3
S
F3
IN
2N7002TXG
G
93 CPU_PEG_COMP
H1
=PEG_D2R_P & lt; 0 & gt;
Q1031
8
G2
1%
1/16W
MF-LF
402
G22
3
1
DP_INT_IG_HPD
2
PEG_RX0
PEG_RX1
PEG_RX2
PEG_RX3
PEG_RX4
PEG_RX5
PEG_RX6
PEG_RX7
PEG_RX8
PEG_RX9
PEG_RX10
PEG_RX11
PEG_RX12
PEG_RX13
PEG_RX14
PEG_RX15
FDI1_LSYNC
FDI0_LSYNC
AE8
DP_INT_IG_HPD_L
R1010
AJ6
AC2
93 CPU_EDP_COMP
PEG_RX0*
PEG_RX1*
PEG_RX2*
PEG_RX3*
PEG_RX4*
PEG_RX5*
PEG_RX6*
PEG_RX7*
PEG_RX8*
PEG_RX9*
PEG_RX10*
PEG_RX11*
PEG_RX12*
PEG_RX13*
PEG_RX14*
PEG_RX15*
DMI_RX0
DMI_RX1
DMI_RX2
DMI_RX3
PLACE_NEAR=U1000.AB1:12.7mm
2
1
93 23 9
24.9
1
R1031
B
R1030
(1 OF 11) PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
DMI_RX0*
DMI_RX1*
DMI_RX2*
DMI_RX3*
DMI
R10
DMI_S2N_N & lt; 2 & gt;
INTEL FLEXIBLE DISPLAY INTERFACE SIGNALS
PCI EXPRESS BASED INTERFACE SIGNALS
N10
DMI_S2N_N & lt; 1 & gt;
IN
93 17 6
OMIT_TABLE
EMBEDDED DISPLAY PORT
DMI_S2N_N & lt; 0 & gt;
IN
93 17
93 17 6
2
24.9
IVY-BRIDGE
BGA
3
7 9 10 12 13 14
PART NUMBER
QTY
DESCRIPTION
REFERENCE DES
CRITICAL
BOM OPTION
116S0066
1
RES,MTL FILM,1/16W,1K,0402,SMD,LF
R1031
EDP:YES
116S0090
1
RES,MTL FILM,1/16W,10K,0402,SMD,LF
R1031
EDP:NO
EDP:YES
NOSTUFF
1
1
R1042
R1044
1K
1
NOSTUFF
R1045
1K
1
R1046
1K
NOSTUFF
NOSTUFF
1
R1047
1K
1
R1040
1K
NOSTUFF
1
NOSTUFF
R1041
1K
NOSTUFF
1
R1043
1K
R1049
1K
1K
5%
5%
5%
5%
5%
5%
5%
5%
5%
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
MF-LF
A
1
MF-LF
MF-LF
MF-LF
MF-LF
MF-LF
MF-LF
MF-LF
MF-LF
402
2
402
2
402
2
402
2
402
402
2
2
402
402
2
402
2
A
2
PAGE TITLE
CPU DMI/PEG/FDI/RSVD
DRAWING NUMBER
These can be Placed close to J2500 and Only for debug access
CPU_CFG & lt; 4 & gt; should be pulled down to enable EDP
Apple Inc.
051-9585
R
CFG [7] :PEG DEFER TRAINING
1 = (DEFAULT) IMMEDIATELY AFTER xxRESETB
CFG [6:5] :PCIE BIFURCATION
11 = 1 X16 (DEFAULT)
CFG [4] :eDP ENABLE/DISABLE
1 = DISABLED
CFG [3] :PCIE x4 LANE REVERSAL
1 = NORMAL OPERATION
1 = NORMAL OPERATION
0 = WAIT FOR BIOS
0 = LANES REVERSED
7
01 = RSVD
NOTICE OF PROPRIETARY PROPERTY:
0 = LANES REVERSED
CFG [2] :PCIE x16 LANE REVERSAL
8
10 = 2 X8
00 = X8, X4, X4
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
0 = ENABLED
6
5
4
3
2
SIZE
D
REVISION
3.0.0
BRANCH
PAGE
10 OF 132
SHEET
9 OF 105
1
8
7
6
5
4
3
2
1
D
D
=PP1V05_S0_CPU_VCCIO
14 13 12 10 9 7
=PP1V05_S0_CPU_VCCIO
NOSTUFF
R1100
1
1
1K
R1101
5%
1/20W
MF
201
68
5%
1/16W
MF-LF
2
NOSTUFF
1
R1104
NOSTUFF
1
5%
1/16W
MF-LF
2
2
402
R1102
1K
51
2
U1000
5%
1/20W
MF
201
IVY-BRIDGE
BGA
OMIT_TABLE
DPLL_REF_CLK
402
NC
93 19
B59
PROC_DETECT*
(2 OF 11)
PROC_SELECT*
OUT
CPU_PROC_SEL_L
AH9
OUT
CPU_CATERR_L
H53
CLOCKS
14 13 12 10 9 7
R1103
93 69 46 45
2
CPU_PROCHOT_L
BI
93 45
1
5%
1/16W
MF-LF
402
93 46 19
CPU_PECI
BI
1
F53
PECI
CPU_PROCHOT_R_L
14 13 12 10 9 7 =PP1V05_S0_CPU_VCCIO
R1126
H51
PROCHOT*
75
1%
1/16W
MF-LF
402
CATERR*
93 46 19
F51
PM_THRMTRIP_L
OUT
THERMAL
C
56
AJ4
DPLL_REF_CLK_P
IN
8
DPLL_REF_CLK*
AJ2
DPLL_REF_CLK_N
IN
8
BCLK_ITP
BCLK_ITP*
K63
ITPCPU_CLK100M_P
IN
16 93
K65
ITPCPU_CLK100M_N
IN
16 93
BCLK
BCLK*
D5
DMI_CLK100M_CPU_P
IN
16 93
C6
DMI_CLK100M_CPU_N
IN
16 93
PRDY*
PREQ*
J62
XDP_CPU_PRDY_L
OUT
23 93
H65
XDP_CPU_PREQ_L
IN
23 93
TCK
TMS
TRST*
J58
(IPU)
(IPU)
THERMTRIP*
1
K51
1%
1/16W
MF-LF
402
93 17
93 23 19
PM_SYNC
IN
PM_SYNC
C60
CPU_PWRGD
IN
RESET*
K53
PLT_RESET_LS1V1_L
AY25
PM_MEM_PWRGD_R
PWR MGMT
(IPU)
UNCOREPWRGOOD
JTAG & BPM
2
CPU_RESET_L
IN
43.2
(IPU)
(IPU)
=PP1V5_S3_CPU_VCCDDR
BJ44
CPU_DDR_VREF
PLACE_NEAR=R1121.2:1mm
R1120 1
SM_VREF
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
200
B
IN
93 CPU_SM_RCOMP & lt; 0 & gt;
BJ46
1%
1/16W
MF-LF
402
93 26 17
93 CPU_SM_RCOMP & lt; 1 & gt;
BG46
93 CPU_SM_RCOMP & lt; 2 & gt;
BF45
R1121
2
1
1%
1/16W
MF-LF
402
PLACE_NEAR=U1000.AY25:51.562mm
R1112
1
140
R1113
1
25.5
1
200
1%
1%
1/16W
2
1/16W
PLACE_NEAR=U1000.BF45:12.7mm
1/16W
MF-LF
MF-LF
R1131
IN
23 93
K59
XDP_CPU_TDO
OUT
23 93
H61
XDP_DBRESET_L
OUT
23 24 93
BPM0*
BPM1*
BPM2*
BPM3*
BPM4*
BPM5*
BPM6*
BPM7*
C62
XDP_BPM_L & lt; 0 & gt;
BI
(IPU)
(IPU)
D61
XDP_BPM_L & lt; 1 & gt;
BI
E62
XDP_BPM_L & lt; 2 & gt;
(IPU)
BI
23 93
F63
XDP_BPM_L & lt; 3 & gt;
BI
23 93
(IPU)
(IPU)
(IPU)
D59
XDP_BPM_L & lt; 4 & gt;
BI
23 93
F61
XDP_BPM_L & lt; 5 & gt;
BI
23 93
F59
XDP_BPM_L & lt; 6 & gt;
(IPU)
BI
23 93
G60
XDP_BPM_L & lt; 7 & gt;
BI
23 93
23 93
23 93
402
2
402
2
B
R1111
5%
402
PLACE_NEAR=U1800.AY11:157mm
1/16W
MF-LF
402
PLACE_NEAR=U1000.BJ46:12.7mm
2
1
1
1K
5%
1/16W
MF-LF
402
XDP_CPU_TDI
PLACE_NEAR=U1000.BG46:12.7mm
1
1K
PLACE_NEAR=U1000.BJ44:2.54mm
K61
10K
2
5%
1/16W
MF-LF
402
23 93
TDI
TDO
R1114
1%
=PP1V5_S3_CPU_VCCDDR
R1130
23 93
IN
1
MF-LF
PLACE_NEAR=U1000.BJ44:2.54mm
23 93
IN
XDP_CPU_TRST_L
130
2
PM_MEM_PWRGD
R1120 and R1121 are Intel recommended values
26 15 13 10 7
SM_DRAMRST*
DDR3 MISC
26 15 13 10 7
BE24
=MEM_RESET_L
OUT
IN
XDP_CPU_TMS
H63
SM_DRAMPWROK
(IPU)
26
XDP_CPU_TCK
H59
DBR*
24 23
(IPD)
R1125
2
C
C1130
0.1UF
2
2
10%
16V
X5R
402
PLACE_NEAR=U1000.BJ44:2.54mm
A
A
PAGE TITLE
CPU CLOCK/MISC/JTAG
DRAWING NUMBER
Apple Inc.
051-9585
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
3.0.0
BRANCH
PAGE
11 OF 132
SHEET
10 OF 105
1
6
94 28 6
BI
MEM_A_DQ & lt; 0 & gt;
AL6
94 28 6
BI
MEM_A_DQ & lt; 1 & gt;
AL8
BI
MEM_A_DQ & lt; 2 & gt;
AP7
94 28 6
BI
MEM_A_DQ & lt; 3 & gt;
AM5
94 28 6
BI
MEM_A_DQ & lt; 4 & gt;
AK7
94 28 6
BI
MEM_A_DQ & lt; 5 & gt;
AL10
94 28 6
BI
MEM_A_DQ & lt; 6 & gt;
AN10
94 28 6
BI
MEM_A_DQ & lt; 7 & gt;
AM9
94 28 6
BI
MEM_A_DQ & lt; 8 & gt;
AR10
94 28 6
D
BI
MEM_A_DQ & lt; 9 & gt;
AR8
94 28 6
BI
MEM_A_DQ & lt; 10 & gt;
AV7
94 28 6
BI
MEM_A_DQ & lt; 11 & gt;
AY5
94 28 6
BI
MEM_A_DQ & lt; 12 & gt;
AT5
94 28 6
BI
MEM_A_DQ & lt; 13 & gt;
AR6
94 28 6
BI
MEM_A_DQ & lt; 14 & gt;
AW6
94 28 6
BI
MEM_A_DQ & lt; 15 & gt;
AT9
94 28 6
MEM_A_DQ & lt; 16 & gt;
BA6
BI
MEM_A_DQ & lt; 17 & gt;
BA8
94 28 6
BI
MEM_A_DQ & lt; 18 & gt;
BG6
94 28 6
BI
MEM_A_DQ & lt; 19 & gt;
AY9
94 28 6
BI
94 28 6
BI
MEM_A_DQ & lt; 20 & gt;
AW8
94 28 6
BI
MEM_A_DQ & lt; 21 & gt;
BB7
94 28 6
BI
MEM_A_DQ & lt; 22 & gt;
BC8
BI
MEM_A_DQ & lt; 23 & gt;
BE4
AW12
94 28 6
94 28 6
BI
MEM_A_DQ & lt; 24 & gt;
94 28 6
BI
MEM_A_DQ & lt; 25 & gt;
AV11
94 28 6
BI
MEM_A_DQ & lt; 26 & gt;
BB11
94 28 6
BI
MEM_A_DQ & lt; 27 & gt;
BA12
94 28 6
BI
MEM_A_DQ & lt; 28 & gt;
BE8
94 28 6
BI
MEM_A_DQ & lt; 29 & gt;
BA10
BI
MEM_A_DQ & lt; 30 & gt;
BD11
BE12
94 28 6
94 28 6
C
BI
MEM_A_DQ & lt; 31 & gt;
94 28 6
BI
MEM_A_DQ & lt; 32 & gt;
BB49
94 28 6
BI
MEM_A_DQ & lt; 33 & gt;
AY49
94 28 6
BI
MEM_A_DQ & lt; 34 & gt;
BE52
94 28 6
BI
MEM_A_DQ & lt; 35 & gt;
BD51
94 28 6
BI
MEM_A_DQ & lt; 36 & gt;
BD49
94 28 6
BI
MEM_A_DQ & lt; 37 & gt;
BE48
BA52
94 28 6
BI
MEM_A_DQ & lt; 38 & gt;
94 28 6
BI
MEM_A_DQ & lt; 39 & gt;
AY51
94 28 6
BI
MEM_A_DQ & lt; 40 & gt;
BC54
94 28 6
BI
MEM_A_DQ & lt; 41 & gt;
AY53
94 28 6
BI
MEM_A_DQ & lt; 42 & gt;
AW54
94 28 6
BI
MEM_A_DQ & lt; 43 & gt;
AY55
94 28 6
BI
MEM_A_DQ & lt; 44 & gt;
BD53
BB53
94 28 6
BI
MEM_A_DQ & lt; 45 & gt;
94 28 6
BI
MEM_A_DQ & lt; 46 & gt;
BE56
94 28 6
BI
MEM_A_DQ & lt; 47 & gt;
BA56
94 28 6
BI
MEM_A_DQ & lt; 48 & gt;
BD57
94 28 6
BI
MEM_A_DQ & lt; 49 & gt;
BF61
94 28 6
BI
MEM_A_DQ & lt; 50 & gt;
BA60
94 28 6
BI
94 28 6
94 28 6
MEM_A_DQ & lt; 51 & gt;
BB61
BI
MEM_A_DQ & lt; 52 & gt;
BE60
94 28 6
BI
MEM_A_DQ & lt; 53 & gt;
BD63
94 28 6
BI
MEM_A_DQ & lt; 54 & gt;
BB59
BI
MEM_A_DQ & lt; 55 & gt;
BC58
94 28 6
BI
MEM_A_DQ & lt; 56 & gt;
AW58
94 28 6
BI
MEM_A_DQ & lt; 57 & gt;
AY59
94 28 6
BI
MEM_A_DQ & lt; 58 & gt;
AL60
94 28 6
BI
MEM_A_DQ & lt; 59 & gt;
AP61
94 28 6
BI
MEM_A_DQ & lt; 60 & gt;
AW60
94 28 6
BI
MEM_A_DQ & lt; 61 & gt;
AY57
94 28 6
BI
MEM_A_DQ & lt; 62 & gt;
AN60
94 28 6
BI
MEM_A_DQ & lt; 63 & gt;
AR60
94 27 6
OUT
94 27 6
94 28 6
B
MEM_A_BA & lt; 0 & gt;
BA36
OUT
MEM_A_BA & lt; 1 & gt;
BC38
94 27 6
OUT
MEM_A_BA & lt; 2 & gt;
BB19
94 27 6
OUT
MEM_A_CAS_L
BE44
94 27 6
OUT
MEM_A_RAS_L
BE36
OUT
MEM_A_WE_L
BA44
94 27 6
SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63
U1000
IVY-BRIDGE
BGA
SA_CLK0
SA_CLK0*
5
4
3
BB31
MEM_A_CLK_P & lt; 0 & gt;
OUT
6 27 94
94 28 6
BI
MEM_B_DQ & lt; 0 & gt;
AL4
BA32
MEM_A_CLK_N & lt; 0 & gt;
OUT
6 27 94
94 28 6
BI
MEM_B_DQ & lt; 1 & gt;
AK3
SA_CKE0
BI
MEM_B_DQ & lt; 2 & gt;
94 28 6
BI
MEM_B_DQ & lt; 3 & gt;
AR2
94 28 6
OMIT_TABLE
(3 OF 11)
AP3
BI
MEM_B_DQ & lt; 4 & gt;
AL2
94 28 6
BC18
MEM_A_CKE & lt; 0 & gt;
OUT
6 27 94
SA_CLK1
SA_CLK1*
AW34
MEM_A_CLK_P & lt; 1 & gt;
OUT
6 27 94
94 28 6
BI
MEM_B_DQ & lt; 5 & gt;
AK1
AY33
MEM_A_CLK_N & lt; 1 & gt;
OUT
6 27 94
94 28 6
BI
MEM_B_DQ & lt; 6 & gt;
AP1
94 28 6
BI
MEM_B_DQ & lt; 7 & gt;
AR4
SA_CKE1
BD17
MEM_A_CKE & lt; 1 & gt;
OUT
6 27 94
94 28 6
BI
MEM_B_DQ & lt; 8 & gt;
AV3
94 28 6
BI
MEM_B_DQ & lt; 9 & gt;
AU4
SA_CS0*
SA_CS1*
BD41
MEM_A_CS_L & lt; 0 & gt;
OUT
6 27 94
94 28 6
BI
MEM_B_DQ & lt; 10 & gt;
BA4
BD45
MEM_A_CS_L & lt; 1 & gt;
OUT
6 27 94
94 28 6
BI
MEM_B_DQ & lt; 11 & gt;
BB1
94 28 6
BI
MEM_B_DQ & lt; 12 & gt;
AV1
SA_ODT0
SA_ODT1
BB41
MEM_A_ODT & lt; 0 & gt;
OUT
6 27 94
94 28 6
BI
MEM_B_DQ & lt; 13 & gt;
AU2
BC46
MEM_A_ODT & lt; 1 & gt;
OUT
6 27 94
94 28 6
BI
MEM_B_DQ & lt; 14 & gt;
BA2
94 28 6
BI
MEM_B_DQ & lt; 15 & gt;
BB3
BC2
SA_DQS0*
SA_DQS1*
SA_DQS2*
SA_DQS3*
SA_DQS4*
SA_DQS5*
SA_DQS6*
SA_DQS7*
AN8
MEM_A_DQS_N & lt; 0 & gt;
BI
6 28 94
94 28 6
BI
MEM_B_DQ & lt; 16 & gt;
AU6
MEM_A_DQS_N & lt; 1 & gt;
BI
6 28 94
94 28 6
BI
MEM_B_DQ & lt; 17 & gt;
BF7
BC6
MEM_A_DQS_N & lt; 2 & gt;
BI
6 28 94
94 28 6
BI
MEM_B_DQ & lt; 18 & gt;
BF11
BD9
MEM_A_DQS_N & lt; 3 & gt;
BI
6 28 94
94 28 6
BI
MEM_B_DQ & lt; 19 & gt;
BJ10
BC4
BC50
MEM_A_DQS_N & lt; 4 & gt;
BI
6 28 94
94 28 6
BI
MEM_B_DQ & lt; 20 & gt;
BB55
MEM_A_DQS_N & lt; 5 & gt;
BI
6 28 94
94 28 6
BI
MEM_B_DQ & lt; 21 & gt;
BH7
BD59
MEM_A_DQS_N & lt; 6 & gt;
BI
6 28 94
94 28 6
BI
MEM_B_DQ & lt; 22 & gt;
BH11
BI
MEM_B_DQ & lt; 23 & gt;
BG10
BJ14
AU60
MEM_A_DQS_N & lt; 7 & gt;
BI
6 28 94
94 28 6
BI
MEM_B_DQ & lt; 24 & gt;
BI
6 28 94
94 28 6
BI
MEM_B_DQ & lt; 25 & gt;
BG14
BI
6 28 94
94 28 6
BI
MEM_B_DQ & lt; 26 & gt;
BF17
BJ18
94 28 6
SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7
AN6
MEM_A_DQS_P & lt; 0 & gt;
AU8
MEM_A_DQS_P & lt; 1 & gt;
BD5
MEM_A_DQS_P & lt; 2 & gt;
BI
6 28 94
94 28 6
BI
MEM_B_DQ & lt; 27 & gt;
BC10
MEM_A_DQS_P & lt; 3 & gt;
BI
6 28 94
94 28 6
BI
MEM_B_DQ & lt; 28 & gt;
BF13
BB51
MEM_A_DQS_P & lt; 4 & gt;
BI
6 28 94
94 28 6
BI
MEM_B_DQ & lt; 29 & gt;
BH13
BI
MEM_B_DQ & lt; 30 & gt;
BH17
BG18
BD55
MEM_A_DQS_P & lt; 5 & gt;
BD61
MEM_A_DQS_P & lt; 6 & gt;
AV61
MEM_A_DQS_P & lt; 7 & gt;
BI
6 28 94
94 28 6
6 28 94
94 28 6
BI
BI
6 28 94
94 28 6
BI
MEM_B_DQ & lt; 32 & gt;
BH49
94 28 6
SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_MA14
SA_MA15
BI
MEM_B_DQ & lt; 31 & gt;
BI
MEM_B_DQ & lt; 33 & gt;
BF47
BD27
MEM_A_A & lt; 0 & gt;
OUT
6 27 94
94 28 6
BI
MEM_B_DQ & lt; 34 & gt;
BH53
BA28
MEM_A_A & lt; 1 & gt;
OUT
6 27 94
94 28 6
BI
MEM_B_DQ & lt; 35 & gt;
BG50
BB27
MEM_A_A & lt; 2 & gt;
OUT
6 27 94
94 28 6
BI
MEM_B_DQ & lt; 36 & gt;
BF49
AW26
MEM_A_A & lt; 3 & gt;
OUT
6 27 94
94 28 6
BI
MEM_B_DQ & lt; 37 & gt;
BH47
BB23
MEM_A_A & lt; 4 & gt;
OUT
6 27 94
94 28 6
BI
MEM_B_DQ & lt; 38 & gt;
BF53
BA24
MEM_A_A & lt; 5 & gt;
OUT
6 27 94
94 28 6
BI
MEM_B_DQ & lt; 39 & gt;
BJ50
AY21
MEM_A_A & lt; 6 & gt;
OUT
6 27 94
94 28 6
BI
MEM_B_DQ & lt; 40 & gt;
BF55
BD21
MEM_A_A & lt; 7 & gt;
OUT
6 27 94
94 28 6
BI
MEM_B_DQ & lt; 41 & gt;
BH55
BC22
MEM_A_A & lt; 8 & gt;
OUT
6 27 94
94 28 6
BI
MEM_B_DQ & lt; 42 & gt;
BJ58
BB21
MEM_A_A & lt; 9 & gt;
OUT
6 27 94
94 28 6
BI
MEM_B_DQ & lt; 43 & gt;
BH59
AW38
MEM_A_A & lt; 10 & gt;
OUT
6 27 94
94 28 6
BI
MEM_B_DQ & lt; 44 & gt;
BJ54
AW22
MEM_A_A & lt; 11 & gt;
OUT
6 27 94
94 28 6
BI
MEM_B_DQ & lt; 45 & gt;
BG54
BA20
MEM_A_A & lt; 12 & gt;
OUT
6 27 94
94 28 6
BI
MEM_B_DQ & lt; 46 & gt;
BG58
BB45
MEM_A_A & lt; 13 & gt;
OUT
6 27 94
94 28 6
BI
MEM_B_DQ & lt; 47 & gt;
BF59
BE20
MEM_A_A & lt; 14 & gt;
AW18
MEM_A_A & lt; 15 & gt;
OUT
6 27 94
94 28 6
BI
MEM_B_DQ & lt; 48 & gt;
BA64
OUT
6 27 94
94 28 6
BI
MEM_B_DQ & lt; 49 & gt;
BC62
94 28 6
BI
MEM_B_DQ & lt; 50 & gt;
AU62
94 28 6
BI
94 28 6
MEM_B_DQ & lt; 51 & gt;
AW64
BI
MEM_B_DQ & lt; 52 & gt;
BA62
94 28 6
BI
MEM_B_DQ & lt; 53 & gt;
BC64
94 28 6
BI
MEM_B_DQ & lt; 54 & gt;
AU64
94 28 6
BI
MEM_B_DQ & lt; 55 & gt;
AW62
94 28 6
BI
MEM_B_DQ & lt; 56 & gt;
AR64
94 28 6
BI
MEM_B_DQ & lt; 57 & gt;
AT65
94 28 6
BI
MEM_B_DQ & lt; 58 & gt;
AL64
94 28 6
BI
MEM_B_DQ & lt; 59 & gt;
AM65
94 28 6
BI
MEM_B_DQ & lt; 60 & gt;
AR62
94 28 6
BI
MEM_B_DQ & lt; 61 & gt;
AT63
94 28 6
BI
MEM_B_DQ & lt; 62 & gt;
AL62
94 28 6
BI
MEM_B_DQ & lt; 63 & gt;
AM63
SA_BS0
SA_BS1
SA_BS2
94 29 6
OUT
MEM_B_BA & lt; 0 & gt;
BJ38
94 29 6
OUT
MEM_B_BA & lt; 1 & gt;
BD37
94 29 6
OUT
MEM_B_BA & lt; 2 & gt;
AY29
SA_CAS*
SA_RAS*
SA_WE*
94 29 6
OUT
MEM_B_CAS_L
BH39
94 29 6
OUT
MEM_B_RAS_L
BG38
OUT
MEM_B_WE_L
BF39
94 29 6
SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63
2
U1000
1
MEM_B_CLK_P & lt; 0 & gt;
OUT
6 29 94
BH33
MEM_B_CLK_N & lt; 0 & gt;
OUT
6 29 94
SB_CKE0
BD25
MEM_B_CKE & lt; 0 & gt;
OUT
6 29 94
BF37
MEM_B_CLK_P & lt; 1 & gt;
OUT
6 29 94
BH37
MEM_B_CLK_N & lt; 1 & gt;
OUT
6 29 94
SB_CKE1
BJ26
MEM_B_CKE & lt; 1 & gt;
OUT
6 29 94
SB_CS0*
SB_CS1*
BE40
MEM_B_CS_L & lt; 0 & gt;
OUT
6 29 94
BH41
MEM_B_CS_L & lt; 1 & gt;
OUT
6 29 94
SB_ODT0
SB_ODT1
BG42
MEM_B_ODT & lt; 0 & gt;
OUT
6 29 94
BH45
MEM_B_ODT & lt; 1 & gt;
OUT
6 29 94
SB_DQS0*
SB_DQS1*
SB_DQS2*
SB_DQS3*
SB_DQS4*
SB_DQS5*
SB_DQS6*
SB_DQS7*
AN4
MEM_B_DQS_N & lt; 0 & gt;
BI
6 28 94
AW2
MEM_B_DQS_N & lt; 1 & gt;
BI
6 28 94
BH9
MEM_B_DQS_N & lt; 2 & gt;
BI
6 28 94
BF15
MEM_B_DQS_N & lt; 3 & gt;
BI
6 28 94
BF51
MEM_B_DQS_N & lt; 4 & gt;
BI
6 28 94
BH57
MEM_B_DQS_N & lt; 5 & gt;
BI
6 28 94
AY63
MEM_B_DQS_N & lt; 6 & gt;
BI
6 28 94
AN62
MEM_B_DQS_N & lt; 7 & gt;
BI
6 28 94
SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7
AN2
MEM_B_DQS_P & lt; 0 & gt;
BI
6 28 94
AW4
MEM_B_DQS_P & lt; 1 & gt;
BI
6 28 94
BF9
MEM_B_DQS_P & lt; 2 & gt;
BI
6 28 94
BH15
MEM_B_DQS_P & lt; 3 & gt;
BI
6 28 94
BH51
MEM_B_DQS_P & lt; 4 & gt;
BI
6 28 94
BF57
MEM_B_DQS_P & lt; 5 & gt;
BI
6 28 94
AY65
MEM_B_DQS_P & lt; 6 & gt;
BI
6 28 94
AN64
MEM_B_DQS_P & lt; 7 & gt;
BI
6 28 94
SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_MA14
SB_MA15
BGA
BF33
SB_CLK1
SB_CLK1*
IVY-BRIDGE
BF31
MEM_B_A & lt; 0 & gt;
OUT
6 29 94
BH31
MEM_B_A & lt; 1 & gt;
OUT
6 29 94
BB37
MEM_B_A & lt; 2 & gt;
OUT
6 29 94
BC34
MEM_B_A & lt; 3 & gt;
OUT
6 29 94
BF27
MEM_B_A & lt; 4 & gt;
OUT
6 29 94
BB33
MEM_B_A & lt; 5 & gt;
OUT
6 29 94
BH27
MEM_B_A & lt; 6 & gt;
OUT
6 29 94
BG30
MEM_B_A & lt; 7 & gt;
OUT
6 29 94
BH29
MEM_B_A & lt; 8 & gt;
OUT
6 29 94
BF29
MEM_B_A & lt; 9 & gt;
OUT
6 29 94
AY37
MEM_B_A & lt; 10 & gt;
OUT
6 29 94
BJ30
MEM_B_A & lt; 11 & gt;
OUT
6 29 94
AW30
MEM_B_A & lt; 12 & gt;
OUT
6 29 94
BA40
MEM_B_A & lt; 13 & gt;
OUT
6 29 94
BB29
MEM_B_A & lt; 14 & gt;
OUT
6 29 94
BE28
MEM_B_A & lt; 15 & gt;
OUT
6 29 94
SB_CLK0
SB_CLK0*
OMIT_TABLE
(4 OF 11)
MEMORY CHANNEL B
7
MEMORY CHANNEL A
8
D
C
B
SB_BS0
SB_BS1
SB_BS2
SB_CAS*
SB_RAS*
SB_WE*
A
SYNC_DATE=06/15/2010
PAGE TITLE
CPU DDR3 INTERFACES
DRAWING NUMBER
Apple Inc.
051-9585
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
3.0.0
BRANCH
PAGE
12 OF 132
SHEET
11 OF 105
1
A
8
7
6
5
4
3
2
1
D
D
=PP3V3_S0_CPU_VCCIO_SEL
7
105 49 14 12 7 =PPVCORE_S0_CPU
=PPVCORE_S0_CPU
CPU:SNB
R1320
1
Pullup for SNB
R46
15 12 7
=PP1V05_S0_CPU_VCCIO
=PPVCCSA_S0_CPU
402
7 9 10 12 13 14
H31
BGA
H29
R36
2
H35
IVY-BRIDGE
R40
5%
MF-LF
U1000
R42
10K
1/16W
(6 OF 11)
CORE POWER
R34
=PP1V05_S0_CPU_VCCIO
PLACE_NEAR=R1310.1:2.54mm
1
R1300
1
75
1/16W
93 69
CPU_VIDSOUT
BI
MF-LF
R1312
402
0
1/16W
2
1
2
5%
93 69
OUT
402
0
1/16W
1
2
5%
IN
CPU_VIDALERT_L
402
2
5%
43
PLACE_NEAR=U1000.B51:38mm
G28
N43
G26
F45
N37
F43
AK63
N33
F41
N30
F37
F35
N24
F31
AT21
N20
F29
AP21
M46
F25
AL21
M42
=PPVCORE_S0_CPU
=PPVCORE_S0_CPU_VCCAXG
7 12 13
15
7 12 14 49
105
7 12 13 15
E44
M40
E40
BJ60
M36
E38
=PP1V8_S0_CPU_VCCPLL_R
AV21
VCCPQE
M12
7 9 10 12 13 14
=PPVCORE_S0_CPU_VCCAXG
N45
N26
M15
7 12 14 49 105
=PP1V05_S0_CPU_VCCIO
G32
AP23
7 15
7 14
VCCSA
N16
M17
C
G34
R21
AK61
VCCPLL
N18
CPU_VIDALERT_L_R
MF-LF
G38
R23
=PP1V5_S3_CPU_VCCDQ
AK65
N14
=PPVCORE_S0_CPU
AV23
G40
N39
T11
1
1/16W
G44
AL23
VCCDQ
T14
CPU_VIDSCLK_R
MF-LF
H25
R29
CPU_VCCIO_SEL
T16
R1310
93 69
AJ8
AT23
OMIT_TABLE
U12
CPU_VIDSOUT_R
R1311
CPU_VIDSCLK
(9 OF 11)
OMIT_TABLE
R27
VCCIO_SEL
U15
402
MF-LF
BGA
U17
1/16W
402
IVY-BRIDGE
W12
PLACE_NEAR=U1000.A50:2.54mm
U1000
W15
1%
MF-LF
2
W17
R1302
130
1%
7 9 10 12 13 14
=PP1V05_S0_CPU_VCCPQE
7 8 14
M11
L18
BJ6
NOSTUFF
R1360
NOSTUFF
1
1
100
PLACE_NEAR=U1000.B47:50.8mm
1%
1/16W
MF-LF
402
PLACE_SIDE=BOTTOM
R1362
100
R1366
R1364
100
NOSTUFF
NOSTUFF
1%
1/16W
1/16W
1
MF-LF
MF
402
2
1%
402
201
PLACE_SIDE=BOTTOM
R1370
1
49.9
1/20W
MF-LF
2
1
49.9
1%
2
D51
NOSTUFF
1
R1368
1/20W
1/16W
MF
2
1%
MF-LF
201
2
402
93 66
93 66
OUT
OUT
CPU_VCCSA_VID & lt; 0 & gt;
AE10
CPU_VCCSA_VID & lt; 1 & gt;
AG10
93 69
OUT
CPU_VCCSENSE_P
B47
93 69
OUT
CPU_VCCSENSE_N
A46
93 69
93 69
93 71
93 71
OUT
CPU_AXG_SENSE_P
F49
OUT
CPU_AXG_SENSE_N
E50
OUT
CPU_VCCIOSENSE_P
AW10
OUT
CPU_VCCIOSENSE_N
AU10
TP_CPU_VDDQSENSEP
AY19
TP_CPU_VDDQSENSEN
AW20
VCCIO_SENSE
VSS_SENSE_VCCIO
PLACE_NEAR=U1000.E50:50.8mm
1
PLACE_SIDE=BOTTOM
R1367
VDDQ_SENSE
VSS_SENSE_VDDQ
100
1%
1/16W
93 66
MF-LF
2
K3
CPU_VCCSASENSE
OUT
NOSTUFF
B
VCCSA_SENSE
402
TP_CPU_DIE_SENSE
F47
CPU_VCC_VALSENSE_P
D47
CPU_VCC_VALSENSE_N
C48
CPU_AXG_VALSENSE_P
B49
CPU_AXG_VALSENSE_N
A48
VCC_DIE_SENSE
VCC_VAL_SENSE
VSS_VAL_SENSE
VAXG_VAL_SENSE
VSSAXG_VAL_SENSE
PLACE_SIDE=BOTTOM
PLACE_NEAR=U1000.A46:50.8mm
PLACE_NEAR=U1000.AU10:50.8mm
PLACE_SIDE=BOTTOM
R1361
1
1
100
NOSTUFF
1%
1/16W
MF-LF
402
R1363
100
1%
PLACE_SIDE=BOTTOM
NOSTUFF
R1314
1
1
R1313
1/16W
MF-LF
2
2
R1365
402
10K
1
1
49.9
NOSTUFF
1%
1%
MF
201
5%
1/16W
1/16W
MF-LF
49.9
1/20W
10K
5%
R1371
PLACE_SIDE=BOTTOM
MF-LF
402
402
2
NOSTUFF
2
1/20W
D37
F1
L34
D35
L32
D31
L28
D29
L26
C44
B5
L22
C40
A60
K45
C38
K43
C34
K41
DC_TEST_A4
DC_TEST_A62
DC_TEST_A64
DC_TEST_B3
DC_TEST_B63
DC_TEST_B65
DC_TEST_BF1
DC_TEST_BF65
DC_TEST_BG2
DC_TEST_BG64
DC_TEST_BH1
DC_TEST_BH3
DC_TEST_BH63
DC_TEST_BH65
DC_TEST_BJ2
DC_TEST_BJ4
DC_TEST_BJ62
DC_TEST_BJ64
DC_TEST_C2
DC_TEST_C64
DC_TEST_D1
DC_TEST_D65
D41
L38
E2
VAXG_SENSE
VSSAXG_SENSE
L40
E64
VCC_SENSE
VSS_SENSE
L44
F65
VSS_NCTF
M21
BD1
(IPU)
PLACE_NEAR=U1000.F49:50.8mm
E28
M23
BE2
VCCSA_VID0
VCCSA_VID1
M27
BE64
100
1%
2
B51
VIDSOUT
VIDSCLK
VIDALERT*
E32
BH5
BD65
A50
PLACE_NEAR=U1000.AW10:50.8mm
C32
K37
C28
K35
C26
K31
B45
K29
B43
B63
K25
B41
B65
DC_TEST_B65_C64
J44
B37
BF1
TP_DC_TEST_BF1
J40
B35
BF65
TP_DC_TEST_BF65
J38
B31
6 DC_TEST_BH1_BG2
J34
B29
J32
A44
J28
A40
J26
C
E34
A6
PLACE_SIDE=BOTTOM
7 12
15
M29
B61
=PPVCCSA_S0_CPU
M34
BH61
L14
PLACE_SIDE=BOTTOM
PLACE_SIDE=BOTTOM
7 12 14 49 105
A38
A4
TP_DC_TEST_A4
A62
TP_DC_TEST_A62
A64
DC_TEST_B63_A64
B3
BG2
BG64
6
6 DC_TEST_B3_C2
DC_TEST_BG64_BH65
BH1
BH3
6 DC_TEST_BH3_BJ2
E26
D45
VCC
VCC
D43
H45
A34
BH65
H43
A32
BJ2
H41
A28
H37
B
A26
BH63
DC_TEST_BJ64_BH63
BJ4
TP_DC_TEST_BJ4
BJ62
TP_DC_TEST_BJ62
BJ64
C2
C64
D1
TP_DC_TEST_D1
D65
TP_DC_TEST_D65
6
MF
2
2
201
NOTE: Intel validation sense lines per doc 439028 rev1.0
HR_PPDG sections 6.2.1 and 6.3.1.
A
SYNC_MASTER=K92_MLB
SYNC_DATE=08/03/2010
PAGE TITLE
CPU POWER
DRAWING NUMBER
Apple Inc.
051-9585
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
3.0.0
BRANCH
PAGE
13 OF 132
SHEET
12 OF 105
1
A
8
7
6
5
BJ56
U1000
AW16
AG12
U1000
IVY-BRIDGE
AV65
AF65
IVY-BRIDGE
AV63
AF63
BGA
AF61
(11 OF 11)
BJ32
AV57
AF11
K39
BJ24
AV50
AF9
K33
BJ20
AV44
AF5
K27
BJ16
AV38
AE57
K1
BJ12
AV31
AD16
J64
BJ8
AV25
AD14
J60
BG60
OMIT_TABLE
BJ40
D
1
L12
AV59
2
L16
BGA
3
L20
BJ52
BJ48
4
(10 OF 11)
OMIT_TABLE
L8
D
=PPVCORE_S0_CPU_VCCAXG
=PP1V5_S3_CPU_VCCDDR
15 12 7
7 10 15 26
AV19
AD7
J56
BG56
AV9
AD3
J52
AH65
U1000
BJ36
BG52
AV5
AD1
J48
AH63
IVY-BRIDGE
BJ28
BG48
AU54
AC64
J46
AH61
BGA
BG40
BG44
AU47
AC62
J42
AH58
(8 OF 11)
BG36
AU41
AC60
J36
AH56
BD47
BG28
AU35
AC57
J30
AG64
BD43
OMIT_TABLE
BG32
=PP1V05_S0_CPU_VCCIO
=PP1V05_S0_CPU_VCCIO
14 13 12 10 9 7
7 9 10 12 13 14
AV55
AU28
AB11
J24
AG62
BD39
BG20
AU22
AB9
J22
AG60
BD31
BG16
AU16
AB5
J18
AF58
AN20
AV53
BG24
U1000
BD23
AU14
J14
AA57
AF56
AN18
BGA
AN16
AV17
BG12
IVY-BRIDGE
AV48
(7 OF11)
IO POWER
BB35
AV15
BG8
AT61
AA17
J10
AE64
AT57
AA15
J6
AE62
AN14
AM11
AY47
BF5
OMIT_TABLE
AY43
AV12
AL17
AU49
AL15
AU20
AL12
AU18
AK58
AT55
AK56
AT53
AJ17
AT48
AE60
H39
AA12
AL48
AU52
AT50
AL53
AU56
BE62
AL55
AU58
AJ15
AY39
BE58
AT44
Y65
H33
AD65
AY35
BE54
AT38
Y63
H27
AD63
AY31
BE50
AT31
Y61
H3
AD61
AY27
BE46
AT25
Y7
AD58
G62
AY23
BE42
AT19
Y3
G58
AD56
AV46
BE38
AT11
Y1
G54
AB65
AV42
BE34
AT7
W57
AB63
G50
AV40
BE30
AT3
V16
G46
AB61
AV36
BE26
AT1
V14
G42
AB58
AV34
BE22
AR54
V11
G36
AB56
AV29
AT17
AT15
AJ12
VCCIO
VCCIO
AH16
BE18
AR47
V9
AF16
AF14
AR49
AE17
AR20
AE15
AR18
AE12
AR16
AD11
AR14
AC17
AP55
AC15
AP53
AC12
AP48
AB16
AV27
AR41
V5
G24
AA62
AU45
AR35
U64
G20
AA60
AU43
AR28
U62
G16
Y58
BD7
AR22
U60
G12
Y56
BD3
AP65
U57
G8
W64
BC60
AP63
T7
F39
W62
BC56
AP57
VSS
VSS
T3
F33
W60
BC52
AP50
T1
F27
V65
BC48
AP44
R57
E60
V63
AP38
R50
E56
V61
BC44
VSS
BC40
VSS
AP31
E52
R44
VAXG
AU39
IO POWER DDR3
BD35
GRAPHIC CORE POWER
BE14
BE10
AU37
AU33
AU30
AU26
AU24
AT46
AT42
V58
AT40
AN58
R38
E48
V56
BC32
AP19
R31
E46
T65
VDDQ
AB14
Y16
Y14
AN49
AP25
AN56
AN52
BC36
Y11
AT36
AT34
BC28
AP17
R25
E42
T63
AT29
BC26
AP15
R19
E36
T61
AT27
BC24
AP12
R17
E30
T58
AR45
BC20
AP11
R15
E24
T56
AR43
BC16
AP9
R12
E22
R64
AR39
BC12
AP5
P65
E18
R62
AR37
BB65
AN54
P63
E14
R60
AR33
BB63
AN47
P61
E10
R55
AR30
BB47
AN41
P11
E6
R53
AR26
BB39
AN35
P9
E4
R48
AR24
BB9
AN28
P5
D63
N64
AP46
BB5
AN22
N54
D39
N62
AP42
BA58
AM61
N47
D33
N60
AP40
BA54
AM7
N41
D27
N58
AP36
BA50
AM3
N35
C58
N56
AP34
BA46
AM1
N28
C54
N52
AP29
BA42
AL57
N22
C50
N49
AP27
BA38
AL50
M57
C46
M65
AN45
BA34
AL44
M50
C42
M63
AN43
BA30
AL38
M44
C36
M61
AN39
BA26
AL31
M38
C30
M59
AN37
BA22
AL25
M31
C20
M55
AN33
BA18
AL19
M25
C16
M53
AN30
BA14
AK16
M19
C12
M48
AN26
AY61
AK14
M7
C8
L56
AN24
AY11
AK11
M3
B39
L52
AL46
AY7
AK9
M1
B33
L48
AL42
AY3
AK5
L64
B27
AL40
AY1
AJ64
L62
A56
AL36
AW56
AJ62
L60
A52
AL34
AW52
AJ60
L58
A42
AL29
AW48
AJ57
L54
A36
AL27
AW44
AH7
L50
A30
AW40
AH3
L46
A24
AW36
AH1
L42
A20
AW32
AG57
L36
A16
AW28
AG17
L30
A12
AW24
B
C
AH11
AR52
AA64
G30
AH14
AR58
AR56
C
AT12
AG15
L24
A8
B
A
A
PAGE TITLE
CPU POWER AND GND
DRAWING NUMBER
Apple Inc.
051-9585
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
3.0.0
BRANCH
PAGE
14 OF 132
SHEET
13 OF 105
1
8
7
6
5
4
3
2
1
CPU VCORE DECOUPLING
Intel recommendation: 4x 470uF 4mOhm, 16x 22uF 0805, 4x 10uF 0603, 20x 1uF 0402, 8x 1uF 0402 (NOSTUFF)
Apple Implementation: 4x 470uF 4mOhm, 1x 470uF 4mOhm (NOSTUFF), 16x 22uF 0603, 4x 10uF 0402, 20x 1uF 0402, 28x 1uF 0201 (NOSTUFF), 4x 22uF 0603 (NOSTUFF)
PLACEMENT_NOTE (C1600-C16C7):
105 49 12 7
=PPVCORE_S0_CPU
Place on bottom side of U1000
U100.
C1600
1
1
C1601
C1602
1
1
C1603
1
C1604
C1605
1
C1606
1
C1607
1
C1608
1
C1609
1
1
C1610
1
C1611
1
C1612
1
C1613
1
C1614
1
C1615
1
C1616
1
C1617
1
C1618
1UF
D
2
1UF
1UF
1UF
1UF
1UF
1UF
1UF
1UF
1UF
1UF
1UF
1UF
1UF
1UF
1UF
1UF
1UF
10%
10V
X5R
402
10%
10V
X5R
402
10%
10V
X5R
402
10%
10V
X5R
402
10%
10V
X5R
402
10%
10V
X5R
402
10%
10V
X5R
402
10%
10V
X5R
402
10%
10V
X5R
402
10%
10V
X5R
402
10%
10V
X5R
402
10%
10V
X5R
402
10%
10V
X5R
402
10%
10V
X5R
402
10%
10V
X5R
402
10%
10V
X5R
402
10%
10V
X5R
402
10%
10V
X5R
402
2
NOSTUFF
NOSTUFF
1
NOSTUFF
1
C16C0
1UF
20%
6.3V
X5R
0201
2
2
NOSTUFF
1
C16C2
1UF
20%
6.3V
X5R
0201
20%
6.3V
X5R
0201
2
20%
6.3V
X5R
0201
2
NOSTUFF
1
20%
6.3V
X5R
0201
1
1UF
20%
6.3V
X5R
0201
2
NOSTUFF
C16A9
2
NOSTUFF
C16B0
1
1UF
20%
6.3V
X5R
0201
2
2
NOSTUFF
C16B1
1
1UF
20%
6.3V
X5R
0201
2
2
C16B2
NOSTUFF
1
1UF
20%
6.3V
X5R
0201
2
2
NOSTUFF
C16B3
1
1UF
20%
6.3V
X5R
0201
2
2
NOSTUFF
C16B4
1
1UF
20%
6.3V
X5R
0201
2
2
NOSTUFF
C16B5
1
1UF
20%
6.3V
X5R
0201
2
2
NOSTUFF
C16B6
1
1UF
20%
6.3V
X5R
0201
2
2
NOSTUFF
C16B7
1
1UF
20%
6.3V
X5R
0201
2
1UF
NOSTUFF
C16B8
1
1UF
20%
6.3V
X5R
0201
2
D
10%
10V
X5R
402
2
C16B9
1UF
20%
6.3V
X5R
0201
2
20%
6.3V
X5R
0201
1UF
20%
6.3V
X5R
0201
2
1
1UF
2
C16C7
1UF
20%
6.3V
X5R
0201
2
NOSTUFF
C16A8
1
2
NOSTUFF
1
C16C6
1UF
20%
6.3V
X5R
0201
2
2
2
NOSTUFF
C16A7
1UF
NOSTUFF
1
C16C5
1UF
1
20%
6.3V
X5R
0201
2
2
NOSTUFF
C16A6
1UF
20%
6.3V
X5R
0201
C16C4
1UF
1
1UF
2
2
NOSTUFF
C16A5
NOSTUFF
1
C16C3
1UF
1
20%
6.3V
X5R
0201
2
2
NOSTUFF
C16A4
1UF
20%
6.3V
X5R
0201
2
NOSTUFF
1
C16C1
1
1UF
20%
6.3V
X5R
0201
2
2
NOSTUFF
C16A3
1
1UF
20%
6.3V
X5R
0201
2
2
NOSTUFF
C16A2
1
1UF
20%
6.3V
X5R
0201
2
NOSTUFF
C16A1
1
1UF
2
2
NOSTUFF
C16A0
1
C1619
1
1UF
10%
10V
X5R
402
20%
6.3V
X5R
0201
2
PLACEMENT_NOTE (C1620-C1623):
Place near U1000 on bottom side
CRITICAL
CRITICAL
C1620
1
CRITICAL
C1621
1
C
10UF
20%
6.3V
CERM-X5R
0402-1
1
20%
6.3V
CERM-X5R
0402-1
C1623
10UF
20%
6.3V
CERM-X5R
0402-1
2
CRITICAL
C1622
1
10UF
2
2
10UF
20%
6.3V
CERM-X5R
0402-1
2
C
PLACEMENT_NOTE (C1624-C16D5):
Place near inductors on inductors on inductors on bottom side.
Place near bottom side. bottom side.
Place near
CRITICAL
1
CRITICAL
C1624
1
22UF
1
2
C1626
1
22UF
22UF
20%
6.3V
X5R-CERM1
0603
2
CRITICAL
CRITICAL
C1625
20%
6.3V
X5R-CERM1
0603
2
C1628
1
22UF
20%
6.3V
X5R-CERM1
0603
2
CRITICAL
CRITICAL
C1627
1
22UF
20%
6.3V
X5R-CERM1
0603
1
22UF
20%
6.3V
X5R-CERM1
0603
2
CRITICAL
C1629
2
1
22UF
20%
6.3V
X5R-CERM1
0603
2
CRITICAL
CRITICAL
C1630
C1631
1
22UF
20%
6.3V
X5R-CERM1
0603
2
CRITICAL
C1632
1
22UF
20%
6.3V
X5R-CERM1
0603
2
CRITICAL
C1633
1
22UF
20%
6.3V
X5R-CERM1
0603
2
CRITICAL
C1634
1
22UF
20%
6.3V
X5R-CERM1
0603
2
CRITICAL
C1635
1
22UF
20%
6.3V
X5R-CERM1
0603
2
C1636
CRITICAL
1
22UF
20%
6.3V
X5R-CERM1
0603
2
20%
6.3V
X5R-CERM1
0603
C1637
CRITICAL
1
CRITICAL
1
22UF
22UF
2
C1638
20%
6.3V
X5R-CERM1
0603
2
20%
6.3V
X5R-CERM1
0603
NOSTUFF
C1639
1
22UF
2
C16D0
NOSTUFF
1
22UF
20%
6.3V
X5R-CERM1
0603
2
20%
6.3V
X5R-CERM1
0603
NOSTUFF
C16D1
1
22UF
2
NOSTUFF
C16D2
1
22UF
20%
6.3V
X5R-CERM1
0603
2
C16D3
NOSTUFF
1
22UF
20%
6.3V
X5R-CERM1
0603
2
20%
6.3V
X5R-CERM1
0603
NOSTUFF
C16D4
1
22UF
2
C16D5
22UF
20%
6.3V
X5R-CERM1
0603
2
20%
6.3V
X5R-CERM1
0603
PLACEMENT_NOTE (C1640-C1645):
Place near inductors on bottom side.
NOSTUFF
1
CRITICAL
1
C1640
3
2
CRITICAL
C1641
1
470UF-4MOHM
470UF-4MOHM
20%
3 2 2.0V
POLY-TANT
D2T-SM1
20%
2.0V
POLY-TANT
D2T-SM
CRITICAL
C1642
1
470UF-4MOHM
CRITICAL
C1643
1
470UF-4MOHM
20%
3 2 2.0V
POLY-TANT
D2T-SM1
3
20%
2 2.0V
POLY-TANT
D2T-SM1
C1644
470UF-4MOHM
3
20%
2 2.0V
POLY-TANT
D2T-SM1
CPU VCCIO/VCCPQ DECOUPLING
Intel recommendation: 2x 330uF, 10x 10uF 0603, 26x 1uF 0402
Apple Implementation: 2x 330uF, 10x 10uF 0603, 26x 1uF 0402
PLACEMENT_NOTE (C1646-C1671):
13 12 10 9 7
=PP1V05_S0_CPU_VCCIO
B
CPU VCCPLL DECOUPLING
Place on bottom side of U1000
U100.
R1600
1
C1646
1
C1647
C1648
1
1
C1649
1
C1650
1
C1651
1
C1652
1
C1653
1
C1654
1
C1655
1
C1656
1
C1657
1
C1658
1UF
2
1UF
1UF
1UF
1UF
1UF
1UF
1UF
1UF
1UF
1UF
1UF
1UF
10%
10V
X5R
402
10%
10V
X5R
402
10%
10V
X5R
402
10%
10V
X5R
402
10%
10V
X5R
402
10%
10V
X5R
402
10%
10V
X5R
402
10%
10V
X5R
402
10%
10V
X5R
402
10%
10V
X5R
402
10%
10V
X5R
402
10%
10V
X5R
402
2
2
2
2
2
2
2
2
2
2
2
2
=PP1V8_S0_CPU_VCCPLL_R
B
7 12
0
7 =PP1V8_S0_CPU_VCCPLL
10%
10V
X5R
402
1
2
5%
1/16W
MF-LF
402
CRITICAL
1
1
C1686
1UF
2
PLACE_NEAR=U1000.AK63:2.54 mm:NO_VIA
C1685
10%
10V
X5R
402
1
2
C1687
330UF-0.006OHM
1UF
10%
10V
X5R
402
2
20%
2V
POLY
CASE-D2-SM
PLACE_NEAR=U1000.AK61:5 mm
PLACE_NEAR=U1000.AK65:2.54 mm:NO_VIA
1
C1659
1
C1660
1UF
2
C1661
1
1UF
10%
10V
X5R
402
10%
10V
X5R
402
2
1
1UF
1
1UF
10%
10V
X5R
402
2
C1662
2
C1663
1
1UF
10%
10V
X5R
402
2
C1664
1
1UF
10%
10V
X5R
402
2
C1665
1
1UF
10%
10V
X5R
402
2
C1666
1
1UF
10%
10V
X5R
402
2
C1667
1
1UF
10%
10V
X5R
402
2
C1668
1
1UF
10%
10V
X5R
402
2
10%
10V
X5R
402
C1669
1
1UF
2
10%
10V
X5R
402
C1670
1
1UF
2
10%
10V
X5R
402
C1671
CPU VCCPLL Low pass filter
1UF
2
10%
10V
X5R
402
PLACEMENT_NOTE (C1672-C1681):
Place near U1000 on bottom side
CRITICAL
1
CRITICAL
C1672
1
CRITICAL
C1673
1
CRITICAL
C1674
1
C1675
CRITICAL
1
C1676
CRITICAL
1
C1677
CRITICAL
1
C1678
CRITICAL
1
CRITICAL
C1679
1
C1680
10UF
2
10UF
10UF
10UF
10UF
10UF
10UF
10UF
20%
6.3V
X5R
603
20%
6.3V
X5R
603
20%
6.3V
X5R
603
20%
6.3V
X5R
603
20%
6.3V
X5R
603
20%
6.3V
X5R
603
20%
6.3V
X5R
603
20%
6.3V
X5R
603
20%
6.3V
X5R
603
CRITICAL
1
10UF
2
2
2
2
2
2
2
2
C1681
10UF
2
20%
6.3V
X5R
603
Place near inductors on bottom side
CRITICAL
1
C1682
1
330UF-0.006OHM
A
2
C1683
330UF-0.006OHM
20%
2V
POLY
CASE-D2-SM
2
20%
2V
POLY
CASE-D2-SM
SYNC_MASTER=K92_MLB
CRITICAL
SYNC_DATE=08/19/2010
PAGE TITLE
CPU DECOUPLING-I
Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402
DRAWING NUMBER
R1601
1
0.010
2
Apple Inc.
=PP1V05_S0_CPU_VCCPQE
1%
1/4W
MF
0603
1
R
NOTICE OF PROPRIETARY PROPERTY:
C1684
1UF
2
8
7 8 12
7
051-9585
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
10%
10V
X5R
402
6
5
4
3
2
SIZE
D
REVISION
3.0.0
BRANCH
PAGE
16 OF 132
SHEET
14 OF 105
1
A
8
7
6
5
4
3
2
1
VAXG DECOUPLING
Intel recommendation: 2x 470uF 4mOhm, 2x 470uF 4mOhm (NOSTUFF), 6x 22uF 0805, 2x 22uF 0805 (NOSTUFF), 8x 10uF 0603, 2x 10uF 0603 (NOSTUFF), 9x 1uF 0402, 9x 1uF 0402 (NOSTUFF)
Apple Implementation: 2x 470uF 4mOhm, 1x 470uF 4mOhm (NOSTUFF), 6x 22uF 0603, 2x 22uF 0603 (NOSTUFF), 6x 10uF 0402, 2x 10uF 0402 (NOSTUFF), 9x 1uF 0402, 9x 1uF 0402 (NOSTUFF)
PLACEMENT_NOTE (C1700-C1708):
13 12 7
=PPVCORE_S0_CPU_VCCAXG
Place on bottom side of U1000
U100.
D
NOSTUFF
1
C1700
1
1UF
2
C1701
1
1UF
10%
10V
X5R
402
2
C1702
1
1UF
10%
10V
X5R
402
2
C1703
C1704
1
1UF
10%
10V
X5R
402
10%
10V
X5R
402
2
C1705
1
1UF
10%
10V
X5R
402
2
1
C1706
1UF
10%
10V
X5R
402
2
1
C1707
1UF
10%
10V
X5R
402
2
1
1UF
1
1UF
10%
10V
X5R
402
2
C1708
2
NOSTUFF
C1709
1
1UF
10%
10V
X5R
402
2
C1710
NOSTUFF
1
1UF
10%
10V
X5R
402
2
C1711
NOSTUFF
1
1UF
10%
10V
X5R
402
2
10%
10V
X5R
402
C1712
NOSTUFF
1
C1713
1UF
2
10%
10V
X5R
402
NOSTUFF
1
1UF
1
1UF
10%
10V
X5R
402
2
NOSTUFF
C1714
2
NOSTUFF
C1715
1
1UF
10%
10V
X5R
402
2
1
1UF
10%
10V
X5R
402
2
D
NOSTUFF
C1716
C1717
1UF
10%
10V
X5R
402
2
10%
10V
X5R
402
PLACEMENT_NOTE (C1718-C1723):
Place close to U1000 on bottom side
NOSTUFF
C1718
1
1
10UF
C1720
1
10UF
20%
6.3V
CERM-X5R
0402-1
2
C1719
2
C1721
1
10UF
20%
6.3V
CERM-X5R
0402-1
20%
6.3V
CERM-X5R
0402-1
2
C1722
1
10UF
20%
6.3V
CERM-X5R
0402-1
2
C1723
1
10UF
20%
6.3V
CERM-X5R
0402-1
2
1
10UF
1
10UF
20%
6.3V
CERM-X5R
0402-1
2
NOSTUFF
C1724
2
C1725
10UF
20%
6.3V
CERM-X5R
0402-1
2
20%
6.3V
CERM-X5R
0402-1
PLACEMENT_NOTE (C1726-C1731):
Place near inductors on bottom side.
NOSTUFF
1
C1726
1
22UF
2
C1727
1
22UF
20%
6.3V
X5R-CERM1
0603
2
C1728
1
22UF
20%
6.3V
X5R-CERM1
0603
2
C1729
1
22UF
20%
6.3V
X5R-CERM1
0603
2
C1730
1
22UF
20%
6.3V
X5R-CERM1
0603
2
C1731
1
20%
6.3V
X5R-CERM1
0603
2
NOSTUFF
C1732
22UF
1
C1733
22UF
20%
6.3V
X5R-CERM1
0603
2
22UF
20%
6.3V
X5R-CERM1
0603
2
20%
6.3V
X5R-CERM1
0603
PLACEMENT_NOTE (C1734-C1735):
NOSTUFF
C
CRITICAL
1
CRITICAL
C1734
1
470UF-4MOHM
20%
2 2.0V
POLY-TANT
D2T-SM1
3
1
470UF-4MOHM
3
C
CRITICAL
C1735
20%
2 2.0V
POLY-TANT
D2T-SM1
C1737
470UF-4MOHM
20%
2 2.0V
POLY-TANT
D2T-SM1
3
CPU VCCSA DECOUPLING
CPU VDDQ/VCCDQ DECOUPLING
Intel recommendation: 1x 330uF, 3x 10uF 0603, 3x 1uF 0402
Apple Implementation: 1x 330uF, 5x 10uF 0603, 5x 1uF 0402
Intel recommendation: 1x 330uF, 8x 10uF 0603, 10x 1uF 0402
Apple Implementation: 1x 330uF, 8x 10uF 0603, 10x 1uF 0402
PLACEMENT_NOTE (C1758-C1762):
PLACEMENT_NOTE (C1738-C1747):
26 13 10 7
=PP1V5_S3_CPU_VCCDDR
Place on bottom side of U1000
U100.
1
C1738
1
1UF
C1739
1UF
10%
10V
X5R
402
2
12 7
1
2
C1740
1
1UF
10%
10V
X5R
402
2
C1741
1
1UF
10%
10V
X5R
402
2
10%
10V
X5R
402
C1742
1
1UF
2
10%
10V
X5R
402
C1743
1
1UF
2
C1744
1
1UF
10%
10V
X5R
402
2
C1745
1
1UF
10%
10V
X5R
402
2
10%
10V
X5R
402
C1746
1
1UF
2
10%
10V
X5R
402
=PPVCCSA_S0_CPU
Place on bottom side of U1000
U100.
C1747
1
1UF
2
C1758
1
C1759
1
C1760
1
C1761
1UF
10%
10V
X5R
402
2
1UF
1UF
10%
10V
X5R
402
10%
10V
X5R
402
10%
10V
X5R
402
1
1UF
10%
10V
X5R
402
2
2
2
C1762
1UF
2
10%
10V
X5R
402
Place close to U1000 on bottom side
1
C1748
1
10UF
B
C1749
1
C1750
10UF
20%
6.3V
X5R
603
2
2
1
10UF
20%
6.3V
X5R
603
2
C1751
1
10UF
20%
6.3V
X5R
603
2
20%
6.3V
X5R
603
C1752
1
10UF
2
20%
6.3V
X5R
603
C1753
1
10UF
2
20%
6.3V
X5R
603
C1754
1
10UF
2
C1755
10UF
20%
6.3V
X5R
603
2
20%
6.3V
X5R
603
1
1
C1764
1
C1765
1
C1766
10UF
2
Place near inductors on bottom side
1
C1763
10UF
10UF
20%
6.3V
X5R
603
20%
6.3V
X5R
603
20%
6.3V
X5R
603
1
10UF
20%
6.3V
X5R
603
2
2
2
C1767
10UF
2
B
20%
6.3V
X5R
603
C1756
330UF-0.006OHM
2
20%
2V
POLY
CASE-D2-SM
1
C1768
330UF-0.006OHM
2
20%
2V
POLY
CASE-D2-SM
Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402
R1700
1
0.010
1%
1/4W
MF
0603
2
=PP1V5_S3_CPU_VCCDQ
1
7 12
C1757
1UF
2
10%
10V
X5R
402
A
SYNC_MASTER=K92_MLB
SYNC_DATE=08/19/2010
PAGE TITLE
CPU DECOUPLING-II
DRAWING NUMBER
Apple Inc.
051-9585
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
3.0.0
BRANCH
PAGE
17 OF 132
SHEET
15 OF 105
1
A
7
6
5
4
3
2
OMIT_TABLE
C20
C38
D36
LPC_FRAME_R_L
(IPU) LDRQ0*
LDRQ1*/GPIO23
(IPU)
SERIRQ
E36
TP_LPC_DREQ0_L
TBT_PWR_EN_PCH
PANTHERPOINT
MOBILE
FCBGA
(1 OF 10)
16
D20
RTC_RESET_L
RTCRST*
D
PCH_SRTCRST_L
G22
SRTCRST*
16
PCH_INTRUDER_L
K22
INTRUDER*
16
C17
PCH_INTVRMEN_L
RTC
LPC
16
INTVRMEN
LPC_AD_R & lt; 0 & gt;
LPC_AD_R & lt; 1 & gt;
LPC_AD_R & lt; 2 & gt;
LPC_AD_R & lt; 3 & gt;
A38
B37
C37
16
96 36
IN
16
96 36
IN
=PP3V3_S0_PCH
16
V5
96 36
16
10K
5%
1/20W
MF
2 201
6
OUT
24
LPC_SERIRQ
OUT
96 32
R1820
OUT
96 36
1
K36
7 22
16
IN
96 32
IN
96 32
OUT
96 32
OUT
6 45 47
BI
96 38
IN
96 38
96 16
96 16
HDA_BIT_CLK_R
N34
HDA_SYNC_R
L34
HDA_SYNC (IPD-BOOT)
T10
SPKR (IPD-PLTRST#)
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
HDA_BCLK
VSel strap not functional (VCCVRM = 1.8V)
96 57
IN
6
6
6
24 16
E34
HDA_SDIN0
TP_HDA_SDIN1
TP_HDA_SDIN2
TP_HDA_SDIN3
G34
C34
A34
HDA_RST*
HDA_SDIN0
HDA_SDIN1
HDA_SDIN2
HDA_SDIN3
(IPD)
(IPD)
(IPD)
(IPD)
OUT
IN
HDA_SDOUT_R
A36
HDA_SDO (IPD-BOOT)
C36
HDA_DOCK_EN*/GPIO33
HDA_DOCK_RST*/GPIO13
N32
XDP_PCH_TCK
J3
IN
JTAG_TCK (IPD)
23
XDP_PCH_TMS
H7
IN
JTAG_TMS (IPU)
C
23
96 47
96 47
XDP_PCH_TDI
IN
OUT
K5
XDP_PCH_TDO
H1
T3
OUT
SPI_CLK_R
OUT
SPI_CS0_R_L
Y14
TP_SPI_CS1_L
96 47
96 47
OUT
T1
SPI_MOSI_R
V4
U3
SPI_MISO
IN
JTAG_TDI (IPU)
JTAG_TDO
SPI_CS1*
AM8
AP10
AH5
AH4
AB8
1
OUT
96 38
OUT
41 95
OUT
41 95
8
AF3
AF1
Y7
Y3
SATAICOMPO
SATAICOMPI
SATA3RCOMPO
SATA3COMPI
SATA3RBIAS
SPI_MOSI (IPD-BOOT)
SPI_MISO (IPU)
IN
8
IN
IN
41 95
8
OUT
8
OUT
IN
41 95
OUT
OUT
PCIE_AP_D2R_N
PCIE_AP_D2R_P
PCIE_AP_R2D_C_N
PCIE_AP_R2D_C_P
BE34
PCIE_FW_D2R_N
PCIE_FW_D2R_P
PCIE_FW_R2D_C_N
PCIE_FW_R2D_C_P
BG36
Y5
AD3
AD1
41 95
AB3
AB1
Y11
95
6
=PP1V05_S0_PCH_VCCIO_SATA
7 20 22
6
AY32
BJ36
AV34
AU34
R1800
1
330K
1M
5%
1/20W
MF
201 2
BB34
BG40
1
6
R1830
BE38
37.4
1%
1/20W
MF
2 201
6
6
6
=PP1V05_S0_PCH
7 22
6
96 36
PCH_SATAICOMP
96 36
R1831
OUT
BH37
AY36
BB36
BG38
AU36
AV36
BJ40
AY40
BB40
OUT
16
1%
1/20W
MF
201
AY38
PCIECLKRQ0_L_GPIO73
J2
96 38
OUT
96 38
PLACE_NEAR=U1800.AB12:2.54mm
PCH_SATA3COMP
PCH_SATA3RBIAS
AW38
Y40
OUT
IN
Y39
AB49
PCIE_CLK100M_FW_N
PCIE_CLK100M_FW_P
39 16
2
BC38
PCIE_CLK100M_ENET_N
PCIE_CLK100M_ENET_P
FW_CLKREQ_L
PCIE_CLK100M_AP_N
PCIE_CLK100M_AP_P
AB47
M1
SATA0GP/GPIO21
SATA1GP/GPIO19
(IPU)
P1
V14
PCH_SATALED_L
1
OUT
OUT
23
23
R1832
96 32
OUT
750
16
XDP_DC2_PCH_GPIO21_DP_AUXCH_ISOL
XDP_DC3_PCH_GPIO19_SATARDRVR_EN
96 32
OUT
5%
1/20W
MF
2 201
32 16
AA48
AA47
IN
AP_CLKREQ_L
V10
Y37
96 8
OUT
20K
96 8
OUT
PCIE_CLK100M_EXCARD_N
PCIE_CLK100M_EXCARD_P
5%
1/20W
MF
2 201
IN
EXCARD_CLKREQ_L
16
RTC_RESET_L
PCH_SRTCRST_L
PCH_INTRUDER_L
PCH_INTVRMEN_L
C1802
1
1
2
2
1UF
10%
10V
X5R
402
6
16
16
C1803
16
16
10%
10V
X5R
402
16
LPC_AD_R & lt; 0 & gt;
LPC_AD_R & lt; 1 & gt;
LPC_AD_R & lt; 2 & gt;
LPC_AD_R & lt; 3 & gt;
LPC_FRAME_R_L
R1860
R1861
R1862
R1863
R1864
33
33
33
33
33
1
OUT
1
2
1
2
16
1
2
1
2
1
5%
1/20W
MF
201
5%
1/20W
MF
201
1/20W
MF
201
5%
1/20W
MF
201
1/20W
MF
OUT
6 45 47 89 96
OUT
57 96
BI
2
6 45 47 89 96
BI
6 45 47 89 96
BI
96 16
96 16
96 24 16
33
HDA_BIT_CLK_R
R1810
PLACE_NEAR=U1800.N34:1.27mm
33
HDA_SYNC_R
R1811
PLACE_NEAR=U1800.L34:1.27mm
33
HDA_RST_R_L
R1812
PLACE_NEAR=U1800.K34:1.27mm
33
HDA_SDOUT_R
R1813
PLACE_NEAR=U1800.A36:1.27mm
IN
6
5%
1/20W
MF
201
1
1/20W
MF
1/20W
MF
Y36
A8
4.7K
10K
57 96
201
2
JTAG_TBT_TMS
10K
10K
1
1
2
R1842
R1869
R1844
R1845
R1847
R1814
R1815
10K
10K
10K
10K
10K
10K
10K
1
1
2
10K
10K
10K
10K
10K
10K
1
1/20W
MF
OUT
201
1
2
10K
1
5%
1/20W
MF
201
1/20W
MF
1/20W
MF
201
1
2
2
2
1
2
1
2
2
1
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
2
1
2
1
2
5%
1/20W
MF
201
5%
1
1/20W
MF
1/20W
MF
201
PCH_SPKR
PCH_SATALED_L
ITPCPU_CLK100M_N
MF
201
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
1/20W
MF
MF
16
NO STUFF
R1841
DP_AUXCH_ISOL
SATARDRVR_EN
FW_CLKREQ_L
AP_CLKREQ_L
EXCARD_CLKREQ_L
JTAG_DPMUXUC_TRST_L
ENET_CLKREQ_L
PEG_CLKREQ_L
TBT_CLKREQ_L
23 87
93 10
ITPCPU_CLK100M_P
1
48 96
48 96
M16
D
48 96
OUT
16
OUT
48 96
BI
M7
TP_CLINK_CLK
T11
TP_CLINK_DATA
6
CL_RST1*
P10
TP_CLINK_RESET_L
48 96
6
(IPU/IPD) CL_DATA1
6
16
(IPU/IPD) CL_CLK1
M10
PEGCLKRQA_L_GPIO47
AB37
TP_PCIE_CLK100M_PEGAN
TP_PCIE_CLK100M_PEGAP
CLKOUT_DMI_N
CLKOUT_DMI_P
AV22
CLKOUT_DP_N
CLKOUT_DP_P
AM12
PERN8
PERP8
PETN8
PETP8
CLKOUT_PCIE0N
Controlled by PCIECLKRQ5#
CLKOUT_PCIE0P
CLKIN_DMI_N
PCIECLKRQ0*/GPIO73
CLKIN_DMI_P
CLKOUT_PCIE1N
CLKOUT_PCIE1P
CLKIN_GND1_N
CLKIN_GND1_P
PCIECLKRQ1*/GPIO18
CLKOUT_PCIE2N
CLKOUT_PCIE2P
AB38
DMI_CLK100M_CPU_N
DMI_CLK100M_CPU_P
AM13
BF18
OUT
10 93
OUT
10 93
TP_PCH_CLKOUT_DPN
TP_PCH_CLKOUT_DPP
AU22
OUT
8
OUT
8
PCIE_CLK100M_PCH_N
PCIE_CLK100M_PCH_P
C
16 96
IN
16 96
IN
16 96
IN
16 96
PCH_CLK100M_SATA_N
PCH_CLK100M_SATA_P
IN
16 96
IN
16 96
PCH_CLK14P3M_REFCLK
IN
16 96
PCH_CLK33M_PCIIN
BJ30
IN
PCH_CLK96M_DOT_N
PCH_CLK96M_DOT_P
BE18
IN
24 96
PCH_CLKIN_GNDN1
PCH_CLKIN_GNDP1
BG30
G24
CLKIN_SATA_N
CLKIN_SATA_P
AK7
K45
CLKIN_PCILOOPBACK
CLKOUT_PCIE3N
CLKOUT_PCIE3P
CLKIN_DOT_96N
CLKIN_DOT_96P
REFCLK14IN
PCIECLKRQ2*/GPIO20
16
16
JTAG_DPMUXUC_TRST_L
L12
PCIECLKRQ4*/GPIO26
TP_PCIE_CLK100M_PE5N
TP_PCIE_CLK100M_PE5P
V45
H45
CLKOUT_PCIE5N
CLKOUT_PCIE5P
L14
Y45
E24
AK5
PCIECLKRQ3*/GPIO25
CLKOUT_PCIE4N
CLKOUT_PCIE4P
DOES THIS NEED LENGTH MATCH???
V46
AB42
TP_PCIE_CLK100M_PEBN
TP_PCIE_CLK100M_PEBP
AB40
E6
PEGCLKRQB_L_GPIO56
0
0
5%
1/20W
MF
201
TBT_CLKREQ_L
K12
IN
93 23
V37
AK14
ITPXDP_CLK100M_N
ITPXDP_CLK100M_P
AK13
CLKOUT_PCIE6N
CLKOUT_PCIE6P
XCLK_RCOMP
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P
IN
SYSCLK_CLK25M_SB
1
PCH_CLK96M_DOT_P
PCH_CLK96M_DOT_N
R1891
R1892
10K
10K
1
1
2
PCH_CLK100M_SATA_P
PCH_CLK100M_SATA_N
R1893
R1894
10K
10K
1
2
1
2
PCIE_CLK100M_PCH_P
PCIE_CLK100M_PCH_N
R1895
R1896
10K
10K
1
2
16
16 24
16
201
1/20W
MF
201
1/20W
MF
201
5%
1/20W
MF
96 16
GPU:2P
1/20W
MF
7
96 16
16
201
96 16
1/20W
MF
CLKOUTFLEX1/GPIO65
(IPD-PWROK)
8
CLKOUTFLEX2/GPIO66
(IPD-PWROK)
H47
TP_PCH_GPIO66_CLKOUTFLEX2
8
K49
TP_PCH_GPIO67_CLKOUTFLEX3
8
SYSCLK_CLK25M_SB_R
2
1
16
1.8V - & gt; 1.1V
R1873
1%
1/20W
MF
2 201
201
5%
1/20W
MF
201
1/20W
MF
201
PCH_CLK14P3M_REFCLK
R1897
10K
1
R1870
R1871
10K
10K
1
Apple Inc.
4
2
051-9585
1/20W
MF
201
5%
1/20W
MF
201
1/20W
MF
201
3
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
2
SIZE
D
REVISION
R
2
1
SYNC_DATE=06/02/2011
PCH SATA/PCIe/CLK/LPC/SPI
2
PCH_CLKIN_GNDP1
PCH_CLKIN_GNDN1
SYNC_MASTER=J31_ANNE
DRAWING NUMBER
5%
16
5
8
TP_PCH_GPIO65_CLKOUTFLEX1
PAGE TITLE
5%
16
6
TP_PCH_GPIO64_CLKOUTFLEX0
F47
201
5%
96 16
5%
5%
96 16
5%
K43
2
1
16 35
16
16 25
CLKOUTFLEX0/GPIO64
(IPD-PWROK)
1K
2
5%
96 16
604
1%
1/16W
MF-LF
402
Unused clock terminations for FCIM Mode
PEGCLKRQB_L_GPIO56
PLACE_NEAR=U1800.Y47:2.54mm
PCH_XCLK_RCOMP
CLKOUTFLEX3/GPIO67
(IPD-PWROK)
PCIECLKRQ7*/GPIO46
(IPU-RSMRST#)
Y47
R1872
96 16
2
1
1%
1/20W
MF
201 2
2
16 36
1
B
=PP1V05_S0_PCH_VCCDIFFCLK
90.9
CLKOUT_PCIE7N
CLKOUT_PCIE7P
OUT
PCIE_CLK100M_TBT_N
PCIE_CLK100M_TBT_P
V38
OUT
93 23
16
10K
16
PCIECLKRQ6*/GPIO45
IN
PEG_CLKREQ_L
35 16
2
8 16
R1880
SYSCLK_CLK25M_SB_R
NC
PEG_B_CLKRQ*/GPIO56
16
16
V49
CLKOUT_PEG_B_N
CLKOUT_PEG_B_P
T13
V42
24
16
V47
22 20 7
V40
16 32
PCIECLKRQ0_L_GPIO73
PEGCLKRQA_L_GPIO47
PEGCLKRQB_L_GPIO56
PCH_GPIO11
USB_EXTB_SEL_XHCI
USB_EXTD_SEL_XHCI
XTAL25_IN
XTAL25_OUT
PCIECLKRQ5*/GPIO44
(IPU-RSMRST#)
5%
1/20W
MF
201
23 41
16 39
Connect to ENET_MEDIA_SENSE via alias if HDA = 3.3V.
Connect to ENET_MEDIA_SENSE via 12K R if HDA = 1.5V.
If HDA = S0, must also ensure that signal cannot be high in S3.
8
SML_PCH_1_CLK
SML_PCH_1_DATA
PERN7
PERP7
PETN7
PETP7
201
1/20W
GPU:1P
BI
USB_EXTD_SEL_XHCI
E14
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
PEG_CLK100M_N
PEG_CLK100M_P
16 8
1
16
ENET_MEDIA_SENSE_RDIV
1/20W
5%
5%
2
5%
C13
PERN6
PERP6
PETN6
PETP6
OUT
57 96
201
5%
5%
1
93 10
201
5%
2
1
16 33
201
2
R1879
201
MF
2
R1843
R1846
R1848
R1853
R1854
R1855
MF
1/20W
5%
R1834
R1833
1/20W
5%
A
5%
201
5%
48 96
G12
PEG_A_CLKRQ*/GPIO47
PERN5
PERP5
PETN5
PETP5
OUT
NO STUFF
2
PERN4
PERP4
PETN4
PETP4
96 75
R1840
1
16 25
OUT
SML1CLK/GPIO58
SML1DATA/GPIO75
96 75
HDA_SDOUT
2
7 19
1
OUT
SML_PCH_0_CLK
SML_PCH_0_DATA
SML0CLK
SML0DATA
SML1ALERT*/PCHHOT*/GPIO74
Y43
96 33
R1877
R1878
PERN3
PERP3
PETN3
PETP3
TP_PCIE_CLK100M_PE4N
TP_PCIE_CLK100M_PE4P
96 33
MF
PERN2
PERP2
PETN2
PETP2
57 96
OUT
201
5%
OUT
HDA_RST_L
5%
7 17 18 19 30
1/20W
USB_EXTB_SEL_XHCI
C8
BI
R1890
16
HDA_SYNC
7 17 18 19
5%
A12
C9
6 45 47 89 96
6
36 16
6
2
SML0ALERT*/GPIO60
FCBGA
6 45 47 89 96
BI
201
2
1
5%
2
1
6
LPC_AD & lt; 0 & gt;
LPC_AD & lt; 1 & gt;
LPC_AD & lt; 2 & gt;
LPC_AD & lt; 3 & gt;
LPC_FRAME_L
HDA_BIT_CLK
2
5%
1
OUT
16
(2 OF 10)
16
16
10K
SMBUS_PCH_CLK
SMBUS_PCH_DATA
16
96 16
R1876
PCH_GPIO11
H14
MOBILE
ENET_CLKREQ_L
6
16
1UF
=PP3V3_SUS_PCH_GPIO
=PP3V3_S0_PCH_GPIO
=PP3V3_T29_PCH_GPIO
E12
SMBCLK
SMBDATA
PANTHERPOINT
PLACE_NEAR=U1800.AH1:2.54mm
P3
R1803
5%
1/20W
MF
2 201
B
AY34
BJ38
5%
1/20W
MF
201 2
R1801
BE36
BG37
20K
1
BF36
SMBALERT*/GPIO11
U1800
PERN1
PERP1
PETN1
PETP1
PLACE_NEAR=U1800.Y11:2.54mm
6
AB12
95
BB32
NC_PCIE_8_D2RN
NC_PCIE_8_D2RP
NC_PCIE_8_R2D_CN
NC_PCIE_8_R2D_CP
6
49.9
AH1
BF34
NC_PCIE_7_D2RN
NC_PCIE_7_D2RP
NC_PCIE_7_R2D_CN
NC_PCIE_7_R2D_CP
6
Y10
AB13
AU32
NC_PCIE_6_D2RN
NC_PCIE_6_D2RP
NC_PCIE_6_R2D_CN
NC_PCIE_6_R2D_CP
6
TP_SATA_F_D2RN
TP_SATA_F_D2RP
TP_SATA_F_R2D_CN
TP_SATA_F_R2D_CP
Y1
AV32
NC_PCIE_5_D2RN
NC_PCIE_5_D2RP
NC_PCIE_5_R2D_CN
NC_PCIE_5_R2D_CP
6
TP_SATA_E_D2RN
TP_SATA_E_D2RP
TP_SATA_E_R2D_CN
TP_SATA_E_R2D_CP
BJ34
PCIE_EXCARD_D2R_N
PCIE_EXCARD_D2R_P
PCIE_EXCARD_R2D_C_N
PCIE_EXCARD_R2D_C_P
41 95
1
7 17 20
R1802 1
96 38
41 95
OUT
TP_SATA_D_D2RN
TP_SATA_D_D2RP
TP_SATA_D_R2D_CN
TP_SATA_D_R2D_CP
AB10
SATALED*
=PPVRTC_G3_PCH
41 95
IN
BG34
TP_SATA_C_D2RN
TP_SATA_C_D2RP
TP_SATA_C_R2D_CN
TP_SATA_C_R2D_CP
AD5
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
SPI_CLK
SPI_CS0*
AD7
IN
SATA_ODD_D2R_N
SATA_ODD_D2R_P
SATA_ODD_R2D_C_N
SATA_ODD_R2D_C_P
AP11
SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP
SPI
23
AP5
AM10
SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP
JTAG
23
AP7
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
JTAG_TBT_TMS
ENET_MEDIA_SENSE_RDIV
96 24 16
33 16
K34
HDA_RST_R_L
SATA_HDD_D2R_N
SATA_HDD_D2R_P
SATA_HDD_R2D_C_N
SATA_HDD_R2D_C_P
AM1
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
IHDA
96 16
PCH_SPKR
SATA
16
AM3
IN
PCIE_ENET_D2R_N
PCIE_ENET_D2R_P
PCIE_ENET_R2D_C_N
PCIE_ENET_R2D_C_P
SMBUS
NC
1
OMIT_TABLE
FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3
(IPU)
FWH4/LFRAME*
U1800
RTCX1
RTCX2
CLOCKS
A20
SYSCLK_CLK32K_RTC
IN
PCI-E*
C-LINK
24
FLEX
CLOCKS
8
3.0.0
BRANCH
PAGE
18 OF 132
SHEET
16 OF 105
1
A
8
7
=PP3V3_SUS_PCH_GPIO
=PP1V05_S0_PCH_VCCIO_PCIE
6
5
4
3
2
1
7 16 17 18 19
7
PLACE_NEAR=U1800.BJ24:12.7mm
R1905 1
1
49.9
OMIT_TABLE
93 9 6
D
93 9 6
IN
93 9
IN
93 9 6
IN
93 9 6
IN
93 9 6
IN
93 9 6
OUT
93 9 6
OUT
93 9
OUT
93 9 6
OUT
93 9 6
OUT
93 9
OUT
93 9 6
AW24
BE20
BG18
BG20
BC20
BJ18
BJ20
AW20
BB18
AV18
AY24
DMI_S2N_P & lt; 0 & gt;
DMI_S2N_P & lt; 1 & gt;
DMI_S2N_P & lt; 2 & gt;
DMI_S2N_P & lt; 3 & gt;
OUT
93 9 6
BE24
DMI_S2N_N & lt; 0 & gt;
DMI_S2N_N & lt; 1 & gt;
DMI_S2N_N & lt; 2 & gt;
DMI_S2N_N & lt; 3 & gt;
IN
BC24
DMI_N2S_P & lt; 0 & gt;
DMI_N2S_P & lt; 1 & gt;
DMI_N2S_P & lt; 2 & gt;
DMI_N2S_P & lt; 3 & gt;
IN
93 9 6
DMI_N2S_N & lt; 0 & gt;
DMI_N2S_N & lt; 1 & gt;
DMI_N2S_N & lt; 2 & gt;
DMI_N2S_N & lt; 3 & gt;
IN
OUT
AY20
AY18
AU18
BJ24
PCH_DMI_COMP
BG25
BH21
PCH_DMI2RBIAS
DMI0RXN
DMI1RXN
DMI2RXN
DMI3RXN
OMIT_TABLE
U1800
FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7
PANTHERPOINT
MOBILE
FCBGA
(3 OF 10)
DMI0RXP
DMI1RXP
DMI2RXP
DMI3RXP
BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9
FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7
BG14
FDI_INT
AW16
FDI_FSYNC0
FDI_FSYNC1
AV12
DMI0TXN
DMI1TXN
DMI2TXN
DMI3TXN
DMI0TXP
DMI1TXP
DMI2TXP
DMI3TXP
DMI_ZCOMP
DMI_IRCOMP
FDI_LSYNC0
FDI_LSYNC1
DMI2RBIAS
BB14
BF14
BG13
BE12
BG12
BJ10
BH9
BC10
AV14
BB10
FDI_DATA_N & lt; 0 & gt;
FDI_DATA_N & lt; 1 & gt;
FDI_DATA_N & lt; 2 & gt;
FDI_DATA_N & lt; 3 & gt;
FDI_DATA_N & lt; 4 & gt;
FDI_DATA_N & lt; 5 & gt;
FDI_DATA_N & lt; 6 & gt;
FDI_DATA_N & lt; 7 & gt;
FDI_DATA_P & lt; 0 & gt;
FDI_DATA_P & lt; 1 & gt;
FDI_DATA_P & lt; 2 & gt;
FDI_DATA_P & lt; 3 & gt;
FDI_DATA_P & lt; 4 & gt;
FDI_DATA_P & lt; 5 & gt;
FDI_DATA_P & lt; 6 & gt;
FDI_DATA_P & lt; 7 & gt;
FDI_INT
FDI_FSYNC & lt; 0 & gt;
FDI_FSYNC & lt; 1 & gt;
FDI_LSYNC & lt; 0 & gt;
FDI_LSYNC & lt; 1 & gt;
8
2
1%
1/20W
MF
201
C12
PCH_SUSACK_L
17
K3
SUSACK* (IPU)
IN
PM_SYSRST_L
92 45 23
P12
IN
PM_PCH_SYS_PWROK
SYS_PWROK
92 24
PM_PCH_PWROK
L22
IN
PWROK
92
PM_PCH_APWROK
L10
IN
45 24 6
C
93 26 10
74
PM_RSMRST_L
C21
PCH_SUSWARN_L
K16
IN
PM_PWRBTN_L
E20
IN
SMC_ADAPTER_EN
H20
IN
17
45 23 17
74 46 45
46
B13
PM_MEM_PWRGD
OUT
APWROK
DRAMPWROK
RSMRST*
DSWVRMEN
DPWROK
E22
E10
A10
PCH_RI_L
T40
T45
6
TP_LVDS_IG_CTRL_CLK
TP_LVDS_IG_CTRL_DATA
6
PCH_LVDS_IBG
TP_PCH_LVDS_VBG
OUT
IN
6 9 93
17 8
IN
9 93
IN
9 93
IN
6 9 93
86
OUT
IN
6 9 93
86
OUT
IN
6 9 93
IN
6 9 93
6
IN
9 93
IN
6 9 93
IN
9 93
IN
9 93
IN
6 9 93
IN
6 9 93
PLACE_NEAR=U1800.AF37:2.54mm
R1950 1
95 89
OUT
OUT
6 9 93
OUT
6 9 93
95 89
OUT
OUT
6 9 93
95 8
OUT
=PPVRTC_G3_PCH
1
95 89
7 16 20
R1915
390K
6 9 93
6 9 93
95 89
95 89
5%
1/20W
MF
201
OUT
95 89
PM_DSW_PWRGD
45
OUT
OUT
N3
PM_CLKRUN_L
SUS_STAT*/GPIO61
G8
LPC_PWRDWN_L
OUT
6 45 47
PM_CLK32K_SUSCLK_R
OUT
8
95 89
OUT
95 89
SLP_S5*/GPIO63
N14
OUT
8
D10
SLP_S4*
PWRBTN* (IPU)
H4
SLP_S3*
F4
SLP_A*
G10
ACPRESENT/GPIO31
(IPD-DeepS4/S5)
BATLOW*/GPIO72 (IPU)
SLP_SUS*
PMSYNCH
SLP_LAN*/GPIO29
AP14
K14
PM_SLP_S5_L
PM_SLP_S4_L
PM_SLP_S3_L
5%
1/20W
MF
201
OUT
95 89
OUT
17 45 74
OUT
95 89
OUT
95 89
17 26 32 45 74
6 17 26 45 74
OUT
OUT
8
OUT
OUT
AN47
AM49
AK49
AJ47
AF40
AH45
AH43
AF39
AH47
AF49
AF45
AH49
AF47
AF43
PM_SLP_SUS_L
PM_SYNC
MEM_VDD_SEL_1V5_L
OUT
17 74
TP_CRT_IG_BLUE
TP_CRT_IG_GREEN
TP_CRT_IG_RED
6
OUT
OUT
10 93
6
N48
TP_CRT_IG_DDC_CLK
TP_CRT_IG_DDC_DATA
6
T39
P49
T49
=PP3V3_SUS_PCH_GPIO
M40
M47
TP_CRT_IG_HSYNC
TP_CRT_IG_VSYNC
6
6
R1983 1
M49
T43
PCH_DAC_IREF
10K
PCH_SUSWARN_L
17
R1986
0
LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3
DDPD_CTRLCLK
DDPD_CTRLDATA
(IPD-PLTRST#)
DDPD_AUXN
DDPD_AUXP
DDPD_HPD
CRT_BLUE
CRT_GREEN
CRT_RED
CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_VSYNC
DAC_IREF
CRT_IRTN
DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P
DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P
6
TP_SDVO_STALLN
TP_SDVO_STALLP
AM40
AP39
6
TP_SDVO_INTN
TP_SDVO_INTP
AP40
P38
6
6
DPA_IG_DDC_CLK
DPA_IG_DDC_DATA
M39
AT49
8
8
DPA_IG_AUX_CH_N
DPA_IG_AUX_CH_P
DPA_IG_HPD
AT47
AT40
AV42
8
8
8
TP_DP_IG_B_MLN & lt; 0 & gt;
TP_DP_IG_B_MLP & lt; 0 & gt;
TP_DP_IG_B_MLN & lt; 1 & gt;
TP_DP_IG_B_MLP & lt; 1 & gt;
TP_DP_IG_B_MLN & lt; 2 & gt;
TP_DP_IG_B_MLP & lt; 2 & gt;
TP_DP_IG_B_MLN & lt; 3 & gt;
TP_DP_IG_B_MLP & lt; 3 & gt;
AV40
AV45
AV46
AU48
AU47
AV47
AV49
P46
8
8
8
8
8
8
8
8
DPB_IG_DDC_CLK
DPB_IG_DDC_DATA
P42
AP47
8
8
DPB_IG_AUX_CH_N
DPB_IG_AUX_CH_P
DPB_IG_HPD
AP49
AT38
AY47
8
8
8
TP_DP_IG_C_MLN & lt; 0 & gt;
TP_DP_IG_C_MLP & lt; 0 & gt;
TP_DP_IG_C_MLN & lt; 1 & gt;
TP_DP_IG_C_MLP & lt; 1 & gt;
TP_DP_IG_C_MLN & lt; 2 & gt;
TP_DP_IG_C_MLP & lt; 2 & gt;
TP_DP_IG_C_MLN & lt; 3 & gt;
TP_DP_IG_C_MLP & lt; 3 & gt;
AY49
AY43
AY45
BA47
BA48
BB47
BB49
M43
AT45
6
6
6
6
6
6
6
6
6
TP_DP_IG_D_AUXN
TP_DP_IG_D_AUXP
TP_DP_IG_D_HPD
AT43
BH41
BB43
6
6
6
TP_DP_IG_D_MLN & lt; 0 & gt;
TP_DP_IG_D_MLP & lt; 0 & gt;
TP_DP_IG_D_MLN & lt; 1 & gt;
TP_DP_IG_D_MLP & lt; 1 & gt;
TP_DP_IG_D_MLN & lt; 2 & gt;
TP_DP_IG_D_MLP & lt; 2 & gt;
TP_DP_IG_D_MLN & lt; 3 & gt;
TP_DP_IG_D_MLP & lt; 3 & gt;
BB45
BF44
BE44
BF42
BE42
BJ42
BG42
C
6
TP_DP_IG_D_CTRL_CLK
TP_DP_IG_D_CTRL_DATA
M36
D
6
6
6
6
6
6
6
6
6
R1951
PCH_SUSACK_L
5%
1/20W
MF
2 201
17
B
7
1K
1
2
8.2K
1
2
PM_PWRBTN_L
10K
1
1K
1
201
1/20W
MF
201
2
MEM_VDD_SEL_1V5_L
100K
100K
100K
100K
2
1
2
1
R1981
R1984
100K
100K
2
MF
201
1
2
1/20W
1
1
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1
5%
1/20W
MF
1/20W
MF
201
6 17 24 32
MAKE_BASE=TRUE
PM_SLP_S3_L
PM_SLP_S4_L
PM_SLP_S5_L
PM_SLP_SUS_L
SYNC_MASTER=J5_MLB
=TBT_WAKE_L
5%
1/20W
MF
LVDS_IG_BKL_ON
LVDS_IG_PANEL_PWR
PCH DMI/FDI/PM/Graphics
87
DRAWING NUMBER
6 17 26 45 74
Apple Inc.
17 26 32 45 74
17 45 74
051-9585
17 74
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8 17
8 17
6
5
4
3
2
SIZE
D
REVISION
R
201
7
SYNC_DATE=05/26/2011
PAGE TITLE
IN
201
5%
17
PCIE_WAKE_L
5%
R1924
R1921
R1922
R1923
6 17 45 47
201
MF
2
R1925
MF
1/20W
5%
R1982
1/20W
5%
17 23 45
PM_CLKRUN_L
5%
8
LVDSB_DATA0*
LVDSB_DATA1*
LVDSB_DATA2*
LVDSB_DATA3*
AM42
6
7 16 18 19 30
R1991
2
LVDSB_CLK*
LVDSB_CLK
DDPC_CTRLCLK
DDPC_CTRLDATA
(IPD-PLTRST#)
DDPC_AUXN
DDPC_AUXP
DDPC_HPD
TP_SDVO_TVCLKINN
TP_SDVO_TVCLKINP
AP45
7 16 17 18 19
R1985
2
LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3
DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P
AP43
1K
1
5%
1/20W
MF
201
=PP3V3_SUS_PCH_GPIO
=PP3V3_S0_PCH_GPIO
=PP3V3_S5_PCH
A
1
2
B
T42
PLACE_NEAR=U1800.T43:2.54mm
2
LVDSA_DATA0*
LVDSA_DATA1*
LVDSA_DATA2*
LVDSA_DATA3*
17
6
5%
1/20W
MF
201
LVDSA_CLK*
LVDSA_CLK
TP_PM_SLP_A_L
6
19 18 17 16 7
AJ48
LVDS_IG_B_DATA_P & lt; 0 & gt;
LVDS_IG_B_DATA_P & lt; 1 & gt;
LVDS_IG_B_DATA_P & lt; 2 & gt;
LVDS_IG_B_DATA_P & lt; 3 & gt;
OUT
95 89
R1909
100K
6 17 45 47
2
SUSWARN*/SUSPWRDNACK/GPIO30
RI*
1
AK47
LVDS_IG_B_DATA_N & lt; 0 & gt;
LVDS_IG_B_DATA_N & lt; 1 & gt;
LVDS_IG_B_DATA_N & lt; 2 & gt;
LVDS_IG_B_DATA_N & lt; 3 & gt;
OUT
46
BI
6 17 24 32
AM47
LVDS_IG_B_CLK_N
LVDS_IG_B_CLK_P
OUT
8
IN
AN48
AK40
LVDS_IG_A_DATA_P & lt; 0 & gt;
LVDS_IG_A_DATA_P & lt; 1 & gt;
LVDS_IG_A_DATA_P & lt; 2 & gt;
LVDS_IG_A_DATA_P & lt; 3 & gt;
OUT
95 8
CLKRUN*/GPIO32
SUSCLK/GPIO62
OUT
AK39
LVDS_IG_A_DATA_N & lt; 0 & gt;
LVDS_IG_A_DATA_N & lt; 1 & gt;
LVDS_IG_A_DATA_N & lt; 2 & gt;
LVDS_IG_A_DATA_N & lt; 3 & gt;
OUT
95 89
LVDS_IG_A_CLK_N
LVDS_IG_A_CLK_P
OUT
95 89
IN
AF36
U1800
SDVO_TVCLKINN
(IPD)
PANTHERPOINT SDVO_TVCLKINP
(IPD)
MOBILE
FCBGA
L_BKLTCTL
SDVO_STALLN
(4 OF 10)
(IPD)
SDVO_STALLP
(IPD)
L_DDC_CLK
L_DDC_DATA
SDVO_INTN
(IPD)
(IPD-PLTRST#)
SDVO_INTP
L_CTRL_CLK
(IPD)
L_CTRL_DATA
SDVO_CTRLCLK
LVD_IBG
SDVO_CTRLDATA
(IPD-PLTRST#)
LVD_VBG
DDPB_AUXN
LVD_VREFH
DDPB_AUXP
DDPB_HPD
LVD_VREFL
L_BKLTEN
L_VDD_EN
2
PCH_DSWVRMEN
PCIE_WAKE_L
AF37
AE47
6 9 93
WAKE*
P39
AE48
6 9 93
OUT
K47
1%
1/20W
MF
201
IN
OUT
M45
2.37K
IN
B9
G16
PM_BATLOW_L
IN
SYS_RESET*
SYSTEM POWER
MANAGEMENT
750
A18
LVDS_IG_DDC_CLK
LVDS_IG_DDC_DATA
17 8
2
R1920
LVDS_IG_BKL_PWM
P45
OUT
9 93
PLACE_NEAR=U1800.BH21:2.54mm
1
J47
OUT
LVDS_IG_BKL_ON
LVDS_IG_PANEL_PWR
IN
DIGITAL DISPLAY INTERFACE
93 9
LVDS
1%
1/20W
MF
2 201
CRT
5%
1/20W
MF
201 2
DMI
FDI
10K
R1900
3.0.0
BRANCH
PAGE
19 OF 132
SHEET
17 OF 105
1
A
8
7
6
5
4
3
2
1
OMIT_TABLE
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
D
BG26
BJ26
BH25
BJ16
BG16
AH38
AH37
AK43
AK45
C18
N30
H3
AH12
AM4
AM5
Y13
K24
L24
AB46
AB45
B21
NC
NC
M20
AY16
TP_PCH_TP23
TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18
TP19
TP20
U1800
PANTHERPOINT
MOBILE
FCBGA
(5 OF 10)
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
TP21
TP22
TP23
TP24
AY7
AV7
AU3
BG4
AT10
BC8
AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6
8
8
C
IN
IN
95 42 6
IN
95 43 6
IN
8
IN
8
IN
95 42 6
OUT
95 43 6
OUT
8
OUT
8
OUT
95 42 6
OUT
95 43 6
OUT
8
OUT
10K
10K
10K
10K
1
2
1
2
1
2
1
2
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
OUT
B
NO STUFF
R2054
10K
2
1
5%
1/20W
MF
IN
63 18
IN
87 18
IN
63 18
IN
6
26 24
OUT
96 24
7 24
6
7 16 17 18 19 30
2
2
2
24
1
1/20W
MF
201
5%
1/20W
MF
201
1/20W
MF
5%
1/20W
MF
A
10K
10K
1
2
5%
1/20W
MF
201
1/20W
MF
1
1/20W
MF
MF
R2067
10K
2
1
2
1
2
2
K40
PCI_INTA_L
PCI_INTB_L
PCI_INTC_L
PCI_INTD_L
K38
PIRQA*
PIRQB*
PIRQC*
PIRQD*
H38
G38
JTAG_GMUX_TMS
BLC_I2C_MUX_SEL
USE_HDD_OOB_L
C46
D47
G42
TP_PCI_PME_L
K10
C44
USBP7N
USBP7P
E40
E42
F46
OUT
G40
C42
D44
C6
PLT_RESET_L
H49
LPC_CLK33M_SMC_R
LPC_CLK33M_LPCPLUS_R
TP_PCI_CLK33M_OUT2
TP_PCI_CLK33M_OUT3
PCH_CLK33M_PCIOUT
H43
J48
K42
H40
REQ1*/GPIO50
REQ2*/GPIO52
REQ3*/GPIO54
GNT1*/GPIO51
GNT2*/GPIO53
GNT3*/GPIO55
(IPU-PCIERST#)
PIRQE*/GPIO2
PIRQF*/GPIO3
PIRQG*/GPIO4
PIRQH*/GPIO5
PME* (IPU)
PLTRST*
CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4
(IPD)
C29
N28
USBP8N
USBP8P
L30
USBP9N
USBP9P
G30
USBP10N
USBP10P
C30
USBP11N
USBP11P
L32
USBP12N
USBP12P
G32
USBP13N
USBP13P
(IPD)
C32
USBRBIAS*
USBRBIAS
C33
OC0*/GPIO59
OC1*/GPIO40
OC2*/GPIO41
OC3*/GPIO42
OC4*/GPIO43
OC5*/GPIO9
OC6*/GPIO10
OC7*/GPIO14
A14
25 95
BI
8 95
BI
8 95
BI
25 95
BI
25 95
Ext B (XHCI)
Ext D (XHCI) (Mobiles: Trackpad?)
TP_USB_4N
TP_USB_4P
B29
RSVD: SD
TP_USB_WLANN
TP_USB_WLANP
A28
Unused
TP_USB_SDN
TP_USB_SDP
D28
RSVD: WiFi
USB_HUB_UP_N
USB_HUB_UP_P
E30
25 95
BI
25 95
BI
32 95
BI
32 95
USB_EXTB_EHCI_N
USB_EXTB_EHCI_P
K30
BI
USB_CAMERA_N
USB_CAMERA_P
M28
BI
25 95
USB_EXTD_EHCI_N
USB_EXTD_EHCI_P
A30
BI
Ext B (EHCI)
8
BI
Camera
25 95
BI
USB Hub (All LS/FS Devices)
8
Ext D (EHCI)
TP_USB_BT_HSN
TP_USB_BT_HSP
A32
95
Unused
TP_USB_13N
TP_USB_13P
E32
RSVD: BT (HS)
TP_USB_12N
TP_USB_12P
K32
C
Ext C (XHCI/EHCI)
Unused
B
PCH_USB_RBIAS
B33
PLACE_NEAR=U1800.B33:2.54mm
1
K20
B17
C16
L16
A16
D14
C14
XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L
XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L
XDP_DA2_PCH_GPIO41_USB_EXTC_OC_L
XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L
XDP_DB0_PCH_GPIO43_USB_EXTB_OC_EHCI_L
XDP_DB1_PCH_GPIO9_USB_EXTD_OC_EHCI_L
XDP_DB2_PCH_GPIO10_AP_PWR_EN
XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE
IN
18 23
IN
18 23
IN
18 23
IN
23
IN
23
OUT
22.6
18 23
IN
R2070
23
IN
1%
1/20W
MF
2 201
18 23
18 89
18
18
18
18 63
18 87
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
1/20W
MF
SYNC_MASTER=J31_ANNE
SYNC_DATE=06/02/2011
PAGE TITLE
18 63
PCH PCI/USB/TP/RSVD
201
XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE
1
1/20W
MF
DRAWING NUMBER
18 23
XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L
XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L
XDP_DA2_PCH_GPIO41_USB_EXTC_OC_L
XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L
AP_PWR_EN
5%
8
USBP6N
USBP6P
25 95
BI
Ext A (XHCI/EHCI)
201
2
1
AW30
C28
BI
USB_EXTD_XHCI_N
USB_EXTD_XHCI_P
H28
42 95
USB_EXTC_N
USB_EXTC_P
A26
42 95
BI
USB_EXTB_XHCI_N
USB_EXTB_XHCI_P
B25
BI
201
1/20W
2
1
5%
5%
1
10K
10K
10K
10K
1/20W
5%
10K
AUD_IP_PERIPHERAL_DET
TBT_PWR_REQ_L
AUD_I2C_INT_L
5%
R2060
R2061
R2062
R2068
AV28
USBP5N
USBP5P
USB3TP1
USB3TP2
USB3TP3
USB3TP4
E28
USB_EXTA_N
USB_EXTA_P
A24
Redundant to pull-up on audio page
2
R2069
AY26
K28
USBP4N
USBP4P
NC
NC
201
NO STUFF
10K
AY30
USB3TN1
USB3TN2
USB3TN3
USB3TN4
NC
NC
C26
USBP3N
USBP3P
NC
C25
USBP2N
USBP2P
NC
NC
C24
USBP1N
USBP1P
USB3RP1
USB3RP2
USB3RP3
USB3RP4
D
Redundant to pull-up on audio page
5%
R2033
JTAG_GMUX_TMS
BLC_I2C_MUX_SEL
USE_HDD_OOB_L
BLC_GPIO
2
1
AU28
BF3
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
201
2
NO STUFF
R2014
R2031
BB26
AT12
BA2
NC
NC
201
5%
10K
OUT
24
5%
R2030
OUT
24
7 16 17 19
1
BG32
201
18
1
BF32
BLC_GPIO
AUD_IP_PERIPHERAL_DET
TBT_PWR_REQ_L
AUD_I2C_INT_L
OUT
18
1
AU26
BE30
TP_PCH_STRP_BBS1
TP_PCH_STRP_ESI_L
PCH_STRP_TOPBLK_SWP_L
OUT
18
10K
10K
10K
USB3_EXTA_TX_P
USB3_EXTB_TX_P
USB3_EXTC_TX_P
USB3_EXTD_TX_P
BJ32
AY5
AV10
USBP0N
USBP0P
USB3RN1
USB3RN2
USB3RN3
USB3RN4
201
89 18
R2016
R2017
R2018
USB3_EXTA_TX_N
USB3_EXTB_TX_N
USB3_EXTC_TX_N
USB3_EXTD_TX_N
AV26
BE32
=PP3V3_S0_PCH_GPIO
R2010
R2011
R2012
R2013
=PP3V3_SUS_PCH_GPIO
=PP3V3_S3_PCH_GPIO
=PP3V3_S0_PCH_GPIO
BC28
BC30
PCI
30 19 18 17 16 7
OUT
8
BE28
USB3_EXTA_RX_P
USB3_EXTB_RX_P
USB3_EXTC_RX_P
USB3_EXTD_RX_P
IN
USB
USB3_EXTA_RX_N
USB3_EXTB_RX_N
USB3_EXTC_RX_N
USB3_EXTD_RX_N
IN
AT8
RSVD28
RSVD29
95 43 6
AV5
RSVD26
RSVD27
95 42 6
RSVD23
RSVD24
RSVD25
NC
BG46
NC
NC
NC
NC
Apple Inc.
18 23
18 23
R
18 23
NOTICE OF PROPRIETARY PROPERTY:
SIZE
D
3.0.0
BRANCH
18 23
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
23 32 74
201
7
051-9585
REVISION
6
5
4
3
2
PAGE
20 OF 132
SHEET
18 OF 105
1
A
8
7
6
5
4
3
2
1
TABLE_BOMGROUP_HEAD
BOM GROUP
BOM OPTIONS
RAMCFG_SLOT
RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:H
TABLE_BOMGROUP_ITEM
Systems with no chip-down memory should pull all 4 RAMCFG GPIOs high.
Systems with chip-down memory should add pull-downs on another page and set straps per software.
30 19 18 17 16 7
=PP3V3_S0_PCH_GPIO
RAMCFG3:H
R2172 1
RAMCFG2:H
1
10K
D
5%
1/20W
MF
201
OMIT_TABLE
T7
XDP_FC1_PCH_GPIO0
23 19
BMBUSY*/GPIO0
U1800
IN
DPMUX_UC_IRQ
H36
TACH2/GPIO6
(6 OF 10)
45 19
IN
SMC_RUNTIME_SCI_L
E38
TACH3/GPIO7
TP_PCH_GPIO8
C10
WOL_EN
C4
OUT
GPIO15 (IPU)
U2
OUT
XDP_DD2_PCH_GPIO16_AUD_IPHS_SWITCH_EN_PCH
SATA4GP/GPIO16
D
5%
1/20W
MF
201
IN
23
19
5%
MF
1/20W
201
23
OUT
E16
P8
XDP_DC0_PCH_GPIO28_ISOLATE_CPU_MEM_L
OUT
2
E8
PCH_GPIO24
(PU necessary?)
SMC_SCI_L
XDP_DD1_PCH_GPIO37_JTAG_ISP_TCK
M5
OUT
JTAG_ISP_TDO
N2
IN
OUT
JTAG_ISP_TDI
OUT
FW_PWR_EN_PCH
89 8
23
56 47 19 6
P5
PCH_RCIN_L
AY11
PCH_PROCPWRGD
43
1
CPU_PECI
2
BI
1/20W
201
10 46 93
19
M3
R2140
0
1
CPU_PWRGD
2
5%
MF
THRMTRIP*
AY10
46
R2156
PM_THRMTRIP_L_R
390
1
INIT3_3V*
(IPU)
T14
DF_TVS
(IPD-PLTRST#?)
AY1
AH8
P37
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_NCTF_22
VSS_NCTF_23
VSS_NCTF_24
VSS_NCTF_25
VSS_NCTF_26
VSS_NCTF_27
VSS_NCTF_28
VSS_NCTF_29
VSS_NCTF_30
VSS_NCTF_31
1/20W
201
PM_THRMTRIP_L
2
5%
MF
NC_1
SATA2GP/GPIO36
(IPD-PLTRST#)
SATA3GP/GPIO37
(IPD-PLTRST#)
SLOAD/GPIO38
1/20W
201
=PP1V8_S0_PCH_VCC_DFTERM
OUT
1
IN
7 20 22
10 23 93
10 46 93
R2179
2.2K
5%
1/20W
MF
201
BG2
SDATAOUT0/GPIO39
V13
PROCPWRGD
TS_VSS1
TS_VSS2
TS_VSS3
TS_VSS4
STP_PCI*/GPIO34
GPIO35
23
24 19
GPIO28 (IPU-RSMRST#)
K4
XDP_DD0_PCH_GPIO36_DP_GPU_TBT_SEL
89 19 8
GPIO27 (IPU-DeepS4/S5)
XDP_DC1_PCH_GPIO35_MXM_GOOD
OUT
C
RCIN*
GPIO24
TBT_SW_RESET_R_L
23 19
R2170
SCLOCK/GPIO22
K1
V8
19
5%
MF
TACH0/GPIO17
CPU/MISC
46 19
1
2
NO STUFF
(IPD) PECI
PCH_INIT3V3_L
R2178
PCH_DF_TVS
2
NO STUFF
R2130 1
AK11
1K
AH10
5%
1/20W
MF
201
AK10
1K
1
5%
1/20W
MF
201
This has internal pull up and should not pulled low.
2
CPU_PROC_SEL_L
10 93
DF_TVS:DMI & FDI Term Voltage
Set to Vss when Low
Set to Vcc when High
C
THIS SIGNAL IS INTENDED FOR FIRMWARE HUB AND WE ARE NOT USING IT.
2
SDATAOUT1/GPIO48
OUT
XDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCH
V3
SPIROM_USE_MLB
D6
BI
A4
A44
A45
A46
A5
A6
B3
B47
BD1
BD49
BE1
BE49
BF1
BF49
SATA5GP/GPIO49/TEMP_ALERT*
GPIO57
VSS_NCTF_0
VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
NCTF
19
A20GATE
GPIO
ODD_PWR_EN_L
T5
OUT
41 19
LPCPLUS_GPIO
D40
BI
47 19 6
R2180
2
LAN_PHY_PWR_CTRL/GPIO12
XDP_FC0_PCH_GPIO15
G2
IN
23
TBT_SW_RESET_L
10K
GPIO8 (IPU-RSMRST#)
68 23
OUT
PCH_PECI
R2175
FCBGA
74 19
35
PCH_A20GATE
AU16
5%
1/20W
MF
201
MLB_RAMCFG0
P4
2
5%
1/20W
MF
201
MLB_RAMCFG1
A40
2
RAMCFG0:H
1
10K
MLB_RAMCFG2
C41
R2174 1
10K
MLB_RAMCFG3
TACH6/GPIO70
MOBILE
B41
TACH7/GPIO71
TACH1/GPIO1
C40
TACH5/GPIO69
FW_PME_L
A42
IN
19 8
0
TACH4/GPIO68
PANTHERPOINT
39 19 8
RAMCFG1:H
R2173
NC
BG48
BH3
BH47
BJ4
BJ44
BJ45
BJ46
BJ5
BJ6
C2
C48
D1
D49
E1
E49
F1
F49
B
B
=PP3V3_S5_PCH_GPIO
=PP3V3_SUS_PCH_GPIO
=PP3V3_S0_PCH_GPIO
=PP3V3_T29_PCH_GPIO
R2186
R2199
10K
10K
7
7 16 17 18
7 16 17 18 19 30
7 16
1
2
1
2
10K
10K
10K
100K
1
2
1
2
1
2
MF
201
1/20W
MF
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
10K
10K
1
2
A
R2194
R2192
R2193
10K
10K
100K
1
2
MF
201
1/20W
MF
1
5%
1/20W
MF
201
1/20W
MF
2
1
2
1
2
1
2
1
2
1
2
1
201
MF
201
1/20W
MF
2
1
1/20W
MF
1
SPIROM_USE_MLB
5%
1/20W
MF
6 19 47 56
201
8 19 39
6 19 47
TBT_SW_RESET_R_L
FW_PWR_EN_PCH
19
PCH_A20GATE
PCH_RCIN_L
19 24
19
19
WOL_EN
PCH_GPIO24
SPIROM_USE_MLB
19
19 46
19 74
201
5%
5%
1/20W
1/20W
MF
MF
5%
1/20W
MF
5%
1/20W
MF
5%
1/20W
MF
5%
8
2
201
1
2
10K
19 45
SMC_SCI_L
MF
1/20W
2
20K
100K
10K
10K
10K
10K
1/20W
5%
5%
10K
R2111
R2195
R2112
R2198
R2113
R2116
5%
5%
R2191
NO STUFF
R2181
19 23
201
2
1
8 33
201
2
1
1/20W
5%
10K
10K
5%
5%
R2150
R2155
XDP_FC1_PCH_GPIO0
FW_PME_L
SMC_RUNTIME_SCI_L
LPCPLUS_GPIO
201
2
1
8 19 89
Must stuff R2197 when R2180 NO STUFFed.
NO STUFF
R2197
R2184
JTAG_ISP_TDO
JTAG_TBT_TDI
201
2
1
1/20W
5%
R2160
R2185
R2196
R2190
5%
1/20W
MF
SYNC_MASTER=J31_ANNE
SYNC_DATE=06/02/2011
PAGE TITLE
6 19 47 56
PCH GPIO/MISC/NCTF
DRAWING NUMBER
DPMUX_UC_IRQ
201
AUD_IPHS_SWITCH_EN_PCH
201
ODD_PWR_EN_L
201
XDP_DD0_PCH_GPIO36_DP_GPU_TBT_SEL
201
JTAG_ISP_TCK
201
ENET_LOW_PWR_PCH
8 19
Apple Inc.
23 24
R
NOTICE OF PROPRIETARY PROPERTY:
19 23
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8 23
23 24
6
5
4
3
2
SIZE
D
3.0.0
19 41
201
7
051-9585
REVISION
BRANCH
PAGE
21 OF 132
SHEET
19 OF 105
1
A
8
7
6
5
4
3
2
1
D
D
AL24 left as NC per DG
22 20 7
AL24
NC
AA19
=PP1V05_S0_PCH_VCCASW
AA21
AA24
AA26
AA27
AA29
AA31
AC26
C
AC27
AC29
AC31
AD29
AD31
W21
W23
W24
W26
W29
W31
PCH output, for decoupling only
PLACE_NEAR=U1800.N16:2.54mm
1
20 7
Y49
=PP1V8R1V5_S0_PCH_VCCVRM
V5REF_SUS
M26
=PP5V_SUS_PCH_V5REFSUS
22
VCCASW_3_CLK
VCCASW_4_CLK
VCCASW_5_CLK
VCCASW_6_CLK
VCCASW_7_CLK
VCCASW_8_CLK
VCCASW_9_CLK
VCCASW_10_CLK
VCCASW_11_CLK
VCCASW_12_CLK
VCCASW_13_CLK
VCCASW_14_CLK
VCCASW_15_CLK
VCCASW_16_CLK
VCCASW_17_CLK
VCCASW_18_CLK
VCCASW_19_CLK
VCCASW_20_CLK
T27
AD23
T29
AF21
AF23
T23
=PP3V3_SUS_PCH_VCCSUS_USB
7 22
AG21
T24
AG23
V23
AG24
V24
AG26
P24
AG27
AG29
AJ23
DCPSUS_4_USB
AN23
VCCSUS3_3_1_USB
AN24
NC
AJ26
NC-ed per DG
AJ27
AJ29
V5REF
P34
=PP3V3_SUS_PCH_VCCSUS
=PP5V_S0_PCH_V5REF
7 22
AJ31
22
22
2
22
22 20 7
22 16 7
PP1V05_S0_PCH_VCCADPLLA_F
PP1V05_S0_PCH_VCCADPLLB_F
BD47
=PP1V05_S0_PCH_VCCIO_CLK
AF17
BF47
AF33
=PP1V05_S0_PCH_VCCDIFFCLK
55mA Max, 5mA Idle
AF34
AG34
22 7
AG33
=PP1V05_S0_PCH_VCCSSC
VCCSUS3_3_2_GPIO
VCCSUS3_3_3_GPIO
VCCSUS3_3_4_GPIO
VCCSUS3_3_5_GPIO
N20
AN19
TP_1V05_S0_PCH_VCCAPLLEXP
BJ22
=PP1V05_S0_PCH_VCCIO
AN16
AN17
=PP3V3_S0_PCH_VCC3_3_GPIO
AN21
VCC3_3_1_GPIO
VCC3_3_8_GPIO
VCC3_3_4_GPIO
W16
AN26
T34
AN27
AJ2
7 22
AP21
AP23
VCCIO_5_PLLSATA
AF13
VCCIO_12_SATA3
VCCIO_13_SATA3
=PP1V05_S0_PCH_VCCIO_SATA
7 16 20 22
AP24
AF14
AP26
AT24
DCPRTC
VCCVRM_4_CLK
VCCADPLLA
VCCADPLLB
VCCAPLLSATA
AH14
VCCVRM_1_SATA
VCCDIFFCLKN
VCCDIFFCLKN
VCCDIFFCLKN
VCCIO_2_SATA
VCCIO_3_SATA
VCCIO_4_SATA
AK1
AF11
AN33
AC16
=PP1V05_S0_PCH_VCCIO_SATA
BH29
7 16 20 22
=PP1V8R1V5_S0_PCH_VCCVRM
AP16
T17
NC-ed per DG NC
2
22 7
17 16 7
V19
NC
PLACE_NEAR=U1800.V16:2.54mm
DCPSUS_1_CLK
DCPSUS_2_CLK
=PP1V05_S0_PCH_V_PROC_IO
BJ8
V_PROC_IO
=PPVRTC_G3_PCH
A22
VCCRTC
C2231
1
1
C2232
1UF
20%
10V
CERM
402
1
0.1UF
10%
6.3V
CERM
402
2
PLACE_NEAR=U1800.A22:2.54mm
2
VCCASW_22_MISC
VCCASW_23_MISC
VCCASW_21_MISC
T21
7
VCCSUSHDA
P32
=PP1V05_S0_PCH_VCCASW
AM38
C
AP36
AP37
VCC3_3_6_HVCMOS
VCC3_3_7_HVCMOS
7 22
V33
V34
AT16
=PP1V8R1V5_S0_PCH_VCCVRM
7 20
VCCDMI_1_DMI
AT20
=PP1V05_S0_PCH_VCC_DMI
7 22
VCCCLKDMI
VCCVRM_2_FDI
VCCAFDIPLL pin left as NC per DG
AD17
MISC
20%
10V
CERM
402
DCPSST
22
AM37
AB36
PP1V05_S0_PCH_VCCCLKDMI_F
22
7 19 22
VCCDFTERM
VCCDFTERM
VCCDFTERM
VCCDFTERM
AG16
=PP3V3_SUS_PCH_VCC_SPI
7 22
VCC3_3_3_PCIE
7 20
AC17
7
VCCVRM_3_DMI
VCCIO_25_DP
VCCIO_26_DP
=PP3V3_S0_PCH_VCC3_3_PCI
VCCSSC
CPU
1
0.1UF
VCCIO_17_PCIE
VCCIO_18_PCIE
VCCIO_19_PCIE
VCCIO_20_PCIE
VCCIO_21_PCIE
VCCIO_22_PCIE
VCCIO_23_PCIE
VCCIO_24_PCIE
22 7
NC VCCAPLLSATA pin left as NC per DG
=PP1V8R1V5_S0_PCH_VCCVRM
VCCTX_LVDS
VCCTX_LVDS
VCCTX_LVDS
VCCTX_LVDS
=PP3V3_S0_PCH_VCCA_LVDS
AK37
=PP3V3_S0_PCH_VCC3_3_HVCMOS
20 7
VCCIO_7_CLK
AK36
22
PP1V8_S0_PCH_VCCTX_LVDS_F
VCCALVDS
PP3V3_S0_PCH_VCCA_DAC_F
=PP1V8_S0_PCH_VCC_DFTERM
7 22
AH13
VCCIO_6_PLLSATA3
=PP3V3_S0_PCH_VCC3_3_SATA
U47
VSSALVDS
VCCIO_15_FDI
VCCIO_16_FDI
22 7
P22
AA16
U48
VCCAPLLEXP
7 22
P20
VCCADAC
VSSADAC
VCCIO_28_PLLPCIE
6
=PP3V3_SUS_PCH_VCCSUS_GPIO
N22
HDA
C2222
FCBGA
=PP1V05_S0_PCH_VCCIO_PLLPCIE
VCC3_3_2_SATA
RTC
B
MOBILE
(7 OF 10)
7
7
V16
PPVOUT_S0_PCH_DCPSST
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
U1800
PANTHERPOINT
CRT
7
AD21
AN34
0.1UF
20%
10V
CERM
402
N16
PPVOUT_G3_PCH_DCPRTC
=PP1V05_S0_PCH_VCCIO_PLLUSB
SATA
C2210
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
W33
T26
AC23
P28
HVCMOS
AL29
=PP1V05_S0_PCH_VCCIO_CLK
P26
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCIO
22 20 7
BH23
NC
AA23
DMI
VCCAPLLDMI2 pin left as NC per DG
OMIT_TABLE
=PP1V05_S0_PCH_VCC_CORE
1.44 A Max, 474mA Idle
7 22
NC
BG6
=PP1V05_S0_PCH_VCCIO_PLLFDI
AP17
=PP1V05_S0_PCH_VCCDMI_FDI
AU20
VCCAFDIPLL
VCCIO_27_PLLFDI
VCCDMI_2_FDI
FDI
T38
=PP1V05_S0_PCH_VCCIO_USB
DFT/SPI
PP3V3_S0_PCH_VCC3_3_CLK_F
USB
V12
CLK/MISC
T16
N26
PCI/GPIO/
LPC
22
=PP3V3_S5_PCH_VCCDSW
TP_PPVOUT_PCH_DCPSUSBYP
22 7
U1800
VCCIO_29_USB
PANTHERPOINT VCCIO_30_USB
VCCDSW3_3
MOBILE
VCCIO_31_USB
FCBGA
DCPSUSBYP
(8 OF 10) VCCIO_32_USB
VCCIO_33_USB
VCC3_3_5_CLK
VCCSUS3_3_7_USB
VCCAPLLDMI2
VCCSUS3_3_8_USB
VCCIO_14_PLLCLK
VCCSUS3_3_9_USB
VCCSUS3_3_10_USB
DCPSUS_3_CLK
VCCSUS3_3_6_USB
VCCASW_1_CLK
VCCIO_34_PLLUSB
VCCASW_2_CLK
VCCACLK
VCC CORE
22 7
AD49
NC
LVDS
OMIT_TABLE
VCCACLK pin left as NC per DG
VCCSPI
AG17
AJ16
AJ17
V1
7 20 22
B
V21
T19
=PP3V3R1V5_S0_PCH_VCCSUSHDA
7 22 24
10 mA Max, 1mA Idle
C2233
0.1UF
2
20%
10V
CERM
402
PLACE_NEAR=U1800.A22:2.54mm
PLACE_NEAR=U1800.A22:2.54mm
A
SYNC_MASTER=J5_MLB
SYNC_DATE=03/21/2011
PAGE TITLE
PCH POWER
DRAWING NUMBER
Apple Inc.
051-9585
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
3.0.0
BRANCH
PAGE
22 OF 132
SHEET
20 OF 105
1
A
8
7
6
5
4
3
OMIT_TABLE
H5
AA17
AA2
AA3
AA33
AA34
AB11
AB14
AB39
AB4
D
AB43
AB5
AB7
AC19
AC2
AC21
AC24
AC33
AC34
AC48
AD10
AD11
AD12
AD13
AD19
AD24
AD26
AD27
AD33
AD34
AD36
AD37
AD38
AD39
AD4
AD40
AD42
C
AD43
AD45
AD46
AD8
AE2
AE3
AF10
AF12
AD14
AD16
AF16
AF19
AF24
AF26
AF27
AF29
AF31
AF38
AF4
AF42
AF46
AF5
AF7
AF8
AG19
AG2
B
AG31
AG48
AH11
AH3
AH36
AH39
AH40
AH42
AH46
AH7
AJ19
AJ21
AJ24
AJ33
AJ34
AK12
AK3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
U1800
PANTHERPOINT
MOBILE
FCBGA
(9 OF 10)
VSS
AY4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AK38
AY42
AK4
AY46
AK42
AY8
AK46
B11
AK8
B15
AL16
B19
AL17
B23
AL19
B27
AL2
B31
AL21
B35
AL23
B39
AL26
B7
AL27
F45
AL31
BB12
AL33
BB16
AL34
BB20
AL48
BB22
AM11
BB24
AM14
BB28
AM36
BB30
AM39
BB38
AM43
BB4
AM45
BB46
AM46
BC14
AM7
BC18
AN2
BC2
AN29
BC22
AN3
BC26
AN31
BC32
AP12
BC34
AP19
BC36
AP28
BC40
AP30
BC42
AP32
BC48
AP38
BD46
AP4
BD5
AP42
BE22
AP46
BE26
AP8
BE40
AR2
BF10
AR48
BF12
AT11
BF16
AT13
BF20
AT18
BF22
AT22
BF24
AT26
BF26
AT28
BF28
AT30
BD3
AT32
BF30
AT34
BF38
AT39
BF40
AT42
BF8
AT46
BG17
AT7
BG21
AU24
BG33
AU30
BG44
AV11
BG8
AV16
BH11
AV20
BH15
AV24
BH17
AV30
BH19
AV38
H10
AV4
BH27
AV43
BH31
AV8
BH33
AW14
BH35
AW18
BH39
AW2
BH43
AW22
BH7
AW26
D3
AW28
D12
AW32
D16
AW34
D18
AW36
D22
AW40
D24
AW48
D26
AY12
D30
AY22
D32
AY28
D34
D38
D42
D8
E18
E26
G18
G20
G26
G28
A
G36
G48
H12
H18
H22
H24
H26
H30
H32
H34
F3
8
7
2
1
OMIT_TABLE
6
5
4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
3
U1800
PANTHERPOINT
MOBILE
FCBGA
(10 OF 10)
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
H46
K18
K26
K39
K46
K7
L18
L2
L20
L26
D
L28
L36
L48
M12
P16
M18
M22
M24
M30
M32
M34
M38
M4
M42
M46
M8
N18
P30
N47
P11
P18
T33
P40
P43
P47
P7
R2
C
R48
T12
T31
T37
T4
W34
T46
T47
T8
V11
V17
V26
V27
V29
V31
V36
V39
V43
V7
W17
W19
W2
W27
W48
Y12
Y38
B
Y4
Y42
Y46
Y8
BG29
N24
AJ3
AD47
VSS
VSS
VSS
B43
VSS
VSS
G14
VSS
T36
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
BE10
BG41
H16
BG22
BG24
C22
AP13
M14
AP3
AP1
BE16
SYNC_MASTER=J5_MLB
SYNC_DATE=03/21/2011
PAGE TITLE
BC16
PCH GROUNDS
BG28
DRAWING NUMBER
BJ28
Apple Inc.
051-9585
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
2
SIZE
D
REVISION
3.0.0
BRANCH
PAGE
23 OF 132
SHEET
21 OF 105
1
A
8
20 7
7
7
=PP3V3_SUS_PCH_VCCSUS
=PP5V_SUS_PCH
24 7
3
1
NC
1
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=5V
MAKE_BASE=TRUE
C2439
20%
10V
CERM
402
1
C2486
0.1UF
6
1
1
=PP1V05_S0_PCH_VCCSSC
C2475
1
2
PP5V_S0_PCH_V5REF
0.1UF
D
20 7
SOT-363
& lt; 1 mA S0-S5
1
=PP3V3_S0_PCH_VCC3_3_GPIO
BAT54DW-X-G
NC
5%
1/16W
MF-LF
402
SOT-363
20 7
2
D2400
5
PP5V_SUS_PCH_V5REFSUS
C2438
3
1
2
100
BAT54DW-X-G
NC
NC
R2405
D2400
2
4
PCH V5REF Filter & Follower
(PCH Reference for 5V Tolerance on PCI)
1 mA
4
2
10
5%
1/16W
MF-LF
402
5
=PP3V3_S0_PCH
=PP5V_S0_PCH
16 7
PCH V5REF_SUS Filter & Follower
(PCH Reference for 5V Tolerance on USB)
1 mA S0-S5
R2404
6
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=5V
MAKE_BASE=TRUE
& lt; 1 mA
10%
6.3V
CERM
402
0.1UF
10%
25V
X5R
402
2
1
1UF
C2485
10%
25V
X5R
402
2
PLACE_NEAR=U1800.AG33:2.54mm
PLACE_NEAR=U1800.T34:2.54mm
PLACE_NEAR=U1800.AA16:2.54mm
D
1UF
=PP5V_SUS_PCH_V5REFSUS
10%
10V
X5R
402
20
2
PLACE_NEAR=U1800.M26:2.54mm
=PP5V_S0_PCH_V5REF
20
20 16 7
=PP1V05_S0_PCH_VCCDIFFCLK
2
PLACE_NEAR=U1800.P34:2.54mm
20 7
C2434
=PP3V3_S0_PCH_VCC3_3_HVCMOS
1
1UF
C2424
10%
6.3V
CERM
402
1
0.1UF
10%
16V
X5R
402
2
PLACE_NEAR=U1800.AF34:2.54mm
2
PLACE_NEAR=U1800.V33:2.54mm
CRITICAL
20 7
L2407
7
0.1UH
=PP1V8_S0_PCH_VCCTX_LVDS
PP1V8_S0_PCH_VCCTX_LVDS_F
1
20
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=1.8V
2
0805
20 7
=PP3V3_S5_PCH_VCCDSW
20 7
C2499
C2421
1
0.1UF
1
1
2
2
22UF
C2406
1
10%
16V
CERM
402
10%
16V
X5R
402
0.01UF
10%
16V
CERM
402
2
10%
6.3V
CERM
402
1
0.1UF
20%
10V
CERM
402
C2408
0.01UF
20%
6.3V
X5R-CERM-1
603
C2469
=PP3V3_S0_PCH_VCC3_3_PCI
2
PLACE_NEAR=U1800.T16:2.54mm
2
PLACE_NEAR=U1800.BH29:2.54mm
20 16 7
20 7
=PP3V3_SUS_PCH_VCC_SPI
20 7
=PP1V05_S0_PCH_VCCIO_SATA
=PP3V3_S0_PCH_VCC3_3_SATA
C2444
R2450
=PP3V3_S0_PCH_VCCADAC
0
1
20
C2423
1
1UF
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
2
5%
1/20W
MF
201
C
C2442
PP3V3_S0_PCH_VCCA_DAC_F
10%
6.3V
CERM
402
10%
16V
X5R
402
PLACE_NEAR=U1800.V1:2.54mm
2
C2450
1
2
2
10UF
C2451
1
10%
16V
X5R
402
2
C
PCH VCCIO BYPASS
(PCH USB 1.05V PWR)
0.01UF
10%
16V
CERM
402
2
2
PLACE_NEAR=U1800.AH13:2.54mm
PLACE_NEAR=U1800.AC17:2.54mm
PLACE_NEAR=U1800.AJ2:2.54mm
C2455
0.1UF
20%
6.3V
X5R
603
10%
6.3V
CERM
402
1
1UF
10%
6.3V
CERM
402
0.1UF
2
C2452
1
1UF
1
CRITICAL
1
2
PLACE_NEAR=U1800.AF17:2.54mm
PLACE_NEAR=U1800.AM37:2.54mm
PLACE_NEAR=U1800.AM37:2.54mm
PLACE_NEAR=U1800.AM37:2.54mm
7
1
1UF
CRITICAL
C2400
=PP1V05_S0_PCH_VCCIO_CLK
20 7
=PP3V3_SUS_PCH_VCCSUS_GPIO
20 7
C2476
PLACE_NEAR=U1800.U48:2.54mm
PLACE_NEAR=U1800.U48:2.54mm
PLACE_NEAR=U1800.U48:2.54mm
=PP1V05_S0_PCH_VCCIO_USB
C2446
1
1UF
10%
6.3V
CERM
402
1
1UF
10%
6.3V
CERM
402
2
PLACE_NEAR=U1800.P22:2.54mm
2
PLACE_NEAR=U1800.P28:2.54mm
PCH VCCSUS3_3 BYPASS
(PCH SUSPEND USB 3.3V PWR)
20 7
=PP3V3_SUS_PCH_VCCSUS_USB
20 7
=PP1V05_S0_PCH_VCCIO
CRITICAL
L2451
7
R2451
=PP3V3_S0_PCH_VCC3_3_CLK
1
1
10UH-0.12A-0.36OHM
1
PP3V3_S0_PCH_VCC3_3_CLK_R
2
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.075 MM
VOLTAGE=3.3V
5%
1/16W
MF-LF
402
PP3V3_S0_PCH_VCC3_3_CLK_F
1
20
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.075 MM
VOLTAGE=3.3V
2
0603
CRITICAL
1
1
2
2
10UF
20%
6.3V
X5R
603
C2454
R2490
0
10UH-0.12A-0.36OHM
PP1V05_S0_PCH_VCCADPLLA_R
2
1
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
5%
1/16W
MF-LF
402
2
PP1V05_S0_PCH_VCCADPLLA_F
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
2
0603
CRITICAL
C2491
1
20 7
2.5V 2
TANT
B16
2
C2414
1
C2407
1UF
10%
6.3V
CERM
402
1
1UF
10%
6.3V
CERM
402
10%
6.3V
CERM
402
2
2
2
2
C2463
1UF
2
10%
6.3V
CERM
402
1
C2496
=PP1V05_S0_PCH_VCCASW
C2420
1
0.1UF
20
20%
10V
CERM
402
68 mA
1
C2428
22UF
20%
6.3V
X5R-CERM-1
603
2
PLACE_NEAR=U1800.P32:2.54mm
1
1
2
2
22UF
2
20%
6.3V
X5R-CERM-1
603
C2426
1
1UF
10%
6.3V
CERM
402
C2456
1UF
2
1UF
10%
6.3V
CERM
402
2
10%
6.3V
CERM
402
1
C2483
PLACE_NEAR=U1800.AC27:2.54mm
PLACE_NEAR=U1800.AC27:2.54mm
PLACE_NEAR=U1800.AC27:2.54mm
PLACE_NEAR=U1800.AC27:2.54mm
PLACE_NEAR=U1800.AC27:2.54mm
C2492
20 19 7
1
1UF
B
C2441
10%
6.3V
CERM
402
C2429
PLACE_NEAR=U1800.AN27:2.54mm
PLACE_NEAR=U1800.AN27:2.54mm
PLACE_NEAR=U1800.AN27:2.54mm
PLACE_NEAR=U1800.AN27:2.54mm
PLACE_NEAR=U1800.AN27:2.54mm
1UF
220UF
(Z = 1.2MM, PLACE ON SHORT SIDE BEHIND PCH) 20%
1
=PP3V3R1V5_S0_PCH_VCCSUSHDA
NO STUFF
1
1
10UF
20%
6.3V
X5R
603
PCH VCCADPLLA Filter
(PCH DPLLA PWR)
L2490
1
10%
16V
X5R
402
PCH VCCSUSHDA BYPASS
CRITICAL
=PP1V05_S0_PCH_VCCADPLL
C2401
0.1UF
10%
10V
X5R
402
24 20 7
7
C2413
10%
16V
X5R
402
PLACE_NEAR=U1800.P24:2.54mm
PLACE_NEAR=U1800.V24:2.54mm
1UF
PLACE_NEAR=U1800.T38:2.54mm
PLACE_NEAR=U1800.T38:2.54mm
B
1
0.1UF
2
C2453
C2484
PCH VCCCORE BYPASS
(PCH 1.05V CORE PWR)
=PP1V8_S0_PCH_VCC_DFTERM
20 7
PLACE_NEAR=U1800.BD47:2.54MM
PLACE_NEAR=U1800.BD47:2.54MM
C2440
=PP1V05_S0_PCH_VCC_CORE
1
0.1UF
L2491
R2491
1
0
5%
1/16W
MF-LF
402
10UH-0.12A-0.36OHM
PP1V05_S0_PCH_VCCADPLLB_R
2
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
20%
10V
CERM
402
PCH VCCADPLLB Filter
(PCH DPLLB PWR)
CRITICAL
1
PP1V05_S0_PCH_VCCADPLLB_F
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
2
0603
CRITICAL
1
2.5V 2
TANT
B16
2
C2493
C2494
10%
6.3V
CERM
402
C2416
20%
6.3V
X5R
402
1
2
2
C2417
1
0.1UF
R2415
2
PP1V05_S0_PCH_VCCCLKDMI_R
1098AS-SM
(Z = 1.2MM, PLACE ON SHORT SIDE BEHIND PCH)
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=1.05V
1
0
PP1V05_S0_PCH_VCCCLKDMI_F
2
2
5%
1/16W
MF-LF
402
2
2
1UF
2
10%
6.3V
CERM
402
SYNC_MASTER=J5_MLB
DRAWING NUMBER
Apple Inc.
10%
6.3V
CERM
402
2
NOTICE OF PROPRIETARY PROPERTY:
2
PLACE_NEAR=U1800.AT20:2.54mm
PCH VCCIO BYPASS
PLACE_NEAR=U1800.AB36:2.54mm
PCH VCC3_3 BYPASS
(PCH PCI 3.3V PWR)
5
4
051-9585
3
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
2
SIZE
D
REVISION
R
1
1UF
1
6
SYNC_DATE=05/26/2011
PAGE TITLE
=PP1V05_S0_PCH_VCC_DMI
10UF
7
2
PCH DECOUPLING
C2419
8
10%
6.3V
CERM
402
10%
16V
X5R
402
20
20 7
20%
6.3V
X5R
603
1UF
C2430
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=1.05V
C2411
C2482
10%
6.3V
CERM
402
0.1UF
10%
16V
X5R
402
PLACE_NEAR=U1800.BJ8:2.54mm
PLACE_NEAR=U1800.BJ8:2.54mm
PLACE_NEAR=U1800.BJ8:2.54mm
L2406
10UH-0.58A-0.35OHM
1
1
4.7UF
CRITICAL
=PP1V05_S0_PCH
1
1UF
PLACE_NEAR=U1800.AG26:2.54mm
PLACE_NEAR=U1800.AD21:2.54mm
PLACE_NEAR=U1800.AG24:2.54mm
PLACE_NEAR=U1800.AJ27:2.54mm
=PP1V05_S0_PCH_V_PROC_IO
PLACE_NEAR=U1800.BF47:2.54MM
PLACE_NEAR=U1800.BF47:2.54MM
16 7
C2481
1UF
220UF
(Z = 1.2MM, PLACE ON SHORT SIDE BEHIND PCH) 20%
A
1
20%
6.3V
X5R
603
69 mA
20 7
1
10UF
20
NO STUFF
1
C2460
2
PLACE_NEAR=U1800.AJ16:2.54mm
3.0.0
BRANCH
PAGE
24 OF 132
SHEET
22 OF 105
1
A
8
7
6
5
23 7
4
R2510
51
2
93 23 10
XDP_CPU_TDI
R2511
51
2
93 23 10
XDP_CPU_TMS
R2512
51
2
93 23 10
XDP_CPU_TCK
R2513
51
2
93 23 10
XDP_CPU_TRST_L
R2514
51
2
5%
M-ST-SM
5%
62
61
XDP
93 10
(R2560-R2563)
BI
IN
1
4
3
6
OBSFN_A0
OBSFN_A1
5
7
OBSDATA_A0
OBSDATA_A1
IN
93 10
IN
1
2
1
2
1/20W
MF
18
5%
1/20W
MF
1/20W
MF
201
1/20W
MF
201
93 10
IN
93 10
IN
22
93 9
IN
93 9
IN
93 9
IN
93 9
R2564
R2565
R2566
R2567
CPU_CFG & lt; 12 & gt;
CPU_CFG & lt; 13 & gt;
CPU_CFG & lt; 14 & gt;
CPU_CFG & lt; 15 & gt;
IN
93 9
IN
0
0
0
0
1
2
1
2
1
2
5%
1/20W
MF
201
5%
1/20W
MF
5%
1/20W
MF
201
5%
1/20W
MF
201
93 19 10
IN
CPU_PWRGD
OUT
PM_PWRBTN_L
OUT
CPU_CFG & lt; 0 & gt;
1K
1
R2500
PLACE_NEAR=U1000.C60:2.54mm
2
93
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
XDP
45 23 17
0
1
R2502
PLACE_NEAR=U4900.P17:2.54mm
2
XDP_CPU_CFG & lt; 0 & gt;
XDP_VR_READY
XDP
93 23 9
1K
1
R2501
PLACE_NEAR=U1000.B57:2.54mm
48 23
BI
48 23
IN
XDP
92 45 17
R2504
PM_PCH_SYS_PWROK
OUT
330
1
2
C
93 23 10
OUT
XDP_CPU_TCK
(R2520-R2537)
XDP SIGNALS
23
OUT
23
OUT
23
OUT
23
OUT
33
33
33
33
47
49
52
51
54
53
56
55
58
57
59
PCH SIGNALS
2
1
2
1
2
1
2
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L
XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L
XDP_DA2_PCH_GPIO41_USB_EXTC_OC_L
XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L
C2500
201
10%
16V
X5R
402
IN
9 93
IN
9 93
XDP
R2515
0
1
2
PLACE_NEAR=R1841.1:2.54mm
ITPXDP_CLK100M_P
5%
1/20W
MF
PLACE_NEAR=U1000.G3:2.54mm
2
CPU_RESET_L
IN
5%
1/20W
MF
201
5%
1
1/20W
MF
33
33
33
33
33
1
OUT
R2524
R2525
R2526
R2527
R2528
1
2
OUT
XDP_FC1
R2529
33
1
2
OUT
23
IN
23
OUT
23
23
23
IN
23
IN
23
IN
23
IN
23
IN
23
IN
23
23
IN
IN
2
1
2
1
2
1
2
5%
1/20W
5%
1/20W
5%
1/20W
5%
1/20W
5%
1/20W
XDP_DB0_PCH_GPIO43_USB_EXTB_OC_EHCI_L
MF
201
XDP_DB1_PCH_GPIO9_USB_EXTD_OC_EHCI_L
MF
201
XDP_DB2_PCH_GPIO10_AP_PWR_EN
MF
201
XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE
MF
201
XDP_FC0_PCH_GPIO15
1
64
63
C2501
IN
18 23
IN
18
23 18
OUT
IN
18 23
23 18
OUT
2
998-2516
2
Non-XDP Signals
10%
16V
X5R
402
18 23
R2590
R2591
R2596
R2597
0
0
0
0
MF
XDP_FC1_PCH_GPIO0
5%
R2530
R2531
R2532
R2533
R2534
R2535
XDP_DC0_ISOLATE_CPU_MEM_L
XDP_DC1_MXM_GOOD
XDP_DC2_DP_AUXCH_ISOL
XDP_DC3_SATARDRVR_EN
XDP_DD0_DP_GPU_TBT_SEL
XDP_DD1_JTAG_ISP_TCK
33
33
33
33
33
33
1
2
1
2
1/20W
MF
5%
1/20W
MF
5%
1/20W
201
MF
XDP_DC0_PCH_GPIO28_ISOLATE_CPU_MEM_L
201
XDP_DC1_PCH_GPIO35_MXM_GOOD
201
XDP_DC2_PCH_GPIO21_DP_AUXCH_ISOL
201
XDP_DC3_PCH_GPIO19_SATARDRVR_EN
201
XDP_DD0_PCH_GPIO36_DP_GPU_TBT_SEL
201
XDP_DD1_PCH_GPIO37_JTAG_ISP_TCK
2
1
201
1
2
1
2
1
2
5%
1/20W
MF
B
33
33
1
2
MF
1/20W
MF
5%
XDP_DD2_PCH_GPIO16_AUD_IPHS_SWITCH_EN_PCH
1/20W
MF
201
XDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCH
1/20W
2
1
1/20W
5%
R2536
R2537
1/20W
5%
5%
XDP_DD2_AUD_IPHS_SWITCH_EN
XDP_DD3_ENET_LOW_PWR
5%
MF
201
MF
IN
18 23
18 23
IN
18 23
IN
OUT
19 23
OUT
OUT
16 23
OUT
19
OUT
19 23
OUT
PCH Micro2-XDP
19
OUT
OUT
4
6
IN
ALL_SYS_PWRGD
OUT
PM_PWRBTN_L
R2584
1K
1
PLACE_NEAR=J2550.39:2.54mm
XDP_DA0_USB_EXTA_OC_L
XDP_DA1_USB_EXTB_OC_L
OBSDATA_A0
OBSDATA_A1
9
12
11
5%
1/20W
MF
201
16
15
18
17
21
24
23
27
30
29
33
36
35
1/20W
MF
201
6
6
A
48 23
48 23
23 16
BI
IN
OUT
39
OBSDATA_B0
OBSDATA_B1
XDP_DB2_AP_PWR_EN
XDP_DB3_SDCONN_STATE_CHANGE
OBSDATA_B2
OBSDATA_B3
PWRGD/HOOK0
HOOK1
VCC_OBS_AB
HOOK2
HOOK3
TP_XDPPCH_HOOK2
TP_XDPPCH_HOOK3
42
1K
1
XDP_PCH_TCK
XDP_DB0_PCH_GPIO43_USB_EXTB_OC_EHCI_L
2
5%
23 18
5%
XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L
8
R2581
7
1K
1
1/20W
1/20W
MF
MF
10%
16V
X5R
402
18 23
201
XDP_DB1_PCH_GPIO9_USB_EXTD_OC_EHCI_L
2
OUT
OUT
OUT
XDP_DD1_PCH_GPIO37_JTAG_ISP_TCK
XDP_DD2_PCH_GPIO16_AUD_IPHS_SWITCH_EN_PCH
XDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCH
201
SATARDRVR_EN
1/20W
MF
MF
18 32 74
26
OUT
16 87
OUT
201
16 41
OUT
201
1/20W
42
24
OUT
ISOLATE_CPU_MEM_L
DP_AUXCH_ISOL
R2575
R2576
R2577
0
0
0
1
2
1
2
1
2
5%
1/20W
5%
1/20W
5%
1/20W
JTAG_ISP_TCK
MF
201
AUD_IPHS_SWITCH_EN_PCH
MF
201
ENET_LOW_PWR_PCH
MF
8 19
OUT
19 24
OUT
201
19 24
OBSDATA_D2
OBSDATA_D3
XDP_DD2_AUD_IPHS_SWITCH_EN
XDP_DD3_ENET_LOW_PWR
23
23
23
23
23
R2551
51
2
XDP_PCH_TMS
R2552
51
201
1
XDP
23 16
MF
2
1/20W
MF
201
PLACE_NEAR=U1800.H7:2.54mm
1
XDP
1/20W
MF
201
PLACE_NEAR=U1800.J3:2.54mm
1
5%
1/20W
MF
201
SYNC_DATE=06/09/2011
CPU & PCH XDP
Apple Inc.
1
63
C2581
DRAWING NUMBER
051-9585
10%
16V
X5R
402
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
4
3
2
D
3.0.0
0.1uF
2
SIZE
REVISION
R
18 23
5
XDP_PCH_TDI
23
1/20W
PLACE_NEAR=U1800.K5:2.54mm
5%
59
998-2516
PLACE_NEAR=J2550.52:2.54mm
1
5%
XDP
2
2
TP_XDP_PCH_HOOK4
ITPCLK/HOOK4
51
2
XDP_PCH_TCK
R2556
23 16
ITPCLK#/HOOK5 TP_XDP_PCH_HOOK5
VCC_OBS_CD
XDPPCH_PLTRST_L
RESET#/HOOK6
1K series R on PCH Support Page
IN 24
XDP_DBRESET_L
DBR#/HOOK7
OUT 10 23 24 93
NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page
XDP_PCH_TDO
TDO
IN 16 23
SYNC_MASTER=J31_ANNE
TP_XDP_PCH_TRST_L
TRSTn
PAGE TITLE
XDP_PCH_TDI
TDI
OUT 16 23
XDP_PCH_TMS
TMS
OUT 16 23
XDP_PRESENT#
57
64
51
XDP
23
201
6
R2550
5%
55
1
=PP1V05_SUS_PCH_JTAG
XDP
XDP_PCH_TDO
23
23 16
53
56
XDP_DD0_DP_GPU_TBT_SEL
XDP_DD1_JTAG_ISP_TCK
23
23 16
51
58
NC
TP_XDP_PCH_OBSFN_D & lt; 0 & gt;
TP_XDP_PCH_OBSFN_D & lt; 1 & gt;
OBSDATA_D0
OBSDATA_D1
49
54
XDP_DC2_DP_AUXCH_ISOL
XDP_DC3_SATARDRVR_EN
23
7
47
52
XDP_DC0_ISOLATE_CPU_MEM_L
XDP_DC1_MXM_GOOD
OBSFN_D0
OBSFN_D1
45
48
XDP_FC0
XDP_FC1
OBSDATA_C2
OBSDATA_C3
43
46
0.1uF
R2580
IN
42
7
OBSDATA_C0
OBSDATA_C1
41
44
SDA
SCL
TCK1
TCK0
=SMBUS_XDP_SDA
=SMBUS_XDP_SCL
C2580
XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L
MF
2
5%
OBSFN_C0
OBSFN_C1
XDP
23 18
1/20W
OUT
201
37
40
XDP_DB0_USB_EXTB_OC_EHCI_L
XDP_DB1_USB_EXTD_OC_EHCI_L
2
5%
1
MF
5%
31
34
OBSFN_B0
OBSFN_B1
60
0
1
PLACE_NEAR=U4900.P17:2.54mm
2
0
1/20W
5%
R2573
25
28
OBSDATA_A2
OBSDATA_A3
50
R2585
1
MF
19
22
XDP_DA2_USB_EXTC_OC_L
XDP_DA3_USB_EXTD_OC_L
XDP
45 23 17
0
1/20W
IN
13
XDP_PCH_S5_PWRGD
XDP_PCH_PWRBTN_L
2
R2572
201
5%
IN
201
MF
7
XDP
92 89 74 45
XDP_DC2_PCH_GPIO21_DP_AUXCH_ISOL
MF
1/20W
B
5
10
38
23
IN
23 19
3
32
23
2
2
1/20W
5%
1
OBSFN_A0
OBSFN_A1
26
23
1
23 19
19 23
TP_XDP_PCH_OBSFN_B & lt; 0 & gt;
TP_XDP_PCH_OBSFN_B & lt; 1 & gt;
23
0
23 19
61
20
R252x, R253x, R257x and R259x should be placed where signal path
needs to split between route from PCH to J2550
and path to non-XDP signal destination.
R2570
M-ST-SM
62
14
23
XDP_DC0_PCH_GPIO28_ISOLATE_CPU_MEM_L
1
5%
5%
J2550
8
23
OUT
=PP3V3_S5_XDP
19 23
2
23
23 19
2
CRITICAL
XDP_CONN_PCH
TP_XDP_PCH_OBSFN_A & lt; 0 & gt;
TP_XDP_PCH_OBSFN_A & lt; 1 & gt;
23
XDP_DC3_PCH_GPIO19_SATARDRVR_EN
2
1
USB_EXTA_OC_L
USB_EXTB_OC_L
AP_PWR_EN
201
SDCONN_STATE_CHANGE
2
1
16 23
PCH/XDP Signal Isolation Notes:
- Following Intel’s Debug Prot Design Guid for HR and CR v1.3
doc id 404081.
Initially, stuffing both 33 and 0 ohms and validate whether
it is functional in that state, else add BOM options.
- For isolated GPIOs:
- ’Output’ non-XDP signals require pulls.
- ’Output’ PCH/XDP signals require pulls.
IN
23 16
1
19
DF40RC-60DP-0.4V
201
OUT
XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L
XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L
XDP_DB2_PCH_GPIO10_AP_PWR_EN
XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE
19 68
IN
NOTE: This is not the standard XDP pinout.
Use with 921-0133 Adapter Flex to
support chipset debug.
IN
23 18
18 23
OUT
10 24
C
PCH SIGNALS
0.1uF
IN
IN
201
201
16 93
XDP
23 16
23
XDP_DB0_USB_EXTB_OC_EHCI_L
XDP_DB1_USB_EXTD_OC_EHCI_L
XDP_DB2_AP_PWR_EN
XDP_DB3_SDCONN_STATE_CHANGE
XDP_FC0
OUT
IN
PLACE_NEAR=R1840.1:2.54mm
2
ITPXDP_CLK100M_N
1
MF
16 93
XDP
23 18
23
IN
201
1/20W
XDP
1
0.1uF
1
9 93
CPU_CFG & lt; 6 & gt;
CPU_CFG & lt; 7 & gt;
5%
ITPCLK/HOOK4 93 XDP_CPU_CLK100M_P
0
R2516
ITPCLK#/HOOK5 93 XDP_CPU_CLK100M_N
VCC_OBS_CD
XDP_CPURST_L
RESET#/HOOK6
1K
XDP_DBRESET_L
R2505
DBR#/HOOK7
OUT 10 23 24 93
NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page
XDP_CPU_TDO
TDO
IN 10 23 93
XDP_CPU_TRST_L
TRSTn
OUT 10 23 93
XDP_CPU_TDI
TDI
OUT 10 23 93
XDP_CPU_TMS
TMS
OUT 10 23 93
XDP_PRESENT#
XDP
XDP
R2520
R2521
R2522
R2523
XDP_DA0_USB_EXTA_OC_L
XDP_DA1_USB_EXTB_OC_L
XDP_DA2_USB_EXTC_OC_L
XDP_DA3_USB_EXTD_OC_L
45
48
NC
43
46
SDA
SCL
TCK1
TCK0
=SMBUS_XDP_SDA
=SMBUS_XDP_SCL
41
44
2
39
42
PWRGD/HOOK0
HOOK1
VCC_OBS_AB
HOOK2
HOOK3
XDP_CPU_PWRGD
XDP_CPU_PWRBTN_L
9 93
IN
37
40
XDP
35
IN
OBSDATA_D2
OBSDATA_D3
33
CPU_CFG & lt; 4 & gt;
CPU_CFG & lt; 5 & gt;
31
36
OBSDATA_B2
OBSDATA_B3
XDP_OBSDATA_B & lt; 2 & gt;
XDP_OBSDATA_B & lt; 3 & gt;
29
9 93
OBSDATA_D0
OBSDATA_D1
27
34
201
9 93
IN
D
201
25
30
OBSDATA_B0
OBSDATA_B1
XDP_OBSDATA_B & lt; 0 & gt;
XDP_OBSDATA_B & lt; 1 & gt;
2
1
IN
MF
9 93
CPU_CFG & lt; 8 & gt;
CPU_CFG & lt; 9 & gt;
1/20W
1
9 93
IN
OBSFN_D0
OBSFN_D1
23
28
XDP_CPU:CFG
IN
201
9 93
OBSDATA_C2
OBSDATA_C3
21
24
OBSFN_B0
OBSFN_B1
CPU_CFG & lt; 10 & gt;
CPU_CFG & lt; 11 & gt;
IN
93 9
(R2564-R2567)
OBSDATA_A2
OBSDATA_A3
IN
MF
PLACE_NEAR=U1000.H63:2.54mm
XDP
9 23 93
CPU_CFG & lt; 2 & gt;
CPU_CFG & lt; 3 & gt;
1/20W
PLACE_NEAR=U1000.J58:2.54mm
5%
IN
201
1
9 93
CPU_CFG & lt; 0 & gt;
CPU_CFG & lt; 1 & gt;
MF
19
32
201
5%
XDP_BPM_L & lt; 2 & gt;
XDP_BPM_L & lt; 3 & gt;
17
20
201
15
26
5%
IN
1/20W
13
50
2
11
16
2
1
IN
12
38
1
5%
IN
93 10
0
0
0
0
IN
9 93
OBSDATA_C0
OBSDATA_C1
9
60
93 10
R2560
R2561
R2562
R2563
XDP_BPM_L & lt; 4 & gt;
XDP_BPM_L & lt; 5 & gt;
XDP_BPM_L & lt; 6 & gt;
XDP_BPM_L & lt; 7 & gt;
IN
IN
93 10
XDP_CPU:BPM
93 10
XDP_BPM_L & lt; 0 & gt;
XDP_BPM_L & lt; 1 & gt;
10
14
93 10
CPU_CFG & lt; 16 & gt;
CPU_CFG & lt; 17 & gt;
201
PLACE_NEAR=U1000.H59:2.54mm
XDP
OBSFN_C0
OBSFN_C1
MF
1
5%
2
2
XDP_CPU_PREQ_L
XDP_CPU_PRDY_L
1/20W
PLACE_NEAR=U1000.K61:2.54mm
1
1
8
D
PLACE_NEAR=J2500.52:2.54mm
1
XDP
1K
93 10
=PPVCCIO_S0_XDP
XDP
XDP_CPU_TDO
93 23 10
DF40RC-60DP-0.4V
NO STUFF
5%
1/16W
MF-LF
402
1
23 7
NOTE: This is not the standard XDP pinout.
Use with 921-0133 Adapter Flex to
support chipset debug.
J2500
=PP3V3_S0_XDP
R2540
2
CPU Micro2-XDP
=PPVCCIO_S0_XDP
CRITICAL
XDP_CONN_CPU
7
3
BRANCH
PAGE
25 OF 132
SHEET
23 OF 105
1
A
8
7
6
5
4
3
2
1
Ethernet WAKE# Isolation
=PP3V3_ENET_PHY
GPIO Glitch Prevention
Platform Reset Connections
7 36 72
Unbuffered
CRITICAL
1
Q2630
=PP3V3_S3_PCH_GPIO
24 18 7
R2630
1
G
SSM3K15FV
SOD-VESM-HF
2
32 17 6
0.1UF
VCC
U2150
D
C2150
2
SOT833
PCIE_WAKE_L
OUT
3
20%
10V
CERM
402
IN
LPC_RESET_L
33
1
2
5%
1/16W
MF-LF
402
=ENET_WAKE_L
IN
MAKE_BASE=TRUE
2
IN
19
IN
2
5
6
74LVC2G08GT
IN
92 24 17
1
ENET_LOW_PWR_PCH
PM_PCH_PWROK
FW_PWR_EN_PCH
A1
B1
A2
B2
Y1
Y2
7
ENET_LOW_PWR
OUT
FW_PWR_EN
OUT
39
PCH Reset Button
1
=PP3V3_S0_SB_PM
92 7
1
R2696
93 23 10
XDP_DBRESET_L
IN
0
1
2
1
PM_SYSRST_L
2
VCC
U2152
2
SOT833
SDCONN_STATE_CHANGE
7
20%
10V
CERM
402
92 24 17
IN
23 19
IN
1
TBT_PWR_EN_PCH
PM_PCH_PWROK
AUD_IPHS_SWITCH_EN_PCH
2
5
6
74LVC2G08GT
IN
A1
B1
A2
B2
Y1
7
=PP3V3_S3_SDBUF
1
2
Y2
3
AUD_IPHS_SWITCH_EN
63
OUT
GND
0
SDCONN_STATE_CHANGE
4
Y
OUT
23
OUT
89
OUT
39
GMUX_RESET_L
2
MAKE_BASE=TRUE
5%
1/16W
MF-LF
402
=GMUX_PCIE_RESET_L
SILK_PART=SYS RESET
C2630
=FW_RESET_L
10%
6.3V
X5R
201
Buffered
Series R is R4283
Note: Based on K91/K92 layout, ENET,AP and BKLT are moved to Buffered reset.
=PP3V3_S0_RSTBUF
CRITICAL
TC7SZ08FEAPE 5
SOT665
4
23
XDPPCH_PLTRST_L
2
5%
1/16W
MF-LF
402
24 7
C
1K
0.1UF
35
OUT
31
R2687
1
R2697
2
TBT_PWR_EN
OUT
5%
1/16W
MF-LF
402
6 17 45
0
08
16
BI
OMIT
0.1UF
PCA9557D_RESET_L
2
R2689
1
C2152
0
XDP
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
=PP3V3_S3_PCH_GPIO
8
D
R2695
XDP
CRITICAL
45
SMC_LRESET_L
2
5%
1/16W
MF-LF
402
4.7K
4
1
33
5%
1/16W
MF-LF
402
R2671
GND
24 18 7
OUT
R2683
30 36
3
6 47
36
08
23 19
89 96
OUT
MAKE_BASE=TRUE
5%
1/16W
MF-LF
402
ENET_WAKE_L
OUT
LPCPLUS_RESET_L
R2681
PLT_RESET_L
MAKE_BASE=TRUE
1
S
1
8
D
CRITICAL
26 18
10K
CRITICAL
C
2
A
5
MC74VHC1G08
1
U2630
B
1
SDCONN_STATE_CHANGE_SMC
SC70-HF
30 46
4
U2680
PLT_RST_BUF_L
=ENET_RESET_L
OUT
30
OUT
35
AP_RESET_L
OUT
32
BKLT_PLT_RST_L
OUT
90
MAKE_BASE=TRUE
2
3
1
3
C2680
1
20%
10V
CERM
402
R2680
=TBT_RESET_L
100K
5%
1/16W
MF-LF
2 402
0.1UF
2
Series R on Pg38, R3803
R2688
0
1
R2655
IN
22
LPC_CLK33M_SMC_R
1
LPC_CLK33M_SMC
2
5%
1/20W
MF
201
18
IN
18
IN
IN
LPC_CLK33M_GMUX_R
1
MAKE_BASE=TRUE
2
LPC_CLK33M_LPCPLUS
OUT
6 47 96
36
IN
89
24 18 7
D
C2690
2
PCH_CLK33M_PCIIN
OUT
R2611
16 96
1
1
100K
3
CPU_RESET_L
OUT
10 23
VTT voltage divider on CPU page
R2690
100K
NC
0.1UF
20%
10V
CERM
402
5%
1/16W
MF-LF
2 402
2
5%
5
1/20W
G
S
MF
201
4
2
B
ENET_MEDIA_SENSE_EN_L
PCH uses HDA_SDO as a power-up strap. If low, ME functions normally.
If high, ME is disabled. This allows for full re-flashing of SPI ROM.
SMC controls strap enable to allow in-field control of strap setting.
Q2620 & 5V pull-up allows circuit to work regardless of HDA voltage.
SSM6N37FEAPE
Q2610
=PPVBAT_G3_SYSCLK
1
R2612
Coin-Cell:
VBAT (300-ohm & 10uF RC)
No Coin-Cell: 3.42V G3Hot (no RC)
SOT563
D
6
0
22 7
5%
1/16W
MF-LF
402
=PP3V3_S5_SYSCLK
Coin-Cell & G3Hot:
3.42V G3Hot
Coin-Cell & No G3Hot: 3.3V S5
No Coin-Cell:
3.3V S5
No bypass necessary
G
S
=PP5V_S0_PCH
PCH ME Disable Strap
2
2
7
1
3
1
24 22 20 7 =PP3V3R1V5_S0_PCH_VCCSUSHDA
=PP3V3_ENET_SYSCLK
2
PLT_RST_CPU_BUF_L
NC
SOT563
System RTC Power Source & 32kHz / 25MHz Clock Generator
7
SC70
4
1/16W
SSM6N37FEAPE
=PP3V3_S3_PCH_GPIO
B
NOTE: VDD_25M must be powered if any VDDIO_25M_x is powered.
0
5%
1/16W
MF-LF
402
74LVC1G07
MAKE_BASE=TRUE
OUT
5%
1/20W
MF
201
7
U2690
5
16
Q2610
1
Ethernet XTAL Power
SB XTAL Power
T29 XTAL Power
OUT
2
R2659
PCH_CLK33M_PCIOUT
7
MF-LF
ENET_MEDIA_SENSE_RDIV
CRITICAL
LPC_CLK33M_GMUX
5%
1/20W
MF
201
2
402
22
GreenClk 25MHz Power
R2693
1
5%
1
ENET_MEDIA_SENSE
5%
1/20W
MF
201
2
VDDIO_25M_A: SB power rail for XTAL circuit.
VDDIO_25M_B: Ethernet power rail for XTAL circuit.
VDDIO_25M_C: T29 power rail for XTAL circuit.
=PP3V3_S0_RSTBUF
CRITICAL
12K
1
TP_PCI_CLK33M_OUT2
24 7
R2610
22
R2657
18
Buffered CPU reset
ENET_MEDIA_SENSE ISOLATION CIRCUIT
45 96
R2656
LPC_CLK33M_LPCPLUS_R
22
OUT
1
ENET_MEDIA_SENSE_EN
1
R2620
100K
Q2620
2
SSM6N37FEAPE
5
96 18
2
5%
1/16W
MF-LF
402
SPI_DESCRIPTOR_OVERRIDE_LS5V
0.1UF
0.1UF
20%
20%
20%
10V
U2600
10%
10V
10V
CERM
402
2
CERM
402
2
CERM
402
2
2
SLG3NB148A
X5R
402-1
TQFN
11
A
6
14
C2605
R2605
12PF
SYSCLK_CLK25M_X2
1
C2606
3
4
2
1
CRITICAL
NC
NC
Y2605
5%
1/16W
MF-LF
402
8
R2606
1M
25.000MHZ-12PF-20PPM
2
GND
5%
1/16W
MF-LF
402
6
4
D
6
THRM
PAD
2
SYSCLK_CLK32K_RTC
9
SYSCLK_CLK25M_SB
SYSCLK_CLK25M_ENET_R
SYSCLK_CLK25M_TBT
=PPVRTC_G3_OUT
OUT
15
1
R2600
16
OUT
0
1
OUT
7
G
S
OUT
16 96
IPD = 9-50k
1
16
45
8
5%
1/20W
MF
201
HDA_SDOUT_R
2
12
R2621
1K
SOT563
33
2
IN
SPI_DESCRIPTOR_OVERRIDE_L
SYNC_MASTER=K92_MLB
SYNC_DATE=07/06/2010
PAGE TITLE
SYSCLK_CLK25M_ENET
OUT
Chipset Support
36
5%
1/20W
MF
201
DRAWING NUMBER
Apple Inc.
For SB RTC Power
051-9585
1
C2610
NOTICE OF PROPRIETARY PROPERTY:
1UF
10%
6.3V
CERM
402
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
5
4
3
2
SIZE
D
REVISION
R
NOTE: 30 PPM crystal required
7
S
D
1
Q2620
+V3.3A should be first
available ~3.3V power
to reduce VBAT draw.
2
SYSCLK_CLK25M_X1
2
5%
50V
CERM
402
4
NO STUFF
1
SM-3.2X2.5MM
12PF
1
3
SYSCLK_CLK25M_X2_R
2
CRITICAL
VDDIO_25M_A
32KHZ_A
VDDIO_25M_B
VDDIO_25M_C
25MHZ_A
25MHZ_B
X2
25MHZ_C
X1
VDD_RTC_OUT
7
1
5%
50V
CERM
402
0
SPI_DESCRIPTOR_OVERRIDE
SSM6N37FEAPE
1UF
10V
2
13
C2602
+3.42V
1
2
1
=PP3V3R1V5_S0_PCH_VCCSUSHDA
VBAT and +V3.3A are
internally ORed to
create VDD_RTC_OUT.
17
0.1UF
C2620
1
16
C2622
1
10
C2624
24 22 20 7
3
5
7
VDD_25M
7
=PPVDDIO_ENET_CLK
=PPVDDIO_S0_SBCLK
=PPVDDIO_T29_CLK
+V3.3A
G
SOT563
5%
1/20W
MF
201
3.0.0
BRANCH
PAGE
26 OF 132
SHEET
24 OF 105
1
A
8
7
6
5
4
3
2
1
TABLE_BOMGROUP_HEAD
BOM GROUP
BOM OPTIONS
HUB_ALLREM
HUB_NONREM1_0,HUB_NONREM0_0
HUB_1NONREM
HUB_NONREM1_0,HUB_NONREM0_1
HUB_2NONREM
HUB_NONREM1_1,HUB_NONREM0_0
HUB_3NONREM
HUB_NONREM1_1,HUB_NONREM0_1
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
USB MUX FOR LS/FS INTERNAL DEVICES
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
D
25 7
C2700
C2701
1
4.7UF
1
2
C2702
1
2
0.1UF
20%
6.3V
X5R
603
NON_REM 1 : NON_REM 0
STRAP PIN CFG
0
:
0
ALL PORTS ARE REMOVABLE
0
:
1
PORT 1 IS NON REMOVABLE
1
:
0
PORT 1 & 2 ARE NON REMOVABLE
1
:
1
PORT 1 & 2 & 3 ARE NON REMOVABLE
CANNOT INDICATE ALL 4 PORTS ARE NON REMOVABLE ON USB2514B VIA STARPPING, PROGRAM NON_REMOVABLE DEVICE REGISTER 09H
BYPASS=U2700.5::2MM
BYPASS=U27000.5::5MM
=PP3V3_S3_USB_HUB
10%
16V
X7R-CERM
402
2
1
0.1UF
C2703
D
0.1UF
10%
16V
X7R-CERM
402
2
10%
16V
X7R-CERM
402
BOM TABLE
TABLE_5_HEAD
PART#
BYPASS=U2700.15::2MM
BYPASS=U2700.10::2MM
BYPASS=U2700.23::5MM
BYPASS=U2700.23::2MM
QTY
DESCRIPTION
1
REFERENCE DESIGNATOR(S)
USB HUB 2514B
CRITICAL
BOM OPTION
CRITICAL
USBHUB2514B
CRITICAL
USBHUB2513B
CRITICAL
USBHUB2512B
TABLE_5_ITEM
338S0824
U2700
TABLE_5_ITEM
338S0923
1
U2700
USB HUB 2513B
TABLE_5_ITEM
0.1UF
VOLTAGE=1.8V
VDD33
Y2700
24.000M-60PPM-16PF
1
USB_HUB_XTAL_C
C2709
HUB_NONREM1_1
1
HUB_NONREM0_1
C
R2702
1
10K
2
5%
1/16W
MF-LF
402
2
2
2
1
5%
1/16W
MF-LF
402
R2701
5%
50V
CERM
402
100
1
2
USB_HUB_TEST
2
5%
1/16W
MF-LF
402
11
TEST
USB_HUB_RESET_L
26
RESET*
33
USB_HUB_XTAL1
USB_HUB_XTAL2
5%
1/16W
MF-LF
402
32
XTALIN/CLKIN
XTALOUT
28
USB_HUB_NONREM1
22
USB_HUB_CFG_SEL0
24
5%
1/16W
MF-LF
402
1
2
34
1
10%
16V
X7R-CERM
402
2
C2712
1UF
10%
16V
X7R-CERM
402
R2705
5%
1/16W
MF-LF
402
1
25
10%
16V
X5R
402
1UF
2
10%
16V
X5R
402
=PP3V3_S3_USB_HUB
1
USBDM_DN1/PRT_DIS_M1
USBDP_DN1/PRT_DIS_P1
1
3
6
8
SDA/SMBDATA/NON_REM1
R2706
1
2
5%
1/16W
MF-LF
402
10K
2
9
OCS1*
OCS2*
OSC3*
NC
13
IPU
IPU
IPU
IPU
8
BI
8
BI
16
18
20
17
19
21
1
R2717
NOSTUFF
1
R2718
10K
BLUETOOTH FOR J5 & J3X
2
7 25
NOSTUFF
1
R2719
25 8
BI
8 25
BI
8 25
BI
10K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
2
2
10K
5%
1/16W
MF-LF
C
2 402
8 25
USBHUB_DN3_N
USBHUB_DN3_P
8 25
BI
10K
5%
1/16W
MF-LF
402
TP/KB FOR J5, IR FOR J3X
SMC DEBUG PORT FOR J5, TP/KB FOR J3X
=PP3V3_S3_USB_HUB
TP_USB_HUB_OCS1
NC_USB_HUB_OCS2
NC_USB_HUB_OCS3
NC_USB_HUB_OCS4
RBIAS
35
27
1
30
USB_HUB_UP_N
USB_HUB_UP_P
USBHUB_DN4_N
USBHUB_DN4_P
7 25
R2708
10K
5%
1/16W
MF-LF
402
USB_HUB_VBUS_DET
USBDM_UP
USBDP_UP
25 8
25 8
TP_USB_HUB_PRTPWR1
NC_USB_HUB_PRTPWR2
NC_USB_HUB_PRTPWR3
NC_USB_HUB_PRTPWR4
VBUS_DET
25 8
NC FOR J5, SMC DEBUG PORT FOR J3X
2
J5 USES 197S0181 FOR Y2700 DUE TO HEIGHT LIMITATION
J3X USE 197S0284 FOR Y2700 TO SAVE COST
R2716
NOSTUFF
8
USBHUB_DN4_N
USBHUB_DN4_P
12
5%
1/16W
MF-LF
402
8
BI
USBHUB_DN3_N
USBHUB_DN3_P
7
PRTPWR1/BC_EN1*
PRTPWR2/BC_EN2*
PRTPWR3/BC_EN3*
NC
R2707
BI
USBHUB_DN2_N
USBHUB_DN2_P
4
NC
NC
SUSP_IND/LOCAL_PWR/NON_REM0
USBHUB_DN1_N
USBHUB_DN1_P
2
USBDM_DN3/PRT_DIS_M3
USBDP_DN3/PRT_DIS_P3
HS_IND/CFG_SEL1
10K
USB_HUB_RBIAS
CRITICAL
31
THRM_PAD
BI
18 95
BI
1
18 95
R2709
TO CONNECT TP/KB TO PCH XHCI
NOSTUFF R5701 & R5702, STUFF R2720 & R2721
12K
PCH PORT 7 (EHCI1)
=PP3V3_S3_USB_RESET
2
37
7
2
NOSTUFF
10K
2
2
SCL/SMBCLK/CFG_SEL0
USB_HUB_CFG_SEL1
HUB_NONREM0_0
10K
C2711
0.1UF
USBDM_DN2/PRT_DIS_M2
USBDP_DN2/PRT_DIS_P2
OMIT
25
USB_HUB_NONREM0
R2704 1
1
QFN
CRITICAL
HUB_NONREM1_0
C2714
USB2513B
R2700
1M
1
0.1UF
MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.8V
C2713
U2700
USB HUB 2512B
U2700
C2710
18PF
5%
1/16W
MF-LF
402
R2703
10K
1
R2710
0
2
1
SYM VER 1
5X3.2X1.4-SM
1
18PF
5%
50V
CERM
402
2
CRITICAL
CRITICAL
14
5
BYPASS=U2700.36::2MM
BYPASS=U2650.29::2MM
CRITICAL
1
PPUSB_HUB2_VDD1V8PLL
1
J5 ENGINEERING: USE USB2513B PRODUCTION: USE USB2512B
J3X ENGINEERING: USE USB2514B PRODUCTION: USE USB2513B
MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM
2
PLLFILT
10%
16V
X7R-CERM
402
2
36
0.1UF
10%
16V
X7R-CERM
402
2
PPUSB_HUB2_VDD1V8
CRFILT
10%
16V
X7R-CERM
402
2
338S0983
1
29
0.1UF
20%
6.3V
X5R
603
C2708
1
23
4.7UF
C2706
1
15
C2705
1
10
C2704
1%
1/16W
MF
402
NOSTUFF
R2720
95 18
B
BI
USB_EXTD_XHCI_N
1
NOSTUFF
TO PCH XHCI
1
R2712
10K
95 18
5%
1/16W
MF-LF
R2721
BI
USB_EXTD_XHCI_P
27
2
USB_TPAD_R_N
BI
53 95 101
B
TO TP/KB
2
USB_TPAD_R_P
BI
53 95 101
5%
1/16W
MF-LF
402
2 402
USB_HUB_RESET_L
C2715
1
27
5%
1/16W
MF-LF
402
25
1
0.1UF
2
BYPASS=U2700.26::2MM
USB XHCI/EHCI2 PORT MUX FOR EXT B
7
=PP3V3_S3_USBMUX
C2760
1
9
10%
16V
X7R-CERM
402
0.1UF
95 18
BI
95 18
PCH PORT 9 (EHCI2)
BI
A
USB_EXTB_EHCI_P
USB_EXTB_EHCI_N
20%
10V
CERM
402
VCC
2
5 M+
4 M-
Y+ 1
Y- 2
U2760
USB_EXTB_MUX_P
USB_EXTB_MUX_N
BI
43 95
BI
43 95
TO CONNECTOR
PI3USB102ZLE
95 18
PCH PORT 1 (XHCI)
BI
95 18
BI
USB_EXTB_XHCI_P
USB_EXTB_XHCI_N
7 D+
6 D-
SYNC_MASTER=J31_LINDA
TQFN
CRITICAL
USB HUB & MUX
PULL-UP TO 3.3V SUS ON PCH PAGE, SEL PIN IS LEAKAGE-SAFE
8
SEL 10
OE*
3
GND
SYNC_DATE=09/16/2011
PAGE TITLE
USB_EXTB_SEL_XHCI
IN
SEL=0 CHOOSE USB EHCI2 PORT
SEL=1 CHOOSE USB XHCI PORT
16
DRAWING NUMBER
PCH GPIO60
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
051-9585
3
2
SIZE
D
REVISION
3.0.0
BRANCH
PAGE
27 OF 132
SHEET
25 OF 105
1
A
8
7
6
5
4
3
2
1
The circuit below handles CPU and VTT power during S0- & gt; S3- & gt; S0 transitions, as well
as isolating the CPU’s SM_DRAMRST# output from the SO-DIMMs when necessary.
ISOLATE_CPU_MEM_L GPIO state during S3 & lt; - & gt; S0 transitions determines behavior of signals.
D
WHEN HIGH: CPU 1.5V remains powered in S3, VTT follows S0 rails, MEM_RESET_L not isolated.
D
WHEN LOW:
CPU 1.5V follows S0 rails, VTT ensures clean CKE transition, MEM_RESET_L isolated.
P1V5CPU_EN
= (ISOLATE_CPU_MEM_L + PLT_RST_L)
1V5 S0 " PGOOD " for CPU
= (ISOLATE_CPU_MEM_L + PM_SLP_S3_L) * PM_SLP_S4_L
MEMVTT_EN
* PM_SLP_S3_L
MEM_RESET_L = !ISOLATE_CPU_MEM_L + CPU_MEM_RESET_L
7
74 45 32 17
=PP3V3_S5_CPU_VCCDDR
PM_SLP_S4_L
IN
PM_MEM_PWRGD pull-up to CPU VTT rail is on CPU page
CPUMEM_S0
1
R2805
15 13 10 7
=PP1V5_S3_CPU_VCCDDR
PM_MEM_PWRGD
1
10K
5%
1/16W
MF-LF
2 402
CPUMEM_S0
OUT
R2820 1
73
CRITICAL
7
=PP3V3_S3_MEMRESET
2
5%
1/16W
MF-LF
402
CRITICAL
6
D
Q2820
27.4K
Q2805
CPUMEM_S0
D
SOT563
10 17 93
10K
P1V5CPU_EN
SSM6N37FEAPE
OUT
R2822
1%
1/16W
MF-LF
402
6
R2801 1
DMB53D0UV
SOT-563
G
2
PM_MEM_PWRGD_L
2
100K
Q2820
1
P1V5CPU_EN_L
4
SSM6N37FEAPE
D
D
3
Q2805
SOT563
5
SOT563
G
S
R2821
SSM6N37FEAPE
3
Q2800
4
S
4
G
NO STUFF
1
C2820
33.2K
CRITICAL
1%
1/16W
MF-LF
402
CPUMEM_S0
1
0.001UF
20%
50V
CERM
402
2
C
2
5
ISOLATE_CPU_MEM_L
IN
1
SOT-563
CRITICAL
23
S
DMB53D0UV
5
P1V5_S0_DIV
S
G
2
2
CPUMEM_S0
C
CRITICAL
3
5%
1/16W
MF-LF
402
PM_SLP_S3_L
IN
6 17 45 74
CPUMEM_S0
1
R2810
10K
5%
1/16W
MF-LF
2 402
CPUMEM_S0
26 7
=PP5V_S3_MEMRESET
MEMVTT_EN
SSM6N37FEAPE
OUT
8
MEMVTT Clamp
CRITICAL
Q2810
CPUMEM_S0
R2815
CPUMEM_S0
1
R2802
100K
5%
1/16W
MF-LF
402
D
SOT563
6
Ensures CKE signals are held low in S3
1
100K
5%
1/16W
MF-LF
402
2
S
7
CPUMEM_S0
R2850
CRITICAL
Q2800
CPUMEM_S0
D
SOT563
3
CPUMEM_S0
D
CRITICAL
SOT563
2
CPUMEM_S0
G
S
1
4
S
G
26 7
5
=PP5V_S3_MEMRESET
IN
18 24
5%
1/16W
MF-LF
402
C2817
CRITICAL
10%
6.3V
X5R
201
=PP1V5_S3_MEMRESET
CPUMEM_S0
Q2815
CPUMEM_S0
1
SSM6N37FEAPE
SOT563
B
6
1
CRITICAL
C2816
SSM6N37FEAPE
Q2850
D
10%
16V
X5R
402
3
MEM_RESET_L
OUT
NO STUFF
C2851
20%
50V
CERM
402
27 29
5
68 8
CPUMEM_S3
IN
G
1
0.001UF
SOT563
D
CPU_MEM_RESET_L
MAKE_BASE=TRUE
2
S
CPUMEM_S0
0.1UF
1
5%
1/16W
MF-LF
402
G
VTTCLAMP_EN
3
=MEM_RESET_L
4
IN
S
2
10
R2816
2
2
7
CPUMEM_S0
1K
5
MEMRESET_ISOL_LS5V_L
G
OUT
D
100K
0.047UF
31
SOT563
R2851 1
NOSTUFF
2
2
Q2850
CPUMEM_S0
PLT_RESET_L
1
6
D
G
S
2
75mA max load @ 0.75V
60mW max power
VTTCLAMP_L
SSM6N37FEAPE
SOT563
1
5%
1/10W
MF-LF
603
CRITICAL
Q2810
SSM6N37FEAPE
1
10
SSM6N37FEAPE
6
Q2815
B
=PPVTT_S0_VTTCLAMP
1
MEMVTT_EN_L
SSM6N37FEAPE
CRITICAL
G
2
2
CPUMEM_S0
S
2
4
=DDRVTT_EN
R2817
1
0
2
5%
1/16W
MF-LF
402
Step
S0
to
A
S3
to
S0
PM_SLP_S3_L
PM_SLP_S4_L
CPU_MEM_RESET_L
0
1
2
3
ISOLATE_CPU_MEM_L
1
0
0
0
PLT_RESET_L
1
1
0
0
1
1
1
0
1
1
1
1
1
1
1
X
CPU_MEM_RESET_L
1
1
1
MEM_RESET_L
MEMVTT_EN
1
1
0
0
P1V5CPU_EN
1
1
1
0
4
5
6
7
0
0
0
1
0
1
1
1
1
1
1
1
1
1
1
1
X
0 (*)
1
1
1
1
1
CPU_MEM_RESET_L
0
1
1
1
1
1
1
1
SYNC_MASTER=K18_MLB
CPU Memory S3 Support
DRAWING NUMBER
Apple Inc.
(*) CPU_MEM_RESET_L asserts due to loss of PM_MEM_PWRGD, must wait for software to clear before deasserting ISOLATE_CPU_MEM_L GPIO.
NOTICE OF PROPRIETARY PROPERTY:
Rails will power-up as if from S3, but MEM_RESET_L will not properly assert.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
Software
must deassert ISOLATE_CPU_MEM_L and then generate a valid reset cycle on CPU_MEM_RESET_L.
8
7
6
051-9585
5
4
3
2
SIZE
D
REVISION
R
NOTE: In the event of a S3- & gt; S5 transition ISOLATE_CPU_MEM_L will still be asserted on next S5- & gt; S0
transition.
SYNC_DATE=04/27/2010
PAGE TITLE
3.0.0
BRANCH
PAGE
28 OF 132
SHEET
26 OF 105
1
A
8
7
6
5
4
3
2
1
DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR)
Page Notes
7
=PP1V5_S3_MEM_A
Power aliases required by this page:
- =PP1V5_S0_MEM_A
1
- =PP1V5_S3_MEM_A
C2910
2
- =PPSPD_S0_MEM_A (2.5 - 3.3V)
Signal aliases required by this page:
1
- =I2C_SODIMMA_SCL
C2900
1
1
C2912
1
C2913
1
C2914
1
C2915
1
C2916
1
C2917
1
C2918
1
C2919
1
C2920
1
C2921
1
C2922
PLACE_NEAR=J2900.75:2.54mm
BOM options provided by this page:
2
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
1
0.1UF
20%
10V
CERM
402
20%
10V
CERM
402
2
2
2
2
2
2
2
2
2
2
2
2
20%
6.3V
X5R
603
20%
10V
CERM
402
PLACE_NEAR=J2900.75:2.54mm
PLACE_NEAR=J2900.75:2.54mm
10UF
20%
6.3V
X5R
603
C2923
0.1UF
2
C2901
10UF
- =I2C_SODIMMA_SDA
D
C2911
1
0.1UF
- =PP0V75_S0_MEM_VTT_A
2
PLACE_NEAR=J2900.75:2.54mm
PLACE_NEAR=J2900.75:2.54mm
PLACE_NEAR=J2900.75:2.54mm
PLACE_NEAR=J2900.75:2.54mm
PLACE_NEAR=J2900.75:2.54mm
PLACE_NEAR=J2900.75:2.54mm
PLACE_NEAR=J2900.75:2.54mm
PLACE_NEAR=J2900.75:2.54mm
PLACE_NEAR=J2900.75:2.54mm
PLACE_NEAR=J2900.75:2.54mm
PLACE_NEAR=J2900.75:2.54mm
PLACE_NEAR=J2900.75:2.54mm
D
93 31 PP0V75_S3_MEM_VREFDQ_A
(NONE)
1
1
C2930
C2931
2.2UF
0.1UF
20%
6.3V
PLACE_NEAR=J2900.75:2.54mm
2
20%
10V
2
CERM
402-LF
CERM
402
OMIT_TABLE
3
73
MEM_A_CKE & lt; 0 & gt;
75
NC
94 11 6
IN
77
79
MEM_A_BA & lt; 2 & gt;
81
94 11 6
IN
MEM_A_A & lt; 12 & gt;
94 11 6
IN
83
MEM_A_A & lt; 9 & gt;
85
87
94 11 6
IN
MEM_A_A & lt; 8 & gt;
94 11 6
IN
89
MEM_A_A & lt; 5 & gt;
91
93
94 11 6
IN
94 11 6
IN
95
MEM_A_A & lt; 3 & gt;
MEM_A_A & lt; 1 & gt;
97
99
94 11 6
MEM_A_CLK_P & lt; 0 & gt;
101
94 11 6
C
IN
IN
MEM_A_CLK_N & lt; 0 & gt;
103
105
IN
MEM_A_A & lt; 10 & gt;
107
IN
MEM_A_BA & lt; 0 & gt;
109
94 11 6
IN
MEM_A_WE_L
113
94 11 6
IN
MEM_A_CAS_L
115
94 11 6
94 11 6
111
117
94 11 6
94 11 6
IN
MEM_A_A & lt; 13 & gt;
119
IN
MEM_A_CS_L & lt; 1 & gt;
121
123
NC
125
127
28
BI
=MEM_A_DQ & lt; 32 & gt;
129
28
BI
=MEM_A_DQ & lt; 33 & gt;
131
133
28
28
BI
=MEM_A_DQS_N & lt; 4 & gt;
135
BI
=MEM_A_DQS_P & lt; 4 & gt;
137
139
28
28
BI
=MEM_A_DQ & lt; 34 & gt;
141
BI
=MEM_A_DQ & lt; 35 & gt;
143
145
28
28
BI
=MEM_A_DQ & lt; 40 & gt;
147
BI
=MEM_A_DQ & lt; 41 & gt;
149
151
153
155
B
28
BI
=MEM_A_DQ & lt; 42 & gt;
157
28
BI
=MEM_A_DQ & lt; 43 & gt;
159
161
28
BI
=MEM_A_DQ & lt; 48 & gt;
163
28
BI
=MEM_A_DQ & lt; 49 & gt;
165
167
28
BI
=MEM_A_DQS_N & lt; 6 & gt;
28
BI
=MEM_A_DQS_P & lt; 6 & gt;
169
171
173
28
28
BI
=MEM_A_DQ & lt; 50 & gt;
175
BI
=MEM_A_DQ & lt; 51 & gt;
177
179
28
BI
=MEM_A_DQ & lt; 56 & gt;
181
28
BI
=MEM_A_DQ & lt; 57 & gt;
183
185
187
189
28
BI
=MEM_A_DQ & lt; 58 & gt;
191
28
BI
=MEM_A_DQ & lt; 59 & gt;
193
195
6 MEM_A_SA & lt; 0 & gt;
197
199
7 =PPSPD_S0_MEM_A
6 MEM_A_SA & lt; 1 & gt;
201
203
1
1
A
C2940
10K
2.2UF
402-LF
IN
6 11 94
28
28
78
MEM_A_A & lt; 15 & gt;
IN
MEM_A_A & lt; 14 & gt;
IN
5%
MF-LF
402
2
BI
=MEM_A_DQ & lt; 0 & gt;
5
=MEM_A_DQ & lt; 1 & gt;
7
6 11 94
80
BI
6 11 94
9
11
82
13
84
MEM_A_A & lt; 11 & gt;
IN
6 11 94
28
BI
=MEM_A_DQ & lt; 2 & gt;
15
86
MEM_A_A & lt; 7 & gt;
IN
6 11 94
28
BI
=MEM_A_DQ & lt; 3 & gt;
17
88
19
90
MEM_A_A & lt; 6 & gt;
IN
6 11 94
28
BI
=MEM_A_DQ & lt; 8 & gt;
21
92
MEM_A_A & lt; 4 & gt;
IN
6 11 94
28
BI
=MEM_A_DQ & lt; 9 & gt;
23
94
25
96
MEM_A_A & lt; 2 & gt;
IN
6 11 94
28
BI
98
MEM_A_A & lt; 0 & gt;
IN
6 11 94
28
BI
27
=MEM_A_DQS_N & lt; 1 & gt;
=MEM_A_DQS_P & lt; 1 & gt;
29
100
31
102
MEM_A_CLK_P & lt; 1 & gt;
IN
6 11 94
28
BI
=MEM_A_DQ & lt; 10 & gt;
33
104
MEM_A_CLK_N & lt; 1 & gt;
IN
6 11 94
28
BI
=MEM_A_DQ & lt; 11 & gt;
35
106
37
108
MEM_A_BA & lt; 1 & gt;
110
MEM_A_RAS_L
114
116
BI
=MEM_A_DQ & lt; 16 & gt;
39
BI
=MEM_A_DQ & lt; 17 & gt;
41
28
BI
=MEM_A_DQS_N & lt; 2 & gt;
28
BI
=MEM_A_DQS_P & lt; 2 & gt;
IN
6 11 94
28
IN
6 11 94
28
MEM_A_CS_L & lt; 0 & gt;
IN
6 11 94
MEM_A_ODT & lt; 0 & gt;
IN
6 11 94
112
43
45
47
118
49
120
122
MEM_A_ODT & lt; 1 & gt;
IN
6 11 94
28
NC
28
BI
=MEM_A_DQ & lt; 18 & gt;
51
BI
=MEM_A_DQ & lt; 19 & gt;
53
124
55
126
28
128
28
130
=MEM_A_DQ & lt; 36 & gt;
BI
132
=MEM_A_DQ & lt; 37 & gt;
BI
BI
=MEM_A_DQ & lt; 24 & gt;
57
BI
=MEM_A_DQ & lt; 25 & gt;
59
61
28
28
63
134
65
136
28
28
138
140
=MEM_A_DQ & lt; 38 & gt;
BI
=MEM_A_DQ & lt; 39 & gt;
BI
=MEM_A_DQ & lt; 44 & gt;
BI
=MEM_A_DQ & lt; 45 & gt;
BI
=MEM_A_DQS_N & lt; 5 & gt;
BI
=MEM_A_DQS_P & lt; 5 & gt;
BI
=MEM_A_DQ & lt; 46 & gt;
BI
=MEM_A_DQ & lt; 47 & gt;
BI
=MEM_A_DQ & lt; 52 & gt;
BI
=MEM_A_DQ & lt; 53 & gt;
BI
=MEM_A_DQ & lt; 54 & gt;
BI
=MEM_A_DQ & lt; 55 & gt;
BI
28
180
=MEM_A_DQ & lt; 60 & gt;
BI
=MEM_A_DQ & lt; 61 & gt;
BI
28
=MEM_A_DQ & lt; 6 & gt;
BI
28
18
=MEM_A_DQ & lt; 7 & gt;
BI
28
22
=MEM_A_DQ & lt; 12 & gt;
BI
28
24
=MEM_A_DQ & lt; 13 & gt;
BI
28
20
26
28
30
MEM_RESET_L
IN
34
=MEM_A_DQ & lt; 14 & gt;
BI
28
36
=MEM_A_DQ & lt; 15 & gt;
BI
28
40
=MEM_A_DQ & lt; 20 & gt;
BI
28
42
=MEM_A_DQ & lt; 21 & gt;
BI
28
50
=MEM_A_DQ & lt; 22 & gt;
BI
28
52
=MEM_A_DQ & lt; 23 & gt;
BI
28
56
=MEM_A_DQ & lt; 28 & gt;
BI
28
58
=MEM_A_DQ & lt; 29 & gt;
BI
28
62
=MEM_A_DQS_N & lt; 3 & gt;
BI
28
64
=MEM_A_DQS_P & lt; 3 & gt;
BI
28
68
=MEM_A_DQ & lt; 30 & gt;
BI
28
70
=MEM_A_DQ & lt; 31 & gt;
BI
28
26 29
32
C
38
44
46
48
54
60
66
72
28
182
28
16
28
176
BI
28
174
28
=MEM_A_DQS_P & lt; 0 & gt;
28
166
BI
12
14
28
164
=MEM_A_DQS_N & lt; 0 & gt;
28
160
28
10
28
158
28
BI
28
154
69
BI
=MEM_A_DQ & lt; 5 & gt;
8
28
152
=MEM_A_DQ & lt; 27 & gt;
=MEM_A_DQ & lt; 4 & gt;
6
28
148
BI
28
146
67
28
142
BI
=MEM_A_DQ & lt; 26 & gt;
71
KEY
144
See CSA05 BOM table
150
156
B
162
168
170
172
PP0V75_S3_MEM_VREFCA_A
31 93
178
1
C2935
184
186
1
2.2UF
20%
6.3V
188
=MEM_A_DQS_N & lt; 7 & gt;
BI
28
2
=MEM_A_DQS_P & lt; 7 & gt;
BI
20%
10V
CERM
=MEM_A_DQ & lt; 62 & gt;
BI
=MEM_A_DQ & lt; 63 & gt;
BI
402
28
194
CERM
28
192
C2936
0.1UF
2
402-LF
28
190
196
198
MEM_EVENT_L
OUT
29 45 46
200
=I2C_SODIMMA_SDA
BI
202
=I2C_SODIMMA_SCL
IN
" Factory " (top) slot
48
48
204
=PP0V75_S0_MEM_VTT_A
1
516-0229
1/16W
MF-LF
2
MEM_A_CKE & lt; 1 & gt;
76
10K
1/16W
CERM
74
2
4
7
R2941
5%
20%
6.3V
2
1
R2940
CKE0
CKE1
VDD
VDD
NC
J2900 A15
BA2
A14
F-RT-THB
VDD
VDD
A12/BC*
A11
A9
A7
VDD
VDD
A8
A6
A5
A4
VDD
VDD
A3
A2
A0
A1
VDD
VDD
CK0
CK1
CK0*
CK1*
VDD
VDD
A10/AP
BA1
BA0
RAS*
VDD
VDD
WE*
S0*
CAS*
ODT0
VDD
VDD
A13
ODT1
S1*
NC
VDD
VDD
TEST
VREFCA
VSS
VSS
DQ32
DQ36
DQ33
DQ37
VSS
VSS
DQS4*
DM4
DQS4
VSS
VSS
DQ38
DQ34
DQ39
DQ35
VSS
VSS
DQ44
DQ40
DQ45
DQ41
VSS
VSS
DQS5*
DM5
DQS5
VSS
VSS
DQ42
DQ46
DQ43
DQ47
VSS
VSS
DQ48
DQ52
DQ49
DQ53
VSS
VSS
DQS6*
DM6
DQS6
VSS
VSS
DQ54
DQ50
DQ55
DQ51
VSS
VSS
DQ60
DQ56
DQ61
DQ57
VSS
VSS
DQS7*
DM7
DQS7
VSS
VSS
DQ58
DQ62
DQ59
DQ63
VSS
VSS
SA0
EVENT*
VDDSPD
SDA
SA1
SCL
VTT
VTT
(SYMBOL 2 OF 2)
IN
DDR3-SODIMM-DUAL-K6
94 11 6
KEY
VREFDQ
VSS
VSS
DQ4
DQ0
DQ5
CRITICAL
DQ1
VSS
VSS
DQS0*
J2900 DQS0
DM0
F-RT-THB
VSS
VSS
DQ2
DQ6
DQ3
DQ7
VSS
VSS
DQ8
DQ12
DQ9
DQ13
VSS
VSS
DQS1*
DM1
DQS1
RESET*
VSS
VSS
DQ10
DQ14
DQ11
DQ15
VSS
VSS
DQ16
DQ20
DQ17
DQ21
VSS
VSS
DQS2*
DM2
DQS2
VSS
DQ22
VSS
DQ18
DQ23
DQ19
VSS
DQ28
VSS
DQ24
DQ29
DQ25
VSS
DQS3*
VSS
DM3
DQS3
VSS
VSS
DQ26
DQ30
DQ27
DQ31
VSS
VSS
(SYMBOL 1 OF 2)
1
DDR3-SODIMM-DUAL-K6
OMIT_TABLE
C2950
1
C2951
1
C2952
1UF
SPD ADDR=0xA0(WR)/0xA1(RD)
402
2
1UF
10%
10V
X5R
402
1
10%
10V
X5R
402
2
2
C2953
1UF
1UF
10%
10V
X5R
402
2
SYNC_MASTER=K92_SUMA
10%
10V
X5R
402
PAGE TITLE
SYNC_DATE=06/23/2010
DDR3 SO-DIMM Connector A
DRAWING NUMBER
Apple Inc.
051-9585
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
3.0.0
BRANCH
PAGE
29 OF 132
SHEET
27 OF 105
1
A
8
7
6
CPU CHANNEL A DQS 0 - & gt; DIMM A DQS 0
94 11 6 MEM_A_DQS_N & lt; 0 & gt;
4
3
2
1
CPU CHANNEL B DQS 0 - & gt; DIMM B DQS 0
=MEM_A_DQS_N & lt; 0 & gt;
27
94 11 6 MEM_B_DQS_N & lt; 0 & gt;
=MEM_A_DQS_P & lt; 0 & gt;
27
94 11 6 MEM_B_DQS_P & lt; 0 & gt;
MAKE_BASE=TRUE
94 11 6 MEM_A_DQS_P & lt; 0 & gt;
5
=MEM_B_DQS_N & lt; 0 & gt;
29
=MEM_B_DQS_P & lt; 0 & gt;
29
=MEM_B_DQ & lt; 6 & gt;
29
=MEM_B_DQ & lt; 3 & gt;
29
=MEM_B_DQ & lt; 5 & gt;
29
=MEM_B_DQ & lt; 4 & gt;
29
MAKE_BASE=TRUE
MAKE_BASE=TRUE
94 11 6 MEM_A_DQ & lt; 7 & gt;
=MEM_A_DQ & lt; 3 & gt;
27
94 11 6 MEM_B_DQ & lt; 7 & gt;
=MEM_A_DQ & lt; 6 & gt;
MAKE_BASE=TRUE
94 11 6 MEM_A_DQ & lt; 6 & gt;
MAKE_BASE=TRUE
27
94 11 6 MEM_B_DQ & lt; 6 & gt;
=MEM_A_DQ & lt; 5 & gt;
27
94 11 6 MEM_B_DQ & lt; 5 & gt;
=MEM_A_DQ & lt; 4 & gt;
27
94 11 6 MEM_B_DQ & lt; 4 & gt;
=MEM_A_DQ & lt; 7 & gt;
27
94 11 6 MEM_B_DQ & lt; 3 & gt;
MAKE_BASE=TRUE
94 11 6 MEM_A_DQ & lt; 5 & gt;
MAKE_BASE=TRUE
MAKE_BASE=TRUE
94 11 6 MEM_A_DQ & lt; 4 & gt;
MAKE_BASE=TRUE
MAKE_BASE=TRUE
94 11 6 MEM_A_DQ & lt; 3 & gt;
MAKE_BASE=TRUE
MAKE_BASE=TRUE
94 11 6 MEM_A_DQ & lt; 2 & gt;
=MEM_A_DQ & lt; 0 & gt;
27
27
27
27
=MEM_A_DQS_P & lt; 1 & gt;
27
=MEM_A_DQ & lt; 15 & gt;
27
94 11 6 MEM_B_DQ & lt; 15 & gt;
=MEM_A_DQ & lt; 14 & gt;
27
94 11 6 MEM_B_DQ & lt; 14 & gt;
=MEM_A_DQ & lt; 12 & gt;
27
94 11 6 MEM_B_DQ & lt; 13 & gt;
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_A_DQ & lt; 13 & gt;
27
27
94 11 6 MEM_B_DQ & lt; 11 & gt;
=MEM_A_DQ & lt; 11 & gt;
27
94 11 6 MEM_B_DQ & lt; 10 & gt;
=MEM_A_DQ & lt; 9 & gt;
27
27
27
27
27
=MEM_A_DQ & lt; 22 & gt;
27
27
27
27
27
=MEM_A_DQS_N & lt; 3 & gt;
27
27
27
27
27
27
27
27
27
CPU CHANNEL B DQS 4 - & gt; DIMM B DQS 4
=MEM_A_DQS_N & lt; 4 & gt;
27
94 11 6 MEM_B_DQS_N & lt; 4 & gt;
=MEM_A_DQS_P & lt; 4 & gt;
27
94 11 6 MEM_B_DQS_P & lt; 4 & gt;
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_A_DQ & lt; 38 & gt;
27
94 11 6 MEM_B_DQ & lt; 39 & gt;
=MEM_A_DQ & lt; 37 & gt;
27
94 11 6 MEM_B_DQ & lt; 38 & gt;
=MEM_A_DQ & lt; 39 & gt;
27
94 11 6 MEM_B_DQ & lt; 37 & gt;
=MEM_A_DQ & lt; 33 & gt;
27
94 11 6 MEM_B_DQ & lt; 36 & gt;
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_A_DQ & lt; 35 & gt;
27
94 11 6 MEM_B_DQ & lt; 35 & gt;
=MEM_A_DQ & lt; 34 & gt;
27
94 11 6 MEM_B_DQ & lt; 34 & gt;
=MEM_A_DQ & lt; 32 & gt;
27
94 11 6 MEM_B_DQ & lt; 33 & gt;
=MEM_A_DQ & lt; 36 & gt;
27
94 11 6 MEM_B_DQ & lt; 32 & gt;
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
CPU CHANNEL A DQS 5 - & gt; DIMM A DQS 5
CPU CHANNEL B DQS 5 - & gt; DIMM B DQS 5
=MEM_A_DQS_N & lt; 5 & gt;
27
94 11 6 MEM_B_DQS_N & lt; 5 & gt;
=MEM_A_DQS_P & lt; 5 & gt;
27
94 11 6 MEM_B_DQS_P & lt; 5 & gt;
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_A_DQ & lt; 47 & gt;
27
94 11 6 MEM_B_DQ & lt; 47 & gt;
=MEM_A_DQ & lt; 41 & gt;
27
94 11 6 MEM_B_DQ & lt; 46 & gt;
=MEM_A_DQ & lt; 43 & gt;
27
94 11 6 MEM_B_DQ & lt; 45 & gt;
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_A_DQ & lt; 44 & gt;
27
94 11 6 MEM_B_DQ & lt; 44 & gt;
=MEM_A_DQ & lt; 40 & gt;
27
94 11 6 MEM_B_DQ & lt; 43 & gt;
=MEM_A_DQ & lt; 46 & gt;
27
94 11 6 MEM_B_DQ & lt; 42 & gt;
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_A_DQ & lt; 42 & gt;
27
27
MAKE_BASE=TRUE
=MEM_A_DQS_N & lt; 6 & gt;
27
27
27
=MEM_A_DQ & lt; 54 & gt;
27
27
29
=MEM_B_DQ & lt; 51 & gt;
29
=MEM_B_DQ & lt; 50 & gt;
29
=MEM_B_DQ & lt; 49 & gt;
29
=MEM_B_DQ & lt; 48 & gt;
29
=MEM_B_DQS_N & lt; 7 & gt;
29
=MEM_B_DQS_P & lt; 7 & gt;
29
=MEM_B_DQ & lt; 63 & gt;
29
=MEM_B_DQ & lt; 62 & gt;
29
=MEM_B_DQ & lt; 61 & gt;
29
=MEM_B_DQ & lt; 60 & gt;
29
=MEM_B_DQ & lt; 59 & gt;
29
=MEM_B_DQ & lt; 58 & gt;
29
=MEM_B_DQ & lt; 57 & gt;
29
=MEM_B_DQ & lt; 56 & gt;
94 11 6 MEM_B_DQ & lt; 53 & gt;
=MEM_A_DQ & lt; 52 & gt;
27
94 11 6 MEM_B_DQ & lt; 52 & gt;
29
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
=MEM_A_DQ & lt; 51 & gt;
27
94 11 6 MEM_B_DQ & lt; 51 & gt;
=MEM_A_DQ & lt; 50 & gt;
27
94 11 6 MEM_B_DQ & lt; 50 & gt;
=MEM_A_DQ & lt; 53 & gt;
27
94 11 6 MEM_B_DQ & lt; 49 & gt;
=MEM_A_DQ & lt; 48 & gt;
27
94 11 6 MEM_B_DQ & lt; 48 & gt;
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
CPU CHANNEL A DQS 7 - & gt; DIMM A DQS 7
CPU CHANNEL B DQS 7 - & gt; DIMM B DQS 7
=MEM_A_DQS_N & lt; 7 & gt;
27
94 11 6 MEM_B_DQS_N & lt; 7 & gt;
=MEM_A_DQS_P & lt; 7 & gt;
27
94 11 6 MEM_B_DQS_P & lt; 7 & gt;
MAKE_BASE=TRUE
94 11 6 MEM_A_DQS_P & lt; 7 & gt;
29
=MEM_B_DQ & lt; 52 & gt;
94 11 6 MEM_B_DQ & lt; 54 & gt;
=MEM_A_DQ & lt; 55 & gt;
94 11 6 MEM_A_DQS_N & lt; 7 & gt;
29
=MEM_B_DQ & lt; 53 & gt;
94 11 6 MEM_B_DQ & lt; 55 & gt;
MAKE_BASE=TRUE
A
29
=MEM_B_DQ & lt; 54 & gt;
MAKE_BASE=TRUE
MAKE_BASE=TRUE
94 11 6 MEM_A_DQ & lt; 48 & gt;
29
=MEM_B_DQ & lt; 55 & gt;
MAKE_BASE=TRUE
MAKE_BASE=TRUE
94 11 6 MEM_A_DQ & lt; 49 & gt;
29
=MEM_B_DQS_P & lt; 6 & gt;
94 11 6 MEM_B_DQS_P & lt; 6 & gt;
=MEM_A_DQ & lt; 49 & gt;
94 11 6 MEM_A_DQ & lt; 50 & gt;
=MEM_B_DQS_N & lt; 6 & gt;
94 11 6 MEM_B_DQS_N & lt; 6 & gt;
=MEM_A_DQS_P & lt; 6 & gt;
MAKE_BASE=TRUE
94 11 6 MEM_A_DQ & lt; 51 & gt;
29
MAKE_BASE=TRUE
CPU CHANNEL B DQS 6 - & gt; DIMM B DQS 6
MAKE_BASE=TRUE
94 11 6 MEM_A_DQ & lt; 52 & gt;
29
=MEM_B_DQ & lt; 40 & gt;
94 11 6 MEM_B_DQ & lt; 40 & gt;
CPU CHANNEL A DQS 6 - & gt; DIMM A DQS 6
94 11 6 MEM_A_DQ & lt; 53 & gt;
29
=MEM_B_DQ & lt; 41 & gt;
94 11 6 MEM_B_DQ & lt; 41 & gt;
MAKE_BASE=TRUE
=MEM_A_DQ & lt; 45 & gt;
94 11 6 MEM_A_DQ & lt; 54 & gt;
=MEM_B_DQ & lt; 42 & gt;
MAKE_BASE=TRUE
MAKE_BASE=TRUE
94 11 6 MEM_A_DQ & lt; 55 & gt;
B
MAKE_BASE=TRUE
MAKE_BASE=TRUE
94 11 6 MEM_A_DQS_P & lt; 6 & gt;
29
MAKE_BASE=TRUE
CPU CHANNEL A DQS 4 - & gt; DIMM A DQS 4
94 11 6 MEM_A_DQS_N & lt; 6 & gt;
29
=MEM_B_DQ & lt; 43 & gt;
94 11 6 MEM_B_DQ & lt; 24 & gt;
MAKE_BASE=TRUE
94 11 6 MEM_A_DQ & lt; 40 & gt;
29
=MEM_B_DQ & lt; 44 & gt;
94 11 6 MEM_B_DQ & lt; 25 & gt;
MAKE_BASE=TRUE
=MEM_A_DQ & lt; 24 & gt;
94 11 6 MEM_A_DQ & lt; 41 & gt;
29
=MEM_B_DQ & lt; 45 & gt;
MAKE_BASE=TRUE
=MEM_A_DQ & lt; 25 & gt;
94 11 6 MEM_A_DQ & lt; 42 & gt;
29
=MEM_B_DQ & lt; 46 & gt;
MAKE_BASE=TRUE
MAKE_BASE=TRUE
94 11 6 MEM_A_DQ & lt; 43 & gt;
29
=MEM_B_DQ & lt; 47 & gt;
94 11 6 MEM_B_DQ & lt; 26 & gt;
MAKE_BASE=TRUE
MAKE_BASE=TRUE
94 11 6 MEM_A_DQ & lt; 44 & gt;
29
=MEM_B_DQS_P & lt; 5 & gt;
94 11 6 MEM_B_DQ & lt; 27 & gt;
=MEM_A_DQ & lt; 26 & gt;
94 11 6 MEM_A_DQ & lt; 45 & gt;
29
=MEM_B_DQS_N & lt; 5 & gt;
94 11 6 MEM_B_DQ & lt; 28 & gt;
27
MAKE_BASE=TRUE
94 11 6 MEM_A_DQ & lt; 46 & gt;
29
=MEM_B_DQ & lt; 32 & gt;
MAKE_BASE=TRUE
=MEM_A_DQ & lt; 27 & gt;
94 11 6 MEM_A_DQ & lt; 47 & gt;
29
=MEM_B_DQ & lt; 33 & gt;
94 11 6 MEM_B_DQ & lt; 29 & gt;
=MEM_A_DQ & lt; 28 & gt;
94 11 6 MEM_A_DQS_P & lt; 5 & gt;
29
=MEM_B_DQ & lt; 34 & gt;
MAKE_BASE=TRUE
MAKE_BASE=TRUE
94 11 6 MEM_A_DQS_N & lt; 5 & gt;
29
=MEM_B_DQ & lt; 35 & gt;
MAKE_BASE=TRUE
MAKE_BASE=TRUE
B
29
=MEM_B_DQ & lt; 36 & gt;
94 11 6 MEM_B_DQ & lt; 30 & gt;
=MEM_A_DQ & lt; 29 & gt;
94 11 6 MEM_A_DQ & lt; 32 & gt;
29
=MEM_B_DQ & lt; 37 & gt;
94 11 6 MEM_B_DQ & lt; 31 & gt;
=MEM_A_DQ & lt; 30 & gt;
94 11 6 MEM_A_DQ & lt; 33 & gt;
29
=MEM_B_DQ & lt; 38 & gt;
MAKE_BASE=TRUE
=MEM_A_DQ & lt; 31 & gt;
94 11 6 MEM_A_DQ & lt; 34 & gt;
29
=MEM_B_DQ & lt; 39 & gt;
MAKE_BASE=TRUE
MAKE_BASE=TRUE
94 11 6 MEM_A_DQ & lt; 35 & gt;
29
=MEM_B_DQS_P & lt; 4 & gt;
94 11 6 MEM_B_DQS_P & lt; 3 & gt;
MAKE_BASE=TRUE
94 11 6 MEM_A_DQ & lt; 36 & gt;
29
=MEM_B_DQS_N & lt; 4 & gt;
94 11 6 MEM_B_DQS_N & lt; 3 & gt;
=MEM_A_DQS_P & lt; 3 & gt;
94 11 6 MEM_A_DQ & lt; 37 & gt;
29
=MEM_B_DQ & lt; 24 & gt;
C
CPU CHANNEL B DQS 3 - & gt; DIMM B DQS 3
MAKE_BASE=TRUE
94 11 6 MEM_A_DQ & lt; 38 & gt;
29
=MEM_B_DQ & lt; 25 & gt;
MAKE_BASE=TRUE
MAKE_BASE=TRUE
94 11 6 MEM_A_DQ & lt; 39 & gt;
29
=MEM_B_DQ & lt; 26 & gt;
MAKE_BASE=TRUE
CPU CHANNEL A DQS 3 - & gt; DIMM A DQS 3
94 11 6 MEM_A_DQS_P & lt; 4 & gt;
29
=MEM_B_DQ & lt; 27 & gt;
94 11 6 MEM_B_DQ & lt; 16 & gt;
MAKE_BASE=TRUE
MAKE_BASE=TRUE
94 11 6 MEM_A_DQS_N & lt; 4 & gt;
29
=MEM_B_DQ & lt; 28 & gt;
94 11 6 MEM_B_DQ & lt; 17 & gt;
=MEM_A_DQ & lt; 21 & gt;
94 11 6 MEM_A_DQ & lt; 24 & gt;
29
=MEM_B_DQ & lt; 29 & gt;
94 11 6 MEM_B_DQ & lt; 18 & gt;
27
MAKE_BASE=TRUE
94 11 6 MEM_A_DQ & lt; 25 & gt;
29
=MEM_B_DQ & lt; 30 & gt;
MAKE_BASE=TRUE
=MEM_A_DQ & lt; 16 & gt;
94 11 6 MEM_A_DQ & lt; 26 & gt;
=MEM_B_DQ & lt; 31 & gt;
MAKE_BASE=TRUE
=MEM_A_DQ & lt; 18 & gt;
94 11 6 MEM_A_DQ & lt; 27 & gt;
29
MAKE_BASE=TRUE
MAKE_BASE=TRUE
94 11 6 MEM_A_DQ & lt; 28 & gt;
29
=MEM_B_DQS_P & lt; 3 & gt;
94 11 6 MEM_B_DQ & lt; 19 & gt;
MAKE_BASE=TRUE
MAKE_BASE=TRUE
94 11 6 MEM_A_DQ & lt; 29 & gt;
29
=MEM_B_DQS_N & lt; 3 & gt;
94 11 6 MEM_B_DQ & lt; 20 & gt;
=MEM_A_DQ & lt; 19 & gt;
94 11 6 MEM_A_DQ & lt; 30 & gt;
29
=MEM_B_DQ & lt; 16 & gt;
94 11 6 MEM_B_DQ & lt; 21 & gt;
MAKE_BASE=TRUE
94 11 6 MEM_A_DQ & lt; 31 & gt;
29
=MEM_B_DQ & lt; 17 & gt;
94 11 6 MEM_B_DQ & lt; 22 & gt;
=MEM_A_DQ & lt; 20 & gt;
94 11 6 MEM_A_DQS_P & lt; 3 & gt;
29
=MEM_B_DQ & lt; 18 & gt;
MAKE_BASE=TRUE
27
=MEM_A_DQ & lt; 17 & gt;
94 11 6 MEM_A_DQS_N & lt; 3 & gt;
29
=MEM_B_DQ & lt; 19 & gt;
94 11 6 MEM_B_DQ & lt; 23 & gt;
MAKE_BASE=TRUE
C
29
=MEM_B_DQ & lt; 20 & gt;
MAKE_BASE=TRUE
MAKE_BASE=TRUE
94 11 6 MEM_A_DQ & lt; 16 & gt;
29
=MEM_B_DQ & lt; 21 & gt;
MAKE_BASE=TRUE
MAKE_BASE=TRUE
94 11 6 MEM_A_DQ & lt; 17 & gt;
29
=MEM_B_DQ & lt; 22 & gt;
94 11 6 MEM_B_DQS_P & lt; 2 & gt;
=MEM_A_DQ & lt; 23 & gt;
94 11 6 MEM_A_DQ & lt; 18 & gt;
29
=MEM_B_DQ & lt; 23 & gt;
94 11 6 MEM_B_DQS_N & lt; 2 & gt;
=MEM_A_DQS_P & lt; 2 & gt;
94 11 6 MEM_A_DQ & lt; 19 & gt;
29
=MEM_B_DQS_P & lt; 2 & gt;
CPU CHANNEL B DQS 2 - & gt; DIMM B DQS 2
=MEM_A_DQS_N & lt; 2 & gt;
94 11 6 MEM_A_DQ & lt; 20 & gt;
=MEM_B_DQS_N & lt; 2 & gt;
MAKE_BASE=TRUE
MAKE_BASE=TRUE
94 11 6 MEM_A_DQ & lt; 21 & gt;
29
MAKE_BASE=TRUE
MAKE_BASE=TRUE
94 11 6 MEM_A_DQ & lt; 22 & gt;
29
=MEM_B_DQ & lt; 8 & gt;
94 11 6 MEM_B_DQ & lt; 8 & gt;
CPU CHANNEL A DQS 2 - & gt; DIMM A DQS 2
94 11 6 MEM_A_DQ & lt; 23 & gt;
29
=MEM_B_DQ & lt; 9 & gt;
94 11 6 MEM_B_DQ & lt; 9 & gt;
=MEM_A_DQ & lt; 8 & gt;
MAKE_BASE=TRUE
94 11 6 MEM_A_DQS_P & lt; 2 & gt;
29
=MEM_B_DQ & lt; 10 & gt;
MAKE_BASE=TRUE
MAKE_BASE=TRUE
94 11 6 MEM_A_DQS_N & lt; 2 & gt;
=MEM_B_DQ & lt; 11 & gt;
MAKE_BASE=TRUE
MAKE_BASE=TRUE
94 11 6 MEM_A_DQ & lt; 8 & gt;
29
MAKE_BASE=TRUE
MAKE_BASE=TRUE
94 11 6 MEM_A_DQ & lt; 9 & gt;
29
=MEM_B_DQ & lt; 12 & gt;
94 11 6 MEM_B_DQ & lt; 12 & gt;
=MEM_A_DQ & lt; 10 & gt;
94 11 6 MEM_A_DQ & lt; 10 & gt;
=MEM_B_DQ & lt; 13 & gt;
MAKE_BASE=TRUE
MAKE_BASE=TRUE
94 11 6 MEM_A_DQ & lt; 11 & gt;
29
MAKE_BASE=TRUE
MAKE_BASE=TRUE
94 11 6 MEM_A_DQ & lt; 12 & gt;
29
=MEM_B_DQ & lt; 14 & gt;
94 11 6 MEM_B_DQS_P & lt; 1 & gt;
MAKE_BASE=TRUE
94 11 6 MEM_A_DQ & lt; 13 & gt;
29
=MEM_B_DQ & lt; 15 & gt;
94 11 6 MEM_B_DQS_N & lt; 1 & gt;
MAKE_BASE=TRUE
94 11 6 MEM_A_DQ & lt; 14 & gt;
=MEM_B_DQS_P & lt; 1 & gt;
D
MAKE_BASE=TRUE
CPU CHANNEL B DQS 1 - & gt; DIMM B DQS 1
=MEM_A_DQS_N & lt; 1 & gt;
94 11 6 MEM_A_DQ & lt; 15 & gt;
29
MAKE_BASE=TRUE
CPU CHANNEL A DQS 1 - & gt; DIMM A DQS 1
94 11 6 MEM_A_DQS_P & lt; 1 & gt;
29
=MEM_B_DQS_N & lt; 1 & gt;
94 11 6 MEM_B_DQ & lt; 0 & gt;
MAKE_BASE=TRUE
MAKE_BASE=TRUE
94 11 6 MEM_A_DQS_N & lt; 1 & gt;
29
=MEM_B_DQ & lt; 0 & gt;
94 11 6 MEM_B_DQ & lt; 1 & gt;
=MEM_A_DQ & lt; 2 & gt;
94 11 6 MEM_A_DQ & lt; 0 & gt;
29
=MEM_B_DQ & lt; 2 & gt;
94 11 6 MEM_B_DQ & lt; 2 & gt;
=MEM_A_DQ & lt; 1 & gt;
MAKE_BASE=TRUE
D
29
=MEM_B_DQ & lt; 7 & gt;
MAKE_BASE=TRUE
MAKE_BASE=TRUE
94 11 6 MEM_A_DQ & lt; 1 & gt;
=MEM_B_DQ & lt; 1 & gt;
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
SYNC_MASTER=K92_SUMA
94 11 6 MEM_A_DQ & lt; 63 & gt;
=MEM_A_DQ & lt; 59 & gt;
27
94 11 6 MEM_B_DQ & lt; 63 & gt;
=MEM_A_DQ & lt; 58 & gt;
27
94 11 6 MEM_B_DQ & lt; 62 & gt;
=MEM_A_DQ & lt; 56 & gt;
27
94 11 6 MEM_B_DQ & lt; 61 & gt;
=MEM_A_DQ & lt; 61 & gt;
27
94 11 6 MEM_B_DQ & lt; 60 & gt;
=MEM_A_DQ & lt; 63 & gt;
27
94 11 6 MEM_B_DQ & lt; 59 & gt;
=MEM_A_DQ & lt; 62 & gt;
27
94 11 6 MEM_B_DQ & lt; 58 & gt;
=MEM_A_DQ & lt; 57 & gt;
27
94 11 6 MEM_B_DQ & lt; 57 & gt;
=MEM_A_DQ & lt; 60 & gt;
27
94 11 6 MEM_B_DQ & lt; 56 & gt;
MAKE_BASE=TRUE
94 11 6 MEM_A_DQ & lt; 62 & gt;
MAKE_BASE=TRUE
94 11 6 MEM_A_DQ & lt; 61 & gt;
MAKE_BASE=TRUE
MAKE_BASE=TRUE
94 11 6 MEM_A_DQ & lt; 56 & gt;
NOTICE OF PROPRIETARY PROPERTY:
SIZE
D
3.0.0
BRANCH
MAKE_BASE=TRUE
MAKE_BASE=TRUE
8
051-9585
REVISION
R
MAKE_BASE=TRUE
MAKE_BASE=TRUE
94 11 6 MEM_A_DQ & lt; 57 & gt;
Apple Inc.
MAKE_BASE=TRUE
MAKE_BASE=TRUE
94 11 6 MEM_A_DQ & lt; 58 & gt;
DRAWING NUMBER
MAKE_BASE=TRUE
MAKE_BASE=TRUE
94 11 6 MEM_A_DQ & lt; 59 & gt;
DDR3 Byte/Bit Swaps
MAKE_BASE=TRUE
MAKE_BASE=TRUE
94 11 6 MEM_A_DQ & lt; 60 & gt;
SYNC_DATE=05/10/2010
PAGE TITLE
MAKE_BASE=TRUE
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
MAKE_BASE=TRUE
7
6
5
4
3
2
PAGE
30 OF 132
SHEET
28 OF 105
1
A
8
7
6
5
4
3
2
1
DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR)
Page Notes
7
=PP1V5_S3_MEM_B
Power aliases required by this page:
- =PP1V5_S0_MEM_B
1
- =PP1V5_S3_MEM_B
C3111
1
1
C3112
1
C3113
1
C3114
1
C3115
1
C3116
1
C3117
1
C3118
1
C3119
1
C3120
1
C3121
1
C3122
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
Signal aliases required by this page:
C3100
1
- =I2C_SODIMMB_SCL
1
20%
10V
CERM
402
PLACE_NEAR=J3100.75:2.54mm
BOM options provided by this page:
10UF
20%
6.3V
X5R
603
2
2
2
2
2
2
2
2
2
2
2
2
2
C3123
0.1UF
2
20%
10V
CERM
402
PLACE_NEAR=J3100.75:2.54mm
PLACE_NEAR=J3100.75:2.54mm
C3101
10UF
- =I2C_SODIMMB_SDA
1
0.1UF
20%
10V
CERM
402
2
- =PPSPD_S0_MEM_B (2.5 - 3.3V)
D
C3110
0.1UF
- =PP0V75_S0_MEM_VTT_B
2
PLACE_NEAR=J3100.75:2.54mm
PLACE_NEAR=J3100.75:2.54mm
20%
6.3V
X5R
603
PLACE_NEAR=J3100.75:2.54mm
PLACE_NEAR=J3100.75:2.54mm
PLACE_NEAR=J3100.75:2.54mm
PLACE_NEAR=J3100.75:2.54mm
PLACE_NEAR=J3100.75:2.54mm
PLACE_NEAR=J3100.75:2.54mm
PLACE_NEAR=J3100.75:2.54mm
PLACE_NEAR=J3100.75:2.54mm
PLACE_NEAR=J3100.75:2.54mm
PLACE_NEAR=J3100.75:2.54mm
D
93 31 PP0V75_S3_MEM_VREFDQ_B
(NONE)
1
1
C3130
C3131
2.2UF
PLACE_NEAR=J3100.75:2.54mm
0.1UF
20%
6.3V
2
20%
10V
2
CERM
402-LF
CERM
402
OMIT_TABLE
3
75
NC
94 11 6
79
MEM_B_BA & lt; 2 & gt;
IN
77
81
94 11 6
IN
MEM_B_A & lt; 12 & gt;
94 11 6
IN
83
MEM_B_A & lt; 9 & gt;
85
87
94 11 6
IN
MEM_B_A & lt; 8 & gt;
94 11 6
IN
89
MEM_B_A & lt; 5 & gt;
91
93
94 11 6
IN
94 11 6
IN
95
MEM_B_A & lt; 3 & gt;
MEM_B_A & lt; 1 & gt;
97
99
94 11 6
MEM_B_CLK_P & lt; 0 & gt;
101
94 11 6
C
IN
IN
MEM_B_CLK_N & lt; 0 & gt;
103
105
IN
MEM_B_A & lt; 10 & gt;
107
IN
MEM_B_BA & lt; 0 & gt;
109
94 11 6
IN
MEM_B_WE_L
113
94 11 6
IN
MEM_B_CAS_L
115
94 11 6
94 11 6
111
117
94 11 6
94 11 6
IN
MEM_B_A & lt; 13 & gt;
119
IN
MEM_B_CS_L & lt; 1 & gt;
121
123
NC
125
127
28
BI
=MEM_B_DQ & lt; 32 & gt;
129
28
BI
=MEM_B_DQ & lt; 33 & gt;
131
133
28
28
BI
=MEM_B_DQS_N & lt; 4 & gt;
135
BI
=MEM_B_DQS_P & lt; 4 & gt;
137
139
28
28
BI
=MEM_B_DQ & lt; 34 & gt;
141
BI
=MEM_B_DQ & lt; 35 & gt;
143
145
28
28
BI
=MEM_B_DQ & lt; 40 & gt;
147
BI
=MEM_B_DQ & lt; 41 & gt;
149
151
153
155
B
28
BI
=MEM_B_DQ & lt; 42 & gt;
157
28
BI
=MEM_B_DQ & lt; 43 & gt;
159
161
28
BI
=MEM_B_DQ & lt; 48 & gt;
163
28
BI
=MEM_B_DQ & lt; 49 & gt;
165
167
28
BI
=MEM_B_DQS_N & lt; 6 & gt;
28
BI
=MEM_B_DQS_P & lt; 6 & gt;
169
171
173
28
28
BI
=MEM_B_DQ & lt; 50 & gt;
175
BI
=MEM_B_DQ & lt; 51 & gt;
177
179
28
BI
=MEM_B_DQ & lt; 56 & gt;
181
28
BI
=MEM_B_DQ & lt; 57 & gt;
183
185
187
189
28
BI
=MEM_B_DQ & lt; 58 & gt;
191
28
BI
=MEM_B_DQ & lt; 59 & gt;
193
195
6 MEM_B_SA & lt; 0 & gt;
197
199
7 =PPSPD_S0_MEM_B
6 MEM_B_SA & lt; 1 & gt;
201
203
1
1
A
C3140
10K
1/16W
MF-LF
2
5%
1/16W
CERM
402-LF
R3141
5%
20%
6.3V
2
1
R3140
10K
2.2UF
MF-LF
402
2
402
205
207
209
211
CKE0
CKE1
VDD
VDD
NC
A15
BA2
A14
J3100
VDD
F-RT-BGA6
VDD
A12/BC*
A11
A9
A7
VDD
VDD
A8
A6
A5
A4
VDD
VDD
A3
A2
A1
A0
VDD
VDD
CK0
CK1
CK0*
CK1*
VDD
VDD
A10/AP
BA1
BA0
RAS*
VDD
VDD
WE*
S0*
CAS*
ODT0
VDD
VDD
A13
ODT1
S1*
NC
VDD
VDD
TEST
VREFCA
VSS
VSS
DQ32
DQ36
DQ33
DQ37
VSS
VSS
DQS4*
DM4
DQS4
VSS
VSS
DQ38
DQ39
DQ34
DQ35
VSS
DQ44
VSS
DQ40
DQ45
DQ41
VSS
VSS
DQS5*
DM5
DQS5
VSS
VSS
DQ42
DQ46
DQ43
DQ47
VSS
VSS
DQ48
DQ52
DQ49
DQ53
VSS
VSS
DQS6*
DM6
DQS6
VSS
VSS
DQ54
DQ50
DQ55
DQ51
VSS
VSS
DQ60
DQ56
DQ61
DQ57
VSS
DQS7*
VSS
DQS7
DM7
VSS
VSS
DQ58
DQ62
DQ59
DQ63
VSS
VSS
SA0
EVENT*
VDDSPD
SDA
SA1
SCL
VTT
VTT
(2 OF 2)
73
MEM_B_CKE & lt; 0 & gt;
IN
DDR3-SODIMM
94 11 6
KEY
MTG PINS
MTG
MTG
MTG
MTG
74
6 11 94
IN
28
28
78
MEM_B_A & lt; 15 & gt;
IN
MEM_B_A & lt; 14 & gt;
IN
=MEM_B_DQ & lt; 1 & gt;
BI
5
7
6 11 94
80
=MEM_B_DQ & lt; 0 & gt;
BI
6 11 94
9
11
82
13
84
MEM_B_A & lt; 11 & gt;
IN
6 11 94
28
BI
=MEM_B_DQ & lt; 2 & gt;
15
86
MEM_B_A & lt; 7 & gt;
IN
6 11 94
28
BI
=MEM_B_DQ & lt; 3 & gt;
17
88
19
90
MEM_B_A & lt; 6 & gt;
IN
6 11 94
28
BI
=MEM_B_DQ & lt; 8 & gt;
21
92
MEM_B_A & lt; 4 & gt;
IN
6 11 94
28
BI
=MEM_B_DQ & lt; 9 & gt;
23
94
25
96
MEM_B_A & lt; 2 & gt;
IN
6 11 94
28
BI
=MEM_B_DQS_N & lt; 1 & gt;
27
98
MEM_B_A & lt; 0 & gt;
IN
6 11 94
28
BI
=MEM_B_DQS_P & lt; 1 & gt;
29
100
31
102
MEM_B_CLK_P & lt; 1 & gt;
IN
6 11 94
28
BI
=MEM_B_DQ & lt; 10 & gt;
33
104
MEM_B_CLK_N & lt; 1 & gt;
IN
6 11 94
28
BI
=MEM_B_DQ & lt; 11 & gt;
35
106
37
108
MEM_B_BA & lt; 1 & gt;
110
MEM_B_RAS_L
114
116
BI
=MEM_B_DQ & lt; 16 & gt;
39
BI
=MEM_B_DQ & lt; 17 & gt;
41
28
BI
=MEM_B_DQS_N & lt; 2 & gt;
45
28
BI
=MEM_B_DQS_P & lt; 2 & gt;
47
IN
6 11 94
28
IN
6 11 94
28
MEM_B_CS_L & lt; 0 & gt;
IN
6 11 94
MEM_B_ODT & lt; 0 & gt;
IN
6 11 94
112
43
118
49
120
122
MEM_B_ODT & lt; 1 & gt;
6 11 94
IN
28
NC
28
BI
=MEM_B_DQ & lt; 18 & gt;
51
BI
=MEM_B_DQ & lt; 19 & gt;
53
124
55
126
28
128
28
130
=MEM_B_DQ & lt; 36 & gt;
BI
132
=MEM_B_DQ & lt; 37 & gt;
BI
BI
=MEM_B_DQ & lt; 24 & gt;
57
BI
=MEM_B_DQ & lt; 25 & gt;
59
61
28
28
63
134
65
136
28
140
=MEM_B_DQ & lt; 38 & gt;
BI
=MEM_B_DQ & lt; 39 & gt;
BI
=MEM_B_DQ & lt; 44 & gt;
BI
=MEM_B_DQ & lt; 45 & gt;
BI
=MEM_B_DQS_N & lt; 5 & gt;
BI
=MEM_B_DQS_P & lt; 5 & gt;
BI
=MEM_B_DQ & lt; 46 & gt;
BI
=MEM_B_DQ & lt; 47 & gt;
BI
=MEM_B_DQ & lt; 52 & gt;
BI
=MEM_B_DQ & lt; 53 & gt;
BI
=MEM_B_DQ & lt; 54 & gt;
BI
=MEM_B_DQ & lt; 55 & gt;
BI
28
180
=MEM_B_DQ & lt; 60 & gt;
BI
=MEM_B_DQ & lt; 61 & gt;
BI
28
BI
28
16
=MEM_B_DQ & lt; 6 & gt;
BI
28
18
=MEM_B_DQ & lt; 7 & gt;
BI
28
22
=MEM_B_DQ & lt; 12 & gt;
BI
28
24
=MEM_B_DQ & lt; 13 & gt;
BI
28
20
26
28
30
MEM_RESET_L
IN
34
=MEM_B_DQ & lt; 14 & gt;
BI
28
36
=MEM_B_DQ & lt; 15 & gt;
BI
28
40
=MEM_B_DQ & lt; 20 & gt;
BI
28
42
=MEM_B_DQ & lt; 21 & gt;
BI
28
50
=MEM_B_DQ & lt; 22 & gt;
BI
28
52
=MEM_B_DQ & lt; 23 & gt;
BI
28
56
=MEM_B_DQ & lt; 28 & gt;
BI
28
58
=MEM_B_DQ & lt; 29 & gt;
BI
28
62
=MEM_B_DQS_N & lt; 3 & gt;
BI
28
64
=MEM_B_DQS_P & lt; 3 & gt;
BI
28
68
=MEM_B_DQ & lt; 30 & gt;
BI
28
70
=MEM_B_DQ & lt; 31 & gt;
BI
28
26 27
32
C
38
44
46
48
54
60
66
72
28
182
28
=MEM_B_DQS_P & lt; 0 & gt;
14
28
176
BI
12
28
174
=MEM_B_DQS_N & lt; 0 & gt;
28
166
28
10
28
164
28
BI
28
160
BI
=MEM_B_DQ & lt; 5 & gt;
8
28
158
=MEM_B_DQ & lt; 4 & gt;
6
28
154
2
4
28
152
69
71
28
148
=MEM_B_DQ & lt; 27 & gt;
28
146
BI
28
142
BI
67
=MEM_B_DQ & lt; 26 & gt;
28
138
KEY
144
516S0806
150
156
B
162
168
170
172
PP0V75_S3_MEM_VREFCA_B
31 93
178
1
1
C3135
184
2.2UF
186
20%
6.3V
188
=MEM_B_DQS_N & lt; 7 & gt;
28
BI
2
BI
20%
10V
CERM
=MEM_B_DQ & lt; 62 & gt;
BI
28
194
=MEM_B_DQ & lt; 63 & gt;
BI
CERM
402
28
192
C3136
0.1UF
2
402-LF
=MEM_B_DQS_P & lt; 7 & gt;
28
190
196
198
MEM_EVENT_L
27 45 46
OUT
200
=I2C_SODIMMB_SDA
BI
202
=I2C_SODIMMB_SCL
IN
48
" Expansion " (bottom) slot
48
204
MTG PIN
210
MTG PIN
212
7
208
MTG PIN
=PP0V75_S0_MEM_VTT_B
206
MTG PIN
PIN
PIN
PIN
PIN
MEM_B_CKE & lt; 1 & gt;
76
VREFDQ
VSS
VSS
DQ4
DQ0
DQ5
CRITICAL
DQ1
VSS
VSS
DQS0*
J3100 DQS0
DM0
F-RT-BGA6
VSS
VSS
DQ2
DQ6
DQ3
DQ7
VSS
VSS
DQ8
DQ12
DQ9
DQ13
VSS
VSS
DQS1*
DM1
DQS1
RESET*
VSS
VSS
DQ14
DQ10
DQ15
DQ11
VSS
VSS
DQ20
DQ16
DQ17
DQ21
VSS
VSS
DQS2*
DM2
DQS2
VSS
DQ22
VSS
DQ23
DQ18
DQ19
VSS
DQ28
VSS
DQ24
DQ29
DQ25
VSS
DQS3*
VSS
DM3
DQS3
VSS
VSS
DQ26
DQ30
DQ27
DQ31
VSS
VSS
(1 OF 2)
1
DDR3-SODIMM
OMIT_TABLE
1
C3150
1
C3151
1
C3152
1UF
2
1UF
10%
10V
X5R
402
10%
10V
X5R
402
1
2
2
C3153
1UF
1UF
10%
10V
X5R
402
2
SYNC_MASTER=K92_SUMA
10%
10V
X5R
402
PAGE TITLE
SYNC_DATE=06/23/2010
DDR3 SO-DIMM Connector B
DRAWING NUMBER
516S0806
Apple Inc.
SPD ADDR=0xA4(WR)/0xA5(RD)
051-9585
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
3.0.0
BRANCH
PAGE
31 OF 132
SHEET
29 OF 105
1
A
8
7
6
5
4
3
2
1
SD Card Connector
516-0225
CRITICAL
J3300
SD-CARD-K19-K24
F-RT-TH
CRITICAL
L3300
3
47NH-1.3OHM
97 36
97 36
D
97 36
97 36
SDCONN_CLK
SDCONN_CMD
SDCONN_DATA & lt; 0 & gt;
SDCONN_DATA & lt; 1 & gt;
SDCONN_DATA & lt; 2 & gt;
SDCONN_DATA & lt; 3 & gt;
SDCONN_DATA & lt; 4 & gt;
SDCONN_DATA & lt; 5 & gt;
SDCONN_DATA & lt; 6 & gt;
SDCONN_DATA & lt; 7 & gt;
SDCONN_CARDDETECT_L
IN
OUT
BI
BI
97 36
BI
97 36
BI
97 36
BI
97 36
BI
97 36
BI
97 36
BI
30
OUT
R3379
R3361
R3371
R3372
R3373
R3374
R3375
R3376
R3377
R3378
33
33
33
33
33
33
33
33
33
33
1
2
5%
1/16W MF-LF 402
1
2
5%
1/16W MF-LF 402
1
2
5%
1/16W MF-LF 402
1
2
5%
1/16W MF-LF 402
97
1
2
5%
1/16W MF-LF 402
97
1
2
5%
1/16W MF-LF 402
97
1
2
5%
1/16W MF-LF 402
97
1
2
5%
1/16W MF-LF 402
97
1
2
5%
1/16W MF-LF 402
97
1
2
5%
1/16W MF-LF 402
97
97
97
1
SDCONN_CLK_R
SDCONN_CMD_R
SDCONN_R_DATA & lt; 0 & gt;
SDCONN_R_DATA & lt; 1 & gt;
SDCONN_R_DATA & lt; 2 & gt;
SDCONN_R_DATA & lt; 3 & gt;
SDCONN_R_DATA & lt; 4 & gt;
SDCONN_R_DATA & lt; 5 & gt;
SDCONN_R_DATA & lt; 6 & gt;
SDCONN_R_DATA & lt; 7 & gt;
2
6
SDCONN_CLK_R_L
97
5
2
0402
7
8
9
1
10
11
12
13
14
15
36
16
SDCONN_WP
=PP3V3_S0_SW_SD_PWR
OUT
30
4
NOSTUFF
1
Place near attr for series resistors:
NOSTUFF
C3373
1
10PF
PLACE_NEAR=U3900.21:5MM
PLACE_NEAR=U3900.25:5MM
C3375
1
NOSTUFF
C3377
10PF
5%
25V
2 CER
0201
PLACE_NEAR=U3900.26:5MM
NOSTUFF
1
10PF
5%
25V
CER
0201
5%
25V
CER
0201
2
2
NOSTUFF
C3379
1
C3381
10PF
1
10PF
5%
25V
2 CER
0201
NOSTUFF
C3371
1
22PF
5%
25V
2 CER
0201
5%
50V
2 CERM
402
2
17
C3370
18
15PF
NOSTUFF
19
5%
50V
CERM
402
20
VSS
VSS
CLK
CMD
DAT0
DAT1
DAT2
D
CD/DAT3
DAT4
DAT5
DAT6
DAT7
SD Not Inserted, CARD_DETECT is OPEN.
CAESAR-IV Card Detect is programmable,
but a Silicon bug makes the active
high case unusable.
CARD_DETECT_SW
CARD_DETECT_GND
WRITE_PROTECT_SW
VDD
SHLD_PIN
SHLD_PIN
SHLD_PIN
SHLD_PIN
PLACE_NEAR=U3900.24:5MM
PLACE_NEAR=U3900.23:5MM
PLACE_NEAR=U3900.22:5MM
NOSTUFF
PLACE_NEAR=U3900.52:5MM
1
PLACE_NEAR=U3900.53:5MM
NOSTUFF
C3372
PLACE_NEAR=U3900.55:5MM
1
10PF
5%
2 25V
CER
0201
PLACE_NEAR=U3900.54:5MM
NOSTUFF
C3374
1
10PF
NOSTUFF
C3376
1
10PF
5%
2 25V
CER
0201
C3378
NOSTUFF
1
10PF
5%
2 25V
CER
0201
2
C3380
10PF
5%
25V
CER
0201
2
5%
25V
CER
0201
C
C
SD Detect & Reset Logic
SDCONN_DETECT Debounce, Inversion, Detect-Changed PCH GPIO Latch Circuit
Converts SDCONN from active-low level signal to active-high pulses.
=PP3V3_S4_SD_HPD
C3310
Must STUFF R3312 and NOSTUFF R3314
when R3311 is NOT STUFFED.
R3314 and R3312 mutually exclusive
to bypass reset logic
1
10
7
1UF
R3311 and R3310 mutually exclusive
to control effect of =ENET_RESET_L
on DET_CHANGED# logic.
10%
10V 2
X5R
402-1
1
CRITICAL
U3311
TDFN
2
R3311
=ENET_RESET_L
1
7
30
SDCONN_CARDDETECT_L
SD_DET_LVL_L
1
1
R3310
1
1
0
ENET_RESET_L
2
OUT
36 97
OUT
24 46
- & gt; To SMC & to Isolation Circuit (then to PCH GPIO)
(Low active pulse signal)
OUT
36
- & gt; To ENET Chip
5%
1/16W
MF-LF
402
6
SD_DET_CH_EN_L
(OD)
9
SDCONN_STATE_CHANGE_SMC
8
SDCONN_DETECT_L
DET_OUT
B
DET_LVL
R3316
10K
5%
1/16W
MF-LF
402
THRM
PAD
GND
5%
1/16W
MF-LF
402
2
SLG_ENET_RESET_OUT_L
DET_CHNGD*
(OD)
10K
2
4
DET_CH_EN*
DLY
5
B
IN
DET_IN
(IPU)
SLG_ENET_RESET_IN_L
2
5%
1/16W
MF-LF
402
- & gt; From SD Conn
(Low active)
RST_IN*
RST_OUT*
1
R3317
1
R3312
10K
11
IN
3
RST
LOGIC
XOR
24
- & gt; From PCH GPI0
0
R3314
LOW_PWR
XOR
IN
ENET_LOW_PWR
5%
1/16W
MF-LF
402
2
SLG4AP026V
36 24
R3315
10K
VDD
2
NOSTUFF
0
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
2
DLY block is 20ms nominal
When ENET_LOW_PWR deasserts, RST_OUT#
deasserts for & gt; 80ms, then asserts for
10ms regardless ofmove RST_IN# state.
Otherwise RST_OUT# follows RST_IN#
NOSTUFF
SD Card 3.3V Overcurrent Protection
TPS2065-1 (1.0A limit) has active load discharge so R4810 is NOSTUFF.
CRITICAL
=PP3V3_S0_SW_SD_PWR
U3300
30
TPS2065-1
7
36
=PP3V3_S0_SDCARD
3
4
ENET_CR_PWREN
A
EN
CRITICAL
C3300
10UF
20%
6.3V
2 X5R
603
1
C3301
0.1UF
GND
1
1
10%
16V
2 X7R-CERM
402
OUT0
OUT1
OUT2
6
OC*
IN0
IN1
DGN
5
7
PP3V3_S0_SW_SD_PWR
8
THRM
PAD
9
2
353S3004
CRITICAL
1
C3302
1
1
10UF
C3303
10%
16V
2 X7R-CERM
402
R3300
47K
0.1UF
20%
6.3V
2 X5R
603
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
NOSTUFF
2
=PP3V3_S0_PCH_GPIO
5%
1/16W
MF-LF
402
SYNC_MASTER=J31_YONAS
7 16 17 18 19
SD Card Connector
R33011
DRAWING NUMBER
10K
5%
1/16W
MF-LF
402 2
Apple Inc.
1
0
2
NOTICE OF PROPRIETARY PROPERTY:
SDCONN_OC_L
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
5%
1/16W
MF-LF
402
7
6
5
051-9585
4
3
2
SIZE
D
REVISION
R
R3302
SDCONN_OC_L_R
8
SYNC_DATE=10/25/2011
PAGE TITLE
3.0.0
BRANCH
PAGE
33 OF 132
SHEET
30 OF 105
1
A
8
7
7
6
5
4
3
2
NOTE: Must not enable more than two SO-DIMM margining
buffers at once or VRef source may be overloaded.
=PP3V3_S3_VREFMRGN
VREFDQ:LDO_DAC
OMIT
R3418
68 7
SHORT
1
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
DDRVREF_DAC
C3400
20%
6.3V
CERM
402-LF
1
1
2
2
D
C3401
DDRVREF_DAC
0.1UF
C3403
CRITICAL
DDRVREF_DAC
20%
10V
CERM
402
U3400
8
=I2C_VREFDACS_SCL
6 SCL
=I2C_VREFDACS_SDA
7 SDA
1
2
4
A3
V-
1
1
CRITICAL
R3401
5%
1/16W
MF-LF
PP3V3_S3_VREFMRGN_CTRL
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
NONE
NONE
NONE
402
16
C3402
Power aliases required by this page:
1
0.1UF
- =PP3V3_S3_VREFMRGN
- =PPVTT_S3_DDR_BUF
- =PPDDR_S3_MEMVREF
CRITICAL
DDRVREF_DAC
3
4
5
48
IN
BI
1
VB4
=I2C_PCA9557D_SCL
=I2C_PCA9557D_SDA
1
2
P1
P2
P3
P4
P5
P6
P7
7
- Stuffs Apple margining circuit.
RESET*
THRM
PAD
17
VREFDQ:LDO_DAC - Margined LDO outputs sent to DQ inputs.
PLACE_NEAR=R3405.2:1mm
NC
1
VREFMRGN_DQ_SODIMMA_EN
VREFMRGN_DQ_SODIMMB_EN
VREFMRGN_CA_SODIMMA_EN
VREFMRGN_CA_SODIMMB_EN
VREFMRGN_MEMVREG_EN
VREFMRGN_FRAMEBUF_EN
9
10
11
12
13
14
R3409
200
R3402
1
100K
2
2
PLACE_NEAR=J2900.126:2.54mm
CRITICAL
5%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
DDRVREF_DAC
C3404
DDRVREF_DAC
1
A2
20%
10V
CERM
402
NC
MAX4253
V+
R3410
UCSP
2
A1
A3
15
27 93
C
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.75V
133
VREFMRGN_CA_SODIMMA_BUF
1
2
PLACE_NEAR=R3409.2:1mm
1%
1/16W
MF-LF
402
A4
V-
GND
PP0V75_S3_MEM_VREFCA_A
VREFCA:LDO_DAC
U3403
B1
0.1UF
B4
8
VREFDQ:LDO - LDO outputs sent to DQ inputs.
2
VREFCA:LDO_DAC
DDRVREF_DAC
6
SCL
SDA
29 31 93
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.75V
NC
(OD) P0
A0
A1
A2
133
1%
1/16W
MF-LF
402
PCA9557
Addr=0x30(WR)/0x31(RD)
BOM options provided by this page:
VREFMRGN_DQ_SODIMMB_BUF
C4
U3401
2
QFN
48
C3
VCC
20%
10V
CERM
402
=I2C_VREFDACS_SCL
=I2C_VREFDACS_SDA
=I2C_PCA9557D_SCL
=I2C_PCA9557D_SDA
R3406
UCSP
C1
DDRVREF_DAC
Signal aliases required by this page:
MAX4253
V+
PLACE_NEAR=J3100.1:2.54mm
VREFDQ:LDO_DAC
U3402
C2
2
PP0V75_S3_MEM_VREFDQ_B
NC DDRVREF_DAC
B1
2 402
200
1%
1/16W
MF-LF
402
100K
2
PLACE_NEAR=R3403.2:1mm
R3405
OMIT
DDRVREF_DAC
A4
D
2
1%
1/16W
MF-LF
402
DDRVREF_DAC
a DAC output, cannot enable
R3419
SHORT
133
VREFDQ:LDO_DAC
both at the same time!
C
1
VREFMRGN_MEMVREG_FBVREF
3
Page Notes
VREFMRGN_DQ_SODIMMA_BUF
NOTE: MEMVREG and FRAMEBUF share
GND
1
A1
27 31 93
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.75V
VREFMRGN_SODIMMS_CA
5
2
VREFMRGN_SODIMMB_DQ
VOUTC
R3404
UCSP
B4
10 A1
PLACE_NEAR=J2900.1:2.54mm
VREFDQ:LDO_DAC
MAX4253
V+
VREFMRGN_SODIMMA_DQ
VOUTB
VOUTD
9 A0
Addr=0x98(WR)/0x99(RD)
VOUTA
MSOP
DAC5574
IN
BI
2
PP0V75_S3_MEM_VREFDQ_A
U3402
B1
A2
20%
10V
CERM
402
200
1%
1/16W
MF-LF
402
DDRVREF_DAC
1
0.1UF
VDD
48
1
CRITICAL
DDRVREF_DAC
2.2UF
48
R3403
=PPVTT_S3_DDR_BUF
10mA max load
PP3V3_S3_VREFMRGN_DAC
2
NONE
NONE
NONE
402
-
1
VREFDQ:M1_M3 - CPU margined DDR voltage divider sent to DQ inputs.
VREFCA:LDO_DAC
VREFDQ:M1_DAC - DAC margined DDR voltage divider sent to DQ inputs.
R3411
VREFCA:LDO - LDO outputs sent to CA inputs.
1
VREFCA:LDO_DAC - DAC margined LDO outputs sent to CA inputs.
24
IN
PCA9557D_RESET_L
DDRVREF_DAC
1
RST* on ’platform reset’ so that system
watchdog will disable margining.
NCDDRVREF_DAC
100K
C2
V+
MAX4253
=PPDDR_S3_MEMVREF
UCSP
1
Q3420
1
2
SSM6N15FEAPE
MEMRESET_ISOL_LS5V_L
1
2
1%
1/16W
MF-LF
402
R3408
DDRVREF_DAC
100K
C3405
5%
1/16W
MF-LF
2 402
D
PPCPU_MEM_VREFDQ_A
NC
1K
10%
16V
X5R
402
PP0V75_S3_MEM_VREFDQ_A
CRITICAL
DDRVREF_DAC
1
0.1UF
20%
10V
CERM
402
27 31 93
C2
2
V+
DDRVREF_DAC
U3404
B1
MAX4253
R3414
UCSP
C1
VREFMRGN_MEMVREG_BUF
1
VREFDQ:M1_M3
1
Q3420
5
SSM6N15FEAPE
SOT563
G
MEMRESET_ISOL_LS5V_L
4
DDRVREF_DAC
C3440
5%
1/16W
MF-LF
402
2
5%
1/16W
MF-LF
402
B1
A2
V+
U3404
MAX4253
UCSP
2
A4
VREFMRGN_MEMVREG_FBVREF_R
NC
29 31 93
R3417
PART NUMBER
0
V2
B4
5%
1/16W
MF-LF
402
PLACE_NEAR=R3441.2:1mm
2
MEM B VREF DQ
MEM A VREF CA
MEM B VREF CA
VREFDQ:LDO
2
RES,MTL FILM,0,5%,0402,SM,LF
R3409,R3411
VREFCA:LDO
QTY
DESCRIPTION
REFERENCE DES
R3421,R3422,R3441,R3442
VREFDQ:M1_DAC
114S0171
2
RES,MTL FILM,332,1%,0402,SM,LF
R3404,R3406
VREFDQ:M1_DAC
GPU Frame Buffer (1.8V, 70% VRef)
A
B
C
C
D
2
3
4
5
SYNC_MASTER=J31_ANNE
DDR3/FRAMEBUF VREF MARGINING
6
DRAWING NUMBER
Apple Inc.
0.75V (DAC: 0x3A)
1.5V (DAC: 0x3A)
1.267V (DAC: 0x8B)
Margined target:
0.300V - 1.200V (+/- 450mV)
1.000V - 2.000V (+/- 500mV)
1.056V - 1.442V (+/- 180mV)
DAC range:
0.000V - 1.501V (0x00 - 0x74)
0.000V - 3.000V (0x00 - 0x74)
0.000V - 3.300V (0x00 - 0xFF)
VRef current:
+3.4mA - -3.4mA (- = sourced)
8
7
-61uA (- = sourced)
6
5
NOTICE OF PROPRIETARY PROPERTY:
1.51mV / step @ output
4
051-9585
3
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
2
SIZE
D
REVISION
R
+6.0mA - -5.0mA (- = sourced)
8.59mV / step @ output
SYNC_DATE=06/09/2011
PAGE TITLE
D
1
7.69mV / step @ output
BOM OPTION
RES,MTL FILM,1K,1%,0402,SM,LF
5%
1/16W
MF-LF
402
PCA9557D Pin:
DAC step size:
CRITICAL
4
R3415
MEM VREG
+61uA -
BOM OPTION
R3403,R3405
114S0218
DAC Channel:
Nominal value
CRITICAL
RES,MTL FILM,0,5%,0402,SM,LF
VREFMRGN_FRAMEBUF_BUF_R
100K
2
REFERENCE DES
2
PART NUMBER
1%
1/16W
MF-LF
402
DESCRIPTION
116S0004
DDRVREF_DAC
1
QTY
116S0004
VREFDQ:M1_M3
R3442
1K
MEM A VREF DQ
B
6 68
Required zero ohm resistors when no VREF margining circuit stuffed
DDRVREF_DAC
1
A1
A3
PP0V75_S3_MEM_VREFDQ_B
1
A
OUT
NCDDRVREF_DAC
R3413
100K
0
1%
1/16W
MF-LF
402
2
1
R3416 1
R3441
D
PPCPU_MEM_VREFDQ_B
DDRREG_FB
CRITICAL
1K
10%
16V
X5R
402
2
VREFMRGN_FRAMEBUF_BUF
DDRVREF_DAC
3
S
2
93 9
1
0.1UF
1
VB4
PLACE_NEAR=Q3420.3:1mm
VREFDQ:M1_M3
PLACE_NEAR=Q3420.3:2mm
VREFDQ:M1_M3
33.2K
1%
1/16W
MF-LF
402
C4
1%
1/16W
MF-LF
2 402
NOTE: CPU DAC output step sizes:
DDR3 (1.5V)
7.70mV per step
DDR3L (1.35V) 6.99mV per step
CRITICAL
VREFDQ:M1_M3
31 26
R3422
=PPDDR_S3_MEMVREF
31 7
C3
1K
PLACE_NEAR=R3421.2:1mm
PLACE_NEAR=R3411.2:1mm
DDRVREF_DAC
R3421
6
S
2
1
B
93 9
C3420
0.1UF
SOT563
G
31 26
1
29 93
2
1%
1/16W
MF-LF
402
V-
PLACE_NEAR=Q3420.6:1mm
VREFDQ:M1_M3
PLACE_NEAR=Q3420.6:2mm
VREFDQ:M1_M3
PP0V75_S3_MEM_VREFCA_B
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.75V
133
VREFMRGN_CA_SODIMMB_BUF
C4
B4
CRITICAL
VREFDQ:M1_M3
PLACE_NEAR=J3100.126:2.54mm
R3412
C1
C3
2
VREFCA:LDO_DAC
U3403
B1
5%
1/16W
MF-LF
2 402
NOTE: Margining will be disabled across all
soft-resets and sleep/wake cycles.
31 7
CRITICAL
R3407
200
1%
1/16W
MF-LF
402
3.0.0
BRANCH
PAGE
34 OF 132
SHEET
31 OF 105
1
A
8
7
6
5
4
3
2
1
PLACE_NEAR=J3501.15:2.54mm
C3531
1
1
2
10%
16V
PCIE_AP_R2D_C_P
PCIE_AP_R2D_C_N
0.1UF
16V
0201
X5R-CERM
C3530
0.1UF
2
10%
X5R-CERM
IN
16 96
IN
16 96
0201
PLACE_NEAR=J3501.17:2.54mm
D
D
R3510
1
5% 1/20W
0
PCIE_AP_D2R_P
PCIE_AP_D2R_N
2
MF
201
R3511
1
5% 1/20W
0
OUT
3V S3 WLAN FET
16 96
OUT
16 96
MOSFET
TPCP8102
CHANNEL
P-TYPE
2
MF
201
RDS(ON)
20-30 MOHM @2.5V
LOADING
1 A (EDP)
CRITICAL
Q3550
WIFI_EVENT_L
OUT
DMP2018LFK
6 45 46
DFN2563-6
155S0367
46 6
1
32
2
SM
2
1
MIN_LINE_WIDTH=1 mm
MIN_NECK_WIDTH=0.5 mm
2
S
XW3552
PP3V3_WLAN_F
1
PP3V3_WLAN
MIN_NECK_WIDTH=0.4 mm
MIN_LINE_WIDTH=1 mm
=PP3V3_S3_WLAN
0603
7 32
G
PCIE_AP_R2D_P
4
L3504
FERR-120-OHM-3A
96 6
D
MIN_NECK_WIDTH=0.4 mm
MIN_LINE_WIDTH=1 mm
PP3V3_WLAN_R
C
96 6
PCIE_AP_R2D_N
C3522
1
C3521
3
1
1
C3551
0.1uF
0.1uF
20%
10V
CERM
402
10%
16V
X5R
402
CRITICAL
96
J3501
CRITICAL
F-ST-SM
96
32
2
PLACE_NEAR=J3501.29:2.54MM
PCIE_AP_D2R_R_P
500913-0302
PCIE_AP_D2R_R_N
2
C3550
0.1UF
PLACE_NEAR=J3501.29:2.54MM
1
AIRPORT
L3501
R3550
P3V3WLAN_SS
2
DLP11S
R3551
C
10K
2
33K
1
2
5%
1/16W
MF-LF
402
PM_WLAN_EN_L
2
IN
74
5%
1/16W
MF-LF
402
10%
16V
X5R
402-1
330-OHM-80MA
31
1
0.033UF
20%
10V
CERM
402
516S0582
SYM_VER-1
4
2
4
3
101 6
6
5
101 6
8
10
R3520
51
16 96
19
22
IN
17
20
PCIE_CLK100M_AP_N
15
18
2
13
16
16 96
11
14
IN
9
12
PCIE_CLK100M_AP_P
1
7
3
1
21
5%
1/16W
MF-LF
2 402
24
25
28
95 6
27
95 6
1
R3521
51
NOSTUFF
1
BTPWR:S3
R3518 1
R3517
15K
USB_BT_CONN_P
USB_BT_CONN_N
1
6
PP3V3_S3RS4_BT_F
L3505
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.5 mm
5%
1/20W
MF
201 2
2
VCC
30
1
C3532
2
1
=PP3V3_S4_BT
0.01UF
34
33
2
B
10%
16V
CERM
402
NOSTUFF1
7 32
1
R3515
0402-LF
PLACE_NEAR=J3501.27:2.54mm
2
M+
MD+
D-
7
TQFN
15K
1%
1/20W
MF
201
2
CRITICAL
10
IN
PM_SLP_S4_L
1
2
SEL
OE*
1
G
USB_BT_N
USB_BT_P
BI
8 95
BI
1
8 95
8
R3512
NOSTUFF
1
15K
2
R3513
15K
1%
1/20W
MF
201
2
1%
1/20W
MF
201
3
Delay = 60 ms +/- 20%
SEL
C3511
10%
10V
X5R
201
=PP3V3_S3_WLAN
32
NOSTUFF
OUTPUT
1
1
L
H
0.01UF
USB_BT_WAKE
USB_BT
2
R3553
1
7 32
CRITICAL
R3554
100K
VDD
232K
1%
1/16W
MF-LF
2 402
1%
1/16W
MF-LF
2 402
P3V3WLAN_VMON
1
U3540
2
TDFN
2
C3540
0.1uF
SLG4AP016V
RESET*
20%
10V
CERM
402
SENSE +
0.7V -
4
OUT
6 17 24
518S0815
DLY
6
AP_RESET_CONN_L
AP_RESET_L
MR*
3
EN
OUT
CRITICAL
6
IN
819Q-3506-K281
F-RT-SM1
6
5
4
95 6
3
95 6
2
PP5V_S3_ALSCAMERA_F
=I2C_ALS_SCL
=I2C_ALS_SDA
USB_CAMERA_CONN_P
USB_CAMERA_CONN_N
IN
BI
48
7
1
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm
PLACE_NEAR=J3502.6:2.54MM
7
SYNC_MASTER=J30_MLB
L3508
2
90-OHM
DLP0NS
1
=PP5V_S3_ALSCAMERA
DRAWING NUMBER
7
Apple Inc.
0402-LF
SYM_VER-1
3
USB_CAMERA_P
BI
18 95
USB_CAMERA_N
BI
18 95
1
2
PLACE_NEAR=J3502.2:2.54MM
8
7
6
5
2
051-9585
NOTICE OF PROPRIETARY PROPERTY:
20%
10V
CERM
402
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
4
3
2
SIZE
D
REVISION
R
C3552
0.1uF
1
SYNC_DATE=11/11/2011
X19/ALS/CAMERA CONNECTOR
FERR-120-OHM-1.5A
L3507
4
16
GND
PAGE TITLE
CAMERA
CRITICAL
18 23 74
OUT
AP_CLKREQ_L
1%
1/16W
MF-LF
2 402
ALS
1
THRM
PAD
R3555
8
(OD)
100K
275 mA peak
206 mA nominal max
48
IN
AP_PWR_EN
5
6
AP_CLKREQ_Q_L
9
6
8
24
IN
J3502
A
B
Supervisor & CLKFREG # ISolation
PP3V3_WLAN_F
BTMUX_SEL
5%
1/20W
MF
201
PCIE_WAKE_L
2
USB_BT_WAKEN
GND
R3519
0
S
46
OUT
SSM3K15AMFVAPE
USB_BT_WAKEP
BTPWR:S4
6
D
VESM
1%
1/20W
MF
2 201
PI3USB102ZLE
BTPWR:S4
74 45 26 17
U3510
=BT_WAKE_L
3
R3514
15K
4
NOSTUFF
1%
1/20W
MF
201
1
10%
6.3V
X5R
201
5
Y-
R3516
15K
FERR-120-OHM-1.5A
Y+
2
BTPWR:S4
C3510
0.1UF
0
1%
1/20W
MF
2 201
29
BTPWR:S4
1
5%
1/16W
MF-LF
402 2
BTPWR:S4
CRITICAL
7 32
Q3510
BLUETOOTH
23
26
=PP3V3_S4_BT
1
1
PLACE_NEAR=J3501.11:2.54mm
9
AP_TEMP_SMB_SCL_PD
AP_TEMP_SMB_SDA_PD
PCIE_CLK100M_AP_CONN_P
PCIE_CLK100M_AP_CONN_N
3.0.0
BRANCH
PAGE
35 OF 132
SHEET
32 OF 105
1
A
8
7
6
5
4
3
2
1
CRITICAL
96 8
IN
C3600
PCIE_TBT_R2D_C_P & lt; 0 & gt;
1
96 8
IN
6.3V
X5R
96
201
96
C3601
PCIE_TBT_R2D_C_N & lt; 0 & gt;
OMIT_TABLE
2
10%
0.1UF
1
V19
PCIE_TBT_R2D_P & lt; 0 & gt;
PCIE_TBT_R2D_N & lt; 0 & gt;
T19
2
10%
0.1UF
6.3V
X5R
PER_0_P
PER_0_N
PET_0_P
PET_0_N
U3600
T29
V21
96
T21
96
C3640
PCIE_TBT_D2R_C_P & lt; 0 & gt;
PCIE_TBT_D2R_C_N & lt; 0 & gt;
FCBGA
201
1
PCIE_TBT_D2R_P & lt; 0 & gt;
2
10%
0.1UF
C3641
1
6.3V
10%
0.1UF
X5R
OUT
X5R
6.3V
8 96
OUT
8 96
OUT
8 96
OUT
8 96
OUT
8 96
OUT
8 96
OUT
201
8 96
OUT
201
PCIE_TBT_D2R_N & lt; 0 & gt;
2
8 96
(SYM 1 OF 2)
1
2
10%
0.1UF
96 8
IN
1
IN
C3604
PCIE_TBT_R2D_C_P & lt; 2 & gt;
10%
1
96 8
IN
1
IN
PCIE_TBT_R2D_C_P & lt; 3 & gt;
C3606
IN
PCIE_TBT_R2D_C_N & lt; 3 & gt;
C3607
10%
1
X5R
201
6.3V
X5R
201
PER_1_P
PER_1_N
96
K19
PCIE_TBT_R2D_P & lt; 2 & gt;
PCIE_TBT_R2D_N & lt; 2 & gt;
H19
6.3V
X5R
201
6.3V
X5R
201
PER_2_P
PER_2_N
2
10%
0.1UF
96 8
M19
2
0.1UF
96 8
6.3V
96
C3605
PCIE_TBT_R2D_C_N & lt; 2 & gt;
P19
PCIE_TBT_R2D_P & lt; 1 & gt;
PCIE_TBT_R2D_N & lt; 1 & gt;
2
10%
0.1UF
D
96
201
2
0.1UF
96 8
X5R
96
C3603
PCIE_TBT_R2D_C_N & lt; 1 & gt;
6.3V
96
96
1
F19
PCIE_TBT_R2D_P & lt; 3 & gt;
PCIE_TBT_R2D_N & lt; 3 & gt;
D19
2
10%
0.1UF
6.3V
X5R
PER_3_P
PER_3_N
TRANSMIT
C3602
PCIE_TBT_R2D_C_P & lt; 1 & gt;
PCIE GEN2
IN
RECEIVE
96 8
PET_1_P
PET_1_N
P21
96
M21
96
C3642
PCIE_TBT_D2R_C_P & lt; 1 & gt;
PCIE_TBT_D2R_C_N & lt; 1 & gt;
C3643
PET_2_P
PET_2_N
K21
96
H21
96
PET_3_P
PET_3_N
F21
96
D21
96
C3646
PCIE_TBT_D2R_C_P & lt; 3 & gt;
PCIE_TBT_D2R_C_N & lt; 3 & gt;
TP_TBT_MONDC0
TP_TBT_MONDC1
A20
MONDC0
MONDC1
WAKE*
F1
PERST*
E6
RSENSE
R3651
TBT_PCIE_WAKE_L
E14
TBT_RESET_L
3.3K
2
8
10K
5%
1/16W
MF-LF
402
CRITICAL
OMIT_TABLE
5%
1/16W
MF-LF
402
2
10K
2
2
C
D
U3690
(TBT_SPI_MISO)
M95320-RMB6TG
MLP
(TBT_SPI_CLK)
6
C
(TBT_SPI_CS_L)
1
2
5%
1/16W
MF-LF
402
=TBT_CLKREQ_L
TBT_GPIO & lt; 1 & gt;
TBT_GPIO & lt; 2 & gt;
TBT_RSVD
OUT
R3693
3.3K
98
98
TBTROM_WP_L
3
W_L
TBTROM_HOLD_L
7
HOLD_L
98
VSS
4
PCIE_TBT_D2R_P & lt; 3 & gt;
2
6.3V
X5R
201
PCIE_TBT_D2R_N & lt; 3 & gt;
2
10%
6.3V
X5R
201
2
D
7 33 34 35
1
5%
1/16W
MF-LF
402
E16
2
TBT_RBIAS
10K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
2 402
S_L
201
1K
1%
1/16W
MF-LF
402
98
THM
PAD
P3
TBT_SPI_MOSI
TBT_SPI_MISO
TBT_SPI_CS_L
TBT_SPI_CLK
P1
TP_TBT_THERM_DP
2
Q
X5R
R3655 1
RBIAS
35
1
5
6.3V
R3621
VCC
(TBT_SPI_MOSI)
201
TBT_RSENSE
MONOBSN
A2
THERM_DP
E4
TEST_EN
TEST_POINT_0
TEST_POINT_1
TEST_POINT_2
TEST_POINT_3
N4
M3
L4
M1
N2
L2
PCIE_CLKREQ_0*
PCIE_CLKREQ_1*
PCIE_CLKREQ_2*
PCIE_CLKREQ_3*
EE_DI
EE_DO
EE_CS*
EE_CLK
1
TBT_TEST_EN
TP_TBT_TEST_POINT_0
TP_TBT_TEST_POINT_1
TP_TBT_TEST_POINT_2
TBT_TEST_POINT_3
R3625
0
2
5%
1/16W
MF-LF
402
P5
N6
M5
L6
K1
TDI
TMS
TCK
TDO
T3
J2
K3
J4
Not used in host mode.
TP_TBT_PCIE_RESET0_L
TP_TBT_PCIE_RESET1_L
TP_TBT_PCIE_RESET2_L
TP_TBT_PCIE_RESET3_L
T1
H17
G16
P17
TMU_CLK_OUT
TMU_CLK_IN
U2
6
6
6
PCIE_CLK100M_TBT_P
PCIE_CLK100M_TBT_N
XTAL_25_IN
XTAL_25_OUT
6
JTAG_TBT_TDI
JTAG_TBT_TMS
JTAG_TBT_TCK
JTAG_TBT_TDO
REFCLK_100_IN_P
REFCLK_100_IN_N
Use B1 GND ball for THERM_DN
9
PCIE_RST_0*
PCIE_RST_1*
PCIE_RST_2*
PCIE_RST_3*
JTAG
1UF
10%
6.3V
CERM
402
M17
POWER ON RESET
5%
1/16W
MF-LF
2 402
TP_TBT_MONOBSN
CLOCKS
3.3K
1
R3622
X5R
35
IN
DEBUG: For monitoring clock
MISC
R3691
1
MONOBSP
CLK REQUEST
5%
1/16W
MF-LF
402 2
R3623 1
K17
TEST PORT
3.3K
R3692 1
TP_TBT_MONOBSP
EEPROM
R3690
1
201
PCIE_TBT_D2R_N & lt; 2 & gt;
10K
6
C3690
6.3V
2
10%
1
X5R
=PP3V3_TBT_RTR
6
1
1
201
PCIE_TBT_D2R_P & lt; 2 & gt;
2
10%
0.1UF
C3647
X5R
6.3V
10%
1
0.1UF
DEBUG: For monitoring current/voltage
1
1
C3645
6.3V
PCIE_TBT_D2R_N & lt; 1 & gt;
2
10%
0.1UF
0.1UF
B21
6
35 34 33 7
1
C3644
PCIE_TBT_D2R_C_P & lt; 2 & gt;
PCIE_TBT_D2R_C_N & lt; 2 & gt;
PCIE_TBT_D2R_P & lt; 1 & gt;
2
10%
0.1UF
201
6
=PP3V3_TBT_RTR
1
0.1UF
R4
R2
R16
E2
IN
8 19
IN
8
=PP3V3_TBT_RTR
C
7 33 34 35
16
IN
OUT
1
8
R3698
10K
IN
16 96
IN
16 96
2
5%
1/16W
MF-LF
402
R3695
806
SYSCLK_CLK25M_TBT_R
TP_TBT_XTAL25OUT
1
R3696 1
TBT_TMU_CLK_OUT
TBT_TMU_CLK_IN
SYSCLK_CLK25M_TBT
2
IN
24
1%
1/16W
MF-LF
402
1K
5%
1/16W
MF-LF
402 2
NO STUFF
R3699 1
10K
98 81 6
IN
DP_TBTSNK0_ML_C_P & lt; 1 & gt;
C3622
1
0.1uF
98 81 6
IN
DP_TBTSNK0_ML_C_N & lt; 1 & gt;
C3623
1
B
98 33 6
98 33 6
DP_TBTSNK0_ML_P & lt; 1 & gt;
6 33 98
98 33 6
16V
402
98 33 6
DP_TBTSNK0_ML_N & lt; 1 & gt;
2
10%
X5R
0.1uF
98 33 6
16V
402
2
10%
X5R
6 33 98
6 33 98
16V
402
98 33 6
98 33 6
98 81 6
IN
DP_TBTSNK0_ML_C_P & lt; 2 & gt;
C3624
1
98 81 6
IN
DP_TBTSNK0_ML_C_N & lt; 2 & gt;
C3625
1
98 81 6
IN
DP_TBTSNK0_ML_C_P & lt; 3 & gt;
C3626
1
98 81 6
IN
DP_TBTSNK0_ML_C_N & lt; 3 & gt;
BI
DP_TBTSNK0_AUXCH_C_P
C3627
1
0.1uF
DP_TBTSNK0_ML_N & lt; 2 & gt;
6 33 98
DP_TBTSNK0_ML_N & lt; 3 & gt;
5%
1/16W
MF-LF
402
6 33 98
98 33 6
98 33 6
2
98 33 6
6 33 98
16V
402
98 33 6
98 33 6
98 81 6
C3628
1
0.1uF
98 81 6
BI
DP_TBTSNK0_AUXCH_C_N
C3629
1
6 33 98
98 33 6
16V
402
DP_TBTSNK0_AUXCH_N
2
10%
X5R
0.1uF
DP_TBTSNK0_AUXCH_P
2
10%
X5R
98 33 6
6 33 98
16V
402
98 33 6
SNK1 AC Coupling
C3630
IN
DP_TBTSNK1_ML_C_P & lt; 0 & gt;
98 81 6
IN
DP_TBTSNK1_ML_C_N & lt; 0 & gt;
C3631
98 81 6
IN
DP_TBTSNK1_ML_C_P & lt; 1 & gt;
C3632
1
10%
X5R
0.1uF
1
10%
X5R
0.1uF
1
0.1uF
98 81 6
IN
DP_TBTSNK1_ML_C_N & lt; 1 & gt;
C3633
1
A
98 81 6
IN
DP_TBTSNK1_ML_C_P & lt; 2 & gt;
C3634
1
98 81 6
IN
DP_TBTSNK1_ML_C_N & lt; 2 & gt;
C3635
1
DP_TBTSNK1_ML_P & lt; 1 & gt;
86 82
OUT
5%
1/16W
MF-LF
402
IN
DP_TBTSNK1_ML_C_P & lt; 3 & gt;
C3636
1
98 87 6
OUT
98 87 6
OUT
98 87
6 33 98
16V
402
98 87
IN
IN
DP_TBTSNK1_ML_N & lt; 2 & gt;
OUT
87
DP_TBTSNK1_ML_P & lt; 2 & gt;
87
IN
6 33 98
16V
402
6 33 98
16V
402
10%
X5R
0.1uF
98 81 6
IN
DP_TBTSNK1_ML_C_N & lt; 3 & gt;
C3637
1
OUT
OUT
6 33 98
16V
402
98 87
DP_TBTSNK1_ML_N & lt; 3 & gt;
2
10%
X5R
0.1uF
98 87 6
DP_TBTSNK1_ML_P & lt; 3 & gt;
2
98 87
6 33 98
16V
402
IN
IN
BI
DP_TBTSNK1_AUXCH_C_P
C3638
BI
DP_TBTSNK1_AUXCH_C_N
C3639
1
98 81 6
0.1uF
8
1
10%
X5R
DP_TBTSNK1_AUXCH_N
6 33 98
IN
BI
98 48
16V
402
7
W2
V5
DPSNK0_AUX_CHP
DPSNK0_AUX_CHN
DP_TBTSNK1_ML_P & lt; 3 & gt;
DP_TBTSNK1_ML_N & lt; 3 & gt;
V9
DP_TBTSNK1_ML_P & lt; 2 & gt;
DP_TBTSNK1_ML_N & lt; 2 & gt;
V11
DP_TBTSNK1_ML_P & lt; 1 & gt;
DP_TBTSNK1_ML_N & lt; 1 & gt;
V13
U8
DPSNK0_HOT_PLUG_DET
U10
U12
V15
DP_TBTSNK1_ML_P & lt; 0 & gt;
DP_TBTSNK1_ML_N & lt; 0 & gt;
U14
DPSNK1_ML_LANE_3P
DPSNK1_ML_LANE_3N
DPSNK1_ML_LANE_2P
DPSNK1_ML_LANE_2N
DPSNK1_ML_LANE_1P
DPSNK1_ML_LANE_1N
DPSNK1_ML_LANE_0P
DPSNK1_ML_LANE_0N
DPSRC0_ML_LANE_3P
DPSRC0_ML_LANE_3N
DPSRC0_ML_LANE_2P
DPSRC0_ML_LANE_2N
DPSRC0_ML_LANE_1P
DPSRC0_ML_LANE_1N
DPSRC0_ML_LANE_0P
DPSRC0_ML_LANE_0N
DPSRC0_AUX_CHP
DPSRC0_AUX_CHN
DPSRC0_HOT_PLUG_DET
DP_ATEST
DP_RES_0
DP_RES_1
AA18
Y17
AA16
Y15
AA14
Y13
AA12
Y11
W16
TP_DP_TBTSRC_ML_CP & lt; 3 & gt;
TP_DP_TBTSRC_ML_CN & lt; 3 & gt;
DP_TBTSNK1_AUXCH_P
DP_TBTSNK1_AUXCH_N
V7
U4
TBT_R2D_C_P & lt; 0 & gt;
TBT_R2D_C_N & lt; 0 & gt;
A6
C4
TBT_LSEO & lt; 0 & gt;
TBT_LSOE & lt; 0 & gt;
J6
6
6
TP_DP_TBTSRC_ML_CP & lt; 1 & gt;
TP_DP_TBTSRC_ML_CN & lt; 1 & gt;
6
TP_DP_TBTSRC_ML_CP & lt; 0 & gt;
TP_DP_TBTSRC_ML_CN & lt; 0 & gt;
U16
6
6
TP_DP_TBTSRC_AUXCH_CP
TP_DP_TBTSRC_AUXCH_CN
V3
B
6
DP_TBTSRC_HPD
Y19
6
6
100pF SRF & gt; 40MHz
BYPASS=U3600.Y19::2mm
BYPASS=U3600.Y19::5.08mm
TBT_DP_ATEST
Y21
AA20
C3685
TBT_DP_RES
1
1
2
2
100PF
PRT0_T29T_P
PRT0_T29T_N
TBT_D2R_P & lt; 0 & gt;
TBT_D2R_N & lt; 0 & gt;
6
TP_DP_TBTSRC_ML_CP & lt; 2 & gt;
TP_DP_TBTSRC_ML_CN & lt; 2 & gt;
DPSNK1_HOT_PLUG_DET
U6
6
1
1
14.0K
DPSNK1_AUX_CHP
DPSNK1_AUX_CHN
1%
1/16W
MF-LF
402
5%
50V
CERM
402
R3632
100K
2
2
C3686
0.01UF
10%
16V
CERM
402
5%
1/16W
MF-LF
402
A4
C2
K5
A10
TBT_R2D_C_P & lt; 1 & gt;
TBT_R2D_C_N & lt; 1 & gt;
A8
TBT_D2R_P & lt; 1 & gt;
TBT_D2R_N & lt; 1 & gt;
C8
TBT_LSEO & lt; 1 & gt;
TBT_LSOE & lt; 1 & gt;
G6
I2C_TBT_SDA
I2C_TBT_SCL
F3
C6
H5
PRT0_T29R_P
PRT0_T29R_N
PRT2_T29T_P
PRT2_T29T_N
T29_0_LSEO
T29_0_LSOE
PRT1_T29T_P
PRT1_T29T_N
PRT1_T29R_P
PRT1_T29R_N
A14
PRT2_T29R_P
PRT2_T29R_N
C12
T29_2_LSEO
T29_2_LSOE
A12
C10
G4
H3
TBT_R2D_C_P & lt; 2 & gt;
TBT_R2D_C_N & lt; 2 & gt;
OUT
8 98
OUT
8 98
IN
8 98
IN
TBT_D2R_P & lt; 2 & gt;
TBT_D2R_N & lt; 2 & gt;
8 98
TBT_LSEO & lt; 2 & gt;
TBT_LSOE & lt; 2 & gt;
OUT
8
IN
8
TBT_R2D_C_P & lt; 3 & gt;
TBT_R2D_C_N & lt; 3 & gt;
OUT
6
OUT
F5
5
SYNC_MASTER=T29_REF
SYNC_DATE=06/14/2011
PAGE TITLE
PRT3_T29T_P
PRT3_T29T_N
T29_1_LSEO
T29_1_LSOE
A18
PRT3_T29R_P
PRT3_T29R_N
C16
T29_3_LSEO
T29_3_LSOE
A16
C14
G2
H1
OUT
TBT_LSEO & lt; 3 & gt;
TBT_LSOE & lt; 3 & gt;
8 98
IN
T29_SDA
T29_SCL
8 98
OUT
8
IN
8
NOTE: All unused LSOE/EO pairs should be aliased
together. Other signals okay to float (TP/NC).
4
3
DRAWING NUMBER
8 98
IN
TBT_D2R_P & lt; 3 & gt;
TBT_D2R_N & lt; 3 & gt;
Thunderbolt Host (1 of 2)
8 98
6 33 98
16V
402
2
OUT
98 48
DP_TBTSNK1_AUXCH_P
2
10%
X5R
0.1uF
87
87
98 81 6
V1
DPSNK0_ML_LANE_0P
DPSNK0_ML_LANE_0N
2
98 87 6
0.1uF
98 81 6
DP_TBTSNK0_AUXCH_P
DP_TBTSNK0_AUXCH_N
Y9
DPSNK0_ML_LANE_1P
DPSNK0_ML_LANE_1N
2
R3631 1
100K
DP_TBTSNK1_ML_N & lt; 1 & gt;
2
10%
X5R
6 33 98
16V
402
2
10%
X5R
0.1uF
6 33 98
16V
402
2
10%
X5R
0.1uF
DP_TBTSNK1_ML_N & lt; 0 & gt;
2
10%
X5R
6 33 98
16V
402
2
AA10
Y7
DP_TBTSNK1_HPD
98 33 6
DP_TBTSNK1_ML_P & lt; 0 & gt;
2
DP_TBTSNK0_ML_P & lt; 0 & gt;
DP_TBTSNK0_ML_N & lt; 0 & gt;
Y5
DPSNK0_ML_LANE_2P
DPSNK0_ML_LANE_2N
R3685
98 33 6
98 81 6
AA8
DP_TBTSNK0_HPD
OUT
100K
DP_TBTSNK0_ML_P & lt; 3 & gt;
DP_TBTSNK0_ML_P & lt; 1 & gt;
DP_TBTSNK0_ML_N & lt; 1 & gt;
Y3
R3630 1
16V
402
2
10%
X5R
86 82
16V
402
2
10%
X5R
0.1uF
6 33 98
16V
402
2
10%
X5R
0.1uF
DP_TBTSNK0_ML_P & lt; 2 & gt;
2
10%
X5R
0.1uF
AA6
PORT2
10%
X5R
0.1uF
DP_TBTSNK0_ML_N & lt; 0 & gt;
16V
402
2
DP_TBTSNK0_ML_P & lt; 2 & gt;
DP_TBTSNK0_ML_N & lt; 2 & gt;
PORT3
1
98 33 6
SOURCE PORT 0
10%
X5R
0.1uF
C3621
98 33 6
5%
1/16W
MF-LF
402 2
6 33 98
SINK PORT 0
DP_TBTSNK0_ML_C_N & lt; 0 & gt;
DP_TBTSNK0_ML_P & lt; 0 & gt;
2
SINK PORT 1
IN
1
5%
1/16W
MF-LF
402
DPSNK0_ML_LANE_3P
DPSNK0_ML_LANE_3N
PORTS
98 81 6
0
SNK0 AC Coupling
C3620
AA4
PORT0
IN
DP_TBTSNK0_ML_C_P & lt; 0 & gt;
DP_TBTSNK0_ML_P & lt; 3 & gt;
DP_TBTSNK0_ML_N & lt; 3 & gt;
PORT1
98 81 6
98 33 6
DISPLAY
R3629 1
Apple Inc.
051-9585
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
2
SIZE
D
REVISION
3.0.0
BRANCH
PAGE
36 OF 132
SHEET
33 OF 105
1
A
8
7
6
5
4
D
3
2
=PP3V3_TBT_RTR
CRITICAL
=PP1V05_TBT_RTR
OMIT_TABLE
H9
2100 mA (Single Port)
2250 mA (Dual Port)
EDP: 3000 mA
H11
C3700
1
1
10UF
20%
6.3V
X5R
603
C3705
1
1UF
2
2
10%
6.3V
CERM
402
C3706
1
1UF
2
10%
6.3V
CERM
402
C3707
1
1UF
2
10%
6.3V
CERM
402
C3708
1
1UF
2
10%
6.3V
CERM
402
C3709
1UF
2
10%
6.3V
CERM
402
H13
K9
K11
K13
M9
M11
M13
C3701
1
1
10UF
20%
6.3V
X5R
603
C3710
1
1UF
2
2
10%
6.3V
CERM
402
C3711
1
1UF
2
10%
6.3V
CERM
402
C3712
1
1UF
2
10%
6.3V
CERM
402
C3713
1
1UF
2
10%
6.3V
CERM
402
C3714
H15
1UF
2
10%
6.3V
CERM
402
K15
M15
E8
E10
E12
G14
R8
R10
1
C3720
1
C3721
1
C3722
R12
VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC3P3
VCC3P3
VCC3P3
U3600
T29
FCBGA
H7
C3744
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC3P3_T29
VCC3P3_T29
VCC3P3_DP_RX1
VCC3P3_DP_RX1
C3743
1
C3745
1
1
C3746
1UF
1UF
2
10%
6.3V
CERM
402
20%
6.3V
X5R
603
1
2
2
2
VDD3P3DP_PLL
C3747
D
7 33 35
135 mA (Single-Port)
152 mA (Dual-Port)
EDP: 200 mA
10UF
2
20%
6.3V
X5R
603
G10
G12
P7
R6
1
C3750
1UF
P9
P11
1UF
1UF
1UF
10%
6.3V
CERM
402
2
10%
6.3V
CERM
402
10%
6.3V
CERM
402
2
10%
6.3V
CERM
402
C3760
VDD1P0_DP_RX1
VDD1P0_DP_TXRX
VDD1P0_DP_TXRX
VCC3P3_DP_TXRX
VCC3P3_DP_TXRX
1
10UF
10%
6.3V
CERM
402
C3753
K7
1
C3752
1
C3751
2
1
2
P13
1UF
2
1
1UF
10%
6.3V
CERM
402
M7
(SYM 2 OF 2)
VCC
104 7
1
1UF
1UF
1UF
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
2
2
2
C
C
L3730
L3770
FERR-120-OHM-1.5A
FERR-120-OHM-1.5A
2
0402
R14
PP1V05_TBT_VDD_DPPLL
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
1
20%
6.3V
CERM
402-LF
P15
J8
J10
J14
L8
L10
L12
L14
N8
N10
N12
N14
B1
B3
B5
B7
B9
B11
B13
B15
B17
B19
C18
C20
D1
D3
D5
D7
D9
D11
D13
D15
D17
E18
E20
F7
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSDP
VSSDP
VSSDP
VSSDP
VSSDP
VSSDP
VSSDP
VSSDP
VSSDP
VSSDP
VSSDP
VSSDP
VSSDP
VSSDP
VSSDP
VSSDP_PLL
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
1
PP3V3_TBT_DPBIAS
C3770
G8
J12
B
VCC3P3_DP_TXRXBIAS
C3730
2.2UF
2
VDD1P0_DP_PLL
GND
1
1
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
2
0402
2.2UF
T5
20%
6.3V
CERM
402-LF
T7
T9
2
T11
T15
T17
V17
W4
W6
W8
W10
W12
W14
Y1
AA2
T13
F9
F11
F13
B
F15
F17
G18
G20
J16
J18
J20
L16
L18
L20
N16
N18
N20
R18
R20
U18
U20
W18
W20
A
SYNC_MASTER=T29_REF
SYNC_DATE=06/14/2011
PAGE TITLE
Thunderbolt Host (2 of 2)
DRAWING NUMBER
Apple Inc.
051-9585
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
Current numbers from Vendor slide ( & lt; REDACTED & gt; power measure 1.ppt), emailed 6/21/2010, TDP @ 90C.
8
7
6
5
4
3
2
SIZE
D
REVISION
3.0.0
BRANCH
PAGE
37 OF 132
SHEET
34 OF 105
1
A
470K
D
2
1
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
TBTBST:Y
C3880
C3890
10%
25V
X5R
402
2
2
R3891 1
1%
1/16W
MF-LF
402
2
R3889
2
TBTBST_PWREN_DIV_L
VIN
CRITICAL
TBTBST:Y
2
& lt; R1 & gt;
25
TBTBST_EN_UVLO
1
EN/UVLO
28
TBTBST_INTVCC
INTVCC
6
SNS2
3
TBTBST_VC
TBTBST_VSNS_RC
2
C3892
Q3805
10%
10V
X5R
805
SOD-VESM-HF
TBTBST_RT
5%
50V
CERM
402
RT
10K
1%
1/16W
MF-LF
402
32
34
2
SS
SYNC
2
C3893
0.0033UF
1%
1/16W
MF-LF
402
2
10%
50V
CERM
402
R3894
1
1
41.2K
1%
1/16W
MF-LF
402
1
0.33UF
2
2
& lt; R2 & gt;
SGND
10%
6.3V
CERM-X5R
402
=PP3V3_TBT_RTR
1
0.1UF
10%
25V
X5R
402
Platform (PCIe) Reset
24
=TBT_RESET_L
IN
R3803
U3800
2
SLG4AP016V
2
19
IN
IN
1
15.8K
2
Max Current = 1A
C3897
4.7UF
4.7UF
10%
50V
X7R-CERM
1206
2
Freq = 300KHz
10%
50V
X7R-CERM
1206
TBTBST:Y
TBTBST:Y
C3896
1%
1/16W
MF-LF
402 2
C3898
1
4.7UF
10%
50V
X7R-CERM
1206
10%
50V
X7R-CERM
1206
TBTBST:Y
1
1
2
2
4.7UF
2
C3899
0.001UF
10%
50V
X7R
402
Vout = 1.6V * (1 + Ra / Rb)
C
TBTBST:Y
1
5%
1/16W
MF-LF
402
S
G
2
1
Max Vgs: 10V
R3888
2
5%
1/16W
MF-LF
402
TBTBST_SHDN_DIV
TBTBST:Y
1
7
2
R3887
TBTBST:Y
3
D
330K
2
Q3888
SSM6N37FEAPE
5%
1/16W
MF-LF
402
SOT563
1
TBT_PWR_EN
TBT_CLKREQ_L
3
RESET*
MR*
4
TBT_RESET_L
OUT
IN
4
33
6
8
EN
OUT
IN
(OD)
Pull-ups provided by SB page.
THRM
PAD
7
G
5
SMC_DELAYED_PWRGD
=TBT_CLKREQ_L
TBT_CLKREQ_ISOL_L
IN
45 46 92
MAKE_BASE=TRUE
9
5
GND
S
33
DLY = 60 ms +/- 20%
OUT
R3896
C3895
DLY
TBT_SW_RESET_L
24
5%
50V
CERM
402
1
1
330K
R3807
PP1V05_TBT
+ SENSE
- 0.7V
2
10K
5%
1/16W
MF-LF
402
Open-Drain GPIO
Q3888
SOT563
7 33 34
100K
VDD
TDFN
16
D
SSM6N37FEAPE
CRITICAL
& lt; Ra & gt;
TBTBST:Y
7 8
Vout = 15.47V
TBTBST:Y
TBTBST:Y
TBTBST:Y
6
=PP3V3_S0_TBTPWRCTL
C3800
2
GND_TBTBST_SGND
Supervisor & CLKREQ# Isolation
1
2
& lt; Rb & gt;
C
1
C3889
100PF
GND
SGND shorted to
GND inside package,
no XW necessary.
PLACE_NEAR=C3895.1:2 mm
=PP15V_TBT_REG
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=0V
UVLO(falling) = 1.22 * (R1 + R2) / R2
UVLO(rising) = UVLO(falling) + (2uA * R1)
UVLO = 4.55V (falling), 4.95 (rising)
7
1%
1/16W
MF-LF
402
TBTBST_FBX
31
C3894
16
1
73.2K
1
137K
5%
50V
CERM
402
NO STUFF
15
R3892
TBTBST:Y
14
1
TBTBST:Y
FBX
TBTBST:Y
13
TBTBST:Y
2
R3895 1
C3888
22PF
1
2
TBTBST_VC_RC
2
TBTBST:Y
NC
36
TBTBST_SS
SM
TBTBST_VSNS
TBTBST:Y
10
35
12
S
2
2
37
IN
TBT_A_HV_EN
G
C3887
47PF
2
33
NC
R3893 1
24
1
88 87
1
4.7UF
SSM3K15FV
1
XW3895
1
1%
1/16W
MF-LF
402
17
3
VC
23
D
D
TBTBST:Y
49.9K
QFN
TBTBST:Y
4
TBTBST:Y
30
POWERDI-123
DFLS230L
K
R3890
1
TBTBST:Y
1
TBTBST_SNS2
SNS1
2
TBTBST:Y
CRITICAL
TBTBST:Y
D3895
5%
1/16W
MF-LF
402 2
SW
LT3957
TBTBST_PWREN_L
A
0
U3890
330K
5%
1/16W
MF-LF
402
TBTBST_SNS1
TBTBST:Y
200K
TBTBST:Y
R3881
10%
25V
X5R
805
TBTBST_BOOST
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
SWITCH_NODE=TRUE
DIDT=TRUE
1
10UF
10%
25V
X5R
805
TBTBST:Y
0.1UF
5%
1/16W
MF-LF
402
C3891
10UF
2
PCMB063T-100MS
TBTBST:Y
1
38
1
L3895
10UH-4A-68-MOHM
PPVIN_SW_TBTBST
Voltage not specified here,
add property on another page.
TBTBST:Y
R3880 1
BOM options provided by this page:
TBTBST:Y - Stuffs 15V boost circuitry.
S
3
TBTBST:Y
Signal aliases required by this page:
- =TBT_CLKREQ_L
- =TBT_RESET_L
7
G
(1.05V FET Input)
(1.05V FET Output)
BGA
1
CRITICAL
TBTBST:Y
21
=PPVIN_SW_TBTBST
8-13V Input
Changes required
for 2S.
2
Thunderbolt 15V Boost Regulator
-30V
+/-12V
-1.4V
46mOhm @ 4.5V Vgs
3.7A @ 70C
8
Q3880
SI8409DB
3
9
SI8409DB:
Vds(max):
Vgs(max):
Vgs(th):
Rds(on):
Id(max):
CRITICAL
TBTBST:Y
8 7
4
20
this page:
(8-13V Boost Input)
(15V Boost Output)
(3.3V FET Input)
(3.3V FET Output)
5
1
D
6
4
Power aliases required by
- =PPVIN_SW_TBTBST
- =PP15V_TBT_REG
- =PP3V3_S0_P3V3TBTFET
- =PP3V3_TBT_FET
- =PP3V3_S0_TBTPWRCTL
- =PP1V05_S0_P1V05TBTFET
- =PP1V05_TBT_FET
7
27
8
Page Notes
B
B
3.3V Thunderbolt Switch
U3810
7
TPS22924
=PP3V3_S0_P3V3TBTFET
=PP3V3_TBT_FET
7
CSP
A2
B2
A1
VIN
VOUT
Max Current = 2A (85C)
B1
U3810
CRITICAL
C3810
1
C2
ON
C1
2
R3816
TPS22924C
Type
Load Switch
R(on)
@ 2.5V
10%
6.3V
CERM
402
Part
GND
1UF
18.3 mOhm Typ
24 mOhm Max
1
0
5%
1/16W
MF-LF
402
2
TBT_PWR_EN_RC
1.05V Thunderbolt Switch
U3815
7
TPS22920
=PP1V05_S0_P1V05TBTFET
=PP1V05_TBT_FET
7
CSP
A2
A
A1
B2
B1
VIN
VOUT
C2
1
D2
Part
SYNC_MASTER=T29_REF
Type
Thunderbolt Power Support
Load Switch
R(on)
@ 1.05V
2
SYNC_DATE=06/22/2011
PAGE TITLE
TPS22920
8 mOhm Typ
11.5 mOhm Max
DRAWING NUMBER
D1
10%
6.3V
CERM
402
ON
GND
1UF
U3815
C1
CRITICAL
C3815
Max Current = 4A (85C)
Apple Inc.
051-9585
R
NOTICE OF PROPRIETARY PROPERTY:
1
1UF
10%
6.3V
CERM
402
8
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
2
7
6
5
4
3
2
D
3.0.0
NO STUFF
C3816
SIZE
REVISION
BRANCH
PAGE
38 OF 132
SHEET
35 OF 105
1
A
8
7
6
5
4
3
2
BCM57765 ENET SR pins are internal 1.2V switching regulator. See note for SR_DISABLE below.
If disabled: Okay to float VDD, VDDP & LX pin. VFB must always connect to =PP1V2_S3_ENET_PHY.
If enabled: VDD/VDDP connect to =PP3V3_S3_ENET_PHY (add bypassing), LX connects to inductor.
Special Star routing needed on these pins. Decoupling on Pg 37.
1
=PP1V2_ENET_PHY
7
???mA (1000base-T, Caesar V)
72 36 24 7
=PP3V3_ENET_PHY
281mA (1000base-T max power, Caesar IV)
36
VDD for Card Reader I/O
=PP3V3R1V8_ENET_LR_OUT
ENET_SR_LX
2
D
72
Internal 1.2V Switching Regulator pins.
L3900
1
72
ENET_SR_VFB
CRITICAL
FERR-600-OHM-0.5A
CRITICAL
L3920
PP3V3_S3_ENET_PHY_XTALVDDH
FERR-600-OHM-0.5A
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
SM
C3900
PP1V2_ENET_PHY_AVDDL
1
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.2V
0.1UF
10%
16V
X7R-CERM
402
CRITICAL
1
2
0.1UF
1
2
CRITICAL
2
C3926
1
R3910 1
OUT
1
(See note)
96 16
97 30
16
34
31
30
30 24
36
36
36
11
PERST*
(IPD)
ENET_CLKREQ_L
12
CLKREQ*
TRD0_P
TRD0_N
TRD1_P
TRD1_N
TRD2_P
TRD2_N
TRD3_P
TRD3_N
(OD)
3
WAKE*
GPIO_0/CR_ACT_LED*
GPIO_1/LR_OUT
GPIO_2/MEDIA_SENSE
(OD)
ENET_LOW_PWR
4
6
10
BCM57765_SCLK
BCM57765_MISO
BCM57765_MOSI
BCM57765_CS_L
66
64
65
63
TP_BCM57765_SPD100LED_L
TP_BCM57765_TRAFFICLED_L
24
2
67
SYSCLK_CLK25M_ENET
IN
10%
6.3V
X5R-CERM
603
18
NC
BCM57765_RDAC
19
38
1
1
10%
16V
X7R-CERM
402
C3935
LR_OUT/GPIO1 is used as a 3.3V/1.8V internal LDO out for
the card reader on-chip I/O.
Connect only to U3900 pin 20.
10UF
2
2
10%
6.3V
X5R
805
ENET_MDI_P & lt; 0 & gt;
ENET_MDI_N & lt; 0 & gt;
ENET_MDI_P & lt; 1 & gt;
ENET_MDI_N & lt; 1 & gt;
ENET_MDI_P & lt; 2 & gt;
ENET_MDI_N & lt; 2 & gt;
ENET_MDI_P & lt; 3 & gt;
ENET_MDI_N & lt; 3 & gt;
40
41
44
43
46
47
50
49
5
BI
37 97
BI
37 97
BI
37 97
BI
37 97
BI
37 97
BI
37 97
BI
MAKE_BASE=TRUE
37 97
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.8V
1
C3970
1
C3971
4.7UF
2
1
0.1UF
10%
6.3V
X5R-CERM
603
10%
16V
X7R-CERM
402
2
C3972
0.1UF
2
10%
16V
X7R-CERM
402
NC
8
ENET_MEDIA_SENSE
9
OUT
24
IN
30
NOTE: " IPx " == Programmable pull-up/down
LOW_PWR
CR_CMD
26
SDCONN_CMD
IN
30 97
CR_CLK
(IPD)
SMB_CLK
SMB_DATA
SDCONN_DETECT_L
SD_DETECT o1
21
SDCONN_CLK
OUT
30 97
CR_DATA0
CR_DATA1
CR_DATA2
CR_DATA3
CR_DATA4
CR_DATA5
CR_DATA6
CR_DATA7
25
SDCONN_DATA & lt; 0 & gt;
SDCONN_DATA & lt; 1 & gt;
SDCONN_DATA & lt; 2 & gt;
SDCONN_DATA & lt; 3 & gt;
SDCONN_DATA & lt; 4 & gt;
SDCONN_DATA & lt; 5 & gt;
SDCONN_DATA & lt; 6 & gt;
SDCONN_DATA & lt; 7 & gt;
MS_INS*
CR_LED*/CR_BUS_PWR
CR_WP*
SR_DISABLE
59
(IPU)
(IPD)
SCLK_SPD1000LED*
SI/EEDATA
SO_LINKLED*
CS*/EECLK
SPD100LED*/SERIAL_DO
TRAFFICLED*/SERIAL_DI
(OD)
(OD)
XTALI
XTALO
RDAC
24
23
22
52
53
54
55
60
TP_CE_L_MS_INS_L
ENET_CR_PWREN
OUT
BDM57765_SR_DISABLE
R3980
30
57
68
No MS (Memory Stick) Insert feature needed.
Control signal to light LED or control SD bus power.
SDCONN_WP
1K
1
2
5%
MF-LF
BI
30 97
BI
30 97
BI
30 97
BI
B
30 97
BI
30 97
BI
30 97
BI
30 97
IN
30
402
69
1/16W
30 97
BI
R3965
1.24K
ROM contains MAC address, PCIe config
info as well as code for Bonjour proxy.
Required for proper PHY operation.
(Required ROM size TBD)
=PP3V3_ENET_PHY
1%
1/16W
MF-LF
2 402
6
72 36 24 7
1
37 97
BI
THRM_PAD
PHY Non-Volatile Memory
C
36
PP3V3R1V8_ENET_LR_OUT_REG
BCM57765B0
PCIE_REFCLK_P
PCIE_REFCLK_N
ENET_RESET_L
BCM57765_SMB_CLK
BCM57765_SMB_DATA
36
C3930
=PP3V3R1V8_ENET_LR_OUT
PCIE_RXD_P
PCIE_RXD_N
IN
IN
2
SM
4.7UF
C3936
VDDC
PCIE_TXD_N
PCIE_TXD_P
OUT
61
35
36
32
29
51
45
39
13
16
SR_LX
SR_VFB
14
62
7
56
20
17
15
SR_VDDP
SR_VDD
AVDDL
(IPx)
SD_DETECT can only be used active low due to errata.
Must isolate from PCIe WAKE# if PHY
is powered-down in S3/S5. Standard
N-channel FET isolation suggested.
If PHY is always powered then alias
=ENET_WAKE_L to PCIE_WAKE_L.
B
VMAIN_PRSNT (IPD)
ENET_WAKE_R_L
2
10%
16V
X5R
402
2
33
28
PCIE_CLK100M_ENET_P
PCIE_CLK100M_ENET_N
IN
0.1uF
27
PCIE_ENET_R2D_P
PCIE_ENET_R2D_N
IN
96 16
C3956
5%
1/16W
MF-LF
402
WAKE#
58
PCIE_ENET_D2R_C_N
PCIE_ENET_D2R_C_P
96
2
0
VDDO
QFN-8X8
96
2
0.1UF
2
1
=ENET_WAKE_L
AVDDH
U3900
96
R3943
24
10%
16V
X7R-CERM
402
ENET_VMAIN_PRSNT
10%
16V
X5R
402
PCIE_ENET_R2D_C_N
L3930
1
CRITICAL
0.1UF
(IPU)
IN
2
Current
Limiting
Resistor
96
10%
16V
X5R
402
96 16
2
1
2
C3916
(IPD)
1
1
1
0.1uF
PCIE_ENET_D2R_P
PCIE_ENET_R2D_C_P
10%
6.3V
X5R-CERM
603
GPHY_PLLVDDL
5%
1/16W
MF-LF
402
0.1uF
IN
1
4.7UF
R3942
C3951
C3955
96 16
10%
16V
X7R-CERM
402
C3915
1
0.1UF
37
5%
1/16W
MF-LF
402
2
C3931
(IPU)
OUT
4.7K
2
2
(IPU)
96 16
2
PCIE_PLLVDDL
2
10%
16V
X5R
402
CRITICAL
PP1V2_ENET_PHY_GPHYPLL
1K
2
10%
6.3V
X5R-CERM
603
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.2V
10%
16V
X7R-CERM
402
XTALVDDH
=PP3V3_S0_ENETPHY
1
4.7UF
0.1UF
2
R3941
5%
1/16W
MF-LF
402
0.1uF
OUT
2
C3911
10%
16V
X7R-CERM
402
48
1
4.7K
1
0.1UF
BIASVDDH
R3940 1
C3910
42
5%
1/16W
MF-LF
402
C3950
2
C3925
FERR-600-OHM-0.5A
4.7K
PCIE_ENET_D2R_N
1
2
SM
PP3V3_S3_ENET_PHY_AVDDH
SM
96 16
1
0.1UF
10%
16V
X7R-CERM
402
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
1
L3925
1
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.2V
10%
16V
X7R-CERM
402
FERR-600-OHM-0.5A
7
CRITICAL
PP1V2_ENET_PHY_PCIEPLL
C3905
L3910
C
10%
6.3V
X5R-CERM
603
FERR-600-OHM-0.5A
0.1UF
1
C3920
PP3V3_S3_ENET_PHY_BIASVDDH
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
SM
D
2
SM
4.7UF
10%
16V
X7R-CERM
402
FERR-600-OHM-0.5A
2
1
2
C3921
2
L3905
1
1
1
BCM57765 supports both active-levels for WP.
SR_DISABLE must be pulled down to use
internal SR. IPD has a race condition.
C3990
0.1UF
VCC
U3990
2
AT45DB011D
10%
16V
X7R-CERM
402
SOIC-8S1
36
BCM57765_SCLK
2
36
BCM57765_CS_L
4
CS*
5
WP*
3
RESET*
OMIT
SI
1
BCM57765_MOSI
36
SO
SCK
8
BCM57765_MISO
36
SYNC_MASTER=K91_ERIC
ETHERNET PHY (CAESAR IV)
NOSTUFF
1
GND
R3990
1
DRAWING NUMBER
R3997
4.7K
Apple Inc.
4.7K
5%
1/16W
MF-LF
2 402
5%
1/16W
MF-LF
2 402
7
051-9585
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
NOTE: Pull-down on SO plus internal pull-ups on
other 3 SPI pins configures ENET for the
Atmel AT45DB011D (1Mbit) ROM. If a different
ROM is used then the straps must change.
NOTE: ENETM requires SI pull-down instead of SO.
8
SYNC_DATE=10/11/2010
PAGE TITLE
7
A
6
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
5
4
3
2
3.0.0
BRANCH
PAGE
39 OF 132
SHEET
36 OF 105
1
SIZE
D
A
8
7
6
5
4
3
2
1
Page Notes
Power aliases required by this page:
(NONE)
Signal aliases required by this page:
(NONE)
BOM options provided by this page:
(NONE)
D
D
Place one of 0.1uf cap close to each centertap pin of transformer
ENETCONN_CTAP
1
C4000
1
0.1UF
C4002
0.1UF
10%
2 16V
X5R
402-1
1
C4004
0.1UF
10%
2 16V
X5R
402-1
10%
2 16V
X5R
402-1
1
C4006
0.1UF
10%
2 16V
X5R
402-1
CRITICAL
97 36
BI
ENET_MDI_P & lt; 0 & gt;
1
97 36
BI
ENET_MDI_N & lt; 0 & gt;
T4000
SM
12
101
ENETCONN_P & lt; 0 & gt;
2
11
101
ENETCONN_N & lt; 0 & gt;
3
10
ENET_CTAP0
4
9
ENET_CTAP1
CRITICAL
J4000
RJ45-M97-3
TX
F-RT-TH
TLA-6T213HF
C
9
C
10
97 36
BI
ENET_MDI_N & lt; 1 & gt;
5
8
101
ENETCONN_N & lt; 1 & gt;
97 36
BI
ENET_MDI_P & lt; 1 & gt;
6
7
101
ENETCONN_P & lt; 1 & gt;
1
2
3
RX
4
5
CRITICAL
97 36
97 36
BI
ENET_MDI_N & lt; 2 & gt;
1
BI
ENET_MDI_P & lt; 2 & gt;
T4001
SM
2
6
7
12
101
ENETCONN_N & lt; 2 & gt;
8
11
101
ENETCONN_P & lt; 2 & gt;
11
12
3
10
ENET_CTAP2
4
9
ENET_CTAP3
ENET_MDI_N & lt; 3 & gt;
5
8
101
ENETCONN_N & lt; 3 & gt;
ENET_MDI_P & lt; 3 & gt;
6
7
101
ENETCONN_P & lt; 3 & gt;
TX
514-0636
TLA-6T213HF
97 36
97 36
BI
BI
RX
Transformers should be
mirrored on opposite
sides of the board
R40001 R40011
75
5%
1/16W
MF-LF
402 2
B
75
5%
1/16W
MF-LF
402 2
1
R4002
75
5%
1/16W
MF-LF
2 402
1
R4003
75
CRITICAL
5%
1/16W
MF-LF
2 402
1000PF
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
PLACE_NEAR=T4001.1:5mm
4
9
2 10
1
GND
D4001
RCLAMP0524P
SLP2510P8
CRITICAL
2
10%
2KV
CERM
1206
PLACE_NEAR=T4000.5:5mm
6
5
7
4
9
2 10
1
D4000
RCLAMP0524P
GND
7
1
NC
IO
NC
IO
NC
IO
NC
IO
5
NC
IO
NC
IO
NC
IO
NC
IO
6
B
C4008
ENET_BOB_SMITH_CAP
SLP2510P8
3
NOSTUFF
CRITICAL
3
NOSTUFF
A
SYNC_MASTER=K91_TRINHNI
SYNC_DATE=05/26/2010
PAGE TITLE
Ethernet Connector
DRAWING NUMBER
Apple Inc.
051-9585
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
3.0.0
BRANCH
PAGE
40 OF 132
SHEET
37 OF 105
1
A
8
7
6
5
4
3
2
1
=PP3V3_FW_FWPHY
7 38 39 40
7 mA I/O
138 mA
1
C4120
C4121
1
C4122
1
C4123
1
C4124
1UF
1UF
1UF
1UF
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
1
1UF
10%
6.3V
CERM
402
2
2
2
2
2
L4130
120-OHM-0.3A-EMI
D
114 mA FireWire PHY
C4130
1
PP3V3_FW_FWPHY_VDDA
1
C4131
1UF
1UF
2
10%
6.3V
CERM
402
C4132
10%
6.3V
CERM
402
1
2
1
2
L4110
R4100
39 7
=PP1V0_FW_FWPHY
1
0
5%
1/16W
MF-LF
402
135 mA
2
L4135
120-OHM-0.3A-EMI
1
PP1V0_FW_R
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.0V
2
120-OHM-0.3A-EMI
25 mA PCIe SerDes
PP1V0_FW_FWPHY_AVDD
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.0V
0402-LF
1
C4110
17 mA PCIe SerDes
C4111
1
1UF
2
C4135
1UF
10%
6.3V
CERM
402
10%
6.3V
CERM
402
C4100
1
C4136
1
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
1
2
0 mA VReg PWR
C4101
1
C4102
1
C4103
1
C4104
1
C4105
C4106
1
C4141
1UF
1UF
1UF
1UF
1UF
1UF
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
10%
6.3V
CERM
402
20%
10V
CERM
402
1
1
2
2
0.1UF
10%
6.3V
CERM
402
2
2
0402-LF
1UF
10%
6.3V
CERM
402
2
1UF
2
1
PP3V3_FW_FWPHY_VP25
1UF
10%
6.3V
CERM
402
2
110 mA Digital Core
1
D
2
0402-LF
1UF
10%
6.3V
CERM
402
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
2
2
2
2
2
C4140
1UF
10%
6.3V
CERM
402
C
C
40
40
IN
40
IN
97 40
BI
97 40
BI
97 40
BI
40
BI
40
BI
97 40
BI
97 40
BI
97 40
97 40
BI
BI
40
R4160 1
B
BI
40
BI
40
BI
2
E13
B8
A8
B5
A5
B3
A3
B9
A9
B6
A6
B4
A4
B7
C3
A2
FW643_R0
FW643_TPCPS
PLACE_NEAR=U4100.B10:2mm
A11
E12
FW_P0_TPBIAS
FW_P1_TPBIAS
FW_P2_TPBIAS
BI
40 39
200K
1%
1/16W
MF-LF
402
BI
40
=PPVP_FW_PHY_CPS
A13
F12
FW_P0_TPA_N
FW_P0_TPA_P
FW_P1_TPA_N
FW_P1_TPA_P
FW_P2_TPA_N
FW_P2_TPA_P
FW_P0_TPB_N
FW_P0_TPB_P
FW_P1_TPB_N
FW_P1_TPB_P
FW_P2_TPB_N
FW_P2_TPB_P
BI
97 40
40
=FW_PHY_DS0
=FW_PHY_DS1
=FW_PHY_DS2
IN
B13
B11
B10
VP
K12
L9
L6
L5
L10
D8
D6
D5
M2
L3
J1
A12
VDDH
VDD33
OMIT
CRITICAL
ATBUSB
ATBUSH
ATBUSN
DS0
DS1
DS2
L11
F1
VDD10
NC
NC
NC
G12
C1
C12
N3
N11
L1
K2
M12
H2
H12
E2
E10
B1
C13
A1
B12
PLACE_NEAR=U1800.AV34:2.54mm
C41701
VP25
0.1UF
PCIE_RXD0N
PCIE_RXD0P
PCIE_TXD0N
PCIE_TXD0P
U4100
FW643
N8
96
N7
96
N5
96
N6
96
BGA
REFCLKN
REFCLKP
PCI EXPRESS PHY
(IPD) NT-21
TPA0N
TPA0P
TPA1N
TPA1P
TPA2N
TPA2P
TPB0N
TPB0P
TPB1N
TPB1P
TPB2N
TPB2P
N9
N10
NT-4 (IPU) TCK
NT-3 (IPU) TDI
M1
NT-1 (IPU) TMS
M3
N1
WAKE*
REGCLT
VAUX_DETECT
VAUX_DISABLE
(OD) CLKREQN
FIXME!!! - TYPO IN SYMBOL REGCTL
POWER MANAGEMENT
NT-12 (IPD)
NT-13
R0
TPCPS
C2
D13
E1
D2
L2
K13
J13
OCR_CTL_V10
OCR_CTL_V12
NT-7
NT-6
CHIP RESET
SCL
SDA
PERST*
NT-5
6
=PP3V3_FW_FWPHY
7 38 39 40
6
6
R4165 1
=FW_PME_L
FW643_REGCTL
FW643_VAUX_DETECT
TP_FW643_VAUX_ENABLE
=FW_CLKREQ_L
H1
OUT
1
R4166
8 39
10K
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
2 402
6
OUT
F2
TP_FW643_SCIFCLK
TP_FW643_SCIFDAIN
TP_FW643_SCIFDOUT
TP_FW643_SCIFMC
39
1
B
R4164
6
6
6
6
M11
FW643_SCL
TP_FW643_SDA
N4
FW_RESET_L
N12
6
IN
1
39
R4163
10K
(Reserved)
2
K6
K10
L7
K9
K8
K7
K5
K4
J10
J9
J5
J4
H8
H10
H7
VREG_VSS
H6
H4
VSS
10%
6.3V
CERM-X5R
402
6
MISCELLANEOUS
G8
2
J12
NC
16 96
5%
1/16W
MF-LF
402
L12
C4162
0.33UF
2
H13
TP_FW643_OCR10_CTL
1
470K
5%
1/16W
MF-LF
402
D1
A10
G10
R4162 1
D12
G7
6
L13
G1
SERIAL EEPROM
CONTROLLER
G6
6
J2
SE (IPD)
SM (IPD)
MODE_A (IPD) NT-18
CE (IPD)
FW620* (IPU)
JASI_EN (IPD) NT-11
AVREG
VBUF
FW_RESET* (IPU) NT-8
G4
6
N13
F8
6
5%
50V
CERM
402
M13
F10
2
6
TP_FW643_SE
TP_FW643_SM
TP_FW643_MODE_A
TP_FW643_CE
TP_FW643_FW620_L
TP_FW643_JASI_EN
TP_FW643_AVREG
TP_FW643_VBUF
FW643_PU_RST_L
F7
2
1%
1/16W
MF-LF
402
6
F6
3
2
191
F4
4
1%
1/16W
MF-LF
402
6
R4170
OUT
NAND tree order.
E9
1
2.94K
G2
SCIFCLK
SCIFDAIN
NT-17 SCIFDOUT
NT-15 (IPD)
SCIFMC
NOTE: NT-xx notes show
E5
R4161 1
G13
PCIE_FW_D2R_P
X5R 402-1
FW643_LDO
NT-14 (IPD)
SCIF
NT-OUT
E4
SM-3.2X2.5MM
F13
NAND_TREE
REXT
XO
XI NT-9
D10
Y4150
1%
1/16W
MF-LF
402
24.576MHZ
2
22PF
NC
NC
2
16 96
5%
1/16W
MF-LF
2 402
D9
1
C4151
1
OUT
10K
D7
CRITICAL
5%
50V
CERM
402
1
FW_CLK24P576M_XO
L8
16 96
16 96
FW643_TRST_L
NT-10 (IPD)
IN
PLACE_NEAR=U1800.BJ36:2.54mm
10K
TPBIAS0
TPBIAS1
TPBIAS2
B2
2
412
K1
10% 16V
2
16 96
IN
TP_FW643_TCK
TP_FW643_TDI
TP_FW643_TDO
TP_FW643_TMS
NT-2 (IPU) TRST*
1394 PHY
N2
(IPU) TDO
TEST CONTROLLER
IN
PCIE_FW_D2R_N
X5R 402-1
0.1UF
PCIE_CLK100M_FW_N
PCIE_CLK100M_FW_P
M4
16 96
PLACE_NEAR=U1800.BG36:2.54mm
10% 16V
2
0.1UF
C41761
(IPD) NT-20
IN
PLACE_NEAR=U1800.AU34:2.54mm
PCIE_FW_R2D_C_P
X5R 402-1
C41751
(IPD) NT-19
D4
R4150
22PF
1
TP_FW643_NAND_TREE
FW643_REXT
FW_CLK24P576M_XO_R
FW_CLK24P576M_XI
2
10% 16V
0.1UF
PCIE_FW_R2D_N
PCIE_FW_R2D_P
PCIE_FW_D2R_C_N
PCIE_FW_D2R_C_P
PCIE_FW_R2D_C_N
X5R 402-1
C41711
VREG_PWR
NT-16 (IPD)
C4150
10% 16V
2
A
SYNC_MASTER=K18_MLB
SYNC_DATE=04/27/2010
PAGE TITLE
FireWire LLC/PHY (FW643)
DRAWING NUMBER
Apple Inc.
051-9585
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
3.0.0
BRANCH
PAGE
41 OF 132
SHEET
38 OF 105
1
A
8
Page Notes
D
Power aliases required
- =PPBUS_S5_FWPWRSW
- =PPBUS_FW_FET
- =PP3V3_FW_P3V3FWFET
- =PP3V3_FW_FET
- =PP3V3_FW_FWPHY
- =PP3V3_S0_FWLATEVG
- =PP3V3_S0_FWPWRCTL
- =PP1V05_S0_FWPWRCTL
- =PP1V05_FW_P1V0FWFET
- =PP1V0_FW_FET_R
- =PP1V0_FW_FWPHY
7
6
5
4
3
2
1
FireWire Port Power Switch
by this page:
(FW VP FET Input)
(FW VP FET Output)
(3.3V FET Input)
(3.3V FET Output)
(PHY 3.3V Power)
CRITICAL
Q4260
CRITICAL
FDC638P_G
F4260
SM
CRITICAL
D4260
1.1A-24V
6
7
=PPBUS_S5_FWPWRSW
Q4262 provides for fast-off of Q4260 in S0 (Late-VG detection)
5
4
2
PPBUS_FW_FWPWRSW_F
1
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.6V
=PPBUS_FW_FET
SBR3U30P1
PPBUS_FW_FWPWRSW_D
2
A
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.6V
MINISMDC110H24
7
K
PWRDI123
1
(5KPD Bias Rail)
(1.0V FET Input)
(1.0V FET Output)
(PHY 1.0V)
R4262
1
1
10K
4
2
2
FWPORT_FASTOFF_L_DIV
Signal aliases required by this page:
- =FW_CLKREQ_L
- =FW_PME_L
(SYM-VER2)
S
5
SOT-363
C4260
R4263
10%
25V
X5R
402
D
3
2
Q4262
1
CRITICAL
D
10
5%
1/16W
MF-LF
402
1
0.1UF
5%
1/16W
MF-LF
402
FWPORT_PWREN_L_DIV
BSS8402DW
G
BOM options provided by this page:
(NONE)
R4260
300K
5%
1/16W
MF-LF
402
3
2
FWPORT_FASTOFF_L
1
CRITICAL
D
Q4262
=PP3V3_S0_FWLATEVG
2
BSS8402DW
G
2
Supervisor & CLKREQ# Isolation
5%
1/16W
MF-LF
402
40 39 38 7
7
FWPORT_PWREN_L
SOT-363
S
(SYM-VER1)
CRITICAL
D
1
3
C4261
SSM3K15FV
10%
25V
X5R
402
G
S
10%
25V
X5R
402
24
2
IN
=FW_RESET_L
1
CRITICAL
U4290
2
R4290
100K
VDD
SLG4AP016V
2
5%
1/16W
MF-LF
402
=PP1V0_FW_FWPHY
TDFN
2
2
FWPORT_PWR_EN
IN
1
0.1UF
1
0.1UF
SOD-VESM-HF
1
C4290
NO STUFF
Q4261
40
=PP3V3_FW_FWPHY
=PP3V3_S0_FWPWRCTL
1
40 7
R4261
470K
6
+ SENSE
- 0.7V
10K
1
C
5%
1/16W
MF-LF
402
4
7 38
2
RESET*
R4283
DLY
FW_RESET_R_L
3
MR*
FW_RESET_L
OUT
IN
C
38
38
DLY = 60 ms +/- 20%
16
IN
OUT
FW_PWR_EN
FW_CLKREQ_L
6
8
EN
OUT
IN
(OD)
Pull-up provided by another page.
5
GND
7
=FW_CLKREQ_L
FW_CLKREQ_PHY_L
7
MAKE_BASE=TRUE
THRM
PAD
9
39 24
=PP1V05_S0_FWPWRCTL
FireWire Port 5K Pull-Down Detect
R4275 1
All FireWire devices require 5K pull-down on TPB pair.
Host can detect as load on TPBIAS signal.
Current source only active when FW_PWR_EN is low.
1K
5%
1/16W
MF-LF
402 2
3.3V FW Switch
FW_PWR_EN_L
U4201
D
330K
Q4275
DMB53D0UV
IN
FW_PWR_EN
2
7
5%
1/16W
MF-LF
402 2
3
B2
1
B
3
6
5
BC847CDXV6TXG
SOT563
10%
16V
X5R
402
BC847CDXV6TXG
SOT563
4
C2
10%
6.3V
CERM
402
GND
4
Part
2
2
TPS22924C
Type
Load Switch
R(on)
1
18 mOhm Typ
50 mOhm Max
1.0V FW Switch
U4202
R4273 1
1K
12K
5%
1/16W
MF-LF
402 2
7
TPS22924
=PP1V05_FW_P1V0FWFET
5%
1/16W
MF-LF
402 2
CSP
A2
B2
VIN
PP1V05_FW_FET
A1
VOUT
B1
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
CRITICAL
PLACE_NEAR=C4360.1:2 mm
C4202
FW_P1_TPBIAS
1
10%
6.3V
CERM
402
FireWire PHY WAKE# Support
C2
1
ON
GND
1UF
2
LSI FireWire PHY requires 1.0V.
To avoid an extra power supply,
1.05V is used with a series R
to reduce voltage.
R4202
0.549
2
1%
1/16W
MF
402
=PP1V0_FW_FET_R
When PHY is powered, FW_5KPD_DET_L acts as legacy PME# signal.
40 39 38 7
=PP3V3_FW_FWPHY
1
1) 5K Pull-down Detect when FW_PWR_EN is low.
2) FW643 WAKE# (PME#) when PHY is powered.
R4276
10K
100K
FW_PME_L
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
Pull-up provided on another page.
CRITICAL
2
2
3
6
D
=FW_PME_L
8
FW643_WAKE_L
2
C4276
8 19
DMB53D0UV
NO STUFF
A
OUT
Q4276
5
FW_WAKE
IN
SOT-563
1
4
SYNC_MASTER=K91_MLB
0.1UF
10%
16V
X5R
402
FireWire Port & PHY Power
DRAWING NUMBER
G
MAKE_BASE=TRUE
Apple Inc.
Q4276
S
DMB53D0UV
NOTICE OF PROPRIETARY PROPERTY:
SOT-563
6
051-9585
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
5
4
3
2
SIZE
D
REVISION
R
1
7
SYNC_DATE=06/17/2011
PAGE TITLE
2
CRITICAL
8
7
Dual-purpose output:
R4277 1
38 8
B
Max Output: 2A
FWDET_EMIT
R4272 1
IN
U4201 & U4202
ON
1
FW_P1_TPBIAS_R
40 38
7
Max Current = 1.7A (85C)
B1
0.1UF
Q4270
2
FWDET_MIRROR
C4270
CRITICAL
1
1UF
SOT-563
Q4270
=PP3V3_FW_FET
A1
VOUT
CRITICAL
C4201
DMB53D0UV
CRITICAL
VIN
CRITICAL
Q4275
5
FW_5KPD_DET_RC
CSP
A2
MAKE_BASE=TRUE
G
S
TPS22924
=PP3V3_FW_P3V3FWFET
FW_5KPD_DET_L
56K
5%
1/16W
MF-LF
2 402
SOT-563
39 24
R4271 1
R4270
C1
CRITICAL
C1
1
6
3.0.0
BRANCH
PAGE
42 OF 132
SHEET
39 OF 105
1
A
8
Page Notes
7
6
4
FW643 TPCPS Leakage Protection
Power aliases required by this page:
- =PPVP_FW_PORT1
- =PPVP_FW_PHY_CPS_FET (From Port)
- =PPVP_FW_PHY_CPS
(To PHY)
- =PP3V3_FW_FWPHY
- =PP3V3_S0_FWLATEVG
3
2
Unused FireWire Ports
FW643 has internal leakage path from TPCPS pin to VDD33.
FET blocks current to TPCPS until VDD33 is powered.
Configures PHY for:
- Port " 1 " Bilingual (1394B)
CRITICAL
SOT-363
BSS8402DW
38
470K
5%
1/16W
MF-LF
402
D
3
S
FW_P0_TPA_P
BI
FW_P0_TPA_N
97 38
BI
FW_P0_TPB_P
97 38
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=12.6V
MAKE_BASE=TRUE
=PPVP_FW_PHY_CPS
G
R4311
1
FW_P0_TPBIAS
BI
BI
FW_P0_TPB_N
IN
FW_P2_TPBIAS
BI
FW_P2_TPA_P
BI
FW_P2_TPA_N
BI
FW_P2_TPB_P
97 38
PPVP_FW_CPS
From Port
IN
97 38
=PPVP_FW_PHY_CPS_FET
4
7
Q4300
(SYM-VER2)
40 39 38 7
Signal aliases required by this page:
- =FW_PHY_DS0
- =FW_PHY_DS1
- =FW_PHY_DS2
NOTE: This page is expected to contain
the necessary aliases to map the
FireWire TPA/TPB pairs to their
appropriate connectors and/or to
properly terminate unused signals.
38
=PP3V3_FW_FWPHY
NC_FW0_TPBIAS
MAKE_BASE=TRUE
R4382 1
NO_TEST=TRUE
NC_FW0_TPAP
NC_FW0_TPAN
NO_TEST=TRUE
NC_FW0_TPBP
10K
1%
1/16W
MF-LF
2 402
6
MAKE_BASE=TRUE
R4380
1%
1/16W
MF-LF
402 2
NO_TEST=TRUE
MAKE_BASE=TRUE
1
10K
6
MAKE_BASE=TRUE
FWPHY_DS0
NO_TEST=TRUE
=FW_PHY_DS0
MAKE_BASE=TRUE
NC_FW0_TPBN
6
MAKE_BASE=TRUE
FWPHY_DS1
NO_TEST=TRUE
=FW_PHY_DS1
MAKE_BASE=TRUE
To FW643
38
38
2
BOM options provided by this page:
(NONE)
1
FireWire PHY Config Straps
Disabled per LSI instructions
(All unused port signals TP/NC)
5
D
5
CPS_EN_L_DIV
1394b implementation based on Apple
FireWire Design Guide (FWDG 0.6, 5/14/03)
38
R4312
38
1
330K
38
5%
1/16W
MF-LF
402 2
BI
NC_FW2_TPBIAS
MAKE_BASE=TRUE
NC_FW2_TPAP
MAKE_BASE=TRUE
6
NC_FW2_TPAN
1
MAKE_BASE=TRUE
6
NO_TEST=TRUE
NC_FW2_TPBN
MAKE_BASE=TRUE
38
OUT
38
OUT
38
R4381
10K
6
NO_TEST=TRUE
NC_FW2_TPBP
FW_P2_TPB_N
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
=FW_PHY_DS2
FWPHY_DS2
6
NO_TEST=TRUE
D
OUT
2
1%
1/16W
MF-LF
402
6
NO_TEST=TRUE
CPS_EN_L
6
CRITICAL
D
40 39 38 7
Q4300
=PP3V3_FW_FWPHY
2
BSS8402DW
G
S
SOT-363
(SYM-VER1)
1
C
C
Cable Power
39 38
IN
7
CRITICAL
=PPVP_FW_PORT1
FERR-250-OHM
Note: Trace PPVP_FW_PORT1 must handle up to 5A
1
Termination
Place close to FireWire PHY
PPVP_FW_PORT1_F
L4310
2
FW_P1_TPBIAS
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=33V
SM
1
B
C4314
B
0.01UF
1
C4360
2
0.33UF
2
10%
6.3V
CERM-X5R
402
10%
50V
X7R
402
(FW_PORT1_TPB_N)
(FW_PORT1_TPB_P)
" Snapback " & " Late VG " Protection
SIGNAL_MODEL=EMPTY
SIGNAL_MODEL=EMPTY
R4360
R4361
56.2
BI
BILINGUAL
CRITICAL
PLACE_NEAR=U4350.1:2 mm
1%
1/16W
MF-LF
402 2
FW_P1_TPA_P
C4350
10%
16V
X5R
402
FW_PORT1_TPA_P
MAKE_BASE=TRUE
FW_P1_TPA_N
J4310
1
0.1UF
FW_PORT1_TPA_N
TP_FWLATEVG_VCLMP
BI
FW_P1_TPB_P
FW_PORT1_TPB_P
97 38
BI
FW_P1_TPB_N
FW_PORT1_TPB_N
39
MAKE_BASE=TRUE
SIGNAL_MODEL=EMPTY
SIGNAL_MODEL=EMPTY
1
R4362
R4363
56.2
U4350
2
3
LLP
D1+
D1-
VCLMP
2
1%
1/16W
MF-LF
402
R4350 1
100K
1
6
D2-
5
GND
2
7
NC
C4364
220pF
2
5%
25V
CERM
402
4
3
VP
SC/NC
NC
VG
TPA-
VG
TPA-
5
PLACE_NEAR=J4310.5:2 mm
10%
50V
X7R
603-1
(FW_PORT1_TPA_N)
1
4.99K
(FW_PORT1_TPA_P)
TPA & lt; R & gt;
TPA+
TPA(R)
INPUT
TPA+
11
1
1
R4319
1M
6
5
CHASSIS
GND
12
13
SYNC_MASTER=T27_REF
2
4
5%
1/16W
MF-LF
402
SYNC_DATE=06/10/2010
PAGE TITLE
514S0605
1%
1/16W
MF-LF
402 2
PLACE_NOTE=J4310.5:2 mm
7
OUTPUT
TPB+
10
2
2
8
TPB & lt; R & gt;
VP
6
(FW_PORT1_TPA_P)
5%
1/16W
MF-LF
402 2
C4319
R4364
TPB-
TPB+
7
(GND)
(FW_PORT1_TPA_N)
FW_PORT1_AREF
0.1uF
1
TPB(R)
8
FW_PORT1_TPB_C
A
TPB-
9
FWPWR_EN
CRITICAL
MAKE_BASE=TRUE
8
D2+
1
(FW_PORT1_TPB_N)
(FW_PORT1_BREF)
(FW_PORT1_TPB_P)
TPD4S1394
4
FWPORT_PWR_EN
56.2
1%
1/16W
MF-LF
402
OUT
F-RT-TH
VCC
MAKE_BASE=TRUE
97 38
1394B-M97
2
97 38
BI
PORT 1
=PP3V3_S0_FWLATEVG
56.2
1%
1/16W
MF-LF
2 402
97 38
39 7
1
1
1
FireWire Connector
AREF needs to be isolated from all
local grounds per 1394b spec
When a bilingual device is connected to a
beta-only device, there is no DC path
between them (to avoid ground offset issue)
BREF should be hard-connected to logic
ground for speed signaling and connection
3
DRAWING NUMBER
Apple Inc.
051-9585
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
2
SIZE
D
REVISION
3.0.0
BRANCH
PAGE
43 OF 132
SHEET
40 OF 105
1
A
8
7
6
5
4
Q4590
ODD Power Control
=PP5V_S3_ODD
DFN2563-6
D
4
G
3
J4500
C4596
=PP3V3_S0_ODD
D
Q4596
1
100K
2
1
3
14
16
95 6
516S0616
=PP3V3_S0_ODD
3
95 6
G
S
45 6
=PP3V3_S0_SMC
1
2
1
2
100K
5%
1/16W
MF-LF
2 402
=PP5V_S0_HDD
=PP3V3_S0_HDD
0.1UF
20%
10V
CERM
402
1
OUT
OUT
101 103
7
R4537
SSD_OOBR2D_L
R4538
1%
1
NOSTUFF
C4538
L4539
SSD_OOBD2R_L
6
1/16W
1
MF-LF
2
SSD_OOBD2R_FTL_L
OUT
0402
ADD0
6
R4531
SYS_LED_ANODE_R
1
5%
4.7
C4531
PLACE_NEAR=J4501.10:10MM
SYS_LED_ANODE
2
1/16W
MF-LF
L
R4584
IN
402
H
0x98/0x99
NO STUFF
R45131
L
H
0xB8/0xB9
6 46
41 7
=PP1V5_S0_RDRVR
OUT
41 7
2
R4536
3
4
68.1
5
6
C4518 & C4517 Placement Note:
0.01UF
20%
16V
2 CERM
402
It is critical that these two should be near
to U1800 pin AM1 and AM3.
B
PLACE_NEAR=U4510.6:2MM
PLACE_NEAR=U4510.16:2MM
SATA_HDD_D2R_C_P
16
GND_VOID=TRUE
2
1%
C4536
1
2
1/20W
MF
PLACE_NEAR=U1800.AM1:5MM
GND_VOID=TRUE
201
GND_VOID=TRUE
95
SATA_HDD_D2R_RC_P
C4516
2
GND_VOID=TRUE
10%
1
16V
SATA_HDD_D2R_RDRIN_P
95
95
C4518
SATA_HDD_D2R_RDROUT_P
1
2
5.0PF
95 6
SATA_HDD_D2R_C_N
C4535
5.0PF
R4535
GND_VOID
17
18
GND_VOID
GND_VOID
19
20
1
0201
+/-0.1PF
2
C0G
0.01UF
25V
GND_VOID=TRUE
+/-0.1PF
1
C0G
95
SATA_HDD_D2R_RC_N
C4515
2
16V
0.01UF
402
GND_VOID=TRUE
10%
1
0.01UF
25V
CERM
SATA_HDD_D2R_RDRIN_N
95
CERM
95
22
1%
1/20W
MF
10%
1
SATA_HDD_D2R_P
OUT
16 95
SATA_HDD_D2R_N
OUT
16 95
SATA_HDD_R2D_C_N
IN
16 95
SATA_HDD_R2D_C_P
16V
CERM
IN
16 95
402
16V
CERM
402
2
0.01UF
GND_VOID=TRUE
2
68.1
C4517
SATA_HDD_D2R_RDROUT_N
402
GND_VOID
21
0201
10%
PLACE_NEAR=U1800.AM3:5MM
GND_VOID=TRUE
16
14
1
6
10%
16V
X7R-CERM
402
12
13
15
2
C4519
1
10
11
0.1UF
95 6
8
9
C4532
201
VDD
U4510
R4534
516S0687
1
2
1%
41.2
PS8521A
GND_VOID=TRUE
1/20W
MF
201
95 6
SATA_HDD_R2D_N
C4534
1
2
GND_VOID=TRUE
5%
15PF
25V
NPO
PLACE_NEAR=U4510.12:5MM
GND_VOID=TRUE
TQFN
1
CRITICAL
95
SATA_HDD_R2D_RC_N
C4511
0.01UF
201
2
10%
1
GND_VOID=TRUE
16V
SATA_HDD_R2D_RDROUT_N
95
CERM
2
A_INP
A_INN
GND_VOID
GND_VOID
GND_VOID
GND_VOID
GND_VOID
GND_VOID
GND_VOID
GND_VOID
A_OUTP
A_OUTN
15
B_INN
B_INP
12
14
95
C4513
SATA_HDD_R2D_RDRIN_N
C4533
1
2
GND_VOID=TRUE
5%
15PF
R4533
41.2
A
1
2
25V
NPO
95
5
IN
SATARDRVR_EN
7
EN
41
IN
SATARDRVR_I2C_ADDR0
8
B_PRE0/I2C_ADDR0
A_PRE1/SCL_CTL 19
=SATARDRVR_I2C_SCL
IN
41
SATA_HDD_R2D_P
B_OUTN
B_OUTP
23 16
95 6
IN
SATARDRVR_I2C_ADDR1
9
APRE0/I2C_ADDR1
B_PRE1/SDA_CTL 17
=SATARDRVR_I2C_SDA
BI
SATA_HDD_R2D_RC_P
C4510
1
0.01UF
201
2
GND_VOID=TRUE
10%
16V
SATA_HDD_R2D_RDROUT_P
95
CERM
1
2
0.01UF
402
4
11
95
C4512
SATA_HDD_R2D_RDRIN_P
10%
1
REXT 20
SATARDRVR_REXT
1/20W
MF
201
SATARDRVR_I2C_EN_L
10
18
TEST
16V
CERM
402
48
R4512
2
SATA Redriver/Conn, IR, SIL
1%
1/16W
MF-LF
402
DRAWING NUMBER
Apple Inc.
0
2
5%
1/16W
MF-LF
402
6
5
051-9585
R
CRITICAL
NOTICE OF PROPRIETARY PROPERTY:
4
3
2
SIZE
D
REVISION
3.0.0
338S0907
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
7
SYNC_DATE=11/17/2011
PAGE TITLE
3.74K
21
3
13
R4511
10%
SYNC_MASTER=J31_YONAS
1
GND THRM
PAD
1
402
48
I2C_EN*
SATARDRVR_TEST
VALUE: 3.0 DB
CERM
PLACE_NEAR=U4510.11:5MM
GND_VOID=TRUE
GND_VOID=TRUE
1%
16V
2
0.01UF
402
R2D Passive DeEmphasis
8
41
NOSTUFF
F-ST-SM
1
7
1
C4514
20%
2 10V
CERM
402
5%
1/16W
MF-LF
402 2
VALUE: 4.5 DB
41
=PP1V5_S0_RDRVR
0.1UF
D2R Passive DeEmphasis
J4501
54722-0224
PP5V_S3_IR_R
5%
1/16W
MF-LF
402 2
SATARDRVR_I2C_ADDR0
SATARDRVR_I2C_ADDR1
6 44
R4532
6
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=5V
4.7K
5%
1/16W
MF-LF
402 2
0xB6/0xB7
H
R45151
4.7K
4.7K
5%
1/16W
MF-LF
2 402
46
=PP1V5_S0_RDRVR
1
IR_RX_OUT
0
OUT
0.1UF
20%
10V
CERM
402
0.001UF
7 44
SMC_SSD_OOBD2R_L
C4584
2
41
1
B
1
2
5%
1/16W
MF-LF
402
GND
2
1
0
1
SMC_SSD_OOBD2R_R_L
0x96/0x97
R45101
1
1
SSD_OOBD2R_R_L
41 7
10%
50V
CERM 2
402
=PP5V_S3_IR
SC70-5
4
C
R4586
LMV331
46
H
20%
10V
X5R-CERM
1206
3
Address (R/W)
L
IN
402
FERR-220-OHM
100UF
1K
5%
1/16W
MF-LF
2 402
R4585
Write:0xB6 Read:0xB7
SMC_SSD_OOBR2D_L
2
0.1UF
20%
10V
CERM
402
U4580
5
100K
5%
1/16W
MF-LF
2 402
L
1
2
Internally PD ~150K
5%
1/16W
MF-LF
2 402
453
3.3K
SATA Redriver
ADDR1
6
1
SSD_OOBD2R_FTL_L
5%
1/16W
MF-LF
402
PLACE_NEAR=J4501.9:10MM
2
IN
101 103
100K
PLACE_NEAR=L4500.2:2MM
49.9K
1%
1/16W
MF-LF
402
R4582
7
41
ISNS_HDD_P
ISNS_HDD_N
C4502
1
2
4
20%
10V
CERM
402
PLACE_NEAR=L4500.1:2MM
20%
10V
X5R-CERM
1206
2
2
1
3
0.1UF
R4583
VCC+
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.4MM
VOLTAGE=5V
1
2
1
SSD_OOB1V0REF
PP5V_S0_HDD_R
C4580
=PP1V5_S0_RDRVR
1%
1W
MF-1
0612
CRITICAL
PLACE_NEAR=J4501.9:3MM
100UF
16 95
OOBR2D was TEMP_CTL, from SMC, to SSD
0.001
0603
C4537
OUT
402
OOBD2R was OOB_TEMP, from SSD, to SMC
41 7
FERR-70-OHM-4A
1
1
Notes:
SMC_ODD_DETECT
OUT
R4599
C4501
SATA_ODD_D2R_P
16 95
SATA OOB Comparator
4
L4500
2
2 GND_VOID=TRUE
10% 16V
CERM
OUT
402
33K
5%
1/16W
MF-LF
402 2
CRITICAL
NOSTUFF
SATA_ODD_D2R_N
R4590
R4581
1
C4525
SATA_ODD_D2R_C_P
1
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.4MM
VOLTAGE=5V
2 GND_VOID=TRUE
10% 16V
CERM
0.01UF
SATA HDD Connector (Gen3)
PP5V_S0_HDD_FLT
1
1
7
6
C4526
SATA_ODD_D2R_C_N
0.01UF
Note: Indicates disc presence.
C
16 95
CRITICAL
ODD_PWR_EN_L
IN
IN
402
12
1
SOT563
19
16 95
10
15
SSM6N37FEAPE
5
SATA_ODD_R2D_C_N
IN
402
D
9
41 7
D
SATA_ODD_R2D_N
0.01UF
13
S
2 GND_VOID=TRUE
10% 16V
CERM
8
ODD_PWR_EN
Q4596
95 6
11
G
1
C4520
6
7
SOT563
2
SATA_ODD_R2D_C_P
4
5
100K
5%
1/16W
MF-LF
402 2
2 GND_VOID=TRUE
10% 16V
CERM
2
10%
16V
CERM
402
SSM6N37FEAPE
R45971
1
2
1
ODD_PWR_SS
5%
1/16W
MF-LF
402
6
54722-0164
F-ST-SM
0.01UF
R4595
ODD_PWR_EN_LS5V_L
C4521
SATA_ODD_R2D_P
0.01UF
2
ensure the drive is unpowered in S3/S5.
41 7
95 6
10%
10V
CERM 2
402
5%
1/16W
MF-LF
402
PP5V_SW_ODD
0.068UF
100K
Note: 3.3V must be S0 if 5V is S3 or S5 to
1
1
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.4MM
VOLTAGE=5V
1
C4595
R4596
S
2
6
1
2
SATA ODD Connector
CRITICAL
DMP2018LFK
7
D
3
BRANCH
PAGE
45 OF 132
SHEET
41 OF 105
1
A
8
7
6
5
4
3
2
1
D
USB Port Power Switch
D
USB Port A (Front Port)
CRITICAL
CRITICAL
U4600
L4605
TPS2561DR
FERR-120-OHM-3A
SON
2
=PP5V_S3_USB
3
23
OUT
23
OUT
10
USB_EXTB_OC_L
USB_EXTA_OC_L
6
4
74
5
=USB_PWR_EN
C4690
1
2
C4691
2
10UF
20%
6.3V
X5R
603
1
ILIM
FAULT1*
FAULT2*
EN1
EN2
GND
C4696
0.1UF
OUT1
OUT2
9
PP5V_S3_USB_A_ILIM
7
USB_ILIM
PP5V_S3_USB_A_F
2
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V
0603
C4605
PP5V_S3_USB_B_ILIM
43
1
0.01UF
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V
20%
16V
CERM
402
CRITICAL
2
CRITICAL
J4600
L4600
90-OHM-100MA
DLP11S
USB-3.0-J30
F-RT-TH
SYM_VER-1
R4600 1
23.2K
1%
1/16W
MF-LF
402
220UF-35MOHM
20%
10V
CERM
402
1
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V
8
THRM
PAD
1
CRITICAL
1
IN_0
IN_1
11
7
20%
2 6.3V
POLY-TANT
CASE-B2-SM1
C4695
1
10UF
2
20%
6.3V
X5R
603
C4617
95
1
4
USB_EXTA_MUXED_N
3
10UF
20%
6.3V
X5R
603
2
95
95
2
USB_EXTA_MUXED_P
1
2
95
Current limit per port (R4600): 2.18A min / 2.63A max
USB_EXTA_MUXED_F_N
USB_EXTA_MUXED_F_P
95 6
NC
IO
NC
IO
2 5 3 4
6 VBUS
95 6
95 6
1 GND
1
2
3
4
5
6
7
8
9
95 6
USB3_EXTA_RX_F_N
USB3_EXTA_RX_F_P
USB3_EXTA_TX_F_N
USB3_EXTA_TX_F_P
D4600
C
10
RCLAMP0582N
VBUS
DD+
GND
STDA_SSRXSTDA_SSRX+
GND_DRAIN
STDA_SSTXSTDA_SSTX+
11
SLP1210N6
CRITICAL
C
12
13
14
SHIELD
15
16
GND_VOID=TRUE
CRITICAL
17
18
L4610
80OHM-25%-100MA
0504
L2
Mojo SMC Debug Mux
95 18 6
OUT
95 18 6
USB3_EXTA_RX_N
OUT
3
4
1
USB3_EXTA_RX_P
2
L1
7
=PP3V42_G3H_SMCUSBMUX
MOJO:YES
1
MOJO:YES
1
SMC_DEBUGPRT_RX_L
SMC_DEBUGPRT_TX_L
5
M+
4
M-
Y+
1
Y-
U4650
2
PI3USB102ZLE
BI
95 18
BI
USB_EXTA_P
USB_EXTA_N
B
6
8
D+
D-
GND_VOID=TRUE
CRITICAL
TQFN
CRITICAL
MOJO:YES
OE*
L4620
SEL
SMC_DEBUGPRT_EN_L
10
3
GND
SIGNAL_MODEL=MOJO_MUX
45
SEL=0 Choose SMC
SEL=1 Choose USB
C4620
L2
0.1UF
IN
USB3_EXTA_TX_N
1
2
95 18 6
MOJO:NO
IN
95 6
USB3_EXTA_TX_C_N
4
95 6
USB3_EXTA_TX_C_P
1
3
C4621
10% 6.3V
X5R 201
USB3_EXTA_TX_P
0.1UF
1
2
2
L1
R4651
10% 6.3V
X5R 201
0
GND_VOID=TRUE
2
5%
1/16W
MF-LF
402
0504
GND_VOID=TRUE
95 18 6
1
B
80OHM-25%-100MA
IN
1
95 18
7
5
IN
OUT
2
4
46 45
46 45
5%
1/16W
MF-LF
2 402
VCC
2
0.1UF
20%
10V
CERM
402
R4650
10K
9
C4650
MOJO:NO
R4652
0
CRITICAL
2
5%
1/16W
MF-LF
402
PGTSLP91-XSON-COMBO
A
NC
6
7
8
9
ESD3V3U4ULC-IP4292CZ10
GND
D4610
3
1
SYNC_MASTER=J31_LINDA
SYNC_DATE=09/21/2011
PAGE TITLE
External A USB3 Connector
DRAWING NUMBER
Apple Inc.
051-9585
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
3.0.0
BRANCH
PAGE
46 OF 132
SHEET
42 OF 105
1
A
8
7
6
5
4
3
2
1
D
USB Port B (Back Port)
D
CRITICAL
L4705
FERR-120-OHM-3A
42
1
PP5V_S3_USB_B_ILIM
2
PP5V_S3_USB_B_F
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V
0603
C4705
1
0.01UF
20%
16V
CERM
402
CRITICAL
2
CRITICAL
J4700
L4700
90-OHM-100MA
DLP11S
USB-3.0-J30
F-RT-TH
SYM_VER-1
95 25
USB_EXTB_MUX_N
BI
4
3
95
95 25
1
USB_EXTB_MUX_P
BI
2
95
NC
IO
NC
IO
2 5 3 4
6 VBUS
95 6
95 6
95 6
1 GND
95 6
USB_EXTB_F_N
USB_EXTB_F_P
USB3_EXTB_RX_F_N
USB3_EXTB_RX_F_P
USB3_EXTB_TX_F_N
USB3_EXTB_TX_F_P
D4700
VBUS
DD+
GND
STDA_SSRXSTDA_SSRX+
GND_DRAIN
STDA_SSTXSTDA_SSTX+
10
11
RCLAMP0582N
C
1
2
3
4
5
6
7
8
9
SLP1210N6
CRITICAL
C
12
13
14
15
SHIELD
16
17
GND_VOID=TRUE
CRITICAL
18
L4710
80OHM-25%-100MA
0504
L2
95 18 6
OUT
USB3_EXTB_RX_N
4
OUT
USB3_EXTB_RX_P
1
95 18 6
3
2
L1
GND_VOID=TRUE
CRITICAL
B
B
L4720
80OHM-25%-100MA
0504
GND_VOID=TRUE
C4720
L2
0.1UF
95 18 6
IN
USB3_EXTB_TX_N
1
2
IN
USB3_EXTB_TX_C_N
4
95 6
USB3_EXTB_TX_C_P
1
3
C4721
10% 6.3V
X5R 201
95 18 6
95 6
USB3_EXTB_TX_P
0.1UF
1
2
2
L1
5
1
GND_VOID=TRUE
4
6.3V
201
2
10%
X5R
CRITICAL
NC
6
7
8
9
PGTSLP91-XSON-COMBO
3
ESD3V3U4ULC-IP4292CZ10
GND
D4710
NOTE: Swapped pin4 and 5, pin6 and 7 for layout.
A
SYNC_MASTER=J30_MLB
SYNC_DATE=08/04/2011
PAGE TITLE
External B USB3 Connector
DRAWING NUMBER
Apple Inc.
051-9585
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
3.0.0
BRANCH
PAGE
47 OF 132
SHEET
43 OF 105
1
A
8
7
6
5
4
3
2
1
IR SUPPORT
D
41 7
D
=PP5V_S3_IR
1
C4801
0.1UF
10%
16V
X7R-CERM
402
14
2
VCC
U4800
CY7C63803-LQXC
QFN
95 8
BI
BI
DIFFERENTIAL_PAIR=USB2_TPAD
DIFFERENTIAL_PAIR=USB2_TPAD
USB_IR_P
USB_IR_N
12
IR_VREF_FILTER
15
1
13
NC
NC
NC
NC
C4803
1UF
2
10%
10V
X5R
402-1
NC
NC
NC
NC
NC
NC
NC
NC
17
18
19
8
P0.0
P0.1
INT0/P0.2
INT1/P0.3
INT2/P0.4
TIO0/P0.5
TIO1/P0.6
7
6
5
4
3
2
1
NC
NC
NC
NC
NC
45
R4800
100
IR_RX_OUT_RC
1
1
P/N 338S0633
IR_RX_OUT
IN
6 41
C4804
0.001UF
20
21
2
5%
1/16W
MF-LF
402
NC
CRITICAL
OMIT
9
10
2
NC
10%
50V
CERM
402
22
C
23
24
THRML
PAD
25
C
16
P1.0/D+
P1.1/DP1.2/VREG
P1.3/SSEL
P1.4/SCLK
P1.5/SMOSI
P1.6/SMISO
VSS
11
95 8
B
B
A
SYNC_MASTER=K18_MLB
SYNC_DATE=04/27/2010
PAGE TITLE
Front Flex Support
DRAWING NUMBER
Apple Inc.
051-9585
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
3.0.0
BRANCH
PAGE
48 OF 132
SHEET
44 OF 105
1
A
8
7
6
5
4
3
2
1
D
D
U4900
LM4FSXAH5BB
96 89 47 16 6
BI
96 89 47 16 6
BI
96 89 47 16 6
96 89 47 16 6
BI
BI
96 24
IN
96 89 47 16 6
IN
24
IN
47 16 6
BI
47 17 6
OUT
47 17 6
IN
19
OUT
46
OUT
99 48
99 48
BI
BI
99 48
BI
99 48
BI
99 48 6
BI
99 48 6
BI
99 48
C
99 48
BI
BI
46
BI
46
BI
99 48 6
BI
99 48 6
BI
52
OUT
52
IN
52
OUT
52
IN
46
OUT
46
OUT
54
OUT
46
OUT
46
64
46
41 6
BI
IN
IN
IN
46
BI
46
OUT
64 46 6
46
IN
46
B
IN
IN
46
74 46
IN
OUT
LPC_AD & lt; 0 & gt;
LPC_AD & lt; 1 & gt;
LPC_AD & lt; 2 & gt;
LPC_AD & lt; 3 & gt;
LPC_CLK33M_SMC
LPC_FRAME_L
SMC_LRESET_L
LPC_SERIRQ
PM_CLKRUN_L
LPC_PWRDWN_L
SMC_RUNTIME_SCI_L
SMC_WAKE_SCI_L
SMBUS_SMC_0_S0_SCL
SMBUS_SMC_0_S0_SDA
SMBUS_SMC_1_S0_SCL
SMBUS_SMC_1_S0_SDA
SMBUS_SMC_2_S3_SCL
SMBUS_SMC_2_S3_SDA
SMBUS_SMC_3_SCL
SMBUS_SMC_3_SDA
SMBUS_SMC_4_ASF_SCL
SMBUS_SMC_4_ASF_SDA
SMBUS_SMC_5_G3_SCL
SMBUS_SMC_5_G3_SDA
SMC_FAN_0_CTL
SMC_FAN_0_TACH
SMC_FAN_1_CTL
SMC_FAN_1_TACH
SMC_MPM5_LED_PWR
SMC_MPM5_LED_CHG
SMC_SYS_KBDLED
SMC_T25_EN_L
SYS_TDM_ONEWIRE
SYS_ONEWIRE
HISIDE_ISENSE_OC
SMC_ODD_DETECT
B13
A13
C12
D11
H12
D12
C13
(OD)
H13
(OD)
G11
F13
F12
B12
(OD)
E10
(OD)
D13
(OD)
M4
(OD)
N2
(OD)
N8
(OD)
M8
(OD)
L8
(OD)
K8
NC FOR ENG PKG
N7
NC FOR ENG PKG
M7
(OD)
N4
(OD)
N3
H11
L13
C11
A12
NC FOR STACK BRD
G3
NC FOR STACK BRD
D10
L11
N12
N11
M11
J4
J2
(OD)
CPU_PECI_R
SMC_PECI_L
C4
C6
SMC_BIL_BUTTON_L
SMC_DP_HPD_L
SMC_PME_S4_WAKE_L
SMC_PME_S4_DARK_L
SMC_S4_WAKESRC_EN
M13
L12
M5
J12
J13
NC FOR ENG PKG
64 53 46
IN
NC
NC
L5
D8
SMC_LID
K6
ENET_ASF_GPIO
SMS_INT_L
SMC_BC_ACOK
G3_POWERON_L
PM_SLP_S3_L
PM_SLP_S4_L
PM_SLP_S5_L
SMC_ONOFF_L
D4
BGA
AIN00
AIN01
AIN02
AIN03
AIN04
AIN05
AIN06
AIN07
AIN08
AIN09
AIN10
AIN11
AIN12
AIN13
AIN14
AIN15
AIN16
AIN17
AIN18
AIN19
AIN20
AIN21
AIN22
AIN23
C0C0+
C1PC5/C1+
T3CCP1/PJ5/C2T3CCP0/PJ4/C2+
K2
I2C0SCL
I2C0SDA
I2C1SCL
I2C1SDA
I2C2SCL
I2C2SDA
I2C3SCL
I2C3SDA
I2C4SCL
I2C4SDA
I2C5SCL
I2C5SDA
PM6/FAN0PWM0
PM7/FAN0TACH0
PK6/FAN0PWM1
PK7/FAN0TACH1
PN2/FAN0PWM2
PN3/FAN0TACH2
PN4/FAN0PWM3
PN5/FAN0TACH3
PN6/FAN0PWM4
PN7/FAN0TACH4
PH2/FAN0PWM5
PH3/FAN0TACH5
E1
F2
F1
B3
A3
B4
A4
B5
A5
B6
A6
C1
C2
B1
B2
G2
G1
H1
H2
B7
A7
B8
A8
IN
L2
L1
C5
D5
46
IN
46
IN
46
IN
46
IN
46
IN
46
IN
46
IN
46
IN
46
NC FOR STACK BRD
IN
IN
46
IN
46
IN
46
NC FOR STACK BRD
IN
IN
46
NC FOR STACK BRD
IN
2
46
NC FOR STACK BRD
L4901
30-OHM-1.7A
1
46
IN
7 46 82
46
IN
=PP3V3_S5_SMC
46
NC FOR STACK BRD
46
NC FOR STACK BRD
NC FOR STACK BRD
IN
1
1
C4902
1
C4904
1
C4905
IN
IN
C4906
0.1UF
0.1UF
0.1UF
10%
10V
X5R-CERM
0201
10%
10V
X5R-CERM
0201
10%
10V
X5R-CERM
0201
10%
10V
X5R-CERM
0201
2
2
2
2
2
65 47 46 6
IN
46 32 6
46
1
C4907
1
C4908
1
2
46
IN
BI
C4909
0.1UF
IN
0.1UF
0.1UF
10%
10V
X5R-CERM
0201
10%
10V
X5R-CERM
0201
10%
10V
X5R-CERM
0201
2
2
46
46
IN
46
46
WIFI_EVENT_L
SMC_WAKE_L
NC_SMC_HIB_L
B11
(OD)
N13
M12
M10
SMC_CLK32K
NC_SMC_XOSC1
N10
G12
G13
K12
10 93
IN
0.1UF
SSI0CLK/PA2
SSI0FSS/PA3
SSI0RX/PA4
SSI0TX/PA5
SMC_PM_G2_EN
PM_DSW_PWRGD
SMC_DELAYED_PWRGD
SMC_PROCHOT
M2
M3
L4
(2 OF 2)
SWCLK/TCK
SWDIO/TMS
PK4/RTCCLK
SWO/TDO
WAKE*
TDI
HIB*
OMIT_TABLE
NC
XOSC0
XOSC1
VDDA
OSC0
OSC1
VREFA+
VREFAVBAT
RST*
N1
C10
GNDA
A11
B10
A2
17
OUT
35 46 92
OUT
6 46 47
6 46 47
6 46 47
46
NC
D3
PP3V3_S5_AVREF_SMC
D2
6 46
D1
XW4900
SM
103 50
49
C3
46
GND_SMC_AVSS
2
A1
E9
C7
D9
VDD
J7
E5
J9
F9
J10
H5
1
U1RX/B0
U1TX/PB1
T0CCP0/PB6
T0CCP1/PB7
SMC_DEBUGPRT_RX_L
SMC_DEBUGPRT_TX_L
SMC_SYS_LED
SMC_GFX_THROTTLE_L
F11
E11
F4
F3
SSI1RX/PF0
SSI1TX/PF1
SSI1CLK/PF2
SSI1FSS/PF3
PF4
PF5
WT0CCP0/PG4
WT0CCP1/PG5
K7
WT2CCP0/PH0
WT2CCP1/PH1
K3
WT3CCP0/PH4
WT3CCP1/PH5
WT4CCP0/PH6
WT4CCP1/PH7
J3
T1CCP0/PJ0
T1CCP1/PJ1
T2CCP0/PJ2
T2CCP1/PJ3
SPI_SMC_MISO
SPI_SMC_MOSI
SPI_SMC_CLK
SPI_SMC_CS_L
S5_PWRGD
PM_PCH_SYS_PWROK
M9
C9
N9
L10
K10
L9
K9
IN
46
BI
2
H9
GND
46
82
J1
PP1V2_S5_SMC_VDDC
MIN_LINE_WIDTH=0.25MM
MIN_NECK_WIDTH=0.1MM
VOLTAGE=1.2V
IN
K13
NC FOR STACK BRD
OUT
46
OUT
NC FOR STACK BRD
OUT
PLACE_NEAR=U4900.D2:1MM
PLACE_NEAR=U4900.D1:1MM
PLACE_NEAR=U4900.D2:1MM
PLACE_NEAR=U4900.D1:1MM
J11
74
IN
OUT
55
IN
64 46
IN
46
IN
74 26 17 6
IN
74 32 26 17
IN
74 17
IN
53 46 6
IN
47 46 6
IN
47 46 6
OUT
(OD)
E4
F5
N5
N6
K5
M6
L6
L3
SMC_RX_L
SMC_TX_L
M1
NC
NC
E13
E12
PQ0/IRQ124
PQ1/IRQ125
PQ2/IRQ126
PQ3/IRQ127
PQ4/IRQ128
PQ5/IRQ129
PQ6/IRQ130
PQ7/IRQ131
17 23 92
OUT
IN
U0RX
U0TX
USB0DM
USB0DP
WT5CCP1/PM3
ALL_SYS_PWRGD
SMC_THRMTRIP
K4
PM_PWRBTN_L
PM_SYSRST_L
MEM_EVENT_L
SMC_ADAPTER_EN
H4
H3
G4
C8
SMC_OOB1_RX_L
SMC_OOB1_TX_L
IR_RX_OUT_RC
BDV_BKL_PWM
H10
SMC_BATLOW_L
B9
A9
20%
6.3V
X5R
0201
46
IN
1UF
2
J8
VDDC
D6
NC FOR STACK BRD
10%
10V
X5R
201
J5
J6
46
NC FOR STACK BRD
K11
46
B
42
1
46 82
C4910
1
C4911
1
C4912
1
C4913
1
C4914
1
C4915
1
C4916
1.0UF
46
C4920 1 C4921
0.01UF
42 46
OUT
SMC_DEBUGPRT_EN_L
SMC_GFX_OVERTEMP
L7
42 46
OUT
1
E3
PLACE_NEAR=U4900.A1:4MM
E8
F10
C
6 46 47
E6
46 74
OUT
SMC_TCK
SMC_TMS
SMC_TDO
SMC_TDI
A10
46
OUT
10%
10V
X5R-CERM
0201
BGA
G10
SMC_RESET_L
24
IN
C4901
2
LM4FSXAH5BB
SMC_EXTAL
SMC_XTAL
46
1
U4900
5%
1/20W
MF
201
10 46 69 93
OUT
MIN_LINE_WIDTH=0.25MM
MIN_NECK_WIDTH=0.1MM
VOLTAGE=3.3V
R4902
1M
0.1UF
20%
6.3V
X5R
0201
46
NC FOR STACK BRD
1
1UF
46
1.2V FOR ENG PKG
C4903
1
46
IN
PP3V3_S5_SMC_VDDA
0402
2
NC FOR STACK BRD
CPU_PROCHOT_L
SMC_VCCIO_CPU_DIV2
SMC_S5_PWRGD_VIN
SPI_DESCRIPTOR_OVERRIDE_L
CPU_CATERR_L
CPU_THRMTRIP_3V3
K1
46
IN
D7
PECI0RX
PECI0TX
PP0/IRQ116
PP1/IRQ117
PP2/IRQ118
PP3/IRQ119
PP4/IRQ120
PP5/IRQ121
PP6/IRQ122
PP7/IRQ123
SMC_ADC0
SMC_ADC1
SMC_ADC2
SMC_ADC3
SMC_ADC4
SMC_ADC5
SMC_ADC6
SMC_ADC7
SMC_ADC8
SMC_ADC9
SMC_ADC10
SMC_ADC11
SMC_ADC12
SMC_ADC13
SMC_ADC14
SMC_ADC15
SMC_ADC16
SMC_ADC17
SMC_ADC18
SMC_ADC19
SMC_ADC20
SMC_ADC21
SMC_ADC22
SMC_ADC23
E2
LPC0AD0
(1 OF 2)
LPC0AD1
OMIT_TABLE
LPC0AD2
LPC0AD3
LPC0CLK
LPC0FRAME*
LPC0RESET*
LPC0SERIRQ
LPC0CLKRUN*
LPC0PD*
LPC0SCI*
PK5
IN
OUT
46
OUT
0.1UF
0.1UF
0.1UF
10%
10V
X5R-CERM
0201
10%
10V
X5R-CERM
0201
10%
10V
X5R-CERM
0201
10%
10V
X5R-CERM
0201
1
0.1UF
20%
10V
X5R-CERM
0201-1
2
2
2
2
2
2
C4917
0.1UF
2
10%
10V
X5R-CERM
0201
BI
NOSTUFF
6 17 24
27 29 46
IN
NC FOR ENG PKG
1.0UF
20%
10V
X5R-CERM
0201-1
17 23
OUT
(OD)
2
23 74 89 92
1.0UF
20%
10V
X5R-CERM
0201-1
17 46 74
IN
46
OUT
46
NC FOR ENG PKG
IN
44
NC FOR ENG PKG
OUT
46
OUT
46 74
NOTE:
SMS Interrupt can be active high or low, rename net accordingly.
If SMS interrupt is not used, pull up to SMC rail.
A
NOTE:
Unused pins have " SMC_Pxx " names. Unused
pins designed as outputs can be left floating,
those designated as inputs require pull-ups.
SYNC_MASTER=J31_YONAS
PAGE TITLE
SYNC_DATE=12/19/2011
SMC
DRAWING NUMBER
Apple Inc.
051-9585
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
3.0.0
BRANCH
PAGE
49 OF 132
SHEET
45 OF 105
1
A
8
7
6
5
4
93 69 45 10
SMC Reset " Button " , Supervisor & AVREF Supply
7
SMC_CPU_VSENSE
BI
49
45
SMC_ADC1
45
SMC_CPU_ISENSE
SMC_ADC2
1
SMC12 PECI Support
SSM6N15AFE
50
MAKE_BASE=TRUE
6
SMC_GPU_HI_ISENSE
2
Q5059
MAKE_BASE=TRUE
=PP3V3_S5_SMC
=PPVIN_S5_SMCVREF
82 46 45 7
SMC_ADC0
45
3
CPU_PROCHOT_L
=PPVCCIO_S0_SMC
SOT563
D
Desktops: 5V
45
SMC_ADC3
45
SMC_ADC4
CRITICAL
SMC_DCIN_VSENSE
Mobiles: 3.42V
0.47UF
VREF-3.3V-VDET-3.0V
IN
4
DELAY
45
SN0903048
RESET*
OMIT
5
SMC_RESET_L
C5001
0
1
6 45 47 65
SMC_ADC7
45
6 45
1
1
SMC_CPU_HI_ISENSE
SMC_ADC9
SMC_ADC10
20%
6.3V
X5R
603
2
C5026
19
OUT
SMC_OTHER_HI_ISENSE
2
50
SSM6N15AFE
D
1
SMC_PECI_L
IN
2
10%
16V
CERM
402
45
SMC_ADC12
SMC_ADC13
CRITICAL
1
45
SMC_ADC14
S
G
5
2
NOSTUFF
49
SMC_THRMTRIP
SMC_GPU_VSENSE
IN
49
45 46
49
MAKE_BASE=TRUE
SMC_ADC15
45
SMC_ADC16
Q5057
SMC_GPU_ISENSE
Used on mobiles to support SMC reset via keyboard.
49
3
MAKE_BASE=TRUE
NOTE: Internal pull-ups are to VIN, not V+.
SSM6N15AFE
D
R5054
SOT563
SMC_GPU_FB_VSENSE
CRITICAL
103
45
MAKE_BASE=TRUE
45
SMC_ADC17
45
SMC_ADC18
45
SMC_CPUVCCSA_VSENSE
SMC_ADC19
43
1
CPU_PECI_R
OUT
To SMC.
49
SMC_AXG_ISENSE
50
4
MAKE_BASE=TRUE
Debug Power " Buttons "
SMC_GPU_FB_ISENSE
45
OMIT
0
5%
1/10W
MF-LF
603
C
6 45 46 53
SMC_ADC20
45
SMC_ADC21
SMC_GPU_1V05_ISENSE
2
45 82
topology of 2 SPI Masters are verified.
R5021
R5013
103
SMC_CPUMEM_ISENSE_R
1
MAKE_BASE=TRUE
45
ENET_ASF_GPIO
45
SMC_MPM5_LED_PWR
0
45
SMC_CPUMEM_ISENSE
2
NC_SMC_MPM5_LED_PWR
SPI_SMC_MISO
IN
45
SPI_SMC_MOSI
IN
SMC_MPM5_LED_CHG
45
45
NC_SMC_MPM5_LED_CHG
19
SMC_SCI_L
SMC_T25_EN_L
45
46 45
OUT
CPU_THRMTRIP_3V3
45
NC_SMC_T25_EN_L
45
SYS_TDM_ONEWIRE
45
SMC_OOB1_RX_L
NC_SYS_TDM_ONEWIRE
3
MAKE_BASE=TRUE
41
MMBT3904LP-7
DFN1006-3
CRITICAL
SMC USB Clock require 12 MHz.
SMC_OOB1_TX_L
45
SMC_SSD_OOBR2D_L
41
MAKE_BASE=TRUE
=CHGR_ACOK
65 49
SMC_BC_ACOK
1
1
PM_THRMTRIP_B_L
3.3K
2
HISIDE_ISENSE_OC
45
SMC_XTAL
45
1
2.49K
45
1%
1/20W
MF
201
SMBUS_SMC_4_ASF_SCL
SMBUS_SMC_4_ASF_SDA
2
SMC_EXTAL
1
64 53 45
47 45 6
NC_SMBUS_SMC_4_ASF_SDA
SCM12 Eng Pkg Support
BDV_BKL_PWM
NC_BDV_BKL_PWM
SMC_PME_S4_DARK_L
SDCONN_STATE_CHANGE_SMC
1
C5010
2
MAKE_BASE=TRUE
Eng Package requires 1.2V ON SMC_ADC23 pin.
45 42
24 30
MAKE_BASE=TRUE
4
NC
17
1
CRITICAL
PM_CLK32K_SUSCLK_R
IN
47 45 6
5%
50V
CERM
402
2
22
2
PP1V2_S5_SMC_VDDC
45
SMC_CLK32K
OUT
47 45 6
45
47 45 6
1
5%
1/20W
MF
201
12PF
5%
50V
CERM
402
1
PLACE_NEAR=U1800.N14:5MM
C5011
12PF
2
47 45 6
45 42
R5012
NC
IN
10 19 93
82 46 45 7
R5099
47 45 6
0
64 45 6
5%
1/16W
MF-LF
2 402
SMC_ADC23
46 45
B
64 46 45
45
R5070
R5072
R5071
R5073
R5074
R5075
R5076
R5077
R5078
R5079
R5080
R5081
R5087
R5092
SMC_ONOFF_L
G3_POWERON_L
SMC_LID
SMC_TX_L
SMC_RX_L
SMC_DEBUGPRT_TX_L
SMC_DEBUGPRT_RX_L
SMC_TMS
SMC_TDO
SMC_TDI
SMC_TCK
SMC_BIL_BUTTON_L
SMC_BC_ACOK
SMC_S5_PWRGD_VIN
46 45
R5014
R5017
MEM_EVENT_L
CPU_THRMTRIP_3V3
R5097
System (Sleep) LED Circuit
2
1
R5020
1%
1/16W
MF-LF
2 402
IN
=PSOC_WAKE_L
IN
CRITICAL
=PP3V3_S5_SMCBATLOW
=PP3V3_SUS_SMC
1
2
1
2
1
2
1
2
1
2
1
2
1
2
201
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
1/20W
MF
201
10K
100K
1
5%
1/20W
MF
201
1/20W
MF
201
2
1
2
SMC_ADAPTER_EN
R5085
10K
1
2
SMC_THRMTRIP
SMC_S4_WAKESRC_EN
SMC_DELAYED_PWRGD
SMC_PM_G2_EN
R5086
R5090
R5091
R5093
10K
100K
100K
100K
1
2
1
2
1
2
1
2
45 32 6
DMB54D0UV
R5040
SYS_LED_L
1
100K
2
Q2
S
G
1/20W
MF
201
5%
1/20W
MF
201
1/20W
MF
201
2
3
WIFI_EVENT_L
10K
1
MF
201
PP3V3_WLAN
2
74 45
IN
SMC_BATLOW_L
1/20W
CRITICAL
SYNC_MASTER=J31_YONAS
SMC Support
DRAWING NUMBER
PM_BATLOW_L
OUT
17
Apple Inc.
Internal 20K pull-up on
IN
SMC_SYS_LED
SYS_LED_ANODE
OUT
6 41
1
0
5%
1/16W
MF-LF
402
6
5
4
SYNC_DATE=01/19/2012
PAGE TITLE
45
45
7
201
5%
5%
5%
1/20W
MF
201 2
C
1
=BT_WAKE_L
201
MF
VESM
D
5%
1/20W
MF
201
OUT
MF
1/20W
SSM3K15AMFVAPE
3
Q1
R5082
R5089
Q5040
SOT-563
SMC_PME_S4_WAKE_L
1/20W
5%
7
Q5030
1
4
E
G
5
B
7
7 46
MAKE_BASE=TRUE
8
2
32 6
6
D
1%
1/16W
MF-LF
402 2
R5041
32
1
MF
1/20W
BATLOW# Isolation
100K
53
2
1/20W
5%
1
1.47K
2
1
201
5%
5%
46 45
92 45 35
S
R5032
1
2
201
MF
45
3
=PP3V3_S4_SMC
DP_A_EXT_HPD
74 45 17
2
OUT
CRITICAL
IN
1%
1/16W
MF-LF
402
74 45
SYS_LED_L_VDIV
VESM
87 86
2
74 45
SMC_DP_HPD_L
A
1
MF
1/20W
R5088
5%
1/20W
MF
2 201
SYS_LED_ILIM
Q5020
S
2
1/20W
5%
OOBR2D was TEMP_CTL, from SMC, to SSD
SMC_ROMBOOT
R5096
100K
R5030
20
1%
1/16W
MF-LF
402 2
5%
1/20W
MF
2 201
G
1
5%
5%
7 46
100K
1
2
1K
523
=PP3V3_S4_SMC
D
47 6
1
1
R5031 1
SSM3K15AMFVAPE
2
1
OOBD2R was OOB_TEMP, from SSD, to SMC
1%
1/16W
MF-LF
402
SMC_VCCIO_CPU_DIV2
S4 HPD SMC Wake Source
1
2
1
Notes:
100K
45
1
B
45 29 27
1
=PP5V_S3_SYSLED
10K
10K
100K
10K
100K
10K
100K
10K
10K
10K
10K
10K
470K
100K
SMC_PACKAGE:ENG
=PPVCCIO_S0_SMC
46 7
7
=PP3V3_S5_SMC
5%
NC_SMBUS_SMC_4_ASF_SCL
45
3
47 56
5%
45
45
12.000MHZ-30PPM-10PF
45
53 46 45 6
MAKE_BASE=TRUE
3.2X2.5MM-SM
OUT
C
SPI_MLB_CS_L
2
47 56
45 46 64
MAKE_BASE=TRUE
Y5010
OUT
PLACE_NEAR=U6100.1:1MM
PM_THRMTRIP_L
NC_HISIDE_ISENSE_OC
45
SMC_XTAL_R
5%
1/16W
MF-LF
402
47 56
5%
1/20W
MF
201
MAKE_BASE=TRUE
2
2
NO STUFF
SPI_MLB_CLK
5%
1/16W
MF-LF
402
MAKE_BASE=TRUE
R5010
1
R5024
1
R5058
Q5058
SMC_SSD_OOBD2R_L
MAKE_BASE=TRUE
0
47 56
OUT
SPI_MLB_MOSI
PLACE_NEAR=U6100.5:1MM
R5023
0
SPI_SMC_CS_L
IN
MAKE_BASE=TRUE
SMC Crystal Circuit
OUT
PLACE_NEAR=U6100.2:1MM
PLACE_NEAR=U6100.6:1MM
NO STUFF
SMC_WAKE_SCI_L
MAKE_BASE=TRUE
NO STUFF
SPI_MLB_MISO
2
5%
1/16W
MF-LF
402
SPI_SMC_CLK
IN
MAKE_BASE=TRUE
45
0
1
2
5%
1/16W
MF-LF
402
R5022
SMC_PACKAGE:PROD
MAKE_BASE=TRUE
0
1
NO STUFF
103
5%
1/20W
MF
201
NC_ENET_ASF_GPIO
MAKE_BASE=TRUE
SILK_PART=PWR_BTN
PLACE_SIDE=TOP
10 19 93
Series resistors are no stuffed until the
103
SMC_AIRPORT_ISENSE
SMC_ADC23
46 45
5%
1/10W
MF-LF
603
SILK_PART=PWR_BTN
PLACE_SIDE=BOTTOM
IN
103
MAKE_BASE=TRUE
0
2
SMC_ADC22
45
on Stack Board.
BI
From/To CPU/PCH.
SMC12 SPI Support
SMC_GFX_OVERTEMP
MAKE_BASE=TRUE
share with comparators
R5015
SMC_PCH_ISENSE
CPU_PECI
5
MAKE_BASE=TRUE
ADC10 and ADC11 are
OMIT
1
G
103
MAKE_BASE=TRUE
Note:
R5016 1
S
2
5%
1/16W
MF-LF
402
MAKE_BASE=TRUE
OUT
2
330
5%
1/16W
MF-LF
402
MAKE_BASE=TRUE
45 49 50 103
45
SMC_ONOFF_L
R5051
1.6K
5%
1/16W
MF-LF
402
MAKE_BASE=TRUE
SMC_CPUVCCSA_ISENSE
D
1
R5053
49
4
SMC_AXG_VSENSE
S 2
SMC_PECI_L_R
5%
1/16W
MF-LF
402
From SMC.
SOT563
50
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.1MM
VOLTAGE=0V
MR1* and MR2* must both be low to cause manual reset.
45
Q5059
0
49
SMC_CPUVCCIO_ISENSE
G
R5052
PM_THRMTRIP_L_R
3
SMC_MEM_ISENSE
SMC_ADC11
45
GND_SMC_AVSS
PLACEMENT_NOTE=Place R5001 on BOTTOM side
45
MAKE_BASE=TRUE
0.01UF
10uF
2
IN
1
50
MAKE_BASE=TRUE
C5025
SILK_PART=SMC_RST
VESM
SMC_PROCHOT
MAKE_BASE=TRUE
45
D 3
SSM3K15AMFVAPE
2
49
SMC_BMON_ISENSE
SMC_ADC8
45
45
10%
16V
CERM
402
G
103
MAKE_BASE=TRUE
45
0.01UF
5%
1/10W
MF-LF
2 603
OUT
MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.1MM
VOLTAGE=3.3V
8
SMC_PBUS_VSENSE
SMC_HDD_ISENSE
PAD
GND
R5001
REFOUT
THRM
SMC_ADC6
1
S
MAKE_BASE=TRUE
PP3V3_S5_AVREF_SMC
2
1
Q5050
50
MAKE_BASE=TRUE
(IPU)
CRITICAL
SMC_ADC5
45
9
53 46 45 6
MR1*
SMC_DCIN_ISENSE
MAKE_BASE=TRUE
5%
1/16W
MF-LF
402
MR2*
SMC_MANUAL_RST_L
D
7
2
DFN
(IPU)
6
R5000
100K
VIN
U5010
2
SMC_TPAD_RST_L
SMC_ONOFF_L
IN
1
3
1
1
V+
10%
6.3V
CERM-X5R
402
53
49
MAKE_BASE=TRUE
C5020
7 46
CRITICAL
50
MAKE_BASE=TRUE
PM_BATLOW_L in PCH.
2
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
NOSTUFF
3
051-9585
2
SIZE
D
REVISION
3.0.0
BRANCH
PAGE
50 OF 132
SHEET
46 OF 105
1
A
8
7
6
5
4
3
2
1
D
D
LPC+SPI Connector
CRITICAL
LPCPLUS_CONN:YES
J5100
55909-0374
M-ST-SM
7
7
31
=PP3V3_S5_LPCPLUS
=PP5V_S0_LPCPLUS
32
1
96 89 45 16 6
96 89 45 16 6
BI
LPC_CLK33M_LPCPLUS
LPC_AD & lt; 2 & gt;
LPC_AD & lt; 3 & gt;
2
3
4
5
LPC_AD & lt; 0 & gt;
LPC_AD & lt; 1 & gt;
BI
6
7
OUT
24 6
IN
46 45 6
OUT
46 45 6
IN
15
16
17
18
19
20
21
22
23
24
25
26
27
C
14
28
30
33
IN
OUT
46 45 6
12
13
SPI_ALT_MOSI
SPI_ALT_MISO
LPC_FRAME_L
PM_CLKRUN_L
SMC_TMS
LPCPLUS_RESET_L
SMC_TDO
TP_SMC_TRST_L
TP_SMC_MD1
SMC_TX_L
IN
OUT
45 17 6
11
29
47 6
47 6
96 89 45 16 6
10
6 24 96
BI
6 16 45 89 96
BI
6 16 45 89 96
8
9
IN
34
SPIROM_USE_MLB
SPI_ALT_CLK
SPI_ALT_CS_L
LPC_SERIRQ
LPC_PWRDWN_L
SMC_TDI
SMC_TCK
SMC_RESET_L
SMC_ROMBOOT
SMC_RX_L
LPCPLUS_GPIO
OUT
6 19 56
IN
6 47
IN
6 47
6 16 45
BI
IN
6 17 45
OUT
6 45 46
OUT
6 45 46
OUT
6 45 46 65
OUT
6 46
OUT
6 45 46
OUT
6 19
C
516S0573
SPI Bus Series Termination
SPI_ALT_MISO
SPI_ALT_MOSI
SPI_ALT_CLK
SPI_ALT_CS_L
LPCPLUS_R:YES
1
LPCPLUS_R:YES
1
R5128
LPCPLUS_R:YES
1
R5127
R5125
0
2
PLACE_NEAR=U1800.AV3:5mm
96 16
IN
B
96 16
IN
IN
SPI_MOSI_R
R5112
1
15
5%
1/16W
MF-LF
402
96
47
1
2
96
1
OUT
R5123
SPI_MISO
1
15
5%
1/16W
MF-LF
402
47
5%
1/16W
MF-LF
402
46 56
OUT
46 56
OUT
46 56
IN
46 56
PLACE_NEAR=R5125.2:5mm
B
SPI_MLB_CLK
2
5%
1/16W
MF-LF
402
OUT
SPI_MLB_MISO
1
SPI_MOSI
SPI_MLB_CS_L
SPI_MLB_MOSI
47
SPI_CLK
R5122
2
2
5%
1/16W
MF-LF
402
R5121
96
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
96 16
2
SPI_CS0_L
5%
1/16W
MF-LF
402
15
1
PLACE_NEAR=U1800.AY1:5mm
96 16
R5111
2
PLACE_NEAR=J5100.14:5mm
PLACE_NEAR=J5100.12:5mm
PLACE_NEAR=J5100.9:5mm
PLACE_NEAR=J5100.11:5mm
47
5%
1/16W
MF-LF
402
2
6 47
R5120
15
1
SPI_CLK_R
47
5%
1/16W
MF-LF
402
R5110
SPI_CS0_R_L
PLACE_NEAR=U1800.BA2:5mm
47
5%
1/16W
MF-LF
402
2
6 47
LPCPLUS_R:YES
1
R5126
6 47
6 47
PLACE_NEAR=R5126.2:5mm
2
PLACE_NEAR=R5127.2:5mm
2
PLACE_NEAR=U6100.2:5mm
A
SYNC_MASTER=J5_MLB
SYNC_DATE=05/26/2011
PAGE TITLE
LPC+SPI Debug Connector
DRAWING NUMBER
Apple Inc.
051-9585
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
3.0.0
BRANCH
PAGE
51 OF 132
SHEET
47 OF 105
1
A
8
7
6
5
=PP3V3_S0_SMBUS_PCH
7
R5200 1
Panther Point
5%
1/16W
MF-LF
402
U1800
(MASTER)
96 16
D
R5201
SO-DIMM " A "
1K
2
2
1
R5251
4.7K
U4900
(MASTER)
27
SMB_0_S0_CLK
99
45
=I2C_SODIMMA_SDA
27
SMB_0_S0_DATA
99
45
MAKE_BASE=TRUE
GPU Temp (Ext)
4.7K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
2
2
=PP3V42_G3H_SMBUS_SMC_5
R5280 1
SMC
EMC1414-A: U5550
(Write: 0x98 Read: 0x99)
SMBUS_SMC_0_S0_SCL
51
SMB_5_CLK
=I2C_GPUTHMSNS_SDA
51
SMB_5_DATA
5%
1/16W
MF-LF
402
2
2
SMBUS_SMC_5_G3_SCL
Battery Charger
ISL6258 - U7000
(Write: 0x12 Read: 0x13)
=SMBUS_CHGR_SCL
65
=SMBUS_CHGR_SDA
SMBUS_SMC_5_G3_SDA
65
D
MAKE_BASE=TRUE
SO-DIMM " B "
GPU Temp (Int)
J3100
(Write: 0xA4 Read: 0xA5)
U3300
(Write: 0x98 Read: 0x99)
2.0K
MAKE_BASE=TRUE
SMBUS_SMC_0_S0_SDA
MAKE_BASE=TRUE
VRef DACs
R5281
5%
1/16W
MF-LF
402
U4900
(MASTER)
=I2C_GPUTHMSNS_SCL
1
2.0K
MAKE_BASE=TRUE
MAKE_BASE=TRUE
1
SMC " 5 " SMBus Connections
7
R5250 1
=I2C_SODIMMA_SCL
SMBUS_PCH_DATA
2
=PP3V3_S0_SMBUS_SMC_0_S0
SMC
J2900
(Write: 0xA0 Read: 0xA1)
5%
1/16W
MF-LF
402
SMBUS_PCH_CLK
96 16
1
1K
3
SMC " 0 " SMBus Connections
PCH SMBus " 0 " Connections
48 7
4
Battery
KEPLER: U8000
(Write: 0x82 Read: 0x83)
J6955
(See Table)
Battery
31
=I2C_VREFDACS_SCL
=I2C_SODIMMB_SCL
29
GPU_SMB_CLK_R
82
31
=I2C_VREFDACS_SDA
=I2C_SODIMMB_SDA
29
GPU_SMB_DAT_R
82
Battery Manager - (Write: 0x16 Read: 0x17)
Battery LED Driver - (Write: 0x36 Read: 0x37)
Battery Temp - (Write: 0x92 Read: 0x93)
=SMBUS_BATT_SCL
64
=SMBUS_BATT_SDA
64
Margin Control
SMC " 3 " SMBus Connections
U3301
(Write: 0x30 Read: 0x31)
31
=I2C_PCA9557D_SCL
31
=I2C_PCA9557D_SDA
7
=PP3V3_S3_SMBUS_SMC_3
R5290
SMC
SATA Redriver
U9701
U4510
C
SMB_3_CLK
SMB_3_DATA
(WRITE: 0x58 READ: 0x59)
99
45
99
45
(Write: 0xB6 Read: 0xB7)
41
41
=I2C_BKL_1_SCL
=SATARDRVR_I2C_SDA
=I2C_BKL_1_SDA
SMC " 2 " SMBus Connections
90
Mikey
U6880
(Write: 0x72 Read: 0x73)
SMBUS_SMC_3_SCL
=I2C_SMC_ADCS_SCL
104
=I2C_SMC_ADCS_SDA
=SMBUS_XDP_SCL
=I2C_MIKEY_SCL
=SMBUS_XDP_SDA
=I2C_MIKEY_SDA
SMBUS_SMC_3_SDA
104
C
=PP3V3_S3_SMBUS_SMC_2_S3
R5270 1
SMC
SMB_2_S3_CLK
R5271
T29 SMBus Connections
Trackpad
1K
5%
1/16W
MF-LF
402 2
U4900
(MASTER)
63
1
1K
5%
1/16W
MF-LF
2 402
J5800
(Write: 0x90 Read: 0x91)
SMBUS_SMC_2_S3_SCL
7
=I2C_TPAD_SCL
=I2C_TPAD_SDA
54
=PP3V3_S0_T29I2C
54
MAKE_BASE=TRUE
63
SMB_2_S3_DATA
SMBUS_SMC_2_S3_SDA
R5230 1
T29 IC
MAKE_BASE=TRUE
1
SDRVI2C:SB
R5237
1
0
5%
1/20W
MF
201 2
DP SDRV " A "
J3401
U9310
(Write: 0x94 Read: 0x95)
(Write: 0x72 Read: 0x73)
0
5%
1/20W
MF
2 201
98 33
R5231
4.7K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
2
2
I2C_TBT_SDA
=I2C_TBTAMCU_SCL
87
=I2C_TBTAMCU_SDA
87
MAKE_BASE=TRUE
Lid Angle Detect
MAKE_BASE=TRUE
48
I2C_DPSDRVA_SCL
I2C_DPSDRVA_SDA
(Write: 0x32 Read: 0x33)
=I2C_DPSDRVA_SCL
48 87
=I2C_DPSDRVA_SDA
48 87
=I2C_ALS_SCL
MAKE_BASE=TRUE
32
=I2C_ALS_SDA
MAKE_BASE=TRUE
32
SDRVI2C:MCU
R5234 1
0
5%
1/20W
MF
201 2
Digital SMS
PCH " SMLink 0 " Connections
LIS331DLH: U5920
(Write: 0x30 Read: 0x31)
SDRVI2C:MCU
1
R5235
DP SDRV " A "
0
5%
1/20W
MF
2 201
U9310
(Write: 0x94 Read: 0x95)
=PP3V3_S0_SMBUS_PCH
48
R5210 1
1
48 87
55
=I2C_DPSDRVA_SDA
48 87
=I2C_SMC_SMS_SDA
55
MAKE_BASE=TRUE
R5211
8.2K
8.2K
5%
1/16W
MF-LF
402
U1800
(MASTER)
I2C_DPSDRVA_SDA
B
=I2C_DPSDRVA_SCL
MAKE_BASE=TRUE
=I2C_SMC_SMS_SCL
Panther Point
I2C_DPSDRVA_SCL
48
48 7
T29 Port A MCU
J9330
(Write: 0x26 Read: 0x27)
I2C_TBT_SCL
98 33
ALS
1
4.7K
U3600
(MASTER)
R5236
48
5%
1/16W
MF-LF
402
2
2
SML_PCH_0_CLK
SMC " 1 " SMBus Connections
MAKE_BASE=TRUE
96 16
U5930
(Write: 0x10 Read: 0x11)
MAKE_BASE=TRUE
SDRVI2C:SB
96 16
5%
1/16W
MF-LF
2 402
90
J2500 & J2550
(MASTER)
B
Sensor ADC A
4.7K
NOTE: SMC RMT bus remains powered and may be active in S3 state
XDP Connectors
23
R5291
MAKE_BASE=TRUE
=SATARDRVR_I2C_SCL
7
23
1
5%
1/16W
MF-LF
402 2
U4900
(MASTER)
LED BACKLIGHT
1
4.7K
SML_PCH_0_DATA
MAKE_BASE=TRUE
7
=PP3V3_S0_SMBUS_SMC_1_S0
R5260 1
SMC
PCH " SMLink 1 " Connections
48 7
R5261
99
45
SMB_1_S0_CLK
CPU Temp
4.7K
5%
1/16W
MF-LF
402
U4900
(MASTER)
=PP3V3_S0_SMBUS_PCH
1
4.7K
5%
1/16W
MF-LF
402
2
2
EMC1414-A: U5570
(Write: 0x98 Read: 0x99)
SMBUS_SMC_1_S0_SCL
=I2C_CPUTHMSNS_SCL
51
=I2C_CPUTHMSNS_SDA
51
MAKE_BASE=TRUE
NO STUFF
Panther Point
A
U1800
(Write: 0x88 Read: 0x89)
96 16
R5220 1
1
8.2K
5%
1/16W
MF-LF
402
SML_PCH_1_CLK
2
SMBUS_SMC_1_S0_SDA
MAKE_BASE=TRUE
R5221
8.2K
2
99
45
SMB_1_S0_DATA
NO STUFF
R5223
5%
1/16W
MF-LF
402
0
5%
1/16W
MF-LF
402
1
96 16
SML_PCH_1_DATA
SYNC_MASTER=K18_MLB
T29 Temp
1
SMBus Connections
EMC1412-A: U5520
(Write: 0x90 Read: 0x91)
2
DRAWING NUMBER
MAKE_BASE=TRUE
R5222
Apple Inc.
=I2C_T29THMSNS_SCL
0
5%
1/16W
MF-LF
402
SMLink 1 is slave port to
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
7
6
5
4
051-9585
3
2
SIZE
D
REVISION
R
=I2C_T29THMSNS_SDA
access PCH & CPU via PECI.
8
SYNC_DATE=04/27/2010
PAGE TITLE
2
MAKE_BASE=TRUE
3.0.0
BRANCH
PAGE
52 OF 132
SHEET
48 OF 105
1
A
8
7
6
5
4
3
2
1
GPU Core Load Side Current Sense (IG0C)
Gain: 130.2x, EDP: 25 A
Rsense: 0.001 (R8940)
PBUS Voltage Sense & Enable (VP0R)
Gain Number needs Updating!
V across Rsense: 25 mV
NOSTUFF
PLACE_NEAR=U4900.B2:5MM
Gain needed: 132.0x
84
IN
CRITICAL
R5359
4.53K
GFXIMVP6_IMON
1
104 103 50 49 7
Q5300
2
NTUD3169CZ
1%
1/20W
MF
201
=PP3V3_S0_ISNS
SOT-963
N-CHANNEL
LOADISNS:YES
1
LOADISNS:YES
D
U5350
2
74
4
1
1%
1/20W
MF
201
2
ISNS_GPU_INV
OUT
S
D
R5303 1
C5358
0.22UF
LOADISNS:YES
2
PLACE_NEAR=U4900.B2:5MM
R5350
20%
6.3V
X5R
0201
=PPBUS_S0_VSENSE
7
LOADISNS:YES
27.4K
G
5
1%
1/20W
MF
201
S
4
2
Rthevenin = 4573 Ohms
P-CHANNEL
499K
2
PLACE_NEAR=U4900.A3:5MM
PBUS_S0_VSENSE
46
PLACE_NEAR=U4900.B2:5MM
1
D
1%
1/16W
MF-LF
402 2
3
SMC_GPU_ISENSE
2
1
100K
G
2
1
4.53K
ISNS_GPU_IOUT
V-
-
=PBUSVSENS_EN
IN
R5358
SC70-5
V+
1
PBUSVSENS_EN_L
R5302
20%
10V
CERM
402
OPA333DCKG4
5
+
3
6
D
0.1UF
CRITICAL
1
Enables PBUS VSense
divider when in S0.
C5350
1%
1/20W
MF
201
1M
1
LOADISNS:YES
GND_SMC_AVSS
SIGNAL_MODEL=EMPTY
100K
45 46 49 50 103
2
1%
1/16W
MF-LF
402
LOADISNS:YES
1%
1/20W
MF
201
SMC_PBUS_VSENSE
R5301 1
R5357
R5304
1
5.49K
1%
1/20W
MF
201 2
2
46
C5304
0.22UF
20%
6.3V
X5R
0201
2
PBUSVSENS_EN_L_DIV
SIGNAL_MODEL=EMPTY
OUT
PLACE_NEAR=U4900.A3:5MM
1
GND_SMC_AVSS
45 46 49 50 103
PLACE_NEAR=U4900.A3:5MM
CPU VCCIO 1.05V Load Side Current Sense (IC1C)
Gain: 161.5x, EDP: 20 A
DC-In Voltage Sense & Enable (VD0R)
Rsense: 0.001 (R7640)
104 103 50 49 7
=PP3V3_S0_ISNS
V across Rsense: 20 mV
CRITICAL
Gain needed: 165x
LOADISNS:YES
LOADISNS:YES
SIGNAL_MODEL=EMPTY
Enables DC-In VSense
CRITICAL
C
101 71
IN
6.19K
CPUVCCIOS0_CS_P
1
1
2
3
101 71
IN
CPUVCCIOS0_CS_N
1
2
4 ISNS_CPUVCCIO_IOUT
1
4.53K
2
1%
1/20W
MF
201
V-
-
R5324
2
OUT
46
65 46
IN
=CHGR_ACOK
74
IN
PM_SUS_EN
1
20%
6.3V
X5R
0201
LOADISNS:YES
GND_SMC_AVSS
1
3
2
R5313
=PPDCIN_S5_VSENSE
7
PLACE_NEAR=U4900.F1:5MM
DCIN_S5_VSENSE
D
1%
1/20W
MF
201 2
S
4
SIGNAL_MODEL=EMPTY
SMC_DCIN_VSENSE
R5311 1
1%
1/16W
MF-LF
402
CPU VCCSA Load Side Current Sense (IC2C)
Gain: 549x, EDP: 6A
104 103 50 49 7
LOADISNS:YES
U5360
101 66
IN
1
2
101 ISNS_CPUVCCSA_R_P
B
3
R5364
101 66
IN
1.82K
VCCSAS0_CS_N
1
2
+
2
OPA333DCKG4
5
4 ISNS_CPUVCCSA_IOUT
4.53K
2
R5365
SMC_CPUVCCSA_ISENSE
OUT
46
XW5320
C5367
105 14 12 7
0.22UF
20%
6.3V
X5R
0201
1
2
CPUVSENSE_IN
1
DESCRIPTION
3
BOM OPTION
=PPVCORE_S0_AXG_REG
1
2
R5330
AXGVSENSE_IN
4.53K
1
SMC_AXG_VSENSE
2
1%
1/20W
MF
201
=PP3V3_S3_ISNS
3
PLACE_NEAR=R5370.4:10MM
2
20%
10V
CERM
402
PLACE_NEAR=U4900.B6:5MM
0.001
1%
1W
MF-1
0612
101
1
3
ISNS_1V5_S3_DDR_P
4
OUT
CRITICAL
SC70
IN+
REF
6
ISNS_1V5_S3_DDR_IOUT
4.53K
1
2
SMC_MEM_ISENSE
=PP1V5_S3_DDR_ISNS_R
OUT
1
XW5335
7
0.22UF
2
R5335
SM
C5379
=PPVCORE_GPU_REG
1
2
GPUVSENSE_IN
PLACE_NEAR=R8940.1:5 MM
20%
6.3V
X5R
0201
SYNC_MASTER=J31_YONAS
Power Sensors: Load Side
4.53K
1
SMC_GPU_VSENSE
2
1%
1/20W
MF
201
8
7
6
5
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
3
051-9585
45 46 49 50 103
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
2
SIZE
D
REVISION
R
20%
6.3V
X5R
0201
GND_SMC_AVSS
4
DRAWING NUMBER
46
C5335
0.22UF
2
45 46 49 50 103
OUT
PLACE_NEAR=U4900.B1:5MM
1
PLACE_NEAR=U4900.B1:5MM
GND_SMC_AVSS
SYNC_DATE=01/19/2012
PAGE TITLE
46
PLACE_NEAR=U4900.B6:5MM
PLACE_NEAR=R5370.3:10MM
2
IN
1
1%
1/20W
MF
201
GND
7
GPU Core Voltage Sense (VG0C)
R5379
INA210
IN-
45 46 49 50 103
C5370
U5370
5
20%
6.3V
X5R
0201
0.1UF
V+
2 4 101 ISNS_1V5_S3_DDR_N
45 46 49 50 103
C5330
GND_SMC_AVSS
OUT =PP1V5_S3_DDR_ISNS
20%
6.3V
X5R
0201
0.22UF
V across Rsense: 9 mV
1
0.22UF
GND_SMC_AVSS
46
46
C5380
PLACE_NEAR=U4900.C1:5MM
1
2
R5370
OUT
OUT
PLACE_NEAR=U4900.G1:5MM
1
PLACE_NEAR=U4900.G1:5MM
PLACE_NEAR=U4900.C1:5MM
Gain needed: 336.7x
SMC_CPUVCCSA_VSENSE
2
2
XW5330
LOADISNS:NO
C5358,C5327,C5367
4.53K
1
1%
1/20W
MF
201
Gain: 200x, EDP: 9A
A
45 46 49 50 103
AXG Core Voltage Sense (VN0C)
CRITICAL
DDR 1.5V S3 (Memory) Current Sense (IM0C)
7
2
PLACE_NEAR=R7140.1:5 MM
CPUVCCSAVSENSE_IN
PLACE_NEAR=R7550.2:5 MM
104 103 7
1
20%
6.3V
X5R
0201
GND_SMC_AVSS
70 7
Rsense: 0.001 (R5370)
=PPVCCSA_S0_REG
R5380
REFERENCE DES
RES,100K,201
66 7
C5320
LOADISNS:YES
SM
117S0008
46
0.22UF
45 46 49 50 103
2
1%
1/16W
MF-LF
402
OUT
PLACE_NEAR=U4900.E2:5MM
1
PLACE_NEAR=U4900.E2:5MM
GND_SMC_AVSS
1M
LOADISNS:YES
QTY
SMC_CPU_VSENSE
2
1%
1/20W
MF
201
B
SM
4.53K
1
PLACE_NEAR=R7510.2:5 MM
LOADISNS:YES
SIGNAL_MODEL=EMPTY
PART NUMBER
=PPVCORE_S0_CPU
XW5380
R5320
SM
PLACE_NEAR=U4900.C2:5MM
1
R5366
SIGNAL_MODEL=EMPTY
45 46 49 50 103
CPU VCCSA Voltage Sense (VC2C)
2
1%
1/16W
MF-LF
2 402
GND_SMC_AVSS
CPU Core Voltage Sense (VC0C)
2
1%
1/20W
MF
201
V-
-
1
1M
LOADISNS:YES
SIGNAL_MODEL=EMPTY
20%
6.3V
X5R
0201
PLACE_NEAR=U4900.C2:5MM
R5367
ISNS_CPUVCCSA_R_N
1
0.22UF
2
LOADISNS:YES
2
1%
1/16W
MF-LF
402
C5314
PLACE_NEAR=U4900.F1:5MM
20%
10V
CERM
402
SC70-5
V+
1%
1/16W
MF-LF
402
46
0.1UF
R5363
1.82K
1
PDCINVSENS_EN_L_DIV
C5360
CRITICAL
1
1%
1/20W
MF
201 2
OUT
PLACE_NEAR=U4900.F1:5MM
1
5.49K
LOADISNS:YES
1
LOADISNS:YES
SIGNAL_MODEL=EMPTY
VCCSAS0_CS_P
R5314
2
=PP3V3_S0_ISNS
V across Rsense: 6mV
Gain needed: 550x
Rthevenin = 4573 Ohms
P-CHANNEL
100K
Rsense: 0.001 (R7140)
1
27.4K
G
5
LOADISNS:YES
1%
1/20W
MF
201
SIGNAL_MODEL=EMPTY
45 46 49 50 103
2
1%
1/16W
MF-LF
402 2
S
5%
1/20W
MF
201
1M
LOADISNS:YES
100K
G
2
0
1
R5326
1
R5312 1
R5394
1M
LOADISNS:YES
SIGNAL_MODEL=EMPTY
C
DCINVSENS_EN_L
2
5%
1/20W
MF
201
C5327
0.22UF
R5325
1%
1/20W
MF
2 201
6
D
DCIN_VSENSE_EN
0
PLACE_NEAR=U4900.A6:5MM
1
ISNS_CPUVCCIO_R_N
1
N-CHANNEL
R5393
SMC_CPUVCCIO_ISENSE
2
1%
1/20W
MF
201
SOT-963
NOSTUFF
R5327
SC70-5
V+
NTUD3169CZ
divider when AC present.
PLACE_NEAR=U4900.A6:5MM
OPA333DCKG4
5
+
101 ISNS_CPUVCCIO_R_P
1%
1/20W
MF
201
6.19K
Q5310
LOADISNS:YES
U5320
R5323
3.0.0
BRANCH
PAGE
53 OF 132
SHEET
49 OF 105
1
A
8
7
6
5
4
3
2
1
CPU High Side Current Sense (IC0R)
Gain: 50x, EDP: 22.8 A
Rsense: 0.003 (R5400)
V across Rsense: 68.4 mV
Gain needed: 48.25x
104 103 50 49 7
CPU Core Load Side Current Sense (IC0C)
=PP3V3_S0_ISNS
Gain: 136.1x, EDP: 97 A
1
3
D
7
OUT =PPVIN_S5_HS_COMPUTING_ISNS
2
Rsense: 3x of 0.00075 (R7510, R7520. R7530), Rsum: 0.00025.
V across Rsense: 24.25 mV
20%
10V
CERM
402
5
IN-
101 ISNS_HS_COMPUTING_P
4
IN+
0.003
2%
0.5W
MF
0612
R5403
INA213
2 4 101 ISNS_HS_COMPUTING_N
SC70
OUT
HS_COMPUTING_IOUT
6
4.53K
1
1
2
1%
1/20W
MF
201
CRITICAL
REF
1
3
SMC_CPU_HI_ISENSE
2
1
2
1%
1/20W
MF
201
R5457
C5403
101 70 69
20%
6.3V
X5R
0201
IN
50 7
5.23K
CPUIMVP_ISNS2_P
1
101 70 69
45 46 49 50 103
IN
1%
1/20W
MF
201
CPUIMVP_ISNS3_P
1
101 70 69
IN
Rsense: 0.003 (R5410)
CPUIMVP_ISNS1_N
1
V across Rsense: 15.6 mV
Gain needed: 211.54x (Kepler)
3
OUT =PPVIN_S5_HS_GPU_ISNS
CRITICAL
2
C5411
2%
0.5W
MF
0612
5
IN-
SC70
OUT
1
2
101 CPUIMVP_ISNS_P
ISNS_HS_GPU_P
4
IN+
REF
1
2
1%
1/20W
MF
201
1
SMC_GPU_HI_ISENSE
1
2
101
CPUIMVP_ISUM_R_P
1%
1/16W
MF-LF
402
5.23K
2
1
3.57K
+
IN
1
OUT
PLACE_NEAR=U4900.F2:5MM
2
4
-
4.53K
2
1%
1/20W
MF
201
V2
1
SMC_CPU_ISENSE
1
2
R5454
OUT
46
C5451
0.22UF
LOADISNS:YES
20%
6.3V
X5R
0201
LOADISNS:YES
PLACE_NEAR=U4900.E1:5MM
732K
LOADISNS:YES
2
1%
1/16W
MF-LF
402
R5455
GND_SMC_AVSS
732K
1
LOADISNS:YES
1%
1/16W
MF-LF
402
SIGNAL_MODEL=EMPTY
45 46 49 50 103
2
LOADISNS:YES
5.23K
1
CPUIMVP_ISUM_IOUT
PLACE_NEAR=U4900.E1:5MM
1%
1/20W
MF
201
CPUIMVP_ISNS3_N
R5451
SC70-5
CPUIMVP_ISUM_R_N
2
20%
10V
CERM
402
2
OPA333DCKG4
5
V+
3
1%
1/16W
MF-LF
402
5.23K
1
R5453
101 CPUIMVP_ISNS_N
SIGNAL_MODEL=EMPTY
2
1%
1/20W
MF
201
C
46
C5413
AXG Core Load Side Current Sense (IN0C)
0.22UF
3
=PPVIN_S5_HS_GPU_ISNS_R
1
2
PLACE_NEAR=R7530.4:5MM
SIGNAL_MODEL=EMPTY
LOADISNS:YES
2
IN
4.53K
HS_GPU_IOUT
6
GND
7
101 70
CRITICAL
101
3.57K
R5472
20%
10V
CERM
402
R5413
INA210
2 4 101 ISNS_HS_GPU_N
0.003
1
PLACE_NEAR=R7520.4:5MM
SIGNAL_MODEL=EMPTY
LOADISNS:YES
U5410
R5410
CPUIMVP_ISNS2_N
0.1UF
V+
C
IN
=PP3V3_S0_ISNS
1
7
5.23K
R5471
101 70
0.1UF
U5450
R5452
1%
1/20W
MF
201
PLACE_NEAR=R7510.4:5MM
SIGNAL_MODEL=EMPTY
LOADISNS:YES
C5450
LOADISNS:YES
R5470
GPU High Side Current Sense (IG0R)
1
CRITICAL
1%
1/20W
MF
201
PLACE_NEAR=R7530.3:5MM
SIGNAL_MODEL=EMPTY
LOADISNS:YES
Gain: 200x, EDP: 5.2 A (Kepler)
PLACE_NEAR=U5450.5:3MM
LOADISNS:YES
PLACE_NEAR=R7520.3:5MM
SIGNAL_MODEL=EMPTY
LOADISNS:YES
GND_SMC_AVSS
LOADISNS:YES
=PP3V3_S0_IMVPISNS
2
R5458
104 103 50 49 7
D
5.23K
CPUIMVP_ISNS1_P
PLACE_NEAR=R7510.3:5MM
SIGNAL_MODEL=EMPTY
LOADISNS:YES
46
0.22UF
PLACE_NEAR=U4900.B5:5MM
=PPVIN_S5_HS_COMPUTING_ISNS_R
OUT
IN
PLACE_NEAR=U4900.B5:5MM
2
IN
101 70 69
1
GND
7
Gain needed: 136.1x
R5456
U5400
R5400
CRITICAL
C5401
0.1UF
V+
20%
6.3V
X5R
0201
Gain: 185.5x, EDP: 46 A
PLACE_NEAR=U4900.F2:5MM
Rsense: 2x of 0.00075 (R7550, R7560), Rsum: 0.000375.
V across Rsense: 17.25 mV
Gain needed: 191.3x
GND_SMC_AVSS
45 46 49 50 103
OTHER High Side Current Sense (IO0R)
R5466
Gain: 50x, EDP: 10.3 A
101 70
Rsense: 0.005 (R5440)
IN
1
0.5%
1/16W
MF
402
Gain needed: 64.1x
101 70
=PP3V3_S0_ISNS
1
3
OUT =PPVIN_S5_HS_OTHER_ISNS
CRITICAL
20%
10V
CERM
402
2%
0.5W
MF
0612
5
IN-
SC70
OUT
HS_OTHER_IOUT
6
1
ISNS_HS_OTHER_P
4
IN+
REF
4.53K
1%
1/20W
MF
201
1
2
SMC_OTHER_HI_ISENSE
1
=PPVIN_S5_HS_OTHER_ISNS_R
PLACE_NEAR=U4900.A5:5MM
OUT
2
20%
6.3V
X5R
0201
IN
CPUIMVP_ISNS2G_N
1
PLACE_NEAR=U4900.A5:5MM
5.23K
45 46 49 50 103
LOADISNS:YES
2
4 CPUIMVP_ISUMG_IOUT
1
4.53K
1%
1/20W
MF
201
V2
SMC_AXG_ISENSE
1
2
R5464
OUT
46
C5461
0.22UF
LOADISNS:YES
PLACE_NEAR=U4900.H1:5MM
1
2
20%
6.3V
X5R
0201
LOADISNS:YES
PLACE_NEAR=U4900.H1:5MM
732K
1%
1/16W
MF-LF
2 402
SIGNAL_MODEL=EMPTY
R5465
GND_SMC_AVSS
732K
1
45 46 49 50 103
2
1%
1/16W
MF-LF
402
SIGNAL_MODEL=EMPTY
QTY
DESCRIPTION
REFERENCE DES
2
RES,100K,201
C5451,C5461
CRITICAL
BOM OPTION
LOADISNS:NO
Rsense: 0.020 (R7020)
Max Measured I: 8.3 A
PLACE_NEAR=U4900.B3:5MM
R5422
45.3K
1
2
1%
1/20W
MF
201
R5441
SMC_BMON_ISENSE
1
OUT
46
65
IN
CHGR_AMON
4.53K
1
2
1%
1/20W
MF
201
C5422
SMC_DCIN_ISENSE
1
0.022UF
2
10%
6.3V
X5R-CERM
0201
PLACE_NEAR=U4900.A4:5MM
OUT
46
C5441
0.22UF
2
20%
6.3V
X5R
0201
SYNC_MASTER=J31_YONAS
PLACE_NEAR=U4900.B3:5MM
SYNC_DATE=10/25/2011
PAGE TITLE
Power Sensors: High Side, CPU, AXG
DRAWING NUMBER
GND_SMC_AVSS
GND_SMC_AVSS
45 46 49 50 103
Apple Inc.
45 46 49 50 103
051-9585
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
7
6
5
4
3
2
SIZE
D
REVISION
R
8
B
LOADISNS:YES
Charger Gain: 20x
PLACE_NEAR=U4900.A4:5MM
A
-
R5461
SC70-5
CPUIMVP_ISUMG_R_N
LOADISNS:YES
PART NUMBER
5
20%
10V
CERM
402
DC-In (AMON) Current Sense (ID0R)
Charger Gain: 36x
Rsense: 0.010 (R7050)
Max Measured I: 9.2 A
CHGR_BMON
2
1%
1/16W
MF-LF
402
0.5%
1/16W
MF
402
PLACE_NEAR=R7560.3:5MM
SIGNAL_MODEL=EMPTY
LOADISNS:YES
Charger (BMON Prod) Current Sense (IPBR)
1
101 CPUIMVP_ISNS1G_R_N
+
2
OPA333DCKG4
V+
3
1.33K
2
R5469
101 70
101 CPUIMVP_ISUMG_R_P
R5463
117S0008
IN
1
2
0.5%
1/16W
MF
402
C5460
0.1UF
U5460
1%
1/16W
MF-LF
402
1
46
C5433
GND_SMC_AVSS
65
1
101 CPUIMVP_ISNS1G_R_P
5.23K
CPUIMVP_ISNS1G_N
PLACE_NEAR=R7550.4:5MM
SIGNAL_MODEL=EMPTY
LOADISNS:YES
0.22UF
3
2
IN
1
CRITICAL
101
IN
R5433
GND
7
101 70
INA213
2 4 101 ISNS_HS_OTHER_N
0.005
B
2
1.33K
2
0.5%
1/16W
MF
402
R5467
C5431
U5430
R5430
1
PLACE_NEAR=R7560.3:5MM
SIGNAL_MODEL=EMPTY
LOADISNS:YES
1
CRITICAL
R5462
5.23K
CPUIMVP_ISNS2G_P
0.1UF
V+
7
IN
PLACE_NEAR=U5460.5:3MM
LOADISNS:YES
R5468
104 103 50 49 7
LOADISNS:YES
=PP3V3_S0_IMVPISNS
2
LOADISNS:YES
PLACE_NEAR=R7550.3:5MM
SIGNAL_MODEL=EMPTY
LOADISNS:YES
V across Rsense: 51.5 mV
50 7
5.23K
CPUIMVP_ISNS1G_P
3.0.0
BRANCH
PAGE
54 OF 132
SHEET
50 OF 105
1
A
8
7
6
5
4
3
2
1
Thermal Sensor A:
GPU Proximity, GPU Die, Left Heat Pipe, Right Fin Stack
I2C Write: 0x98, I2C Read: 0x99
R5550
=PP3V3_S0_GPUTHMSNS
7
1
47
PP3V3_S0_GPUTHMSNS_R
2
MIN_LINE_WIDTH=0.38 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
5%
1/20W
MF
201
D
101 81
Thermal Diode: GPU Die
10%
10V
X7R-CERM
0201
101
U5550
2
NOSTUFF
2
2
1
CRITICAL
PLACE_SIDE=BOTTOM
3
101
C5503
22PF
NOSTUFF
PLACE_NEAR=Q5501.3:5MM
10K
2
5%
1/20W
MF
201
2
DFN
2
DP1
THERM*/ADDR
7
GPUTHMSNS_THM_L
3
DN1
ALERT*
8
GPUTHMSNS_ALERT_L
4
PLACE_NEAR=Q5503.3:5MM
1
5%
50V
CERM
402
D
R5552
DP2
SMDATA
9
=I2C_GPUTHMSNS_SDA
BI
48
5
GPU_TDIODE_N
BI
PLACE_NEAR=U5550.3:5MM
GPUTHMSNS_D_P
Q5501
BC846BMXXH
SOT732-3
1
10K
5%
1/20W
MF
201
EMC1414
DN2
SMCLK
10
=I2C_GPUTHMSNS_SCL
BI
48
SIGNAL_MODEL=EMPTY
101 81
22PF
R5551 1
VDD
1
2200PF
C5501
10%
10V
X5R-CERM
0201
1
C5510
PLACE_NEAR=Q5501.2:5MM
C5550
0.1UF
2
GPU_TDIODE_P
BI
Placement Note:
None.
1
1
2
5%
50V
CERM
402
3
C5552
Q5503
CRITICAL
PLACE_NEAR=Q5503.2:5MM
GPUTHMSNS_D_N
10%
10V
X7R-CERM
0201
BC846BMXXH
SOT732-3
2
1
GND
2200PF
1
THRM_PAD
6
2
Thermal Sensor: GPU Proximity
SIGNAL_MODEL=EMPTY
PLACE_NEAR=U5550.5:5MM
Thermal Diode: Right Fin Stack
Placement Note:
Place U5550 on bottom side under GPU
Thermal Diode: Left Heat Pipe
Placement Note:
Place Q5501 on the bottom side,
close to the Right Fin Stack.
PLACE_SIDE=BOTTOM
11
Placement Note:
Place Q5503 under the Left Heat Pipe,
near GPU.
C
C
Thermal Sensor B:
CPU Proximity, Memory Proximity, T29/PCH Proximity, LVDS Proximity (Airflow)
I2C Write: 0x98, I2C Read: 0x99
R5570
=PP3V3_S0_CPUTHMSNS
7
1
47
PP3V3_S0_CPUTHMSNS_R
2
MIN_LINE_WIDTH=0.38 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
5%
1/16W
MF-LF
402
101
Thermal Diode: Memory Proximity
1
C5505
22PF
NOSTUFF
2
5%
50V
CERM
402
1
Q5505
1
BC846BMXXH
SOT732-3
BC846BMXXH
SOT732-3
22PF
NOSTUFF
B
2
2
1
CRITICAL
PLACE_SIDE=BOTTOM
3
101
10%
50V
CERM 2
402
U5570
1
R5572
10K
10K
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
2 402
EMC1414
DFN
CPUTHMSNS_D1_N
C5504
22PF
2
5%
50V
CERM
402
1
BC846BMXXH
SOT732-3
PLACE_NEAR=U5570.5:5MM
Thermal Diode: LVDS Prox (Airflow)
CPUTHMSNS_THM_L
ALERT*
8
CPUTHMSNS_ALERT_L
DP2
SMDATA
9
=I2C_CPUTHMSNS_SDA
BI
48
DN2
SMCLK
10
=I2C_CPUTHMSNS_SCL
BI
48
GND
6
THRM_PAD
11
PLACE_SIDE=BOTTOM
Thermal Sensor: CPU Proximity
B
Placement Note:
Place U5570 on bottom side under CPU
Thermal Diode: T29/PCH Proximity
Placement Note:
Place Q5502 on the bottom side,
close to the LVDS connector.
1
10%
50V
CERM 2
402
CRITICAL
PLACE_NEAR=Q5504.2:5MM
CPUTHMSNS_D2_N
C5590
0.0022uF
SIGNAL_MODEL=EMPTY
2
7
DN1
PLACE_NEAR=U5570.4:5MM
3
Q5504
THERM*/ADDR
3
PLACE_NEAR=U5570.3:5MM
DP1
5
CRITICAL
2
4
NOSTUFF
PLACE_NEAR=Q5502.3:5MM
1
0.0022uF
SIGNAL_MODEL=EMPTY
2
PLACE_NEAR=Q5504.3:5MM
1
5%
50V
CERM
402
C5571
CPUTHMSNS_D2_P
Q5502
C5502
R55711
1
VDD
101
101
0.1uF
CPUTHMSNS_D1_P
3
PLACE_NEAR=Q5505.2:5MM
PLACE_NEAR=Q5502.2:5MM
C5570
20%
10V
2 CERM
402
PLACE_NEAR=U5570.2:5MM
PLACE_NEAR=Q5505.3:5MM
Placement Note:
Place Q5505 on the right side of the DIMM
connector.
1
Placement Note:
Place between the T29 and PCH.
Place side is either side.
Thermal Sensor: T29 Die
TP_TBT_THERMDP
TBT_THERMDP
MAKE_BASE=TRUE
1
R5520
10K
2
A
1
2
TBT_THERMDN
NOSTUFF
SYNC_MASTER=J31_YONAS
PLACE_SIDE=BOTTOM
XW5520
SM
5%
1/16W
MF-LF
402
PAGE TITLE
SYNC_DATE=09/08/2011
Thermal Sensors
PLACE_NEAR=U3600.B1:2mm
DRAWING NUMBER
Note: Use GND pin B1 on U3600 for N leg.
Apple Inc.
051-9585
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
3.0.0
BRANCH
PAGE
55 OF 132
SHEET
51 OF 105
1
A
8
7
6
5
4
3
2
1
D
D
C
Left Fan
7
7
C
Right Fan
=PP5V_S0_FAN_LT
=PP3V3_S0_FAN_LT
7
7
=PP5V_S0_FAN_RT
=PP3V3_S0_FAN_RT
CRITICAL
CRITICAL
J5650
R5650
1
47K
5%
1/16W
MF-LF
402 2
R5655
45
OUT
SMC_FAN_0_TACH
1
47K
2
6
FAN_LT_TACH
J5660
78171-0004
R5660
M-RT-SM
5
47K
2
45
OUT
SMC_FAN_1_TACH
SMC_FAN_0_CTL
2
6
FAN_RT_TACH
78171-0004
M-RT-SM
5
1
2
3
4
R5661 1
6
6
100K
5%
1/16W
MF-LF
402 2
IN
47K
5%
1/16W
MF-LF
402
100K
45
1
4
R5651 1
5%
1/16W
MF-LF
402 2
R5665
1
3
5%
1/16W
MF-LF
402
1
5
2N7002DW-X-G
G
SOT-363
4
S
5%
1/16W
MF-LF
402 2
Q5660
D
3
6
518S0369
FAN_LT_PWM
45
IN
SMC_FAN_1_CTL
2
Q5660
2N7002DW-X-G
G
SOT-363
1
S
D 6
6
518S0369
FAN_RT_PWM
B
B
A
SYNC_MASTER=K18_MLB
SYNC_DATE=04/27/2010
PAGE TITLE
Fan Connectors
DRAWING NUMBER
Apple Inc.
051-9585
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
3.0.0
BRANCH
PAGE
56 OF 132
SHEET
52 OF 105
1
A
8
7
6
5
PSOC USB CONTROLLER
IC
D
1.5
1
BYPASS=U5701.49:50:11 mm
BYPASS=U5701.49:50:8 mm
BYPASS=U5701.49:50:5 mm
PP3V3_S3_PSOC
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=3.3V
5%
1/16W
MF-LF
402
1
2
220K
54 6
P2_3
2
P2_1
3
P4_7
4
P4_5
5
P4_3
6
P4_1
7
P3_7
8
P3_5
9
P3_3
10
P3_1
11
P5_7
12
P5_5
13
P5_3
14
P5_1
NC
TPAD_VBUS_EN
Z2_DEBUG3
Z2_RESET
PSOC_MISO
PSOC_F_CS_L
PSOC_MOSI
PSOC_SCLK
Z2_MISO
Z2_CS_L
Z2_MOSI
Z2_SCLK
IN
54 6
54 6
54 6
54 6
54 6
54 6
54 6
54 6
54 6
CY8C24794
MLF
(SYM-VER2)
337S2983
TP_PSOC_SCL
TP_PSOC_SDA
TP_PSOC_P1_3
TP_ISSP_SCLK_P1_1
6
6
6
8
USB_TPAD_P
24
1
2
10%
16V
X7R-CERM
402
VDD
8MA (TYP) 1.5 OHM
14MA (MAX)
0.012
0.021
V
V
96E-6 W
294E-6 W
VIN
4MA (MAX) 4.7 OHM
0.0188 V
75.2E-6 W
2
2
=PP3V3_S4_TPAD
=PP3V42_G3H_TPAD
54 53 7
53 7
42
53 6
20%
6.3V
X5R
603
53 6
53 6
53 6
6 53
53 6
6 53
53 6
6 53
R5714
6 53
6 53
53
WS_KBD15_C
1
53 6
470
53 6
2
53 6
1%
1/16W
MF-LF
402
53 6
53 6
10K
6 53
41
40
39
38
37
36
35
34
33
32
31
30
29
WS_KBD17
WS_KBD16N
WS_KBD15_C
WS_KBD14
WS_KBD13
WS_KBD12
WS_KBD11
WS_KBD10
WS_KBD9
WS_KBD8
WS_KBD7
WS_KBD1
WS_KBD2
WS_KBD3
32
D
29
53 6
R5715
P2_2
P2_0
P4_6
P4_4
P4_2
P4_0
P3_6
P3_4
P3_2
P3_0
P5_6
P5_4
P5_2
P5_0
THRML
PAD
NC
30
53 6
6 53
53
WS_KBD16N
53 6
1
6
2
53 6
1%
1/16W
MF-LF
402
53
53
53 6
53 6
6 53
53 6
R5710
6 53
6 53
46 45 6
6 53
OUT
SMC_ONOFF_L
1
6 53
C5710
6 53
0.1UF
20%
10V
CERM
402
6 53
6 53
6 53
1
1K
5%
1/16W
MF-LF
402
53 6
2
6
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
53 6
53 6
2
28
WS_KBD1
WS_KBD2
WS_KBD3
WS_KBD4
WS_KBD5
WS_KBD6
WS_KBD7
WS_KBD8
WS_KBD9
WS_KBD10
WS_KBD11
WS_KBD12
WS_KBD13
WS_KBD14
WS_KBD15_CAP
WS_KBD16_NUM
WS_KBD17
WS_KBD18
WS_KBD19
WS_KBD20
WS_KBD21
WS_KBD22
WS_KBD23
WS_KBD_ONOFF_L
53 6
3
WS_LEFT_SHIFT_KBD
WS_LEFT_OPTION_KBD
WS_CONTROL_KBD
C
2
1
PLACEMENT_NOTE=NEAR J5713
NC
6 53
31
F-RT-SM
6 53
FF14-30A-R11B-B-3H
57
J5713
CRITICAL
518S0637
6 53
6 53
6 53
8
101
95
25
Z2_CLKIN
TP_P7_7
USB_TPAD_R_P
6 54
6
SMC Manual Reset & Isolation
(PP3V3_S3_PSOC)
24
1
PSOC
ISSP SDATA/I2C SDA
1
R5702
USB_TPAD_N
36E-3 W
0.72E-3 W
6
5%
1/16W
MF-LF
402
95 8
V
V
C5706
WS_KBD4
WS_KBD5
WS_KBD6
TP_ISSP_SDATA_P1_0
ISSP SCLK/I2C SCL
R5701
95 8
0.6
0.012
43
45
46
44
47
48
49
50
51
U5701
15
54 6
CRITICAL
OMIT
P1_7
P1_5
17 P1_3
18 P1_1
19 VSS
20 D+
21 D22 VDD
23
P7_7
24
P7_0
25
P1_0
26
P1_2
27
P1_4
28
P1_6
1
WS_CONTROL_KEY
Z2_KEY_ACT_L
53
P2_5
P2_7
P0_1
P0_3
P0_5
P0_7
VSS
VDD
P0_6
P0_4
P0_2
P0_0
P2_6
P2_4
56
53
1
WS_KBD23
WS_KBD22
WS_KBD21
WS_KBD20
WS_KBD19
WS_KBD18
52
53
60MA (MAX)
10 OHM
60MA (MAX) 0.2 OHM
53 6
53
54 6
C
2
VDD
VOUT
1
Keyboard Connector
0.255E-6 W
16.32E-6 W
4.7UF
C5705
0.1UF
5%
50V
CERM
402
2.55 KOHM 0.0255 V
0.204 V
2
54
53
POWER
10UA
80UA
53 6
55
54 6
74
1
=PSOC_WAKE_L
PICKB_L
BUTTON_DISABLE
Z2_HOST_INTN
WS_LEFT_SHIFT_KEY
WS_LEFT_OPTION_KEY
OUT
V_SNS
2
16
46
C5704
100PF
R5703 1
5%
1/16W
MF-LF
402
R_SNS
V+
3V3 LDO
USB INTERFACES TO MLB
SPI HOST TO Z2
TRACKPAD PICK BUTTONS
KEYBOARD SCANNER
R5704
2
CURRENT
TMP102
PLACE_SIDE=BOTTOM
=PP3V3_S4_TPAD
PIN NAME
3
18V BOOSTER
54 53 7
4
101
95
25
C5702
1
100PF
USB_TPAD_R_N
2
5%
1/16W
MF-LF
402
5%
50V
CERM
402
C5703
1
0.1UF
2
10%
16V
X7R-CERM
402
C5701
4.7UF
2
Left shift, option & control keys combined with power button cause SMC RESET# assertion.
20%
6.3V
X5R
603
BYPASS=U5701.22:19:5 mm
BYPASS=U5701.22:19:8 mm
BYPASS=U5701.22:19:11
Keys ANDed with MSP power to isolate when MSP is not powered. No IPD on OE input pin PP3V3_S4 (symbol error).
53 7
=PP3V42_G3H_TPAD
mm
B
1
B
C5750
10
0.1UF
CRITICAL
2
VDD
TPAD Buttons Disable
10%
16V
X7R-CERM
402
U5750
SLG4AP021
TQFN
BUTTON_DISABLE
53
54 53 7
=PP3V3_S4_TPAD
4
OE
(IPD)
Q5701
SSM3K15FV
D
3
PLACE THESE COMPONENTS CLOSE TO J5800
THIS ASSUMES THERE’S A PP3V42_G3H PULL UP ON MLB
53 6
WS_LEFT_SHIFT_KBD
1
53 6
WS_LEFT_OPTION_KBD
2
53 6
WS_CONTROL_KBD
3
CRITICAL
SMC_LID
WS_LEFT_SHIFT_KEY
53
8
WS_LEFT_OPTION_KEY
53
OUT_3
IN_2
G
S
2
THE TPAD BUTTONS WILL BE DISABLE
WHEN THE LID IS CLOSED
LID OPEN = & gt; SMC_LID_LC ~ 3.42V
LID CLOSE = & gt; SMC_LID_LC & lt; 0.50V
IN_3
7
WS_CONTROL_KEY
53
(IPD)
OUT_ALL#
5
GND
6
Pull-up in U5010.
SMC_TPAD_RST_L
OUT
46
THRM
PAD
11
IN
9
OUT_2
(IPD)
1
64 46 45
OUT_1
IN_1
(IPD)
SOD-VESM-HF
A
SYNC_MASTER=J30_MLB
SYNC_DATE=06/10/2011
PAGE TITLE
WELLSPRING 1
DRAWING NUMBER
Apple Inc.
051-9585
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
3.0.0
BRANCH
PAGE
57 OF 132
SHEET
53 OF 105
1
A
8
7
6
5
4
3
2
1
BOOSTER +18.5VDC FOR SENSORS
BOOSTER DESIGN CONSIDERATION:
- POWER CONSUMPTION
- DROOP LINE REGULATION
- RIPPLE TO MEET ERS
- 100-300 KHZ CLEAN SPECTRUM
- STARTUP TIME LESS THAN 2MS
- R5812,R5813,C5818 MODIFIED
D
D
TPAD:Z2
CRITICAL
TPAD:Z2
CRITICAL
L5801
PP5V_S4_P18V5S5
R5805
=PP5V_S5_TPAD
2
P18V5S4_SW
2
A
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
SWITCH_NODE=TRUE
VLF3010AT-SM-HF
B0520WSXG
C5818
1
1
5%
50V
U5805
1
L
3
DO
2
CERM
402
FB
4
5
2
2.2UF
10%
16V
10%
2
16V
THRML
X5R
603
PAD
9
2
PGND
0.1UF
X7R-CERM
402
C5817
1
6 54
SW
R5811
100K
2
1
2
1%
1/16W
MF-LF
402
PP18V5_Z2
M-ST-SM
C5815
2
4
3
6
5
8
7
10
9
12
11
14
13
16
15
18
17
20
19
22
6 54
1
21
1000PF
10%
25V
X5R
603-1
R5813
55560-0228
=PP3V3_S4_TPAD
53 7
2
2
5%
25V
NP0-C0G
402
53 6
53 6
71.5K
TPAD:Z2
1
8
TPAD:Z2
1
1UF
TPAD:Z2
GND
1
IPD Flex Connector
J5800
TPAD:Z2
C5819
Z2_BOOST_EN
6
1
TPAD:Z2
CRITICAL
7
C5816
NC
6 54
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=18.5V
CRITICAL
1%
1/16W
MF-LF
402
P18V5S4_FB
CTRL
TPAD:Z2
QFN-1
TPAD:Z2
PP18V5_Z2
2
R5812
TPS61045
TPAD:Z2
0
5%
1/16W
MF-LF
402
1M
39PF
VIN
1
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=18.5V
TPAD:Z2
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=5V
5%
1/16W
MF-LF
402
PP18V5_S4_R
K
PP5V_S5_P18V5S5_VIN
1
R5806
SOD-323
2
7
0
1
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=5V
TPAD:Z2
D5802
3.3UH-870MA
53 6
1%
1/16W
MF-LF
402
53 6
53 6
54 6
53 6
6
Z2_CS_L
Z2_DEBUG3
Z2_MOSI
Z2_MISO
Z2_SCLK
Z2_BOOST_EN
Z2_HOST_INTN
PP5V_S5_CUMULUS
VOLTAGE=5V
MIN_NECK_WIDTH=0.20MM
MIN_LINE_WIDTH=0.50MM
53 6
Z2_CLKIN
Z2_KEY_ACT_L
Z2_RESET
PSOC_F_CS_L
PICKB_L
PSOC_MISO
PSOC_MOSI
PSOC_SCLK
=I2C_TPAD_SDA
=I2C_TPAD_SCL
6 53
6 53
6 53
6 53
6 53
6 53
6 53
48
48
C
C
516S0689
NOSTUFF
L5800
FERR-120-OHM-1.5A
1
PIN 21 IS NC ON CUMULUS FLEX
2
0402-LF
NOSTUFF
1
PIN 18 IS NC ON Z2 FLEX
PLACE_NEAR=J5800.18:3MM
C5800
0.1UF
PLACE_NEAR=J5800.18:3MM
2
20%
10V
CERM
402
Keyboard Backlight Driver & Detection
7
=PP5V_S0_KBDLED
CRITICAL
Keyboard Backlight Connector
B
L5850
7
=PP3V3_S0_TPAD
1
2
5%
1/16W
MF-LF
402
BI
X5R
402-1
2
SMC_SYS_KBDLED
2
SW
LED
CTRL
2
R5853 always stuffed, R5854 only
grounded when KB BL flex connected.
R5854
5
6
DFN
2
5%
1/16W
MF-LF
402
CAP
4
R5855
518S0691
1%
1/16W
MF-LF
402
KBDLED_CAP
4
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.25 MM
THRML
GND
2
10K
KBDLED_ANODE
10
LT3491
NO STUFF
J5815 pin 1 is grounded
on keyboard backlight flex
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM
U5850
5%
1/16W
MF-LF
402
R5852 1
1
3
1
4.7K
If LOW, keyboard backlight present
If HIGH, keyboard backlight not present
SMC_KDBLED_PRESENT_L
3
CRITICAL
OMIT_TABLE
1
F-RT-SM
6
2
6
To detect Keyboard backlight, SMC will
tristate and read SMC_SYS_KBDLED:
FF18-4A-R11AD-B-3H
VIN
10%
PAD
1
7
45
1
1UF
10V
J5815
1
C5850
470K
KBDLED_SW
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.25 MM
SWITCH_NODE=TRUE
1098AS-SM
R5853 1
B
CRITICAL
10UH-0.58A-0.35OHM
C5855
1
0.47UF
2
2
10%
50V
CERM-X5R
0603
C5856
0.47UF
2
10%
50V
CERM-X5R
0603
PART NUMBER
353S3085
QTY
1
DESCRIPTION
IC,STLA02,1-STRING LED DRIVER,2X2DFN-6
REFERENCE DES
CRITICAL
U5850
BOM OPTION
CRITICAL
(SMC_KBDLED_PRESENT_L)
A
SYNC_MASTER=J31_LINDA
SYNC_DATE=07/01/2011
PAGE TITLE
WELLSPRING 2
DRAWING NUMBER
Apple Inc.
051-9585
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
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1
A
8
7
6
5
4
3
2
1
D
D
7
=PP3V3_S3_SMS
BYPASS=U5920.14:13:8 mm
1
C
20%
6.3V
X5R
603
C5922
0.1UF
2
2
VDD
10%
6.3V
X5R
201
R5924 1
BYPASS=U5920.14:13:8 mm
NC
NC
10K
5%
1/20W
MF
201
45
OUT
1
1
10UF
14
CRITICAL
C5926
3
NC
U5920
LGA
CS
9
2
2
SDO
SDA/SDI/SDO
SCL/SPC
INT1
INT2
0
1
7
6
4
SMS_ADDR_SELECT
I2C_SMC_SMS_SDA_R
I2C_SMC_SMS_SCL_R
=I2C_SMC_SMS_SDA
BI
=I2C_SMC_SMS_SCL
IN
48
R5922
R5921 1
16
13
5
2
5%
1/20W
MF
201
GND
12
C
R5923
SMS_I2C_SEL
RESERVED
2
11
8
5%
1/20W
MF
201
NOSTUFF
10K
5%
1/20W
MF
201
LIS331DLH
15
R5925 1
10K
10
SMS_INT_L
TP_SMS_INT2
R5920 1
VDD_IO
2
0
1
2
10K
338S0687
5%
1/20W
MF
201
PLACEMENT_NOTE=See schematic for orientation.
2
48
5%
1/20W
MF
201
SMS_ADDR_SELECT=0 Addr: 0x30(Wr)/0x31(Rd)
SMS_ADDR_SELECT=1 Addr: 0x32(Wr)/0x33(Rd)
Desired orientation when
placed on board bottom-side (view thru top):
NOTE: SDA and SCL have internal pull-ups to VDD_IO.
+Y
Front of system
+X
+Z (dn)
B
B
Circle indicates pin 1 location when placed
in correct orientation
A
SYNC_MASTER=J31_YONAS
SYNC_DATE=08/11/2011
PAGE TITLE
Digital Accelerometer
DRAWING NUMBER
Apple Inc.
051-9585
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
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1
A
8
7
6
5
4
3
2
1
D
D
C
C
=PP3V3_SUS_ROM
1
R6101
3.3K
2
C6100
8
7
1
20%
10V
CERM
402
CRITICAL
VDD
0.1UF
5%
1/16W
MF-LF
402
2
U6100
64MBIT
47 46
IN
SPI_MLB_CLK
6
SOIC
SCK
SI
5
SPI_MLB_MOSI
IN
46 47
SO
2
SPI_MLB_MISO
OUT
46 47
SST25VF064C
47 46
47 19 6
IN
IN
SPI_MLB_CS_L
SPI_WP_L
SPIROM_USE_MLB
1
3
7
CE*
WP*
HOLD*
OMIT
VSS
4
NOTE: If HOLD* is asserted
ROM will ignore SPI cycles.
B
B
A
SYNC_MASTER=K91_BEN
SYNC_DATE=06/08/2010
PAGE TITLE
SPI ROM
DRAWING NUMBER
Apple Inc.
051-9585
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
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1
A
8
7
6
5
4
3
2
1
AUDIO CODEC
APPLE P/N 353S3199
CRITICAL
L6201
=PP5V_S0_AUDIO
8 57
=PP3V3_S0_AUDIO
7 57 62 63
FERR-220-OHM
PP1V5_S0_AUDIO_DIG
0402
VOLTAGE=1.5V
MIN_LINE_WIDTH=0.30MM
MIN_NECK_WIDTH=0.20MM
CRITICAL
1
C6210
4.7UF
Replacing 2 0402s with one 0306
Low ESL cap
2
PP4V5_AUDIO_ANALOG
20%
6.3V
X5R
0306
CRITICAL
CRITICAL
C6219
GND_AUDIO_HPAMP
PP4V5_AUDIO_ANALOG
IN
C6218
20%
16V 2
TANT-POLY
2012-LLP
1
1
1
R6210
2
1%
1/16W
MF-LF
402
2
20%
10V
X5R-CERM
0402-1
MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM
10UF
C6221
10UF
2.67K
C6220
VBIAS_DAC
20%
10V
X5R-CERM
0402-1
2
VD VA_REF VA_HP VA
VBIAS_DAC
CRITICAL
HPOUT_L
VHP_FILT+
VHP_FILTU6201 HPOUT_R
CS4206B
HPREF
29
VHP_FILTP
44
VHP_FILTM
10%
16V
X5R
402-1
41
10%
10V
X5R
402-1
1CRITICAL
1
C6217
0.1UF
9
63 57
C6215
1
1UF
10UF
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
60 59 57
25
D
C6216
1
46
=PP1V5_S0_AUDIO
IN
2
24
7
1
10UF
2
2
C6214
0.1UF
10%
16V
X5R
402-1
2
1
1
AUD_DMIC_SDA1
NC_AUD_GPIO_1
NC_AUD_GPIO_2
2
2
0.1UF
10UF
10%
16V
2
X5R
402
20%
16V
TANT-POLY
2012-LLP
X5R-CERM
0402-1
GND_AUDIO_HPAMP
MIN_LINE_WIDTH=0.30MM
MIN_NECK_WIDTH=0.20MM
MIN_NECK_WIDTH=0.20MM
AUD_HP_PORT_L
AUD_HP_PORT_R
OUT
MIN_LINE_WIDTH=0.30MM
39
MIN_LINE_WIDTH=0.30MM
MIN_NECK_WIDTH=0.20MM
HPAMP_REF
IN
15
13
63
31
FLYP
FLYC
FLYN
LINEOUT_L2+
LINEOUT_L2LINEOUT_R2+
LINEOUT_R2-
MICBIAS
AUD_SENSE_A
IN
SENSE_A
16
VCOM
Control for spk amps.
28
CS4206_FLYP
CS4206_FLYC
1
VL_HD - supply for HDA interface
1
2
C6222
2
C6223
43
2.2UF
42
2.2UF
20%
6.3V
VL_IF - supply for GPIO, S/PDIF and DMIC
20%
6.3V
CERM
CERM
402-LF
34
36
37
30
32
33
1
96 16
IN
HDA_BIT_CLK
IN
VL_IF
OUT
HDA_SDIN0
LINEIN_L+
LINEIN_CLINEIN_R+
96 16
IN
62
HDA_SDOUT
HDA_RST_L
AUD_SPDIF_IN
IN
96 16
39
IN
2
96
AUD_SDI_R
5%
1/16W
MF-LF
402
VREF+_ADC
AUD_LI_P_L
AUD_LI_REF
AUD_LI_P_R
18
27
SDI
SDO
8
5
RESET*
11
SPDIF_IN
SPDIF_OUT
47
AUD_SPDIF_OUT_CHIP
22
23
48
AUD_MIC_INP_L
AUD_MIC_INN_L
AUD_MIC_INP_R
AUD_MIC_INN_R
17
19
20
DMIC_SCL
5%
1/16W
MF-LF
402
AUD_DMIC_CLK
4
61 101
OUT
61 101
OUT
61 101
OUT
61 101
BI
Feeding into Woofer amp LO1_R only
Feeding into Tweeter amps
63
IN
58
IN
58
IN
63
IN
63
IN
63
IN
C
58
IN
63
OUT
62
26
7
DGND THRM_PAD AGND
CRITICAL
C6224
CRITICAL
1
1
1UF
GND_AUDIO_HPAMP
60 59 57
C6225
10UF
10%
20V 2
TANT
CASE-P3-HF
63 58 57
OUT
MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM
2
49
1
61 101
CS4206_VREF_ADC
39
AUD_SPDIF_OUT
OUT
61 101
OUT
MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM
R6212
62
OUT
SYNC
10
R6211
CS4206_VCOM
21
MICIN_L+
MICIN_LMICIN_R+
MICIN_R-
BITCLK
6
1
60 62
59
VCOM - filter connection for internal quiescent voltage
HDA_SYNC
96 16
AUD_CODEC_MICBIAS
60 62
VL_HD
CS4206_FLYN
96 16
AUD_LO2_L_P
AUD_LO2_L_N
AUD_LO2_R_P
AUD_LO2_R_N
OUT
402-LF
3
C
NC_AUD_LO1_LP
NC_AUD_LO1_LN
AUD_LO1_R_P
AUD_LO1_R_N
35
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.2MM
57 58 63
40
LINEOUT_L1+
LINEOUT_L1LINEOUT_R1+
LINEOUT_R1-
14
OUT AUD_GPIO_3
57 59 60
38
GPIO0/DMIC_SDA1
GPIO1/DMIC_SDA2
/SPDIF_OUT2
GPIO2
GPIO3
2
12
D
CRITICAL
20%
10V
GND_AUDIO_CODEC
45
61
IN
57 63
C6213
QFN
62
IN
1
2
20%
16V
POLY-TANT
CASE-B2-SM
1
R6213
100K
5%
1/16W
MF-LF
2 402
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=0V
GND_AUDIO_CODEC
B
B
4.5V POWER SUPPLY FOR CODEC
APPLE P/N 353S2234
CRITICAL
CRITICAL
L6200
FERR-220-OHM
57 8
IN
=PP5V_S0_AUDIO
=PP3V3_S0_AUDIO
2.21K
1
1
4V5_REG_EN
2
1%
1/16W
MF-LF
402
NOTES ON CODEC usage
MAX8840-4.5V
4V5_REG_IN
IN
UDFN
OUT
BP
4
NC
5
PP4V5_AUDIO_ANALOG
6
OUT
57 63
Hpamp of Codec enabled
DAC1 FSOUTPUT= 1.34VRMS
DAC2/3 FSOUTPUTDIFF= 2.67VRMS
DAC2/3 FSOUTPUTSE= 1.34VRMS
3
SHDN*
GND
CRITICAL
1
NC
C6200
1
C6201
MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM
XW6200
SM
1
2
10%
10V
X5R
402-1
1
0.1UF
1
1UF
10%
10V
X5R
402-1
CRITICAL
C6202
CRITICAL
1UF
2
4V5_NR
2
IN
2
0402
R6202
63 62 57 7
1
MIN_LINE_WIDTH=0.40MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=4.5V
U6200
MIN_LINE_WIDTH=0.40MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=5V
C6203
1UF
2
2
10%
16V
X7R-CERM
402
10%
10V
X5R
402-1
GND_AUDIO_CODEC
2
57 58 63
A
2
5%
1/20W
MF
201
100K
DRAWING NUMBER
XW6201
SM
1
2
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
GND_AUDIO_HPAMP
Apple Inc.
57 59 60
VOLTAGE=0V
NOTICE OF PROPRIETARY PROPERTY:
7
6
051-9585
5
4
3
2
SIZE
D
REVISION
R
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
SYNC_DATE=10/26/2011
AUDIO: CODEC/REGULATOR
1
R6203
SYNC_MASTER=J31_AUDIO
PAGE TITLE
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1
A
8
7
6
5
4
3
2
1
D
D
LINE INPUT VOLTAGE DIVIDER
CODEC RIN = 20K OHMS
NET RIN = 18K OHMS
FC = 0.36 HZ
VIN = 2VRMS, CODEC VIN = 1.14 VRMS
CRITICAL
C6300
R6300
62
AUD_LI_L
IN
1
7.87K
MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM
22UF
AUD_LI_L_DIV
2
2
1
MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM
1%
1/16W
MF-LF
402
AUD_LI_P_L
MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM
OUT
57
20%
10V
TANT
SM-HF-PL
C
C
R6301 1
21.5K
1%
1/16W
MF-LF
402 2
CRITICAL
C6302
22UF
62
IN
AUD_LI_GND
2
1
MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM
1
AUD_LI_REF
MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM
OUT
57
20%
10V
TANT
SM-HF-PL
R6303
10
1%
1/16W
MF-LF
2 402
63 57
IN
GND_AUDIO_CODEC
R6305 1
21.5K
B
B
1%
1/16W
MF-LF
402 2
CRITICAL
C6303
R6306
62
IN
AUD_LI_R
MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM
22UF
7.87K
1
AUD_LI_R_DIV
2
2
1
MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM
1%
1/16W
MF-LF
402
AUD_LI_P_R
MIN_LINE_WIDTH=.1MM
MIN_NECK_WIDTH=.1MM
OUT
57
20%
10V
TANT
SM-HF-PL
A
SYNC_MASTER=J31_AUDIO
SYNC_DATE=10/26/2011
PAGE TITLE
AUDIO: LINE INPUT FILTER
DRAWING NUMBER
Apple Inc.
051-9585
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
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A
8
7
6
5
4
3
2
1
EXTERNAL (HEADSET) MIC INPUT CIRCUITRY
D
D
APN: 353S3066 as of JUly 2011
U6400 should get VDD from battery. Should be powered all the time.
CRITICAL
L6400
FERR-220-OHM
=PP3V42_G3H_AUDIO
1
7
2
VOLTAGE=3.42V
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.175 MM
PP3V42_G3H_CHS
0402
C6410
1
10UF
20%
6.3V
2 CERM-X5R
0402-1
C6400
1
0.1UF
2
10%
16V
X5R
402
C6405
10UF
2
20%
6.3V
CERM-X5R
0402-1
CHS_CLAMPI
A1
1
VDD
R6403
U6400
TS3A8235YFP
1
WCSP
C
RAMPI
62
IN
B4
1
2.21K
R6401
2
1
1%
1/16W
MF-LF
402
1.02K
2
EXT_MIC_BIAS
IN
C
EXT_MIC_P
OUT
AUD_HS_MIC1_HI
63
1%
1/16W
MF-LF
402
D3
C4
CLAMPO
MIN_NECK_WIDTH=0.05MM
R6402
2
1%
1/16W
MF-LF
402
D4
RAMPO
CLAMPI
MIN_LINE_WIDTH=0.1MM
2.21K
63
CHS_CLAMPO
NOSTUFF
5%
50V
CERM
402
SCL
SDA
ADDR
2
AUD_HS_MIC2_HI
C3
B3
IN
62
IN
1
C6402
10UF
20%
6.3V
2 CERM-X5R
0402-1
A3
A4
A2
1
C6401
TO MIKEY & FILTER
10UF
20%
6.3V
2 CERM-X5R
0402-1
EXT_MIC_REF
OUT
63
R6404
MIN_LINE_WIDTH=0.1MM
MIN_NECK_WIDTH=0.05MM
GND
62
D2
D1
NOSTUFF
0
1
CHS_CAP_REF
IN
MIC
REF
GND2
GND1
62
B1 MIC1
C1 MIC2
1
33PF
2
5%
1/16W
MF-LF
402
B2
C2
FROM HEADSET
C6416
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM
AUD_HS_MIC2_RET
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM
AUD_HS_MIC1_RET
R6406
CHS_SCL
1
0
2
HS_SCL
2
HS_SDA
IN
63
5%
1/16W
MF-LF
402
CHS_SDA
R6405
60 57
0
GND_AUDIO_HPAMP
1
R6407
2
1
5%
1/16W
MF-LF
402
0
BI
63
5%
1/16W
MF-LF
402
B
B
XW6400
SM
1
HPAMP_REF
2
OUT
57
I2C ADDRESSES: CHS uses SMBus 0 connections
CHS
U6400
READ
0111
0111
0x77
CHS
U6400
WRITE
0111
0110
0x76
A
SYNC_MASTER=J31_AUDIO
SYNC_DATE=10/26/2011
PAGE TITLE
AUDIO: DETECT/MIC BIAS
DRAWING NUMBER
Apple Inc.
051-9585
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
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REVISION
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64 OF 132
SHEET
59 OF 105
1
A
8
7
6
5
4
3
2
1
D
D
ZOBEL NETWORK & 1ST ORDER DAC FILTER PLACEHOLDER
62 57
IN
AUD_HP_PORT_L
CRITICAL
C6500
1
0.1UF
10%
16V
2
X7R-CERM
402
AUD_HP_ZOBEL_L
C
C
1
R6500
39
5%
1/16W
MF-LF
402
2
59 57
IN
GND_AUDIO_HPAMP
1
R6510
39
5%
1/16W
MF-LF
402
2
AUD_HP_ZOBEL_R
CRITICAL
C6510
1
0.1UF
10%
16V
X7R-CERM
2
402
62 57
IN
AUD_HP_PORT_R
B
B
A
SYNC_MASTER=J31_AUDIO
8
7
6
5
4
3
2
SYNC_DATE=10/26/2011
1
A
8
7
6
5
4
3
2
3X MONO SPEAKER AMPLIFIERS (SSM2375)
1
Gain Pin
Gain dB
Connect to VDD
6
Connect to VDD through 47k
12
1ST ORDER FC (L & R) = ~737 HZ
Not connected
3
1ST ORDER FC (SUB) = ~90 HZ
Connect to GND through 47k
9
Connect to GND
0
APN: 353S2958 as of July 2011
GAIN = +3 DB
Rin=80k irrespective of gain
D
D
PLACE C6611 CLOSE TO VDD PIN
8
PP5V_S0_AUDIO_AMP_L
CRITICAL
L6610
1
0.0027UF
2
0402
1
AUD_SPKRAMP_LIN_P
NO_TEST=TRUE
CRITICAL
101 57
61
MIN_NECK_WIDTH=0.20 MM
AUD_SPKRAMP_LIN_N
NO_TEST=TRUE
IN+
IN-
OUT+
OUT-
OUT
6 62 101
C3
SD*
GAIN
A3
EDGE
A1
B2
B3
MIN_LINE_WIDTH=0.50 MM
A2
2
10%
50V
CERM
402
MIN_NECK_WIDTH=0.20 MM
NC
SPKRCONN_L_OUT_N
GND
5%
1/16W
MF-LF
402 2
FERR-1000-OHM
IN
B1
SSM2375L_P
SSM2375L_N
100K
L6601
1
6 62 101
R6600 1
CRITICAL
AUD_GPIO_3
OUT
WLCSP
101
1
SPKRCONN_L_OUT_P
SSM2375
101
AUD_SPKRAMP_SHUTDOWN_L
57
MIN_LINE_WIDTH=0.50 MM
U6610
0.0027UF
0402
10%
16V
X5R
402-1
VDD
C6614
2
2
CRITICAL
CRITICAL
1
AUD_LO2_L_N
IN
2
C6611
0.1UF
10%
50V
CERM
402
L6611
FERR-1000-OHM
1
20%
6.3V 2
TANT-POLY
CASE-A4
C1
AUD_LO2_L_P
IN
TWEETER with HPF FC=737Hz
CRITICAL
1
47UF
C6613
FERR-1000-OHM
101 57
C6612
CRITICAL
C2
CRITICAL
2
0402
C
C
PLACE C6621 CLOSE TO VDD PIN
61 8
PP5V_S0_AUDIO_AMP_R
CRITICAL
C6622
FERR-1000-OHM
IN
AUD_LO2_R_P
0.0027UF
2
1
AUD_SPKRAMP_RIN_P
NO_TEST=TRUE
0402
CRITICAL
AUD_LO2_R_N
1
61
MIN_NECK_WIDTH=0.20 MM
SPKRCONN_R_OUT_P
101
B1
SSM2375R_P
SSM2375R_N
A1
A2
1
IN+
IN-
OUT+
OUT-
6 62 101
OUT
6 62 101
C3
SD*
GAIN
A3
EDGE
101
0.0027UF
AUD_SPKRAMP_RIN_N
NO_TEST=TRUE
OUT
WLCSP
C6624
0402
MIN_LINE_WIDTH=0.50 MM
SSM2375
CRITICAL
2
10%
16V
X5R
402-1
VDD
2
10%
50V
CERM
402
FERR-1000-OHM
IN
2
U6620
L6621
101 57
CRITICAL
B2
2
B3
MIN_LINE_WIDTH=0.50 MM
MIN_NECK_WIDTH=0.20 MM
NC
SPKRCONN_R_OUT_N
GND
10%
50V
CERM
402
C1
101 57
1
20%
6.3V 2
TANT-POLY
CASE-A4
C6623
C6621
0.1UF
47UF
CRITICAL
L6620
1
C2
CRITICAL
TWEETER with HPF FC=737Hz
CRITICAL
1
AUD_SPKRAMP_SHUTDOWN_L
R6601 1
100K
B
B
5%
1/16W
MF-LF
402 2
PLACE C6631 CLOSE TO VDD PIN
61 8
PP5V_S0_AUDIO_AMP_R
WOOFER with HPF FC=90Hz
CRITICAL
CRITICAL
IN
AUD_LO1_R_P
1
2
0402
AUD_SPKRAMP_SUBIN_P
NO_TEST=TRUE
1
C6631
0.1UF
2
VDD
10%
16V
X5R
402-1
MIN_LINE_WIDTH=0.50 MM
MIN_NECK_WIDTH=0.20 MM
SPKRCONN_S_OUT_P
SSM2375S_P
SSM2375S_N
B1
IN+
IN-
OUT+
OUT-
0402
A
1
A1
A2
0.022UF
AUD_SPKRAMP_SUBIN_N
NO_TEST=TRUE
OUT
6 62 101
C3
GAIN
A3
EDGE
101
101
2
6 62 101
WLCSP
B2
C6634
1
OUT
SSM2375
CRITICAL
FERR-1000-OHM
AUD_LO1_R_N
1
CRITICAL
U6630
10%
25V
X7R
0402
L6631
IN
20%
6.3V 2
TANT
CASE-AL1
2
CRITICAL
101 57
1
100UF
0.022UF
SD*
B3
MIN_LINE_WIDTH=0.50 MM
MIN_NECK_WIDTH=0.20 MM
NC
SPKRCONN_S_OUT_N
2
10%
25V
X7R
0402
GND
C1
101 57
C6632
C6633
L6630
C2
CRITICAL
FERR-1000-OHM
CRITICAL
SYNC_MASTER=J31_AUDIO
AUD_SPKRAMP_SHUTDOWN_L
SYNC_DATE=10/26/2011
PAGE TITLE
61
AUDIO: SPEAKER AMP
DRAWING NUMBER
Apple Inc.
051-9585
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
3.0.0
BRANCH
PAGE
66 OF 132
SHEET
61 OF 105
1
A
8
7
6
5
4
3
AUDIO JACK 1 LO/HP JACK, SPDIF TX
IN
AUD_HS_MIC1_UNFILT
1
57
CRITICAL
FERR-1000-OHM
AUD_HS_MIC1_HI
2
59
OUT
2
0402
CRITICAL
MIC CONNECTOR
SM
L6707
FERR-120-OHM-2.0A
AUD_HS_MIC2_RET
1
XW6700
1
AUD_SPDIF_OUT
L6703
Place XW on/near Jack pin
2
1
2
59
OUT
CRITICAL
0402
J6780
D
L6702
1
OUT
101 63 6
SM
XW6704
4
59
0402
2
63 62 57 7
D
M-RT-SM
AUD_HS_MIC2_HI
2
CRITICAL
63 6
L6708
101 63 6
FERR-120-OHM-2.0A
1
Place XW on/near Jack pin
CRITICAL
FERR-1000-OHM
AUD_HS_MIC2_UNFILT
78171-0003
=PP3V3_S0_AUDIO
1
OUT BI_MIC_N
1
OUT BI_MIC_SHIELD
2
OUT BI_MIC_P
3
AUD_HS_MIC1_RET
2
59
OUT
5
0402
APN: 514-0671
CRITICAL
J6700
AUD_CONNJ1_TIPDET
SPDIF-TXRX-K24
MIN_LINE_WIDTH=0.40MM
MIN_NECK_WIDTH=0.20MM
F-RT-TH
MIN_LINE_WIDTH=0.30MM
MIN_NECK_WIDTH=0.20MM
MIC
DETECT
SWITCH
LEFT
RIGHT
GND
6
AUD_CONNJ1_USMIC
AUD_CONNJ1_USGND_DET
5
MIN_LINE_WIDTH=0.40MM
MIN_NECK_WIDTH=0.20MM
CRITICAL
2
1
FERR-120-OHM-2.0A
AUD_CONNJ1_LEFT
AUD_CONNJ1_RIGHT
AUD_CONNJ1_USGND
3
4
1
AUDIO
AUD_HP_PORT_L
AUD_DMIC_SDA1
57
2
MIN_LINE_WIDTH=0.40MM
MIN_NECK_WIDTH=0.20MM
BI
OUT
57 60
POF
1
CRITICAL
11
SOD882
CRITICAL
1
13
C6700
1
C6701
0.1UF
2
10%
16V
X5R
402-1
CRITICAL
2.2UF
20%
6.3V
CERM
402-LF
2
1
1
402
CRITICAL
1
CRITICAL
2
1
10K
AUD_J1_SLEEVEDET_R
2
OUT
J6783
78171-0004
CON_DMIC_CLK
2
M-RT-SM
5
1
2
CON_DMIC_SDA
3
4
CRITICAL
L6785
=PP3V3_S0_AUDIO
1
2
C
6
600-OHM-300MA
63
63 62 57 7
CON_DMIC_PWR
0402
FERR-1000-OHM
402
6.8V-100PF
1
DIGI_MIC
L6705
DZ6700
6.8V-100PF
2
0402
5%
1/16W
MF-LF
402
ESDALC5-1BM2
2
DZ6704
2
DZ6703
1
0402
R6700
12
AUD_DMIC_CLK
L6784
DIGI_MIC
600-OHM-300MA
L6706
1
SHIELD
PINS
OUT
CRITICAL
8
SHELL
57
0402
FERR-120-OHM-2.0A
10
L6783
CRITICAL
OPERATING VOLTAGE 3.3
C
57 60
BI
0402
7
9
DIGI_MIC
CRITICAL
CRITICAL
600-OHM-300MA
AUD_HP_PORT_R
2
MIN_LINE_WIDTH=0.40MM
MIN_NECK_WIDTH=0.20MM
MIN_LINE_WIDTH=0.30MM
MIN_NECK_WIDTH=0.20MM
A - VIN
B - VCC
C - GND
DIGI_MIC
L6704
CRITICAL
2
AUD_J1_TIPDET_R
OUT
63
0402
2
CRITICAL
2
DZ6706
J6781
DZ6701
6.8V-100PF
6.8V-100PF
402
1
402
1
SPEAKER CONNECTOR
C6705
78171-0002
APN: 518S0519
M-RT-SM
3
100PF
1
2
5%
50V
CERM
402
101 61 6
MIN_LINE_WIDTH=0.50 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=0V
GND_CHASSIS_AUDIO_JACK
IN
101 61 6
8 62
IN
SPKRCONN_L_OUT_P
SPKRCONN_L_OUT_N
1
2
4
XW6701
CRITICAL
SM
1
2
J6782
78171-0004
XW6702
GND PATCH
SPEAKER CONNECTOR
SM
1
2
R6701
=PP3V3_S0_AUDIO
62 8
B
GND_CHASSIS_AUDIO_JACK
101 61 6
IN
0
101 61 6
IN
101 61 6
63 62 57 7
IN
101 61 6
IN
1
2
5%
1/16W
MF-LF
402
APN: 514-0635
M-RT-SM
5
APN: 518S0521
SPKRCONN_S_OUT_P
SPKRCONN_S_OUT_N
SPKRCONN_R_OUT_P
SPKRCONN_R_OUT_N
1
2
3
4
B
6
R6749
CRITICAL
AUD_J2_OPT_OUT
J6750
1
AUDIO-RCVR-M97
4.7
2
AUD_SPDIF_IN
5%
1/16W
MF-LF
402
F-RT-TH5
DETECT FOR PLUG TYPE
5
SWITCH
2
AUD_CONNJ2_TIPDET
LEFT
1
MIN_LINE_WIDTH=0.40MM
MIN_NECK_WIDTH=0.20MM
RIGHT
3
GROUND
4
CRITICAL
L6754
1
AUD_CONNJ2_RING
MIN_LINE_WIDTH=0.40MM
MIN_NECK_WIDTH=0.20MM
AUD_LI_R
BI
58
AUD_LI_L
BI
58
L6756
FERR-1000-OHM
6
7
1
AUD_CONNJ2_TIP
MIN_LINE_WIDTH=0.40MM
MIN_NECK_WIDTH=0.20MM
8
2
0402
CRITICAL
L6758
POF
600-OHM-300MA
9
1
AUD_CONNJ2_SLEEVE
MIN_LINE_WIDTH=0.40MM
MIN_NECK_WIDTH=0.20MM
10
CRITICAL
12
1
C6750
CRITICAL
1UF
2
AUD_LI_GND
58
1
402
SOD882
2
1
2
AUD_J2_TIPDET_R
OUT
63
0402
CRITICAL
1
DZ6756
CRITICAL
DZ6757
L6752
FERR-1000-OHM
6.8V-100PF
ESDALC5-1BM2
2
CRITICAL
2
DZ6754
2
DZ6758
10%
10V
X5R
402-1
A
2
0402-1
11
SHIELD
PINS
2
0402
CRITICAL
OPERATING VOLTAGE 3.3
SHELL
57
FERR-1000-OHM
AUDIO
A - VDD
B - GND
C - VOUT
OUT
6.8V-100PF
402
ESDALC5-1BM2
1
SOD882
SYNC_MASTER=J31_AUDIO
C6756
2
1
SYNC_DATE=10/26/2011
PAGE TITLE
100PF
1
AUDIO: JACKS
5%
50V
CERM
402
DRAWING NUMBER
GND_CHASSIS_AUDIO_JACK
Apple Inc.
8 62
051-9585
R
NOTICE OF PROPRIETARY PROPERTY:
AUDIO JACK 2 LINE IN JACK, SPDIF RX
8
7
6
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
5
4
3
2
SIZE
D
REVISION
3.0.0
BRANCH
PAGE
67 OF 132
SHEET
62 OF 105
1
A
8
7
6
5
4
3
2
CODEC OUTPUT SIGNAL PATHS
VOLUME
CONVERTER
PIN COMPLEX
HP/LINE OUT
0X02 (2)
0X02 (2)
0X09 (9,A)
NA
0X09 (Jack Detect A)
DET ASSIGNMENT
SATELLITES
0X04 (4)
0X04 (4)
0X0B (11)
GPIO_3
N/A
L6880
0X03 (3)
0X03 (03)
0X0A (10)
GPIO_3
N/A
N/A
0X08 (8)
0X10 (16)
N/A
1
=PP3V3_S0_AUDIO
0X0C (Jack detect B)
63 62 57 7
48
CODEC INPUT SIGNAL PATHS
IN
=I2C_MIKEY_SCL
0
1
CONVERTER
PIN COMPLEX
VREF
LINE IN
0X05 (5)
0X0C (12,C)
N/A
R6886
DET ASSIGNMENT
5%
1/16W
MF-LF
402
0X0C (Jack detect C)
0X0F (15)
N/A
0X0D (13)
N/A
0X06 (6)
0X0D (13,V22,B,LEFT)
MIKEY
MIKEY
2
2
2
C6887
10%
25V
X5R
402
18
OUT
24
PORT A DETECT (HEADPHONES)
IN
AUD_IPHS_SWITCH_EN
1
1
1
2
R6806
39.2K
R6804
DMC2400UV
5%
1/16W
MF-LF
402
SOT563
D
P-CH
3
AUD_J1_SLEEVEDET_R_INV
5%
1/16W
MF-LF
402
1
0
2
2
5
G
10%
16V
CERM
402
2
GND_AUDIO_CODEC
4
S
2
D
63 58 57
D1
HS_RX_BP
A3
TIPDET_UNFILT
ENABLE
CS
AUD_PORTB_DET_L
1
2
HS_MIC_HI_RC
1
2
R6888
2
220K
5%
1/16W
MF-LF
402
D
3
GND_AUDIO_CODEC
SSM6N37FEAPE
D
Place this next to Charleston
C6885
10%
X7R
C
27PF
0.0082UF
2
59
1
C6884
5%
1/16W
MF-LF
402
MIN_LINE_WIDTH=0.1MM
MIN_NECK_WIDTH=0.05MM
IN
5%
CERM
2
25V
402
50V
402
CRITICAL
CRITICAL
EXT_MIC_REF
IN
59
MIN_LINE_WIDTH=0.1MM
MIN_NECK_WIDTH=0.05MM
6
Q6801
SOT563
EXT_MIC_P
2
2
CRITICAL
SSM6N37FEAPE
59
10%
25V
X5R
402
CRITICAL
1
R6803
1
2.2K
1
0.1UF
OUT AUD_MIC_INN_L
1
5%
1/16W
MF-LF
402
100K
CRITICAL
Q6801
2
R6890
0.1UF
OUT AUD_MIC_INP_L
10%
25V
X5R
402
N-CH
57 58 63
OUT
C6883
6
S
GND_AUDIO_CODEC
CRITICAL
57
1
16V
402
1K
5%
1/16W
MF-LF
402
APN:376S0975
10%
CERM
1%
1/16W
MF-LF
402
R6814
G
20%
6.3V
TANT
402
0.01UF
2
R6805
C6886
2
2
C6881
GND_AUDIO_CODEC
63 AUD_J1_SLEEVEDET_R_BUF
AUD_J1_SLEEVEDET_R_INV
CRITICAL
C6882
2.2UF
1
HDET
B2
63
A1
5%
1/16W
MF-LF
402
220K
0.01UF
BYPASS
R6887
1%
1/16W
MF-LF
2 402
AUD_PORTA_DET_L
C6802
INT*
R6880 1
63 58 57
57
1
D3
5%
1/16W
MF-LF
402
IN
1
HS_SW_DET
20.0K
1%
1/16W
MF-LF
2 402
Q6803
150K
AUD_J1_SLEEVEDET_R
1
EXT_MIC_BIAS
B1
100K
2
PP4V5_AUDIO_ANALOG_FLT
63
1
0
AUD_I2C_INT_L
PORT B DETECT(SPDIF DELEGATE)
C1
DETECT
HS_ENABLE
59
BI
R6885
OUT AUD_SENSE_A
MICBIAS
SDA
1
R6884
GPIO 3
SCL
B3
HS_INT_L
GPIO 5
PIRQ F
C3
C2
PIRQ H
MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM
HS_SDA
SATA4GP/GPIO 16
MIKEY INTERRUPT
CD3282A1
HS_SCL
2
GPIO
PERIPHERAL DETECT
D
U6880
AGND
INT
CRITICAL
AVDD
0.1UF
20%
6.3V
X5R
603
DGND
1
0x72
D2
FUNCTION
C
1
0
=I2C_MIKEY_SDA
5%
1/16W
MF-LF
402
MIKEY ENABLE
0x73
0010
CRITICAL
1
10UF
R6883
BI
SYSTEM INT AND GPIO LINES
62
C6880
WCSP
48
63 57
CRITICAL
N/A
HEADSET MIC
0011
CSP MIKEY
59
OUT
0111
APN:353S2640
N/A
0X06 (6)
0111
WRITE
PP3V3_S0_HS_RX
1
10K
2
5%
1/16W
MF-LF
402
PULLUPS ON MCP PAGE
FUNCTION
2
0402
R6882
0X07 (7)
READ
U6880
A2
SUB
SPDIF OUT
SPDIF IN
U6880
MIKEY
MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM
VOLTAGE=3.3V
FERR-1000-OHM
BUILT-IN MIC
MIKEY
CRITICAL
FUNCTION
D
I2C addresses: Mikey uses SMBus 0
PORT B LEFT(HEADSET MIC)
HP=80HZ, LP=8.82KHZ
MUTE CONTROL
1
PORT B RIGHT(BUILT-IN MIC)
SOT563
63 58 57
R6850
5
G
S
4
2
G
S
57
1
IN
AUD_CODEC_MICBIAS
100
1
R6851
MIC_BIAS_FILT
2
CRITICAL
1%
1/16W
MF-LF
402
1
63 58 57
1
FERR-1000-OHM
OUT AUD_MIC_INP_R
57
2
1
BI_MIC_HI_F
B
C6804
0.1UF
20%
CERM
PP4V5_AUDIO_ANALOG_FLT
1
C6851
R6852
AUD_J1_DET_NMOS_DRN
1
OUT AUD_MIC_INN_R
57
2
50V
402
10%
CERM
2
1
GND_AUDIO_CODEC
R6853
1
2.4K
S
AUD_J1_TIPDET_R
R6802
R6807
AUD_J1_DET_RC
1
1
C6801
0.1UF
2
20%
CERM
SM
1
1
C6803
2
TIPDET_UNFILT
PORT C DETECT (LINE-IN)
3
R6813
D
20%
CERM
R6808
10V
402
10K
VESM
63 57
1
G
S
AUD_SENSE_A
OUT
5%
1/16W
MF-LF
402
2
63 58 57
2
AUD_J1_DET_NMOS_GATE
Q6802
1
270K
GND_AUDIO_CODEC
2
A
SSM3K15FV
R6811
1
100K
2
1
5%
1/16W
MF-LF
402
OUT
18
62
IN
AUD_J2_TIPDET_R
1
47K
2
2
SYNC_MASTER=J31_AUDIO
1
C6811
20%
CERM
SYNC_DATE=10/26/2011
PAGE TITLE
AUDIO: JACK TRANSLATORS
0.1UF
10V
402
DRAWING NUMBER
GND_AUDIO_CODEC
2
Apple Inc.
051-9585
REVISION
R
5%
1/16W
MF-LF
402
200K
R6841
S
APN:376S0612
2
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
63 58 57
6
3
AUD_J2_DET_RC
5%
1/16W
MF-LF
402
EXTRACTION NOTIFICATION
Voltage level shifting from 5V to 3.3V
63 58 57
GND_AUDIO_CODEC
G
R6812
AUD_IP_PERIPHERAL_DET
D
SOD-VESM-HF
5%
1/16W
MF-LF
402
R6840
7
NC
=PP3V3_S0_AUDIO
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
8
AUD_INJACK_INSERT_L
1
1%
1/16W
MF-LF
402
63 62 57 7
R6809
2
220K
220K
2
63
D
6
1
1
BI_MIC_SHIELD
2
HP=80HZ
SSM3K15AMFVAPE
AUD_J1_DET_R_GATE
0.1UF
10V
402
Q6800
3
2
5%
1/20W
MF
201
Q6804
Q6804
100K
2
R6830
2
NTZD3152P
G
D
NOSTUFF
1
G
AUD_J1_DET_RC2
5%
1/20W
MF
201
0
2
NTZD3152P
5%
1/16W
MF-LF
402
1
6 62
B
APN:376S1017
SOT-563-HF
SOT-563-HF
5
BI_MIC_N
XW6851
2
1%
1/16W
MF
402-1
1
IN
IN
2
Place this next to the connector
S
62
6 62 101
L6851
BI_MIC_LO_F
4
R6801
2
FERR-1000-OHM
2
10%
25V
X5R
402
1
100K
IN
1
0.001UF
0402
63 58 57
2
6 62 101
C6853
5%
1/16W
MF-LF
402
0.1UF
GND_AUDIO_CODEC
220K
IN
CRITICAL
100K
CRITICAL
MIN_LINE_WIDTH=0.1MM
MIN_NECK_WIDTH=0.1MM
VOLTAGE=5V
1
10V
402
BI_MIC_P
0402
10%
25V
X5R
402
63
1
2
2
0402
63 58 57
L6850
C6850
0.1UF
1
PP4V5_AUDIO_ANALOG
20%
6.3V
TANT
402
CRITICAL
L6801
FERR-1000-OHM
IN
C6852
GND_AUDIO_CODEC
CRITICAL
57
2
1%
1/16W
MF
402-1
2.2UF
2
63
AUD_J1_SLEEVEDET_R_BUF
2.4K
1
5
4
3
2
3.0.0
BRANCH
PAGE
68 OF 132
SHEET
63 OF 105
1
SIZE
D
A
8
7
6
5
4
3
2
1
MagSafe DC Power Jack
PP18V5_DCIN_FUSE
CRITICAL
F6905
J6900
78048-0573
1
MIN_LINE_WIDTH=1mm
MIN_NECK_WIDTH=0.20mm
VOLTAGE=18.5V
1
PWR
C6905
1
2
PWR
1206-2
=PP3V42_G3H_ONEWIREPROT
20%
50V
CERM
603
2
4
GND
1
SMC_BC_ACOK_VCC
7
CRITICAL
2
R6929
2.0K
VCC
5%
1/16W
MF-LF
402
U6900
SOT665
MAX9940
4
2
U6901
TC7SZ08FEAPE
SC70-5
45
C6908
0.1UF
1
5
SIG
SYS_ONEWIRE
BI
4 INT
20%
10V
CERM
402
PLACEMENT_NOTE=PLACE NEAR U6900 and U6901
5
2
A
SMC_BC_ACOK
IN
45 46
Y
EXT 5
1
B
CRITICAL
3
NC
3
2
GND
NC
BIL CONNECTOR
=PP3V42_G3H_BIL
7
C6951
1-Wire OverVoltage Protection
516S0523
CRITICAL
1
0.1UF
ADAPTOR_SENSE
ADAPTER_SENSE
10%
25V
X5R
402
6
OUT
J6955
2
CPB6312-0101F
F-ST-SM
14
The chassis ground will otherwise float and can
13
2
53 46 45
OUT
SMC_LID
100
2
402
1
1/16W
5%
MF-LF
64 48
64 48
C6955
C6953
1
0.001UF
10%
50V
CERM
402
1
47PF
5%
50V
CERM
402
2
C6952
5%
50V
CERM
402
7
9
11
16
15
C
NC
TO SMC
SMC_BIL_BUTTON_L
C6954
1
47PF
2
5
12
SMC_LID_R
=SMBUS_BATT_SDA
BI
=SMBUS_BATT_SCL
BI
6
3
10
NC
6
8
R6961
connected.
1
4
send transients onto ADAPTER_SENSE when AC is
C
D
7 64
2
0.01UF
3
GND
=PP18V5_DCIN_CONN
6AMP-24V
PP18V5_DCIN_FUSE
M-RT-SM
1
D
6
CRITICAL
OUT
6 45 46
1
0.001UF
10%
50V
CERM
402
2
2
CRITICAL
R6905
1
5.1
5%
1/3W
MF
0805-1
2
CRITICAL
PBUS_G3H_R
1
VOLTAGE=18.5V
5%
1/3W
MF
0805
B
P18V5_DCIN_CONN_R
2
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.3 mm
VOLTAGE=18.5V
2
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.3 mm
VOLTAGE=18.5V
P3V42G3H_BOOST
DIDT=TRUE
3
1
PPVIN_G3H_P3V42G3H
3
47
=PP18V5_DCIN_CONN
Supply needs to guarantee 3.31V delivered to SMC VRef generator
SOT-323
R6990
64 7
3.425V " G3Hot " Supply
D6990
BAT30CWFILM
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
C6990
C6994
1
VIN
4.7UF
10%
35V
X5R-CERM
0805
7
=PPBUS_G3H
65 7
BOOST
10%
16V
X5R
402
U6990
2
1
0.1UF
LT3970
B
CRITICAL
L6995
2
33UH-20%-0.44A-0.455OHM
=PP3V42_G3H_REG
DFN
2
EN/UVL0
9
PG
BATTERY CONNECTOR
1
M-RT-TH
1
2
A
SWITCH_NODE=TRUE
DIDT=TRUE
1
1
P3V42_BD_R
1%
1/16W
MF-LF
402
2
Vout = 3.414
D52LC-SM
0
1
2
350mA max output
& lt; Ra & gt;
R6992
1/16W
MF-LF
402
5%
THRM
PAD
1
C6995
1
5%
50V
CERM
402
2
2
6
=SMBUS_BATT_SCL
SYS_DETECT_L
=SMBUS_BATT_SDA
65 6 PPVBAT_G3H_CONN
10
11
R6996
2
20%
6.3V
X5R-CERM-1
603
D6950
1
C6950
1
C6960
10%
25V
X5R
603-1
1
RCLAMP2402B
R6950 1
Vout = 1.21V * (1 + Ra / Rb)
10K
SC-75
5%
1/16W
MF-LF
402
1UF
10%
25V
X5R
402
2
1%
1/16W
MF-LF
2 402
48 64
CRITICAL
8
9
C6999
22UF
& lt; Rb & gt;
1
48 64
2
7
1
549K
4
6
1%
1/16W
MF-LF
402
P3V42G3H_FB
3
5
(Switcher limit)
R6995
1M
47PF
2
0.1UF
SHLD_PIN
SHLD_PIN
SHLD_PIN
SHLD_PIN
P3V42G3H_SW
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
2
2
3
P1
P2
P3
P4
P5
P6
P7
P8
P9
6
R6991
150K
BAT-K90-K91-K92
5
GND
4
CRITICAL
8
FB
RT
P3V42_RT
J6950
6
BD
353S2730
10
518-0375
SW
CRITICAL
11
NC
7
12
13
SYNC_MASTER=J31_JACK
SYNC_DATE=09/02/2011
PAGE TITLE
DC-In & Battery Connectors
DRAWING NUMBER
Apple Inc.
051-9585
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
3.0.0
BRANCH
PAGE
69 OF 132
SHEET
64 OF 105
1
A
8
7
6
5
4
3
2
1
R7091
0
CRITICAL
1
Q7080
R7093
IRF9395TRPBF
DIRECTFET-MC
PPCHGR_DCIN_D
0
1
PPCHGR_DCIN_D_R
6
10%
25V
X5R
402
2
2
3
6
1%
1/16W
MF-LF
402
R7086
D
S
G
C7090
10%
35V
X5R-CERM
0805
R7081
62K
1%
1/16W
MF-LF
402 2
2
BAT30CWFILM
5%
1/16W
MF-LF
402
SW
4
BIAS
2
SHDN*
CRITICAL
NC
GND
1
4.7UF
332K
(CHGR_AGATE)
7
NC
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.3 mm
1
D7005
8
CHGR_SGATE_DIV
1
CRITICAL
L7095
2
6
1
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
FB
THRM
PAD
PPCHGR_DCIN_D
20
1
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=18.5V
2
1
R7095 1
C7095
2
2
1%
1/20W
MF
201
5%
50V
CERM
201
10
1
5%
1/16W
MF-LF
402
1
2
1
5%
1/16W
MF-LF
402
48
IN
48
BI
74
IN
6
3
6
9.31K
1%
1/16W
MF-LF
2 402
1
R7015
99
330K
99
5%
1/16W
MF-LF
2 402
1
ACIN
11
10
4
CHGR_ICOMP
CHGR_VCOMP
CHGR_VNEG
CHGR_CSO_P
CHGR_CSO_N
5
7
8
18
17
C7050
1UF
2
C7015
10%
16V
X5R
402
1
1
0.1UF
10%
25V
X5R
402
1
B
1
101
CHGR_CSI_R_N
2
CRITICAL
1
2
2
10%
25V
X5R
402
CRITICAL
1
20%
2 25V
POLY-TANT
CASE-D2-SM
SGATE
AGATE
CSIP
CSIN
65
PPCHGR_DCIN
CHGR_SGATE
CHGR_AGATE
CHGR_CSI_P
CHGR_CSI_N
26
1
28 99
27 99
BOOT
UGATE
PHASE
25
23
6
CHGR_BOOT
CHGR_UGATE
CHGR_PHASE
21
6
4
1
24
6
C7025
2
C7037
0.001UF
10%
50V
X7R
402
2
C
LFPAK-SM
f = 400 kHz
10%
10V
CERM
402
GATE_NODE=TRUE
CRITICAL
S
3
1
2
3
BGATE
AMON
36V/V BMON
(OD) ACOK
20V/V
CHGR_BGATE
CHGR_AMON
CHGR_BMON
=CHGR_ACOK
16
9
15
14
DIDT=TRUE
1
1
NO STUFF
50
OUT
46 49
F7041
8AMP-24V
1
PPVBAT_G3H_CHGR_REG
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.4 mm
VOLTAGE=12.6V
OMIT_TABLE
RJK0305DPB
2
XW7000
2
3
CRITICAL
Q7055
SI7137DP
SO-8
(GND)
1
3
PPVBAT_G3H_CHGR_R
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.4 mm
VOLTAGE=12.6V
10%
25V
X5R
603-1
R7051
2.2
1
2
R7052
0
1
2
101
5%
1
C7056
1
0.1UF
2
10%
16V
X5R
402-1
C7057
1
D
2
10%
16V
CERM
402
5
PPVBAT_G3H_CONN
6 64
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.4 mm
VOLTAGE=12.6V
1
0.01uF
G
2
4
CHGR_CSO_R_P
1/16W
101
5%
S
2
C7055
1UF
(CHGR_CSO_N)
10%
50V
CERM
402
3
B
TO/FROM BATTERY
SYM-VER-2
2
PLACE_NEAR=U7000.29:1mm
PLACE_NEAR=U7000.22:1mm
(CHGR_CSO_P)
10%
50V
X7R
402
1%
1W
MF
0612
SM
2
2
0.005
4
1
C7045
0.001UF
20%
25V
POLY-TANT
CASE-D2-SM
R7050
10%
50V
CERM
402
2
C7040
1206
CRITICAL
NO STUFF
C7039
1
1
22UF
CHGR_PHASE_RC
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
DIDT=TRUE
2
CRITICAL
1
5
CRITICAL
7 64
CRITICAL
180
5%
1/10W
MF-LF
603 2
353S2392
=PPBUS_G3H
1206
50
OUT
2
FDA1254F-SM
R7039 1
OUT
LFPAK-HF
1
8AMP-24V
2
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
SWITCH_NODE=TRUE
DIDT=TRUE
TO SYSTEM
F7040
4.7UH-10.2A
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm
GATE_NODE=TRUE
CRITICAL
NC L7030
DIDT=TRUE
MF-LF
402
CHGR_CSO_R_N
1/16W
MF-LF
402
(PPVBAT_G3H_CHGR_R)
(CHGR_BGATE)
CHGR_ICOMP_RC
C7042
C7011
0.068UF
2
10%
25V
X5R
603-1
(L7030 limit)
RJK0332DPB-01
PLACE_NEAR=U7000.25:2mm
DIDT=TRUE
(PPVBAT_G3H_CHGR_R)
1
2
1
1UF
Max Current = 8A
Q7030
G
0.22UF
2
CHGR_LGATE
6
CRITICAL
D
470PF
6
C7036
OMIT_TABLE
2
C7016
2
1
10%
25V
X5R
603-1
5
DCIN
CHGR_VNEG_R
1
C7035
1UF
22UF
PLACE_NEAR=C7036.1:3mm
4
2
1
C7031
PLACE_NEAR=Q7030.5:1mm
470PF
1%
1/16W
MF-LF
402
C7030
20%
2 25V
POLY-TANT
CASE-D2-SM
0.1UF
2
3.01K
2
1
22UF
Q7035
R7016 1
5%
1/16W
MF-LF
2 402
20%
10V
X5R
0603
Vout = 1.25V * (1 + Ra / Rb)
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.4 mm
VOLTAGE=18.5V
R7042
0
2
R7020
C7021
220PF
10%
50V
X7R-CERM
402
C7099
10UF
20%
10V
X5R
0603
2
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
29
CHGR_VCOMP_R
C7022
1
LGATE
ICOMP
VCOMP
VNEG
CSOP
CSON
(AGND)
R7011
2
0.5%
1W
MF-LF
0612
3
10
VDDP
VHST
CRITICAL
SMB_RST_N
SCL
U7000
TQFN
SDA
VFRQ
CELL
13
CHGR_ACIN
1
CRITICAL
1
20
VDD
CHGR_RST_L
=SMBUS_CHGR_SCL
=SMBUS_CHGR_SDA
CHGR_VFRQ
CHGR_CELL
2
1%
1/16W
MF-LF
2 402
C7001
ISL6259
1
30.1K
PP5V1_CHGR_VDDP
R7002
12
2
CHGR_CSI_R_P
0.020
R7022
10%
10V
X5R
402
5%
1/16W
MF-LF
402
4
101
5%
1/16W
MF-LF
402
PGND
2
10%
10V
CERM
402
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5.1V
22
65
0
SMC_RESET_L
IN
C7020
1UF
R7000
R7010
65
100K
GND_CHGR_AGND
C7098
PPDCIN_G3H_CHGR
2
NO STUFF
2
1%
1/20W
MF
201
SIGNAL_MODEL=EMPTY
CRITICAL
2
5%
1/16W
MF-LF
402
1
5%
1/16W
MF-LF
402
19
1%
1/16W
MF-LF
402 2
4.7
THRM_PAD
10%
10V
X5R
402
1K
1
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.1 mm
VOLTAGE=5.1V
1UF
R7012 1
1
10UF
R7021
R7001
PP5V1_CHGR_VDD
C
CRITICAL
2
P5V5G3H_FB
R7096 1
(CHGR_DCIN)
30mA max load
1
(Switcher limit)
681K
22PF
2
& lt; Rb & gt;
0.047UF
C7002
200MA MAX OUTPUT
& lt; Ra & gt;
1
(CHGR_SGATE)
Divider sets ACIN threshold at 13.55V
1
D
Vout = 5.506V
SWITCH_NODE=TRUE
DIDT=TRUE
200K
65
ACIN pin threshold is 3.2V, +/- 50mV
=PP3V42_G3H_CHGR
65
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5.5V
DP418C-SM
R7005
3
74 7
PPCHGR_DCIN
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5.5V
2
SOT-323
1
Input impedance of ~40K meets
sparkitecture requirements
65
NO STUFF
PP5V5_CHGR_VDDP
33UH-20%-0.39A-0.435OHM
P5V5G3H_SW
2
5%
1/16W
MF-LF
402
DFN
R7080
5%
1/16W
MF-LF
2 402
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.3 mm
CRITICAL
LT3470A
100K
CHGR_AGATE_DIV
10%
10V
CERM
402
U7090
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.4 mm
VOLTAGE=18.5V
1
0.22UF
9
2
470K
0.1UF
10%
25V
X5R
603-1
C7094
BOOST
5
1UF
1
R7085
G
C7085
0
1
PPDCIN_G3H_INRUSH
3
1
1
6
C7086
1
D
S
NO STUFF
PP5V1_CHGR_VDDP
R7092
DIDT=TRUE
VIN
=PPDCIN_S5_CHGR
P5V5G3H_BOOST
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=18.5V
Reverse-Current Protection
2
5%
1/16W
MF-LF
402
2
5%
1/16W
MF-LF
402
NC
7
10
1
2
9
4
5
NC
Inrush Limiter
FROM ADAPTER
D
8
NC
NC
7
65
5.5V " G3Hot " Supply
1
1
2
2
0.01UF
10%
10V
CERM
402
10%
16V
CERM
402
C7000
C7005
1UF
1
0.22UF
10%
10V
X5R
402-1
20%
25V
X5R
603
C7026
1
0.001UF
10%
50V
CERM
402
2
65
2
GND_CHGR_AGND
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V
A
SYNC_MASTER=J31_JACK
SYNC_DATE=11/14/2011
PAGE TITLE
PBus Supply & Battery Charger
DRAWING NUMBER
Apple Inc.
051-9585
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
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REVISION
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70 OF 132
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1
A
8
7
6
5
4
3
2
1
D
D
7
7
=PPVIN_S0_VCCSAS0
=PP5V_S0_VCCSAS0
VCCSAS0_BOOT_RC
CRITICAL
R7101 1
1
2
20%
10V
X5R
603
1
R7130
2
6
1
2
6
1%
1/16W
MF-LF
402
C
1
BOOT
17
19
7
74
SREF
PHASE
12
VO
LGATE
14
10%
16V
CERM-X5R
402
SM
PLACE_NEAR=C1759.2:1mm
1
2
1
1
2
R7150
10%
16V
X5R
603
1/16W
MF-LF
402
VCCSAS0_LL
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VCCSAS0_DRVL
1
1
C7106
10PF
2
5%
50V
CERM
402
R7154
4.64K
1%
1/16W
MF-LF
2 402
1
R7152
1
4.64K
1%
1/16W
MF-LF
2 402
C7105
93 12
IN
5%
50V
CERM
402
1
VID1
2
4
3
4
C
6A Max Output
f = 300 kHz
5
(ENDIAN SWAP)
101 49
VCCSAS0_CS_P
101 49
VCCSAS0_CS_N
SIGNAL_MODEL=EMPTY
GND
2
PGND
R7141
1
1K
C7140
1000PF
2
CPU_VCCSA_VID & lt; 1 & gt;
CPU_VCCSA_VID & lt; 0 & gt;
SIGNAL_MODEL=EMPTY
SIGNAL_MODEL=EMPTY
1
R7142
1K
1%
1/16W
MF-LF
2 402
(VCCSAS0_OCSET)
1%
1/16W
MF-LF
402
1
5%
25V
NP0-C0G
402
R7149
499K
B
3
VID0
5
VCCSAS0_SET_R
10PF
2
IN
7 49
2
GATE_NODE=TRUE
DIDT=TRUE
1%
1/16W
MF-LF
402 2
93 12
=PPVCCSA_S0_REG
1
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
152S0913
2
1%
1/16W
MF-LF
402
PPVCCSA_S0_REG_R
FDV0630H-SM
SWITCH_NODE=TRUE
DIDT=TRUE
82.5K
1
1%
1W
MF-1
0612
2
SET1
R7103 1
0
C7102
5%
2.2UF
1
7
SET0
9
6
1%
1/16W
MF-LF
402
0.001
1.0UH-7.7A
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
8
R7148
52.3K
2
6
6
FSEL
VCCSAS0_SET0
1
0.022UF
R7140
L7100
6
RTN
13
VCCSAS0_SET1
C7103
2
CRITICAL
PGOOD
4
VCCSAS0_FSEL
XW7101
5%
25V
NP0-C0G
402
PLACE_NEAR=C7121.1:3mm
CRITICAL
1
OCSET
VCCSAS0_RTN_DIV
1%
1/16W
MF-LF
402
1000PF
Q7100
GATE_NODE=TRUE
DIDT=TRUE
1
11
PVCCSA_PGOOD
OUT
C7122
RJK0222DNS
2
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
16
VCCSAS0_OCSET
2
2
VCCSAS0_DRVH
18
VCCSAS0_VO
1%
1/16W
MF-LF
2 402
R7153
1
2
HWSON
UGATE
CRITICAL
10%
25V
X5R
603-1
PLACE_NEAR=Q7100.2:1mm
VCCSAS0_VBST
R7147
41.2K
VCCSAS0_RTN
FB
1
1UF
2
376S0944
CRITICAL
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VCCSAS0_SREF
1
1.62K
10
CPU_VCCSASENSE_DIV
C7121
1
10%
10V
CERM
402
2
IN
1.62K
CPU_VCCSASENSE
UTQFN
EN
3
93 12
15
=PVCCSA_EN
IN
10%
16V
X5R-CERM
0805
2
DIDT=TRUE
ISL95870AH
74
2
20
PVCC
C7120
10UF
10%
16V
X5R-CERM
0805
C7130
0.22UF
0
U7100
R7151
1
5%
1/10W
MF-LF
603 2
VCC
CRITICAL
1
10UF
PP5V_S0_VCCSAS0_VCC
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V
C7119
DIDT=TRUE
10UF
2.2
5%
1/16W
MF-LF
402
CRITICAL
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
C7101
OCP = R7141 x 8.5uA / R7140
OCP = 8.5A
B
(VCCSAS0_VO)
XW7100
SM
VCCSAS0_AGND
1
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V
2
PLACE_NEAR=U7100.3:1mm
INTEL TABLE:
VID1
0
VID0
0
Voltage
0.9V
1
0
0.8V
0
1
0.725V
1
1
0.675V
A
SYNC_MASTER=J31_JACK
SYNC_DATE=09/14/2011
PAGE TITLE
System Agent Supply
DRAWING NUMBER
Apple Inc.
051-9585
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
3.0.0
BRANCH
PAGE
71 OF 132
SHEET
66 OF 105
1
A
8
7
6
5
4
3
2
1
D
D
CRITICAL
1
1
C7242
68UF
20%
16V
POLY-TANT
CASE-D2E-SM
1
20%
16V
POLY-TANT
CASE-D2E-SM
2
C7241
1
2
2
0.001UF
10%
25V
X5R
603-1
10%
50V
X7R
402
2
C7200
1UF
10%
25V
X5R
603-1
PLACE_NEAR=C7241.1:3MM
1
SKIP_5V3V3:AUDIBLE
C7271
1
6
P5VS3_VSW
CRITICAL
C7250
1
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
DIDT=TRUE
1
3
6
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
GATE_NODE=TRUE
DIDT=TRUE
VSW
TGR
4
5%
1/16W
MF-LF
402
6
2
GATE_NODE=TRUE
XW7222
SM
1
P5VS3_VFB1_R
2
XW7220
SM
R7220 1
6
SWITCH_NODE=TRUE
GATE_NODE=TRUE
9
1
C7299
10%
50V
CERM
402
1
6.04K
74
SM
1%
1/16W
MF-LF
402
IN
74
13
22
29
23
2
30
VREF2
VREG3
2
2
=P5VS5_EN
12
OUT
1
7
8
9
10
=P5VS3_EN
P5VS3_PGOOD
4
5
DRVH2
2
24
6
SW2
25
6
DRVL2
27
6
CSP1
CSN1
CSP2
CSN2
IN
MODE
VFB1
COMP1
RF
VFB2
COMP2
EN1
PGOOD1
EN2
PGOOD2
3
16
15
21
20
6
1%
1/16W
MF-LF
402
GATE_NODE=TRUE
1
Q7260
2.2UH-14A
IHLP2525CZ-SM1
C7272
1
NO STUFF
6
R7298 1
10
C7288
3
4
5%
1/10W
MF-LF
603
5
0.1UF
1
OUT
6
1%
1/16W
MF-LF
402
NO STUFF
1
R7246
1
1.21K
2
2
1
10.5K
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
C7298
0.001UF
2
1%
1/16W
MF-LF
402
2
P3V3S5_SNUBR
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
DIDT=TRUE
249K
R7239 1
R7238
2
10%
16V
X5R
402-1
R7206 1
74
C
2
CRITICAL
C7290
1
10UF
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
74
1
CRITICAL
7
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
IN
10%
50V
X7R
402
1
1
10%
50V
X7R
402
R7216
2
5.62K
2
2
P3V3S5_COMP2_R
SM
2 WPAK2
2
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
DIDT=TRUE
GATE_NODE=TRUE
GATE_NODE=TRUE
=P3V3S5_EN
P3V3S5_PGOOD
XW7200
6
XW7260
1%
1/16W
MF-LF
402
SM
1
2
C7237
1
1
150PF
1
5%
50V
CERM
402
R7221
10.2K
2
1
C7236
C7238
4700PF
2
2
1
1
2200PF
10%
100V
CERM
402
5%
10V
CERM
0402
(P5VP3V3_VREF2)
C7292
330UF
20%
6.3V
X5R
603
2
20%
6.3V
POLY-TANT
CASE-D3L-SM1
2
XW7262
SM
1
P3V3S5_VFB2_R
2
XW7261
SM
1
R7260 1
23.2K
1%
1/16W
MF-LF
402
P3V3S5_CSP2_R
PLACE_NEAR=U7200.28:1MM
2
7
f = 400 Khz
L7260
P3V3S5_TG
P3V3S5_RF
P3V3S5_VFB2
P3V3S5_COMP2
2
CRITICAL
RJK0214DPA
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
THRM_PAD
2
P5VS3_COMP1_R
6
SWITCH_NODE=TRUE
12.1K
2
10%
50V
X7R
402
0.001UF
2
5%
1/16W
MF-LF
402
P3V3S5_DRVL
1
0.001UF
8.07A MAX OUTPUT
2
CRITICAL
C7264
10%
50V
X7R
603-1
0
P3V3S5_LL
12.1K
1%
1/16W
MF-LF
402
P5VS3_CSP1_R
17
C7283
2
=PP3V3_S5_REG
R7263
74
P3V3S5_CSP2
P3V3S5_CSN2
18
2
PLACE_NEAR=C7281.1:3MM
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
P3V3S5_DRVH
DIDT=TRUE
R7236 1
10.5K
2
20%
10V
X5R-CERM
402
P3V3S5_VBST
DIDT=TRUE
P5VS3_VFB1
P5VS3_COMP1
R7237
6
2
10%
25V
X5R
603-1
Vout = 3.3V
DIDT=TRUE
DRVL1
GND
1%
1/16W
MF-LF
402
26
1
1UF
C7203
1
VBST2
2
C7281
PLACE_NEAR=Q7260.2:1MM
0.1UF
EN
1
2.2UF
DIDT=TRUE
P5VS3_DRVL
2
8.25K
1
DRVH1
SW1
11
R7247
R7256 1
XW7221
6
1
2
10%
16V
X5R
402-1
2
VBST1
32
P5VS3_CSP1
P5VS3_CSN1
1
0.0033UF
10%
10V
CERM
402
DIDT=TRUE
6
NO STUFF
2
SIGNAL_MODEL=EMPTY
P5VS3_DRVH
P5VS3_LL
0.1UF
P5VS3_SNUBR
1
0.22UF
DIDT=TRUE
C7218
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
DIDT=TRUE
SIGNAL_MODEL=EMPTY
1
41.2K
31
DIDT=TRUE
6
PGND
5%
1/10W
MF-LF
603
P5VS3_VBST
DIDT=TRUE
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
5
SKIPSEL1
CRITICAL
SKIPSEL2
U7201
OCSEL
1
QFN
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
BG
R7299
19
14
6
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
8
1
2
2
B
P5VP3V3_SKIPSEL
1
P5VS3_TG
NO STUFF
1
PLACE_NEAR=L7220.2:3MM
2
PLACE_NEAR=L7220.1:3mm
SIGNAL_MODEL=EMPTY
TG
R7244 1
6
PLACE_NEAR=L7220.1:3mm
20%
10V
X5R
805
2
SON5X6
7
10UF
330UF
VIN
2
6
10%
50V
X7R
603-1
28
CRITICAL
2
CSD58872Q5D
0.001UF
2
5%
1/16W
MF-LF
402
20%
16V
POLY-TANT
CASE-D2E-SM
1
68UF
20%
6.3V
X5R
603
33
Q7220
PIMB104E2R2MS-SM
10%
50V
X7R
402
2
0.1UF
2.2UH-14A-7.0M-OHM
C
C7224
5%
1/16W
MF-LF
402
VREG5
CRITICAL
L7220
2
C7282
20%
16V
POLY-TANT
CASE-D2E-SM
C7205
2
C7201
0
TPS51980
1
R7201
VIN
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
CRITICAL
1
20%
6.3V
POLY-TANT
CASE-D3L-SM1
R7200
CRITICAL
1
68UF
10UF
P5VP3V3_VREF2
V5SW
1
f = 400 Khz
C7252
1
0
11.834A MAX OUTPUT
1%
1/16W
MF-LF
402
SKIP_5V3V3:INAUDIBLE
=PP5V_S3_REG
Vout = 5.0V
C7280
CRITICAL
2
P5VP3V3_VREG3
1
7
Vout = 5V
100mA MAX OUTPUT
1
PLACE_NEAR=Q7220.1:1MM
67 7
CRITICAL
=PP5V_S5_LDO
C7270
1UF
68UF
PLACE_NEAR=L7260.2:3mm
C7240
PLACE_NEAR=L7260.2:3mm
CRITICAL
=PP5V_S3_REG
PLACE_NEAR=L7260.1:3mm
67 7
=PPVIN_S5_P5VP3V3
7
2
C7239
47PF
2
2
5%
50V
CERM
402
B
R7261 1
10K
(P5VP3V3_VREF2)
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
2
GND_5V3V3_AGND
MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=0V
A
SYNC_MASTER=J31_JACK
SYNC_DATE=11/09/2011
PAGE TITLE
5V / 3.3V Power Supply
DRAWING NUMBER
Apple Inc.
051-9585
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
3.0.0
BRANCH
PAGE
72 OF 132
SHEET
67 OF 105
1
SIZE
D
A
8
7
6
5
4
3
2
1
D
D
7
=PPVIN_S3_DDRREG
CRITICAL
CRITICAL
C7330
1
C7331
68UF
7
=PPVIN_S0_DDRREG_LDO
7
=PP5V_S3_DDRREG
1
1
C7332
1
C7333
1UF
68UF
20%
16V 2
POLY-TANT
CASE-D2E-SM
20%
16V 2
POLY-TANT
CASE-D2E-SM
2
1
10%
50V
X7R
402
C7334
0.001UF
10%
25V
X5R
603-1
2
1UF
10%
25V
X5R
603-1
2
PLACE_NEAR=C7332.1:3MM
CRITICAL
PLACE_NEAR=Q7330.1:1MM
C7301
1
10UF
20%
10V
X5R
603
CRITICAL
C7300
1
5
2
10UF
20%
10V
X5R
603
CRITICAL
D
2
(DDRREG_DRVH)
Q7330
G
4
RJK0225DNS
2
MIN_LINE_WIDTH=0.6 mm
C
HVSON-3333
MIN_NECK_WIDTH=0.17 mm
VLDOIN
C7325
MIN_NECK_WIDTH=0.17 mm
12
IN
74
IN
DDRREG_FB
=DDRVTT_EN
=DDRREG_EN
(VTT Enable)
(VDDQ/VTTREF Enable)
DDRREG_1V8_VREF
1
C7315
1
R7315
16
6
8
U7300
S3
S5
TPS51916
2
2
DDRREG_MODE
1%
1/16W
MF-LF
402
6 DDRREG_TRIP
19
18
VREF
CRITICAL
REFIN
MODE
TRIP
2
R7316
1
100K
1%
1/16W
MF-LF
402
DDRREG_P1V35_L
2
1%
1/16W
MF-LF
402
C7316
0.01UF
2
1
10%
16V
CERM
402
D
1
2
SSM3K15FV
14
6 DDRREG_DRVH
13
6 DDRREG_LL
GATE_NODE=TRUE
DIDT=TRUE
11
GATE_NODE=TRUE
3
92
OUT
5
XW7360
7 =PPVTT_S0_DDR_LDO
2
(DDRREG_DRVL)
=PPVTT_S3_DDR_BUF
10mA max load
1
C7350
RJK0226DNS
HVSON-333
CRITICAL
MIN_NECK_WIDTH=0.17 mm
CRITICAL
1
1
S
C7361
2
2
20%
6.3V
X5R
603
1
2
1
20%
2.0V 2
POLY-TANT
CASE-B2-SM1
OMIT_TABLE
2
330UF
10UF
3
C7346
0.001UF
CRITICAL
C7341 1
CRITICAL
1
1
2
C7345
10%
50V
X7R
402
2
10UF
XW7301
20%
6.3V
X5R
603
SM
PLACE_NEAR=C7340.1:1MM
1
PLACE_NEAR=J3100.202:1mm
to memory
(DDRREG_VDDQSNS)
MIN_LINE_WIDTH=0.2 mm
0.22UF
10%
10V
CERM
402
G
MIN_LINE_WIDTH=0.6 mm
20%
6.3V
X5R
603
2
4
C7340
20%
2 2.0V
POLY-TANT
CASE-B2-SM1
Q7335
7
Vout = 1.5V
15A max output
(Q7335 limit)
f = 400 kHz
330UF
CRITICAL
D
SM
5
=PPDDR_S3_REG
CRITICAL
1
1
1
2
FDU1040D-SM
MIN_NECK_WIDTH=0.17 mm
10UF
SM
1
DDRREG_VDDQSNS
C7360
XW7300
L7330
MIN_LINE_WIDTH=0.6 mm
DIDT=TRUE
DDRREG_PGOOD
PLACE_NEAR=J3100.202:3mm
NOSTUFF
CRITICAL
1.0UH-21A
6 DDRREG_DRVL
20
9
C7360, C7361 close
SOD-VESM-HF
3
(DDRREG_LL)
VTT THRM
GND PAD
1%
1/16W
MF-LF
402
2
10%
50V
X7R
603-1
DIDT=TRUE
66.5K
1%
1/16W
MF-LF
402
2
1
R7318
200K
Q7319
3
R7317
7
150K
DRVL
PGOOD
VDDQSNS
VTT
VTTSNS
2
DIDT=TRUE
SWITCH_NODE=TRUE
VTTREF
10
1
1
MIN_LINE_WIDTH=0.6 mm
PLACE_NEAR=C7361.1:3mm
PGND GND
R7319
DDRREG_VBST
DDRREG_VTTSNS
NOSTUFF
1
15
QFN
20.0K
0.1UF
10%
16V
X5R
402
17
VBST
DRVH
SW
21
IN
26 8
4
31 6
V5IN
C
OMIT_TABLE
S
0.1UF
MIN_NECK_WIDTH=0.17 mm
2
PLACE_NEAR=U7300.7:1mm
2
S
G
GND_DDRREG_SGND
1
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.17 mm
VOLTAGE=0V
B
B
MEM_VDD_SEL:GPIO15
R7351
0
GPIO15_MEM_VDD_SEL_1V5_L
1
2
XDP_FC0_PCH_GPIO15
IN
19 23
5%
1/20W
MF
201
A
SYNC_MASTER=J31_JACK
SYNC_DATE=07/07/2011
PAGE TITLE
1.5V DDR3 Supply
DRAWING NUMBER
Apple Inc.
051-9585
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
3.0.0
BRANCH
PAGE
73 OF 132
SHEET
68 OF 105
1
A
8
7
6
5
4
3
=PP5V_S0_CPUIMVP
2
1
7 70
R7401
D
10
1
PP5V_S0_CPUIMVP_VCC
D
2
MIN_LINE_WIDTH=0.4 MM
5%
1/20W
MF
201
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=5V
=PPVIN_S0_CPUIMVP
7 =PPVCCIO_S0_CPUIMVP
1
C7401
1
20%
10V
X5R-CERM
402
NO STUFF
402
130
29
QFN
CPUIMVP_AXG_PWM2
13
DRVPWMB
TONB
1
OUT
CPUIMVP_PWM3
37
DRVPWMA
TONA
48
OUT
45
CSPA3
VRHOT*
BSTA1
DHA1
LXA1
DLA1
CSPA1
25
IN
CPUIMVP_ISUM3_P
4
92
74
IN
CPUIMVP_PGOOD
24
OUT
CPUIMVP_AXG_PGOOD
12
47
CPUIMVP_VR_ON
93 12
IN
CPU_VIDSOUT
21
93 12
IN
CPU_VIDSCLK
23
93 12
IN
22
CPU_VIDALERT_L
39
CPUIMVP_NTC
POKA
POKB
R7460
NOSTUFF
1%
1/20W
MF
201
2
301K
301K
NONE
NONE
NONE
0201
1%
1/20W
MF
201
8
2
2
C7408
6 70
OUT
2
CPUIMVP_ISNS2_P
IN
50 70 101
CPUIMVP_ISNS3_P
IN
50 70 101
5%
1/20W
MF
201
NO STUFF
6 70
150PF
1
OUT
OUT
CPUIMVP_PHASE2
OUT
CPUIMVP_LGATE2
OUT
CPUIMVP_BOOT1G
OUT
CPUIMVP_UGATE1G
OUT
CPUIMVP_PHASE1G
OUT
6
70
6
70
6
70
OUT
R7408
CPUIMVP_ISUM_R
300
1
10%
25V
X7R-CERM
0201
2
6
70
14
2
70
6
70
6
70
6
70
6
70
0402
CPUIMVP_ISUM
43
CPUIMVP_ISUM_N
3
CPUIMVP_FBA
IN
70
5%
1/20W
MF
201
C7409
69
33
31
16
1
OUT
C
R7410
470PF
2
1
1
2
5%
1/20W
MF
201
10%
16V
X5R-X7R
201
18
CPUIMVP_LGATE1G
CPUIMVP_ISUMG2_P
OUT
IN
70
CPUIMVP_ISUMG1_P
15
IN
70
CPUIMVP_ISUMG_N
IN
70
70
11
9
10
6
CPUIMVP_FBB
69
CPUIMVP_ISUM3_P
R7463
1
R7461
200K
0402
2
2
137K
1%
1/20W
MF
201
NO STUFF
1%
1/20W
MF
201
2
2
C7418
1
137K
1%
1/20W
MF
201
17
1
R7465
30
100KOHM
49
1
R7467
100KOHM
IN
69 70
XW7400
2
NO STUFF
1
C7419
NO STUFF
1
C7414
NO STUFF
1
C7415
NO STUFF
1
NO STUFF
C7416
1
C7417
100PF
1
2
100PF
100PF
100PF
100PF
100PF
5%
25V
CERM
201
SM
5%
25V
CERM
201
5%
25V
CERM
201
5%
25V
CERM
201
5%
25V
CERM
201
5%
25V
CERM
201
2
2
2
2
2
NO STUFF
1
C7423
100PF
2
PLACE_NEAR=U7400.46:1mm
B
50 70 101
CRITICAL
R7469
2
OUT
CPUIMVP_LGATE1
1
CPUIMVP_ISUM1_P
CPUIMVP_UGATE2
CSPBAVE
AGND
IN
R7407
2
CPUIMVP_ISUM2_P
CSPB2
CSPB1
CSNB
FBB
1
CRITICAL
CPUIMVP_PHASE1
28
42
CPUIMVP_BOOT2
1%
1/20W
MF
201
7
1
1
GNDSA
2
R7462
6 70
BSTB
DHB
LXB
DLB
2
1%
1/20W
MF
201
1
R7464
5
2
1
5.76K
OUT
32
OMIT
R7466
5.76K
36
OUT
CPUIMVP_UGATE1
26
180K
1%
1/20W
MF
201
6 70
34
IMAXA
IMAXB
20
R7468
35
CPUIMVP_ISNS1_P
300
CPUIMVP_BOOT1
27
2
5%
1/20W
MF
201
R7402
1
CPUIMVP_TONA
44
SR
CPUIMVP_IMAXB
1
38
CPUIMVP_IMAXA
1
40
CPUIMVP_TONB
41
THERMA
THERMB
CPUIMVP_SLEW
1%
1/20W
MF
201
CSPA2
BSTA2
DHA2
LXA2
DLA2
VDIO
CLK
ALERT*
CPUIMVP_NTCG
1
CSPAAVE
CSNA
FBA
EN
50 70 101
2
PGNDB
5%
50V
C0G-CERM
0402
OUT
THRM
PAD
PGNDA
C
92
CRITICAL
GNDSB
2
C7450
43PF
1
IN
300
180K
70
CPU_PROCHOT_L
CPUIMVP_ISNS1_N
R7406
R7403
1
70
OUT
2
5%
1/20W
MF
201
Note: value needs scrubbing
MAX15119GTM
70 69
300
1
19
VDDB
2
PLACE_NEAR=U7400.19:2mm
PLACE_NEAR=U7400.29:2mm
46
2
R7409
1%
1/20W
MF
201
U7400
93 46 45 10
X5R-CERM
402
VCC
1%
1/20W
MF
201
2.2UF
2
2
VDDA
54.9
X5R-CERM
R7480
C7403
20%
10V
2
20%
10V
R7479 1
1
C7402
2.2UF
1
2.2UF
7 70
5%
25V
CERM
201
B
GND_CPUIMVP_SGND
C7452
MIN_LINE_WIDTH=0.6 mm
PLACE_NEAR=Q7510.1:1mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V
PLACE_NEAR=Q7550.1:1mm
1
100PF
C7440
1
2
1000PF
2
10%
16V
X7R
201
1
CPU_AXG_SENSE_R
70
IN
C7441
CPUIMVP_ISUMG_AVE_P
10
2
CPU_AXG_SENSE_N
IN
12 93
1
C7412
1000PF
2
R7412
5%
1/20W
MF
201
1000PF
10%
16V
X7R
201
5%
25V
CERM
201
R7440
1
10%
16V
X7R
201
R7413
10
12.7K
69
CPUIMVP_FBA
1
2
1
CPUIMVP_FBA_R
1/16W
2
R7441
2
CPU_VCCSENSE_P
IN
12 93
CPU_AXG_SENSE_P
IN
12 93
5%
1/20W
MF
201
1%
MF-LF
402
10
1
CPU_VCCSENSE_R
NO STUFF
1
C7442
NO STUFF
1
C7443
1000PF
2
CPU_VCCSENSE_N
IN
12 93
C7422
5%
1/20W
MF
201
PLACE HOLDER
10%
16V
X7R
201
R7422
10%
16V
X7R
201
2
1
1000PF
1000PF
10%
16V
X7R
201
2
2
R7423
10
17.4K
69
CPUIMVP_FBB
1
2
PLACE HOLDER
CPUIMVP_FBB_R
1
2
5%
1/20W
MF
201
1%
1/16W
MF-LF
402
C7462
100PF
1
2
5%
25V
CERM
201
NO STUFF
A
SYNC_MASTER=J31_JACK
SYNC_DATE=11/11/2011
PAGE TITLE
CPU IMVP7 & AXG VCore Regulator
DRAWING NUMBER
Apple Inc.
051-9585
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
3.0.0
BRANCH
PAGE
74 OF 132
SHEET
69 OF 105
1
A
8
7
6
5
4
3
THESE TWO CAPS ARE FOR EMC
NOSTUFF
PHASE 1
68UF
Q7510
D
CASE-D2E-SM
G
1
2
1
C7517
1
C7518
1
C7519
10UF
16V
POLY-TANT
2
CASE-D2E-SM
10UF
1UF
0.001UF
0.001UF
10%
16V
X5R-CERM
0805
20%
16V
POLY-TANT
CRITICAL
1
C7516
10%
16V
X5R-CERM
0805
10%
16V
X5R
402
10%
50V
X7R
402
10%
50V
X7R
402
2
2
2
2
PHASE 2
CASE-D2E-SM
G
PLACE_NEAR=Q7510.6:1MM
4
L7510
DIDT=TRUE
D
R7511
0
5%
1/16W
MF-LF
402
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM
0.22UF
2
2
PIMA104E-SM
152S1019
SWITCH_NODE=TRUE
10%
10V
CERM
402
VOLTAGE=1.25V
101 69 50
1
R7512
CPUIMVP_UGATE1
DIDT=TRUE
3
R7513 1
DIDT=TRUE
GATE_NODE=TRUE
1
CRITICAL
5%
1/16W
MF-LF
402
50 69 101
PLACE_NEAR=C7581.1:1mm
R7514
10.2
1%
1/20W
MF
201
CPUIMVP_PH1_SNUB
1%
1/20W
MF
201
6
2
2
69 6
SIGNAL_MODEL=EMPTY
IN
CASE-D2E-SM
2
IN
2
VOLTAGE=1.25V
1W
1
PIMA104E-SM
VOLTAGE=1.25V
101 69 50
D
GATE_NODE=TRUE
OUT
50 101
OUT
1
46.4
SIGNAL_MODEL=EMPTY
1%
1/20W
MF
201
2
CPUIMVP_PH2_SNUB
649135PBF
7 70
CPUIMVP_ISNS2_N
R7523 1
Q7525
6
PLACE_NEAR=C7582.1:1mm
R7524
10.2
2
PLACE_NEAR=C7582.2:1mm
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM
SIGNAL_MODEL=EMPTY
1%
1/20W
MF
201
2
CPUIMVP_ISUM_N
DIRECTFET_S3C
2
DIDT=TRUE
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
GATE_NODE=TRUE
69 6
CPUIMVP_PHASE2
IN
10%
50V
CERM
402
R7515 1
1%
1/20W
MF
201
NOSTUFF
3
5
6
376S1011
1
NOSTUFF
69 6
C7581
2
2
DIDT=TRUE
DIRECTFET_S3C
1
0.001UF
R7525
10%
50V
CERM
402
2
DIDT=TRUE
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
GATE_NODE=TRUE
10%
10V
X7R-CERM
0201
69
C7582
1
2200PF
10%
10V
X7R-CERM
0201
2
2
PLACE_NEAR=U7400.43:1mm
376S1011
SIGNAL_MODEL=EMPTY
CPUIMVP_ISUM2_P
69
OUT
Additonal Input Bulk Caps
SIGNAL_MODEL=EMPTY
CRITICAL
THESE TWO CAPS ARE FOR EMC
Q7530
CRITICAL
649136PBF
S1
376S1014
PHASE 3
1
1
D
4
=PP5V_S0_CPUIMVP
CRITICAL
1
C7533
16V
POLY-TANT
2
CASE-D2E-SM
1
C7537
1
C7538
C7539
1
2
CASE-D2E-SM
10UF
1UF
0.001UF
10%
16V
X5R-CERM
0805
10%
16V
X5R
402
10%
50V
X7R
402
10%
50V
X7R
402
2
2
2
2
CRITICAL
1
C7570
0.001UF
10%
16V
X5R-CERM
0805
68UF
20%
2
CRITICAL
1
C7572
68UF
20%
16V
POLY-TANT
2
CRITICAL
1
C7571
68UF
CASE-D2E-SM
6
G
CRITICAL
1
C7536
10UF
20%
16V
POLY-TANT
2
CRITICAL
1
C7535
68UF
20%
2
CRITICAL
1
C7534
68UF
5
70 69 7
1
300
1%
1/20W
MF
201
NOSTUFF
PLACE_NEAR=U7400.43:1mm
CPUIMVP_ISUM1_P
69 70
C7522
SWITCH_NODE=TRUE
CPUIMVP_LGATE2
IN
2200PF
200
G
4
DIDT=TRUE
MIN_LINE_WIDTH=1.5 MM
MIN_NECK_WIDTH=0.2 MM
3
5
6
G
4
CPUIMVP_LGATE1
IN
69 70
OUT
C7512
0.001UF
S
69 6
1
649135PBF
SWITCH_NODE=TRUE
CPUIMVP_ISUM_N
DIDT=TRUE
Q7515
DIDT=TRUE
MIN_LINE_WIDTH=1.5 MM
MIN_NECK_WIDTH=0.2 MM
S
D
CPUIMVP_PHASE1
IN
OUT
OUT
69 6
D
4
CPUIMVP_ISNS2_P
NOSTUFF
DIDT=TRUE
=PPVCORE_S0_CPU_REG
2
3
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM
2.2
DIDT=TRUE
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
MF
0612
PPVCORE_S0_CPU_PH2
2
1
5%
1/10W
MF-LF
CRITICAL603
10%
50V
X7R
402
1%
R7522
CPUIMVP_UGATE2
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM
69 6
2
0.001UF
2
PLACE_NEAR=Q7510.7:1MM
PLACE_NEAR=C7527.1:3MM
R7520
152S1019
SWITCH_NODE=TRUE
10%
10V
CERM
402
2
0.00075
1
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM
0.22UF
2
CRITICAL
PPVCORE_S0_CPU_PH2_L
C7521
CPUIMVP_BOOT2
PLACE_NEAR=C7581.2:1mm
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM
1
0
46.4
2
R7521
CPUIMVP_ISNS1_N
OUT
SIGNAL_MODEL=EMPTY
6
1
7 70
4
OUT
NOSTUFF
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
=PPVCORE_S0_CPU_REG
2
CPUIMVP_ISNS1_P
2.2
5%
1/10W
MF-LF
603
2
0.36UH-20%-40A-0.00075OHM
MF
VOLTAGE=1.25V
10%
50V
X7R
402
C7529
0.001UF
10%
16V
X5R
402
L7520
1W
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM
1UF
10%
16V
X5R-CERM
0805
CRITICAL
DIDT=TRUE
1
1
C7528
10UF
DIRECTFET-SA
0612
2 PPVCORE_S0_CPU_PH1
1
1
2
8
7
IN
C7511
CPUIMVP_BOOT1
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM
69 6
1
PPVCORE_S0_CPU_PH1_L
S
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.25 MM
1%
0.36UH-20%-40A-0.00075OHM
6
1
6 CPUIMVP_BOOT2_RC
PLACE_NEAR=C7517.1:3MM
0.00075
3
R7510
CRITICAL
1
2
8
7
DIRECTFET-SA
1
C7527
10%
16V
X5R-CERM
0805
IRF6802SDTRPBF
CRITICAL
IRF6802SDTRPBF
S
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.25 MM
16V
POLY-TANT
2
1
C7526
10UF
20%
16V
POLY-TANT
CRITICAL
1
C7525
68UF
20%
2
CRITICAL
1
C7524
68UF
Q7510
D
CRITICAL
1
C7523
CRITICAL
376S1010
2
6 CPUIMVP_BOOT1_RC
THESE TWO CAPS ARE FOR EMC
NOSTUFF
CRITICAL
1
C7515
68UF
20%
2
CRITICAL
1
C7514
8
6
5
376S1010
CRITICAL
1
C7513
CRITICAL
7
CRITICAL
1
IN
1
=PPVIN_S0_CPUIMVP
69 7
69 6
2
68UF
20%
16V
POLY-TANT
2
CASE-D2E-SM
CRITICAL
1
C7574
68UF
20%
16V
POLY-TANT
2
CASE-D2E-SM
CRITICAL
1
C7573
68UF
20%
16V
POLY-TANT
2
CASE-D2E-SM
C7575
20%
16V
POLY-TANT
2
CASE-D2E-SM
16V
POLY-TANT
CASE-D2E-SM
CRITICAL
PLACE_NEAR=Q7530.2:1MM
6 CPUIMVP_BOOT3_RC
3
CRITICAL
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.25 MM
C
1
R7547
5
1
2
10K
VDD
5%
R75311
U7541
MAX17491
2
6
TQFN
PWN
BST
1
DH
8
LX
IN
5%
1/10W
MF-LF
603
7
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM
SKIP*
DIDT=TRUE
6 CPUIMVP_UGATE3
DIDT=TRUE
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.25V
101 69 50
3
1
1
CPUIMVP_ISNS3_P
50 101
OUT
R7533
SIGNAL_MODEL=EMPTY
CPUIMVP_PH3_SNUB
PLACE_NEAR=C7583.1:1mm
R7534
46.4
10.2
1%
1/20W
MF
201
1%
1/20W
MF
201
2
NOSTUFF
CRITICAL
GATE_NODE=TRUE
7 70
CPUIMVP_ISNS3_N
OUT
2.2
6 CPUIMVP_BOOT3
CRITICAL
152S1019
1
=PPVCORE_S0_CPU_REG
1
4
R7532
1
2
8
7
CPUIMVP_PWM3
CPUIMVP_SKIP3
69
VOLTAGE=1.25V
10%
10V
CERM
402
MF
2
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM
PIMA104E-SM
C
1W
0612
2 PPVCORE_S0_CPU_PH3
1
SWITCH_NODE=TRUE
0.22UF
2
PPVCORE_S0_CPU_PH3_L
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM
C7531
3.3
MF-LF
402
1
5%
1/16W
MF-LF
402 2
1/16W
2
6
SWITCH_NODE=TRUE
10%
16V
X5R
402
1%
0.36UH-20%-40A-0.00075OHM
1UF
PLACE_NEAR=C7537.1:3MM
0.00075
L7530
DIDT=TRUE
C7541
R7530
S
6
2
2
SIGNAL_MODEL=EMPTY
CPUIMVP_ISUM_N
PLACE_NEAR=C7583.2:1mm
DL
THRM
PAD
4
G
1
2
GATE_NODE=TRUE
R7536 1
10%
50V
CERM
402
376S1011
C7583
1
2200PF
300
1%
1/20W
MF
201
NOSTUFF
10%
10V
X7R-CERM
0201
2
2
PLACE_NEAR=U7400.43:1mm
3
5
6
AXG PHASE 1
SIGNAL_MODEL=EMPTY
CPUIMVP_ISUM3_P
=PPVIN_S0_CPUAXG
7
NOSTUFF
CRITICAL
AXG PHASE 2
R7556
1
6 CPUIMVP_BOOT1G_R
MIN_LINE_WIDTH=0.25 MM
THESE TWO CAPS ARE FOR EMC
MIN_NECK_WIDTH=0.2 MM
1
Q7550
D
68UF
1
G
DIRECTFET-SA
CASE-D2E-SM
IN
MIN_LINE_WIDTH=0.5 MM
DIDT=TRUE
GATE_NODE=TRUE
GATE_NODE=TRUE
10%
50V
X7R
402
16V
POLY-TANT
2
CASE-D2E-SM
2
2
2
IN
CPUIMVP_PHASE1G
IN
CPUIMVP_LGATE1G
D
DIDT=TRUE
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
Q7551
GATE_NODE=TRUE
6
G
2
VOLTAGE=1.05V
1
101 70 50
R7552
S
2
3
5
6
376S1011
1
2
C7540
OUT
5
R7540
2
10K
VDD
5%
10%
50V
CERM
402
1%
1/20W
MF
201
2
PLACE_NEAR=C7584.2:1mm
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM
69
IN
CPUIMVP_AXG_PWM2
2
BST
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM
CPUIMVP_SKIP2G
6
8
LX
THRM
PAD
9
3
4
G
4
2
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM
1
R7562
10.2
2
2
1%
1/20W
MF
201
SIGNAL_MODEL=EMPTY
CPUIMVP_ISUMG_N
PLACE_NEAR=C7567.2:1mm
OUT
PLACE_NEAR=C7584.1:1mm
376S1011
2
1
10%
50V
CERM
402
OUT
69 70
69
10%
10V
X7R-CERM
0201
PLACE_NEAR=U7400.10:1mm
CPUIMVP_ISUMG2_P
DIDT=TRUE
C7584
CPUIMVP_ISNS1G_P
IN
2200PF
1
C7530
2
0.22UF
2
10%
10V
CERM
402
10%
10V
X7R-CERM
0201
1
R7563
1
CPUIMVP_ISUMG1_P
1%
1/16W
MF-LF
402
69
DIDT=TRUE
50 70 101
Note: value needs scrubbing
R7564
200
200
PLACE_NEAR=U7400.10:1mm
2
1%
1/16W
MF-LF
402
CPUIMVP_ISUMG_AVE_P
2
OUT
69
SYNC_MASTER=J31_JACK
SYNC_DATE=11/11/2011
PAGE TITLE
MIN_LINE_WIDTH=0.5 MM
GATE_NODE=TRUE
MIN_NECK_WIDTH=0.2 MM
CPU IMVP7 & AXG VCore Output
1
R7566
DRAWING NUMBER
GATE_NODE=TRUE
0
DIDT=TRUE
SWITCH_NODE=TRUE
Apple Inc.
5%
1/16W
MF-LF
402
DIDT=TRUE
051-9585
R
NOSTUFF
1
70 69
5%
25V
NP0-C0G
0402
CPUIMVP_ISUMG_N
C7569
330PF
2
2
10%
50V
CERM
402
OUT
Note: value needs scrubbing
5
4
3
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
2
D
3.0.0
CPUIMVP_ISUMG_AVE_R_P
1
SIZE
REVISION
2
GATE_NODE=TRUE
6
69 70
C7567
2200PF
2
1000PF
7
7 49 70
50 101
C7585
C7568
8
1%
1/20W
MF
201
6
DIDT=TRUE
NOSTUFF
1
46.4
SIGNAL_MODEL=EMPTY
CPUIMVP_AXG2_SNUB
6 CPUIMVP_LGATE2G
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
=PPVCORE_S0_AXG_REG
CPUIMVP_ISNS2G_N
OUT
R7561 1
DIDT=TRUE
MIN_LINE_WIDTH=1.5 MM
MIN_NECK_WIDTH=0.2 MM
4
OUT
0.001UF
OUT
6 CPUIMVP_PHASE2G
2
3
PLACE_NEAR=C7567.1:1mm
5%
1/10W
MF-LF
603
DIRECTFET_S3C
DIDT=TRUE
7
DL
GND
101 50
6 CPUIMVP_UGATE2G
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
MF
0612
1
Note: value needs scrubbing
DH
SKIP*
1%
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.25 MM
1
CRITICAL
Q7561
649135PBF
SIGNAL_MODEL=EMPTY
CPUIMVP_ISUMG_N
6 CPUIMVP_BOOT2G
TQFN
PWN
2
6 CPUIMVP_BOOT2G_RC
3.3
U7542
PPVCORE_S0_AXG2_L
CPUIMVP_ISNS2G_P
DIDT=TRUE
5%
1/16W
MF-LF
402 2
B
OUT
6
R75351
MAX17491
A
D
10.2
1%
1/20W
MF
201
1
10%
16V
X5R
402
MF-LF
2
50 101
R7554
C7552
1/16W
402
1
10%
50V
X7R
402
PLACE_NEAR=C7564.1:3MM
2.2
7 49 70
CPUIMVP_ISNS1G_N
1UF
1
=PPVCORE_S0_AXG_REG
4
46.4
0.001UF
1
2
0.001UF
0.00075
VOLTAGE=1.05V
152S1019
376S1010
R7568
3
C7566
2
1W
OUT
SIGNAL_MODEL=EMPTY
2
PIMA104E-SM
SWITCH_NODE=TRUE
1
1
2
R7560
NOSTUFF
CPUIMVP_ISNS1G_P
2
CRITICAL
1
6 CPUIMVP_VSWG2
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM
CRITICAL
CPUIMVP_AXG1_SNUB
=PP5V_S0_CPUIMVP
DIRECTFET-SA
0612
R7553 1
5%
1/10W
MF-LF
603
NOSTUFF
70 69 7
G
MF
2.2
DIRECTFET_S3C
CASE-D2E-SM
2
0.36UH-20%-40A-0.00075OHM
1W
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM
PIMA104E-SM
NOSTUFF
SWITCH_NODE=TRUE
649135PBF
4
1
CPUIMVP_VSWG1
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM
2
1%
PPVCORE_S0_AXG1_L
2
10%
50V
X7R
402
L7560
Q7550
S
1
2
8
7
CRITICAL
69 6
D
R7550
0.36UH-20%-40A-0.00075OHM
SWITCH_NODE=TRUE
16V
POLY-TANT
0.001UF
10%
16V
X5R
402
CRITICAL
CRITICAL
0.00075
L7550
DIDT=TRUE
MIN_LINE_WIDTH=1.5 MM
MIN_NECK_WIDTH=0.2 MM
1
C7565
1UF
10%
16V
X5R-CERM
0805
PLACE_NEAR=Q7550.7:1MM
10%
50V
X7R
402
PLACE_NEAR=C7557.1:3MM
PLACE_NEAR=Q7550.5:1MM
CRITICAL
1
10UF
10%
16V
X5R-CERM
0805
0.001UF
2
CRITICAL
C7564
C7559
0.001UF
10%
16V
X5R
402
152S1019
69 6
1
C7558
1UF
376S1010
DIDT=TRUE
MIN_NECK_WIDTH=0.2 MM
1
C7557
10%
16V
X5R-CERM
0805
IRF6802SDTRPBF
S
MIN_NECK_WIDTH=0.2 MM
1
10UF
10%
16V
X5R-CERM
0805
4
69 6
C7556
10UF
20%
2
1
C7555
68UF
16V
POLY-TANT
2
1
C7554
20%
MIN_LINE_WIDTH=0.5 MM
CPUIMVP_UGATE1G
1
C7553
IRF6802SDTRPBF
2
8
10%
10V
CERM
402
CASE-D2E-SM
CRITICAL
7
B
CRITICAL
0.22UF
DIDT=TRUE
CRITICAL
3
402
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM
CRITICAL
1
2
8
7
CPUIMVP_BOOT1G
CRITICAL
2
1
C7563
10UF
20%
16V
POLY-TANT
CRITICAL
1
C7562
3
5
6
C7551
MF-LF
IN
1
6
DIDT=TRUE
5
1/16W
2
THESE TWO CAPS ARE FOR EMC
NOSTUFF
CRITICAL
1
C7561
68UF
20%
S
2
5%
CRITICAL
1
C7560
68UF
0
1
69 6
69
C7532
0.001UF
DIRECTFET_S3C
DIDT=TRUE
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
9
3
649135PBF
SWITCH_NODE=TRUE
6 CPUIMVP_LGATE3
69 70
DIDT=TRUE
S
GND
DIDT=TRUE
MIN_LINE_WIDTH=1.5 MM
MIN_NECK_WIDTH=0.2 MM
4
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM
Q7535
OUT
OUT
D
6 CPUIMVP_PHASE3
BRANCH
PAGE
75 OF 132
SHEET
70 OF 105
1
A
8
7
6
5
4
3
2
1
D
D
CPU VCCIO REGULATOR
7
7
=PPVIN_S0_CPUVCCIOS0
=PP5V_S0_CPUVCCIOS0
6
CPUVCCIOS0_BOOT_RC
CRITICAL
1
R7601 1
1
R7644
74
6
3
CPUVCCIOS0_FB
IN
6
FB
4
SREF
74
CRITICAL
1
1UF
2
C7622
1000PF
10%
25V
X5R
603-1
2
5%
25V
NP0-C0G
402
PLACE_NEAR=C7624.1:3mm
5
PLACE_NEAR=Q7630.5:1MM
C
CRITICAL
2
RJK0365DPA-01
CPUVCCIOS0_VBST
WPAK
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
DIDT=TRUE
1
CRITICAL
C7604
1
1
47PF
5%
50V
CERM
402
C7605
1
2
6
2
1
2
3
0.001
L7630
1%
1W
MF-1
0612
0.68UH-22A-2.7MOHM
1
CPUVCCIOS0_LL
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
SWITCH_NODE=TRUE
DIDT=TRUE
15
R7640
CRITICAL
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
GATE_NODE=TRUE
DIDT=TRUE
2
PIMB104T-SM
1
2
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
3
4
C7623
2
RTN
5
5%
25V
NP0-C0G
402
Q7635
6
1
CPUVCCIOS0_DRVL
4
G
RJK0208DPA
PGND
20%
2V 2
TANT
CASE-B4-SM
2
20.076A Max Output
f = 300 kHz
1
C7648
270UF
1
2
20%
2 2V
TANT
CASE-B4-SM
3
CPUVCCIOS0_CS_P
R7641
XW7600
OUT
49 101
CPUVCCIOS0_CS_N
1
OUT
49 101
3.24K
SM
1
1
270UF
CRITICAL
S
5%
1/16W
MF-LF
2 402
CPUVCCIOS0_AGND
C7649
7
Vout = 1.05V
PLACE_NEAR=R7640.1:1.5mm
WPAK
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
GATE_NODE=TRUE
DIDT=TRUE
FSEL
R7603
1
1000PF
CRITICAL
PGOOD
CPUVCCIOS0_RTN
10%
16V
X7R
402
2
NO STUFF
CRITICAL
5
0.047UF
5%
50V
CERM
402
=PPCPUVCCIO_S0_REG
PPCPUVCCIO_S0_REG_R
C7603
47PF
2
11
10
CPUVCCIOS0_DRVH
0
2.2UF
10%
16V
X5R
603
UGATE
6
D
GND
C7602
12
LGATE
9
CPUVCCIOS0_FSEL
1
1%
1/16W
MF-LF
402
BOOT
OCSET
R7645
& lt; Rb & gt;
B
VO
7
CPUVCCIOS0_PGOOD
OUT
2.74K
2
8
CPUVCCIOS0_OCSET
6
2
C7624
Q7630
6
PHASE
EN
CPUVCCIOS0_VO
6
1
10%
16V
X5R
402
4
PVCC
UTQFN
=CPUVCCIOS0_EN
CPUVCCIOS0_SREF
2.74K
2
1
20%
16V 2
POLY-TANT
CASE-D2E-SM
ISL95870
1%
1/16W
MF-LF
2 402
& lt; Ra & gt;
R7605 1
C7630
1UF
0
U7600
3.01K
1%
1/16W
MF-LF
402 2
1
1
68UF
16
1
3.01K
1%
1/16W
MF-LF
402
R7630
2
VCC
C7621
20%
16V 2
POLY-TANT
CASE-D2E-SM
14
CPU_VCCIOSENSE_N
R7604
1
5%
1/10W
MF-LF
603
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V
CRITICAL
1
68UF
20%
10V
X5R
603
PP5V_S0_CPUVCCIOS0_VCC
CPU_VCCIOSENSE_P
93 12
C
2
13
93 12
C7620
10UF
2.2
5%
1/16W
MF-LF
402
CRITICAL
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
DIDT=TRUE
C7601
1%
1/16W
MF-LF
402
2
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V
B
C7640
2
1000PF
2
PLACE_NEAR=U7600.1:1mm
1
5%
25V
NP0-C0G
402
(CPUVCCIOS0_OCSET)
1
R7642
3.24K
2
1%
1/16W
MF-LF
402
(CPUVCCIOS0_VO)
OCP = R7641 x 8.5uA / R7640
OCP = 27.54A
Vout = 0.5V * (1 + Ra / Rb)
A
SYNC_MASTER=J31_JACK
SYNC_DATE=09/19/2011
PAGE TITLE
CPU VCCIO (1V0R1V05 S0) POWER SUPPLY
DRAWING NUMBER
Apple Inc.
051-9585
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
3.0.0
BRANCH
PAGE
76 OF 132
SHEET
71 OF 105
1
A
8
72 7
7
6
5
4
3
2
1
1.8V S0 Regulator
=PP3V3_S5_P1V2P1V8
2
2
1
22UF
10%
25V
X5R
603-1
20%
6.3V
X5R-CERM-1
603
2
74
IN
OUT
L7720
1.0UH-7A
PIMB053T-SM
=PP1V8_S0_REG
ISL8014A
=P1V8S0_EN
5
P1V8S0_PGOOD
QFN
EN
CRITICAL
7
PG
4
74
152S1302
U7720
PLACE_NEAR=U7720.1:1MM
PLACE_NEAR=C7725.1:3MM
D
3
C7720
1UF
VDD
5%
25V
NP0-C0G
402
C7725
1
1
VIN
1
1000PF
2
CRITICAL
C7724
SYNCH
LX
LX
P1V8S0_SW
6
SWITCH_NODE=TRUE
DIDT=TRUE
15
1
THRM_PAD
6
13
C7723
1
47PF
R7720
NC
NC
NC
1
2
113K
1%
1/16W
MF-LF
402
5%
50V
CERM
402
C7721
22UF
2
Max Current = 4A
Freq = 1 MHz
20%
6.3V
X5R-CERM-1
603
1.05V SUS LDO
2
17
PGND
12
11
SGND
10
NC
P1V8S0_FB
6
16
D
Vout = 1.794V
CRITICAL
8
7
2
CRITICAL
1
VFB
9
14
& lt; Ra & gt;
Cougar Point-M requires JTAG pull-ups to be powered at 1.05V in Sus.
Pull-ups (3) must be 51 ohms to support XDP (not required in production).
70mA is required to support pull-ups. Alternative is strong voltage
dividers (200/100) to 3.3V Sus, which burns 100mW in all S-states.
CRITICAL
R7721 1
C7722
90.9K
1
CRITICAL
XDP_PCH
22UF
1%
1/16W
MF-LF
402 2
20%
6.3V
X5R-CERM-1
603
2
U7740
& lt; Rb & gt;
7
TPS720105
=PP3V3_SUS_P1V05SUSLDO
=PP1V05_SUS_LDO
SON
4
Vout = 0.8V * (1 + Ra / Rb)
6
IN
OUT
EN
NC
2
XDP_PCH
1
C
Max Current = 0.35A
NC
XDP_PCH
THRM
PAD
GND
1UF
10%
6.3V
CERM
402
Vout = 1.05V
1
3
C7740
7
BIAS
5
1
C7741
2.2UF
7
2
2
10%
6.3V
X5R
402
C
1.5V S0 Regulator
=PP1V5_S0_REG
7
=PP3V3_S5_P1V5S0
MAX CURRENT = 0.3A
1
CRITICAL
C7750
1
1
10uF
20%
6.3V
X5R
603
2
IN
F = 1MHZ
L7770
CRITICAL
10UH-0.55A-330MOHM
VI
U7710
PCAA031B-SM
1
=P1V5S0_EN
3
FB
EN
SOT23-5
2
2
SW
C7771
10uF
TPS62201
4
74
7
Vout = 1.5V
5
P1V5S0_SW
20%
6.3V
X5R
603
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
SWITCH_NODE=TRUE
DIDT=TRUE
GND
2
CAESAR IV 1.2V INT.VR CMPTS
CRITICAL
L7730
4.7UH-0.8A
36 24 7
1
=PP3V3_ENET_PHY
B
2
ENET_SR_LX
PCAA031B-SM
1
C7737
1
4.7UF
2
20%
6.3V
X5R
402
C7738
B
SWITCH_NODE=TRUE
DIDT=TRUE
0.1UF
2
36
MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.2V
10%
16V
X5R
402
ENET_SR_VFB
=PP1V2_S3_ENET_PHY
36
7
CRITICAL
1
1.2V S0 (GMUX) Regulator
=PP1V2_S0_REG
C7760
1
1
10uF
20%
6.3V
X5R
603
10%
16V
X5R
402
7
2
F = 1MHZ
L7760
CRITICAL
10UH-0.55A-330MOHM
VI
U7760
PCAA031B-SM
1
=P1V2S0_EN
3
FB
EN
2
SOT23-5
2
SW 5
GND
2
C7761
10uF
TPS62207
4
IN
C7736
0.1UF
2
MAX CURRENT = 0.3A
1
CRITICAL
74
20%
4V
X5R
402
Vout = 1.2V
=PP3V3_S5_P1V2P1V8
A
1
10UF
2
72 7
C7735
P1V2S0_SW
SYNC_MASTER=J31_JACK
20%
6.3V
X5R
603
SYNC_DATE=06/10/2011
PAGE TITLE
Misc Power Supplies
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
SWITCH_NODE=TRUE
DIDT=TRUE
DRAWING NUMBER
Apple Inc.
051-9585
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
3.0.0
BRANCH
PAGE
77 OF 132
SHEET
72 OF 105
1
A
8
7
6
5
4
3
2
1
NOSTUFF
R7803
0
1
376S0945
3.3V S4 FET
3.3V_SUS FET
2
CRITICAL
5%
1/16W
MF-LF
402
CRITICAL
Q7820
SIA427DJ
1
4
SIA427DJ
D
=PP3V3_S5_P3V3SUSFET
7
S
7
SC70-6L
Q7800
=PP3V3_SUS_FET
7
SSM6N37FEAPE
D
7
3
220K
0.033UF
SOD-VESM-HF
MF-LF
402
2
X5R
CHANNEL
74
IN
1
G
S
1
74
RDS(ON)
10%
MF-LF
RDS(ON)
10%
26 mOhm @1.8V
LOADING
5%
100? mA (EDP)
16V
CERM
402
1/16W
26 mOhm @1.8V
LOADING
5%
1/16W
2
=P3V3S4_EN
P-TYPE 8V/5V
4
=P3V3SUS_EN
IN
2
402
2
SiA427
CHANNEL
0.01UF
1
P3V3SUS_SS
2
P-TYPE 8V/5V
0.01UF
P3V3S3_S4
2
1
SiA427
P3V3SUS_EN_L
D
MOSFET
C7820
R7820
MOSFET
C7800
2
P3V3S4_EN_L
S
3.3V SUS FET
2
5
402
5.1K
G
2
402
12K
R7800
1
X5R
402
3.3V S4 FET
10%
16V
5%
1/16W
10%
16V
MF-LF
G
D
3
SOT563
1
0.033UF
5%
1/16W
1
3
SSM3K15FV
D
R7802
C7809
1
C7821
100K
Q7822
Q7802
1
G
=PP3V3_S4_FET
R7822
3
D
1
4
S
7
SC70-6L
=PP3V3_S4_P3V3S4FET
7
0.7? A (EDP)
16V
MF-LF
CERM
402
402
5V_SUS FET
CRITICAL
Q7840
SIA413DJ
1
CRITICAL
D
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.1 MM
VOLTAGE=5V
S
PP5V_S5_P5VSUSFET_R
4
3.3V S3 FET
7
SC70-6L
73
=PP5V_SUS_FET
7
Q7810
D
6
C7841
10%
16V
5%
1
D
S
4
1/16W
SOT563
=PP3V3_S3_FET
X5R
MF-LF
7
1
0.033UF
220K
Q7822
7
1
G
SSM6N37FEAPE
SC70-6L
=PP3V3_S3_P3V3S3FET
7
R7842
5V SUS FET
3
SIA427DJ
2
402
402
MOSFET
C7840
2
R7840
C7811
0.033UF
10%
16V
1/16W
SOT563
X5R
MF-LF
402
2
3.3V S3 FET
S
G
P3V3S3_EN_L
1
P5VSUS_EN_L
1
P3V3S3_SS
2
402
P-TYPE 8V/5V
RDS(ON)
26 mOhm @1.8V
LOADING
3 A (EDP)
CRITICAL
2
5%
C
10%
MF-LF
3.3V S0 GPU FET
Q7870
SIA427DJ
16V
C
SC70-6L
CERM
402
2 mA (EDP)
16V
CERM
0.01UF
1/16W
29 mOhm @4.5V
LOADING
10%
SiA427
CHANNEL
P-TYPE 12V
RDS(ON)
5%
1/16W
1
=P3V3S3_EN
P5VSUS_SS
1
402
=PP3V3_GPU_P3V3GPUFET
=PP3V3_S0GPU_FET
4
7
7
2
S
MF-LF
MOSFET
C7810
47K
IN
G
=P5VSUS_EN
IN
402
2
402
2
R7810
74
74
CHANNEL
2
7
1
5%
1
D
100K
2
S
6
G
D
1
3
R7812
SSM6N37FEAPE
Q7812
1
SiA413
0.01UF
3.3K
1
3.3V S0 GPU FET
1
C7871
CERM
MF-LF
7
=PPVIN_S3_P1V5S3RS0_FET
402
2
402
R7870
C7801
1
CERM
1
SSM3K15FV
0.11A (EDP)
10%
16V
MF-LF
3
CERM
402
402
APN 376S0651
5
402
2
5%
1/16W
D
SOD-VESM-HF
VCC
2
1
P3V3GPU_SS
2
Q7872
0.1UF
20%
10V
1
26 mOhm @1.8V
LOADING
0.01UF
1K
P3V3GPU_EN_L
P-TYPE 8V/5V
RDS(ON)
C7870
2
=PP5V_S5_P1V5S3RS0FET
SiA427
3
10%
16V
1/16W
MOSFET
CHANNEL
0.22UF
51K
5%
7
1
G
R7872
1.5V S3/S0 FET
U7801
SLG5AP020
26
P1V5CPU_EN
IN
2
D
5
G
SHDN*
7
92
Q7801
R7801
CRITICAL
3
CRITICAL
D
TDFN
ON
0
P1V5S3RS0FET_GATE
1
4
2
G
S
PG
1UF
10%
X5R
2
4
S
2
CRITICAL
Q7830
S
8
SI7615DN
PWRPK-1212-8
1
2
=PP1V5_S3RS0_FET
3
SYM-VER-2
7
THRM
PAD
GND
402
G
7
S
3
=PP3V3_S0_P3V3S0FET
9
10V
5%
1/16W
MF-LF
402
6
1
PWRPK-1212-8-HF
P1V5S3RS0FET_GATE_R
NO STUFF
C7802 1
=P3V3GPU_EN
IN
SI7108DN
D
2
5
=PP3V3_S0_FET
7
1
1.5V S3/S0 FET
R7832
1
C7831
B
OUT
92
SI7108DN
CHANNEL
N-TYPE
1/16W
X5R
MF-LF
402
3.3V S0 FET
4
10%
16V
5%
MOSFET
G
0.033UF
47K
P1V5S3RS0_RAMP_DONE
1
B
2
SWITCH
SI7615DN
CHANNEL
402
P-TYPE 20V/12V
C7830
2
R7830
0.01UF
33K
RDS(ON)
P3V3S0_EN_L
6 mOhm @4.5V
LOADING
5 A (EDP)
1
2
1
P3V30S0_SS
2
RDS(ON)
5.5 mOhm @4.5V
LOADING
5.6 A (EDP)
5%
1.8V GPU FET
1/16W
MF-LF
SSM6N37FEAPE
D
10%
16V
3
CERM
402
402
Q7812
73 7
=PP3V3_S0_P1V8GPUFET
SOT563
C7880
1
74
0.1UF
CERM
IN
=P3V3S0_EN
5
1.8V GPU FET
353S3256
G
S
4
2
20%
10V
PLACE_NEAR=U7880.2:2.54mm
2
VCC
402
MOSFET
NCP4543
CHANNEL
N-TYPE
CRITICAL
U7880
NCP4543IMN5RG-A
RDS(ON)
QFN
6
73 7
=PP1V8_GPU_FET
Q7860
SI7615DN
PWRPK-1212-8
18 mOhm @4.5V
SYM-VER-2
4
CRITICAL
7
LOADING
5
2.4A (EDP)
7
SOURCE
load side
8
3
=PP5V_S3_P5VS0FET
9
DRAIN
13
R_BLEED
15
EN
2
10
IN
=P1V8GPU_EN
16
=PP3V3_S0_P1V8GPUFET
12
=PP1V8_S0_GPUFET
1
C7861
1/16W
X5R
CERM
402
NO STUFF
17
GPUFET_C_SR
18
1
P5V0S0_EN_L
5V_SUS FET inuot filter
GND
Q7865
R7843
THRM
PAD
5%
25V
7 =PP5V_S5_P5VSUSFET
1
1
2
402
7 73
1
2
D
3
10%
16V
CERM
402
SYNC_MASTER=J31_MARY
PP5V_S5_P5VSUSFET_R
SYNC_DATE=05/05/2011
PAGE TITLE
402
PLACE_NEAR=Q7840.4:5mm
C7843
Power FETs
73
1
74
2.2UF
20%
10V
X5R-CERM
IN
Apple Inc.
=P5VS0_EN
1
G
S
2
R
NOTICE OF PROPRIETARY PROPERTY:
402
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
U7880 default Turn on delay EN-- & gt; on is 200~650us.
6
5
051-9585
4
3
2
SIZE
D
REVISION
3.0.0
2
NO STUFF
7
P5V0S0_SS
DRAWING NUMBER
MF-LF
=PP1V8_GPU_FET
8
8 A (EDP)
5%
1/16W
MF-LF
SOD-VESM-HF
2
1/16W
NO STUFF
0.01UF
5%
2
402
5.5 MOHM @4.5V
LOADING
C7860
0
1000PF
NP0-C0G
RDS(ON)
10K
SSM3K15FV
C7882
P-TYPE 20V/12V
2
R7860
C_SR
2
SI7615DN
CHANNEL
4
2
NC
NC
19
20%
10V
NC
1
0.1UF
3
C7881
7
G
402
402
A
=PP5V_S0_FET
1
10%
16V
MF-LF
C_DELAY
5
0.033UF
220K
7
input side
EN_POL_CTRL
14
1
GPUFET_C_DELAY
D
MOSFET
11
5%
73 7
5.0V S0 FET
1
R7862
92
S
BRANCH
PAGE
78 OF 132
SHEET
73 OF 105
1
A
8
7
6
5
4
3
2
1
3.3V,5V S3 ENABLE
S5 Rail Enables & PGOOD
State
SMC_PM_G2_ENABLE
PM_SLP_S5_L
PM_SLP_S4_L
CHGR VFRQ Generation
PM_SLP_S3_L
1
1
1
1
Sleep (S3)
1
1
0
1
1
0
=PP3V42_G3H_CHGR
0
0
65 7
PM_SLP_S4_L:100K pull down in PCH page
2
Run (S0)
Deep Sleep (S4)
1
2
P3V3S5_EN
MAKE_BASE=TRUE
1
OUT
0
0
0
0
Deep Sleep (S5)
=P3V3S5_EN
MAKE_BASE=TRUE
5%
1/16W
MF-LF
402
0
0
2
5.1K
CHGR_VFRQ
1
D
C7942
2
OUT
65
D
3.3K
TPAD_VBUS_EN
P3V3S3_EN
VFRQ High: Variable Frequency
73
=DDRREG_EN
OUT
68
NO STUFF
1
3.3V/5.0V Sus ENABLE
100K
2
G
S
C7910
2
1
C7912
0.47UF
PM_SLP_S3_R_L
=USB_PWR_EN
OUT
42
0.47UF
10%
6.3V
2
10%
6.3V
2
CERM-X5R
CERM-X5R
402
402
PLACE_NEAR=U7940.1:2.3mm
1
0.1uF
46 45
IN
U7940
74AUP1G3208
SOT891
1
SMC_BATLOW_L
R7974
74 45 26 17 6
A
2
5%
1/16W
MF-LF
402
CPUIMVP_VR_ON
69
OUT
17
IN
Y
4 49 PM_SUS_EN
=P5VSUS_EN
PM_SLP_S3_R_L
=P5VS0_EN
=P3V3SUS_EN
GND
R7943
R7987
2
73
R7981
2
OUT
5%
1/16W
MF-LF
402
73
1
1
R7982
20K
5%
1/16W
MF-LF
402
1
R7985
2
R7988
20K
20K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
1
5%
1/16W
MF-LF
402
NO STUFF
OUT
=TBT_S0_EN
49
88
OUT
PLACE_NEAR=U7720.5:6mm
100K
2
73
=PBUSVSENS_EN
5.1K
5%
1/16W
MF-LF
402
73
OUT
R7986
10K
5%
1/16W
MF-LF
402
1
2
OUT
=P3V3S0_EN
33K
C
PLACE_NEAR=U7400.7:5mm
(PM_SLP_S3_R_L)
MAKE_BASE=TRUE
OUT
MAKE_BASE=TRUE
6
PM_SLP_SUS_L
R7978
100 2
1
5%
1/16W
MF-LF
402
PM_SLP_SUS_L:100K pull down on PCH page
1
PM_SLP_S3_L
IN
B
3
0
PM_SLP_S3_L:100K pull down in PCH page
VCC
SMC_BATLOW_L:100K pull up on SMC page
CPUVCORE ENABLE
S0 ENABLE
5
2
2
20%
10V
CERM
402
1
OUT
MAKE_BASE=TRUE
C7940
SMC-- & gt; PM_DSW_PWRGD
45
2
S5_PWRGD
1
P3V3S5_PGOOD
ALL_SYS_PWRGD
1
74
1
=PP3V3_S5_PWRCTL
74 7
S5_PWRGD (old name RSMRST_PWRGD)-- & gt; SMC
92 89 74 45 23
OUT
MAKE_BASE=TRUE
5%
1/16W
MF-LF
402
D
=P3V3S3_EN
DDRREG_EN
NO STUFF
R7941
53
OUT
MAKE_BASE=TRUE
PLACE_NEAR=U7201.20:7mm
67
5%
1/16W
MF-LF
402
PLACE_NEAR=Q7812.2:6mm
VFRQ Low: Fix Frequency
3
SOD-VESM-HF
67
OUT
R7913
R7912
5%
1/16W
MF-LF
402
1
PLACE_NEAR=U7300.16:6mm
SSM3K15FV
10%
50V
CERM
402
2
5%
1/16W
MF-LF
402
1
Q7931
0.0033UF
=PP3V42_G3H_PWRCTL
R7911
0
67
Battery Off (G3Hot)
PLACE_NEAR=U7201.21:7mm
7
5%
1/16W
MF-LF
402
1
SMC_PM_G2_EN
IN
=P5VS3_EN
PLACE_NEAR=U5701.4:6mm
2
R7940
100
46 45
(PM_SLP_S4_L)
PM_SLP_S4_L
MAKE_BASE=TRUE
1
OUT
IN
100K
0
67
=P5VS5_EN
45 32 26 17
R7931
PLACE_NEAR=U7100.15:6mm
PLACE_NEAR=U7600.3:6mm
P1V8S0_EN
=P1V8S0_EN
OUT
72
=P1V5S0_EN
OUT
72
=P1V2S0_EN
PLACE_NEAR=U7760.4:6mm
OUT
72
MAKE_BASE=TRUE
2
P1V5S0_EN
MAKE_BASE=TRUE
R7917
0 2
1
C
P1V2S0_EN
MAKE_BASE=TRUE
C
5%
1/16W
MF-LF
402
PCHVCCIOS0_EN
MAKE_BASE=TRUE
CPUVCCIOS0_EN
=CPUVCCIOS0_EN
OUT
71
=PVCCSA_EN
S0 Rail PGOOD (BJT Version)
=PP3V3_S5_VMON
OUT
66
MAKE_BASE=TRUE
7
=PP3V3_S0_VMON
R7956 1
1%
1/16W
MF-LF
402
15.0K
2
Q1
=PP1V5_S0_VMON
1K
2
7
Q3
CRITICAL
2
NC
5
Sus_PGOOD_CT
B
CT
U7930 RESET*
TPS3808G33DBVRG4
SOT23-6
MR*
C7931
1
C7985
2
3
353S2809
0.47UF
1UF
10%
6.3V
10%
6.3V
CERM-X5R
402
10%
6.3V
2
CERM-X5R
2
CERM-X5R
402
2
CERM-X5R
402
1
OUT
17
NC
ENET Enable Generation
3.3V ENET FET
CRITICAL
Q7922
NTR4101P
=PP3V3_ENET_FET
=PP3V3_S3_P3V3ENETFET
7
100
2
R7921
2
1
1
74 7
R7967 1
5%
1/16W
MF-LF
402 2
2
R7922
PM_SLP_S3_ENET
=PP3V3_S5_PWRCTL
1
C7970
100K
10%
10V
X5R-CERM
0201
1
2
1
SSM3K15FV
0.01UF
100
1
P5VS3_PGOOD
IN
S0PGOOD_ISL
1
R7972
" WLAN " = ( " S3 " & & " AP_PWR_EN " & & ( " AC " || " S0 " ))
D
S
NOTE: S3 term is guaranteed by S3 pull-up
on open-drain AP_PWR_EN signal.
3
2
SOT891
4
PM_WLAN_EN_L
P3V3_S4_EN
MAKE_BASE=TRUE
1
74 45 26 17 6
=P3V3S4_EN
OUT
8
3 V2MON
5 V3MON
6 V4MON
15.0K
(IPU)
MR*
1
IN
CRITICAL
GND
5%
R7963
8
1
ALL_SYS_PWRGD_R
2
7
(AC_EN_L)
AC_EN_L
2
18 23 32
SOT-363
6
2
=TBTAPWRSW_EN
OUT
Q7920
23 45 74 89 92
IN
SMC_ADAPTER_EN
2
G
S
1
5%
1/16W
MF-LF
402 2
D
2N7002DW-X-G
0
46 45 17
Power Control 1/ENABLE
3
NO STUFF
R7929 1
D
88
DRAWING NUMBER
SOT-363
5
G
Apple Inc.
S
5%
1/16W
MF-LF
402
4
3
051-9585
R
4
NOTICE OF PROPRIETARY PROPERTY:
2
SIZE
D
REVISION
3.0.0
(PM_SLP_S3_L)
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
ALL_SYS_PWRGD
5
SYNC_DATE=06/06/2011
PAGE TITLE
2N7002DW-X-G
100
6
SYNC_MASTER=J31_MARY
Q7920
402
R7962
353S2310
IN
4
S0PGOOD_ISL
330
AP_PWR_EN
1
PLACE_NEAR=Q7802.2:5mm
(SMC_S4_WAKESRC_EN)
THRM_PAD
G
S
R7919
0 MF-LF
2
OUT
RST*
G
1/16W
1
5%
1/16W
MF-LF
402
NC
5
2
NOSTUFF
1
PVCCSA_PGOOD
SOT-363
S
SOT-363
WOL_EN
Q7925
D
D
2N7002DW-X-G
IN
32
OUT
2N7002DW-X-G
Q7925
73
MAKE_BASE=TRUE
2
TDFN
P1V05_VID_VMON
1%
1/16W
MF-LF
402
66
ISL88042IRTEZ
2
G
6
3
NC
IN SMC_S4_WAKESRC_EN
100
1
IN
1
PM_SLP_S3_L
3
46 45
5%
1/16W
MF-LF
402
U7960
R7973
2
71
VDD
4
1%
1/16W
MF-LF
402
IN
NC
R7964
CPUVCCIOS0_PGOOD
2
9
1%
1/16W
MF-LF
402
S0PGOOD_ISL
1
10K
1
10%
16V
CERM
402
74LVC1G32
2
19
7
20%
10V
CERM
402
P1V5_DIV_VMON
R7971
2
PM_SLP_S5_L
1
6.04K
S0PGOOD_ISL
1
15.0K
1%
1/16W
MF-LF
402
IN
2
5%
1/16W
MF-LF
402
0.1uF
P5V_DIV_VMON
R7961
45 17
5
=PP3V3_S0_VMON
2
=PP1V05_S0_VMON
S0PGOOD_ISL
1
S0PGOOD_ISL
1
2
U7970
6
2
5%
1/16W
MF-LF
402
R7965
C7960
2
C7922
P3V3ENET_SS
2
Q7921
2
100
P1V8S0_PGOOD
IN
S0PGOOD_ISL S0PGOOD_ISL
2
1
0.1UF
=PP1V5_S0_VMON
10K
B
7
3
G
10%
16V
X5R
402
5%
1/16W
MF-LF
402
PLACE_NEAR=U7970.6:3mm
10K
C7921
0.033UF
10K
=PP3V3_S0_PWRCTL
=PP5V_S0_VMON
1%
1/16W
MF-LF
402
D
3.3V/5.0V S4 ENABLE
5%
1/16W
MF-LF
402
R7966
72
67
R7970
S
PLACE_NEAR=Q7802.2:5mm
74 7
1%
1/16W
MF-LF
402
CERM-X5R
402
SOT-23-HF
Thresholds:
VDD:
2.734V-3.010V
V2MON: 2.815V-3.099V
V3MON: 0.572V-0.630V
V4MON: 0.572V-0.630V
6.04K
10%
6.3V
402
PM_RSMRST_L goes to U1800.C21
3
SOD-VESM-HF
R7960
0.47UF
2
CERM-X5R
2
PM_RSMRST_L
R7957 1
5%
1/16W
MF-LF
402
A
2
Worst-Case Thresholds:
(ISL Version in development)
74 7
C7986
0.47UF
10%
6.3V
NO STUFF
S0PGD_BJT_GND_R
S0 Rail PGOOD Circuitry
74 7
PLACE_NEAR=U7720.5:6mm
1
C7988
0.47UF
402
PM_SLP_S5_L:100K pull down on PCH page
S0PGOOD_ISL
1
1
20%
50V
CERM
402
2
Q2: 0.XXXV
Q3: 0.640V
3.3V w/Divider: 2.345V
Q4: 0.660V
7
PLACE_NEAR=U7710.2:6mm
PLACE_NEAR=U7760.4:6mm
1
C7982
10%
6.3V
GND
Q4
VMON_Q4_BASE
2
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
PLACE_NEAR=U7800.3:6mm
1
C7981
0.47UF
1
100K
2
PLACE_NEAR=U7600.3:6mm
1
C7987
0.001UF
1K
1
SENSE
4
=PP3V3_SUS_CNTRL
R7955
=PP1V05_S0_VMON
R7933
VDD
74 7
1
74 7
1
8
NC
VMON_Q3_BASE
5%
1/16W
MF-LF
402
PP1V5_S0
CRITICAL
ASMCC0179
Q2
20%
10V
CERM
402
PLACE_NEAR=U7100.15:6mm
7 74
1
0.1uF
U7930 Sense input
threhold is 3.07V
DFN2015H4-8
R7954
1
C7930
No stuff C7931, 12ms
Min delay time
Q7950
5
1%
1/16W
MF-LF
402
=PP3V3_SUS_CNTRL
PLACE_NEAR=U7930.6:2.3mm
VMON_Q2_BASE
5%
1/16W
MF-LF
402
R7952
74 7
=PP3V3_S5_PWRCTL
2
1K
1
MAKE_BASE=TRUE
74 7
R7953
7.15K
2
23 45 74 89 92
S0PGD_C
VMON_3V3_DIV
1
ALL_SYS_PWRGD
2
4
2
1%
1/16W
MF-LF
402
PVCCSA_EN
3.3V SUS Detect
150K
R7951
6
1
6
74 7
BRANCH
PAGE
79 OF 132
SHEET
74 OF 105
1
A
8
7
6
5
4
3
2
1
OMIT_TABLE
Page Notes
U8000
Power aliases required by this page:
NV-GK107
- =PP3V3_GPU_VDD33
BGA
(1 OF 10)
93 92 75 6
93 92 75 6
PEG_R2D_P & lt; 0 & gt;
PEG_R2D_N & lt; 0 & gt;
AN12
PEG_R2D_P & lt; 1 & gt;
PEG_R2D_N & lt; 1 & gt;
AN14
PEG_R2D_P & lt; 2 & gt;
PEG_R2D_N & lt; 2 & gt;
AP14
PEG_R2D_P & lt; 3 & gt;
PEG_R2D_N & lt; 3 & gt;
AN15
PEG_R2D_P & lt; 4 & gt;
PEG_R2D_N & lt; 4 & gt;
AN17
PEG_R2D_P & lt; 5 & gt;
PEG_R2D_N & lt; 5 & gt;
AP17
PEG_R2D_P & lt; 6 & gt;
PEG_R2D_N & lt; 6 & gt;
AN18
PEG_R2D_P & lt; 7 & gt;
PEG_R2D_N & lt; 7 & gt;
AN20
AM12
PEX_RX0
PEX_RX0*
PEX_TX0
PEX_TX0*
AK14
PEX_RX1
PEX_RX1*
PEX_TX1
PEX_TX1*
AH14
PEX_RX2
PEX_RX2*
PEX_TX2
PEX_TX2*
AK15
PEX_RX3
PEX_RX3*
PEX_TX3
PEX_TX3*
AL16
PEX_RX4
PEX_RX4*
PEX_TX4
PEX_TX4*
AK17
PEX_RX5
PEX_RX5*
PEX_TX5
PEX_TX5*
AH17
PEX_RX6
PEX_RX6*
PEX_TX6
PEX_TX6*
AK18
PEX_RX7
PEX_RX7*
PEX_TX7
PEX_TX7*
AL19
PEX_RX8
PEX_RX8*
PEX_TX8
PEX_TX8*
AK20
PEX_RX9
PEX_RX9*
PEX_TX9
PEX_TX9*
AH20
PEG_D2R_C_P & lt; 0 & gt;
PEG_D2R_C_N & lt; 0 & gt;
AJ14
6 75 93
6 75 93
Signal aliases required by this page:
(NONE)
BOM options provided by this page:
93 75 6
(NONE)
93 75 6
AM14
PEG_D2R_C_P & lt; 1 & gt;
PEG_D2R_C_N & lt; 1 & gt;
AG14
6 75 93
6 75 93
D
D
93 8
93 8
93 8
93 8
93 8
93 8
93 8
93 8
93 8
93 8
C
93 8
93 8
93 8
93 8
93 8
93 8
IN
PEG_R2D_C_P & lt; 0 & gt;
IN
PEG_R2D_C_N & lt; 0 & gt;
IN
PEG_R2D_C_P & lt; 1 & gt;
2
C8021
0.22UF
1
C8022
0.22UF
C8023
0.22UF
1
PEG_R2D_C_P & lt; 2 & gt;
1
0.22UF
1
IN
PEG_R2D_C_N & lt; 2 & gt;
IN
PEG_R2D_C_P & lt; 3 & gt;
0.22UF
1
6.3V
0.22UF
1
IN
PEG_R2D_C_N & lt; 3 & gt;
IN
PEG_R2D_C_P & lt; 4 & gt;
IN
PEG_R2D_C_N & lt; 4 & gt;
IN
PEG_R2D_C_P & lt; 5 & gt;
0.22UF
1
6.3V
0.22UF
1
6.3V
0.22UF
1
0.22UF
1
6.3V
IN
PEG_R2D_C_N & lt; 5 & gt;
IN
PEG_R2D_C_P & lt; 6 & gt;
0.22UF
1
0.22UF
1
6.3V
PEG_R2D_C_N & lt; 6 & gt;
0.22UF
C8034
0.22UF
1
1
6.3V
PEG_R2D_C_N & lt; 7 & gt;
0.22UF
1
X5R
0201
6.3V
X5R
0201
6.3V
X5R
0201
6.3V
X5R
0201
6.3V
X5R
0201
6.3V
X5R
0201
6.3V
X5R
0201
6.3V
X5R
0201
6.3V
X5R
0201
2
6 75 93
93 75 6
93 75 6
6 75 92 93
93 92 75 6
93 92 75 6
6 75 93
93 75 6
93 75 6
PEG_R2D_N & lt; 4 & gt;
2
6 75 92 93
93 92 75 6
93 92 75 6
PEG_R2D_N & lt; 5 & gt;
20%
AP18
AM18
AM20
6 75 92 93
PEG_R2D_N & lt; 7 & gt;
2
PEG_D2R_C_P & lt; 4 & gt;
PEG_D2R_C_N & lt; 4 & gt;
AJ17
6 75 93
6 75 93
PEG_D2R_C_P & lt; 5 & gt;
PEG_D2R_C_N & lt; 5 & gt;
AG17
6 75 93
6 75 93
PEG_D2R_C_P & lt; 6 & gt;
PEG_D2R_C_N & lt; 6 & gt;
AJ18
6 75 93
6 75 93
PEG_D2R_C_P & lt; 7 & gt;
PEG_D2R_C_N & lt; 7 & gt;
AK19
6 75 93
C
6 75 93
6 75 93
PEG_R2D_P & lt; 7 & gt;
2
AM17
6 75 93
PEG_R2D_N & lt; 6 & gt;
2
6 75 93
6 75 92 93
PEG_R2D_P & lt; 6 & gt;
2
6 75 93
6 75 93
PEG_R2D_P & lt; 5 & gt;
2
PEG_D2R_C_P & lt; 3 & gt;
PEG_D2R_C_N & lt; 3 & gt;
AK16
6 75 92 93
PEG_R2D_P & lt; 4 & gt;
2
AM15
6 75 93
PEG_R2D_N & lt; 3 & gt;
2
6 75 93
6 75 93
PEG_R2D_P & lt; 3 & gt;
20%
C8035
0201
2
20%
PEG_R2D_C_P & lt; 7 & gt;
X5R
93 92 75 6
PEG_R2D_N & lt; 2 & gt;
20%
C8033
0201
2
20%
C8032
X5R
93 92 75 6
PEG_R2D_P & lt; 2 & gt;
2
20%
C8031
0201
6 75 93
PEG_R2D_N & lt; 1 & gt;
20%
C8030
X5R
6 75 93
0201
2
20%
C8029
X5R
PEG_D2R_C_P & lt; 2 & gt;
PEG_D2R_C_N & lt; 2 & gt;
AJ15
6 75 92 93
PEG_R2D_P & lt; 1 & gt;
20%
C8028
0201
2
20%
C8027
X5R
AP15
0201
93 75 6
PEG_R2D_N & lt; 0 & gt;
20%
C8026
X5R
6 75 92 93
0201
6.3V
20%
C8025
X5R
2
20%
C8024
93 75 6
PEG_R2D_P & lt; 0 & gt;
6.3V
20%
IN
IN
1
20%
PEG_R2D_C_N & lt; 1 & gt;
IN
0.22UF
20%
IN
IN
C8020
6 75 92 93
NC
NC
NC
NC
AP20
AP21
AN21
AM21
NC
NC
AJ20
NC
NC
AG20
=PP3V3_GPU_VDD33
83 82 81 7
1
NC
NC
NC
NC
AN23
AM23
AP23
AP24
PEX_RX10
PEX_RX10*
PEX_TX10
PEX_TX10*
AK21
PEX_RX11
PEX_RX11*
PEX_TX11
PEX_TX11*
AL22
PEX_RX12
PEX_RX12*
PEX_TX12
PEX_TX12*
AK23
PEX_RX13
PEX_RX13*
PEX_TX13
PEX_TX13*
AH23
PEX_RX14
PEX_RX14*
PEX_TX14
PEX_TX14*
AK24
PEX_RX15
PEX_RX15*
PEX_TX15
PEX_TX15*
AL25
NC
NC
AJ21
R8001
10K
1%
1/20W
MF
2 201
PEX_CLKREQ_L_R
NC
NC
AK22
82 75
Note: Removed GND voids from AC caps for layout (J31).
NC
NC
NC
NC
B
93 75 6
PEG_D2R_C_P & lt; 0 & gt;
C8055
0.22UF
C8056
0.22UF
1
2
20%
93 75 6
PEG_D2R_C_N & lt; 0 & gt;
1
20%
93 75 6
PEG_D2R_C_P & lt; 1 & gt;
93 75 6
PEG_D2R_C_N & lt; 1 & gt;
C8057
0.22UF
C8058
0.22UF
1
6.3V
X5R
OUT
8 93
AN26
AM26
NC
NC
AJ23
NC
NC
AG23
B
8 93
0201
2
20%
OUT
PEG_D2R_N & lt; 1 & gt;
X5R
8 93
0201
6.3V
OUT
PEG_D2R_P & lt; 1 & gt;
X5R
AM24
8 93
0201
6.3V
OUT
PEG_D2R_N & lt; 0 & gt;
X5R
2
20%
1
PEG_D2R_P & lt; 0 & gt;
6.3V
2
AN24
0201
NC
NC
NC
NC
AP26
AP27
AN27
AM27
NC
NC
AJ24
NC
NC
AK25
NOSTUFF
R8002
200
1
93 75 6
PEG_D2R_C_P & lt; 2 & gt;
C8059
0.22UF
1
2
20%
PEG_D2R_P & lt; 2 & gt;
6.3V
X5R
0201
OUT
96
8 93
96 16
93 75 6
PEG_D2R_C_N & lt; 2 & gt;
C8060
0.22UF
1
2
20%
PEG_D2R_N & lt; 2 & gt;
6.3V
X5R
0201
OUT
IN
PEG_D2R_C_P & lt; 3 & gt;
C8061
0.22UF
1
2
20%
93 75 6
PEG_D2R_C_N & lt; 3 & gt;
93 75 6
PEG_D2R_C_P & lt; 4 & gt;
93 75 6
PEG_D2R_C_N & lt; 4 & gt;
C8062
0.22UF
1
0.22UF
82 8
OUT
8 93
OUT
8 93
PEG_D2R_P & lt; 4 & gt;
OUT
OUT
PEG_D2R_P & lt; 5 & gt;
OUT
OUT
GPU_RESET_R_L
2
8 93
OUT
IN
0
20%
X5R
0201
6.3V
X5R
0201
6.3V
X5R
PEX_TERMP
AP29
AK26
96
PEX_TSTCLK_O_N
PEX_RST*
R8005
2.49K
8 93
0201
6.3V
AJ12
8 93
PEG_D2R_N & lt; 5 & gt;
X5R
2
PEX_TSTCLK_OUT
PEX_TSTCLK_OUT*
8 93
0201
PEG_D2R_N & lt; 3 & gt;
6.3V
1
MF 5% 1/20W
82 75
OUT
1
201
AK12
PEX_CLKREQ_L_R
NC
1
PEX_REFCLK
PEX_REFCLK*
8 93
PEG_D2R_N & lt; 4 & gt;
X5R
2
20%
C8063
PEG_D2R_P & lt; 3 & gt;
6.3V
AK13
2
1%
1/20W
MF
201
AJ26
R8000
GPU_RESET_L
93 75 6
AL13
PEG_CLK100M_N
IN
96 16
8 93
PEG_CLK100M_P
PEX_TSTCLK_O_P
0201
PEX_CLKREQ*
AJ11
PEX_WAKE*
GPU_PEX_TERMP
PEX_SVDD_3V3
AG12
2
1%
1/20W
MF
201
PP3V3_GPU_PEX_PLL_HVDD
C8064
0.22UF
1
2
20%
A
93 75 6
PEG_D2R_C_P & lt; 5 & gt;
93 75 6
PEG_D2R_C_N & lt; 5 & gt;
C8065
0.22UF
C8066
0.22UF
1
2
20%
SYNC_MASTER=J31_SREE
1
2
20%
93 75 6
PEG_D2R_C_P & lt; 6 & gt;
C8067
0.22UF
C8068
0.22UF
1
PEG_D2R_C_N & lt; 6 & gt;
1
PEG_D2R_C_P & lt; 7 & gt;
C8069
0.22UF
PEG_D2R_C_N & lt; 7 & gt;
C8070
0.22UF
6.3V
X5R
0201
PEG_D2R_P & lt; 6 & gt;
DRAWING NUMBER
Apple Inc.
X5R
0201
8 93
OUT
8 93
0201
6.3V
OUT
PEG_D2R_N & lt; 7 & gt;
X5R
8 93
0201
6.3V
OUT
PEG_D2R_P & lt; 7 & gt;
X5R
SYNC_DATE=10/25/2011
PAGE TITLE
KEPLER PCI-E
PEG_D2R_N & lt; 6 & gt;
6.3V
2
1
2
20%
8
0201
7
051-9585
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
6
5
4
3
2
SIZE
D
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
1
20%
93 75 6
X5R
2
20%
93 75 6
6.3V
2
20%
93 75 6
83
3.0.0
BRANCH
PAGE
80 OF 132
SHEET
75 OF 105
1
A
8
7
6
5
4
3
2
1
Page Notes
OMIT_TABLE
Power aliases required by this page:
- =PPVCORE_GPU
U8000
=PPVCORE_GPU
- =PP1V35_GPU_FBVDDQ
=PPVCORE_GPU
NV-GK107
83 76 7
7 76 83
BGA
(10 OF 10)
AA12
V17
AA14
V18
AA16
V20
AA19
V22
AA21
OMIT_TABLE
W12
Signal aliases required by this page:
U8000
=PP1V35_GPU_FBVDDQ
(NONE)
=PP1V35_GPU_FBVDDQ
NV-GK107
80 79 76 7
7 76 79 80
BGA
W14
H18
AA27
AB13
D
BOM options provided by this page:
W16
AA23
(7 OF 10)
D
(NONE)
VDD
AA30
H19
AB15
W19
AB27
H20
AB17
W21
AB33
H21
AB18
W23
AC27
H22
AB20
Y13
AD27
H23
AB22
Y15
AE27
H24
AC12
Y17
AF27
H8
AC14
Y18
AG27
H9
AC16
Y20
L27
AC19
B13
M27
N27
AC23
E13
P27
Y22
AC21
B19
=PPVCORE_GPU
83 76 7
M12
B16
FBVDDQ
FBVDDQ
U1
U2
U3
E16
R27
M14
E19
T27
M16
U4
U5
H10
T30
M19
H11
T33
M21
U6
U7
H12
V27
M23
U8
H13
W27
N13
V1
H14
W30
N15
H15
W33
N17
H16
Y27
N18
V2
VDD
V3
V4
N20
V5
N22
V6
P12
V7
P14
V8
C
P16
W2
P19
W3
P21
W4
P23
W5
R13
XVDD
R15
W7
W8
R17
Y1
R18
Y2
R20
Y3
R22
Y4
T12
Y5
T14
Y6
T16
Y7
T19
Y8
T21
AA1
T23
AA2
U13
AA3
U15
AA4
U17
AA5
U18
AA6
U20
AA7
U22
AA8
V13
EDP = 30 A
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
GPUDEC:NORMAL
GPUDEC:NORMAL
1
C8161
CRITICAL
1
47UF
2
20%
6.3V
X5R-CERM
0805
GPUDEC:EXP
C8198
CRITICAL
1
22UF
2
20%
6.3V
X5R
0603
GPUDEC:EXP
CRITICAL
GPUDEC:EXP
GPUDEC:NORMAL
C8199
CRITICAL
1
22UF
2
20%
6.3V
X5R
0603
C8162
C8163
2
20%
4V
X5R
402
C8164
20%
4V
X5R
402
NOSTUFF
CRITICAL
CRITICAL
1
22UF
2
NOSTUFF
CRITICAL
CRITICAL
GPUDEC:EXP
CRITICAL
1
22UF
20%
4V
X5R
402
GPUDEC:EXP
CRITICAL
GPUDEC:EXP
CRITICAL
1
22UF
2
GPUDEC:EXP
CRITICAL
GPUDEC:EXP
C8165
1
22UF
2
NOSTUFF
CRITICAL
20%
4V
X5R
402
NOSTUFF
CRITICAL
C8182
1
C8183
22UF
2
C8145
1
C8146
1
C8147
1
C8148
1
C8149
1
C8150
NOSTUFF
CRITICAL
1
2
1
22UF
22UF
22UF
22UF
22UF
20%
4V
X5R
402
20%
4V
X5R
402
20%
4V
X5R
402
20%
4V
X5R
402
20%
4V
X5R
402
20%
4V
X5R
402
1
22UF
20%
4V
X5R
402
C8168
2
1
C8169
2
1
C8170
2
1
2
1
C8171
C8172
2
1
C8173
2
1
C8174
C8130
1
C8175
GPUDEC:NORMAL
2
10UF
10UF
10UF
10UF
10UF
10UF
10UF
20%
10V
20%
10V
20%
10V
20%
10V
20%
10V
20%
10V
20%
10V
X5R-CERM
2
0402-1
1
C8178
X5R-CERM
2
0402-1
1
C8179
X5R-CERM
2
0402-1
1
C8180
2
X5R-CERM
0402-1
1
X5R-CERM
2
0402-1
1
C8181
C8184
X5R-CERM
2
0402-1
1
C8185
X5R-CERM
2
0402-1
1
C8186
X5R-CERM
2
C8187
1
10UF
10UF
10UF
10UF
1UF
1UF
1
1UF
20%
10V
20%
10V
20%
10V
20%
10V
20%
10V
20%
6.3V
20%
6.3V
20%
6.3V
X5R-CERM
2
0402-1
X5R-CERM
2
0402-1
X5R-CERM
2
0402-1
2
X5R-CERM
0402-1
X5R-CERM
2
0402-1
X5R-CERM
2
X5R
2
0201
0402-1
2
X5R
0201
GPUDEC:NORMAL
CRITICAL
1
20%
6.3V
X5R
0603
C8133
22UF
2
C
20%
6.3V
X5R
0603
C8177
20%
10V
X5R-CERM
0402-1
C8188
10UF
20%
10V
C8132
10UF
2
0402-1
10UF
2
2
1
X5R-CERM
0402-1
1
GPUDEC:NORMAL
1
20%
6.3V
X5R
0603
20%
10V
X5R-CERM
22UF
10UF
20%
10V
20%
10V
CRITICAL
C8131
C8176
10UF
C8167
0402-1
CRITICAL
1
2
1
X5R-CERM
22UF
20%
6.3V
X5R
0603
2
0402-1
22UF
2
1
10UF
20%
10V
2
GPUDEC:NORMAL
C8151
22UF
C8166
10UF
20%
4V
X5R
402
2
CRITICAL
1
1
22UF
20%
4V
X5R
402
C8189
1UF
2
X5R
0201
20%
6.3V
X5R
0201
V15
B
B
1
C8190
1
1UF
2
=PP1V35_GPU_FBVDDQ
GPU FB DE-COUPLING
20%
6.3V
X5R
0201
C8191
1
0.1UF
2
10%
6.3V
X5R
201
C8192
1
0.1UF
2
10%
6.3V
X5R
201
1
C8193
0.1UF
2
C8194
1
0.1UF
10%
6.3V
2
X5R
201
10%
6.3V
X5R
201
C8195
1
0.1UF
2
10%
6.3V
X5R
201
C8196
1
1000PF
2
10%
16V
X7R-CERM
0201
C8197
1000PF
2
10%
16V
X7R-CERM
0201
80 79 76 7
EDP = 6500 MA
1
C8125
1
C8126
1
C8127
1
C8128
1
C8101
1
1
C8102
C8103
22UF
2
22UF
22UF
22UF
10UF
10UF
20%
4V
20%
4V
20%
4V
20%
4V
20%
4V
20%
4V
1
10UF
20%
4V
X5R
2
402
X5R
2
402
X5R
2
402
X5R
2
402
X5R
2
402
2
X5R
402
X5R
C8104
10UF
2
402
GPU VCORE DE-COUPLING
20%
4V
X5R
402
NOTE: ATLEAST 2 GND VIAS & 2 POWER VIAS PER CAP
1
C8105
1
4.7UF
2
20%
6.3V
X5R-CERM1
C8106
1
4.7UF
2
402
20%
6.3V
X5R-CERM1
C8107
1
4.7UF
2
402
20%
6.3V
X5R-CERM1
C8108
1
4.7UF
2
402
20%
6.3V
X5R-CERM1
C8109
1
4.7UF
2
402
20%
6.3V
X5R-CERM1
C8110
1
4.7UF
2
402
20%
6.3V
X5R-CERM1
C8111
1
1UF
2
402
20%
6.3V
X5R
1
C8112
1UF
2
0201
C8113
1
1UF
20%
6.3V
2
X5R
0201
20%
6.3V
X5R
0201
C8114
1UF
2
20%
6.3V
X5R
0201
A
SYNC_MASTER=D2_MLB_2P
1
C8115
1
0.1UF
2
10%
6.3V
X5R
201
C8118
1
0.1UF
2
10%
6.3V
X5R
201
C8119
1
0.1UF
2
10%
6.3V
X5R
201
C8120
1
0.1UF
2
10%
6.3V
X5R
C8121
1
0.1UF
2
201
10%
6.3V
X5R
201
C8122
1
0.1UF
2
10%
6.3V
X5R
201
C8123
1
0.1UF
2
10%
6.3V
X5R
201
KEPLER CORE/FB POWER
0.1UF
2
SYNC_DATE=01/18/2012
PAGE TITLE
C8124
10%
6.3V
DRAWING NUMBER
X5R
201
Apple Inc.
051-9585
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
3.0.0
BRANCH
PAGE
81 OF 132
SHEET
76 OF 105
1
A
8
7
6
5
4
3
2
1
Page Notes
NOTE:GDDR5 MODE H MAPPING
FB_A0_RESET_L
100 79 77
1
U8000
BGA
BI
FB_A0_DQ & lt; 0 & gt;
L28
BI
FB_A0_DQ & lt; 1 & gt;
M29
100 79 6
L29
BI
FB_A0_DQ & lt; 2 & gt;
100 79 6
FB_A0_DQ & lt; 3 & gt;
M28
BI
100 79 6
FB_A0_DQ & lt; 4 & gt;
N31
BI
P29
BI
FB_A0_DQ & lt; 5 & gt;
100 79 6
FB_A0_DQ & lt; 6 & gt;
R29
BI
100 79 6
FB_A0_DQ & lt; 7 & gt;
P28
BI
100 79 6
D
100 79 6
100 79 6
BI
FB_A0_DQ & lt; 8 & gt;
J28
100 79 6
BI
FB_A0_DQ & lt; 9 & gt;
H29
100 79 6
FB_A0_DQ & lt; 10 & gt;
J29
BI
100 79 6
BI
FB_A0_DQ & lt; 11 & gt;
H28
100 79 6
FB_A0_DQ & lt; 12 & gt;
G29
BI
100 79 6
FB_A0_DQ & lt; 13 & gt;
E31
BI
100 79 6
FB_A0_DQ & lt; 14 & gt;
E32
BI
100 79 6
FB_A0_DQ & lt; 15 & gt;
F30
BI
100 79 6
FB_A0_DQ & lt; 16 & gt;
C34
BI
100 79 6
D32
BI
FB_A0_DQ & lt; 17 & gt;
100 79 6
FB_A0_DQ & lt; 18 & gt;
B33
BI
100 79 6
BI
FB_A0_DQ & lt; 19 & gt;
C33
100 79 6
BI
FB_A0_DQ & lt; 20 & gt;
F33
100 79 6
FB_A0_DQ & lt; 21 & gt;
F32
BI
100 79 6
FB_A0_DQ & lt; 22 & gt;
H33
BI
100 79 6
FB_A0_DQ & lt; 23 & gt;
H32
BI
P34
BI
FB_A0_DQ & lt; 24 & gt;
100 79 6
FB_A0_DQ & lt; 25 & gt;
P32
FB_A0_DQ & lt; 26 & gt;
P31
BI
100 79 6
P33
BI
FB_A0_DQ & lt; 27 & gt;
100 79 6
FB_A0_DQ & lt; 28 & gt;
L31
BI
BI
FB_A0_DQ & lt; 29 & gt;
L34
L32
L33
100 79 6
C
BI
100 79 6
100 79 6
BI
FB_A0_DQ & lt; 30 & gt;
100 79 6
BI
FB_A0_DQ & lt; 31 & gt;
100 79 6
FB_A1_DQ & lt; 0 & gt;
AG28
BI
100 79 6
FB_A1_DQ & lt; 1 & gt;
AF29
BI
100 79 6
FB_A1_DQ & lt; 2 & gt;
AG29
BI
100 79 6
100 79 6
BI
FB_A1_DQ & lt; 3 & gt;
AF28
100 79 6
BI
FB_A1_DQ & lt; 4 & gt;
AD30
100 79 6
FB_A1_DQ & lt; 5 & gt;
AD29
BI
AC29
BI
FB_A1_DQ & lt; 6 & gt;
100 79 6
100 79 6
BI
FB_A1_DQ & lt; 7 & gt;
AD28
100 79 6
BI
FB_A1_DQ & lt; 8 & gt;
AJ29
100 79 6
FB_A1_DQ & lt; 9 & gt;
AK29
BI
100 79 6
BI
FB_A1_DQ & lt; 10 & gt;
AJ30
100 79 6
BI
FB_A1_DQ & lt; 11 & gt;
AK28
100 79 6
FB_A1_DQ & lt; 12 & gt;
AM29
BI
BI
FB_A1_DQ & lt; 13 & gt;
100 79 6
100 79 6
BI
AM31
FB_A1_DQ & lt; 14 & gt;
AN29
100 79 6
BI
FB_A1_DQ & lt; 15 & gt;
AM30
100 79 6
FB_A1_DQ & lt; 16 & gt;
AN31
BI
100 79 6
FB_A1_DQ & lt; 17 & gt;
AN32
BI
BI
FB_A1_DQ & lt; 18 & gt;
AP30
100 79 6
AP32
BI
FB_A1_DQ & lt; 19 & gt;
100 79 6
FB_A1_DQ & lt; 20 & gt;
AM33
BI
100 79 6
BI
FB_A1_DQ & lt; 21 & gt;
AL31
100 79 6
FB_A1_DQ & lt; 22 & gt;
AK33
BI
100 79 6
FB_A1_DQ & lt; 23 & gt;
AK32
BI
100 79 6
FB_A1_DQ & lt; 24 & gt;
AD34
BI
100 79 6
FB_A1_DQ & lt; 25 & gt;
AD32
BI
100 79 6
FB_A1_DQ & lt; 26 & gt;
AC30
BI
100 79 6
FB_A1_DQ & lt; 27 & gt;
AD33
BI
100 79 6
FB_A1_DQ & lt; 28 & gt;
AF31
BI
BI
FB_A1_DQ & lt; 29 & gt;
AG34
100 79 6
AG32
BI
FB_A1_DQ & lt; 30 & gt;
100 79 6
FB_A1_DQ & lt; 31 & gt;
AG33
BI
100 79 6
B
100 79 6
100 79 6
OUT
FB_A0_WCLK_P & lt; 0 & gt;
K31
100 79 6
OUT
FB_A0_WCLK_N & lt; 0 & gt;
L30
100 79 6
OUT
FB_A0_WCLK_P & lt; 1 & gt;
H34
100 79 6
OUT
FB_A0_WCLK_N & lt; 1 & gt;
J34
100 79 6
FB_A1_WCLK_P & lt; 0 & gt;
AG30
OUT
100 79 6
FB_A1_WCLK_N & lt; 0 & gt;
AG31
OUT
100 79 6
FB_A1_WCLK_P & lt; 1 & gt;
AJ34
OUT
AK34
OUT
FB_A1_WCLK_N & lt; 1 & gt;
100 79 6
(3 OF 10)
MEM INTERFACE A
FBA_D0
FBA_CMD0
FBA_D1
FBA_CMD1
FBA_D2
FBA_CMD2
FBA_D3
FBA_CMD3
FBA_D4
FBA_CMD4
FBA_D5
FBA_CMD5
FBA_D6
FBA_CMD6
FBA_D7
FBA_CMD7
FBA_D8
FBA_CMD8
FBA_D9
FBA_CMD9
FBA_D10
FBA_CMD10
FBA_D11
FBA_CMD11
FBA_D12
FBA_CMD12
FBA_D13
FBA_CMD13
FBA_D14
FBA_CMD14
FBA_D15
FBA_CMD15
FBA_D16
FBA_CMD16
FBA_D17
FBA_CMD17
FBA_CMD18
FBA_D18
FBA_D19
FBA_CMD19
FBA_D20
FBA_CMD20
FBA_CMD21
FBA_D21
FBA_D22
FBA_CMD22
FBA_D23
FBA_CMD23
FBA_D24
FBA_CMD24
FBA_D25
FBA_CMD25
FBA_D26
FBA_CMD26
FBA_D27
FBA_CMD27
FBA_D28
FBA_CMD28
FBA_D29
FBA_CMD29
FBA_CMD30
FBA_D30
FBA_D31
FBA_CMD31
FBA_D32
FBA_CLK0
FBA_D33
FBA_CLK0*
FBA_D34
FBA_CLK1
FBA_D35
FBA_CLK1*
FBA_D36
FBA_D37
FBA_DQM0
FBA_D38
FBA_DQM1
FBA_D39
FBA_DQM2
FBA_D40
FBA_DQM3
FBA_D41
FBA_DQM4
FBA_D42
FBA_DQM5
FBA_D43
FBA_DQM6
FBA_D44
FBA_DQM7
FBA_D45
FBA_D46
FBA_DQS_RN0
FBA_D47
FBA_DQS_RN1
FBA_D48
FBA_DQS_RN2
FBA_D49
FBA_DQS_RN3
FBA_D50
FBA_DQS_RN4
FBA_D51
FBA_DQS_RN5
FBA_D52
FBA_DQS_RN6
FBA_D53
FBA_DQS_RN7
FBA_D54
FBA_D55
FBA_DQS_WP0
FBA_D56
FBA_DQS_WP1
FBA_D57
FBA_DQS_WP2
FBA_D58
FBA_DQS_WP3
FBA_D59
FBA_DQS_WP4
FBA_D60
FBA_DQS_WP5
FBA_D61
FBA_DQS_WP6
FBA_D62
FBA_DQS_WP7
FBA_D63
FB_DLL_AVDD
FBA_WCK01
FBA_PLL_AVDD
FBA_WCK01*
FBA_DEBUG
FBA_WCK23
FBA_DEBUG
FBA_WCK23*
FB_CAL_PD_VDDQ
FBA_WCK45
FB_CAL_PU_GND
FBA_WCK45*
FB_CAL_TERM_GND
FBA_WCK67
FB_CLAMP
FBA_WCK67*
J30
NC
NC
NC
NC
NC
NC
J31
J32
J33
AH31
AJ31
FBA_WCKB01
FBA_WCKB01*
FBA_WCKB23
FBA_WCKB23*
Power aliases required by this page:
- =PP1V35_GPU_S0_REG
- =PP1V05_GPU_PEX_IOVDD
1
R8250
FBA_CMD_RFU
FBA_CMD_RFU
2
10K
1%
1/20W
MF
201
1%
1/20W
MF
201
2
NC
NC
AJ32
AJ33
Signal aliases required by this page:
OMIT_TABLE
(NONE)
U8000
FB_A0_CS_L
79 100
OUT
T31
FB_A0_A & lt; 3 & gt;
OUT
6 79 100
U29
FB_A0_A & lt; 2 & gt;
OUT
6 79 100
R34
FB_A0_A & lt; 4 & gt;
OUT
6 79 100
R33
FB_A0_A & lt; 5 & gt;
OUT
6 79 100
U32
FB_A0_WE_L
OUT
FB_A0_A & lt; 7 & gt;
OUT
6 79 100
U28
FB_A0_A & lt; 6 & gt;
OUT
FB_A0_ABI_L
U34
OUT
6 79 100
1
1
R8252
F9
BI
FB_B0_DQ & lt; 3 & gt;
FB_B0_DQ & lt; 4 & gt;
F11
BI
100 80 6
77 79
100
R8253
10K
6 79 100
FB_A0_A & lt; 0 & gt;
V30
OUT
FB_B0_DQ & lt; 2 & gt;
G8
BI
100 80 6
FB_A1_CKE_L
77 79
100
FB_B0_DQ & lt; 5 & gt;
G11
BI
100 80 6
100 80 6
6 79 100
FB_A0_A & lt; 8 & gt;
V29
OUT
FB_B0_DQ & lt; 1 & gt;
E9
BI
100 80 6
FB_A0_CKE_L
6 79 100
V28
G9
BI
FB_B0_DQ & lt; 0 & gt;
100 80 6
79 100
U33
2
10K
1%
1/20W
MF
201
1%
1/20W
MF
201
2
100 80 6
BI
FB_B0_DQ & lt; 6 & gt;
F12
100 80 6
BI
FB_B0_DQ & lt; 7 & gt;
G12
100 80 6
FB_B0_DQ & lt; 8 & gt;
G6
BI
FB_A0_A & lt; 1 & gt;
OUT
6 79 100
100 80 6
BI
FB_B0_DQ & lt; 9 & gt;
F5
U31
FB_A0_RAS_L
79 100
100 80 6
BI
FB_B0_DQ & lt; 10 & gt;
E6
OUT
V34
FB_A0_RESET_L
77 79 100
100 80 6
BI
FB_B0_DQ & lt; 11 & gt;
F6
OUT
FB_A0_CKE_L
77 79 100
100 80 6
BI
FB_B0_DQ & lt; 12 & gt;
F4
OUT
Y32
FB_A0_CAS_L
79 100
100 80 6
BI
FB_B0_DQ & lt; 13 & gt;
G4
OUT
AA31
FB_A1_CS_L
79 100
100 80 6
BI
FB_B0_DQ & lt; 14 & gt;
E2
OUT
100 80 6
F3
BI
FB_B0_DQ & lt; 15 & gt;
100 80 6
FB_B0_DQ & lt; 16 & gt;
C2
BI
V33
AA29
FB_A1_A & lt; 3 & gt;
OUT
6 79 100
AA28
FB_A1_A & lt; 2 & gt;
OUT
6 79 100
AC34
FB_A1_A & lt; 4 & gt;
OUT
AC33
FB_A1_A & lt; 5 & gt;
OUT
FB_A1_WE_L
OUT
AA33
FB_A1_A & lt; 7 & gt;
OUT
6 79 100
FB_A1_A & lt; 6 & gt;
OUT
6 79 100
OUT
6 79 100
Y29
FB_A1_ABI_L
1
NOSTUFF
R8258
PLACE_NEAR=U8000.H26:8.4MM
1.33K
1%
1/20W
MF
201
BI
FB_B0_DQ & lt; 18 & gt;
D3
FB_B0_DQ & lt; 19 & gt;
C1
BI
FB_B0_DQ & lt; 20 & gt;
B3
BI
100 80 6
7 77
FB_B0_DQ & lt; 17 & gt;
100 80 6
=PP1V35_GPU_S0_FB
BI
100 80 6
6 79 100
D4
100 80 6
79 100
Y28
100 80 6
6 79 100
AA32
FB_B0_DQ & lt; 21 & gt;
C4
BI
B5
BI
FB_B0_DQ & lt; 22 & gt;
100 80 6
W31
FB_A1_A & lt; 8 & gt;
OUT
6 79 100
Y30
FB_A1_A & lt; 0 & gt;
OUT
6 79 100
AA34
FB_A1_A & lt; 1 & gt;
OUT
6 79 100
100 80 6
Y31
FB_A1_RAS_L
OUT
79 100
100 80 6
Y34
FB_A1_RESET_L
Y33
FB_A1_CKE_L
V31
FB_A1_CAS_L
R30
2
100 80 6
1NOSTUFF
BI
FB_B0_DQ & lt; 23 & gt;
C5
100 80 6
PLACE_NEAR=U8000.H26:8.4MM
FB_VREF
77 79 100
OUT
FB_B0_DQ & lt; 24 & gt;
A11
BI
C11
BI
FB_B0_DQ & lt; 25 & gt;
FB_B0_DQ & lt; 26 & gt;
D11
BI
BI
FB_B0_DQ & lt; 27 & gt;
B11
D8
77
NOSTUFF
R8259
1
1.33K
100 80 6
C8260
FB_A0_CLK_P
OUT
79 100
R31
FB_A0_CLK_N
OUT
FB_A1_CLK_P
OUT
79 100
BI
A8
100 80 6
10%
6.3V
X5R
201
FB_B0_DQ & lt; 30 & gt;
C8
BI
BI
FB_B0_DQ & lt; 31 & gt;
FB_B1_DQ & lt; 0 & gt;
F24
BI
FB_B1_DQ & lt; 1 & gt;
G23
BI
79 100
AB31
2
FB_B0_DQ & lt; 29 & gt;
100 80 6
0.1UF
1%
1/20W
MF
2 201
BI
100 80 6
OUT
79 100
100 80 6
100 80 6
77 79 100
FB_B0_DQ & lt; 28 & gt;
100 80 6
OUT
AC31
FB_A1_CLK_N
P30
F34
FB_B1_DQ & lt; 2 & gt;
FB_B1_DQ & lt; 3 & gt;
G24
BI
100 80 6
D21
BI
FB_B1_DQ & lt; 4 & gt;
100 80 6
FB_B1_DQ & lt; 5 & gt;
E21
BI
100 80 6
BI
6 79 100
BI
FB_A0_DBI_L & lt; 1 & gt;
BI
6 79 100
FB_A0_DBI_L & lt; 2 & gt;
BI
M32
FB_A0_DBI_L & lt; 3 & gt;
BI
6 79 100
AD31
FB_A1_DBI_L & lt; 0 & gt;
BI
FB VREF GEN (TEST ONLY)
6 79 100
6 79 100
AL29
FB_A1_DBI_L & lt; 1 & gt;
AM32
100 80 6
FB_A1_DBI_L & lt; 3 & gt;
BI
FB_B1_DQ & lt; 6 & gt;
G21
100 80 6
FB_B1_DQ & lt; 7 & gt;
F21
BI
100 80 6
BI
FB_B1_DQ & lt; 8 & gt;
G27
6 79 100
BI
FB_A1_DBI_L & lt; 2 & gt;
AF34
100 80 6
100 80 6
BI
FB_B1_DQ & lt; 10 & gt;
G26
BI
BI
FB_B1_DQ & lt; 11 & gt;
6 79 100
BI
BI
FB_B1_DQ & lt; 9 & gt;
D27
6 79 100
100 80 6
100 80 6
M30
B8
E24
100 80 6
FB_A0_DBI_L & lt; 0 & gt;
F31
PLACE_NEAR=U8000.H26:8.4MM
79 100
OUT
NC
NC
NC
NC
NC
NC
NC
NC
BI
E27
FB_B1_DQ & lt; 12 & gt;
E29
E34
M34
AF30
AK31
AM34
AF32
M31
100 80 6
100 80 6
FB_B1_DQ & lt; 14 & gt;
E30
BI
100 80 6
FB_B1_DQ & lt; 15 & gt;
D30
BI
BI
FB_B1_DQ & lt; 16 & gt;
A32
100 80 6
C31
BI
FB_B1_DQ & lt; 17 & gt;
100 80 6
FB_B1_DQ & lt; 18 & gt;
C32
BI
100 80 6
BI
FB_B1_DQ & lt; 19 & gt;
B32
100 80 6
FB_B1_DQ & lt; 20 & gt;
D29
BI
FB_B1_DQ & lt; 21 & gt;
A29
BI
100 80 6
FB_B1_DQ & lt; 22 & gt;
C29
BI
100 80 6
FB_B1_DQ & lt; 23 & gt;
B29
BI
100 80 6
FB_B1_DQ & lt; 24 & gt;
B21
BI
100 80 6
FB_B1_DQ & lt; 25 & gt;
C23
BI
100 80 6
FB_B1_DQ & lt; 26 & gt;
A21
BI
BI
FB_B1_DQ & lt; 27 & gt;
C21
B24
100 80 6
FB_A0_EDC & lt; 0 & gt;
G31
BI
FB_B1_DQ & lt; 13 & gt;
F29
100 80 6
H30
IN
FB_A0_EDC & lt; 1 & gt;
IN
6 79 100
=PP1V35_GPU_S0_FB
6 79 100
E33
FB_A0_EDC & lt; 2 & gt;
M33
FB_A0_EDC & lt; 3 & gt;
IN
FB_A1_EDC & lt; 0 & gt;
IN
6 79 100
AK30
FB_A1_EDC & lt; 1 & gt;
IN
6 79 100
7 77
6 79 100
AE31
AN33
IN
FB_A1_EDC & lt; 2 & gt;
6 79 100
IN
R8203
1
60.4
6 79 100
IN
1
FB_A1_EDC & lt; 3 & gt;
6 79 100
PP1V05_GPU_FB_PLL_AVDD
2
77
201
100 80 6
100 80 6
BI
FB_B1_DQ & lt; 28 & gt;
R8270
100 80 6
FB_B1_DQ & lt; 29 & gt;
C24
BI
100
100 80 6
BI
FB_B1_DQ & lt; 30 & gt;
B26
100 80 6
FB_B1_DQ & lt; 31 & gt;
C26
BI
1%
1/20W
1/20W
MF
PP1V05_GPU_FB_DLL_AVDD
R8202
60.4
1%
AF33
K27
1
MF
2
201
77
5%
U27
(NONE)
BGA
1/20W
(4 OF 10)
MEM INTRERFACE B
FBB_D0
FBB_CMD0
FBB_D1
FBB_CMD1
FBB_D2
FBB_CMD2
FBB_D3
FBB_CMD3
FBB_D4
FBB_CMD4
FBB_D5
FBB_CMD5
FBB_D6
FBB_CMD6
FBB_D7
FBB_CMD7
FBB_D8
FBB_CMD8
FBB_D9
FBB_CMD9
FBB_CMD10
FBB_D10
FBB_D11
FBB_CMD11
FBB_D12
FBB_CMD12
FBB_D13
FBB_CMD13
FBB_D14
FBB_CMD14
FBB_D15
FBB_CMD15
FBB_CMD16
FBB_D16
FBB_D17
FBB_CMD17
FBB_D18
FBB_CMD18
FBB_D19
FBB_CMD19
FBB_D20
FBB_CMD20
FBB_D21
FBB_CMD21
FBB_D22
FBB_CMD22
FBB_D23
FBB_CMD23
FBB_D24
FBB_CMD24
FBB_D25
FBB_CMD25
FBB_D26
FBB_CMD26
FBB_D27
FBB_CMD27
FBB_CMD28
FBB_D28
FBB_D29
FBB_CMD29
FBB_D30
FBB_CMD30
FBB_D31
FBB_CMD31
FBB_D32
FBB_CLK0
FBB_D33
FBB_CLK0*
FBB_D34
FBB_CLK1
FBB_D35
FBB_CLK1*
FBB_D36
FBB_D37
FBB_DQM0
FBB_D38
FBB_DQM1
FBB_D39
FBB_DQM2
FBB_D40
FBB_DQM3
FBB_D41
FBB_DQM4
FBB_D42
FBB_DQM5
FBB_D43
FBB_DQM6
FBB_D44
FBB_DQM7
FBB_D45
FBB_D46
FBB_DQS_RN0
FBB_D47
FBB_DQS_RN1
FBB_D48
FBB_DQS_RN2
FBB_D49
FBB_DQS_RN3
FBB_D50
FBB_DQS_RN4
FBB_D51
FBB_DQS_RN5
FBB_D52
FBB_DQS_RN6
FBB_D53
FBB_DQS_RN7
FBB_D54
FBB_D55
FBB_DQS_WP0
FBB_D56
FBB_DQS_WP1
FBB_D57
FBB_DQS_WP2
FBB_D58
FBB_DQS_WP3
FBB_D59
FBB_DQS_WP4
FBB_D60
FBB_DQS_WP5
FBB_D61
FBB_DQS_WP6
FBB_D62
FBB_DQS_WP7
FBB_D63
D13
FB_B0_CS_L
OUT
80 100
E14
FB_B0_A & lt; 3 & gt;
OUT
6 80 100
F14
FB_B0_A & lt; 2 & gt;
OUT
6 80 100
A12
FB_B0_A & lt; 4 & gt;
OUT
6 80 100
6 80 100
B12
FB_B0_A & lt; 5 & gt;
OUT
C14
FB_B0_WE_L
OUT
OUT
6 80 100
FB_B0_A & lt; 6 & gt;
OUT
6 80 100
FB_B0_ABI_L
OUT
6 80 100
FB_B0_A & lt; 8 & gt;
OUT
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
6 80 100
B14
G15
F15
E15
D15
1
2
0603
CRITICAL
ESR = 0.05OHM
FB_B0_A & lt; 0 & gt;
OUT
FB_B0_A & lt; 1 & gt;
OUT
FB_B0_RAS_L
OUT
FB_B0_RESET_L
OUT
FB_B0_CKE_L
OUT
FB_B0_CAS_L
OUT
FB_B1_CS_L
OUT
GPU_FBA_DEBUG0
AC28
GPU_FBA_DEBUG1
2
100 80 6
100 80 6
J27
FB_CAL_PD_VDDQ
77
100 80 6
H27
FB_CAL_PU_GND
77
100 80 6
H25
FB_CAL_TERM_GND
E1
R8201
FB_CLAMP
1
F8
OUT
FB_B0_WCLK_P & lt; 0 & gt;
FB_B0_WCLK_N & lt; 0 & gt;
E8
OUT
80 100
E18
L8202
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
FERR-220-OHM-2A
=PP1V05_GPU_PEX_IOVDD
FB_B1_A & lt; 3 & gt;
OUT
F18
6 83 77 7
80 100
FB_B1_A & lt; 2 & gt;
OUT
6 80 100
A20
FB_B1_A & lt; 4 & gt;
OUT
6 80 100
B20
FB_B1_A & lt; 5 & gt;
OUT
6 80 100
C18
FB_B1_WE_L
OUT
80 100
FB_B1_A & lt; 7 & gt;
OUT
6 80 100
G18
FB_B1_A & lt; 6 & gt;
OUT
6 80 100
G17
FB_B1_ABI_L
OUT
6 80 100
F17
FB_B1_A & lt; 8 & gt;
OUT
6 80 100
D16
FB_B1_A & lt; 0 & gt;
OUT
6 80 100
A18
FB_B1_A & lt; 1 & gt;
OUT
6 80 100
D17
FB_B1_RAS_L
OUT
80 100
A17
FB_B1_RESET_L
OUT
77 80 100
B17
FB_B1_CKE_L
OUT
77 80 100
E17
FB_B1_CAS_L
OUT
80 100
D12
FB_B0_CLK_P
OUT
80 100
FB_B0_CLK_N
OUT
80 100
E20
FB_B1_CLK_P
OUT
80 100
F20
FB_B1_CLK_N
OUT
80 100
B18
1
E11
C8208
1
FB_B0_DBI_L & lt; 0 & gt;
BI
FB_B0_DBI_L & lt; 1 & gt;
BI
FB_B0_DBI_L & lt; 2 & gt;
BI
FB_B0_DBI_L & lt; 3 & gt;
BI
FB_B1_DBI_L & lt; 0 & gt;
BI
FB_B1_DBI_L & lt; 1 & gt;
BI
FB_B1_DBI_L & lt; 2 & gt;
BI
BI
FB_B1_RESET_L
100 80 77
1
1
R8254
10K
FB_B0_WCLK_P & lt; 1 & gt;
A5
OUT
A6
OUT
FB_B0_WCLK_N & lt; 1 & gt;
2
100 80 6
1%
NC
NC
AC32
1
1%
1/20W
201
GPU_FBVDDQ_SENSE_P
OUT
78 101
F2
GPU_FBVDDQ_SENSE_N
OUT
78 101
FB_B1_WCLK_P & lt; 1 & gt;
B27
OUT
FB_B1_WCLK_N & lt; 1 & gt;
C27
FB_CAL_PU_GND
OUT
NC
NC
NC
NC
PLACE CLOSE TO BGA
77
D25
100 80 6
F1
FBA_WCKB45
FBA_WCKB45*
D24
FB_B1_WCLK_N & lt; 0 & gt;
201
2
MF
FB_B1_WCLK_P & lt; 0 & gt;
OUT
100 80 6
MF
FBB_WCK23
FBB_WCK23*
FBB_WCK45
FBB_WCK45*
R8261
10K
R32
1/20W
OUT
100 80 6
60.4
FB_GND_SENSE
=PP1V35_GPU_S0_FB
NC
NC
R8271
100
7 77
5%
1/20W
1
R8204
1
40.2
1%
1/20W
MF
2 201
6 80 100
A24
77 80
100
B2
A9
D22
D28
A30
B23
FB_B1_CKE_L
1
R8256
10K
NC
NC
NC
NC
NC
NC
NC
NC
E4
77 80 100
FB_B0_CKE_L
1
D9
R8257
10K
1%
1/20W
MF
2 201
1%
1/20W
MF
2 201
B
D10
FB_B0_EDC & lt; 0 & gt;
IN
6 80 100
D5
FB_B0_EDC & lt; 1 & gt;
IN
6 80 100
C3
FB_B0_EDC & lt; 2 & gt;
IN
6 80 100
B9
FB_B0_EDC & lt; 3 & gt;
IN
6 80 100
FB_B1_EDC & lt; 0 & gt;
IN
6 80 100
E28
FB_B1_EDC & lt; 1 & gt;
IN
6 80 100
B30
FB_B1_EDC & lt; 2 & gt;
IN
6 80 100
FB_B1_EDC & lt; 3 & gt;
IN
6 80 100
E23
A23
2
R8205
1%
H17
FBB_DEBUG0
FBB_DEBUG1
G14
GPU_FBB_DEBUG0
MEM VREFC & VREFD SWITCH
FB_SW_LEG
80 79
OUT
77
G20
GPU_FBB_DEBUG1
77
FB_VREF
H26
FBB_CMD_RFU0
FBB_CMD_RFU1
C12
NC
NC
201
D6
D7
C6
B6
F26
E26
FBB_WCK67
FBB_WCK67*
C20
77
PP1V05_GPU_FB_PLL_AVDD
FB_VREF
1/20W
D
SSM3K15FV
SOD-VESM-HF
C8206
1
1UF
77
C8207
0.1UF
20%
6.3V
X5R
0201
2
10%
6.3V
X5R
201
2
S
G
1
GPU_ALT_VREF
IN
FBB_WCKB23
FBB_WCKB23*
=PP1V35_GPU_S0_FB
FBB_WCKB45
FBB_WCKB45*
7 77
SYNC_MASTER=J31_SREE
A27
FBB_WCKB67
FBB_WCKB67*
KEPLER FRAME BUFFER I/F
1
R8206
1
DRAWING NUMBER
R8207
60.4
60.4
1%
1/20W
MF
2 201
1%
1/20W
MF
2 201
Apple Inc.
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
GPU_FBB_DEBUG0
77
GPU_FBB_DEBUG1
5
4
3
051-9585
2
SIZE
D
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
77
77
6
SYNC_DATE=10/25/2011
PAGE TITLE
A26
201
FB_CAL_PD_VDDQ
82
FBB_WCKB01
FBB_WCKB01*
1/20W
2
3
1
2
MF
201
Q8265
NC
NC
PLACE_NEAR=U8000.J27:8.4MM
MF
2
FBB_PLL_AVDD
40.2
1%
PLACE_NEAR=U8000.H27:8.4MM
7
R8255
10K
1%
1/20W
MF
2 201
6 80 100
FB_B1_DBI_L & lt; 3 & gt;
FB_B0_RESET_L
6 80 100
C30
10%
6.3V
X5R
201
6 80 100
F27
C8205
2
6 80 100
F23
1
0.1UF
20%
6.3V
X5R
0201
2
6 80 100
C9
C8204
1UF
20%
6.3V
X5R-CERM2
0603
6 80 100
A3
77
C
6 80 100
E3
1
22UF
2
100 80 77
E12
PP1V05_GPU_FB_DLL_AVDD
2
0603
CRITICAL
ESR = 0.05OHM
CRITICAL
FBB_WCK01
FBB_WCK01*
PLACE_NEAR=U8000.H25:8.4MM
MF
8
10%
6.3V
X5R
201
FB PLL & DLL VDD
80 100
D18
0.1UF
2
77 80 100
C17
2
77 80 100
B15
20%
6.3V
X5R
0201
C8203
1UF
80 100
A15
2
1
C8202
20%
6.3V
X5R-CERM2
0603
6 80 100
D14
1
C8201
1
22UF
6 80 100
A14
PP1V05_GPU_FB_PLL_AVDD
77
80 100
FB_B0_A & lt; 7 & gt;
D
L8201
FERR-220-OHM-2A
=PP1V05_GPU_PEX_IOVDD
7
77
83
MF
201
R28
FB_VDDQ_SENSE
FBA_WCKB67
FBA_WCKB67*
BOM options provided by this page:
NV-GK107
U30
1
A
R8251
10K
NV-GK107
100 79 6
FB_A1_RESET_L
100 79 77
OMIT_TABLE
3.0.0
BRANCH
PAGE
82 OF 132
SHEET
77 OF 105
1
A
8
7
6
5
4
7
7
6
1
5%
1/16W
MF-LF
402
DIDT=TRUE
1
2
R8359 1
2
PVCC
6
1.62K
1
17
7
SREF
PHASE
16
12
LGATE
1
11
GPUFB_OCSET
1%
1/20W
MF
2 201
R8353
VO
92
14
GPUFB_PGOOD
OUT
4
GPU_FBGND_SENSE
2
1%
1/20W
MF
201
13
GPUFB_FSEL
1
2
1
3
2
P1V5_GPU_S0_REG_R
1
3
4
CRITICAL
NO STUFF
1
OMIT_TABLE
CRITICAL
D
GPUFB_DRVL
4
G
1
R8361
103 101
2
XW8352
103 101
2
GATE_NODE=TRUE
DIDT=TRUE
GPUFB_SNBR
S
2
1%
1/20W
MF
201
1
R8363
0
C8372
5%
2.2UF
2
R8350
20%
10V
X5R-CERM
402
1
3
1
VID1
1/20W
MF
201 2
C8362
C
1
1
C8376
5%
50V
COG
0201
1
R8352
2
4.64K
1%
1/20W
MF
201
1
1%
1/20W
MF
201
2
NOSTUFF
C8352
1%
1/20W
MF
201
PGND
C8370
2
1000PF
2
1
1
10%
16V
X7R
201
1
C
R8372
1.69K
IN
GPUFB_SET_R
5%
50V
COG
0201
GPUFB_CS_N
GPUFB_GPU_VO_R
1.69K
2
82
10PF
2
FBVDD_ALTVO
2
1%
1/20W
MF
201
GPIO(16) VID1
VID0
FBVDD
R8349
27K
0
0
1.5V
1%
1/20W
MF
2 201
NOSTUFF
5%
25V
NP0-C0G
402
1
R8371 1
5%
1/20W
MF
201
4.64K
10PF
2
R8354
2
GPUFB_GPU_OCSET_R
10%
50V
CERM
402
0
1
2
20%
6.3V
X5R
603
SM
0.0033UF
2
GND
20%
2 2.5V
TANT
CASE-B2-SM1
C8366
1000PF
10UF
XW8351
2
NO STUFF
2
VID0
5
NOSTUFF
150K
1
C8365
SM
SET1
6
R8368
1
HVSON-333
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
3
1
CRITICAL
C8361
330UF
20%
2 2.5V
TANT
CASE-B2-SM1
5%
1/10W
MF-LF
603
CRITICAL
1
C8360
330UF
GPUFB_CS_P
1
RJK0226DNS
7
103
2
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.35V
PCMB065T-SM
1
2
=PP1V5R1V35_GPU_REG
1%
1W
MF-1
0612
1
0.01UF
10%
10V
X5R
201
0.001
L8360
1.0UH-13A-5.6MOHM
5
SET0
R8360
CRITICAL
GPUFB_LL
D
CRITICAL
HVSON-3333
Q8361
9
VOUT = 1.5V / 1.35V
F = 500 KHZ
S
RTN
8
PLACE_NEAR=C8395.1:3mm
RJK0225DNS
GPUFB_DRVH
PGOOD
GPUFB_SET0
1
G
4
SWITCH_NODE=TRUE
DIDT=TRUE
6
2
Q8360
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
FSEL
5%
25V
NP0-C0G
402
OMIT_TABLE
CRITICAL
D
OCSET
GPUFB_SET1
C8373
6
1000PF
5
GATE_NODE=TRUE
DIDT=TRUE
R8367
301K
1.62K
UGATE
GPUFB_VO
1%
1/20W
MF
201
1
FB
2
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
18
10
GPU_FBVDDQ_SENSE_DIV
2
2
GPU FB SUPPLY
C8396
10%
25V
X5R
402
11A MAX OUTPUT
2
GPUFB_VBST
6
BOOT
CRITICAL
GPUFB_SREF
1
IN GPU_FBVDDQ_SENSE_N
UTQFN
EN
1
1UF
2
GPU_FBVDDQ_SENSE_P
15
C8395
1
PLACE_NEAR=Q8360.5:1mm
DIDT=TRUE
ISL95870AH
=P1V35FB_EN
20%
16V
POLY-TANT
CASE-D2E-SM
10%
50V
X7R
603-1
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
U8350
1
68UF
20
19
VCC
IN
2
0
PP5V_S0GPU_P1V5_VCC
D
C8390
C8355
0.1UF
20%
10V
X5R-CERM
0402-1
5%
1/16W
MF-LF
402
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V
CRITICAL
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
C8371
10UF
2.2
IN
1
GPUFB_BOOT_RC
CRITICAL
92
2
=PP5V_S0GPU_P1V5
R8351 1
R8381
3
=PPVIN_S0GPU_P1V5
1
0
1.35V
XW8350
SM
GPUP1V5_AGND
1
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V
7
101 83
P1V05_GPU_PEX_IOVDD_SNS_P
7
2
PLACE_NEAR=U8350.3:1mm
=PPVIN_S0GPU_P1V05
=PP5V_S0GPU_P1V05
IN
CRITICAL
CRITICAL
1
R8301 1
101 83
P1V05_GPU_PEX_IOVDD_SNS_N
IN
6
2
20%
10V
X5R
603
2
R8325 1
SIGNAL_MODEL=EMPTY
1
R8304
1%
1/20W
MF
201
2
& lt; Ra & gt;
PVCC
ISL95870
92
=P1V05_GPU_EN
3
IN
& lt; Ra & gt;
6
P1V05_GPU_FB
BOOT
CRITICAL
FB
12
6
P1V05_GPU_VBST
UGATE
11
6
4
SREF
PHASE
10
8
VO
LGATE
7
OCSET
9
P1V05_S0GPU_PGOOD
OUT
2
C8304
1
C8302
10%
16V
X5R
603
C8305
10PF
2
1
GPU 1V05 SUPPLY
5%
25V
NP0-C0G
402
PLACE_NEAR=Q8310.2:1mm
10%
16V
X5R-CERM
0201
B
2
5%
25V
C0G-NPO
0201
1
2
DIDT=TRUE
3
7
5
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
CRITICAL
6
P1V05_GPU_LL
A
1%
1W
MF-1
0612
2.2UH-8.0A
8
1
2
P1V05_GPU_S0_REG_R
2
1
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
4
3
PCMB065T-SM
SWITCH_NODE=TRUE
DIDT=TRUE
=PP1V05_S0GPU_REG
6
CRITICAL
P1V05_GPU_DRVL
103 101
C8316
P1V05_GPU_CS_P
GND
1
4
GATE_NODE=TRUE
DIDT=TRUE
PGND
5
103 101
XW8302
1
1000PF
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
FSEL
2
2
5%
25V
NP0-C0G
402
P1V05_GPU_CS_N
2
2
330UF
20%
2.0V 2
POLY-TANT
CASE-B2-SM1
VOUT = 1.05V
5.3A MAX OUTPUT
F = 500 KHZ
SM
5%
1/20W
MF
201
XW8301
2
1
SM
P1V05_GPU_OCSET_R
1
C8303
R8321 1
10%
6.3V
X5R
201
1%
1/20W
MF
201
SM
GPUP1V05_AGND
1
P1V05_GPU_VO_R
845
XW8310
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V
2
C8320
2
SYNC_MASTER=J31_JACK
1000PF
2
PLACE_NEAR=U8310.1:1mm
SYNC_DATE=11/16/2011
PAGE TITLE
1
1V05 GPU / 1V35 FB POWER SUPPLY
10%
16V
X7R
201
Vout = 0.5V * (1 + Ra / Rb)
DRAWING NUMBER
1
R8322
Apple Inc.
845
2
1%
1/20W
MF
201
7
6
5
4
3
051-9585
NOTICE OF PROPRIETARY PROPERTY:
2
SIZE
D
REVISION
R
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
C8310 1
6
0.047UF
2
0.001
L8310
1
GATE_NODE=TRUE
DIDT=TRUE
R8310
CRITICAL
POWERPAIR-6X3.7
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
RTN
R8303
CRITICAL
SIZ700DT
0
2.2UF
1
10PF
5%
25V
C0G-NPO
0201
2
2
PGOOD
NOSTUFF
1
1%
1/20W
MF
201
& lt; Rb & gt;
2
P1V05_GPU_FSEL
R8307
2.74K
2
C8325
15
P1V05_GPU_RTN
& lt; Rb & gt;
C8346
1000PF
10%
25V
X5R
603-1
16
92
1
1
1UF
Q8310
P1V05_GPU_OCSET
1%
1/20W
MF
201
2
P1V05_GPU_DRVH
P1V05_GPU_VO
2.74K
C8345
PLACE_NEAR=C8345.1:3mm
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
UTQFN
EN
P1V05_GPU_SREF
R8306 1
2
U8310
3.01K
1%
1/20W
MF
201
14
13
R8305
3.01K
2
VCC
1
2
0.1UF
2.2
SIGNAL_MODEL=EMPTY
1
20%
16V
POLY-TANT
CASE-D2E-SM
1
5%
1/20W
MF
201
1
68UF
DIDT=TRUE
PP5V_S0GPU_P1V05_VCC
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V
B
C8340
P1V05_GPU_BOOT_RC
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
10UF
2.2
5%
1/20W
MF
201
C8301
3.0.0
BRANCH
PAGE
83 OF 132
SHEET
78 OF 105
1
A
8
7
6
5
4
3
2
1
Page Notes
U8450
U8400
Power aliases required by this page:
32MX32-1.25GHZ-MFL
32MX32-1.25GHZ-MFL
- =PP1V5R1V35_S0_FB_VDD
BGA
H5GQ1H24AFR-T2C
BGA
H5GQ1H24AFR-T2C
Signal aliases required by this page:
(NONE)
100 77 6
IN
FB_A0_A & lt; 2 & gt;
H11
100 77 6
BOM options provided by this page:
IN
FB_A0_A & lt; 5 & gt;
K10
IN
FB_A0_A & lt; 4 & gt;
100 77 6
100 77 6
IN
PLACE_NEAR=U8400.J11:8.4MM
R8401
FB_A0_CLK_P
1
79 77
100
40.2
FBA0_CK_MID
2
1
1%
1/20W
MF
201
FB_A0_CLK_N
2
IN
FB_A0_A & lt; 7 & gt;
K4
100 77 6
R8402
40.2
H10
FB_A0_A & lt; 3 & gt;
100 77 6
CK TERMINATION - A0
D
K11
IN
FB_A0_A & lt; 1 & gt;
H5
100 77 6
77 79 100
100 77 6
1%
1/20W
MF
201
100 77
FB_A0_A & lt; 0 & gt;
IN
FB_A0_A & lt; 6 & gt;
IN
FB_A0_CKE_L
J3
J12
100 79 77
10%
10V
X5R-CERM
0201 PLACE_NEAR=U8400.J11:8.4MM
IN
FB_A0_CLK_P
100 79 77
0.01UF
2
K5
IN
FB_A0_CLK_N
IN
FB_A0_CS_L
100 77
100 77
IN
IN
G12
L12
FB_A0_CAS_L
IN
J11
FB_A0_WE_L
100 77
FB_A0_RAS_L
100 77
L3
G3
FB_A0_ZQ
R8400
J13
FB_A0_MF
1
J1
J10
FB_A0_SEN
120
1%
1/20W
MF
201 2
R8404
1
R8403
120
100 77
1
IN
J2
FB_A0_RESET_L
120
1%
1/20W
MF
201 2
1%
1/20W
MF
201
100 77 6
2
100 77 6
IN
BI
J4
FB_A0_ABI_L
FB_A0_EDC & lt; 0 & gt;
C2
100 77 6
BI
FB_A0_EDC & lt; 1 & gt;
C13
100 77 6
BI
FB_A0_EDC & lt; 2 & gt;
R13
BI
FB_A0_EDC & lt; 3 & gt;
100 77 6
CK TERMINATION - A1
R8451
1
C
R8452
40.2
R2
PLACE_NEAR=U8450.J11:8.4MM
100 77 6
FB_A1_CLK_P
2
1%
1/20W
MF
201
1
1
PLACE_NEAR=U8450.J12:8.4MM
100 77 6
40.2
FBA1_CK_MID
DBI0*
DBI1*
DBI2*
DBI3*
(1 OF 2)
A8/A7
A9/A1
A10/A0
A11/A6
CKE*
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
OMIT_TABLE
C8490
1
PLACE_NEAR=U8400.J12:8.4MM
H4
IN
BA0/A2
BA1/A5
BA2/A4
BA3/A3
FB_A1_CLK_N
2
1%
1/20W
MF
201
IN
IN
D4
FB_A0_WCLK_P & lt; 0 & gt;
FB_A0_WCLK_N & lt; 0 & gt;
D5
CK
CK*
CS*
WE*
CAS*
RAS*
ZQ
MF (MF=0)
SEN
RESET*
ABI*
EDC0
EDC1
EDC2
EDC3
WCK01
WCK01*
100
77
79
100 77 6
100 77 6
IN
IN
P4
FB_A0_WCLK_P & lt; 1 & gt;
FB_A0_WCLK_N & lt; 1 & gt;
P5
WCK23
WCK23*
C8491
0.01UF
2
10%
10V
PLACE_NEAR=U8450.J11:8.4MM
X5R-CERM
0201
U8400
76 7
80 79
P2
FB_A0_DBI_L & lt; 3 & gt;
BI
1
4.7UF
2
C8401
1
4.7UF
20%
6.3V
X5R
402
2
20%
6.3V
X5R
402
BI
BI
H5
FB_A1_A & lt; 0 & gt;
H4
6 77 100
B4
FB_A0_DQ & lt; 2 & gt;
B2
BI
BI
FB_A0_DQ & lt; 3 & gt;
6 77 100
6 77 100
IN
FB_A1_A & lt; 6 & gt;
K5
100 77
IN
FB_A1_CKE_L
J3
100 79 77
IN
FB_A1_CLK_P
J12
J11
100 77 6
E4
FB_A0_DQ & lt; 4 & gt;
BI
6 77 100
E2
FB_A0_DQ & lt; 5 & gt;
BI
6 77 100
F4
FB_A0_DQ & lt; 6 & gt;
F2
BI
A11
A13
6 77 100
BI
FB_A0_DQ & lt; 8 & gt;
6 77 100
BI
FB_A0_DQ & lt; 7 & gt;
6 77 100
100 77
B13
IN
FB_A1_CS_L
G12
100 77
BI
IN
FB_A1_WE_L
L12
6 77 100
FB_A0_DQ & lt; 10 & gt;
B11
IN
FB_A1_CLK_N
100 79 77
FB_A0_DQ & lt; 9 & gt;
BI
6 77 100
BI
6 77 100
FB_A0_DQ & lt; 11 & gt;
100 77
100 77
IN
FB_A1_CAS_L
L3
IN
FB_A1_RAS_L
G3
J13
FB_A1_ZQ
E11
FB_A0_DQ & lt; 12 & gt;
BI
6 77 100
E13
FB_A0_DQ & lt; 13 & gt;
BI
6 77 100
R8450
BI
6 77 100
120
BI
6 77 100
F11
FB_A0_DQ & lt; 14 & gt;
F13
FB_A0_DQ & lt; 15 & gt;
U11
FB_A0_DQ & lt; 16 & gt;
T11
6 77 100
FB_A0_DQ & lt; 17 & gt;
U13
BI
BI
BI
T13
BI
M11
BI
BI
BI
100 77 6
6 77 100
BI
6 77 100
100 77 6
100 77 6
FB_A0_DQ & lt; 30 & gt;
BI
BI
FB_A1_EDC & lt; 1 & gt;
C13
BI
FB_A1_EDC & lt; 2 & gt;
R13
BI
FB_A1_EDC & lt; 3 & gt;
R2
80 79 76 7
G10
VSS
L1
BI
IN
FB_A1_WCLK_P & lt; 0 & gt;
D4
IN
FB_A1_WCLK_N & lt; 0 & gt;
D5
IN
FB_A1_WCLK_P & lt; 1 & gt;
P4
IN
FB_A1_WCLK_N & lt; 1 & gt;
P5
C8404
1
C8405
4.7UF
2
4.7UF
H14
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.1 mm
2
20%
6.3V
X5R
402
NC
2
2
IN
6 77 100
1
C8406
R5
C8407
1
C8408
1
C8409
1UF
2
1UF
1UF
1UF
20%
6.3V
X5R
0201
20%
6.3V
X5R
0201
20%
6.3V
X5R
0201
20%
6.3V
X5R
0201
2
2
2
C8450
1
4.7UF
2
PLACE_NEAR=U8400.J14:8.4MM
1
20%
6.3V
X5R
402
C8451
1
4.7UF
2
20%
6.3V
X5R
402
4.7UF
2
D10
G4
20%
6.3V
X5R
402
1
1
C8413
OMIT_TABLE
R8431
1.33K
10%
25V
X7R-CERM
0201
2
1%
1/20W
MF
201
1
2
1
20%
6.3V
X5R
402
C8454
1
H14
VDD
VSS
1UF
20%
6.3V
X5R
0201
20%
6.3V
X5R
0201
2
2
2
D1
C8414
1UF
2
C8415
1UF
20%
6.3V
X5R
0201
2
20%
6.3V
X5R
0201
C8416
0.1UF
2
10%
6.3V
X5R
201
C8417
0.1UF
2
10%
6.3V
X5R
201
A14
4.7UF
2
20%
6.3V
X5R
402
4.7UF
1%
1/20W
MF
2 201
C8418
0.1UF
2
C8419
0.1UF
10%
6.3V
X5R
201
2
10%
6.3V
X5R
201
C8420
0.1UF
2
10%
6.3V
X5R
201
C8421
0.1UF
2
10%
6.3V
X5R
201
F1
1
IN
C8456
1
1UF
77 79 80
2
1
PLACE CLOSE TO U8400
20%
6.3V
X5R
0201
2
C8457
1
1UF
2
C8460
1
1UF
C4
20%
6.3V
X5R
402
P11
2
C12
20%
6.3V
X5R
0201
C8458
1
1UF
2
20%
6.3V
X5R
0201
1
C8424
1
C8425
0.1UF
2
0.1UF
0.1UF
0.1UF
10%
6.3V
X5R
201
10%
6.3V
X5R
201
10%
6.3V
X5R
201
10%
6.3V
X5R
201
2
2
2
G13
VDDQ
H3
20%
6.3V
X5R
0201
C8461
1
1UF
2
E14
PLACE_NEAR=U8400.U10:8.4MM
2
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.1 mm
1 R8432
C8459
H2
H13
M1
6 77 100
BI
6 77 100
E11
FB_A1_DQ & lt; 12 & gt;
BI
6 77 100
E13
FB_A1_DQ & lt; 13 & gt;
BI
6 77 100
F11
FB_A1_DQ & lt; 14 & gt;
BI
6 77 100
F13
FB_A1_DQ & lt; 15 & gt;
BI
6 77 100
U11
FB_A1_DQ & lt; 16 & gt;
BI
6 77 100
U13
FB_A1_DQ & lt; 17 & gt;
BI
6 77 100
T11
FB_A1_DQ & lt; 18 & gt;
BI
6 77 100
T13
FB_A1_DQ & lt; 19 & gt;
BI
6 77 100
N11
FB_A1_DQ & lt; 20 & gt;
BI
6 77 100
N13
FB_A1_DQ & lt; 21 & gt;
BI
6 77 100
M11
FB_A1_DQ & lt; 22 & gt;
BI
6 77 100
M13
FB_A1_DQ & lt; 23 & gt;
BI
6 77 100
U4
FB_A1_DQ & lt; 24 & gt;
BI
6 77 100
U2
FB_A1_DQ & lt; 25 & gt;
BI
6 77 100
T4
FB_A1_DQ & lt; 26 & gt;
BI
6 77 100
T2
FB_A1_DQ & lt; 27 & gt;
BI
6 77 100
N4
FB_A1_DQ & lt; 28 & gt;
BI
6 77 100
N2
FB_A1_DQ & lt; 29 & gt;
BI
6 77 100
M4
FB_A1_DQ & lt; 30 & gt;
BI
6 77 100
M2
FB_A1_DQ & lt; 31 & gt;
BI
6 77 100
FB_A1_A & lt; 8 & gt;
IN
C8462
1
20%
6.3V
X5R
0201
1UF
2
20%
6.3V
X5R
0201
C8463
1UF
2
20%
6.3V
X5R
0201
M12
6 77 100
NC
=PP1V35_GPU_FBVDDQ
1
R8480
549
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.1 mm
1%
1/20W
MF
201
PLACE_NEAR=U8450.J14:8.4MM
FB_A1_VREFC
79
PLACE_NEAR=U8450.J14:8.4MM
1
C8481
PLACE_NEAR=U8450.J14:8.4MM
R8481
1
1.33K
820PF
10%
25V
X7R-CERM
0201
2
1%
1/20W
MF
201
R8484
931
1%
1/20W
MF
2 201
FB_SW_LEG
77 79 80
B
A1
A3
PLACE CLOSE TO U8450
A12
A14
E5
C4
C11
C12
20%
6.3V
X5R
0201
C8465
1
1UF
2
20%
6.3V
X5R
0201
C8466
1
0.1UF
2
10%
6.3V
X5R
201
C8467
0.1UF
2
10%
6.3V
X5R
201
C8468
1
0.1UF
1
M10
1
N1
1
C8432
820PF
N3
N14
2
C8433
820PF
10%
25V
X7R-CERM
0201
2
10%
25V
X7R-CERM
0201
10%
6.3V
X5R
201
C8469
1
0.1UF
2
10%
6.3V
X5R
201
C8470
1
0.1UF
2
10%
6.3V
X5R
201
C8471
0.1UF
2
10%
6.3V
X5R
201
1
1.33K
H3
VDDQ
E12
H12
F5
C8472
1
C8473
1
C8474
1
C8475
FB_A1_VREFD
2
79
PLACE_NEAR=U8450.U10:8.4MM
PLACE_NEAR=U8450.A10:8.4MM
VSSQ
1
H2
1
H13
M1
M3
K13
M12
1
2
M5
FB_SW_LEG
R1
P14
R3
0.1UF
PLACE_NEAR=U8400.A10:8.4MM
10%
25V
X7R-CERM
0201
2
1%
1/20W
MF
201
10%
25V
X7R-CERM
0201
2
0.1UF
0.1UF
10%
6.3V
X5R
201
10%
6.3V
X5R
201
10%
6.3V
X5R
201
2
2
2
2
M10
N1
1
1.33K
R8485
931
2
1%
1/20W
MF
201
FB_SW_LEG
N12
P3
N14
SYNC_MASTER=J31_SREE
R1
PAGE TITLE
P14
R3
R4
T3
PLACE_NEAR=U8400.U10:8.4MM
SYNC_DATE=10/25/2011
GDDR5 Frame Buffer A
DRAWING NUMBER
R11
R12
R14
Apple Inc.
R12
051-9585
U1
A10
79
U3
79
U12
VREFD
7
FB_A1_VREFC
FB_A1_VREFD
J14
U3
VREFC
U12
A10
R
U10
VREFD
U14
U14
6
5
4
3
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
2
SIZE
D
REVISION
3.0.0
R14
U1
VREFC
77 79 80
PLACE_NEAR=U8450.U10:8.4MM
P12
T12
PLACE_NEAR=U8400.U10:8.4MM
IN
N3
R4
R11
IN
77 79
80
0.1UF
10%
6.3V
X5R
201
PLACE_NEAR=U8450.U10:8.4MM
R8483
C8483
820PF
C8482
820PF
K2
T1
P12
2
1%
1/20W
MF
201
F10
P1
1
549
E14
N5
1%
1/20W
MF
201
1 R8482
C14
E3
N10
R8435
931
1%
1/20W
MF
2 201
PLACE_NEAR=U8450.U10:8.4MM
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.1 mm
E1
G13
M14
PLACE_NEAR=U8400.U10:8.4MM
R8433
80 79 76 7
C3
F1
=PP1V35_GPU_FBVDDQ
C1
E10
L2
2
N12
U10
IN
PLACE_NEAR=U8450.J14:8.4MM
D1
L13
1
M5
P3
1
1%
1/20W
MF
2 201
FB_A0_VREFD
79
K13
J14
C
NC
J5
80 79 76 7
B14
K12
K2
M3
T14
8
BI
FB_A1_DQ & lt; 11 & gt;
2
T14
FB_A0_VREFD
FB_A1_DQ & lt; 10 & gt;
B13
B12
20%
6.3V
X5R
0201
549
F10
T12
79
6 77 100
B11
T10
K3
F5
VSSQ
C8464
1UF
E12
H12
T3
FB_A0_VREFC
BI
T5
F14
1
E3
T1
79
6 77 100
FB_A1_DQ & lt; 9 & gt;
B3
1UF
2
80 79 76 7
C14
P1
C8423
BI
A13
1
=PP1V35_GPU_FBVDDQ
E1
N10
1
C8422
6 77 100
FB_A1_DQ & lt; 8 & gt;
P10
R5
C11
N5
1
BI
A11
B1
C3
M14
A
6 77 100
FB_A1_DQ & lt; 7 & gt;
OMIT_TABLE
C1
L13
1
6 77 100
BI
F2
L10
F3
E5
E10
L2
1
BI
FB_A1_DQ & lt; 6 & gt;
A12
K12
1
FB_A1_DQ & lt; 5 & gt;
F4
A3
K3
1
E2
D
K14
G2
1
BI
6 77 100
A1
G2
1
6 77 100
L5
R10
FB_SW_LEG
F14
1
BI
FB_A1_DQ & lt; 4 & gt;
931
PLACE_NEAR=U8400.J14:8.4MM
F12
1
FB_A1_DQ & lt; 3 & gt;
E4
K1
L14
C8455
R8434
B3
B14
C8453
4.7UF
PLACE_NEAR=U8400.J14:8.4MM
B12
F3
2
1UF
20%
6.3V
X5R
0201
6 77 100
B2
H1
G14
F12
C8412
1UF
6 77 100
BI
G10
G11
L11
820PF
2
D14
C8411
BI
FB_A1_DQ & lt; 2 & gt;
G5
D14
1
6 77 100
FB_A1_DQ & lt; 1 & gt;
B4
B10
G1
C8452
D12
20%
6.3V
X5R
0201
BI
A2
2
1
C8431
T10
D3
1UF
FB_A1_DQ & lt; 0 & gt;
B5
(2 OF 2)
L1
PLACE_NEAR=U8400.J14:8.4MM
T5
D12
C8410
6 77 100
A4
U5
D3
1
BI
NC
C5
=PP1V35_GPU_FBVDDQ
1%
1/20W
MF
201
FB_A0_VREFC
1
B1
1
6 77 100
FB_A1_DBI_L & lt; 3 & gt;
BGA
H5GQ1H24AFR-T2C
NC
P10
R10
B
6 77 100
BI
P2
A5
32MX32-1.25GHZ-MFL
FB_A0_A & lt; 8 & gt;
79
L10
P11
20%
6.3V
X5R
402
WCK23
WCK23*
6 77 100
BI
FB_A1_DBI_L & lt; 2 & gt;
K14
L5
L14
4.7UF
20%
6.3V
X5R
402
WCK01
WCK01*
BI
FB_A1_DBI_L & lt; 1 & gt;
P13
U8450
L4
L4
1
C8403
EDC0
EDC1
EDC2
EDC3
FB_A1_DBI_L & lt; 0 & gt;
D13
6 77 100
R8430
549
K1
L11
1
ABI*
6 77 100
FB_A0_DQ & lt; 31 & gt;
M2
BI
C2
6 77 100
BI
FB_A0_DQ & lt; 29 & gt;
M4
6 77 100
100 77 6
BI
FB_A0_DQ & lt; 28 & gt;
N2
6 77 100
FB_A1_ABI_L
FB_A1_EDC & lt; 0 & gt;
6 77 100
BI
FB_A0_DQ & lt; 27 & gt;
N4
100 77 6
IN
J4
CK
CK*
CS*
WE*
CAS*
RAS*
ZQ
MF (MF=0)
SEN
RESET*
D2
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
A8/A7
A9/A1
A10/A0
A11/A6
CKE*
6 77 100
BI
FB_A0_DQ & lt; 26 & gt;
T2
100 77 6
100 77 6
BI
FB_A0_DQ & lt; 25 & gt;
T4
1%
1/20W
MF
201 2
100 77 6
BI
IN
J2
FB_A1_RESET_L
120
1%
1/20W
MF
201 2
6 77 100
FB_A0_DQ & lt; 24 & gt;
U2
2
6 77 100
FB_A0_DQ & lt; 23 & gt;
U4
1
6 77 100
FB_A0_DQ & lt; 22 & gt;
M13
R8453
120
100 77
100 77 6
FB_A0_DQ & lt; 21 & gt;
N13
R8454
1
6 77 100
FB_A0_DQ & lt; 20 & gt;
J10
FB_A1_SEN
6 77 100
FB_A0_DQ & lt; 19 & gt;
N11
1%
1/20W
MF
201
J1
FB_A1_MF
1
6 77 100
FB_A0_DQ & lt; 18 & gt;
DBI0*
DBI1*
DBI2*
DBI3*
(1 OF 2)
OMIT_TABLE
D11
H1
VDD
FB_A1_A & lt; 1 & gt;
IN
6 77 100
FB_A0_DQ & lt; 1 & gt;
G5
G11
G14
IN
100 77 6
FB_A0_DQ & lt; 0 & gt;
A2
80 79 76 7
D10
G4
20%
6.3V
X5R
402
K4
100 77 6
A4
=PP1V35_GPU_FBVDDQ
1
4.7UF
2
IN
FB_A1_A & lt; 7 & gt;
C10
G1
C8402
H10
6 77 100
1
C8400
FB_A1_A & lt; 3 & gt;
6 77 100
FB_A0_DBI_L & lt; 2 & gt;
BA0/A2
BA1/A5
BA2/A4
BA3/A3
B10
D11
1
IN
100 77 6
BI
P13
B5
(2 OF 2)
C10
IN
K11
6 77 100
U5
C5
=PP1V35_GPU_FBVDDQ
K10
FB_A1_A & lt; 4 & gt;
6 77 100
BI
J5
NC
BGA
H5GQ1H24AFR-T2C
H11
FB_A1_A & lt; 5 & gt;
100 77 6
BI
FB_A0_DBI_L & lt; 1 & gt;
IN
100 77 6
FB_A0_DBI_L & lt; 0 & gt;
A5
32MX32-1.25GHZ-MFL
FB_A1_A & lt; 2 & gt;
IN
100 77 6
100 77 6
D2
D13
BRANCH
PAGE
84 OF 132
SHEET
79 OF 105
1
A
8
7
6
5
4
3
2
1
Page Notes
U8550
U8500
Power aliases required by this page:
32MX32-1.25GHZ-MFL
32MX32-1.25GHZ-MFL
- =PP1V5R1V35_S0_FB_VDD
BGA
H5GQ1H24AFR-T2C
BGA
H5GQ1H24AFR-T2C
Signal aliases required by this page:
(NONE)
100 77 6
IN
FB_B0_A & lt; 2 & gt;
H11
100 77 6
BOM options provided by this page:
IN
FB_B0_A & lt; 5 & gt;
K10
IN
FB_B0_A & lt; 4 & gt;
100 77 6
(NONE)
100 77 6
CK TERMINATION - B0
D
FB_B0_CLK_P
1
80 77
100
40.2
40.2
FBB0_CK_MID
1
1%
1/20W
MF
201
FB_B0_A & lt; 7 & gt;
K4
IN
FB_B0_A & lt; 1 & gt;
H5
100 77 6
77 80 100
100 77 6
1%
1/20W
MF
201
1
PLACE_NEAR=U8500.J12:8.4MM
FB_B0_CLK_N
2
IN
100 77 6
R8502
2
100 77
FB_B0_A & lt; 0 & gt;
IN
FB_B0_A & lt; 6 & gt;
IN
FB_B0_CKE_L
J3
J12
IN
FB_B0_CLK_P
100 80 77
10%
10V
X5R-CERM
0201 PLACE_NEAR=U8500.J11:8.4MM
K5
IN
FB_B0_CLK_N
IN
FB_B0_CS_L
100 77
100 77
IN
100 77
IN
G12
L12
FB_B0_CAS_L
IN
J11
FB_B0_WE_L
FB_B0_RAS_L
100 77
L3
G3
FB_B0_ZQ
R8500
J13
FB_B0_MF
1
J1
J10
FB_B0_SEN
120
1%
1/20W
MF
201 2
R8504
1
R8503
120
100 77
1
IN
J2
FB_B0_RESET_L
120
1%
1/20W
MF
201 2
1%
1/20W
MF
201
100 77 6
2
100 77 6
IN
BI
J4
FB_B0_ABI_L
FB_B0_EDC & lt; 0 & gt;
C2
100 77 6
BI
FB_B0_EDC & lt; 1 & gt;
C13
100 77 6
BI
FB_B0_EDC & lt; 2 & gt;
R13
BI
FB_B0_EDC & lt; 3 & gt;
100 77 6
CK TERMINATION - B1
PLACE_NEAR=U8550.J11:8.4MM
100 77 6
R8551
R8552
40.2
FB_B1_CLK_P
1
C
2
1%
1/20W
MF
201
1
1
100 77 6
40.2
FBB1_CK_MID
FB_B1_CLK_N
2
1%
1/20W
MF
201
DBI0*
DBI1*
DBI2*
DBI3*
(1 OF 2)
A8/A7
A9/A1
A10/A0
A11/A6
CKE*
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
OMIT_TABLE
100 80 77
0.01UF
H4
IN
C8590
2
H10
FB_B0_A & lt; 3 & gt;
100 77 6
PLACE_NEAR=U8500.J11:8.4MM
R8501
IN
K11
BA0/A2
BA1/A5
BA2/A4
BA3/A3
IN
D4
FB_B0_WCLK_P & lt; 0 & gt;
IN
R2
FB_B0_WCLK_N & lt; 0 & gt;
D5
CK
CK*
CS*
WE*
CAS*
RAS*
ZQ
MF (MF=0)
SEN
RESET*
ABI*
EDC0
EDC1
EDC2
EDC3
WCK01
WCK01*
100
77
80
100 77 6
100 77 6
IN
IN
P4
FB_B0_WCLK_P & lt; 1 & gt;
FB_B0_WCLK_N & lt; 1 & gt;
P5
WCK23
WCK23*
C8591
0.01UF
PLACE_NEAR=U8550.J12:8.4MM
2
10%
10V
X5R-CERM
0201
U8500
PLACE_NEAR=U8550.J11:8.4MM
76 7
80 79
IN
FB_B1_A & lt; 3 & gt;
H10
100 77 6
IN
FB_B1_A & lt; 7 & gt;
K4
100 77 6
IN
FB_B1_A & lt; 1 & gt;
H5
100 77 6
BI
IN
FB_B1_A & lt; 0 & gt;
H4
6 77 100
P13
FB_B0_DBI_L & lt; 2 & gt;
P2
FB_B0_DBI_L & lt; 3 & gt;
BI
6 77 100
A4
FB_B0_DQ & lt; 0 & gt;
BI
6 77 100
A2
FB_B0_DQ & lt; 1 & gt;
BI
6 77 100
B4
FB_B0_DQ & lt; 2 & gt;
B2
BI
6 77 100
BI
FB_B0_DQ & lt; 3 & gt;
6 77 100
IN
FB_B1_A & lt; 6 & gt;
K5
100 77
IN
FB_B1_CKE_L
J3
100 80 77
IN
FB_B1_CLK_P
J12
J11
100 77 6
E4
FB_B0_DQ & lt; 4 & gt;
BI
6 77 100
E2
FB_B0_DQ & lt; 5 & gt;
BI
6 77 100
F4
FB_B0_DQ & lt; 6 & gt;
F2
BI
A11
A13
6 77 100
BI
FB_B0_DQ & lt; 8 & gt;
6 77 100
100 77
B13
IN
FB_B1_CS_L
G12
100 77
BI
IN
FB_B1_WE_L
L12
6 77 100
FB_B0_DQ & lt; 10 & gt;
B11
IN
FB_B1_CLK_N
100 80 77
FB_B0_DQ & lt; 9 & gt;
BI
6 77 100
BI
6 77 100
FB_B0_DQ & lt; 11 & gt;
100 77
100 77
IN
FB_B1_CAS_L
L3
IN
FB_B1_RAS_L
G3
J13
FB_B1_ZQ
E11
FB_B0_DQ & lt; 12 & gt;
BI
6 77 100
E13
FB_B0_DQ & lt; 13 & gt;
BI
6 77 100
R8550
BI
6 77 100
120
BI
6 77 100
F11
FB_B0_DQ & lt; 14 & gt;
F13
FB_B0_DQ & lt; 15 & gt;
U11
FB_B0_DQ & lt; 16 & gt;
T11
6 77 100
FB_B0_DQ & lt; 17 & gt;
U13
BI
BI
BI
T13
BI
M11
BI
BI
BI
FB_B0_DQ & lt; 27 & gt;
N4
6 77 100
100 77 6
100 77 6
6 77 100
BI
6 77 100
100 77 6
100 77 6
FB_B0_DQ & lt; 30 & gt;
BI
FB_B1_ABI_L
BI
C2
BI
FB_B1_EDC & lt; 1 & gt;
C13
BI
FB_B1_EDC & lt; 2 & gt;
R13
BI
FB_B1_EDC & lt; 3 & gt;
R2
IN
FB_B1_WCLK_P & lt; 0 & gt;
D4
IN
FB_B1_WCLK_N & lt; 0 & gt;
D5
BI
IN
FB_B1_WCLK_P & lt; 1 & gt;
P4
IN
FB_B1_WCLK_N & lt; 1 & gt;
P5
1
4.7UF
2
C8501
1
4.7UF
20%
6.3V
X5R
402
2
20%
6.3V
X5R
402
4.7UF
2
NC
80 79 76 7
IN
6 77 100
1
1
H1
G14
H14
VSS
L1
C8550
1
C8551
1
C8504
1
C8505
4.7UF
2
4.7UF
20%
6.3V
X5R
402
R8530
2
1%
1/20W
MF
2 201
2
2
R5
2
1
T5
T10
B
C8507
1
C8508
1
C8509
2
1UF
1UF
1UF
20%
6.3V
X5R
0201
20%
6.3V
X5R
0201
20%
6.3V
X5R
0201
20%
6.3V
X5R
0201
2
2
2
C8531
820PF
OMIT_TABLE
1
2
10%
25V
X7R-CERM
0201
R8531
1
1.33K
1%
1/20W
MF
2 201
G4
20%
6.3V
X5R
402
2
2
G11
G14
H1
VDD
VSS
C8553
1
20%
6.3V
X5R
402
C8554
1
C8511
1
C8512
1
C8513
1UF
1UF
20%
6.3V
X5R
0201
20%
6.3V
X5R
0201
20%
6.3V
X5R
0201
2
2
2
B14
PLACE_NEAR=U8500.J14:8.4MM
D1
A12
C8514
1UF
1UF
2
C8515
20%
6.3V
X5R
0201
2
20%
6.3V
X5R
0201
C8516
0.1UF
2
10%
6.3V
X5R
201
C8517
0.1UF
2
10%
6.3V
X5R
201
4.7UF
2
20%
6.3V
X5R
402
4.7UF
2
20%
6.3V
X5R
402
F1
1
IN
77 79 80
2
PLACE_NEAR=U8500.J14:8.4MM
C8518
0.1UF
C8519
0.1UF
10%
6.3V
X5R
201
2
10%
6.3V
X5R
201
C8520
0.1UF
2
10%
6.3V
X5R
201
C8521
0.1UF
2
10%
6.3V
X5R
201
C8556
1
C8557
1
C8558
1
C8559
C14
E1
G13
1UF
1UF
C8523
1
C8524
1
C8525
2
0.1UF
0.1UF
0.1UF
10%
6.3V
X5R
201
10%
6.3V
X5R
201
10%
6.3V
X5R
201
10%
6.3V
X5R
201
2
2
2
VDDQ
H3
20%
6.3V
X5R
0201
20%
6.3V
X5R
0201
2
2
D1
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.1 mm
1
6 77 100
BI
6 77 100
F13
FB_B1_DQ & lt; 15 & gt;
BI
6 77 100
U11
FB_B1_DQ & lt; 16 & gt;
BI
6 77 100
U13
FB_B1_DQ & lt; 17 & gt;
BI
6 77 100
T11
FB_B1_DQ & lt; 18 & gt;
BI
6 77 100
T13
FB_B1_DQ & lt; 19 & gt;
BI
6 77 100
N11
FB_B1_DQ & lt; 20 & gt;
BI
6 77 100
N13
FB_B1_DQ & lt; 21 & gt;
BI
6 77 100
M11
FB_B1_DQ & lt; 22 & gt;
BI
6 77 100
M13
FB_B1_DQ & lt; 23 & gt;
BI
6 77 100
U4
FB_B1_DQ & lt; 24 & gt;
BI
6 77 100
U2
FB_B1_DQ & lt; 25 & gt;
BI
6 77 100
T4
FB_B1_DQ & lt; 26 & gt;
BI
6 77 100
T2
FB_B1_DQ & lt; 27 & gt;
BI
6 77 100
N4
FB_B1_DQ & lt; 28 & gt;
BI
6 77 100
N2
FB_B1_DQ & lt; 29 & gt;
BI
6 77 100
M4
FB_B1_DQ & lt; 30 & gt;
BI
6 77 100
M2
FB_B1_DQ & lt; 31 & gt;
BI
6 77 100
FB_B1_A & lt; 8 & gt;
IN
C8560
1
C8561
1
1UF
C8562
1
6 77 100
NC
80 79 76 7
=PP1V35_GPU_FBVDDQ
PLACE_NEAR=U8550.J14:8.4MM
R8580
549
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.1 mm
1%
1/20W
MF
2 201
80
PLACE_NEAR=U8550.J14:8.4MM
1
PLACE_NEAR=U8550.J14:8.4MM
C8581
PLACE_NEAR=U8550.J14:8.4MM
R8581
1
1.33K
820PF
10%
25V
X7R-CERM
0201
R8584
931
1%
1/20W
MF
2 201
1%
1/20W
MF
201
80
77 79 80
B
PLACE CLOSE TO U8550
1UF
C8563
1UF
A14
20%
6.3V
X5R
0201
2
20%
6.3V
X5R
0201
2
20%
6.3V
X5R
0201
2
20%
6.3V
X5R
0201
=PP1V35_GPU_FBVDDQ
E5
C1
E10
C3
F1
C4
C12
1
C8564
1
C8565
1
C8566
1
C8567
1UF
2
1UF
0.1UF
0.1UF
20%
6.3V
X5R
0201
20%
6.3V
X5R
0201
10%
6.3V
X5R
201
10%
6.3V
X5R
201
2
2
2
80 79 76 7
C11
C14
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.1 mm
PLACE_NEAR=U8550.U10:8.4MM
1
E3
H3
VDDQ
FB_B1_VREFD
E12
H12
R8582
549
E1
G13
2
80
1%
1/20W
MF
201
E14
K3
PLACE_NEAR=U8550.U10:8.4MM
F5
K12
PLACE_NEAR=U8500.U10:8.4MM
F10
VSSQ
F10
L13
1
H13
K2
M3
K13
1
M12
VSSQ
H2
M1
1
R8533
2
M10
C8533
820PF
10%
25V
X7R-CERM
0201
10%
25V
X7R-CERM
0201
1
1.33K
820PF
M5
1%
1/20W
MF
201
C8532
2
2
1
0.1UF
R8535
931
2
C8568
2
1%
1/20W
MF
201
10%
6.3V
X5R
201
C8569
1
0.1UF
2
10%
6.3V
X5R
201
C8570
1
0.1UF
2
10%
6.3V
X5R
201
C8571
0.1UF
2
10%
6.3V
X5R
201
H2
1
H13
1
M1
K2
M3
M5
M14
2
PLACE_NEAR=U8550.A10:8.4MM
N3
N14
PLACE_NEAR=U8500.U10:8.4MM
N12
IN
PLACE_NEAR=U8500.U10:8.4MM
C8572
1
C8573
1
C8574
1
C8575
R1
P14
2
R3
0.1UF
0.1UF
0.1UF
10%
6.3V
X5R
201
10%
6.3V
X5R
201
10%
6.3V
X5R
201
10%
6.3V
X5R
201
2
2
2
2
1%
1/20W
MF
201
931
1%
1/20W
MF
2 201
P3
N14
SYNC_MASTER=J31_SREE
R1
PAGE TITLE
P14
R3
R4
DRAWING NUMBER
R11
R12
T14
SYNC_DATE=10/25/2011
GDDR5 Frame Buffer B
R11
R14
Apple Inc.
R12
051-9585
U1
A10
80
U12
VREFD
7
FB_B1_VREFC
J14
80
U3
FB_B1_VREFD
U3
A10
U10
VREFC
U12
R
VREFD
U14
U14
6
5
4
3
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
2
SIZE
D
REVISION
3.0.0
R14
U1
VREFC
77 79 80
N12
P12
R4
T14
IN
PLACE_NEAR=U8550.U10:8.4MM
T1
P12
0.1UF
PLACE_NEAR=U8500.A10:8.4MM
10%
25V
X7R-CERM
0201
R8585
N3
P1
1
2
1
FB_SW_LEG
N1
N10
77 79 80
820PF
10%
25V
X7R-CERM
0201
PLACE_NEAR=U8550.U10:8.4MM
R8583
1.33K
C8583
M10
N5
FB_SW_LEG
1
C8582
820PF
K13
M12
N1
P3
U10
IN
A12
G2
R8532
1%
1/20W
MF
2 201
1
J14
C
NC
J5
A3
F14
549
FB_B0_VREFD
E14
T12
8
BI
FB_B1_DQ & lt; 14 & gt;
A1
T3
FB_B0_VREFD
FB_B1_DQ & lt; 13 & gt;
F11
FB_SW_LEG
T12
80
6 77 100
E13
F5
T3
FB_B0_VREFC
BI
B14
2
PLACE_NEAR=U8500.U10:8.4MM
E12
H12
T1
80
6 77 100
FB_B1_DQ & lt; 12 & gt;
B12
20%
6.3V
X5R
0201
1UF
2
80 79 76 7
E3
P1
1
0.1UF
6 77 100
BI
E11
B3
1UF
20%
6.3V
X5R
0201
C12
N10
C8522
BI
FB_B1_DQ & lt; 11 & gt;
2
F3
N5
1
FB_B1_DQ & lt; 10 & gt;
B13
T10
C11
M14
A
6 77 100
B11
1
T5
L2
2
BI
P10
R5
D14
1
C4
L2
1
6 77 100
FB_B1_DQ & lt; 9 & gt;
2
=PP1V35_GPU_FBVDDQ
L13
1
BI
A13
L10
P11
PLACE CLOSE TO U8500
C3
K12
1
6 77 100
FB_B1_DQ & lt; 8 & gt;
OMIT_TABLE
C1
K3
1
BI
A11
B1
A14
E5
E10
G2
1
6 77 100
FB_B1_DQ & lt; 7 & gt;
A3
F14
1
6 77 100
BI
F2
A1
F12
1
BI
FB_B1_DQ & lt; 6 & gt;
D
K14
F12
1
FB_B1_DQ & lt; 5 & gt;
F4
L5
1UF
F3
2
1UF
E2
K1
L14
C8555
R8534
FB_SW_LEG
D14
1
BI
6 77 100
H14
D12
20%
6.3V
X5R
0201
6 77 100
1
4.7UF
20%
6.3V
X5R
402
R10
1%
1/20W
MF
2 201
B3
D3
1UF
BI
FB_B1_DQ & lt; 4 & gt;
G10
4.7UF
931
B12
D12
C8510
FB_B1_DQ & lt; 3 & gt;
E4
D10
D3
1
6 77 100
B2
FB_B1_VREFC
1
1UF
6 77 100
BI
G5
20%
6.3V
X5R
402
4.7UF
PLACE_NEAR=U8500.J14:8.4MM
B1
C8506
BI
FB_B1_DQ & lt; 2 & gt;
B10
G1
L4
1
FB_B0_VREFC
P10
R10
1
6 77 100
FB_B1_DQ & lt; 1 & gt;
B4
B5
(2 OF 2)
L1
80
L10
P11
20%
6.3V
X5R
402
BI
A2
K14
L5
L14
4.7UF
20%
6.3V
X5R
402
FB_B1_DQ & lt; 0 & gt;
U5
L11
1
6 77 100
A4
NC
C8552
4.7UF
549
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.1 mm
K1
L4
C8503
BI
A5
C5
=PP1V35_GPU_FBVDDQ
PLACE_NEAR=U8500.J14:8.4MM
G10
G11
L11
1
6 77 100
FB_B1_DBI_L & lt; 3 & gt;
BGA
H5GQ1H24AFR-T2C
NC
=PP1V35_GPU_FBVDDQ
G5
VDD
WCK23
WCK23*
6 77 100
BI
P2
32MX32-1.25GHZ-MFL
FB_B0_A & lt; 8 & gt;
80 79 76 7
D10
G4
20%
6.3V
X5R
402
WCK01
WCK01*
6 77 100
BI
FB_B1_DBI_L & lt; 2 & gt;
U8550
C10
G1
C8502
EDC0
EDC1
EDC2
EDC3
BI
FB_B1_DBI_L & lt; 1 & gt;
P13
B10
D11
C8500
ABI*
FB_B1_DBI_L & lt; 0 & gt;
D13
6 77 100
D11
1
CK
CK*
CS*
WE*
CAS*
RAS*
ZQ
MF (MF=0)
SEN
RESET*
D2
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
A8/A7
A9/A1
A10/A0
A11/A6
CKE*
6 77 100
FB_B0_DQ & lt; 31 & gt;
M2
J4
FB_B1_EDC & lt; 0 & gt;
6 77 100
BI
FB_B0_DQ & lt; 29 & gt;
M4
6 77 100
BI
FB_B0_DQ & lt; 28 & gt;
N2
100 77 6
IN
6 77 100
BI
DBI0*
DBI1*
DBI2*
DBI3*
(1 OF 2)
6 77 100
BI
FB_B0_DQ & lt; 26 & gt;
T2
100 77 6
100 77 6
BI
FB_B0_DQ & lt; 25 & gt;
T4
1%
1/20W
MF
201 2
100 77 6
BI
IN
J2
FB_B1_RESET_L
120
1%
1/20W
MF
201 2
6 77 100
FB_B0_DQ & lt; 24 & gt;
U2
2
6 77 100
FB_B0_DQ & lt; 23 & gt;
U4
1
6 77 100
FB_B0_DQ & lt; 22 & gt;
M13
R8553
120
100 77
100 77 6
FB_B0_DQ & lt; 21 & gt;
N13
R8554
1
6 77 100
FB_B0_DQ & lt; 20 & gt;
J10
FB_B1_SEN
6 77 100
FB_B0_DQ & lt; 19 & gt;
N11
1%
1/20W
MF
201
J1
FB_B1_MF
1
6 77 100
FB_B0_DQ & lt; 18 & gt;
BA0/A2
BA1/A5
BA2/A4
BA3/A3
OMIT_TABLE
6 77 100
BI
FB_B0_DQ & lt; 7 & gt;
B5
(2 OF 2)
C10
IN
K11
6 77 100
U5
C5
=PP1V35_GPU_FBVDDQ
K10
FB_B1_A & lt; 4 & gt;
6 77 100
BI
J5
NC
BGA
H5GQ1H24AFR-T2C
H11
FB_B1_A & lt; 5 & gt;
100 77 6
BI
FB_B0_DBI_L & lt; 1 & gt;
IN
100 77 6
FB_B0_DBI_L & lt; 0 & gt;
A5
32MX32-1.25GHZ-MFL
FB_B1_A & lt; 2 & gt;
IN
100 77 6
100 77 6
D2
D13
BRANCH
PAGE
85 OF 132
SHEET
80 OF 105
1
A
8
7
6
5
4
3
DP_TBTSNK0_AUXCH_C_P
L8608
DP_TBTSNK0_AUXCH_C_N
VOLTAGE=1.8V
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 mm
FERR-220-OHM-2A
=PP1V8_GPU_IFPAB_IOVDD
1
7
2
C8660
C8661
1
C8662
1
C8663
1UF
0.1UF
0.1UF
20%
6.3V
10%
16V
10%
16V
100K
2
2
X5R
402
2
X5R-CERM
0201
2
X5R-CERM
0201
0201
1
R8616
100K
1
R8614
100K
R8613
R8603
U8000
1%
1%
1/20W
1/20W
1/20W
1/20W
MF
201
2
MF
201
2
MF
201
2
2
201
201
D
FERR-220-OHM-2A
AG8
PP1V8_GPU_IFPAB_IOVDD
AG9
81
PP1V05_GPU_IFPCD_IOVDD
AF6
81
=PP1V05_GPU_IFPAB_PLLVDD
1
PP1V05_GPU_IFPAB_PLLVDD
2
PP1V05_GPU_IFPCD_IOVDD
81
AG6
81
PP1V05_GPU_IFPEF_IOVDD
AC7
PP1V05_GPU_IFPEF_IOVDD
0603
AC8
81
CRITICAL
ESR = 0.05OHM
1
1
C8665
C8668
1
C8667
1
81
C8669
10UF
2
4.7UF
20%
6.3V
20%
4V
X5R-1
402
PP1V05_GPU_IFPAB_PLLVDD
0.1UF
20%
4V
IFPAB PLLVDD
1UF
10%
16V
2
X5R
2
X5R
402
0201
2
AH8
81
IFPAB_RSET
AJ8
81
X5R-CERM
0201
PP3V3_GPU_IFPX_PLLVDD
AF7
81
IFPC_RSET
AF8
PP3V3_GPU_IFPX_PLLVDD
AG7
IFPD_RSET
AN2
81
81
81
PP3V3_GPU_IFPX_PLLVDD
AB8
IFPEF_RSET
AD6
81
=PP3V3_GPU_VDD33
83 82 81 75 7
81
1
1
R8623
R8624
4.7K
4.7K
1%
86
86
1%
1/20W
MF
R4
OUT
LVDS_EG_DDC_CLK
BI
LVDS_EG_DDC_DATA
R5
1/20W
MF
201
201
2
2
R2
GPU_SSC_SMB_CLK
R3
GPU_SSC_SMB_DAT
C
CRITICAL
82
L8604
330-OHM-1.2A
=PP3V3_GPU_IFPX_PLLVDD
1
82
Signal aliases required by this page:
1
C8610
C8611
10UF
2
1
1UF
20%
10V
IFPX PLLVDD
X5R
C8612
X5R
402
1
C8619
1
C8615
1
C8616
1
C8617
BI
DP_EG_DDC_CLK
R7
DP_EG_DDC_DATA
OUT
R6
DDC MAPPING
--------------------I2CA - & gt; LVDS
1UF
1UF
0.1UF
10%
25V
10%
25V
10%
16V
10%
16V
2
X5R-CERM
603
2
X5R
2
X5R
402
402
2
X5R-CERM
0201
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
2
OUT
89 100
LVDS_EG_A_DATA_N & lt; 0 & gt;
OUT
AN5
LVDS_EG_A_DATA_P & lt; 1 & gt;
OUT
89 100
AM5
LVDS_EG_A_DATA_N & lt; 1 & gt;
OUT
89 100
AJ9
AH9
C8625
1
LVDS_EG_A_DATA_N & lt; 2 & gt;
4.7UF
IFP CD IOVDD
2
C8626
1UF
20%
4V
X5R-1
402
0201
1
C8655
LVDS_EG_B_DATA_P & lt; 0 & gt;
OUT
1UF
0.1UF
20%
6.3V
10%
10%
16V
2
402
16V
2
X5R
0201
2
X5R-CERM
0201
DAC_AVDD
LVDS_EG_B_DATA_N & lt; 0 & gt;
OUT
L8606
2
2
NC_GPU_ROM_CS_L
MAKE_BASE=TRUE
201
83 81
PP1V05_GPU_SP_PLLVDD
PP1V05_GPU_VID_PLLVDD
81
2
MAKE_BASE=TRUE
89 100
AM7
LVDS_EG_B_DATA_P & lt; 1 & gt;
OUT
89 100
AL7
LVDS_EG_B_DATA_N & lt; 1 & gt;
OUT
89 100
AN8
LVDS_EG_B_DATA_P & lt; 2 & gt;
OUT
89 100
AM8
LVDS_EG_B_DATA_N & lt; 2 & gt;
OUT
89 100
AK8
AL8
NC
NC
AG3
OMIT_TABLE
DP_EG_AUX_CH_P
BI
8 81 86 100
AG2
DP_EG_AUX_CH_N
BI
8 81 86 100
AK1
DP_EXTA_ML_C_P & lt; 0 & gt;
OUT
87 100
AJ1
DP_EXTA_ML_C_N & lt; 0 & gt;
OUT
87 100
AJ3
DP_EXTA_ML_C_P & lt; 1 & gt;
OUT
87 100
U8000
NV-GK107
BGA
=PP3V3_GPU_VDD33
AJ2
DP_EXTA_ML_C_N & lt; 1 & gt;
OUT
DP_EXTA_ML_C_P & lt; 2 & gt;
OUT
DP_EXTA_ML_C_N & lt; 2 & gt;
OUT
J8
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
K8
87 100
AH4
(6 OF 10)
83 82 81 75 7
87 100
AH3
87 100
L8
VDD33
M8
GPU_ROM_CS_L
H6
GPU_ROM_SCLK
H4
OUT
82
H5
IN
GPU_ROM_SI
82
GPU_ROM_SO
H7
OUT
AG5
DP_EXTA_ML_C_P & lt; 3 & gt;
OUT
87 100
81
OUT
AG4
DP_EXTA_ML_C_N & lt; 3 & gt;
OUT
87 100
82
DP_TBTSNK0_AUXCH_C_P
AK2
DP_TBTSNK0_AUXCH_C_N
BI
BI
6 33 81 98
PLACE_NEAR=U8000.J1:5MM
6 33 81 98
1
DP_TBTSNK0_ML_C_P & lt; 1 & gt;
AM4
DP_TBTSNK0_ML_C_N & lt; 1 & gt;
OUT
DP_TBTSNK0_ML_C_P & lt; 2 & gt;
OUT
DP_TBTSNK0_ML_C_N & lt; 2 & gt;
OUT
1/20W
R8608
6 33 98
AL4
0.1%
0201
GPU_TESTMODE
6 33 98
MULTI_STRAP_REF0_GND
AK11
6 33 98
AL3
J1
MULTI_STRAP_REF
2
MF
AM3
ROM_CS*
ROM_SCLK
ROM_SI
ROM_SO
R8609
40.2K
AK4
DP_TBTSNK0_ML_C_P & lt; 3 & gt;
AK5
DP_TBTSNK0_ML_C_N & lt; 3 & gt;
OUT
10K
6 33 98
2
1
1/20W
1%
201
MF
PP1V05_GPU_SP_PLLVDD
AE8
PP1V05_GPU_PLLVDD
AD8
83 81
81
OUT
OUT
6 33 98
TESTMODE
SP_PLLVDD
PLLVDD
6 33 98
PP1V05_GPU_VID_PLLVDD
OUT
AD3
DP_TBTSNK1_ML_C_N & lt; 0 & gt;
OUT
AF3
AE3
AD7
81
6 33 98
AG10
DACA_VDD
0201
DP_TBTSNK1_AUXCH_C_P
BI
6 33 81 98
DP_TBTSNK1_AUXCH_C_N
AB4
BI
6 33 81 98
IN
GPU_OSC_27M_XTALIN
H3
H2
OUT
GPU_OSC_27M_XTALOUT
100 82
100 82
PLACE_NEAR=U8000.J4:4MM
AD1
DP_TBTSNK1_ML_C_P & lt; 1 & gt;
OUT
DP_TBTSNK1_ML_C_N & lt; 1 & gt;
OUT
VID_PLLVDD
DP_TBTSNK1_ML_C_P & lt; 2 & gt;
OUT
6 33 98
XTAL_IN
XTAL_OUT
AC3
DP_TBTSNK1_ML_C_N & lt; 2 & gt;
AC4
DP_TBTSNK1_ML_C_P & lt; 3 & gt;
AC5
DP_TBTSNK1_ML_C_N & lt; 3 & gt;
AF2
AE4
AF4
AF5
AD4
AD5
AG1
AF1
OUT
R8611
82
OUT
6 33 98
IN
GPU_MLS_STRAP0
J2
82
IN
GPU_MLS_STRAP1
J7
R8612
10K
1
1%
6 33 98
1/20W
MF
2
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST*
XTAL_SSIN
PLACE_NEAR=U8000.H1:4MM
82
GPU_MLS_STRAP2
J6
IN
82
GPU_MLS_STRAP3
J5
IN
GPU_MLS_STRAP4
J3
10K
6 33 98
OUT
H1
GPU_OSC_27M_SSIN
1
201
1%
1/20W
MF
NC
NC
2
82
201
IN
NC
NC
NC
NC
NC
NC
NC
NC
P6
GPU_GPIO_0
M3
BI
82
GPU_GPIO_1
BI
82
L6
GPU_GPIO_2
BI
82
P5
GPU_GPIO_3
BI
82
P7
GPU_GPIO_4
BI
82
L7
GPU_GPIO_5
BI
82
M7
GPU_GPIO_6
BI
82
N8
GPU_GPIO_7
BI
82
M1
GPU_GPIO_8
BI
82
M2
GPU_GPIO_9
BI
82
L1
GPU_GPIO_10
BI
82
M5
GPU_GPIO_11
BI
82
N3
GPU_GPIO_12
BI
82
M4
GPU_GPIO_13
BI
82
N4
GPU_GPIO_14
BI
82
P2
GPU_GPIO_15
BI
82
R8
GPU_GPIO_16
BI
82
M6
GPU_GPIO_17
BI
82
R1
GPU_GPIO_18
BI
82
P3
GPU_GPIO_19
BI
82
P4
GPU_GPIO_20
BI
82
P1
GPU_GPIO_21
BI
82
C
XTAL_OUTBUFF
6 33 98
AC2
J4
GPU_OSC_27M_XTAL_BUFFOUT_R
6 33 98
AC1
2
DACA_RED
DACA_GREEN
DACA_BLUE
AK9
DACA_HSYNC
DACA_VSYNC
AM9
AL10
AL9
R8600
10K
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
GPU_ROM_CS_L
81
MF
201
6 33 98
X5R-CERM
1
FERR-220-OHM-2A
2
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
THERMDP
THERMDN
AM10
GPU_JTAG_TCK
IN
82
AM11
GPU_JTAG_TDI
IN
82
AP12
GPU_JTAG_TDO
OUT
82
AP11
GPU_JTAG_TMS
IN
82
AN11
GPU_JTAG_TRST_L
IN
82
K3
GPU_TDIODE_P
IN
51 101
GPU_TDIODE_N
OUT
51 101
K4
B
GPU PLL VDD
L8607
MIN_LINE_WIDTH=0.41 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
FERR-220-OHM-2A
=PP1V05_GPU_PEX_PLLVDD
83 7
1
2
PP1V05_GPU_PLLVDD
81
0603
0.1UF
20%
4V
X5R
1%
1/20W
201
2
C8658
10UF
2
1K
89 100
AP5
DP_TBTSNK1_ML_C_P & lt; 0 & gt;
X5R-CERM
1
201
201
R8607
NC
NC
AP6
AD2
X5R-CERM
C8657
1/20W
R8606
1K
1%
1/20W
MF
MF
MF
PLACE_NEAR=U8000.AD6:5MM
1
NC
NC
AB3
0201
1
C8656
1%
2
IFPE_L0
IFPE_L0*
IFPE_L1
IFPE_L1*
IFPE_L2
IFPE_L2*
IFPE_L3
IFPE_L3*
C8628
1/20W
6 33 98
10%
16V
2
X5R-CERM
OUT
OUT
0.1UF
10%
16V
2
X5R
0201
1
C8627
0.1UF
20%
6.3V
2
1K
1/20W
89 100
OUT
I2CB_SCL
I2CB_SDA
1
R8621
R8618
100K
100K
89 100
DP_TBTSNK0_ML_C_N & lt; 0 & gt;
0201
1
OUT
AM2
PP1V05_GPU_IFPCD_IOVDD
1
1
R8617
MF
AK6
AH6
PLACE_NEAR=U8000.AN2:5MM
1
1%
LVDS_EG_A_DATA_P & lt; 2 & gt;
81
PLACE_NEAR=U8000.AF8:5MM
33 6
98 81
1
D
BOM options provided by this page:
IFPEF_RSET
81
1%
AL6
AJ6
IFPD_RSET
81
89 100
81
1
IFPC_RSET
6 33 98
I2CC - & gt; SSC CLK GEN
0603
1
LVDS_EG_A_DATA_P & lt; 0 & gt;
AN3
IFPE_AUX_I2CY_SCL
IFPE_AUX_I2CY_SDA*
CRITICAL
ESR = 0.05OHM
DP_TBTSNK1_AUXCH_C_P
98 81 33 6
DP_TBTSNK1_AUXCH_C_N
AP3
I2CB - & gt; IFPC
0.1UF
10%
6.3V
FERR-220-OHM-2A
=PP1V05_GPU_IFPEF_IOVDD
89 100
IFPF_L0
IFPF_L0*
IFPF_L1
IFPF_L1*
IFPF_L2
IFPF_L2*
IFPF_L3
IFPF_L3*
4.7UF
1
OUT
DP_TBTSNK0_ML_C_P & lt; 0 & gt;
L8605
=PP1V05_GPU_IFPCD_IOVDD
LVDS_EG_A_CLK_N
IFPF_AUX_I2CZ_SCL
IFPF_AUX_I2CZ_SDA*
C8618
20%
10V
B
AN6
AM1
0201
10UF
2
OUT
89 100
IFPD_L0
IFPD_L0*
IFPD_L1
IFPD_L1*
IFPD_L2
IFPD_L2*
IFPD_L3
IFPD_L3*
X5R-CERM
PLACE BELOW GPU NEAR DISPLAY SECTION
603
LVDS_EG_A_CLK_P
AK3
10%
16V
2
86
X5R
(NONE)
PD FOR RSET
PD FOR AUX CHANNELS (FOR NVIDIA)
AM6
IFPD_AUX_I2CX_SCL
IFPD_AUX_I2CX_SDA*
86
2
GPU_SMB_DAT
T3
IFPC_AUX_I2CW_SCL
IFPC_AUX_I2CW_SDA*
I2CC_SCL
IFPC_L0
I2CC_SDA
IFPC_L0*
IFPC_L1
IFPC_L1*
IFPC_L2
I2CS_SCL
IFPC_L2*
I2CS_SDA
IFPC_L3
IFPC_L3*
0.1UF
10%
25V
2
603
1
T4
(5 OF 10)
IFPA_IOVDD
IFPA_TXC
IFPB_IOVDD
IFPA_TXC*
IFPC_IOVDD
IFPA_TXD0
IFPD_IOVDD
IFPA_TXD0*
IFPE_IOVDD
IFPA_TXD1
IFPF_IOVDD
IFPA_TXD1*
IFPAB_PLLVDD
IFPA_TXD2
IFPAB_RSET
IFPA_TXD2*
IFPA_TXD3
IFPC_PLLVDD
IFPA_TXD3*
IFPC_RSET
IFPB_TXC
IFPD_PLLVDD
IFPB_TXC*
IFPD_RSET
IFPB_TXD4
IFPEF_PLLVDD
IFPB_TXD4*
IFPEF_RSET
IFPB_TXD5
IFPB_TXD5*
IFPB_TXD6
I2CA_SCL
IFPB_TXD6*
I2CA_SDA
IFPB_TXD7
IFPB_TXD7*
81
1
C8613
BI
GPU_SMB_CLK
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
0603
1
OUT
PP3V3_GPU_IFPX_PLLVDD
2
- =PP1V05_GPU_IFPAB_PLLVDD
- =PP1V05_GPU_DPLL
- =PP3V3_GPU_IFPX_PLLVDD
BGA
PP1V8_GPU_IFPAB_IOVDD
VOLTAGE=1.05V
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 mm
- =PP1V05_GPU_IFPEF_IOVDD
MF
NV-GK107
81
L8609
- =PP1V05_GPU_IFPCD_IOVDD
- =PP3V3_GPU_VDD33
1%
1%
1/20W
2
- =PP1V8_GPU_IFPAB_IOVDD
- =PP1V8_GPU_DPLL
1K
100K
1%
MF
20%
4V
X5R-1
402
X5R
1
R8615
4.7UF
20%
4V
2
Page Notes
81
1
1
OMIT_TABLE
CRITICAL
C8664
10UF
IFPAB IOVDD
IFPAB_RSET
DP_EG_AUX_CH_N
100 86 81 8
PP1V8_GPU_IFPAB_IOVDD
81
1
1
Power aliases required by this page:
0603
1
DP_EG_AUX_CH_P
PLACE_NEAR=U8000.AJ8:5MM
CRITICAL
1
2
6 100 86 81 8
33 81 98
1%
1/20W
MF
201
NC
NC
AP9
AP8
DACA_VREF
DACA_RSET
AN9
CRITICAL
ESR = 0.05OHM
NC
NC
NC
1
C8651
1
C8652
1
C8653
22UF
2
NC
NC
1UF
20%
6.3V
10%
16V
1
C8654
0.1UF
20%
6.3V
X5R-CERM2
0603
2
X5R
2
0201
X5R-CERM
0.1UF
2
0201
10%
16V
X5R-CERM
0201
GPU 3V3 VDD
=PP3V3_GPU_VDD33
83 82 81 75 7
PP1V05_GPU_IFPEF_IOVDD
81
0603
1
CRITICAL
ESR = 0.05OHM
1
C8629
1
C8630
1
C8631
1
2
A
0.1UF
20%
6.3V
10%
16V
CEC
0.1UF
20%
4V
IFP EF IOVDD
1UF
L3
NC
10%
16V
X5R
402
2
X5R
2
0201
X5R-CERM
2
0201
C8640
1
10UF
C8632
10UF
2
20%
10V
X5R
C8641
1
1UF
2
603
10%
25V
X5R
C8642
1
1UF
2
402
10%
25V
X5R
C8643
1
0.1UF
2
402
10%
16V
X5R-CERM
0201
C8644
0.1UF
2
10%
16V
X5R-CERM
0201
X5R-CERM
0201
SYNC_MASTER=J31_SREE
SYNC_DATE=10/25/2011
PAGE TITLE
KEPLER LVDS/DP/GPIO
DRAWING NUMBER
1
1
C8633
1
4.7UF
2
8
7
20%
4V
X5R-1
402
C8635
1
C8646
1
C8649
1
20%
6.3V
2
X5R
Apple Inc.
C8650
4.7UF
1UF
2
C8645
4.7UF
0.1UF
0.1UF
20%
6.3V
X5R-CERM1
402
20%
6.3V
X5R-CERM1
402
10%
16V
10%
16V
2
2
X5R-CERM
0201
0201
2
X5R-CERM
0201
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
6
5
4
051-9585
3
2
SIZE
D
REVISION
3.0.0
BRANCH
PAGE
86 OF 132
SHEET
81 OF 105
1
A
8
7
6
5
4
3
2
1
JTAG signals
GPIOs
Native Func
81
81
GPU_GPIO_1
81
GPU_GPIO_2
81
GP
GPU_GPIO_0
GPU_GPIO_3
TP_GPU_JTAG_TCK
Native Func
GFXIMVP_VID & lt; 4 & gt;
84
81
84
81
GPU_GPIO_15
84
81
GPU_GPIO_16
82 89
81
GPIOs
GPU_GPIO_17
DP_CA_DET_EG
MAKE_BASE=TRUE
GP
GP
GP
81
GPU_GPIO_4
GPU_GPIO_5
82 89
81
GPU_GPIO_18
84
81
GP
GPU_GPIO_19
D
GPU_GPIO_6
84
81
GP
GPU_GPIO_20
81
GPU_GPIO_8
81
MAKE_BASE=TRUE
GP
GP
GPU_GPIO_9
SMC_GFX_THROTTLE_R_L
MAKE_BASE=TRUE
75
GPU_GPIO_11
GPU_GPIO_12
81
GPU_GPIO_13
1
2
EG_CLKREQ_IN_L
5%
1/20W
MF
201
OUT
8 89
77
GFXIMVP_VID & lt; 0 & gt;
STUFF
STUFF
STUFF
STUFF
STUFF
84
MAKE_BASE=TRUE
NC_GPU_GPIO_12
GP
0
R8795
PEX_CLKREQ_L_R
CURRENTLY STUFFED FOR GK107-GTX (R8705)
GPU_ALT_VREF
MAKE_BASE=TRUE
81
NO_TEST=TRUE
STRAP NOTES:
GP
81
201
82
GP
GPU_GPIO_10
NO_TEST=TRUE
82
MAKE_BASE=TRUE
81
2
NC_GPU_GPIO_21_RSVD
NO_TEST=TRUE
SMC_GFX_OVERTEMP_R_L
MAKE_BASE=TRUE
81
1/20W
MF
GP
GPU_GPIO_21
D
1%
NC_GPU_GPIO_20_RSVD
MAKE_BASE=TRUE
NC_GPU_GPIO_7
R8755
10K
82
MAKE_BASE=TRUE
GFXIMVP_VID & lt; 2 & gt;
GP
GPU_GPIO_7
1
82
IFPE
DP_TBTSNK1_HPD_EG
MAKE_BASE=TRUE
81
GPU_JTAG_TRST_L
MAKE_BASE=TRUE
GP
MAKE_BASE=TRUE
81
81
86
IFPD
DP_TBTSNK0_HPD_EG
MAKE_BASE=TRUE
GFXIMVP_VID & lt; 1 & gt;
GP
78 82
IFPC
DP_EG_HPD
MAKE_BASE=TRUE
EG_BKLT_EN
GP
81
MAKE_BASE=TRUE
MAKE_BASE=TRUE
GP
MAKE_BASE=TRUE
81
81
GPU_JTAG_TMS
TP_GPU_JTAG_TMS
FBVDD_ALTVO
MAKE_BASE=TRUE
EG_LCD_PWR_EN
GP
81
GPU_JTAG_TDO
MAKE_BASE=TRUE
MAKE_BASE=TRUE
GFXIMVP_PSI_R_L
GP
TP_GPU_JTAG_TDO
NC_GPU_GPIO_15
MAKE_BASE=TRUE
GP
81
GPU_JTAG_TDI
MAKE_BASE=TRUE
89
MAKE_BASE=TRUE
GFXIMVP_VID & lt; 3 & gt;
GPU_JTAG_TCK
MAKE_BASE=TRUE
TP_GPU_JTAG_TDI
GP
GPU_GPIO_14
MAKE_BASE=TRUE
GP
GFXIMVP_VID & lt; 5 & gt;
84
MAKE_BASE=TRUE
R8711
R8711
R8711
R8711
R8711
=
=
=
=
=
5KOHM FOR HYNIX 1GB - M die
10KOHM FOR SAMSUNG 1GB
15KOHM FOR HYNIX 512MB
20KOHM FOR SAMSUNG 512MB
24.9KOHM FOR HYNIX 1GB - A die
GP
PART NUMBER
QTY
DESCRIPTION
REFERENCE DES
CRITICAL
BOM OPTION
CONFIG STRAPS - MLPS
Strap values
----0x01
118S0019
RES, 10.2KOHM, 0201
R8711
CRITICAL
FB_1G_SAMSUNG
118S0414
1
RES, 5.1KOHM, 0201
R8711
CRITICAL
FB_1G_HYNIX_M_DIE
0x00
118S0105
1
RES,15KOHM, 0201
R8711
CRITICAL
FB_512_HYNIX
0x02
118S0175
1
RES, 20KOHM, 0201
R8711
CRITICAL
FB_512_SAMSUNG
0x03
118S0230
=PP3V3_GPU_VDD33
=PP3V3_GPU_VDD33
81 75 7
83 82
1
1
RES, 24.9KOHM, 0201
R8711
CRITICAL
FB_1G_HYNIX_A_DIE
0x04
83 82 81 75 7
NOSTUFF
1
1
R8700
R8708
45.3K
3.24K
1%
1%
1/20W
1/20W
MF
MF
201
2
81
OUT
C
201
2
1
1
R8701
C
=PP3V3_GPU_VDD33
R8709
5.62K
1%
1/20W
1/20W
MF
GPU overtemp masking
83 82 81 75 7
45.3K
1%
MF
201
2
81
OUT
GPU_MLS_STRAP4
GPU_MLS_STRAP0
201
2
R8752
NOSTUFF
=PP3V3_GPU_VDD33
1
83 82 81 75 7
100K
46 45 7
=PP3V3_S5_SMC
5%
1/20W
MF
201
=PP3V3_GPU_VDD33
U8701
2
5
81 75 7
83 82
5
83 82 81 75 7
1
SMC_GFX_OVERTEMP_Q
NOSTUFF
1
R8702
3.24K
4
Q8701
R8710
SSM3K15FV
3.24K
1%
2
D
82
45
46
OUT
82
2
SMC_GFX_OVERTEMP
3
1/20W
MF
=PP3V3_GPU_VDD33
MF
201
83 82 81 75 7
201
2
81
OUT
OUT
81
R8796
1
G
1
10K
GPU_ROM_SI
GPU_MLS_STRAP1
S
2
U8701
5%
5
1/20W
1
DP_TBTSNK0_HPD_EG
A 34 Y
3
SOD-VESM-HF
1%
1/20W
2
SOT23-5-LF
NOSTUFF
1
33
86
MC74VHC1G08
1
DP_TBTSNK0_HPD
74LVC2G34
SOT891
6
U8702
=PP3V3_GPU_VDD33
1
R8703
35.7K
MF
R8711
201
2
33
86
25.5K
1%
SOT891
4
DP_TBTSNK1_HPD_EG
82
GPU XTAL 27 MHz
1/20W
MF
74LVC2G34
A 34 Y
1%
1/20W
3
DP_TBTSNK1_HPD
MF
201
2
GPU_OSC_27M_XTALIN
82
201
2
OUT
R8750
CRITICAL
B
GPU_RESET_L
IN
SM-2.5X2.0MM
1
83 82 81 75 7
15.4K
1
R8712
1%
1/20W
1/20W
MF
MF
201
2
GPU internal Temp isolation
81
OUT
OUT
R8705
83 82 81 75 7
Q8702
10K
5%
1/20W
MF
NP0-C0G
201
SOT563
R8797
MF
2
BI
GPU_SMB_DAT
D
S
81
201
5%
GPU_SMB_DAT_R
BI
6
201
1
10K
48
1/20W
MF
NOSTUFF
201
NO STUFF
2
R8780
82
=PP3V3_GPU_VDD33
=PP3V3_GPU_VDD33
81 75 7
83 82
MF
2
R8799
0
1
2
SMC_GFX_THROTTLE_L
1/20W
MF
MF
2
1/20W
MF
OUT
D
GPU_SMB_CLK
GPU_SMB_CLK_R
IN
3
81
S
81
48
R8792
1
10K
GPU_ROM_SCLK
R8793
1
10K
R8794
1
R8790
10K
R8715
1
0
5%
5%
1/20W
DRAWING NUMBER
1/20W
MF
MF
MF
201
201
Apple Inc.
MF
201
2
2
2
2
5%
1/20W
MF
NOTICE OF PROPRIETARY PROPERTY:
201
SIZE
D
3.0.0
BRANCH
NOSTUFF
MF
2
051-9585
REVISION
R
2
1%
1/20W
MF
SYNC_DATE=11/16/2011
KEPLER GPIOS,CLK & STRAPS
1
5%
1/20W
201
R8781
35.7K
1/20W
78 82
10K
5%
1/20W
1%
82 89
OUT
PAGE TITLE
NO STUFF
OUT
5.62K
OUT
45
82 89
SYNC_MASTER=J31_SREE
201
201
81
1
OUT
FBVDD_ALTVO
SOT563
4
2
5%
BI
EG_BKLT_EN
G
1/20W
1
45 46 82
201
SSM6N37FEAPE
1%
OUT
201
MF
10K
R8754
5.1K
1%
201
MF
1/20W
Q8702
R8714
5
34.8K
R8707
SMC_GFX_OVERTEMP
1/20W
5%
201
EG_LCD_PWR_EN
=PP3V3_GPU_VDD33
GPU_MLS_STRAP3
1
SMC_GFX_THROTTLE_R_L
5%
1/20W
83 82 81 75 7
OUT
0
NOSTUFF
1
201
R8798
2
5%
83 82 81 75 7
R8706
SMC_GFX_OVERTEMP_R_L
82
0
1
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
201
NOSTUFF
NOSTUFF
8
5%
25V
=PP3V3_GPU_VDD33
201
1
2
83 82 81 75 7
1/20W
MF
2
1%
1/20W
2
C8701
18PF
2
NP0-C0G
SSM6N37FEAPE
10K
1
R8713
1%
1
1
5%
25V
201
G
1
30K
2
4
=PP3V3_GPU_VDD33
81
GPU_ROM_SO
R8753
A
B
MF
2
GPU_MLS_STRAP2
1
GPU_OSC_27M_XTALOUT
201
2
1
C8700
18PF
10.2K
1%
2
1/20W
PLACE_NEAR=Y8700.3:4MM
NC
NC
1
R8704
5%
3
2
2
1
201
27MHZ-15PPM-18PF
NOSTUFF
0
1
100 GPU_OSC_27M_XTALOUT_R
Y8700
TBT HPD isolation
=PP3V3_GPU_VDD33
81 75 7
83 82
81
100
SMC_GFX_OVERTEMP_R_L
OMIT_TABLE
=PP3V3_GPU_VDD33
81
100
IN
2
7
6
5
4
3
2
PAGE
87 OF 132
SHEET
82 OF 105
1
A
8
7
6
5
4
3
2
1
Page Notes
Power aliases required by this page:
GPU SP PLLVDD
L8804
OMIT_TABLE
FERR-220-OHM-2A
U8000
=PP1V05_GPU_PEX_IOVDD
BGA
P8
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
D
76 7
(2 OF 10)
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
AC6
AJ28
AJ4
AJ5
AL11
C15
D19
D20
D23
D26
H31
T8
V32
7 77 83
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=1.05V
2
=PP1V05_GPU_PEX_PLLVDD
PP1V05_GPU_SP_PLLVDD
81
0603
CRITICAL
ESR = 0.05OHM
AG19
1
C8830
1
C8831
1
C8832
1
C8833
1
C8834
1
C8835
1
C8836
22UF
AG21
AG22
AG24
2
XW8801
SM
1
AH21
4.7UF
1UF
1UF
0.1UF
0.1UF
20%
6.3V
X5R-CERM1
402
20%
6.3V
X5R
0201
20%
6.3V
X5R
0201
10%
16V
X5R-CERM
0201
10%
16V
X5R-CERM
0201
10%
16V
X5R-CERM
0201
1
0.1UF
20%
6.3V
X5R-CERM2
0603
2
2
2
2
2
2
C8837
0.1UF
2
10%
16V
X5R-CERM
0201
Signal aliases required by this page:
(NONE)
2
D
BOM options provided by this page:
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=0V
AH25
=PP1V05_GPU_PEX_IOVDD
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
=PPVCORE_GPU
1
83 81 7
NV-GK107
- =PP3V3_GPU_VDD33
- =PP1V05_GPU_PEX_IOVDD
- =PP1V05_GPU_PEX_PLLVDD
GND_GPU_SP_PLLVDD
(NONE)
7 77 83
AG13
U8000
U8000
AG15
NV-GK107
NV-GK107
AG16
BGA
BGA
(9 OF 10)
(8 OF 10)
AG18
AG11
AG25
A2
C7
AK7
OMIT_TABLE
D2
D31
A33
GND
N7
OMIT_TABLE
P13
AL12
AH15
AL14
GND
P15
P18
P20
E25
P22
E5
R12
E7
R14
F28
R16
AL15
AH26
AA15
P17
E22
AA13
D33
E10
AH18
AL17
AH27
AA17
AL18
AA18
AL2
AA20
AL20
AJ27
AK27
AL27
AA22
AL21
AM28
AB12
AL23
AB14
AL24
C8828
1
4.7UF
C
2
C16
GND_OPT
GND_OPT
W32
OUT
10%
6.3V
X5R
201
2
2
2
L5
GPUVCORE_SENSE_N
PEX_PLL_HVDD
1
GPU_BUFRSTN
1
1
R8800
2
10K
100
2
1%
1/20W
MF
201
1
C8823
4.7UF
R8811
5%
1/20W
MF
2 201
1
C8822
4.7UF
20%
6.3V
X5R-CERM1
402
1UF
20%
6.3V
X5R-CERM1
402
2
1
C8824
2
2
V23
M20
W13
M22
W15
W17
W18
W20
W22
AN7
AP2
AH10
AP33
AH13
B1
AH16
B10
AH19
B22
AH2
B25
AH22
B28
AH24
XW8804
V21
M18
AN4
AE7
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=0V
V19
AN34
AE33
2
V16
AN30
AE32
SM
1
GND_GPU_PEX_PLL_HVDD
AE30
XW8803
V14
M15
AN25
AE5
C8825
10%
6.3V
X5R
201
AN22
AE28
7 75 81 82
V12
K7
=PP3V3_GPU_VDD33
2
AN19
AE2
5%
1/16W
MF-LF
402
0.1UF
20%
6.3V
X5R
0201
0
U23
K5
M17
1
U21
K33
M13
PP3V3_GPU_PEX_PLL_HVDD
BUFRST*
U19
K32
AN16
AC22
R8802
75
L2
AN13
AC20
AH12
U16
K30
AN10
AC18
GND_SENSE
AN1
AC17
MIN_LINE_WIDTH=0.8 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
U14
AM25
AC15
AG26
U12
AM22
AC13
B31
AH28
B34
AH29
B4
N2
1
2
OUT
78 101
PLACE_NEAR=C8803.1:2MM
B
GPUDEC:NORMAL
1
C8803
22UF
2
GPUDEC:EXP
GPUDEC:NORMAL
1
C8804
1
2
20%
6.3V
X5R-CERM2
0603
C8805
4.7UF
22UF
20%
6.3V
X5R-CERM2
0603
1
2
C8893
GPUDEC:EXP
1
22UF
20%
6.3V
X5R-CERM1
402
2
C8894
GPUDEC:EXP
1
22UF
20%
4V
X5R
402
C8890
GPUDEC:NORMAL
1
22UF
C8891
1
22UF
C8800
GPUDEC:NORMAL
1
20%
4V
X5R
402
2
20%
4V
X5R
402
2
22UF
C8801
20%
4V
X5R
402
C8802
Y23
AJ7
C25
AK10
C28
N5
20%
6.3V
X5R-CERM2
0603
2
20%
6.3V
X5R-CERM2
0603
2
20%
6.3V
X5R-CERM1
402
C8812
1
C8813
1
C8814
B
C22
4.7UF
22UF
2
1
2
Y21
C19
AH7
1
Y19
C13
AH5
GPUDEC:EXP
C10
AH33
=PP1V05_GPU_PEX_IOVDD
Y16
B7
AH32
83 77 7
Y14
N33
AH30
EDP = 2000 MA
Y12
N32
P1V05_GPU_PEX_IOVDD_SNS_P
W28
N23
N30
SM
N21
N28
SIGNAL_MODEL=EMPTY
C
AM19
AB7
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=0V
T7
G7
AM16
AB5
GND_GPU_PEX_PLLVDD
VDD_SENSE
T5
AM13
AB32
2
T32
G33
AB30
XW8802
T28
G32
AL5
0.1UF
20%
6.3V
X5R
0201
1
PEX_PLLVDD
SIGNAL_MODEL=EMPTY
1UF
20%
6.3V
X5R-CERM1
402
AL33
AB28
SM
GPUVCORE_SENSE_P
L4
OUT
4.7UF
20%
6.3V
X5R-CERM1
402
T22
G30
G5
C8829
T20
N19
1
T2
G3
N16
C8827
AL32
AB23
5%
1/10W
MF-LF
603
T18
G25
N14
1
AL30
AB21
7 81 83
T17
K28
C8826
1
=PP1V05_GPU_PEX_PLLVDD
AL28
AB2
2
T15
G2
G22
0
1
5%
1/20W
MF
2 201
T13
G19
G28
PP1V05_GPU_PEX_PLLVDD
100
SIGNAL_MODEL=EMPTY
AL26
AB19
R8803
R23
K2
R8810
R21
G16
AB16
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
R19
G13
N12
1
F7
G10
AN28
AH11
SIGNAL_MODEL=EMPTY
XW8800
SM
1
2
P1V05_GPU_PEX_IOVDD_SNS_N
OUT
78 101
PLACE_NEAR=C8803.2:2MM
PLACE XW8800 & XW8804 CLOSE TO C8803
1
C8815
1
C8816
1
C8817
1
C8818
10UF
2
1UF
0.1UF
100PF
10UF
1UF
20%
6.3V
X5R
0201
10%
6.3V
X5R
201
5%
25V
CERM
201
20%
4V
X5R
402
20%
6.3V
X5R
0201
1
0.1UF
20%
4V
X5R
402
10%
6.3V
X5R
201
2
2
2
PEX IOVDD & PEX IOVDDQ
2
2
2
C8821
100PF
2
5%
25V
CERM
201
A
SYNC_MASTER=J31_SREE
SYNC_DATE=10/31/2011
PAGE TITLE
1
1
C8809
1
C8810
1
C8811
1
C8819
10UF
2
1UF
0.1UF
20%
6.3V
X5R
0201
10%
6.3V
X5R
201
5%
25V
CERM
201
2
2
2
C8806
1
C8807
1
2
1
C8808
10UF
100PF
20%
4V
X5R
402
1UF
0.1UF
20%
4V
X5R
402
20%
6.3V
X5R
0201
10%
6.3V
X5R
201
2
2
KEPLER PEX PWR/GNDS
C8820
DRAWING NUMBER
100PF
2
5%
25V
CERM
201
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
051-9585
3
2
SIZE
D
REVISION
3.0.0
BRANCH
PAGE
88 OF 132
SHEET
83 OF 105
1
A
8
7
6
5
4
3
2
=PPVIN_S0_GFXIMVP
84 7
CRITICAL
C8928
C8927
1
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
DIDT=TRUE
=PP5V_S3_GFXIMVP
1
1
C8930
1
PLACE_NEAR=U8900.17:1MM
2
PLACE_NEAR=U8900.16:1MM
1
10%
10V
CERM
402
2
2
R8930
5%
1/10W
MF-LF
603
4
G
17
25
16
5
353S3679
BOOT2
30
2
2
C8917
1
330PF
1
PGOOD
UGATE2
29
4
VR_TT*
PHASE2
28
C8919
84 82
84 82
IN
84
C8918
R8913 1
2
10%
16V
X7R-CERM
0201
84 82
5%
50V
NP0-C0G-CERM
0201
GFXIMVP_PSI_L
GFXIMVP_DPSLP_EN
IN
84 82
2
IN
84 82
22PF
8.06K
GFXIMVP_VID & lt; 0 & gt;
GFXIMVP_VID & lt; 1 & gt;
GFXIMVP_VID & lt; 2 & gt;
GFXIMVP_VID & lt; 3 & gt;
GFXIMVP_VID & lt; 4 & gt;
GFXIMVP_VID & lt; 5 & gt;
GFXIMVP_VID & lt; 6 & gt;
84
2
1
5
6
SWITCH_NODE=TRUE
IN
1000PF
IN
84 82
IN
26
27
37
ISEN2
10
GFXIMVP_ISEN2
2
PSI*
BOOT1
19
UGATE1
20
10%
10V
CERM
402
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=0V
1
VOLTAGE=1.05V
2
92
IN
101 83
D
21
101
Q8961
SIGNAL_MODEL=EMPTY
1
G
R8961
GFXIMVP_PHASE1
7
COMP
LGATE1B
24
9
FB2
VSSP1
22
GFXIMVP_VSSP1
8
FB
ISEN1
11
GFXIMVP_ISEN1
ISUM+
GFXIMVP_ISUMP
1%
1/20W
MF
201
VSEN
C8915
1000PF
10%
16V
X7R-CERM
0201
C8941
5600PF
NC
C8914
18
2
2
2
1%
1/20W
MF
201
GFXIMVP_ISUMN
GFXIMVP_ISUMP
XW8931
IMON
SIGNAL_MODEL=EMPTY
1
1
10%
16V
X7R-CERM
0201
1%
1/20W
MF
201
C8913
2
0.1UF
2
1
1.24K
2
2
10%
10V
CERM
201
1
2
20%
6.3V
X5R
0201
GFXIMVP_ISNS2_N
GFXIMVP_ISUMN
84 101
84
B
NOSTUFF
XW8900
SM
0.22UF
2
C8910
5600PF
GFXIMVP_ISUMN_R
R8910
10K
10%
10V
CERM
201
14
84
C8966
SIGNAL_MODEL=EMPTY
1
R8962 1
1
ISUM-
84
SIGNAL_MODEL=EMPTY
SM
2
THRM
PAD
R8912
1000PF
2
2
3
5
6
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=0V
RTN
SIGNAL_MODEL=EMPTY
1
1.00
10K
15
SIGNAL_MODEL=EMPTY
1
R8964
1K
1%
1/20W
MF
201
23
OUT GFXIMVP6_IMON
SIGNAL_MODEL=EMPTY
R8963
10K
GFXIMVP_LGATE1
GATE_NODE=TRUE
GFXIMVP_ISNS1_N
SIGNAL_MODEL=EMPTY 1 SIGNAL_MODEL=EMPTY
1
1%
1/20W
MF
201
DIRECTFET_S3C
LGATE1A
13
1%
1/20W
MF
201
4
101 84
CRITICAL
649135PBF
4
GFXIMVP_ISNS1_P
VW
GPUVCORE_SENSE_N
NOSTUFF
2
PHASE1
VR_ON
84
49
2
3
6
12
R8917
1%
1W
MF
0612
PPVCORE_S0_GFX_PH1 1
PIMB063T-SM
5%
1/10W
MF-LF
603
CKPLUS_WAIVE=PdifPr_badTerm
GPUVCORE_SENSE_P
IN
101 83
GFXIMVP_FB_GND_R
1
DPRSLPVR
41
10%
10V
X7R
201
49.9
2
2
GFXIMVP_FB2
GFXIMVP_FB
C8940
NOSTUFF
B
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.05V
0.2UH-41A-2.4MOHM
R8960
PLACE_NEAR=Q8961.3:1mm
3300PF
2
2
38
R8999
0.00075
L8960
GFXIMVP_COMP
SIGNAL_MODEL=EMPTY
1
=GPUVCORE_EN
84 101
C
GFXIMVP_VW
GFXIMVP_FB_SNS_R
1
301
1
IN
2
20%
6.3V
X5R
0201
GFXIMVP_ISNS1_N
S
2
SIGNAL_MODEL=EMPTY
1%
1/20W
MF
201
1
2
7 84
1
PPVCORE_S0_GFX_PH1_L
SWITCH_NODE=TRUE
49.9
84
0.22UF
CRITICAL
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
GATE_NODE=TRUE
39
84
0
2
R8916
1%
1/20W
MF
201
DIRECTFET-SA
0.22UF
2
1
270UF
IRF6802SDTRPBF
1
GFXIMVP_UGATE1
36
C8964
20%
2 2V
TANT
CASE-B2-SM
CRITICAL
GFXIMVP_BOOT1
35
2
20%
2V
TANT
CASE-B2-SM
Q8930
1 G
C8965
GFXIMVP_VSSP2
34
2
S
GFXIMVP_LGATE2
VSSP2
33
2
GFXIMVP_BOOT1_R
LGATE2
32
270UF
CRITICAL
D
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
DIDT=TRUE
CLK_EN*
VID0
VID1
VID2
VID3
VID4
VID5
VID6
31
1
C8963
1.00
3
5
6
=PPVIN_S0_GFXIMVP
GATE_NODE=TRUE
1
20%
2 2V
TANT
CASE-B2-SM
10K
1%
1/20W
MF
201
GFXIMVP_PHASE2
84
NOSTUFF
1%
1/20W
MF
201
1
270UF
20%
2 2V
TANT
CASE-B2-SM
CRITICAL
C8931
R8932 1
GFXIMVP_UGATE2
GFXIMVP_VR_TT_L
40
C8962
CRITICAL
GFXIMVP_BOOT2
GPUVCORE_PGOOD
R8914
5.11K
10%
16V
X7R-CERM
0201
GFXIMVP_COMP_R
1%
1/20W
MF
201
2
CRITICAL
1
C8961
270UF
R8934
1K
1%
1/20W
MF
201
GFXIMVP_ISUMN
GFXIMVP_ISUMP
4
1
560PF
R8915
R8933
10K
1%
1/20W
MF
201
1
2
8
7
1
GFXIMVP_ISNS2_N
101 84
1
GATE_NODE=TRUE
OUT
2
SIGNAL_MODEL=EMPTY
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
DIDT=TRUE
NTC
2
=PPVCORE_S0_GFX_REG
CRITICAL
SIGNAL_MODEL=EMPTY 1 SIGNAL_MODEL=EMPTY
1
R8931
DIRECTFET_S3C
S
RBIAS
GFXIMVP_NTC
84
1%
1/20W
MF
201
Q8931
SIGNAL_MODEL=EMPTY
1
Line Width & DIDT
on all DIDT nets
TQFN
3
3
GFXIMVP_ISNS2_P
ISL62882C
92
10%
50V
X7R-CERM
0201
101
SIGNAL_MODEL=EMPTY
2
U8900
GFXIMVP_RBIAS
2
1
4
PIMB063T-SM
649135PBF
10%
25V
X7R
0402
VDD VCCP VIN
2
20%
16V
TANT
SM
7
2
SM
C
C8916
PPVCORE_S0_GFX_PH2
2
XW8930
1%
1/20W
MF
201
10%
25V
X5R
402
Need to confirm
25A max per phase
1%
1W
MF
0612
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.05V
CRITICAL
D
PLACE_NEAR=Q8931.3:1mm
30.1K
15UF
10%
25V
X5R
402
1
147K
R8918
1
C8925
R8998
1
R8940
1
1
1UF
20%
16V 2
POLY-TANT
CASE-D2E-SM
0.00075
L8930
NCNC
(GND_GFXIMVP_AGND)
1%
1/20W
MF
201
C8924
1
1UF
D
CRITICAL
0.2UH-41A-2.4MOHM
0.22UF
2
20%
16V 2
POLY-TANT
CASE-D2E-SM
CRITICAL
C8923
1
68UF
IRF6802SDTRPBF
2
C8900
1
1UF
1
C8922
DIRECTFET-SA
0
10%
25V
X5R
402
20%
16V 2
POLY-TANT
CASE-D2E-SM
S
1
0.22UF
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=12.8V
PPVIN_S0_GFXIMVP_R
C8901
CRITICAL
1
68UF
CRITICAL
5%
1/20W
MF
201
PP5V_S0_GFXIMVP_VDD
2
5%
1/20W
MF
201
2
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=5V
R8901
1
2
C8921
68UF
20%
16V 2
POLY-TANT
CASE-D2E-SM
2
CRITICAL
1
C8920
0
1UF
10%
25V
X5R
402
GFXIMVP_BOOT2_R
2
CRITICAL
1
68UF
Q8930
D
2 G
3
C8902
R8900
C8926
CRITICAL
1
2
8
7
D
1
PLACE_NEAR=U8900.25:1MM
10%
50V
X7R-CERM
0402
1
0.001UF
10%
50V
X7R-CERM
0402
7
8
0.001UF
7
1
C8912
PLACE_NEAR=U8900.41:1mm
1%
1/20W
MF
201
1
0.1UF
1
10%
6.3V
X5R
201
10%
6.3V
X5R
201
NOSTUFF
1
R8911
2
GFXIMVP_ISUMP_C
1
1.15K
C8911
0.1UF
2
2
2
1%
1/20W
MF
201
10%
6.3V
X5R
201
GND_GFXIMVP_AGND
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=0V
GPU VCORE VID STRAPS
84 7
=PP3V3_S0_GFX3V3BIAS
R8971 AND R8974 CANNOT BE STUFFED AT THE SAME TIME
DEFAULT = 0.9 V
Stuff option for GPIO control
NOSTUFF
R8943
NOSTUFF
1
R8944
1
NOSTUFF
R8945
1
NOSTUFF
R8946
NOSTUFF
1
R8947
1
R8948
1
R8949
10K
10K
10K
10K
10K
10K
1%
1/20W
MF
201
1%
1/20W
MF
201
1%
1/20W
MF
201
1%
1/20W
MF
201
1%
1/20W
MF
201
1%
1/20W
MF
201
1%
1/20W
MF
201
R8981 = PSI Control
R8982 = VID6 control (old connection)
R8982 = DPSLP Control
1
10K
2
2
2
2
2
2
84 82
84 82
A
84 82
84 82
84 82
84
=PP3V3_S0_GFX3V3BIAS
NOSTUFF
1
GFXIMVP_VID & lt; 0 & gt;
GFXIMVP_VID & lt; 1 & gt;
GFXIMVP_VID & lt; 2 & gt;
GFXIMVP_VID & lt; 3 & gt;
GFXIMVP_VID & lt; 4 & gt;
GFXIMVP_VID & lt; 5 & gt;
GFXIMVP_VID & lt; 6 & gt;
0
2
GFXIMVP_PSI_L
84
2
5%
1/20W
MF
201
84
NOSTUFF
84
R8982
82
NOSTUFF
R8950 1
R8951 1
R8952 1
R8953 1
R8954 1
10K
10K
10K
10K
1%
1/20W
MF
201
1%
1/20W
MF
201
1%
1/20W
MF
201
1%
1/20W
MF
201
1%
1/20W
MF
201
1%
1/20W
MF
201
2
2
2
0
2
NOSTUFF
1
84
1%
1/20W
MF
201
5%
1/20W
MF
201
2
0
R8974
100K
2
5%
1/20W
MF
201
SYNC_MASTER=D2_MLB_2P
GFXIMVP_VID & lt; 6 & gt;
GFX IMVP VCore Regulator
DRAWING NUMBER
NOSTUFF
1
R8972
1
R8973
100K
2
GFXIMVP_DPSLP_EN
84
2
5%
1/20W
MF
201
5%
1/20W
MF
201
7
6
5
Apple Inc.
100K
2
5%
1/20W
MF
201
8
SYNC_DATE=01/18/2012
PAGE TITLE
84
R8983
1
1
100K
NOSTUFF
2
R8971
GFXIMVP_VR_TT_L
GFXIMVP_PSI_L
GFXIMVP_DPSLP_EN
5%
1/20W
MF
201
10K
1%
1/20W
MF
201
2
1
R8956 1
10K
2
GFXIMVP_PSI_R_L
NOSTUFF
R8955 1
10K
2
IN
R8970
499
R8981
2
1
84 82
84 7
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
4
3
051-9585
2
SIZE
D
REVISION
3.0.0
BRANCH
PAGE
89 OF 132
SHEET
84 OF 105
1
A
8
7
6
5
4
3
2
1
D
D
89
LCD_PWR_EN
IN
R9094 1
10K
5%
1/16W
MF-LF
402 2
LCD (LVDS) INTERFACE
CRITICAL
U9000
CRITICAL
FPF1009
L9000
MFET-2X2-8IN
1
2
=PP3V3_S5_LCD
VIN_1
VOUT_1
4
PP3V3_SW_LCD_UF
3
7
ON
VIN_2
VOUT_2
5
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=3.3V
FERR-250-OHM
GND
1
C9009
THRM
PAD
6
1
2
1
C9011
0.1UF
7
0.1UF
2
SM
C9001
C9012
C9002
1
0.1UF
20%
6.3V
2 X5R
603
10%
50V
X7R
402
1
0.001UF
10%
16V
X5R
402-1
10UF
10%
16V
2 X5R
402-1
10%
16V
X5R
402-1
1
2
518S0852
2
CRITICAL
J9000
20525-140E-01
F-RT-SM
7
=PP3V3_S0_DDC_LCD
41
C
C
1
R9010 1
100K pull-ups are for
1
R9011
100K
Panel has 2K pull-ups
86 6
86 6
100K
5%
1/16W
MF-LF
402
no-panel case (development).
6
5%
1/16W
MF-LF
402
2
2
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=3.3V
10%
50V
X7R
402
1
100 86 6
LVDS_CONN_A_DATA_N & lt; 0 & gt;
LVDS_CONN_A_DATA_P & lt; 0 & gt;
2
100 86 6
100 86 6
CRITICAL
LVDS_CONN_A_DATA_N & lt; 1 & gt;
LVDS_CONN_A_DATA_P & lt; 1 & gt;
100 86 6
DLP11S
SYM_VER-1
100 86 6
LVDS_CONN_A_DATA_N & lt; 2 & gt;
LVDS_CONN_A_DATA_P & lt; 2 & gt;
3
12
14
15
16
100 6
1
9
11
13
L9010
LVDS_CONN_A_CLK_P
8
10
90-OHM-100MA
100 86
5
7
C9010
4
4
6
LVDS_DDC_CLK
LVDS_DDC_DATA
0.001UF
LVDS_CONN_A_CLK_N
3
NC
100 86 6
100 86
2
PP3V3_SW_LCD
100 6
2
LVDS_CONN_A_CLK_F_N
LVDS_CONN_A_CLK_F_P
17
18
19
100 86 6
Place close to the connector
100 86 6
LVDS_CONN_B_DATA_N & lt; 0 & gt;
LVDS_CONN_B_DATA_P & lt; 0 & gt;
20
21
22
100 86 6
100 86 6
CRITICAL
23
24
25
L9011
B
LVDS_CONN_B_DATA_N & lt; 1 & gt;
LVDS_CONN_B_DATA_P & lt; 1 & gt;
90-OHM-100MA
100 86 6
DLP11S
SYM_VER-1
100 86 6
100 86
LVDS_CONN_B_CLK_N
4
3
100 86
LVDS_CONN_B_CLK_P
1
2
LVDS_CONN_B_DATA_N & lt; 2 & gt;
LVDS_CONN_B_DATA_P & lt; 2 & gt;
27
28
100 6
90 6
90 6
90 6
90 6
90 6
29
100 6
90 6
Place close to the connector
B
26
30
LVDS_CONN_B_CLK_F_N
LVDS_CONN_B_CLK_F_P
LED_RETURN_6
LED_RETURN_5
LED_RETURN_4
LED_RETURN_3
LED_RETURN_2
LED_RETURN_1
NC
31
32
33
34
35
36
37
38
39
104 8 6
40
PPVOUT_S0_LCDBKLT
43
44
45
46
47
48
49
50
51
C9000
1
52
0.001UF
A
10%
50V
CERM
402
2
SYNC_MASTER=K18_MLB
42
SYNC_DATE=04/27/2010
PAGE TITLE
LVDS Display Connector
DRAWING NUMBER
Apple Inc.
051-9585
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
3.0.0
BRANCH
PAGE
90 OF 132
SHEET
85 OF 105
1
A
7
6
5
All emulated LVDS outputs require this termination
7
R9202 1
R9220
357
1
LVDS_CONN_A_CLK_P
2
1
1
OUT
5%
1/16W
MF-LF
402
1%
1/20W
MF
201
C9220
1
0.1UF
20%
10V
CERM
402
20%
10V
CERM
402
2
2
D
C9230
0.1UF
10K
85 100
2
18
IN
LVDS_A_CLK_P
2
=PP3V3_S0_DPMUX
PLACE_NEAR=U9600.A6:7mm
100 89
3
DP AUX, DDC, & HPD muxing to IG/EG
LVDS Transmitter Termination
D
4
6
8
VDD
PLACE_NEAR=U9600.A7:7mm
U9220
R9222
100 89
IN
LVDS_A_CLK_N
CBTL03062
357
1
LVDS_CONN_A_CLK_N
2
1%
1/20W
MF
201
100 89
IN
OUT
BGA
85 100
95 8
1
357
LVDS_CONN_A_DATA_P & lt; 0 & gt;
OUT
6 85 100
1%
1/20W
MF
201
PLACE_NEAR=U9600.A8:7mm
BI
100 81 8
2
BI
100 81 8
R9225
LVDS_A_DATA_P & lt; 0 & gt;
BI
95 8
BI
LVDS_A_DATA_N & lt; 0 & gt;
1
IN
LVDS_A_DATA_P & lt; 1 & gt;
357
1
81
IN
357
81
BI
2
LVDS_CONN_A_DATA_N & lt; 0 & gt;
OUT
6 85 100
LVDS_CONN_A_DATA_P & lt; 1 & gt;
2
OUT
IN
LVDS_A_DATA_N & lt; 1 & gt;
IN
DP_EG_DDC_CLK
DP_EG_DDC_DATA
9
11
8
DDC_CLK1
DDC_DAT1
BI
DP_EXTA_DDC_CLK
DP_EXTA_DDC_DATA
3
87 100
BI
87 100
OUT
BI
87
87
TBT/DP HOT PLUG IN
HPD_2
5
4
HPD_1
7
2
HPDIN
10
DP_EXTA_AUXCH_C_P
DP_EXTA_AUXCH_C_N
1
DDC_CLK
DDC_DAT
DDC_CLK2
DDC_DAT2
DP_EG_HPD
GPU_SEL
89
R9205 1
100K
100K
5%
1/16W
MF-LF
402
2
89
IN
DP_MUX_SEL_EG
IN
DP_MUX_EN
(DP_EXTA_HPD)
T29_DP_HPD:MUX_GMUX
R9206
15
XSD*
DP_EXTA_HPD
2
GND
2
89 86 7
OUT
0
1
5%
1/16W
MF-LF
402
19
LVDS_CONN_A_DATA_N & lt; 1 & gt;
2
C
=PP3V3_S0_GMUX
6 85 100
T29_DP_HPD:ALL_OR
1%
1/20W
MF
201
100 89
12
20
AUX+
AUX-
CRITICAL
DP_IG_HPD
R9204 1
357
1
DP_IG_DDC_CLK
DP_IG_DDC_DATA
13
DAUX2+
DAUX2-
OUT
6 85 100
R9232
PLACE_NEAR=U9600.C10:7mm
100 89
14
OUT
5%
1/16W
MF-LF
402
C
DP_EG_AUX_CH_P
DP_EG_AUX_CH_N
16
DAUX1+
DAUX1-
8
1%
1/20W
MF
201
PLACE_NEAR=U9600.A9:7mm
17
82
1%
1/20W
MF
201
R9230
100 89
BI
R9227
PLACE_NEAR=U9600.B9:7mm
IN
IN
8
100 89
8
DP_IG_AUX_CH_P
DP_IG_AUX_CH_N
C9210
R9235
357
LVDS_A_DATA_P & lt; 2 & gt;
1
2
LVDS_CONN_A_DATA_P & lt; 2 & gt;
OUT
6 85 100
8
1%
1/20W
MF
201
PLACE_NEAR=U9600.B10:7mm
82 33
DP_TBTSNK0_HPD
5
74LVC2G32GT
3
U9210
82 33
DP_TBTSNK1_HPD
6
20%
10V
CERM
402
SOT833
A
Y
1
0.1UF
T29_DP_HPD:ALL_OR
CRITICAL
2
TBT_HOTPLUG_DET_OR
B
4
100 89
IN
LVDS_A_DATA_N & lt; 2 & gt;
1
100 89
IN
LVDS_B_CLK_P
1
2
LVDS_CONN_A_DATA_N & lt; 2 & gt;
OUT
1
6 85 100
U9210
(DP_EXTA_HPD)
87
LVDS_CONN_B_CLK_P
2
OUT
OUT
LVDS_CONN_B_CLK_N
2
IN
LVDS_B_DATA_P & lt; 1 & gt;
LVDS_B_DATA_N & lt; 1 & gt;
IN
G
1
LVDS_CONN_B_DATA_N & lt; 0 & gt;
OUT
OUT
357
R9270 1
LVDS_CONN_B_DATA_N & lt; 1 & gt;
2
7
OUT
5%
1/16W
MF-LF
402
6 85 100
R9255
1
357
2
LVDS_CONN_B_DATA_P & lt; 2 & gt;
C9270
OUT
6 85 100
R9272 1
1
20%
10V
CERM
402
LVDS_B_DATA_N & lt; 2 & gt;
PLACE_NEAR=U9600.A5:7mm
1
14
2
IN
LVDS_DDC_SEL_EG
13
357
2
LVDS_CONN_B_DATA_N & lt; 2 & gt;
89
OUT
6 85 100
IN
LVDS_DDC_SEL_IG
5
1%
1/20W
MF
201
1
20K
0.1UF
1%
1/20W
MF
201
1
20K
=PP3V3_S0_LVDSDDCMUX
R9257
IN
=PP3V3_GPU_LVDS_DDC
R9252
89
100 89
B
6 85 100
7
PLACE_NEAR=U9600.C5:7mm
A
DP_A_EXT_HPD
LVDS DDC MUX
2
LVDS_B_DATA_P & lt; 2 & gt;
IN
5%
1/16W
MF-LF
402
6 85 100
LVDS_CONN_B_DATA_P & lt; 1 & gt;
2
1%
1/20W
MF
201
1%
1/20W
MF
201
100 89
6 85 100
1%
1/20W
MF
201
1
100K
2
357
1
PLACE_NEAR=U9600.B3:7mm
IN
OUT
87 46
357
1
PLACE_NEAR=U9600.A1:7mm
100 89
LVDS_CONN_B_DATA_P & lt; 0 & gt;
T29_DP_HPD:MCU_GMUX
R9281
R9247
LVDS_B_DATA_N & lt; 0 & gt;
R9250
100 89
2
1%
1/20W
MF
201
PLACE_NEAR=U9600.A3:7mm
IN
1
SOD-VESM-HF
S
1
357
2
LVDS_B_DATA_P & lt; 0 & gt;
PLACE_NEAR=U9600.A2:7mm
100 89
Q9280
SSM3K15FV
R9245
D
IN
7 86 89
T29_DP_HPD:MCU_GMUX
6
12
VCC
U9270
QFN1
1
C1
A1 2
B1
C2
C3
SN74LV4066A
100 89
5%
1/16W
MF-LF
402
R9271
20K
2
2
5%
1/16W
MF-LF
402
R9273
20K
2
2
5%
1/16W
MF-LF
402
LVDS_EG_DDC_CLK
IN
81
LVDS_IG_DDC_CLK
LVDS_DDC_CLK
4
A2 3
B2
IN
17
OUT
6 85
LVDS_EG_DDC_DATA
BI
11
LVDS_IG_DDC_DATA
LVDS_DDC_DATA
BI
17
BI
6 85
Apple Inc.
6
5
CRITICAL
NOTICE OF PROPRIETARY PROPERTY:
4
051-9585
3
2
SIZE
D
REVISION
R
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
7
SYNC_DATE=11/21/2010
Muxed Graphics Support
81
DRAWING NUMBER
A4
B4 10
GND THRM
15
SYNC_MASTER=K92_MLB
PAGE TITLE
8
A3 9
B3
C4
7
8
89
85 100
3
357
1
1%
1/20W
MF
201
B
OUT
4
85 100
=PP3V3_S0_GMUX
IN
DP_HOTPLUG_DET
B
R9242
PLACE_NEAR=U9600.C9:7mm
LVDS_B_CLK_N
Y
2
IN
1%
1/20W
MF
201
PLACE_NEAR=U9600.C8:7mm
100 89
SOT833
A
7
1%
1/20W
MF
201
R9240
74LVC2G32GT
8
357
357
T29_DP_HPD:ALL_OR
R9237
PLACE_NEAR=U9600.A10:7mm
3.0.0
BRANCH
PAGE
92 OF 132
SHEET
86 OF 105
1
A
6
5
4
3
8
1
98 33
DP_EXTA_ML_N & lt; 0 & gt;
2
10%
X5R
0.1UF
98 33
87 100
OUT
OUT
6.3V
201
C9370
(C9370/C9371)
TBT_D2R_N & lt; 0 & gt;
TBT_D2R_P & lt; 0 & gt;
C9302
DP_EXTA_ML_C_P & lt; 1 & gt;
IN
1
100 81
C9303
DP_EXTA_ML_C_N & lt; 1 & gt;
IN
1
87 100
6.3V
201
98 33 6
DP_EXTA_ML_N & lt; 1 & gt;
2
10%
X5R
0.1UF
(C9372.1 & 2)
DP_EXTA_ML_P & lt; 1 & gt;
2
10%
X5R
0.1UF
98 33 6
87 100
IN
IN
6.3V
201
D
C9304
DP_EXTA_ML_C_P & lt; 2 & gt;
IN
1
100 81
C9305
DP_EXTA_ML_C_N & lt; 2 & gt;
IN
DP_EXTA_ML_P & lt; 2 & gt;
2
10%
X5R
0.1UF
1
8
8
87 100
6.3V
201
1
1.5K
5%
MF
R9372
1
2
1/20W
201
D9372
98
98
TBT_R2D_P & lt; 0 & gt;
TBT_R2D_N & lt; 0 & gt;
2
C9306
DP_EXTA_ML_C_P & lt; 3 & gt;
1
1
10%
X5R
0.1UF
100 81
C9307
DP_EXTA_ML_C_N & lt; 3 & gt;
IN
DP_EXTA_ML_P & lt; 3 & gt;
1
6.3V
201
98 33
2
TBT_A_BIAS2P
IN
5%
MF
1/20W
201
D9365
C9308
DP_EXTA_AUXCH_C_P
BI
1
10%
X5R
100 86
C9309
DP_EXTA_AUXCH_C_N
BI
1
1
C9381
2
1/20W
201
98 33 6
IN
98 33 6
IN
1M
1
2
GND_VOID=TRUE
5%
MF
30
1
R9355
DP A Super-Driver
30
98
1
1
C9311
PS8301 I2C Addresses:
5%
MF
A0
0
1
0
1
2
100 87
100 87
100 87
100 87
100 87
100 87
100 87
R9311
1
1
1K
5%
1/16W
MF-LF
402
100 87
30
98
1
1
1K
2
2
86
IN
86
5%
1/16W
MF-LF
402
BI
100 87
100 87
R9312
86
OUT
5%
1/16W
MF-LF
402
1
1
2
4
DP_EXTA_ML_P & lt; 1 & gt;
DP_EXTA_ML_N & lt; 1 & gt;
5
7
DP_EXTA_ML_P & lt; 2 & gt;
DP_EXTA_ML_N & lt; 2 & gt;
8
9
DP_EXTA_ML_P & lt; 3 & gt;
DP_EXTA_ML_N & lt; 3 & gt;
10
DP_EXTA_DDC_CLK
DP_EXTA_DDC_DATA
14
DP_EXTA_AUXCH_P
DP_EXTA_AUXCH_N
16
13
15
3
DP_EXTA_HPD
26
DPSDRVA_I2C_ADDR0
DPSDRVA_I2C_ADDR1
BI
36
=I2C_DPSDRVA_SCL
=I2C_DPSDRVA_SDA
IN
48
IN_D0P
IN_D0N
C9361
1
23 16
OUT_D1P
OUT_D1N
38
35
37
1
R9318
4.99K
28
98
27
98
25
IN_D3P
IN_D3N
OUT_D3P
OUT_D3N
23
98
22
98
IN_SCL
IN_SDA
AC_AUXP
AC_AUXN
20
98
19
98
OUT_AUXP_SCL
OUT_AUXN_SDA
18
OUT_HPD
31
IN_AUXP
IN_AUXN
IN_HPD
2
C9367
DP_SDRVA_ML_C_P & lt; 1 & gt;
DP_SDRVA_ML_C_N & lt; 1 & gt;
(IPD)
I2C_CTL_EN
I2C_ADDR0
I2C_ADDR1
5%
1/16W
MF-LF
402
2
1
(IPU)
CA_DET
DP_A_CA_DET
11
98 6
6.3V
0201
98 6
2
1
20%
6.3V
CERM
402-LF
98 6
2
DP_SDRVA_ML_P & lt; 2 & gt;
DP_SDRVA_ML_N & lt; 2 & gt;
98
6.3V
201
10%
X5R
98
98
2
PP3V3_SW_TBTAPWR
C9390
IN
IN
48
BI
88
IN
87 8
OUT
33
OUT
33
DP_A_CA_DET
1
OUT
7
=I2C_TBTAMCU_SCL
=I2C_TBTAMCU_SDA
TBT_A_HPD
=TBT_A_BIAS
TBT_LSOE & lt; 0 & gt;
TBT_LSOE & lt; 1 & gt;
8
9
10
11
12
13
14
SWCLK
0
5%
1/16W
MF-LF
402
TBT_A_UC_ADDR
2
1.5K
18
OUT
TBT_PWR_REQ_L
1
C9391
1
1/20W
201
1/20W
201
1/20W
201
5%
MF
1/20W
201
1/20W
201
VOLTAGE=3.3V
C
DP_A_BIAS2
2
8
1/20W
201
20%
10V
CERM
402
8
VOLTAGE=3.3V
R9399 1
1
0.1UF
2
100K
5%
1/20W
MF
201 2
2
31
(DP_SDRVA_ML_N & lt; 1 & gt; )
(DP_SDRVA_ML_P & lt; 1 & gt; )
2
27
30
26
19
DP_SDRVA_AUXCH_P
DP_SDRVA_AUXCH_N
18
5%
1/16W
MF-LF
402
22
C9330
1
1
0.1UF
VDD
20%
10V
CERM
402
OMIT_TABLE
C9331
2
2
5%
1/16W
MF-LF
402
1
AUX+
AUX-
6
1
22
15
1K
5%
1/16W
MF-LF
402
R9397
1K
2
2
5%
1/16W
MF-LF
402
14
NC
8
87
87 8
DP_A_PWRDWN
=TBT_A_BIAS
15
HVQFN25
R/PIO1_0/AD1
R/PIO1_1/AD2
R/PIO1_2/AD3
(IPU) SWDIO/PIO1_3/AD4
PIO1_4/AD5/WAKEUP
PIO0_4/SCL (OD)
PIO0_5/SDA (OD)
PIO0_6/SCK
PIO1_6/RXD
PIO0_7/CTS#
PIO1_7/TXD
PIO0_8/MISO/CT16B0_MAT0
PIO1_8/CT16B1_CAP0
PIO0_9/MOSI/CT16B0_MAT1
SWCLK/PIO0_10/SCK/CT16B0_MAT2 (OD)
R/PIO0_11/AD0 (OD)
THRM
XTALIN
VSS
PAD
DIN2_1+
DIN2_1AUX2+
AUX2-
13
16
17
18
19
87
86 46
20
TBT_A_CONFIG1_RC
TBT_A_CONFIG2_RC
TBT_A_HV_EN_R
TBT_A_UC_ADDR
DP_A_EXT_HPD
IN
GPU_SEL
AUX_SEL
NC
32
11
24
6
R9334
1
I2C Addr:
0x26/0x27 (Wr/Rd)
10K
TBT_A_HV_EN
2
IN
R9335
1K
4
5%
1/16W
MF-LF
402
R9336
BI
88 98
88 98
BI
DP_A_EXT_HPD
IN
88 98
BI
88 98
46 86 87
R9398
100K
5%
1/20W
MF
201
SIGNAL_MODEL=T29DP_MUX
SYNC_MASTER=J31_WILL
SYNC_DATE=06/20/2011
PAGE TITLE
Thunderbolt MUXing A
33
1
DRAWING NUMBER
R9339
Apple Inc.
1M
2
5%
1/16W
MF-LF
402
NOTICE OF PROPRIETARY PROPERTY:
2
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SWDIO
4
051-9585
3
2
SIZE
D
REVISION
R
2
5
OUT
DP_A_EXT_AUXCH_P
DP_A_EXT_AUXCH_N
7
1
35 88
P2R = Plug to Receptacle
R2P = Receptacle to Plug
10K
5%
1/16W
MF-LF
402
OUT
5%
1/16W
MF-LF
402
1
1
88 98
THMPAD GND
88
87
TBT_A_LSX_P2R
TBT_A_LSX_R2P
TBT_LSEO & lt; 1 & gt;
23
88 98
BI
TBT_A_ML_N & lt; 1 & gt;
TBT_A_ML_P & lt; 1 & gt;
5
2
88
IN
OUT
HPD_2
10
4
2
2
6
TBT_A_ML_N & lt; 3 & gt;
TBT_A_ML_P & lt; 3 & gt;
2
DIN2_0+
DIN2_0-
23
TBT_D2R1_BIASP
TBT_D2R1_BIASN
10K
20%
10V
CERM
402
DOUT_0+
DOUT_0CRITICAL
OMIT_TABLE
DOUT_1+
DOUT_1-
HPD_IN
AUX1+
AUX1-
25
(TBT_A_LSX_P2R)
(TBT_A_LSX_R2P)
5%
1/16W
MF-LF
402
R9338 1
0.1UF
HVQFN
R9393
51
2
B
CBTL04DP081
DIN1_1+
DIN1_1-
HPD_1
24
1
DIN1_0+
VDD
DIN1_0- U9390
17
1
R9396 1
RESET#/PIO0_0
PIO0_1/CLKOUT
PIO0_2/SSEL/CT16B0_CAP0
R9330 provides pads for programming/debug of MCU,
please make accessible. If project has space for
10-pin programming header it should be used.
7
5%
MF
87 88
(DP_SDRVA_HPD)
TBT_A_RSVDN
TBT_A_RSVDP
3
R9330 1
1
16V
402
PP3V3_SW_TBTAPWR
TBT_LSEO & lt; 0 & gt;
=TBT_WAKE_L
OMIT
1.5K
DP_A_BIAS0
5%
MF
2
R9392
2
48
Desktops use PCIe WAKE#
Mobiles use S4 WAKE#
2
33
89 87
33
=TBT_WAKE_L:
2
1
LPC1112A
3
IC supports input
high while Vcc = 0V.
1
1.5K
20%
10V
CERM
402
98
CRITICAL
2
4
SC70
1.5K
(DP_SDRVA_ML_N & lt; 3 & gt; )
(DP_SDRVA_ML_P & lt; 3 & gt; )
U9330
74LVC1G04DBDCK
=DP_A_BIAS
2
Must be V3P3 output from U9410
6.3V
201
1
25
5
2
1
DP/TBT A Low-Speed MUX
DP_SDRVA_ML_P & lt; 1 & gt;
DP_SDRVA_ML_N & lt; 1 & gt;
THMPAD
5
U9359
1.5K
DP_SDRVA_ML_P & lt; 3 & gt;
DP_SDRVA_ML_N & lt; 3 & gt;
98
GND
21
2
1
5%
MF
R9361
(IPD)
0.1UF
CRITICAL
1.5K
GND_VOID=TRUE
R9385
DP Path Biasing
6.3V
0201
(IPD)
C9359
10%
16V
X5R
402
GND_VOID=TRUE
R9384
(D9360/D9361)
98 6
6.3V
0201
=PP3V3_S0_DPSDRVA
1
GND_VOID=TRUE
TSLP-2-7
2
Must be 3.3V DP A port power
See Bill C. for layoutspecific guidelines for
=DP_A_BIAS.
88 98
(D9382/D9383)
(D9361.2)
SIGNAL_MODEL=EMPTY
16V
402
10%
X5R
88 98
OUT
(D9382/D9383)
2
10%
X5R
1
10%
X5R
OUT
SIGNAL_MODEL=T29PIN
6.3V
0201
2.2UF
AUXDDC_OFF
88 87
K
SIGNAL_MODEL=T29PIN
DP_SDRVA_ML_P & lt; 0 & gt;
DP_SDRVA_ML_N & lt; 0 & gt;
2
0.1uF
C9319
39
DP_A_PWRDWN
A
BAR90-02LRH
2
88 98
PLACE_NEAR=U9310.11:2 mm
SCL_CTL
SDA_CTL
PD
98
2
8
D9361
1/20W
201
88 98
IN
6.3V
201
Port A MCU
87
5%
MF
R9383
0.1UF
1
0.1uF
87 89
DPSDRVA_CEXT
REXT
34
IN
TSLP-2-7
GND_VOID=TRUE
AUXCH Snoop Port, used by
PS8301 during training.
(IPD)
CEXT
1
0.1UF
C9368
(IPD)
6.3V
201
2
0.1UF
C9362
DP_SDRVA_HPD
32
K
BAR90-02LRH
2
DP_SDRVA_ML_C_P & lt; 3 & gt;
DP_SDRVA_ML_C_N & lt; 3 & gt;
(DP_SDRVA_AUXCH_P)
(DP_SDRVA_AUXCH_N)
17
A
5%
MF
10%
X5R
C9363
IN
TBT: TX_1
TBT_A_ML_C_P & lt; 2 & gt;
TBT_A_ML_C_N & lt; 2 & gt;
TSLP-2-7
R9365
10%
X5R
1
0.1UF
DP_SDRVA_AUXCH_C_P
DP_SDRVA_AUXCH_C_N
1/20W
201
2
0.1UF
DP_SDRVA_ML_C_P & lt; 2 & gt;
DP_SDRVA_ML_C_N & lt; 2 & gt;
24
2
1/20W
201
5%
MF
1
5%
MF
TSLP-2-7
R9360
51
OUT
1
5%
1/20W
MF
201
1
C9366
C9369
PS8301 has internal
~150K pull-down on PD
pin. Okay to drive this
pin even when VCC=0V per
Parade (pin is 5V-tolerant).
2
0
1%
1/16W
MF-LF
402
17
D9383
DP_SDRVA_ML_C_P & lt; 0 & gt;
DP_SDRVA_ML_C_N & lt; 0 & gt;
29
OUT_D2P
OUT_D2N
12
DP_A_PWRDWN_R
R9319
30
IN_D2P
IN_D2N
DP_AUXCH_ISOL
IN
SDRV_PD
A
1.5K
K
BAR90-02LRH
270
2
2
(D9360.2)
GND_VOID=TRUE
5%
MF
5%
1/20W
MF
201
OUT_D0P
OUT_D0N
A
BAR90-02LRH
R9353
270
IN_D1P
IN_D1N
6
R9319 value depends
on layout. 4.99K is
vendor recommendation.
OUT
98
K
R9364
1
1.5K
1
GND_VOID=TRUE
CRITICAL
(All 4 D’s)
20%
X5R
0.22UF
R9352 1
CRITICAL
DPSDRVA_REXT
8
2
TBT_R2D_P & lt; 1 & gt;
TBT_R2D_N & lt; 1 & gt;
GND_VOID=TRUE
20%
X5R
0.22UF
2
VDD
DP_EXTA_ML_P & lt; 0 & gt;
DP_EXTA_ML_N & lt; 0 & gt;
DPSDRVA_I2C_CTL_EN
48
87 7
98
2
20%
X5R
C9360
DP_SDRVA_ML_R_P & lt; 2 & gt;
DP_SDRVA_ML_R_N & lt; 2 & gt;
R9382
1
A
D9382
20%
X5R
C9365
1/20W
201
98
D9360
1/20W
201
2
TBT_A_BIAS2N
1
1.5K
R9375
SIGNAL_MODEL=EMPTY
VOLTAGE=3.3V
0.22UF
R9310
1K
87
1.5K
5%
MF
QFN
NO STUFF
B
20%
10V
CERM
402
PS8301TQFN40GTR-A2
Note: Other Parade
devices use 96/B6,
so only 94/B4 are
used for this part.
2
2
0.1UF
U9310
Addr (W/R)
0x96/0x97
0xB6/0xB7
0x94/0x95
0xB4/0xB5
1
2
R9351
C9312
20%
10V
CERM
402
1/20W
201
D
GND_VOID=TRUE
R9374
SIGNAL_MODEL=T29PIN
SIGNAL_MODEL=T29PIN
D9372/D9373:
GND_VOID=TRUE
41
A1
0
0
1
1
1
0.1UF
33
C
20%
6.3V
CERM
402-LF
1
0.22UF
2
40
1
2.2UF
21
C9310
1
GND_VOID=TRUE
TSLP-2-7
2
20%
4V
CERM-X5R-1
GND_VOID=TRUE
201
IN
1/20W
201
5%
MF
30
DP_SDRVA_ML_R_P & lt; 0 & gt;
DP_SDRVA_ML_R_N & lt; 0 & gt;
2
5%
MF
R9350
98
1/20W
201
88 98
(D9372/D9373)
(D9365.2)
TBT_D2R_C_P & lt; 1 & gt;
TBT_D2R_C_N & lt; 1 & gt;
20%
4V
CERM-X5R-1
201
C9364
2
5%
MF
=PP3V3_S0_DPSDRVA
8
1/20W
201
K
20%
4V
CERM-X5R-1
201
0.47UF
R9354
87 7
1
C9383
(C9383.1 & 2)
R9308
A
CRITICAL
(All 4 D’s)
D9364/D9365:
GND_VOID=TRUE
0.47UF
87 100
88 98
OUT
2
20%
4V
CERM-X5R-1
201
C9382
TBT_R2D_C_N & lt; 1 & gt;
TBT_R2D_C_P & lt; 1 & gt;
16V
402
If GPU uses common pins for AUX_CH
and DDC, alias nets together at GPU.
1
0.47UF
(C9383.1 & 2)
5%
MF
87 100
DP_EXTA_AUXCH_N
10%
X5R
OUT
1
0.47UF
7 87
16V
402
2
0.1uF
1M
DP_EXTA_AUXCH_P
2
0.1uF
=PP3V3_S0_DPSDRVA
C9380
TBT_D2R_N & lt; 1 & gt;
TBT_D2R_P & lt; 1 & gt;
TSLP-2-7
BAR90-02LRH
TBT Path
Biasing
VOLTAGE=3.3V
GND_VOID=TRUE
GND_VOID=TRUE
R9309
100 86
87 100
6.3V
201
OUT
98 33
DP_EXTA_ML_N & lt; 3 & gt;
10%
X5R
0.1UF
87 100
K
VOLTAGE=3.3V
caps to improve layout.
2
A
GND_VOID=TRUE
R9373
TBT_A_BIAS0N
88 98
OUT
TBT: TX_0
TBT_A_ML_C_P & lt; 0 & gt;
TBT_A_ML_C_N & lt; 0 & gt;
TSLP-2-7
BAR90-02LRH
2
88 98
IN
(D9364.2)
GND_VOID=TRUE
K
29
IN
IN
TSLP-2-7
A
D9373
GND_VOID=TRUE
1.5K
K
BAR90-02LRH
(C9380/C9381)
100 81
A
BAR90-02LRH
2
20%
4V
CERM-X5R-1
201
20%
4V
CERM-X5R-1
GND_VOID=TRUE
201
IN
D9364
GND_VOID=TRUE
0.47UF
P/N-swapped after AC
DP_EXTA_ML_N & lt; 2 & gt;
2
10%
X5R
0.1UF
1
C9373
TBT signals are
87 100
6.3V
201
TBT_D2R_C_P & lt; 0 & gt;
TBT_D2R_C_N & lt; 0 & gt;
2
GND_VOID=TRUE
0.47UF
GND_VOID=TRUE
2
20%
4V
CERM-X5R-1
201
20%
4V
CERM-X5R-1
201
C9372
TBT_R2D_C_N & lt; 0 & gt;
TBT_R2D_C_P & lt; 0 & gt;
(C9373.1 & 2)
100 81
1
0.47UF
GND_VOID=TRUE
100 81
1
0.47UF
C9371
3
C9301
DP_EXTA_ML_C_N & lt; 0 & gt;
IN
87 100
6.3V
201
9
100 81
GND_VOID=TRUE
DP_EXTA_ML_P & lt; 0 & gt;
2
10%
X5R
12
1
0.1UF
1
21
C9300
DP_EXTA_ML_C_P & lt; 0 & gt;
IN
VOLTAGE=3.3V
28
100 81
2
TBT A High-Speed Signals
TBT_A_BIAS0P
IN
16
7
20
8
3.0.0
BRANCH
PAGE
93 OF 132
SHEET
87 OF 105
1
A
8
7
6
5
4
3
2
1
3.3V/HV Power MUX
V3P3 must be S4 to support
wake from Thunderbolt devices.
7
D
=PP3V3_S4_TBTAPWRSW
CRITICAL
C9487
C9480
1
1
2
C9481
2
22UF
100UF
20%
6.3V
POLY-TANT
CASE-B2-SM
1
20%
6.3V
X5R-CERM-1
603
2
Nominal
1100mA
890mA
890mA
IV3P3
IHVS0
IHVS3
CRITICAL
0.1UF
PP3V3_SW_TBTAPWR
20
V3P3OUT
12
7
C9410
1
4.7UF
1
10%
50V
X7R
603-1
2
MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=15V
VHV
C9485
CRITICAL
0.1UF
10%
25V
X5R-CERM
0603
PPHV_SW_TBTAPWR
14
OUT
6
20%
10V
CERM
402
CD3210A0RGP
QFN
16
RSVD
1
1
0.1UF
U9410
2
RSVD
87
MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=3.3V
18
V3P3
=PPHV_SW_TBTAPWRSW
20V Max
C9415
D
Max
1200mA
930mA (assumes 15V, 12W minimum)
930mA (assumes 3S - 9-12.6V, 1W minimum)
20%
10V
CERM
402
19
7
Min
1030mA
830mA
830mA
C9486
1
C9411
10UF
2
2
0.1UF
20%
6.3V
X5R
603
2
10%
50V
X7R
603-1
15
IN
=TBTAPWRSW_EN
8
TBTAPWRSW_ISET_V3P3
87 35
IN
TBT_A_HV_EN
11
HV_EN
ISET_S0
10
TBTAPWRSW_ISET_S0
74
IN
=TBT_S0_EN
17
S0
ISET_S3
9
TBTAPWRSW_ISET_S3
74
5
ISET_V3P3
EN
TBTHV:P15V
TBTHV:P15V
R9410 1
12V: See
below
21
4
THRM
PAD
13
3
2
1
GND
1
1
R9411
22.6K
22.6K
1%
1/16W
MF-LF
402 2
& lt; RHVS3 & gt;
R9412
ILIM = 40000 / RISET
36.5K
1%
1/16W
MF-LF
2 402
1%
1/16W
MF-LF
2 402
& lt; RHVS0 & gt;
& lt; RV3P3 & gt;
TBTAPWRSW_ISET_S3_R
C
TBTHV:P15V
C
TBTAPWRSW_ISET_S0_R
R9413 1
TBTHV:P15V
1
22.6K
1%
1/16W
MF-LF
402 2
R9414
22.6K
2
1%
1/16W
MF-LF
402
Thunderbolt Connector A
L9400
For 12V systems:
FERR-120-OHM-3A
PART NUMBER
QTY
114S0464
1
114S0368
Nominal
IHVS0 1120mA
IHVS3
125mA
DESCRIPTION
CRITICAL
BOM OPTION
R9410
RES,MTL FILM,1/16W,384K,1,0402,SMD,LF
1
Min
1090mA
124mA
REFERENCE DES
R9411
RES,MTL FILM,1/16W,36.5K,1,0402,SMD,LF
1
2
C9400
TBTHV:P12V
PP3V3RHV_SW_TBTAPWR
MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=15V
0603
TBTHV:P12V
1
10%
50V
X7R
402
Max
1170mA (12W minimum)
126mA (1W minimum)
TBTACONN_1_C
For J9400 TBT SMT pads
(3, 5, 17 & 19):
GND_VOID=TRUE
2
TBT Dir
98 87
98 87
OUT
OUT
C9405
GND_VOID=TRUE
0.01UF
DP Dir
CRITICAL
TBT_D2R_C_P & lt; 0 & gt;
TBT_D2R_C_N & lt; 0 & gt;
5%
1/20W
MF
201
2
2
8
8
IN
IN
98 87
TBT_A_BIAS1N
2
4
SIGNAL_MODEL=EMPTY
6
OUT
12
14
CRITICAL
5%
1/20W
MF
201
2
2
18
L9498
20
650NH-5%-0.430MA-0.52OHM
2.2K
GND_VOID=TRUE
98 87
10
R9499
5%
1/20W
MF
201
OUT
TBT_A_ML_P & lt; 3 & gt;
TBT_A_ML_N & lt; 3 & gt;
VOLTAGE=3.3V
2.2K
GND_VOID=TRUE
2
1
SIGNAL_MODEL=T29PIN
D9498
GND_VOID=TRUE
TBT_D2R_C_P & lt; 1 & gt;
TBT_D2R_C_N & lt; 1 & gt;
A
A
BAR90-02LRH
98
K
2
DP_A_EXT_AUXCH_P
DP_A_EXT_AUXCH_N
22
OUT
TBT_A_CONFIG1_RC
87
OUT
2
1
1
TBT_A_CONFIG2_RC
2
2
87 98
TBT_A_ML_C_P & lt; 2 & gt;
TBT_A_ML_C_N & lt; 2 & gt;
IN
87 98
IN
87 98
5%
1/20W
MF
201
11
R9452 1
1
1M
5%
1/16W
MF-LF
402
B
87 98
TBT: LSX_R2P/P2R (P/N)
15
17
19
(Both C’s)
C9472
21
1
2
20%
4V
CERM-X5R-1
201
0.47UF
TBT_A_ML_P & lt; 2 & gt;
TBT_A_ML_N & lt; 2 & gt;
C9473
1
2
20%
4V
CERM-X5R-1
201
0.47UF
GND_VOID=TRUE
1
GND_VOID=TRUE
1
R9472
470K
GND_VOID=TRUE
R9401
MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=18V
C9402
1
1
0.01UF
10%
50V
X7R
402
C9401
1
12
2
2
5%
1/16W
MF-LF
402
2
2
5%
1/20W
MF
201
470k R’s for ESD protection
on AC-coupled signals.
0.01UF
2
R9473
470K
5%
1/20W
MF
201
10%
50V
X7R
402
DP Source must pull
down HPD input with
greater than or equal
to 100K (DPv1.1a).
R9451
1M
2
2
5%
1/16W
MF-LF
402
C9494
1
1
330PF
10%
50V
CERM
402
C9495
330PF
2
2
10%
50V
CERM
402
SYNC_MASTER=T29_REF
1
Thunderbolt Connector A
100K
2
7
5%
1/16W
MF-LF
402
DRAWING NUMBER
Apple Inc.
Sink HPD range:
High: 2.0 - 5.0V
Low: 0 - 0.8V
6
SYNC_DATE=06/14/2011
PAGE TITLE
R9441
051-9585
NOTICE OF PROPRIETARY PROPERTY:
5
4
3
2
SIZE
D
REVISION
R
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
BI
13
1
5%
25V
C0G-CERM
0201
IN
R9471
470K
5%
1/20W
MF
201
TBT: TX_1
C9499
2
87 98
GND_VOID=TRUE
1
R9470
9
98
30PF
87 98
IN
TBT_A_HPD
OUT
(0-20V)
7
98
TBTACONN_20_RC
5%
25V
C0G-CERM
0201
87
10%
50V
X7R
402
IN
20%
4V
CERM-X5R-1
201
470K
2
TBT_A_ML_C_P & lt; 0 & gt;
TBT_A_ML_C_N & lt; 0 & gt;
2
GND_VOID=TRUE
SIGNAL_MODEL=EMPTY
30PF
87
5
1
0.01UF
1
MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=3.3V
L9499
C9498
A
3
650NH-5%-0.430MA-0.52OHM
0603
BI
TBTACONN_7_C
CRITICAL
TSLP-2-7
SIGNAL_MODEL=T29PIN
98 87
GND_VOID=TRUE
1
TBT_A_D2R1_AUXCH_P
TBT_A_D2R1_AUXCH_N
CRITICAL
BI
HOT_PLUG_DETECT
GND
CONFIG1
ML_LANE0P
CONFIG2
ML_LANE0N
GND
GND
ML_LANE3P
ML_LANE1P
ML_LANE3N
ML_LANE1N
GND
GND
AUX_CHP
ML_LANE2P
AUX_CHN
ML_LANE2N
DP_PWR
RETURN
C9406
SHIELD PINS
GND_VOID=TRUE
98 87
SM PINS
GND_VOID=TRUE
SIGNAL_MODEL=EMPTY
98
TSLP-2-7
D9499
1
0.47UF
0603
K
BAR90-02LRH
C9471
GND_VOID=TRUE
16
1
2
20%
4V
CERM-X5R-1
201
0.47UF
TBT_A_ML_P & lt; 0 & gt;
TBT_A_ML_N & lt; 0 & gt;
TOP ROW
TH PINS
5%
1/20W
MF
201
TBT_A_BIAS1P
1
1
TBT_A_ML_P & lt; 1 & gt;
TBT_A_ML_N & lt; 1 & gt;
98
BOT ROW
Thunderbolt: Unused
VOLTAGE=3.3V
R9498
98 87
BI
DP Dir
TBT: TX_0
R9495
8
B
(Both C’s)
C9470
F-RT-THSM
1K
SIGNAL_MODEL=EMPTY
BI
GND_VOID=TRUE
(0-20V)
TBT Dir
98
GND_VOID=TRUE
1
1K
2
10%
50V
X7R
402
DSPLYPRT-M97-1
R9494 1
98 87
1
J9400
GND_VOID=TRUE
0.01UF
MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=3.3V
3.0.0
BRANCH
PAGE
94 OF 132
SHEET
88 OF 105
1
A
8
7
6
5
4
3
2
R9600
89 86 7
=PP3V3_S0_GMUX
1
0
C9610
1
PP3V3_S0_GMUX_R
C9621
1
1
C9622
1
C9623
1
C9624
1
C9625
1
C9626
C9627
1
1
C9628
1
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.09 mm
VOLTAGE=3.3V
C9629
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
10%
6.3V
X5R
201
10%
6.3V
X5R
201
10%
6.3V
X5R
201
10%
6.3V
X5R
201
10%
6.3V
X5R
201
10%
6.3V
X5R
201
10%
6.3V
X5R
201
10%
6.3V
X5R
201
95 89 17
95 89 17
0.1UF
10%
6.3V
X5R
201
2
LVDS Receiver Termination
GMUX CPLD
2
5%
1/16W
MF-LF
402
10%
6.3V
X5R
201
2
2
2
2
2
2
2
2
2
95 89 17
95 89 17
L9621
R9610
D
7
=PP1V8_S0_GMUX
0
1
95 89 17
FERR-220-OHM
95 89 17
PP1V8_S0_GMUX_R
2
5%
1/16W
MF-LF
402
1
C9611
1
0.1UF
2
C9612
1
0.1UF
10%
6.3V
X5R
201
2
C9613
1
0.1UF
10%
6.3V
X5R
201
2
C9614
1
0.1UF
10%
6.3V
X5R
201
2
C9615
C9616
1
0.1UF
10%
6.3V
X5R
201
2
1
95 89 17
C9631
100 89 81
0.1UF
10%
6.3V
X5R
201
2
2
2
10%
6.3V
X5R
201
100 89 81
100 89 81
100 89 81
L9620
100 89 81
PP3V3_S0_GMUX_LRC_VCCPLL
1
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.09 mm
VOLTAGE=3.3V
=PP1V2_S0_GMUX
R9650
R9651
R9652
R9653
LVDS_IG_A_CLK_P
LVDS_IG_A_DATA_P & lt; 0 & gt;
LVDS_IG_A_DATA_P & lt; 1 & gt;
LVDS_IG_A_DATA_P & lt; 2 & gt;
R9654
R9655
R9656
LVDS_IG_B_DATA_P & lt; 0 & gt;
LVDS_IG_B_DATA_P & lt; 1 & gt;
LVDS_IG_B_DATA_P & lt; 2 & gt;
100
100
1
2
1
2
100
1
2
100
1
2
100
100
1
1
2
100
1
2
2
100 89 81
0402
1
100 89 81
LVDS_EG_A_CLK_P
LVDS_EG_A_DATA_P & lt; 0 & gt;
LVDS_EG_A_DATA_P & lt; 1 & gt;
LVDS_EG_A_DATA_P & lt; 2 & gt;
R9660
R9661
R9662
R9663
LVDS_EG_B_DATA_P & lt; 0 & gt;
LVDS_EG_B_DATA_P & lt; 1 & gt;
LVDS_EG_B_DATA_P & lt; 2 & gt;
R9664
R9665
R9666
100
1
4.7UF
2
C9604
1
C9605
C9606
1
1
C9607
1
C9608
1
C9609
0.1UF
20%
4V
X5R-1
402
2
0.1UF
0.1UF
0.1UF
0.1UF
10%
6.3V
X5R
201
10%
6.3V
X5R
201
10%
6.3V
X5R
201
10%
6.3V
X5R
201
2
0.1UF
10%
6.3V
X5R
201
10%
6.3V
X5R
201
2
2
2
2
2
2
1
1
201
201
2
100
1
2
100
1
2
100
100
1
2
1
2
C9630
201
201
201
EG_PWRSEQ_EN
R9684
1K
1
GMUX_CFG0
C
R9685
10K
1
10K
1%
1/20W
MF
201
90 8
OUT
90 89 6
OUT
89 86
OUT
1
10K
1%
1/20W
MF
201
89 86
2
OUT
86
OUT
89 86
2
OUT
OUT
92 89
OUT
92 89
OUT
92 89
OUT
8
OUT
82
OUT
89 85
CRITICAL
OUT
92 89
OUT
BI
1909782
96 47 45 16 6
BI
96 47 45 16 6
BI
96 47 45 16 6
BI
96 47 45 16 6
BI
M-RT-SM
7
GMUX_JTAG_CONN
=PP3V3_S0_GMUX
JTAG_GMUX_TDO
JTAG_GMUX_TDI
JTAG_GMUX_TMS
4
18 89
JTAG_GMUX_TCK
3
8 89
7 86 89
96 24
89
24
89
8
IN
IN
OUT
LCD_BKLT_EN
LCD_BKLT_PWM
LVDS_DDC_SEL_EG
LVDS_DDC_SEL_IG
DP_MUX_EN
DP_MUX_SEL_EG
EG_RESET_L
EG_RAIL1_EN
EG_RAIL2_EN
EG_RAIL3_EN
EG_RAIL4_EN
EG_CLKREQ_OUT_L
DP_CA_DET_EG
LCD_PWR_EN
LPC_AD & lt; 0 & gt;
LPC_AD & lt; 1 & gt;
LPC_AD & lt; 2 & gt;
LPC_AD & lt; 3 & gt;
LPC_FRAME_L
LPC_RESET_L
LPC_CLK33M_GMUX
GMUX_INT
VCCIO7
VCCIO6
VCCIO5
VCCIO4
10K
1
GMUX_DEBUG_RESET_L
R9680
1K
1
A4
MF
MF
201
1/20W
MF
201
1/20W
MF
201
2
NO STUFF
R9679
1
10K
PB7B
PT7B
A3
PB14A
PB14B
PB15A (OD)
PB15B
PB16A
PB16B
PB17A
PB17B
PB18A
PB18B (OD)
PB19A
PB19B
PB20A
PB20B
PT8A
PT8B
A1
PT9A
C5
P4
N4
N3
M4
P5
M5
P6
M6
P7
M7
N7
N8
P9
N9
CSBGA
M10
PB26A
PB26B
P12
PB27A
P13
N12
B3
PT9B
PB27B
PB28A
P14
PB28B
P10
LVDS_B_DATA_P & lt; 0 & gt;
LVDS_B_DATA_N & lt; 0 & gt;
LVDS_B_DATA_P & lt; 1 & gt;
LVDS_B_DATA_N & lt; 1 & gt;
LVDS_B_DATA_P & lt; 2 & gt;
LVDS_B_DATA_N & lt; 2 & gt;
EG_PWRSEQ_EN
GMUX_DEBUG_RESET_L
LVDS_A_CLK_P
LVDS_A_CLK_N
LVDS_B_CLK_P
LVDS_B_CLK_N
LVDS_A_DATA_P & lt; 0 & gt;
LVDS_A_DATA_N & lt; 0 & gt;
LVDS_A_DATA_P & lt; 1 & gt;
LVDS_A_DATA_N & lt; 1 & gt;
LVDS_A_DATA_P & lt; 2 & gt;
LVDS_A_DATA_N & lt; 2 & gt;
TP_GMUX_PT20A
TP_GMUX_PT20B
TP_GMUX_PT32A
TP_GMUX_PT32B
A2
PB7A
N2
A5
PT14A
PT14B
PT15A
PT15B
PT16A
PT16B
PT17A
PT17B
PT18A
PT18B
PT19A
PT19B
PT20A
PT20B
B6
C7
A6
A7
C8
C9
A8
B9
A9
C10
B10
A10
A11
B12
OUT
5%
1/20W
MF
201
C
2
86 100
OUT
86 100
OUT
86 100
OUT
86 100
OUT
86 100
OUT
Required Pulldowns
89 86
DP_MUX_SEL_EG
R9681
10K
1
2
89 86
LVDS_DDC_SEL_IG
R9682
10K
1
2
89 86
LVDS_DDC_SEL_EG
R9683
10K
1
2
5%
PT28A
B13
PT28B
A13
PR2A
PR2B
A14
B2
PL2A
PL2B
C2
PL6A
PR6A
D12
MF
201
5%
1/20W
MF
201
5%
IN
IN
1/20W
MF
201
5%
1/20W
MF
201
5%
89
OUT
1/20W
1/20W
MF
201
86 100
89
86 100
OUT
86 100
OUT
86 100
OUT
86 100
OUT
86 100
OUT
86 100
OUT
86 100
OUT
86 100
(Use open-drain PGOOD output to hold off the start of the GPU PWRSEQ until the first GPU rail’s source is valid)
NO STUFF
89 8
90 89 6
OUT
R9691
100K
1
2
R9693
100K
1
2
86 100
OUT
EG_RESET_L
LCD_BKLT_PWM
86 100
8
8
92 89
EG_RAIL4_EN
92 89
EG_RAIL3_EN
92 89
EG_RAIL2_EN
8
8
1
LVDS_IG_B_DATA_P & lt; 2 & gt;
LVDS_IG_B_DATA_N & lt; 2 & gt;
89 17
IN
GMUX_PL6A
TP_GMUX_PL6B
6
LVDS_IG_A_DATA_P & lt; 0 & gt;
89 17
IN
LVDS_IG_A_DATA_N & lt; 0 & gt;
89 17
IN
LVDS_IG_A_DATA_P & lt; 1 & gt;
89 17
IN
LVDS_IG_A_DATA_N & lt; 1 & gt;
89 17
IN
LVDS_IG_A_DATA_P & lt; 2 & gt;
89 17
IN
LVDS_IG_A_DATA_N & lt; 2 & gt;
89 17
IN
LVDS_IG_B_DATA_P & lt; 0 & gt;
89 17
IN
LVDS_IG_B_DATA_N & lt; 0 & gt;
89 17
IN
LVDS_IG_B_DATA_P & lt; 1 & gt;
89 17
IN
LVDS_IG_B_DATA_N & lt; 1 & gt;
89 17
IN
LVDS_IG_A_CLK_P
89 17
IN
LVDS_IG_A_CLK_N
89 17
IN
LVDS_MUX_SEL_EG
8
OUT
TP_GMUX_PL14B
=GMUX_PCIE_RESET_L
24
IN
TP_GMUX_PL15B
ALL_EG_PGOOD
8
IN
EG_CLKREQ_IN_L
82 8
IN
1%
1/20W
MF
201
95
95
95
2
95
95
95
95
E12
E3
PL8B
PL9A
PR8B
PR9A
F12
F1
G1
PL9B
PR9B
G14
F3
G2
H2
G3
H1
H3
L1
L3
L2
N1
P1
BANK2
BANK6
K3
PL10A
PL10B
PL11A
PL11B
PL12A
PL12B
PL14A
PL14B
PL15A
PL15B
BANK3
10K
PR8A
PL25A
PL25B
(Tie/strap low if EGPU doesn’t provide CLKREQ_L output, provide pullup to GPU rail if using CLKREQ_L output from EGPU)
GND
ULC_GNDPLL
LRC_GNDPLL
95
PL8A
GNDIO7
95
1
PR7A
PR7B
D2
GNDIO6
R9647
E1
PL7A
PL7B
D14
GNDIO5
NO STUFF
D13
BANK7
95
PR6B
GNDIO3
GNDIO4
95
PL6B
D1
GNDIO2
95
DP_A_CA_DET
DP_HOTPLUG_DET
LVDS_EG_A_DATA_P & lt; 0 & gt;
LVDS_EG_A_DATA_N & lt; 0 & gt;
LVDS_EG_A_DATA_P & lt; 1 & gt;
LVDS_EG_A_DATA_N & lt; 1 & gt;
LVDS_EG_A_DATA_P & lt; 2 & gt;
LVDS_EG_A_DATA_N & lt; 2 & gt;
LVDS_EG_B_DATA_P & lt; 0 & gt;
LVDS_EG_B_DATA_N & lt; 0 & gt;
LVDS_EG_B_DATA_P & lt; 1 & gt;
LVDS_EG_B_DATA_N & lt; 1 & gt;
LVDS_EG_B_DATA_P & lt; 2 & gt;
LVDS_EG_B_DATA_N & lt; 2 & gt;
LVDS_EG_A_CLK_P
LVDS_EG_A_CLK_N
IG_LCD_PWR_EN
EG_LCD_PWR_EN
IG_BKLT_EN
EG_BKLT_EN
B14
D3
GNDIO1
8
B1
IN
GNDIO0
95 89 17
95
B
=PP3V3_S0_GMUX
201
1/20W
5
6
81 89 100
81 89 100
2
89
PT7A
P2
BANK4
J9600
96 47 45 16 6
2
R9686
1/20W
5%
JTAG_GMUX_TDO
U9600
BANK5
89 8
1
81 89 100
2
SILK_PART=GMUX_RST
BANK0
R9641
OMIT
CRITICAL
81 89 100
XP25-5
NO STUFF
R9646 1
CFG0
VCCIO3
K1
L12
VCCIO2
K2
K13
VCCJ
81 89 100
81 89 100
2
JTAG_GMUX_TDI
5%
ULC_VCCPLL
LRC_VCCPLL
89
89 18
L13
VCCIO1
89
2
NO STUFF
VCCAUX
TCK
TDI
TDO
TMS
TOE
K14
BANK1
2
VCCIO0
1%
1/20W
MF
201
JTAG_GMUX_TCK
JTAG_GMUX_TDI
JTAG_GMUX_TDO
JTAG_GMUX_TMS
GMUX_TOE
81 89 100
LVDS_EG_B_DATA_N & lt; 0 & gt;
LVDS_EG_B_DATA_N & lt; 1 & gt;
LVDS_EG_B_DATA_N & lt; 2 & gt;
89 86 7
P11
F2
K12
C3
M1
N5
M3
M9
M12
F13
C14
B7
A12
B5
M8
J2
J14
P8
C11
J3
N11
J13
C4
B11
1%
1/20W
MF
201
89 8
D
17 89 95
201
5%
VCC
1
17 89 95
Required Pullups
89
10K
17 89 95
17 89 95
LVDS_EG_A_CLK_N
LVDS_EG_A_DATA_N & lt; 0 & gt;
LVDS_EG_A_DATA_N & lt; 1 & gt;
LVDS_EG_A_DATA_N & lt; 2 & gt;
201
5%
R9640
17 89 95
201
SIGNAL_MODEL=EMPTY
10%
6.3V
X5R
201
89
10K
17 89 95
LVDS_IG_B_DATA_N & lt; 0 & gt;
LVDS_IG_B_DATA_N & lt; 1 & gt;
LVDS_IG_B_DATA_N & lt; 2 & gt;
201
PLACE_NEAR=U9600.G14:5mm
1%
1/20W
MF
201
PLACE_NEAR=U9600.G13:5mm
1%
1/20W
MF
201
PLACE_NEAR=U9600.H12:5mm
1/20W
MF
201
1%
=PP3V3_S0_GMUX
R9645 1
17 89 95
201
PLACE_NEAR=U9600.J12:5mm
1%
1/20W
MF
PLACE_NEAR=U9600.D13:5mm
1%
1/20W
MF
PLACE_NEAR=U9600.E14:5mm
1%
1/20W
MF
PLACE_NEAR=U9600.F12:5mm
1%
1/20W
MF
2
1
89
89 86 7
LVDS_IG_A_CLK_N
LVDS_IG_A_DATA_N & lt; 0 & gt;
LVDS_IG_A_DATA_N & lt; 1 & gt;
LVDS_IG_A_DATA_N & lt; 2 & gt;
201
PLACE_NEAR=U9600.G2:5mm
1%
1/20W
MF
PLACE_NEAR=U9600.G3:5mm
1%
1/20W
MF
PLACE_NEAR=U9600.B2:5mm
1%
1/20W
MF
2
100
100
0.1UF
C9600
1
PLACE_NEAR=U9600.H3:5mm
1%
1/20W
MF
PLACE_NEAR=U9600.E1:5mm
1%
1/20W
MF
PLACE_NEAR=U9600.E3:5mm
1%
1/20W
MF
PLACE_NEAR=U9600.G1:5mm
1%
1/20W
MF
0402
1
0.1UF
10%
6.3V
X5R
201
2
1
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.09 mm
VOLTAGE=3.3V
C9617
0.1UF
10%
6.3V
X5R
201
PP3V3_S0_GMUX_ULC_VCCPLL
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.09 mm
VOLTAGE=1.8V
FERR-220-OHM
7
1
E14
F14
PR10A
PR10B
PR11A
PR11B
PR12A
PR12B
PR14A
PR14B
G12
PR24A
PR24B
N14
G13
H13
H12
H14
J12
L14
M13
N13
7
IN
87
IN
86
IN
81 89 100
IN
IN
81 89 100
IN
81 89 100
IN
81 89 100
IN
81 89 100
IN
81 89 100
IN
81 89 100
IN
81 89 100
IN
81 89 100
IN
81 89 100
IN
81 89 100
IN
81 89 100
IN
81 89 100
IN
EG_RAIL1_EN
5%
1/20W
MF
201
B
4.7K
1
89 85
LCD_PWR_EN
5%
1/20W
MF
2 201
R9672
4.7K
1
5%
1/20W
MF
2 201
R9671
4.7K
IN
1
R9678
4.7K
5%
1/20W
MF
201
5%
1/20W
MF
2 201
2
8
IN
82
GMUX_S3_PD_GND
=PP3V3_S3_GMUX
SSM6N37FEAPE
D
3
NO STUFF
Q9607
1
1
R9675
SOT563
R9676
M11
B4
E2
C1
M2
P3
N6
N10
M14
E13
C13
C6
B8
C12
2
82
92 89
0
100K
J1
R9673
8
IN
4.7K
1
81 89 100
R9674
2
5%
1/20W
MF
5%
1/20W
MF
201
5
G
S
2 201
4
GMUX_S3_PD_EN
A
JTAG_GMUX_TDI
JTAG_GMUX_TDO
89
SYNC_MASTER=K91_MARY
89
D
SSM6N37FEAPE
D
D
3
SOT563
2
R9605
1
1K
2
5%
1/20W
MF
201
8
S
5
1
G
S
4
92 74 45 23
IN
G
S
JTAG_ISP_TDI
19 8
R
NOTICE OF PROPRIETARY PROPERTY:
ALL_SYS_PWRGD
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
JTAG_ISP_TDO
6
5
4
051-9585
3
2
SIZE
D
REVISION
3.0.0
1
T29_JTAG_FET
19 8
7
G
DRAWING NUMBER
Apple Inc.
SOT563
2
=PP3V3_T29_JTAG
Graphics MUX (GMUX)
Q9605
SOT563
7
6
Q9607
SSM6N37FEAPE
6
Q9605
SYNC_DATE=08/03/2010
PAGE TITLE
SSM6N37FEAPE
BRANCH
PAGE
96 OF 132
SHEET
89 OF 105
1
A
8
7
6
5
4
3
2
1
PPBUS S0 LCDBkLT FET
MOSFET
43 mOhm @4.5V
LOADING
Q9706
P-TYPE
RDS(ON)
CRITICAL
FDC638APZ
CHANNEL
0.715 A (EDP)
FDC638APZ_SBMS001
SSOT6-HF
5
R9788
BOTTOM
C9782
10%
16V
X5R
402
1%
1/16W
MF-LF
402
ON THE SENSOR PAGE
*PPBUS_SW_LCDBKLT_PWR_SW SHOULD BE KEPT AS SHORT AS POSSIBLE.
*LCD_BKLT_PWM SHOULD BE AWAY FROM BOOST CIRCUIT
1
7
PLACE_NEAR=L9701.2:3mm
=PP5V_S0_BKL
CRITICAL
2
CRITICAL
L9701
D9701
33UH-1.8A-110MOHM
LCDBKLT_EN_DIV
104 7
1
D
*C9797 AND C9799 SHOULD BE PLACED IN T-BONE FOR ACOUSTICS
AND PPBUS_SW_BKL
0.1UF
301K
2
2
PPBUS_S0_LCDBKLT_FUSED
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.6V
1
603-HF
1
=PPBUS_S0_LCDBKLT
90 104
THERE IS A SENSE RESISTOR BETWEEN
PPBUS_SW_LCDBKLT_PWR
3
7
2
4
D
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.6V
6
F9700
3AMP-32V-467
1
PPBUS_SW_LCDBKLT_PWR
1
=PPBUS_SW_BKL
CRITICAL
C9712
R9789
10%
25V
X5R
805
SOD-123
C9713
0.1UF
1
1
2
2
PLACE_NEAR=L9701.1:4mm
A
PPBUS_SW_LCDBKLT_PWR_SW
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=40V
SWITCH_NODE=TRUE
DIDT=TRUE
1217AS-2SM
10UF
147K
1%
1/16W
MF-LF
2 402
2
10%
25V
X5R
402
K
PLACE_NEAR=U9701.A5:3mm
PPVOUT_SW_LCDBKLT
CRITICAL
RB160M-60G
1
C9796
1
220PF
2
PLACE_NEAR=L9701.1:3mm
C9797
CRITICAL
1
10UF
10%
50V
X7R-CERM
402
2
C9799
8
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=50V
10UF
10%
50V
X5R
1210-1
2
10%
50V
X5R
1210-1
PLACE_NEAR=D9701.2:5mm
LCDBKLT_EN_L
PLACE_NEAR=D9701.2:3mm
Q9707
D
3
SSM6N15AFE
SOT563
PLACE_NEAR=U9701.D1:5mm
PLACE_NEAR=U9701.D1:3mm
C9710
1
1
1UF
5
89 8
IN
G
S
10%
25V
X5R
603-1
4
LCD_BKLT_EN
LCDBKLT_DISABLE
Q9707
D
XW9720
C9714
SM
0.01UF
2
2
PPVOUT_SW_LCDBKLT_FB
10%
16V
CERM
402
1
2
VOLTAGE=40V
PLACE_NEAR=C9797.1:5mm
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.25 MM
6
7
SSM6N15AFE
=PP3V3_S0_BKL_VDDIO
SOT563
PLACE_NEAR=U9701.C4:4mm
C
C9711
C
1
0.1UF
IN
S
10%
16V
X5R
402
1
BKLT_PLT_RST_L
2
10K
C4
R9755
1
C1
24
G
D1
2
2
VIN
VDDIO VLDO
MIN_LINE_WIDTH=0.075 mm
MIN_NECK_WIDTH=0.075 mm
5%
1/16W
MF-LF
402
U9701
25-BUMP-MICRO
1
IN
BI
=I2C_BKL_1_SDA
BKL_FSET
2
B3
B4
SW_0
SW_1
ISET
FSET
B1
BKLT:PROD
B2
R9717
FB
PLACE_NEAR=U9701.E5:10mm
A5
1
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
MIN_LINE_WIDTH=0.075 mm
MIN_NECK_WIDTH=0.075 mm
R9731
1%
1/16W
MF-LF
402
R9704
1
33
2
5%
1/16W
MF-LF
402
1
2
6
R9715
A4
PWM
A3
EN
D4
C3
TP_BKL_FAULT
SCLK
SDA
1%
1/16W
MF-LF
1 402
MIN_LINE_WIDTH=0.075 mm
MIN_NECK_WIDTH=0.075 mm
MIN_LINE_WIDTH=0.075 mm
MIN_NECK_WIDTH=0.075 mm
C9704
D5
E3
OUT6
CRITICAL
E5
OUT2
OUT3
FAULT
PLACE_SIDE=BOTTOM
100K
OUT1
OUT4
OUT5
B5
LCD_BKLT_PWM
BKL_PWM
BKL_EN
2
D3
E1
C5
E2
BKL_ISEN1
BKL_ISEN2
BKL_ISEN3
BKL_ISEN4
BKL_ISEN5
BKL_ISEN6
BOTTOM
1
90.9K
Fpwm=9.62kHz
see spec for others
1%
1/16W
MF-LF
402 2
1
OUT
6 85
0
2
LED_RETURN_2
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
OUT
6 85
OUT
6 85
OUT
6 85
OUT
6 85
OUT
6 85
BKLT:PROD
B
R9719
PLACE_NEAR=U9701.C5:10mm
1
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
I_LED=22.7mA
R9716
LED_RETURN_1
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
5%
1/16W
MF-LF
402
0
2
LED_RETURN_3
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
5%
1/16W
MF-LF
402
BOTTOM
5%
50V
CERM
402
2
R9718
1
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
33PF
2
0
5%
1/16W
MF-LF
402
BKLT:PROD
PLACE_NEAR=U9701.D5:10mm
GND_SW
GND_SW
1
301K
B
BKL_SCL
BKL_SDA
MIN_NECK_WIDTH=0.075 mm
MIN_LINE_WIDTH=0.075 mm
A2
2
GND_L
0
PPBUS_SW_LCDBKLT_PWR
IN
FILTER
A1
1
5%
1/16W
MF-LF
402
89 6
C2
E4
5%
1/16W
MF-LF
402
R9757
104 90
BKL_ISET
VSYNC
BOTTOM
Addr: 0x58(Wr)/0x59(Rd)
48
0
BKL_FLTR
D2
GND_S
48
1
2
5%
1/16W
MF-LF
402
R9753
=I2C_BKL_1_SCL
10K
MIN_LINE_WIDTH=0.075 mm
MIN_NECK_WIDTH=0.075 mm
LP8550
BKL_VSYNC_R
R9741
BKLT:PROD
R9714
R9720
16.2K
0
PLACE_NEAR=U9701.E3:10mm
1%
1/16W
MF-LF
2 402
1
PLACEMENT_NOTE=Keep away from noise nodes(E4, A1, A2, B1, B2 pins)
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
XW9710
SM
GND_BKL_SGND
1
2
BOTTOM
LED_RETURN_4
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
5%
1/16W
MF-LF
402
2
BKLT:PROD
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=0V
R9721
0
PLACE_NEAR=U9701.E2:10mm
I_LED=369/Riset
(EEPROM should set EN_I_RES=1)
1
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
2
BOTTOM
LED_RETURN_5
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
5%
1/16W
MF-LF
402
BKLT:PROD
R9722
0
PLACE_NEAR=U9701.E1:10mm
1
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
BOTTOM
A
PART NUMBER
103S0198
103S0198
QTY
DESCRIPTION
REFERENCE DES
CRITICAL
BOM OPTION
3 RES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM R9717,R9718,R9719
BKLT:ENG
3 RES,THIN FLIM,1/16W,10.2 OHM,0.1,0402,SM R9720,R9721,R9722
BKLT:ENG
2
5%
1/16W
MF-LF
402
LED_RETURN_6
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
SYNC_MASTER=J31_KIRAN
10.2 ohm resistors for current
measurement on LED strings.
SYNC_DATE=03/21/2011
PAGE TITLE
LCD Backlight Driver
DRAWING NUMBER
Apple Inc.
051-9585
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
3.0.0
BRANCH
PAGE
97 OF 132
SHEET
90 OF 105
1
A
8
7
6
5
4
3
2
1
D
D
PCH VCCIO (1.05V S0) REGULATOR
C
C
=PPPCHVCCIO_S0_REG
7
Vout = 1.05V
CRITICAL
C9849
1
270UF
20%
2V 2
TANT
CASE-B4-SM
12A MAX OUTPUT
f = 300 kHz
CRITICAL
1
C9848
270UF
2
B
A
20%
2V
TANT
CASE-B4-SM
B
SYNC_MASTER=J31_JACK
SYNC_DATE=09/16/2011
PAGE TITLE
PCH VCCIO (1.05V) POWER SUPPLY
DRAWING NUMBER
Apple Inc.
051-9585
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
3.0.0
BRANCH
PAGE
98 OF 132
SHEET
91 OF 105
1
A
8
7
6
5
4
3
2
1
PCH S0 PWRGD
GPU Rail Sequencing
7
KEPLER GPU REQUIRES RAILS TO COME
up in the following order:
24 7
=PP3V3_S5_PCHPWRGD
=PP3V3_S0_SB_PM
1) GPU_3.3V
2) IFPX IOVDD - 1.8V
D
R9950
3) GPUVCORE
5) PEXVDD/Q
5%
1/16W
MF-LF
402
OR IFPY IOVDD - 1.05V
EG_RAIL1_EN
P3V3GPU_EN
C9950
OUT
MAKE_BASE=TRUE
P1V8GPU_EN
EG_RAIL2_EN
=P1V8GPU_EN
OUT
MAKE_BASE=TRUE
89 74 45 23
IN
ALL_SYS_PWRGD
1
74LVC2G08GT
SOT833
A
U9950 Y
73
69
IN
20%
10V
CERM
402
2
8
73
D
0.1UF
2
=P3V3GPU_EN
89
89
1
1
1K
4) FBVDDQ/GDDR5 1.35V
2
CPUIMVP_PGOOD
B
7
PM_S0_PGOOD
NC
08
8
4
EG_RAIL3_EN
GPUVCORE_EN
5
=GPUVCORE_EN
89
OUT
MAKE_BASE=TRUE
84
PLACE_NEAR=U1800.p12:7mm
74LVC2G08GT
SOT833
U9950 Y 3
6
R9962
A
B
1K
SYS_PWROK_R
1
4
89
R9931
0
1
92 46 45 35
P1V35FB_EN
2
MAKE_BASE=TRUE
1
=P1V35FB_EN
OUT
1/20W
MF
78
201
P1V05GPU_EN
2
SMC_DELAYED_PWRGD
78
OUT
MAKE_BASE=TRUE
5%
R9932
20
17 23 45
OUT
NC
EG_RAIL4_EN
P1V35FB1V05GPU_R_EN
PM_PCH_SYS_PWROK
2
5%
1/16W
MF-LF
402
08
=P1V05_GPU_EN
MAKE_BASE=TRUE
ALL_SYS_PWRGD-- & gt;
SMC delayed 99 ms
-- & gt; SMC_DELAYED_PWRGD
5%
1/20W
1
MF
201
C9932
1
0.47UF
2
10%
6.3V
CERM-X5R
C9931
0.47UF
2
10%
6.3V
CERM-X5R
402
402
PM_PCH_PWROK
C
OUT
MAKE_BASE=TRUE
C
17 24
R9960
92 46 45 35
0
SMC_DELAYED_PWRGD
1
PM_PCH_APWROK
2
17
5%
1/16W
MF-LF
402
Unused PGOOD signal
PCIE TEST STRUCTURES (FOR LAB USE)
92 74 7
PEG_R2D_P & lt; 0 & gt;
=PP3V3_S0_PWRCTL
NO STUFF
PEG_R2D_P & lt; 5 & gt;
6 75 93
6 75 93
R9991 1
EXT GPU PWRGD Pullup
PLACE_NEAR=U8000.AN12:10MM
1
=PP3V3_S0_PWRCTL
1
R9910
82
92 74 7
82
5%
5%
R9990
2
1
CPUIMVP_AXG_PGOOD
2
1
GPUVCORE_PGOOD
5%
R9901
0
PEG_R2D_N & lt; 0 & gt;
PEG_R2D_N & lt; 5 & gt;
6 75 93
1/20W
402
MF
TP_P1V5S3RS0_RAMP_DONE
GPUFB_PGOOD
1
5%
MAKE_BASE=TRUE
PEG_R2D_P & lt; 3 & gt;
201
PEG_R2D_P & lt; 7 & gt;
6 75 93
PLACE_NEAR=U8000.AN15:10MM
MF
1
GPUFB_PGOOD_R
2
1/20W
PLACE_NEAR=U8000.AN20:10MM
1
R9913
82
201
PM_ALL_GPU_PGOOD
R9903
0
5%
IN
P1V05_S0GPU_PGOOD
1
MAKE_BASE=TRUE
1/20W
MF
8
2
201
P1V05_S0GPU_PGOOD_R
NO STUFF
C9905
MF
201
NOSTUFF
2
1
5%
1/20W
MF
OUT
R9917
82
5%
1/20W
78
B
2
6 75 93
IN
73
GPUVCORE_PGOOD_R
R9902
0
78
IN
MAKE_BASE=TRUE
6 75 93
MF-LF
2
68
P1V5S3RS0_RAMP_DONE
TP_DDRREG_PGOOD
NOSTUFF
5%
IN
69
IN
201
1/16W
84
IN
DDRREG_PGOOD
MF
201
NOSTUFF
100K
2
1/20W
MF
B
5%
1/16W
MF-LF
402
R9915
1/20W
PLACE_NEAR=U8000.AH16:7mm
10K
PLACE_NEAR=U8000.AP17:10MM
2
201
NOSTUFF
PEG_R2D_N & lt; 3 & gt;
PEG_R2D_N & lt; 7 & gt;
6 75 93
6 75 93
0.001UF
2
20%
50V
PLACE R9910 - R9917 CLOSE TO U8000
CERM
402
A
SYNC_MASTER=J31_SREE
SYNC_DATE=09/19/2011
PAGE TITLE
Power Sequencing EG/PCH S0
DRAWING NUMBER
Apple Inc.
051-9585
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
3.0.0
BRANCH
PAGE
99 OF 132
SHEET
92 OF 105
1
A
8
7
6
5
CPU Signal Constraints
4
3
2
1
CPU Net Properties
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
CPU_50S
*
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
NET_TYPE
DIFFPAIR NECK GAP
=STANDARD
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
SPACING
TABLE_PHYSICAL_RULE_ITEM
DMI_S2N
PCIE_85D
PCIE
DMI_S2N
PCIE_85D
PCIE
DMI_N2S
PCIE_85D
PCIE
DMI_N2S
PCIE_85D
PCIE
FDI_DATA
PCIE_85D
PCIE
FDI_DATA
PCIE_85D
PCIE
FDI_FSYNC
CPU_50S
CPU_AGTL
FDI_LSYNC
CPU_50S
CPU_AGTL
TABLE_PHYSICAL_RULE_ITEM
CPU_55S
*
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
TABLE_PHYSICAL_RULE_ITEM
CPU_27P4S
*
=27P4_OHM_SE
=27P4_OHM_SE
=27P4_OHM_SE
=27P4_OHM_SE
7 MIL
7 MIL
NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target impedance.
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
TABLE_SPACING_RULE_HEAD
WEIGHT
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
6 9 17
6 9 17
6 9 17
6 9 17
6 9 17
6 9 17
6 9 17
FDI_INT
CPU_AGTL
*
=STANDARD
*
8 MIL
CPU_AGTL
TOP,BOTTOM
=2x_DIELECTRIC
*
0.457 MM
20 MIL
=2:1_SPACING
DMI_CLK100M_CPU_P
10 16
CLK_PCIE_90D
CLK_PCIE
DMI_CLK100M_CPU_N
10 16
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_INT_IG_ML_P & lt; 3:0 & gt;
DP_INT_IG_ML_N & lt; 3:0 & gt;
DP_85D
DISPLAYPORT
6 9 17
D
6 9 17
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
?
*
CLK_PCIE
I126
?
TABLE_SPACING_RULE_ITEM
*
CLK_PCIE_90D
DMI_CLK100M
?
CPU_VID
TABLE_SPACING_RULE_ITEM
CPU_ITP
CPU_AGTL
DMI_CLK100M
I128
?
CPU_COMP
CPU_50S
I125
TABLE_SPACING_RULE_ITEM
?
CPU_8MIL
FDI_LSYNC & lt; 1..0 & gt;
FDI_INT
I127
TABLE_SPACING_RULE_ITEM
D
DMI_S2N_P & lt; 3:0 & gt;
DMI_S2N_N & lt; 3:0 & gt;
DMI_N2S_P & lt; 3:0 & gt;
DMI_N2S_N & lt; 3:0 & gt;
FDI_DATA_P & lt; 7:0 & gt;
FDI_DATA_N & lt; 7:0 & gt;
FDI_FSYNC & lt; 1..0 & gt;
?
CPU_VREF
*
12 MIL
?
TABLE_SPACING_RULE_ITEM
8 9
8 9
TABLE_SPACING_RULE_ITEM
CPU_VCCSENSE
*
25 MIL
?
I129
I131
DP_85D
DISPLAYPORT
CPU_EDP_COMP
CPU_27P4S
CPU_COMP
I130
CPU_PEG_COMP
CPU_27P4S
CPU_COMP
I133
CPU_CFG
CPU_50S
CPU_ITP
XDP_CLK_CPU
CLK_PCIE_90D
CLK_PCIE
XDP_CLK_CPU
CLK_PCIE_90D
CLK_PCIE
XDP_CLK_PCH
CLK_PCIE_90D
CLK_PCIE
XDP_CLK_PCH
SOURCE: IVB PLATFORM DG , Tables 205-207
DP_INT_AUX
I132
Most CPU signals with impedance requirements are 50-ohm single-ended.
Some signals require 27.4-ohm single-ended impedance.
DP_INT_AUX
CLK_PCIE_90D
CLK_PCIE
PCI-Express
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM
PCIE_85D
*
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
CLK_PCIE_90D
*
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
I138
TABLE_PHYSICAL_RULE_ITEM
DPLL_REF_CLK120M
CLK_PCIE_90D
CLK_PCIE
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
CLK_PCIE_90D
CLK_PCIE
CPU_50S
CPU_ITP
XDP_TDO
TABLE_SPACING_RULE_HEAD
DPLL_REF_CLK120M
XDP_TDI
I139
CPU_50S
CPU_ITP
TABLE_SPACING_RULE_HEAD
WEIGHT
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
CPU_50S
CPU_ITP
XDP_BPM
CPU_50S
CPU_ITP
CPU_50S
CPU_ITP
XDP_BDRESET_L
CPU_50S
CPU_ITP
I135
XDP_PRDY_L
CPU_50S
CPU_ITP
I136
XDP_PREQ_L
CPU_50S
CPU_ITP
CPU_CATERR_L
CPU_50S
CPU_AGTL
CPU_PROC_SEL_L
CPU_50S
CPU_AGTL
CPU_PECI
CPU_50S
CPU_VID
CPU_PROCHOT_L
CPU_50S
CPU_AGTL
XDP_CPU_PWRGD
15 MIL
CPU_ITP
CPU_ITP
I134
*
CPU_50S
CPU_50S
XDP_BPM_L
PCIE
XDP_TMS
XDP_TCK
XDP_TRST_L
TABLE_SPACING_RULE_ITEM
CPU_50S
CPU_ITP
TABLE_SPACING_RULE_ITEM
?
PCIE
TOP,BOTTOM
15 MIL
?
TABLE_SPACING_RULE_ITEM
CLK_PCIE
*
?
20 MIL
C
I115
PEG
PM_THRMTRIP_L
CPU_50S
CPU_8MIL
PM_SYNC
CPU_50S
CPU_AGTL
PM_MEM_PWRGD
CPU_50S
CPU_AGTL
CPU_PWRGD
CPU_50S
CPU_AGTL
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM
PEG_80D
*
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
I150
CPU_SM_RCOMP
DP_INT_IG_AUX_P
DP_INT_IG_AUX_N
CPU_EDP_COMP
CPU_PEG_COMP
CPU_CFG & lt; 17..0 & gt;
ITPCPU_CLK100M_P
ITPCPU_CLK100M_N
ITPXDP_CLK100M_P
ITPXDP_CLK100M_N
DPLL_REF_CLKP
DPLL_REF_CLKN
XDP_CPU_TDI
XDP_CPU_TDO
XDP_CPU_TMS
XDP_CPU_TCK
XDP_CPU_TRST_L
XDP_BPM_L & lt; 3..0 & gt;
XDP_BPM_L & lt; 7..4 & gt;
XDP_DBRESET_L
XDP_CPU_PRDY_L
XDP_CPU_PREQ_L
CPU_CATERR_L
CPU_PROC_SEL_L
CPU_PECI
CPU_PROCHOT_L
XDP_CPU_PWRGD
PM_THRMTRIP_L
PM_SYNC
PM_MEM_PWRGD
CPU_PWRGD
CPU_SM_RCOMP & lt; 2..0 & gt;
8 9
8 9
9
9
9 23
10 16
10 16
16 23
16 23
8
8
10 23
10 23
10 23
10 23
10 23
10 23
10 23
10 23 24
10 23
C
10 23
10 45
10 19
10 19 46
10 45 46 69
23
10 19 46
10 17
10 17 26
10 19 23
CPU_27P4S
CPU_COMP
CPU_50S
CPU_VID
CPU_VIDSOUT
12 69
CPU_50S
CPU_VID
CPU_VIDSCLK
12 69
CPU_50S
CPU_VID
CPU_VIDALERT_L
12 69
CPU_VID
CPU_VCCSA_VID & lt; 1..0 & gt;
12 66
10
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_ITEM
PEG_RXRX
*
=3X_DIELECTRIC
CPU_55S
?
SENSE_DIFFPAIR
SENSE_1TO1_55S
SENSE
SENSE_DIFFPAIR
SENSE_1TO1_55S
SENSE
CPU_VCCSENSE_P
CPU_VCCSENSE_N
SENSE_DIFFPAIR
SENSE_1TO1_55S
SENSE
CPU_VCCIOSENSE_P
SENSE_DIFFPAIR
SENSE_1TO1_55S
SENSE
CPU_VCCIOSENSE_N
12 71
SENSE_DIFFPAIR
SENSE_1TO1_55S
SENSE
CPU_AXG_SENSE_P
12 69
TABLE_SPACING_RULE_ITEM
PEG_TXTX
*
=3X_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
PEG_TXRX
*
=10X_DIELECTRIC
12 69
12 69
12 71
?
SENSE_DIFFPAIR
SENSE_1TO1_55S
SENSE
CPU_AXG_SENSE_N
12 69
I120
SENSE_DIFFPAIR
SENSE_1TO1_55S
SENSE
CPU_VCC_VALSENSE_P
12
I121
SENSE_DIFFPAIR
SENSE_1TO1_55S
SENSE
CPU_VCC_VALSENSE_N
12
I122
SENSE_DIFFPAIR
SENSE_1TO1_55S
SENSE
CPU_AXG_VALSENSE_P
12
I123
SENSE_DIFFPAIR
SENSE_1TO1_55S
I137
CPU_VCCSASENSE
CPU_50S
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
B
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM
PEG_D2R
PEG_D2R
*
CPU_AXG_VALSENSE_N
12
CPU_AGTL
CPU_VCCSASENSE
12 66
PPCPU_MEM_VREFDQ_A
PPCPU_MEM_VREFDQ_B
SENSE
B
PEG_RXRX
TABLE_SPACING_ASSIGNMENT_ITEM
PEG_R2D
PEG_R2D
*
PEG_TXTX
PEG_D2R
PEG_R2D
*
PEG_TXRX
I140
CPU_MEM_VREF
CPU_VREF
I141
CPU_MEM_VREF
CPU_VREF
I144
CPU_MEM_VREF
CPU_VREF
I145
CPU_MEM_VREF
CPU_VREF
I146
CPU_MEM_VREF
CPU_VREF
I147
CPU_MEM_VREF
CPU_VREF
I148
XDP_CLK_ITP
CLK_PCIE_90D
CLK_PCIE
I149
TABLE_SPACING_ASSIGNMENT_ITEM
XDP_CLK_ITP
CLK_PCIE_90D
CLK_PCIE
PEG_80D
PEG_R2D
PEG_80D
PEG_D2R
PEG_80D
PEG_D2R
PEG_80D
PEG_D2R
PEG_80D
A
PEG_R2D
PEG_80D
PEG_D2R
PEG_R2D
PEG_80D
PEG_R2D
PEG_R2D
PEG_80D
PEG_D2R
PP0V75_S3_MEM_VREFDQ_A
PP0V75_S3_MEM_VREFDQ_B
PP0V75_S3_MEM_VREFCA_A
PP0V75_S3_MEM_VREFCA_B
XDP_CPU_CLK100M_P
XDP_CPU_CLK100M_N
PEG_R2D_P & lt; 7..0 & gt;
PEG_R2D_N & lt; 7..0 & gt;
PEG_R2D_C_P & lt; 7..0 & gt;
PEG_R2D_C_N & lt; 7..0 & gt;
PEG_D2R_P & lt; 7..0 & gt;
PEG_D2R_N & lt; 7..0 & gt;
PEG_D2R_C_P & lt; 7..0 & gt;
PEG_D2R_C_N & lt; 7..0 & gt;
9 31
9 31
27 31
29 31
27 31
29 31
23
23
6 75 92
6 75 92
8 75
8 75
8 75
8 75
6 75
6 75
SYNC_MASTER=K92_MLB
SYNC_DATE=08/09/2010
PAGE TITLE
CPU Constraints
DRAWING NUMBER
Apple Inc.
051-9585
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
3.0.0
BRANCH
PAGE
100 OF 132
SHEET
93 OF 105
1
A
8
7
6
5
Memory Bus Constraints
4
3
2
1
Memory Net Properties
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
MEM_37S
*
=37_OHM_SE
=37_OHM_SE
=37_OHM_SE
=37_OHM_SE
=STANDARD
NET_TYPE
DIFFPAIR NECK GAP
=STANDARD
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
SPACING
TABLE_PHYSICAL_RULE_ITEM
MEM_A_CLK
MEM_72D
MEM_CLK
MEM_A_CLK
MEM_72D
MEM_CLK
MEM_A_CNTL
MEM_37S
MEM_CTRL
MEM_A_CNTL
MEM_37S
MEM_CTRL
MEM_A_CNTL
MEM_37S
MEM_CTRL
MEM_A_CMD
MEM_40S
MEM_CMD
MEM_A_CMD
MEM_40S
MEM_CMD
MEM_A_CMD
MEM_40S
MEM_CMD
MEM_A_CMD
MEM_40S
MEM_CMD
MEM_A_CMD
MEM_40S
MEM_CMD
TABLE_PHYSICAL_RULE_ITEM
MEM_40S
*
=40_OHM_SE
=40_OHM_SE
=40_OHM_SE
=40_OHM_SE
=STANDARD
=STANDARD
MEM_A_CLK_P & lt; 5..0 & gt;
MEM_A_CLK_N & lt; 5..0 & gt;
6 11 27
6 11 27
TABLE_PHYSICAL_RULE_ITEM
MEM_72D
*
=72_OHM_DIFF
=72_OHM_DIFF
=72_OHM_DIFF
=72_OHM_DIFF
=72_OHM_DIFF
=72_OHM_DIFF
MEM_50S
*
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
TABLE_PHYSICAL_RULE_ITEM
MEM_A_CKE & lt; 3..0 & gt;
MEM_A_CS_L & lt; 3..0 & gt;
MEM_A_ODT & lt; 3..0 & gt;
6 11 27
6 11 27
6 11 27
TABLE_PHYSICAL_RULE_ITEM
MEM_85D
D
*
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_ITEM
MEM_CLK2MEM
*
=4:1_SPACING
?
MEM_A_A & lt; 15..0 & gt;
MEM_A_BA & lt; 2..0 & gt;
MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L
6 11 27
6 11 27
D
6 11 27
6 11 27
6 11 27
TABLE_SPACING_RULE_ITEM
MEM_CTRL2CTRL
*
=3:1_SPACING
?
MEM_CTRL2MEM
*
=2.5:1_SPACING
?
MEM_A_DQ_BYTE0
MEM_50S
MEM_DATA
MEM_A_DQ_BYTE1
MEM_50S
MEM_DATA
MEM_A_DQ_BYTE2
MEM_50S
MEM_DATA
MEM_A_DQ_BYTE3
MEM_50S
MEM_DATA
MEM_A_DQ_BYTE4
MEM_50S
MEM_DATA
MEM_A_DQ_BYTE5
MEM_50S
MEM_DATA
MEM_A_DQ_BYTE6
MEM_50S
MEM_DATA
MEM_A_DQ_BYTE7
MEM_50S
MEM_DATA
MEM_A_DQS0
MEM_85D
MEM_DQS
MEM_A_DQS0
MEM_85D
MEM_DQS
MEM_A_DQS1
MEM_85D
MEM_DQS
MEM_A_DQS1
MEM_85D
MEM_DQS
MEM_A_DQS2
MEM_85D
MEM_DQS
MEM_A_DQS2
MEM_85D
MEM_DQS
MEM_A_DQS3
MEM_85D
MEM_DQS
MEM_A_DQS3
MEM_85D
MEM_DQS
MEM_A_DQS4
MEM_85D
MEM_DQS
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
MEM_CMD2CMD
*
=1.5:1_SPACING
?
TABLE_SPACING_RULE_ITEM
MEM_CMD2MEM
*
=3:1_SPACING
?
TABLE_SPACING_RULE_ITEM
MEM_DATA2DATA
*
=1.5:1_SPACING
?
TABLE_SPACING_RULE_ITEM
MEM_DATA2MEM
*
=3:1_SPACING
?
MEM_A_DQ & lt; 7..0 & gt;
MEM_A_DQ & lt; 15..8 & gt;
MEM_A_DQ & lt; 23..16 & gt;
MEM_A_DQ & lt; 31..24 & gt;
MEM_A_DQ & lt; 39..32 & gt;
MEM_A_DQ & lt; 47..40 & gt;
MEM_A_DQ & lt; 55..48 & gt;
MEM_A_DQ & lt; 63..56 & gt;
6 11 28
6 11 28
6 11 28
6 11 28
6 11 28
6 11 28
6 11 28
6 11 28
TABLE_SPACING_RULE_ITEM
MEM_DQS2MEM
*
=3:1_SPACING
?
MEM_2OTHER
*
25 MILS
?
TABLE_SPACING_RULE_ITEM
Memory Bus Spacing Group Assignments
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_CMD
MEM_*
*
MEM_CMD2MEM
MEM_CMD
MEM_CMD
*
MEM_CMD2CMD
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CLK
MEM_*
*
MEM_CLK2MEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CTRL
MEM_*
*
MEM_CTRL2MEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_DATA
MEM_*
*
MEM_DATA2MEM
TABLE_SPACING_ASSIGNMENT_ITEM
C
MEM_CTRL
MEM_CTRL
*
MEM_CTRL2CTRL
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_DATA
MEM_DATA
*
MEM_DATA2DATA
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_DQS
MEM_*
*
MEM_DQS2MEM
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_*
*
*
MEM_2OTHER
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_85D
MEM_DQS
MEM_A_DQS5
MEM_85D
MEM_DQS
MEM_A_DQS5
MEM_85D
MEM_DQS
MEM_A_DQS6
MEM_85D
MEM_DQS
MEM_A_DQS6
MEM_85D
MEM_DQS
MEM_A_DQS7
MEM_85D
MEM_DQS
MEM_A_DQS7
MEM_85D
MEM_DQS
MEM_B_CLK
MEM_72D
MEM_CLK
MEM_B_CLK
MEM_72D
MEM_CLK
MEM_B_CNTL
MEM_37S
MEM_CTRL
MEM_B_CNTL
MEM_37S
MEM_CTRL
MEM_B_CNTL
MEM_37S
MEM_CTRL
MEM_B_CMD
MEM_40S
MEM_CMD
MEM_B_CMD
MEM_40S
MEM_CMD
MEM_B_CMD
MEM_40S
MEM_CMD
MEM_B_CMD
MEM_40S
MEM_CMD
DDR3:
MEM_B_CMD
MEM_40S
MEM_CMD
DQ/DM signals should be matched within 0.508mm of associated DQS pair.
DQS intra-pair matching should be within 0.127mm, no inter-pair matching requirement.
DQS to clock matching should be within [CLK-12.7mm] and [CLK+25.4mm].
CLK intra-pair matching should be within 0.127mm, inter-pair matching should be within 0.508mm.
CONTROL signals should be matched within [CLK-12.7mm] to [CLK+0.0mm] of CLK pairs.
A/BA/CMD signals should be matched within [CLK-12.7mm] to [CLK+12.7mm] of CLK pairs.
DQ/DQS/A/BA/cmd signal spacing is 4x dielectric, CLK is 5x dielectric.
Maximum length of any signal from die pad to SODIMM pad is 139.7mm, from procesor ball to SODIMM pad is 114.3mm.
MEM_B_DQ_BYTE0
MEM_50S
MEM_DATA
MEM_B_DQ_BYTE1
MEM_50S
MEM_DATA
MEM_B_DQ_BYTE2
MEM_50S
MEM_DATA
MEM_B_DQ_BYTE3
MEM_50S
MEM_DATA
MEM_B_DQ_BYTE4
MEM_50S
MEM_DATA
MEM_B_DQ_BYTE5
MEM_50S
MEM_DATA
MEM_B_DQ_BYTE6
MEM_50S
MEM_DATA
MEM_B_DQ_BYTE7
MEM_50S
MEM_DATA
MEM_B_DQS0
MEM_85D
MEM_DQS
MEM_B_DQS0
MEM_85D
MEM_DQS
MEM_B_DQS1
MEM_85D
MEM_DQS
MEM_B_DQS1
MEM_85D
MEM_DQS
MEM_B_DQS2
MEM_85D
MEM_DQS
MEM_B_DQS2
MEM_85D
MEM_DQS
MEM_B_DQS3
MEM_85D
MEM_DQS
MEM_B_DQS3
MEM_85D
MEM_DQS
MEM_B_DQS4
MEM_85D
MEM_DQS
MEM_B_DQS4
MEM_85D
MEM_DQS
MEM_B_DQS5
MEM_85D
MEM_DQS
MEM_B_DQS5
B
MEM_A_DQS4
MEM_85D
MEM_DQS
MEM_B_DQS6
MEM_85D
MEM_DQS
MEM_B_DQS6
MEM_85D
MEM_DQS
MEM_B_DQS7
MEM_85D
MEM_DQS
MEM_B_DQS7
MEM_85D
MEM_DQS
MEM_A_DQS_P & lt; 0 & gt;
MEM_A_DQS_N & lt; 0 & gt;
MEM_A_DQS_P & lt; 1 & gt;
MEM_A_DQS_N & lt; 1 & gt;
MEM_A_DQS_P & lt; 2 & gt;
MEM_A_DQS_N & lt; 2 & gt;
MEM_A_DQS_P & lt; 3 & gt;
MEM_A_DQS_N & lt; 3 & gt;
MEM_A_DQS_P & lt; 4 & gt;
MEM_A_DQS_N & lt; 4 & gt;
MEM_A_DQS_P & lt; 5 & gt;
MEM_A_DQS_N & lt; 5 & gt;
MEM_A_DQS_P & lt; 6 & gt;
MEM_A_DQS_N & lt; 6 & gt;
MEM_A_DQS_P & lt; 7 & gt;
MEM_A_DQS_N & lt; 7 & gt;
MEM_B_CLK_P & lt; 5..0 & gt;
MEM_B_CLK_N & lt; 5..0 & gt;
MEM_B_CKE & lt; 3..0 & gt;
MEM_B_CS_L & lt; 3..0 & gt;
MEM_B_ODT & lt; 3..0 & gt;
MEM_B_A & lt; 15..0 & gt;
MEM_B_BA & lt; 2..0 & gt;
MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L
MEM_B_DQ & lt; 7..0 & gt;
MEM_B_DQ & lt; 15..8 & gt;
MEM_B_DQ & lt; 23..16 & gt;
MEM_B_DQ & lt; 31..24 & gt;
MEM_B_DQ & lt; 39..32 & gt;
MEM_B_DQ & lt; 47..40 & gt;
MEM_B_DQ & lt; 55..48 & gt;
MEM_B_DQ & lt; 63..56 & gt;
6 11 28
6 11 28
6 11 28
6 11 28
6 11 28
6 11 28
C
6 11 28
6 11 28
6 11 28
6 11 28
6 11 28
6 11 28
6 11 28
6 11 28
6 11 28
6 11 28
6 11 29
6 11 29
6 11 29
6 11 29
6 11 29
6 11 29
6 11 29
6 11 29
6 11 29
6 11 29
6 11 28
6 11 28
6 11 28
6 11 28
B
6 11 28
6 11 28
6 11 28
6 11 28
SOURCE: Calpella SFF Platform DG, Rev 1.5 (#407364), Section 2.2
A
MEM_B_DQS_P & lt; 0 & gt;
MEM_B_DQS_N & lt; 0 & gt;
MEM_B_DQS_P & lt; 1 & gt;
MEM_B_DQS_N & lt; 1 & gt;
MEM_B_DQS_P & lt; 2 & gt;
MEM_B_DQS_N & lt; 2 & gt;
MEM_B_DQS_P & lt; 3 & gt;
MEM_B_DQS_N & lt; 3 & gt;
MEM_B_DQS_P & lt; 4 & gt;
MEM_B_DQS_N & lt; 4 & gt;
MEM_B_DQS_P & lt; 5 & gt;
MEM_B_DQS_N & lt; 5 & gt;
MEM_B_DQS_P & lt; 6 & gt;
MEM_B_DQS_N & lt; 6 & gt;
MEM_B_DQS_P & lt; 7 & gt;
MEM_B_DQS_N & lt; 7 & gt;
6 11 28
6 11 28
6 11 28
6 11 28
6 11 28
6 11 28
6 11 28
6 11 28
6 11 28
6 11 28
6 11 28
6 11 28
6 11 28
6 11 28
SYNC_MASTER=K91_MLB
6 11 28
SYNC_DATE=06/25/2011
PAGE TITLE
Memory Constraints
6 11 28
DRAWING NUMBER
Apple Inc.
051-9585
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
3.0.0
BRANCH
PAGE
101 OF 132
SHEET
94 OF 105
1
A
8
7
6
5
Digital Video Signal Constraints
4
3
2
1
PCH Net Properties
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
NET_TYPE
TABLE_PHYSICAL_RULE_ITEM
DP_85D
*
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
SPACING
=90_OHM_DIFF
DP_AUX_CH
DP_85D
DISPLAYPORT
DP_AUX_CH
DP_85D
DISPLAYPORT
LVDS_IG_A_CLK
LVDS_85D
LVDS
TABLE_PHYSICAL_RULE_ITEM
LVDS_85D
*
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
=4:1_SPACING
?
LVDS
ISL3,ISL4,ISL9,ISL10
=4:1_SPACING
DISPLAYPORT
?
TOP,BOTTOM
=4:1_SPACING
TOP,BOTTOM
=4:1_SPACING
TABLE_SPACING_RULE_ITEM
D
LVDS_85D
LVDS
LVDS_IG_A_DATA3
?
LVDS
LVDS_85D
LVDS
LVDS_85D
LVDS
LVDS_85D
LVDS
?
LVDS
LVDS
LVDS_85D
LVDS_IG_B_DATA
ISL3,ISL4,ISL9,ISL10
TABLE_SPACING_RULE_ITEM
LVDS_85D
LVDS_IG_A_DATA3
DISPLAYPORT
LVDS_IG_A_CLK
LVDS_IG_A_DATA
LVDS_IG_A_DATA
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
SOURCE: HR PLATFORM DESIGN GUIDE, TABLES 191,193
LVDS_IG_B_DATA
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
SATA_90D_ALT
*
=90_OHM_DIFF_ALT
=90_OHM_DIFF_ALT
=90_OHM_DIFF_ALT
=90_OHM_DIFF_ALT
=90_OHM_DIFF_ALT
=90_OHM_DIFF_ALT
SATA_90D
*
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
SATA
SATA_90D_ALT
SATA
SATA_90D_ALT
SATA
SATA_90D_ALT
SATA
SATA
SATA_90D_ALT
ALLOW ROUTE
ON LAYER?
SATA
SATA_90D_ALT
I270
TABLE_PHYSICAL_RULE_HEAD
LAYER
SATA
SATA_90D_ALT
PHYSICAL_RULE_SET
SATA
SATA_90D_ALT
SATA_HDD_R2D
LVDS
SATA_90D_ALT
SATA Interface Constraints
LVDS_85D
SATA_90D_ALT
SATA
=90_OHM_DIFF
I271
DP_IG_AUX_CH_P
DP_IG_AUX_CH_N
8 86
8 86
LVDS_IG_A_CLK_P
LVDS_IG_A_CLK_N
LVDS_IG_A_DATA_P & lt; 2..0 & gt;
LVDS_IG_A_DATA_N & lt; 2..0 & gt;
LVDS_IG_A_DATA_P & lt; 3 & gt;
LVDS_IG_A_DATA_N & lt; 3 & gt;
LVDS_IG_B_DATA_P & lt; 2..0 & gt;
LVDS_IG_B_DATA_N & lt; 2..0 & gt;
SATA_HDD_R2D_C_P
SATA_HDD_R2D_C_N
SATA_HDD_R2D_RC_P
SATA_HDD_R2D_RC_N
SATA_HDD_R2D_P
SATA_HDD_R2D_N
17 89
17 89
17 89
17 89
8 17
8 17
D
17 89
17 89
16 41
16 41
41
41
6 41
6 41
TABLE_PHYSICAL_RULE_ITEM
SATA_90D_ALT
SATA
I272
SATA_90D_ALT
SATA
I273
SATA_90D_ALT
SATA
SATA_HDD_D2R_P
SATA_HDD_D2R_N
SATA_HDD_D2R_C_P
SATA_HDD_D2R_C_N
SATA_HDD_D2R_RC_P
SATA_HDD_D2R_RC_N
I242
SATA_90D_ALT
SATA
SATA_HDD_R2D_RDROUT_P
41
I243
SATA_90D_ALT
SATA
SATA_HDD_R2D_RDROUT_N
41
I246
SATA_90D_ALT
SATA
I247
SATA_90D_ALT
SATA
SATA_HDD_D2R_RDRIN_P
SATA_HDD_D2R_RDRIN_N
I248
SATA_90D_ALT
SATA
SATA_HDD_D2R_RDROUT_P
41
41
SATA_HDD_D2R
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
SATA_37SE
*
=37_OHM_SE
=37_OHM_SE
=37_OHM_SE
=37_OHM_SE
=37_OHM_SE
=37_OHM_SE
SATA_50SE
*
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_ITEM
SATA
I250
SATA_90D_ALT
SATA
SATA_90D_ALT
SATA
SATA_90D
SATA
SATA
SATA_90D
SATA
SATA
SATA_90D
SATA
SATA_90D
?
SATA_90D_ALT
SATA_90D
=5:1_SPACING
I249
SATA_90D
*
SATA
16 41
6 41
6 41
41
41
41
41
SATA_HDD_D2R_RDROUT_N
I251
SATA
16 41
TABLE_SPACING_RULE_ITEM
SATA_ICOMP
*
15 MIL
SATA_ODD_D2R
SATA_90D
SATA_90D
SATA
SATA_HDD_R2D_RDRIN_P
SATA_HDD_R2D_RDRIN_N
SATA_ODD_R2D_C_P
SATA_ODD_R2D_C_N
SATA_ODD_R2D_P
SATA_ODD_R2D_N
SATA_ODD_D2R_P
SATA_ODD_D2R_N
SATA_ODD_D2R_C_P
SATA_ODD_D2R_C_N
PCH_SATA3_ICOMP
SATA_50SE
SATA_ICOMP
PCH_SATA3COMP
PCH_SATA_ICOMP
?
SATA_37SE
SATA_ICOMP
SATA_ODD_R2D
SOURCE: HR PLATFORM DESIGN GUIDE, TABLES 191,193
SATA_ODD_R2D
C
SATA_ODD_D2R
USB 2.0 Interface Constraints
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
SATA
DIFFPAIR NECK GAP
I213
TABLE_PHYSICAL_RULE_ITEM
PCH_USB_RBIAS
*
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
USB_85D
*
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
TABLE_PHYSICAL_RULE_ITEM
USB_EXTA
USB_85D
USB
USB_85D
USB
USB_85D
USB
USB_EXTB_MUX
USB_85D
USB
USB_EXTC
USB_85D
USB
USB_85D
USB
USB_85D
USB
USB_85D
USB
USB_85D
USB
USB_85D
USB
USB_85D
USB
USB_85D
USB
USB_85D
USB
USB_85D
USB
USB_85D
USB
USB_85D
USB
USB_85D
USB
I269
USB_85D
USB
I275
USB_85D
USB
I274
USB_85D
USB
I276
USB_85D
USB
I277
USB_85D
USB
USB_EXTB_MUX
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_ITEM
USB
*
=4:1_SPACING
?
TABLE_SPACING_RULE_ITEM
USB_RBIAS
*
15 MIL
?
USB_CAMERA
I228
USB_CAMERA
I229
USB_BT
SOURCE: CR SFF PLATFORM DESIGN GUIDE V0.7, TABLE 4-211, 1X1+
I278
USB_BT
I279
USB_TPAD
USB 3.0 Interface Constraints
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
I268
USB_TPAD
TABLE_SPACING_RULE_ITEM
USB3
*
=5:1_SPACING
?
B
USB_IR
USB_85D
USB
USB_85D
USB
PCH_USB_RBIAS
PCH_USB_RBIAS
USB_RBIAS
USB3_EXT_TX
USB_85D
USB3
USB_85D
USB3
USB_85D
USB3
USB_85D
USB3
USB_85D
USB3
USB_85D
USB3
USB_85D
USB3
USB_85D
USB3
USB_85D
USB3
USB_85D
USB3
USB_85D
USB3
USB_85D
USB3
USB_85D
USB3
USB_85D
USB3
USB_85D
USB3
USB_85D
USB3
USB_85D
USB3
USB_85D
USB3
USB_85D
USB3
I227
USB_85D
USB3
I230
USB_85D
USB
I231
USB_85D
USB
I232
USB_85D
USB
I233
USB_85D
USB
I221
I220
I222
USB3_EXT_RX
I223
I256
USB3_EXT_TX
I258
I257
USB3_EXT_RX
I259
I260
USB3_EXT_TX
I261
I266
USB3_EXT_TX
I267
I264
USB3_EXT_TX
I265
I262
USB3_EXT_RX
I263
I224
USB3_EXT_TX
I225
I226
A
USB3_EXT_RX
I234
USB_EXTB_MUX
USB_85D
USB
I235
USB_EXTB_MUX
USB_85D
USB
I236
USB_SMC
USB_85D
USB
I237
USB_SMC
USB_85D
USB
USB_EXTA
USB_85D
USB
USB_85D
USB
USB_85D
USB
USB_85D
USB
I253
I252
I254
USB_EXTA
I255
8
7
6
5
4
PCH_SATAICOMP
USB_EXTA_P
USB_EXTA_N
USB_EXTB_MUX_P
USB_EXTB_MUX_N
USB_EXTC_P
USB_EXTC_N
USB_CAMERA_CONN_P
USB_CAMERA_CONN_N
USB_CAMERA_P
USB_CAMERA_N
USB_BT_P
USB_BT_N
USB_BT_CONN_P
USB_BT_CONN_N
USB_TPAD_P
USB_TPAD_N
USB_TPAD_R_P
USB_TPAD_R_N
USB_EXTD_XHCI_P
USB_EXTD_XHCI_N
USB_HUB_UP_P
USB_HUB_UP_N
USB_IR_P
USB_IR_N
PCH_USB_RBIAS
USB3_EXTA_TX_P
USB3_EXTA_TX_N
USB3_EXTA_RX_P
USB3_EXTA_RX_N
USB3_EXTA_TX_F_P
USB3_EXTA_TX_F_N
USB3_EXTA_RX_F_P
USB3_EXTA_RX_F_N
USB3_EXTA_TX_C_P
USB3_EXTA_TX_C_N
USB3_EXTB_TX_C_P
USB3_EXTB_TX_C_N
USB3_EXTB_TX_F_P
USB3_EXTB_TX_F_N
USB3_EXTB_RX_F_P
USB3_EXTB_RX_F_N
USB3_EXTB_TX_P
USB3_EXTB_TX_N
USB3_EXTB_RX_P
USB3_EXTB_RX_N
USB_EXTB_EHCI_P
USB_EXTB_EHCI_N
USB_EXTB_XHCI_P
USB_EXTB_XHCI_N
USB_EXTB_F_P
USB_EXTB_F_N
USB_SMC_N
USB_SMC_P
USB_EXTA_MUXED_P
USB_EXTA_MUXED_N
USB_EXTA_MUXED_F_P
USB_EXTA_MUXED_F_N
3
41
41
16 41
16 41
6 41
C
6 41
16 41
16 41
6 41
6 41
16
16
18 42
18 42
25 43
25 43
8 18
8 18
6 32
6 32
18 32
18 32
8 32
8 32
6 32
6 32
8 53
8 53
25 53 101
25 53 101
18 25
18 25
B
18 25
18 25
8 44
8 44
18
6 18 42
6 18 42
6 18 42
6 18 42
6 42
6 42
6 42
6 42
6 42
6 42
6 43
6 43
6 43
6 43
6 43
6 43
6 18 43
6 18 43
6 18 43
6 18 43
18 25
18 25
18 25
SYNC_MASTER=K92_MLB
SYNC_DATE=08/09/2010
PAGE TITLE
PCH Constraints 1
18 25
DRAWING NUMBER
43
43
Apple Inc.
8
051-9585
R
42
42
42
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
2
D
3.0.0
8
42
SIZE
REVISION
BRANCH
PAGE
102 OF 132
SHEET
95 OF 105
1
A
8
7
6
5
LPC Bus Constraints
4
3
2
1
PCH Net Properties
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
NET_TYPE
TABLE_PHYSICAL_RULE_ITEM
LPC_50S
*
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
CLK_LPC_50S
*
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
=STANDARD
SPACING
=STANDARD
TABLE_PHYSICAL_RULE_ITEM
LPC_50S
LPC_FRAME_L
LAYER
*
6 MIL
LPC
PCH_LPC_CLK0
CLK_LPC_50S
CLK_LPC
CLK_LPC
CLK_LPC
?
TABLE_SPACING_RULE_ITEM
CLK_LPC
*
LPC_AD & lt; 3..0 & gt;
LPC_FRAME_L
LPC_RESET_L
6 16 45 47 89
6 16 45 47 89
24 89
WEIGHT
TABLE_SPACING_RULE_ITEM
LPC
LPC_50S
CLK_LPC_50S
LINE-TO-LINE SPACING
LPC
CLK_LPC_50S
SPACING_RULE_SET
LPC_50S
LPC_RESET_L
TABLE_SPACING_RULE_HEAD
LPC
8 MIL
?
LPC_CLK33M_SMC_R
LPC_CLK33M_SMC
LPC_CLK33M_LPCPLUS
SMBUS_PCH_CLK
SMBUS_PCH_DATA
SML_PCH_0_CLK
SML_PCH_0_DATA
SML_PCH_1_CLK
SML_PCH_1_DATA
18 24
24 45
6 24 47
SMBUS_PCH_CLK
SMB_50S
SMB
SMBUS_PCH_DATA
SMB_50S
SMB
SMBUS_PCH_0_CLK
SMB_50S
SMB
SMBUS_PCH_0_DATA
SMB_50S
SMB
SMBUS_PCH_1_CLK
SMB_50S
SMB
SMBUS_PCH_1_DATA
SMB_50S
SMB
HDA_BIT_CLK
HDA_50S
HDA
HDA_50S
HDA
HDA_50S
HDA
HDA_50S
HDA
HDA_50S
HDA
HDA_50S
HDA
HDA_50S
HDA
HDA_50S
HDA
HDA_50S
HDA
HDA_50S
HDA
SPI_55S
SPI
SPI_55S
SPI
SPI_55S
SPI
SPI_55S
SPI
SPI_MISO
SPI_55S
SPI
SPI_CS0
SPI_55S
SPI
SPI_55S
SPI
PCIE_85D
PCIE
PCIE_85D
PCIE
PCIE_85D
PCIE
PCIE_85D
PCIE
PCIE_85D
PCIE
PCIE_85D
PCIE
PCIE_85D
PCIE
PCIE_85D
PCIE
PCIE_85D
PCIE
PCIE_85D
PCIE
PCIE_85D
PCIE
PCIE_85D
PCIE
PCIE_85D
PCIE
PCIE_85D
PCIE
PCIE_AP_R2D_P
PCIE_AP_R2D_N
PCIE_AP_R2D_C_P
PCIE_AP_R2D_C_N
PCIE_AP_D2R_P
PCIE_AP_D2R_N
I270
PCIE_85D
PCIE
PCIE_AP_D2R_R_P
I269
PCIE
PCIE_AP_D2R_R_N
32
PCIE_85D
PCIE
PCIE_85D
PCIE
PCIE_85D
PCIE
PCIE_85D
PCIE
PCIE_85D
PCIE
PCIE_85D
PCIE
PCIE_85D
PCIE
SMBus Interface Constraints
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM
SMB_50S
*
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
HDA_SYNC
TABLE_SPACING_RULE_ITEM
SMB
*
=2x_DIELECTRIC
?
HDA_RST_L
HD Audio Interface Constraints
HDA_SDIN0
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
HDA_SDOUT
TABLE_PHYSICAL_RULE_ITEM
HDA_50S
*
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
D
32
PCIE_85D
D
=STANDARD
HDA_BIT_CLK
HDA_BIT_CLK_R
HDA_SYNC
HDA_SYNC_R
HDA_RST_R_L
HDA_RST_L
HDA_SDIN0
AUD_SDI_R
HDA_SDOUT
HDA_SDOUT_R
16 48
16 48
16 48
16 48
16 48
16 48
16 57
16
16 57
16
16
16 57
16 57
57
16 57
16 24
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
=2x_DIELECTRIC
?
SPI_CLK
TABLE_SPACING_RULE_ITEM
HDA
*
SPI_MOSI
SIO Signal Constraints
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
SPI_CLK_R
SPI_CLK
SPI_MOSI_R
SPI_MOSI
SPI_MISO
SPI_CS0_R_L
SPI_CS0_L
16 47
47
16 47
47
16 47
16 47
47
TABLE_PHYSICAL_RULE_ITEM
C
CLK_SLOW_45S
*
=45_OHM_SE
=45_OHM_SE
=45_OHM_SE
=45_OHM_SE
=STANDARD
=STANDARD
PCIE_ENET_R2D
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_ITEM
CLK_SLOW
*
8 MIL
?
PCIE_ENET_D2R
SPI Interface Constraints
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
SPI_55S
*
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
TABLE_PHYSICAL_RULE_ITEM
PCIE_AP_R2D
PCIE_AP_D2R
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
PCIE_ENET_R2D_P
PCIE_ENET_R2D_N
PCIE_ENET_R2D_C_P
PCIE_ENET_R2D_C_N
PCIE_ENET_D2R_P
PCIE_ENET_D2R_N
PCIE_ENET_D2R_C_P
PCIE_ENET_D2R_C_N
36
C
36
16 36
16 36
16 36
16 36
36
36
6 32
6 32
16 32
16 32
16 32
16 32
TABLE_SPACING_RULE_ITEM
SPI
*
8 MIL
?
PCIE_FW_R2D
PCIE_FW_D2R
PCIE_85D
I253
CLK_PCIE
I254
CLK_PCIE_90D
CLK_PCIE
CLK_PCIE_90D
CLK_PCIE
I261
CLK_PCIE_90D
CLK_PCIE
I255
CLK_PCIE_90D
CLK_PCIE
I257
CLK_PCIE_90D
CLK_PCIE
I256
CLK_PCIE_90D
CLK_PCIE
I259
CLK_PCIE_90D
CLK_PCIE
I258
CPU_50S
CLK_PCIE
I260
CPU_50S
CLK_PCIE
CLK_PCIE_90D
CLK_PCIE
CLK_PCIE_90D
CLK_PCIE
CLK_PCIE_90D
CLK_PCIE
CLK_PCIE_90D
CLK_PCIE
CLK_PCIE_90D
CLK_PCIE
CLK_PCIE_90D
CLK_PCIE
CLK_PCIE_90D
CLK_PCIE
CLK_PCIE_90D
CLK_PCIE
CLK_PCIE_90D
CLK_PCIE
CLK_PCIE_90D
CLK_PCIE
CLK_PCIE_90D
CLK_PCIE
CLK_PCIE_90D
B
PCIE
CLK_PCIE_90D
CLK_PCIE
I262
I277
PCIE_CLK100M_T29_
PCIE_CLK100M
I278
PCIE_CLK100M
PCIE_CLK100M_ENET
PCIE_CLK100M_AP
PCIE_CLK100M_FW
PCIE_CLK100M_EXCARD
A
PCIE_FW_R2D_P
PCIE_FW_R2D_N
PCIE_FW_R2D_C_P
PCIE_FW_R2D_C_N
PCIE_FW_D2R_P
PCIE_FW_D2R_N
PCIE_FW_D2R_C_P
PCIE_FW_D2R_C_N
PCIE_CLK100M_PCH_P
PCIE_CLK100M_PCH_N
PCIE_CLK100M_TBT_P
PCIE_CLK100M_TBT_N
PCH_CLK96M_DOT_P
PCH_CLK96M_DOT_N
PCH_CLK100M_SATA_P
PCH_CLK100M_SATA_N
PCH_CLK14P3M_REFCLK
PCH_CLK33M_PCIIN
PEX_TSTCLK_O_P
PEX_TSTCLK_O_N
PEG_CLK100M_P
PEG_CLK100M_N
PCIE_CLK100M_ENET_P
PCIE_CLK100M_ENET_N
PCIE_CLK100M_AP_P
PCIE_CLK100M_AP_N
PCIE_CLK100M_FW_P
PCIE_CLK100M_FW_N
PCIE_CLK100M_EXCARD_P
PCIE_CLK100M_EXCARD_N
38
38
16 38
16 38
16 38
16 38
38
38
16
B
16
16 33
16 33
16
16
16
16
16
16 24
75
75
16 75
16 75
16 36
16 36
16 32
16 32
16 38
16 38
8 16
8 16
SYNC_MASTER=J31_YONAS
I263
PCIE_T29_D2R
PCIE_85D
PCIE
PCIE_T29_D2R
PCIE_85D
PCIE
PCIE_T29_R2D
PCIE_85D
PCIE
I274
PCIE_T29_R2D
PCIE_85D
PCIE
I275
PCIE_T29_D2R
PCIE_85D
PCIE
I276
5
PCIE
I273
6
PCIE
PCIE_85D
I268
7
PCIE_85D
PCIE_T29_R2D
I266
8
PCIE_T29_R2D
I264
PCIE_T29_D2R
PCIE_85D
PCIE
4
PCIE_TBT_R2D_C_P & lt; 3..0 & gt;
PCIE_TBT_R2D_C_N & lt; 3..0 & gt;
PCIE_TBT_D2R_P & lt; 3..0 & gt;
PCIE_TBT_D2R_N & lt; 3..0 & gt;
PCIE_TBT_R2D_P & lt; 3..0 & gt;
PCIE_TBT_R2D_N & lt; 3..0 & gt;
PCIE_TBT_D2R_C_P & lt; 3..0 & gt;
PCIE_TBT_D2R_C_N & lt; 3..0 & gt;
3
8 33
SYNC_DATE=05/05/2011
PAGE TITLE
PCH Constraints 2
8 33
DRAWING NUMBER
8 33
8 33
Apple Inc.
33
051-9585
R
33
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
2
D
3.0.0
33
33
SIZE
REVISION
BRANCH
PAGE
103 OF 132
SHEET
96 OF 105
1
A
8
7
6
5
CAESAR IV (Ethernet) Constraints
4
3
2
1
Ethernet Net Properties
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
ENET_50S
*
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
SPACING_RULE_SET
LAYER
NET_TYPE
DIFFPAIR NECK GAP
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
SPACING
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_HEAD
?
ENET_50S
ENET_3X
ENET_RESET_L
ENET_100D
ENET_MDI
ENET_MDI_P & lt; 3..0 & gt;
36 37
ENET_MDI
WEIGHT
=3:1_SPACING
ENET_RESET_L
ENET_MDI
LINE-TO-LINE SPACING
ENET_100D
ENET_MDI
ENET_MDI_N & lt; 3..0 & gt;
36 37
30 36
TABLE_SPACING_RULE_ITEM
ENET_3X
*
SOURCE: Broadcom 5764-DS04-RDS Page 38
ENET_50S
ENET_CR
SDCONN_DATA & lt; 7..0 & gt;
30 36
I170
CR_DATA_A0
ENET_50S
ENET_CR
SDCONN_CMD
30 36
I171
CR_CLK
ENET_50S
ENET_CR
SDCONN_CLK
30 36
ENET_50S
ENET_CR
SDCONN_CLK_R
30
30
30
I169
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
D
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_ITEM
ENET_CR
*
=3X_DIELECTRIC
?
I172
I173
ENET_50S
ENET_CR
I174
SOURCE: Attila Farkas Email - 8/2/10
SDCONN_CLK_R_L
ENET_50S
ENET_CR
SDCONN_R_DATA & lt; 7..0 & gt;
D
CAESAR IV (Ethernet PHY) Constraints
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
ENET_100D
*
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
SPACING_RULE_SET
LAYER
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_HEAD
LINE-TO-LINE SPACING
WEIGHT
0.6 MM
?
TABLE_SPACING_RULE_ITEM
ENET_MDI
*
SOURCE: Broadcom 5764-DS04-RDS Page 38
C
FireWire Interface Constraints
C
FireWire Net Properties
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
FW_110D
*
=110_OHM_DIFF
=110_OHM_DIFF
=110_OHM_DIFF
=110_OHM_DIFF
=110_OHM_DIFF
NET_TYPE
DIFFPAIR NECK GAP
=110_OHM_DIFF
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
SPACING
TABLE_PHYSICAL_RULE_ITEM
I158
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
FW_TP
FW_P0_TPA_P
38 40
FW_P0_TPA
FW_110D
FW_TP
FW_P0_TPA_N
38 40
I160
WEIGHT
FW_110D
I159
TABLE_SPACING_RULE_HEAD
FW_P0_TPA
FW_P0_TPB
FW_110D
FW_TP
FW_P0_TPB_P
38 40
38 40
I161
FW_P0_TPB
FW_110D
FW_TP
FW_P0_TPB_N
I162
FW_P1_TPA
FW_110D
FW_TP
FW_P1_TPA_P
38 40
I163
FW_P1_TPA
FW_110D
FW_TP
FW_P1_TPA_N
38 40
I164
FW_P1_TPB
FW_110D
FW_TP
FW_P1_TPB_P
38 40
I165
FW_P1_TPB
FW_110D
FW_TP
FW_P1_TPB_N
38 40
TABLE_SPACING_RULE_ITEM
FW_TP
*
=3:1_SPACING
?
Port 2 Not Used
B
B
A
SYNC_MASTER=K91_ERIC
SYNC_DATE=08/03/2010
PAGE TITLE
Ethernet/FW Constraints
DRAWING NUMBER
Apple Inc.
051-9585
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
3.0.0
BRANCH
PAGE
104 OF 132
SHEET
97 OF 105
1
A
8
7
6
5
DisplayPort Signal Constraints
4
3
NET_TYPE
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
SPACING
Thunderbolt I2C Signal Constraints
TBT_R2D0
TBTDP_80D
TBTDP
TBT_R2D0
TBTDP_80D
TBTDP
TBT_R2D1
TBTDP_80D
TBTDP
TBT_R2D1
TBTDP_80D
TBTDP
TBT_D2R0
TBTDP_100D
TBTDP
TBT_D2R0
TBTDP_100D
TBTDP
TBT_D2R1
TBTDP_100D
TBTDP
TBT_D2R1
TBTDP_100D
TBTDP
TBTDP_100D
TBTDP
TBTDP_100D
TBTDP
TBTDP_80D
TBTDP
TBTDP_80D
TBTDP
TBTDP_80D
TBTDP
TBTDP_80D
TBTDP
DP_SDRVA_ML_ODD
TBTDP_80D
TBTDP
DP_SDRVA_ML_ODD
TBTDP_80D
TBTDP
I276
DP_SDRVA_ML_ODD
TBTDP_80D
TBTDP
I277
DP_SDRVA_ML_ODD
TBTDP_80D
TBTDP
I278
DP_SDRVA_ML_EVEN
TBTDP_80D
TBTDP
I279
DP_SDRVA_ML_EVEN
TBTDP_80D
TBTDP
I280
DP_SDRVA_ML_EVEN
TBTDP_80D
TBTDP
I281
DP_SDRVA_ML_EVEN
TBTDP_80D
TBTDP
TBTDP_80D
TBTDP
TBTDP_80D
TBTDP
TBTDP_80D
TBTDP
TBTDP_80D
TBTDP
TBTDP_80D
TBTDP
TBTDP_80D
TBTDP
TBTDP_80D
TBTDP
TBTDP_80D
TBTDP
TBTDP_80D
TBTDP
TBTDP_80D
TBTDP
TABLE_PHYSICAL_RULE_HEAD
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM
TBT_I2C_55S
*
=55_OHM_SE
1
Thunderbolt/DP Net Properties
NOTE: DisplayPort Physical/Spacing Constraints provided by Chipset or GPU page.
PHYSICAL_RULE_SET
2
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
TBT_R2D_P & lt; 0 & gt;
TBT_R2D_N & lt; 0 & gt;
TBT_R2D_P & lt; 1 & gt;
TBT_R2D_N & lt; 1 & gt;
87
87
87
87
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
=2x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
TBT_I2C
D
*
Thunderbolt SPI Signal Constraints
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TBT_SPI_55S
*
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
TBT_D2R_C_P & lt; 0 & gt;
TBT_D2R_C_N & lt; 0 & gt;
TBT_D2R_C_P & lt; 1 & gt;
TBT_D2R_C_N & lt; 1 & gt;
TBT_A_D2R1_AUXCH_P
TBT_A_D2R1_AUXCH_N
87 88
87 88
D
87 88
87 88
88
88
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_ITEM
TBT_SPI
*
=2x_DIELECTRIC
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TBTDP_80D
*
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
*
SPACING_RULE_SET
LAYER
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
TABLE_SPACING_RULE_HEAD
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_ITEM
TBTDP
*
6 87
87
87
=5x_DIELECTRIC
DP_SDRVA_ML_P & lt; 3 & gt;
DP_SDRVA_ML_N & lt; 3 & gt;
DP_SDRVA_ML_P & lt; 1 & gt;
DP_SDRVA_ML_N & lt; 1 & gt;
DP_SDRVA_ML_P & lt; 2 & gt;
DP_SDRVA_ML_N & lt; 2 & gt;
DP_SDRVA_ML_P & lt; 0 & gt;
DP_SDRVA_ML_N & lt; 0 & gt;
87
87
87
87
6 87
6 87
6 87
6 87
TABLE_SPACING_RULE_ITEM
?
TBTDP
TOP,BOTTOM
=7x_DIELECTRIC
?
SOURCE: Bill Cornelius’s Thunderbolt Routing Notes
C
B
6 87
?
Thunderbolt/DP Connector Signal Constraints
TBTDP_100D
DP_SDRVA_ML_C_P & lt; 3..0 & gt;
DP_SDRVA_ML_C_N & lt; 3..0 & gt;
DP_SDRVA_ML_R_P & lt; 3..0 & gt;
DP_SDRVA_ML_R_N & lt; 3..0 & gt;
DP_SDRVA_AUXCH_P
DP_SDRVA_AUXCH_N
DP_SDRVA_AUXCH_C_P
DP_SDRVA_AUXCH_C_N
TBT_A_ML_P & lt; 3..0 & gt;
TBT_A_ML_N & lt; 3..0 & gt;
TBT_A_ML_C_P & lt; 3..0 & gt;
TBT_A_ML_C_N & lt; 3..0 & gt;
DP_A_EXT_AUXCH_P
DP_A_EXT_AUXCH_N
87
87
87
87
87 88
C
87 88
87 88
87 88
87 88
87 88
B
Thunderbolt IC Net Properties
NET_TYPE
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
SPACING
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_TBTSNK0_ML
DP_85D
DISPLAYPORT
DP_TBTSNK0_ML
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_TBTSNK0_AUXCH
DP_85D
DISPLAYPORT
DP_TBTSNK0_AUXCH
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_TBTSNK1_ML
DP_85D
DISPLAYPORT
DP_TBTSNK1_ML
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_TBTSNK1_AUXCH
DP_85D
DISPLAYPORT
DP_TBTSNK1_AUXCH
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
TBT_I2C_55S
TBT_I2C
TBT_I2C_55S
TBT_I2C
A
TBT_SPI_CLK
TBT_SPI_55S
TBT_SPI
TBT_SPI_MOSI
TBT_SPI_55S
TBT_SPI
TBT_SPI_MISO
TBT_SPI_55S
TBT_SPI
TBT_SPI_CS_L
TBT_SPI_55S
TBTDP_80D
TBTDP
TBTDP_80D
TBTDP
TBTDP_100D
TBTDP
TBTDP_100D
8
TBT_SPI
TBTDP
DP_TBTSNK0_ML_C_P & lt; 3..0 & gt;
DP_TBTSNK0_ML_C_N & lt; 3..0 & gt;
DP_TBTSNK0_ML_P & lt; 3..0 & gt;
DP_TBTSNK0_ML_N & lt; 3..0 & gt;
DP_TBTSNK0_AUXCH_C_P
DP_TBTSNK0_AUXCH_C_N
DP_TBTSNK0_AUXCH_P
DP_TBTSNK0_AUXCH_N
DP_TBTSNK1_ML_C_P & lt; 3..0 & gt;
DP_TBTSNK1_ML_C_N & lt; 3..0 & gt;
DP_TBTSNK1_ML_P & lt; 3..0 & gt;
DP_TBTSNK1_ML_N & lt; 3..0 & gt;
DP_TBTSNK1_AUXCH_C_P
DP_TBTSNK1_AUXCH_C_N
DP_TBTSNK1_AUXCH_P
DP_TBTSNK1_AUXCH_N
6 33 81
6 33 81
6 33
6 33
6 33 81
6 33 81
6 33
6 33
6 33 81
6 33 81
6 33
6 33
6 33 81
6 33 81
6 33
6 33
DP_TBTSRC_ML_C_P & lt; 3..0 & gt;
DP_TBTSRC_ML_C_N & lt; 3..0 & gt;
DP_TBTSRC_AUXCH_C_P
DP_TBTSRC_AUXCH_C_N
I2C_TBT_SCL
I2C_TBT_SDA
TBT_SPI_CLK
TBT_SPI_MOSI
TBT_SPI_MISO
TBT_SPI_CS_L
TBT_R2D_C_P & lt; 3..0 & gt;
TBT_R2D_C_N & lt; 3..0 & gt;
TBT_D2R_P & lt; 3..0 & gt;
TBT_D2R_N & lt; 3..0 & gt;
7
Only used on hosts supporting Thunderbolt video-in
33 48
SYNC_MASTER=T29_REF
33 48
SYNC_DATE=06/14/2011
PAGE TITLE
Thunderbolt Constraints
33
DRAWING NUMBER
33
Apple Inc.
33
33
051-9585
R
NOTICE OF PROPRIETARY PROPERTY:
SIZE
D
REVISION
3.0.0
BRANCH
6 8 33 87
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
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SMC SMBus Net Properties
NET_TYPE
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
1TO1_DIFFPAIR
*
=STANDARD
=STANDARD
=STANDARD
=STANDARD
0.1 MM
0.1 MM
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
SPACING
TABLE_PHYSICAL_RULE_ITEM
SMBUS_SMC_0_S0_SCL
SMB_50S
SMB
SMBUS_SMC_0_S0_SDA
SMB_50S
SMB
SMBUS_SMC_1_S0_SCL
SMB_50S
SMB
SMBUS_SMC_1_S0_SDA
SMB_50S
SMB
SMBUS_SMC_2_S3_SCL
SMB_50S
SMB
SMBUS_SMC_2_S3_SDA
SMB
SMB_50S
SMB
SMBUS_SMC_3_SDA
SMB_50S
SMB
SMBUS_SMC_5_G3_SCL
SMB_50S
SMB
SMBUS_SMC_5_G3_SDA
D
SMB_50S
SMBUS_SMC_3_SCL
SMB_50S
SMB
SMBUS_SMC_0_S0_SCL
SMBUS_SMC_0_S0_SDA
SMBUS_SMC_1_S0_SCL
SMBUS_SMC_1_S0_SDA
SMBUS_SMC_2_S3_SCL
SMBUS_SMC_2_S3_SDA
SMBUS_SMC_3_SCL
SMBUS_SMC_3_SDA
SMBUS_SMC_5_G3_SCL
SMBUS_SMC_5_G3_SDA
45 48
45 48
45 48
45 48
6 45 48
6 45 48
45 48
45 48
D
6 45 48
6 45 48
SMBus Charger Net Properties
NET_TYPE
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
CHGR_CSI
1TO1_DIFFPAIR
1TO1_DIFFPAIR
CHGR_CSO
1TO1_DIFFPAIR
1TO1_DIFFPAIR
SPACING
CHGR_CSI_P
CHGR_CSI_N
65
65
CHGR_CSO_P
CHGR_CSO_N
65
65
C
C
B
B
A
SYNC_MASTER=J31_YONAS
SYNC_DATE=08/11/2011
PAGE TITLE
SMC Constraints
DRAWING NUMBER
Apple Inc.
051-9585
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
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SIZE
D
REVISION
3.0.0
BRANCH
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GDDR5 Frame Buffer Signal Constraints
4
3
GDDR5 FB A Net Properties
2
1
GDDR5 FB B Net Properties
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM
GDDR5_45R50SE
*
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
12.7 MM
=STANDARD
*
=45_OHM_SE
=45_OHM_SE
=45_OHM_SE
=45_OHM_SE
=STANDARD
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
NET_TYPE
=STANDARD
TABLE_PHYSICAL_RULE_ITEM
FB_A0_CLK
GDDR5_80D
GDDR5_CLK
FB_A0_CLK
GDDR5_80D
GDDR5_CLK
TABLE_PHYSICAL_RULE_ITEM
GDDR5_80D
*
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
LINE-TO-LINE SPACING
WEIGHT
*
=5x_DIELECTRIC
?
LINE-TO-LINE SPACING
=5x_DIELECTRIC
TABLE_SPACING_RULE_ITEM
*
=3x_DIELECTRIC
TABLE_SPACING_RULE_ITEM
?
GDDR5_CMD
TOP,BOTTOM
=4x_DIELECTRIC
*
=3x_DIELECTRIC
*
?
=5x_DIELECTRIC
GDDR5_45SE
GDDR5_CMD
GDDR5_45SE
GDDR5_CMD
GDDR5_45SE
GDDR5_CMD
GDDR5_45SE
GDDR5_CMD
GDDR5_45SE
GDDR5_CMD
TABLE_SPACING_RULE_ITEM
GDDR5_DATA
TOP,BOTTOM
=5x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
GDDR5_EDC
GDDR5_CMD
?
TABLE_SPACING_RULE_ITEM
GDDR5_DATA
GDDR5_CMD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
GDDR5_CMD
GDDR5_CMD
FB_A0_CMD
?
GDDR5_45SE
WEIGHT
TOP,BOTTOM
GDDR5_45SE
FB_A1_CMD
FB_A1_CMD
LAYER
GDDR5_CLK
GDDR5_45SE
FB_A0_CMD
SPACING_RULE_SET
GDDR5_CMD
FB_A0_CMD
LAYER
GDDR5_CLK
GDDR5_45SE
FB_A1_CMD
SPACING_RULE_SET
GDDR5_CLK
FB_A0_CMD
TABLE_SPACING_RULE_HEAD
GDDR5_CLK
GDDR5_80D
FB_A0_CMD
TABLE_SPACING_RULE_HEAD
GDDR5_80D
FB_A1_CMD
=80_OHM_DIFF
FB_A1_CLK
FB_A1_CLK
D
ELECTRICAL_CONSTRAINT_SET
SPACING
PHYSICAL
SPACING
=STANDARD
GDDR5_45SE
NET_TYPE
TABLE_SPACING_RULE_ITEM
?
GDDR5_EDC
TOP,BOTTOM
=5x_DIELECTRIC
?
Digital Video Signal Constraints
FB_A1_CMD
GDDR5_45SE
GDDR5_CMD
FB_A0_CMD_R
GDDR5_45SE
GDDR5_CMD
FB_A1_CMD_R
GDDR5_45SE
GDDR5_CMD
FB_A0_CMD
GDDR5_45SE
GDDR5_CMD
FB_A1_CMD
GDDR5_45SE
GDDR5_CMD
FB_A0_EDC0
GDDR5_45SE
GDDR5_EDC
I293
FB_A0_EDC1
GDDR5_45SE
GDDR5_EDC
I294
FB_A0_EDC2
GDDR5_45SE
GDDR5_EDC
I295
FB_A0_EDC3
GDDR5_45SE
GDDR5_EDC
I296
FB_A1_EDC0
GDDR5_45SE
GDDR5_EDC
I297
FB_A1_EDC1
GDDR5_45SE
GDDR5_EDC
I298
FB_A1_EDC2
GDDR5_45SE
GDDR5_EDC
FB_A1_EDC3
GDDR5_45SE
GDDR5_EDC
FB_A0_DBI_L0
GDDR5_45SE
GDDR5_DATA
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM
DP_85D
*
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
LVDS_85D
*
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
DISPLAYPORT
*
=3x_DIELECTRIC
TABLE_SPACING_RULE_HEAD
?
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
DISPLAYPORT
TOP,BOTTOM
=4x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LVDS
*
LVDS intra-pair matching should be 0.127 mm.
=3x_DIELECTRIC
TABLE_SPACING_RULE_ITEM
?
LVDS
TOP,BOTTOM
=4x_DIELECTRIC
?
Pairs should be within 0.508mm of entire channel.
DisplayPort/TMDS intra-pair matching should be 0.127mm.
DIsplayPort AUX CH intra-pair matching should be 0.127mm.
Inter-pair matching should be within 2.54cm.
Max Length 241.3mm.
Max length 330.2mm.
Max length of LVDS/DisplayPort/TMDS traces: 13 inches.
I299
FB_A0_DBI_L1
GDDR5_45SE
GDDR5_DATA
I300
FB_A0_DBI_L2
GDDR5_45SE
GDDR5_DATA
I301
FB_A0_DBI_L3
GDDR5_45SE
GDDR5_DATA
I302
FB_A1_DBI_L0
GDDR5_45SE
GDDR5_DATA
I303
FB_A1_DBI_L1
GDDR5_45SE
GDDR5_DATA
I304
FB_A1_DBI_L2
GDDR5_45SE
GDDR5_DATA
FB_A1_DBI_L3
GDDR5_45SE
GDDR5_DATA
FB_A0_WCLK0
GDDR5_80D
GDDR5_CMD
FB_A0_WCLK0
GDDR5_80D
GDDR5_CMD
FB_A0_WCLK1
GDDR5_80D
GDDR5_CMD
FB_A0_WCLK1
GDDR5_80D
GDDR5_CMD
FB_A1_WCLK0
GDDR5_80D
GDDR5_CMD
FB_A1_WCLK0
GDDR5_80D
GDDR5_CMD
FB_A1_WCLK1
SOURCE: Calpella SFF DG Rev 1.5 (407364) and Family GPU DG-04202-001-v04.
GDDR5_80D
GDDR5_CMD
C
FB_A1_WCLK1
GDDR5_80D
GDDR5_CMD
FB_A0_DQ_BYTE0
GDDR5_45SE
GDDR5_DATA
FB_A0_DQ_BYTE1
GDDR5_45SE
GDDR5_DATA
FB_A0_DQ_BYTE2
GDDR5_45SE
GDDR5_DATA
FB_A0_DQ_BYTE3
GDDR5_45SE
GDDR5_DATA
FB_A1_DQ_BYTE0
GDDR5_45SE
GDDR5_DATA
FB_A1_DQ_BYTE1
GDDR5_45SE
GDDR5_DATA
FB_A1_DQ_BYTE2
GDDR5_DATA
GDDR5_45SE
GDDR5_DATA
FB_A0_CMD_R
I323
GDDR5_45SE
FB_A1_DQ_BYTE3
GDDR5_45SE
GDDR5_CMD
FB_A1_CMD_R
GDDR5_45SE
GDDR5_CMD
FB_A0_CLK_P
FB_A0_CLK_N
FB_A1_CLK_P
FB_A1_CLK_N
FB_A0_A & lt; 8..0 & gt;
FB_A1_A & lt; 8..0 & gt;
FB_A0_ABI_L
FB_A1_ABI_L
FB_A0_RAS_L
FB_A1_RAS_L
FB_A0_CAS_L
FB_A1_CAS_L
FB_A0_WE_L
FB_A1_WE_L
FB_A0_CKE_L
FB_A1_CKE_L
FB_A0_CS_L
FB_A1_CS_L
FB_A0_EDC & lt; 0 & gt;
FB_A0_EDC & lt; 1 & gt;
FB_A0_EDC & lt; 2 & gt;
FB_A0_EDC & lt; 3 & gt;
FB_A1_EDC & lt; 0 & gt;
FB_A1_EDC & lt; 1 & gt;
FB_A1_EDC & lt; 2 & gt;
FB_A1_EDC & lt; 3 & gt;
FB_A0_DBI_L & lt; 0 & gt;
FB_A0_DBI_L & lt; 1 & gt;
FB_A0_DBI_L & lt; 2 & gt;
FB_A0_DBI_L & lt; 3 & gt;
FB_A1_DBI_L & lt; 0 & gt;
FB_A1_DBI_L & lt; 1 & gt;
FB_A1_DBI_L & lt; 2 & gt;
FB_A1_DBI_L & lt; 3 & gt;
FB_A0_WCLK_P & lt; 0 & gt;
FB_A0_WCLK_N & lt; 0 & gt;
FB_A0_WCLK_P & lt; 1 & gt;
FB_A0_WCLK_N & lt; 1 & gt;
FB_A1_WCLK_P & lt; 0 & gt;
FB_A1_WCLK_N & lt; 0 & gt;
FB_A1_WCLK_P & lt; 1 & gt;
FB_A1_WCLK_N & lt; 1 & gt;
FB_A0_DQ & lt; 7..0 & gt;
FB_A0_DQ & lt; 15..8 & gt;
FB_A0_DQ & lt; 23..16 & gt;
FB_A0_DQ & lt; 31..24 & gt;
FB_A1_DQ & lt; 7..0 & gt;
FB_A1_DQ & lt; 15..8 & gt;
FB_A1_DQ & lt; 23..16 & gt;
FB_A1_DQ & lt; 31..24 & gt;
FB_A0_RESET_L
FB_A1_RESET_L
77 79
FB_B0_CLK
GDDR5_80D
77 79
FB_B0_CLK
GDDR5_80D
GDDR5_CLK
77 79
FB_B1_CLK
GDDR5_80D
GDDR5_CLK
77 79
FB_B1_CLK
GDDR5_80D
GDDR5_CLK
6 77 79
FB_B0_CMD
GDDR5_45SE
GDDR5_CMD
6 77 79
FB_B1_CMD
GDDR5_45SE
GDDR5_CMD
6 77 79
FB_B0_CMD
GDDR5_45SE
GDDR5_CMD
6 77 79
FB_B1_CMD
GDDR5_45SE
GDDR5_CMD
77 79
FB_B0_CMD
GDDR5_45SE
GDDR5_CMD
77 79
FB_B1_CMD
GDDR5_45SE
GDDR5_CMD
77 79
FB_B0_CMD
GDDR5_45SE
GDDR5_CMD
77 79
FB_B1_CMD
GDDR5_45SE
GDDR5_CMD
77 79
FB_B0_CMD
GDDR5_45SE
GDDR5_CMD
77 79
FB_B1_CMD
GDDR5_45SE
GDDR5_CMD
77 79
FB_B0_CMD_R
GDDR5_45SE
GDDR5_CMD
77 79
FB_B1_CMD_R
GDDR5_45SE
GDDR5_CMD
77 79
FB_B0_CMD
GDDR5_45SE
GDDR5_CMD
77 79
FB_B1_CMD
GDDR5_45SE
GDDR5_CMD
6 77 79
FB_B0_EDC0
GDDR5_45SE
GDDR5_EDC
FB_B0_EDC1
GDDR5_45SE
GDDR5_EDC
I306
FB_B0_EDC2
GDDR5_45SE
GDDR5_EDC
6 77 79
I307
FB_B0_EDC3
GDDR5_45SE
GDDR5_EDC
6 77 79
I310
FB_B1_EDC0
GDDR5_45SE
GDDR5_EDC
6 77 79
I309
FB_B1_EDC1
GDDR5_45SE
GDDR5_EDC
6 77 79
I308
6 77 79
I305
6 77 79
FB_B1_EDC2
GDDR5_45SE
GDDR5_EDC
6 77 79
FB_B1_EDC3
GDDR5_45SE
GDDR5_EDC
6 77 79
FB_B0_DBI_L0
GDDR5_45SE
GDDR5_DATA
I311
FB_B0_DBI_L1
GDDR5_45SE
GDDR5_DATA
6 77 79
I312
FB_B0_DBI_L2
GDDR5_45SE
GDDR5_DATA
6 77 79
I313
FB_B0_DBI_L3
GDDR5_45SE
GDDR5_DATA
6 77 79
I316
FB_B1_DBI_L0
GDDR5_45SE
GDDR5_DATA
6 77 79
I315
FB_B1_DBI_L1
GDDR5_45SE
GDDR5_DATA
6 77 79
I314
FB_B1_DBI_L2
GDDR5_45SE
GDDR5_DATA
6 77 79
FB_B1_DBI_L3
GDDR5_45SE
GDDR5_DATA
6 77 79
FB_B0_WCLK0
GDDR5_80D
GDDR5_CMD
6 77 79
FB_B0_WCLK0
GDDR5_80D
GDDR5_CMD
6 77 79
FB_B0_WCLK1
GDDR5_80D
GDDR5_CMD
6 77 79
FB_B0_WCLK1
GDDR5_80D
6 77 79
FB_B1_WCLK0
GDDR5_80D
GDDR5_CMD
6 77 79
FB_B1_WCLK0
GDDR5_80D
GDDR5_CMD
6 77 79
FB_B1_WCLK1
GDDR5_80D
GDDR5_CMD
6 77 79
FB_B1_WCLK1
GDDR5_80D
GDDR5_CMD
6 77 79
FB_B0_DQ_BYTE0
GDDR5_45SE
GDDR5_DATA
6 77 79
FB_B0_DQ_BYTE1
GDDR5_45SE
GDDR5_DATA
6 77 79
FB_B0_DQ_BYTE2
GDDR5_45SE
GDDR5_DATA
6 77 79
FB_B0_DQ_BYTE3
GDDR5_45SE
GDDR5_DATA
6 77 79
FB_B1_DQ_BYTE0
GDDR5_45SE
GDDR5_DATA
6 77 79
FB_B1_DQ_BYTE1
GDDR5_45SE
GDDR5_DATA
6 77 79
FB_B1_DQ_BYTE2
GDDR5_45SE
GDDR5_DATA
6 77 79
FB_B1_DQ_BYTE3
GDDR5_45SE
GDDR5_DATA
6 77 79
I324
FB_B0_CMD_R
GDDR5_45SE
GDDR5_CMD
77 79
I325
FB_B1_CMD_R
GDDR5_45SE
GDDR5_CMD
77 80
77 80
77 80
77 80
6 77 80
6 77 80
6 77 80
6 77 80
D
77 80
77 80
77 80
77 80
77 80
77 80
77 80
77 80
77 80
77 80
6 77 80
6 77 80
6 77 80
6 77 80
6 77 80
6 77 80
6 77 80
6 77 80
6 77 80
6 77 80
6 77 80
6 77 80
6 77 80
6 77 80
6 77 80
6 77 80
C
6 77 80
6 77 80
6 77 80
6 77 80
6 77 80
6 77 80
6 77 80
6 77 80
6 77 80
6 77 80
6 77 80
6 77 80
6 77 80
6 77 80
6 77 80
6 77 80
77 80
77 80
Kepler Net Properties
NET_TYPE
B
GDDR5_CMD
77 79
MUXGFX Net Properties
ELECTRICAL_CONSTRAINT_SET
FB_B0_CLK_P
FB_B0_CLK_N
FB_B1_CLK_P
FB_B1_CLK_N
FB_B0_A & lt; 8..0 & gt;
FB_B1_A & lt; 8..0 & gt;
FB_B0_ABI_L
FB_B1_ABI_L
FB_B0_RAS_L
FB_B1_RAS_L
FB_B0_CAS_L
FB_B1_CAS_L
FB_B0_WE_L
FB_B1_WE_L
FB_B0_CKE_L
FB_B1_CKE_L
FB_B0_CS_L
FB_B1_CS_L
FB_B0_EDC & lt; 0 & gt;
FB_B0_EDC & lt; 1 & gt;
FB_B0_EDC & lt; 2 & gt;
FB_B0_EDC & lt; 3 & gt;
FB_B1_EDC & lt; 0 & gt;
FB_B1_EDC & lt; 1 & gt;
FB_B1_EDC & lt; 2 & gt;
FB_B1_EDC & lt; 3 & gt;
FB_B0_DBI_L & lt; 0 & gt;
FB_B0_DBI_L & lt; 1 & gt;
FB_B0_DBI_L & lt; 2 & gt;
FB_B0_DBI_L & lt; 3 & gt;
FB_B1_DBI_L & lt; 0 & gt;
FB_B1_DBI_L & lt; 1 & gt;
FB_B1_DBI_L & lt; 2 & gt;
FB_B1_DBI_L & lt; 3 & gt;
FB_B0_WCLK_P & lt; 0 & gt;
FB_B0_WCLK_N & lt; 0 & gt;
FB_B0_WCLK_P & lt; 1 & gt;
FB_B0_WCLK_N & lt; 1 & gt;
FB_B1_WCLK_P & lt; 0 & gt;
FB_B1_WCLK_N & lt; 0 & gt;
FB_B1_WCLK_P & lt; 1 & gt;
FB_B1_WCLK_N & lt; 1 & gt;
FB_B0_DQ & lt; 7..0 & gt;
FB_B0_DQ & lt; 15..8 & gt;
FB_B0_DQ & lt; 23..16 & gt;
FB_B0_DQ & lt; 31..24 & gt;
FB_B1_DQ & lt; 7..0 & gt;
FB_B1_DQ & lt; 15..8 & gt;
FB_B1_DQ & lt; 23..16 & gt;
FB_B1_DQ & lt; 31..24 & gt;
FB_B0_RESET_L
FB_B1_RESET_L
GDDR5_CLK
PHYSICAL
NET_TYPE
LVDS_A_CLK
LVDS_85D
LVDS
LVDS_A_CLK
LVDS_85D
LVDS
LVDS_A_DATA
LVDS_85D
LVDS
LVDS_A_DATA
LVDS_85D
LVDS
LVDS_B_CLK
LVDS_85D
LVDS
LVDS_B_CLK
LVDS_85D
LVDS
LVDS_B_DATA
LVDS_85D
LVDS
LVDS_B_DATA
LVDS_85D
LVDS
LVDS_85D
LVDS
LVDS_85D
LVDS
LVDS_85D
LVDS
LVDS_85D
LVDS
LVDS_85D
LVDS
LVDS_85D
LVDS
LVDS_85D
LVDS
LVDS_85D
LVDS
LVDS_85D
ELECTRICAL_CONSTRAINT_SET
SPACING
LVDS
LVDS_85D
LVDS
LVDS_85D
LVDS
LVDS_85D
LVDS
LVDS_A_CLK_P
LVDS_A_CLK_N
LVDS_A_DATA_P & lt; 2..0 & gt;
LVDS_A_DATA_N & lt; 2..0 & gt;
LVDS_B_CLK_P
LVDS_B_CLK_N
LVDS_B_DATA_P & lt; 2..0 & gt;
LVDS_B_DATA_N & lt; 2..0 & gt;
LVDS_CONN_A_CLK_F_P
LVDS_CONN_A_CLK_F_N
LVDS_CONN_B_CLK_F_P
LVDS_CONN_B_CLK_F_N
LVDS_CONN_A_CLK_P
LVDS_CONN_A_CLK_N
LVDS_CONN_A_DATA_P & lt; 2..0 & gt;
LVDS_CONN_A_DATA_N & lt; 2..0 & gt;
LVDS_CONN_B_CLK_P
LVDS_CONN_B_CLK_N
LVDS_CONN_B_DATA_P & lt; 2..0 & gt;
LVDS_CONN_B_DATA_N & lt; 2..0 & gt;
PHYSICAL
GPU_CLK27M_IN
CLK_SLOW_45S
86 89
GPU_CLK27M_OUT
CLK_SLOW_45S
CLK_SLOW
CLK_SLOW_45S
CLK_SLOW
86 89
LVDS_EG_A_CLK
LVDS_85D
LVDS
86 89
LVDS_EG_A_CLK
LVDS_85D
GPU_OSC_27M_XTALIN
GPU_OSC_27M_XTALOUT
GPU_OSC_27M_XTALOUT_R
LVDS_EG_A_CLK_P
LVDS_EG_A_CLK_N
LVDS_EG_A_DATA_P & lt; 2..0 & gt;
LVDS_EG_A_DATA_N & lt; 2..0 & gt;
LVDS_EG_A_DATA_P & lt; 3 & gt;
LVDS_EG_A_DATA_N & lt; 3 & gt;
LVDS_EG_B_DATA_P & lt; 2..0 & gt;
LVDS_EG_B_DATA_N & lt; 2..0 & gt;
LVDS_EG_B_DATA_P & lt; 3 & gt;
LVDS_EG_B_DATA_N & lt; 3 & gt;
DP_EXTA_ML_C_P & lt; 3..0 & gt;
DP_EXTA_ML_C_N & lt; 3..0 & gt;
DP_EXTA_AUXCH_C_P
DP_EXTA_AUXCH_C_N
DP_EG_AUX_CH_P
DP_EG_AUX_CH_N
DP_EXTA_ML_P & lt; 3..0 & gt;
DP_EXTA_ML_N & lt; 3..0 & gt;
DP_EXTA_AUXCH_P
DP_EXTA_AUXCH_N
CLK_SLOW
LVDS
86 89
I326
86 89
LVDS_EG_A_DATA
LVDS_85D
LVDS
86 89
LVDS_EG_A_DATA
LVDS_85D
LVDS
86 89
LVDS_EG_A_DATA3
LVDS_85D
LVDS
LVDS_EG_A_DATA3
LVDS_85D
LVDS
LVDS_EG_B_DATA
LVDS_85D
LVDS
LVDS_EG_B_DATA
LVDS_85D
LVDS
LVDS_EG_B_DATA3
LVDS_85D
LVDS
LVDS_EG_B_DATA3
LVDS_85D
DP_EXTA_ML
DP_85D
DISPLAYPORT
DP_EXTA_ML
DP_85D
DISPLAYPORT
DP_AUX_CH
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
6 85
6 85
6 85
6 85
LVDS
85 86
85 86
6 85 86
6 85 86
85 86
DP_AUX_CH
85 86
DP_85D
DISPLAYPORT
I322
DP_85D
DISPLAYPORT
I320
DP_85D
DISPLAYPORT
I321
DP_85D
DISPLAYPORT
I318
DP_85D
DISPLAYPORT
6 85 86
6 85 86
A
B
SPACING
86 89
81 82
81 82
82
81 89
81 89
81 89
81 89
81 89
81 89
81 87
81 87
86 87
86 87
8 81 86
8 81 86
87
87
87
87
SYNC_MASTER=K92_MLB
SYNC_DATE=08/09/2010
PAGE TITLE
GPU (Kepler) CONSTRAINTS
DRAWING NUMBER
Apple Inc.
051-9585
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
3.0.0
BRANCH
PAGE
107 OF 132
SHEET
100 OF 105
1
A
8
7
6
5
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
4
3
J31 Specific Net Properties
2
1
J31 Specific Net Properties
NET_TYPE
NET_TYPE
TABLE_PHYSICAL_RULE_ITEM
SENSE_1TO1_55S
*
=55_OHM_SE
=1:1_DIFFPAIR
=55_OHM_SE
=55_OHM_SE
=1:1_DIFFPAIR
=1:1_DIFFPAIR
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
SPACING
ELECTRICAL_CONSTRAINT_SET
ENET_100D
ENETCONN
ENETCONN_P & lt; 3..0 & gt;
ENET_100D
THERM_1TO1_55S
*
=55_OHM_SE
=1:1_DIFFPAIR
=55_OHM_SE
=55_OHM_SE
=1:1_DIFFPAIR
ENETCONN
ENETCONN_N & lt; 3..0 & gt;
PHYSICAL
SPACING
37
37
TABLE_PHYSICAL_RULE_ITEM
=1:1_DIFFPAIR
TABLE_PHYSICAL_RULE_ITEM
DIFFPAIR
*
=1:1_DIFFPAIR
=1:1_DIFFPAIR
=1:1_DIFFPAIR
=1:1_DIFFPAIR
=1:1_DIFFPAIR
=1:1_DIFFPAIR
AUDIODIFF
*
=1:1_DIFFPAIR
0.1 MM
0.1 MM
10 MM
0.1 MM
0.1 MM
THERM_1TO1_55S
THERM
CPUTHMSNS_D2_P
51
THERM_1TO1_55S
THERM
CPUTHMSNS_D2_N
51
THERM_1TO1_55S
THERM
CPUTHMSNS_D1_P
51
CLK_PCIE_90D
CLK_PCIE
THERM_1TO1_55S
THERM
CPUTHMSNS_D1_N
51
CLK_PCIE_90D
CLK_PCIE
THERM_1TO1_55S
THERM
GPUTHMSNS_D_P
51
1TO1_DIFFPAIR
THERM_1TO1_55S
SENSE_DIFFPAIR
THERM
GPUTHMSNS_D_N
51
1TO1_DIFFPAIR
THERM_1TO1_55S
THERM
GPU_TDIODE_P
51 81
1TO1_DIFFPAIR
THERM
GPU_TDIODE_N
51 81
1TO1_DIFFPAIR
TABLE_PHYSICAL_RULE_ITEM
I287
SENSE_DIFFPAIR
I288
SENSE_DIFFPAIR
D
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
SENSE_DIFFPAIR
TABLE_SPACING_RULE_ITEM
SENSE
*
=2:1_SPACING
*
=2:1_SPACING
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
CPU_COMP
GND
*
GND_P2MM
?
THERM_1TO1_55S
I392
SENSE_1TO1_55S
SENSE
GPUVCORE_SENSE_P
SENSE_1TO1_55S
SENSE
GPUVCORE_SENSE_N
SENSE_1TO1_55S
SENSE
VCCSAS0_CS_P
SENSE_1TO1_55S
SENSE
VCCSAS0_CS_N
LAYER
LINE-TO-LINE SPACING
SENSE
ISNS_1V5_S3_DDR_P
SENSE_1TO1_55S
SENSE
ISNS_1V5_S3_DDR_N
49
SENSE_1TO1_55S
SENSE
CPUVCCIOS0_CS_P
49 71
SENSE_DIFFPAIR
49 66
I357
*
25 MILS
AREA_TYPE
SPACING_RULE_SET
ENET_MDI
ENETCONN
NET_SPACING_TYPE2
GND
*
GND_P2MM
?
TABLE_SPACING_ASSIGNMENT_ITEM
SENSE_DIFFPAIR
I356
LAYER
LINE-TO-LINE SPACING
WEIGHT
I394
TABLE_SPACING_RULE_ITEM
SENSE
CPUVCCIOS0_CS_N
SENSE
GFXIMVP6_CS_R_P
I312
SENSE_1TO1_55S
SENSE
GFXIMVP6_CS_R_N
*
=STANDARD
NET_SPACING_TYPE1
?
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
CLK_PCIE
GND
GND
*
I393
GND_P2MM
SENSE
GFXIMVP6_CS_P
I314
SENSE_1TO1_55S
GFXIMVP6_CS_N
PCIE
GND
*
LAYER
LINE-TO-LINE SPACING
GND
*
GND_P2MM
WEIGHT
SENSE
SENSE_1TO1_55S
I250
TABLE_SPACING_ASSIGNMENT_ITEM
I256
TABLE_SPACING_RULE_ITEM
GND_P2MM
*
0.20 MM
TABLE_SPACING_ASSIGNMENT_ITEM
1000
SENSE
ISNS_AIRPORT_P
GND
*
SENSE
ISNS_HDD_N
0.20 MM
SB_POWER
*
PWR_P2MM
I283
TABLE_SPACING_ASSIGNMENT_ITEM
1000
I390
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
GND
*
SATA
SB_POWER
*
USB
SB_POWER
*
PWR_P2MM
SENSE_DIFFPAIR
I292
MEM_CMD
GND
*
GND_P2MM
I299
SENSE_DIFFPAIR
SENSE
ISNS_LCDBKLT_P
SENSE
I319
ISNS_LCDBKLT_N
SENSE
SENSE_1TO1_55S
GFXIMVP_ISNS2_P
I300
MEM_CTRL
GND
*
GND
*
GND_P2MM
I301
TABLE_SPACING_ASSIGNMENT_ITEM
NET_SPACING_TYPE2
AREA_TYPE
GFXIMVP_ISNS2_N
I321
I303
TABLE_SPACING_ASSIGNMENT_ITEM
LVDS
GND
*
GND_P2MM
TABLE_PHYSICAL_RULE_HEAD
LAYER
MEM_40S
ALLOW ROUTE
ON LAYER?
*
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
0.09 MM
100 MIL
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
SENSE
ISNS_PP1V0_S0GPU_P
I308
SENSE_DIFFPAIR
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
0.09 MM
100 MIL
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
I307
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
I329
SENSE_DIFFPAIR
*
OVERRIDE
ISNS_PP1V0_S0GPU_N
SENSE_1TO1_55S
SENSE
*
OVERRIDE
OVERRIDE
0.09 MM
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
I359
USB_85D
TOP
OVERRIDE
OVERRIDE
BOTTOM
OVERRIDE
OVERRIDE
0.1 MM
OVERRIDE
100 MIL
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
I361
OVERRIDE
OVERRIDE
I363
I342
SENSE_DIFFPAIR
I341
I346
SENSE_DIFFPAIR
ISNS_PP1V5_S3_N
I367
I369
SENSE
GFXIMVP_ISNS1_P
NET_PHYSICAL_TYPE
AREA_TYPE
I371
PHYSICAL_RULE_SET
GFXIMVP_ISNS1_N
BGA
LVDS_85D
DP_85D
BGA
SENSE_1TO1_55S
SENSE
ISNS_PP1V05_S0GPU_R_P
SATA_90D
BGA
100_DIFF_BGA
ISNS_PP1V05_S0GPU_R_N
SENSE
I378
CLK_PCIE_90D
BGA
AUDIODIFF
AUDIO
SSM2375S_P
61
AUDIO
SSM2375S_N
61
SENSE_1TO1_55S
SENSE
SENSE
ISNS_TBT_N
SENSE_1TO1_55S
SENSE
CPUIMVP_ISNS1G_P
ISNS_TBT_P
SPKRCONN_L_OUT_P
SPKRCONN_L_OUT_N
SPKRCONN_R_OUT_P
SPKRCONN_R_OUT_N
SPKRCONN_S_OUT_P
SPKRCONN_S_OUT_N
AUDIO
AUDIO
50 70
SENSE
CPUIMVP_ISNS1G_N
SENSE_1TO1_55S
SENSE
CPUIMVP_ISNS1G_R_P
CPUIMVP_ISNS1G_R_N
AUDIO
50
SENSE
50
50 70
AUDIO
AUDIO
AUDIO
I381
6 61 62
6 61 62
6 61 62
CPUIMVP_ISNS2G_P
50 70
SENSE
CPUIMVP_ISNS2G_N
50 70
SENSE_1TO1_55S
SENSE
CPUIMVP_ISNS1_P
50 69 70
USB_85D
USB
SENSE
CPUIMVP_ISNS1_N
50 69 70
USB_85D
USB
USB_TPAD_R_P
USB_TPAD_R_N
25 53 95
SENSE_1TO1_55S
SENSE
CPUIMVP_ISNS2_P
50 69 70
SENSE
CPUIMVP_ISNS2_N
50 70
SENSE_1TO1_55S
SENSE
CPUIMVP_ISNS3_P
50 69 70
SENSE
CPUIMVP_ISNS3_N
50 70
SB_POWER
PP3V3_S5
6 7
SENSE_1TO1_55S
SENSE
ISNS_HS_OTHER_P
50
SB_POWER
PP3V3_S0
6 7
SENSE
ISNS_HS_OTHER_N
50
SB_POWER
PP1V5_S3RS0
7
SENSE_1TO1_55S
SENSE
ISNS_HS_GPU_P
50
GND
SENSE
ISNS_HS_GPU_N
50
SENSE_1TO1_55S
SENSE
ISNS_HS_COMPUTING_P
50
SENSE
ISNS_HS_COMPUTING_N
50
SENSE_1TO1_55S
SENSE
CPUIMVP_ISNS_P
50
SENSE
CPUIMVP_ISNS_N
50
SENSE_1TO1_55S
SENSE
ISNS_PP1V0_S0GPU_P
101
101
CPU_VCORE_RMC_P
ISNS_PP1V5_S3_P
101
SENSE_1TO1_55S
SENSE
ISNS_PP1V5_S3_N
101
SENSE_1TO1_55S
SENSE
ISNS_GPU_R_P
SENSE_1TO1_55S
SENSE
ISNS_GPU_R_N
SENSE_1TO1_55S
SENSE
ISNS_CPUVCCSA_R_P
49
SENSE_1TO1_55S
SENSE
ISNS_CPUVCCSA_R_N
49
SENSE_1TO1_55S
SENSE
ISNS_CPUVCCIO_R_P
49
SENSE_1TO1_55S
SENSE
ISNS_CPUVCCIO_R_N
B
105
SENSE
GND
105
CPU_VCORE_RMC_N
SENSE_1TO1_55S
25 53 95
ISNS_PP3V3_S3_N
49
SENSE_DIFFPAIR
SENSE_DIFFPAIR
SENSE_DIFFPAIR
SENSE_DIFFPAIR
SENSE_1TO1_55S
SENSE
CPUIMVP_ISUM_R_P
50
SENSE_1TO1_55S
SENSE
CPUIMVP_ISUM_R_N
50
SENSE_1TO1_55S
SENSE
CPUIMVP_ISUMG_R_P
50
SENSE_1TO1_55S
SENSE
CPUIMVP_ISUMG_R_N
50
SENSE_1TO1_55S
SENSE
ISNS_PP1V5_S3_R_P
SENSE_1TO1_55S
SENSE
ISNS_PP1V5_S3_R_N
103
SENSE_1TO1_55S
SENSE
ISNS_PPGPUFB_S0_R_P
103
SENSE_1TO1_55S
SENSE
ISNS_PPGPUFB_S0_R_N
103
SENSE_1TO1_55S
SENSE
P1V05_GPU_CS_P
78 103
SENSE_1TO1_55S
SENSE
P1V05_GPU_CS_N
78 103
SENSE_1TO1_55S
SENSE
GPUFB_CS_P
SENSE_1TO1_55S
SENSE
GPUFB_CS_N
78 103
SENSE_1TO1_55S
SENSE
ISNS_AIRPORT_R_P
103
SENSE_1TO1_55S
SENSE_DIFFPAIR
SENSE_DIFFPAIR
SENSE_DIFFPAIR
SENSE_DIFFPAIR
SENSE_DIFFPAIR
SENSE_DIFFPAIR
I382
SENSE_DIFFPAIR
SENSE
ISNS_AIRPORT_R_N
103
TABLE_PHYSICAL_RULE_HEAD
103
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
I384
78 103
SYNC_MASTER=K18_MLB
BOTTOM
0.127 MM
Project Specific Constraints
DRAWING NUMBER
Apple Inc.
6.35 MM
TABLE_PHYSICAL_RULE_ITEM
I387
TOP
0.1 MM
SENSE_DIFFPAIR
SENSE
ISNS_TBT_R_N
SENSE_1TO1_55S
SENSE
P1V05_GPU_PEX_IOVDD_SNS_P
SENSE
P1V05_GPU_PEX_IOVDD_SNS_N
SENSE_1TO1_55S
SENSE
GPU_FBVDDQ_SENSE_P
77 78
SENSE
GPU_FBVDDQ_SENSE_N
6
5
R
78 83
SENSE_1TO1_55S
SENSE_DIFFPAIR
I397
051-9585
77 78
SIZE
D
REVISION
3.0.0
78 83
SENSE_1TO1_55S
SENSE_DIFFPAIR
I396
7
104
SENSE
SENSE_1TO1_55S
I388
I398
ISNS_TBT_R_P
SENSE_1TO1_55S
6.35 MM
I395
SYNC_DATE=04/27/2010
PAGE TITLE
TABLE_PHYSICAL_RULE_ITEM
8
6 61 62
SENSE
SENSE
I383
Allow 0.127 mm necks for & gt; 0.127 mm lines for ARD fanout.
MEM_85D
6 61 62
6 61 62
SENSE_1TO1_55S
SENSE
I379
Memory Constraint Relaxations
MEM_72D
C
100_DIFF_BGA
I380
LAYER
61
ISNS_PP3V3_S0GPU_N
SENSE
I377
PHYSICAL_RULE_SET
SSM2375R_N
ISNS_PP3V3_S0GPU_P
SENSE
SENSE_1TO1_55S
I376
TABLE_PHYSICAL_ASSIGNMENT_ITEM
61
AUDIO
103
SENSE
SENSE_1TO1_55S
SENSE_1TO1_55S
I374
I375
AUDIO_DIFFPAIR
I327
SENSE_1TO1_55S
TABLE_PHYSICAL_ASSIGNMENT_ITEM
TABLE_PHYSICAL_ASSIGNMENT_ITEM
61
SSM2375R_P
103
100_DIFF_BGA
I373
61
SSM2375L_N
AUDIO
84
SENSE_DIFFPAIR
I372
TABLE_PHYSICAL_ASSIGNMENT_ITEM
LVDS_85D
SSM2375L_P
AUDIO
84
SENSE
ISNS_PP1V0_S0GPU_N
I370
TABLE_PHYSICAL_ASSIGNMENT_HEAD
AUDIO
AUDIODIFF
ISNS_PP3V3_S3_P
I368
Alternate diffpair width/gap through BGA fanout areas (95-ohm diff)
I328
SENSE_1TO1_55S
SENSE
I354
Graphics ,SATA Constraint Relaxations
AUDIODIFF
61
101
SENSE
I351
I353
61
AUDIODIFF
AUDIO_DIFFPAIR
I325
SENSE_1TO1_55S
I352
I350
I326
SENSE_1TO1_55S
I348
I349
61
AUD_SPKRAMP_SUBIN_N
101
SENSE_DIFFPAIR
I345
I347
AUD_SPKRAMP_SUBIN_P
AUDIO
SENSE_1TO1_55S
SENSE_DIFFPAIR
I336
B
AUD_SPKRAMP_RIN_N
AUDIO
SENSE_1TO1_55S
SENSE_DIFFPAIR
I334
I335
AUDIO
AUDIODIFF
SENSE_1TO1_55S
SENSE_DIFFPAIR
I332
I333
61
SENSE_1TO1_55S
SENSE_DIFFPAIR
I365
I331
AUD_SPKRAMP_RIN_P
SENSE_1TO1_55S
SENSE_DIFFPAIR
I364
I366
AUDIO
SENSE_1TO1_55S
I362
OVERRIDE
61
AUDIODIFF
SENSE_1TO1_55S
SENSE_DIFFPAIR
TABLE_PHYSICAL_RULE_ITEM
OVERRIDE
61
AUD_SPKRAMP_LIN_N
SENSE_1TO1_55S
SENSE_DIFFPAIR
I360
500 MIL
OVERRIDE
0.23 MM
OVERRIDE
57 61
AUD_SPKRAMP_LIN_P
AUDIO
SPK_OUT
TABLE_PHYSICAL_RULE_ITEM
CPU_27P4S
AUD_LO2_R_N
AUDIO
AUDIODIFF
AUDIO_DIFFPAIR
I323
SENSE_1TO1_55S
SENSE_DIFFPAIR
I338
10 mm
ISNS_PP1V5_S3_P
I324
SENSE
TABLE_PHYSICAL_RULE_ITEM
PCIE_85D
AUDIO
AUDIODIFF
57 61
101
SENSE_1TO1_55S
I330
I337
57 61
SPK_OUT
TABLE_PHYSICAL_RULE_ITEM
MEM_72D
OVERRIDE
57 61
AUD_LO2_R_P
SPK_OUT
TABLE_PHYSICAL_RULE_ITEM
OVERRIDE
AUD_LO2_L_N
AUDIO
101
SENSE
SENSE_1TO1_55S
SENSE_DIFFPAIR
I306
AUDIO
84
SENSE
SENSE_1TO1_55S
I304
I305
PHYSICAL_RULE_SET
SENSE_DIFFPAIR
AUDIO
AUDIODIFF
AUDIODIFF
AUDIO_DIFFPAIR
I322
SENSE_1TO1_55S
I302
SPACING_RULE_SET
AUDIODIFF
AUDIODIFF
AUDIO_DIFFPAIR
I320
SENSE_1TO1_55S
SENSE_DIFFPAIR
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
57 61
AUD_LO2_L_P
84
SENSE_1TO1_55S
GND_P2MM
MEM_DQS
57 61
AUD_LO1_R_N
AUDIODIFF
AUDIO_DIFFPAIR
I318
SENSE_1TO1_55S
TABLE_SPACING_ASSIGNMENT_ITEM
AUD_LO1_R_P
AUDIO
41 103
SENSE_1TO1_55S
SENSE_DIFFPAIR
I291
TABLE_SPACING_ASSIGNMENT_ITEM
A
I317
SENSE_1TO1_55S
I389
TABLE_SPACING_ASSIGNMENT_ITEM
AUDIO
AUDIODIFF
AUDIO_DIFFPAIR
I315
GND_P2MM
TABLE_SPACING_ASSIGNMENT_ITEM
C
ISNS_HDD_P
SENSE_1TO1_55S
PWR_P2MM
SPACING_RULE_SET
MEM_CLK
SENSE
SENSE_1TO1_55S
SENSE_DIFFPAIR
I284
TABLE_SPACING_ASSIGNMENT_ITEM
AUDIODIFF
41 103
GND_P2MM
CLK_PCIE
*
AUD_LO1_L_N
103
SENSE_1TO1_55S
SENSE_1TO1_55S
I255
USB
TABLE_SPACING_RULE_ITEM
PWR_P2MM
SENSE_DIFFPAIR
AUD_LO1_L_P
AUDIO
103
SENSE_1TO1_55S
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
ISNS_AIRPORT_N
I316
GND_P2MM
SATA
SENSE_DIFFPAIR
AUDIO
AUDIODIFF
AUDIO_DIFFPAIR
I313
SENSE
AUDIO_DIFFPAIR
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
6 62 63
AUDIODIFF
49 71
SENSE_1TO1_55S
SENSE_DIFFPAIR
6 62 63
BI_MIC_N
AUDIODIFF
I311
SENSE_1TO1_55S
SENSE_DIFFPAIR
TABLE_SPACING_ASSIGNMENT_HEAD
BI_MIC_P
AUDIO
AUDIODIFF
I355
SENSE_1TO1_55S
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
AUDIO_DIFFPAIR
AUDIO
AUDIODIFF
I358
AUDIODIFF
AUDIODIFF
AUDIO_DIFFPAIR
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
65
49
WEIGHT
TABLE_SPACING_RULE_ITEM
65
49 66
SENSE_1TO1_55S
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
D
65
83 84
SENSE_DIFFPAIR
?
=2:1_SPACING
6 32
6 32
65
83 84
SENSE_DIFFPAIR
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
*
SENSE_DIFFPAIR
I391
TABLE_SPACING_RULE_ITEM
AUDIO
PCIE_CLK100M_AP_CONN_P
PCIE_CLK100M_AP_CONN_N
CHGR_CSI_R_P
CHGR_CSI_R_N
CHGR_CSO_R_P
CHGR_CSO_R_N
TABLE_SPACING_ASSIGNMENT_HEAD
?
THERM
PCIE_CLK100M_AP
4
104
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
3
2
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PAGE
108 OF 132
SHEET
101 OF 105
1
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8
7
6
5
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2
1
J31 Board-Specific Spacing & Physical Constraints
TABLE_BOARD_INFO
BOARD LAYERS
BOARD AREAS
BOARD UNITS
(MIL or MM)
ALLEGRO
VERSION
TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM
NO_TYPE,BGA
MM
16.2
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_PHYSICAL_RULE_ITEM
DEFAULT
*
Y
=50_OHM_SE
=50_OHM_SE
10 MM
0 MM
0 MM
TABLE_SPACING_RULE_ITEM
DEFAULT
*
0.1 MM
?
TABLE_PHYSICAL_RULE_ITEM
STANDARD
*
Y
=DEFAULT
=DEFAULT
10 MM
=DEFAULT
=DEFAULT
TABLE_SPACING_RULE_ITEM
STANDARD
*
=DEFAULT
?
BGA_P1MM
*
=DEFAULT
?
BGA_P2MM
*
=DEFAULT
?
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
PHYSICAL_RULE_SET
D
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
55_OHM_SE
TOP,BOTTOM
Y
0.090 MM
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
*
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
*
BGA
P072_SPACE
0.090 MM
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
D
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
55_OHM_SE
*
Y
0.076 MM
0.076 MM
=STANDARD
=STANDARD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
P072_SPACE
*
0.071 MM
?
=STANDARD
DIFFPAIR NECK GAP
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LINE-TO-LINE SPACING
WEIGHT
2X_DIELECTRIC
*
0.140 MM
?
TABLE_SPACING_RULE_ITEM
3X_DIELECTRIC
*
0.210 MM
?
TABLE_SPACING_RULE_ITEM
4X_DIELECTRIC
*
0.280 MM
?
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
LAYER
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
50_OHM_SE
TOP,BOTTOM
Y
0.110 MM
*
Y
0.090 MM
0.090 MM
SPACING_RULE_SET
0.095 MM
50_OHM_SE
TABLE_SPACING_RULE_HEAD
LAYER
LINE-TO-LINE SPACING
WEIGHT
0.15 MM
?
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
=STANDARD
=STANDARD
=STANDARD
1.5:1_SPACING
*
TABLE_SPACING_RULE_ITEM
2:1_SPACING
*
0.2 MM
?
2.5:1_SPACING
*
0.25 MM
?
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
TABLE_SPACING_RULE_ITEM
DIFFPAIR NECK GAP
5X_DIELECTRIC
*
0.350 MM
?
TABLE_SPACING_RULE_ITEM
7X_DIELECTRIC
*
0.490 MM
?
TABLE_SPACING_RULE_ITEM
10X_DIELECTRIC
*
0.700 MM
?
TABLE_PHYSICAL_RULE_ITEM
45_OHM_SE
TOP,BOTTOM
Y
0.13 MM
*
Y
0.099 MM
0.099 MM
TABLE_SPACING_RULE_ITEM
0.13 MM
45_OHM_SE
3:1_SPACING
*
0.3 MM
?
TABLE_PHYSICAL_RULE_ITEM
=STANDARD
=STANDARD
TABLE_SPACING_RULE_ITEM
=STANDARD
4:1_SPACING
*
0.4 MM
?
5:1_SPACING
*
0.5 MM
?
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
40_OHM_SE
TOP,BOTTOM
Y
0.165 MM
40_OHM_SE
*
Y
0.135 MM
0.090 MM
=STANDARD
=STANDARD
=STANDARD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
37_OHM_SE
TOP,BOTTOM
Y
0.185 MM
0.095 MM
37_OHM_SE
*
Y
0.155 MM
0.090 MM
=STANDARD
=STANDARD
=STANDARD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
27P4_OHM_SE
TOP,BOTTOM
Y
0.310 MM
TABLE_SPACING_RULE_ITEM
0.095 MM
0.095 MM
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
C
C
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
TABLE_PHYSICAL_RULE_ITEM
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM
27P4_OHM_SE
*
Y
0.250 MM
0.1 MM
=STANDARD
=STANDARD
=STANDARD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
=STANDARD
1:1_DIFFPAIR
*
Y
=STANDARD
=STANDARD
=STANDARD
0.1 MM
0.1 MM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
72_OHM_DIFF
*
N
=STANDARD
=STANDARD
=STANDARD
=STANDARD
72_OHM_DIFF
ISL3,ISL4,ISL9,ISL10
Y
0.154 MM
0.154 MM
0.200 MM
0.200 MM
72_OHM_DIFF
ISL2,ISL11
Y
0.154 MM
0.154 MM
0.200 MM
0.200 MM
72_OHM_DIFF
TOP,BOTTOM
Y
0.175 MM
0.175 MM
0.200 MM
0.200 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
80_OHM_DIFF
*
N
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
80_OHM_DIFF
ISL3,ISL4,ISL9,ISL10
Y
0.105 MM
0.091 MM
0.120 MM
0.080 MM
80_OHM_DIFF
ISL2,ISL11
Y
0.105 MM
0.091 MM
0.120 MM
0.080 MM
80_OHM_DIFF
TOP,BOTTOM
Y
0.135 MM
0.135 MM
0.160 MM
0.160 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
85_OHM_DIFF
*
N
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
85_OHM_DIFF
ISL3,ISL4,ISL9,ISL10
Y
0.110 MM
0.090 MM
0.180 MM
0.180 MM
85_OHM_DIFF
ISL2,ISL11
Y
0.110 MM
0.090 MM
0.180 MM
0.180 MM
85_OHM_DIFF
TOP,BOTTOM
Y
0.125 MM
0.090 MM
0.190 MM
0.190 MM
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
90_OHM_DIFF
*
N
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
B
B
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
90_OHM_DIFF_ALT
*
N
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
90_OHM_DIFF_ALT
ISL3,ISL4,ISL9,ISL10
Y
0.099 MM
0.099 MM
0.280 MM
0.280 MM
90_OHM_DIFF_ALT
ISL2,ISL11
Y
0.099 MM
0.099 MM
0.280 MM
0.280 MM
90_OHM_DIFF_ALT
TOP,BOTTOM
Y
0.130 MM
0.130 MM
0.300 MM
0.300 MM
PHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_ITEM
90_OHM_DIFF
ISL3,ISL4,ISL9,ISL10
Y
0.102 MM
0.090 MM
0.220 MM
0.220 MM
90_OHM_DIFF
ISL2,ISL11
Y
0.102 MM
0.090 MM
0.220 MM
0.220 MM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
90_OHM_DIFF
TOP,BOTTOM
Y
0.115 MM
0.090 MM
0.230 MM
0.230 MM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
100_OHM_DIFF
*
N
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
100_OHM_DIFF
ISL3,ISL4,ISL9,ISL10
Y
0.080 MM
0.080 MM
0.200 MM
0.200 MM
100_OHM_DIFF
ISL2,ISL11
Y
0.080 MM
0.080 MM
0.200 MM
0.200 MM
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
100_DIFF_BGA
*
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
100_DIFF_BGA
ISL3,ISL4
Y
0.075 MM
0.075 MM
0.125 MM
0.125 MM
100_DIFF_BGA
ISL9,ISL10
Y
0.075 MM
0.075 MM
0.125 MM
0.125 MM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
100_OHM_DIFF
TOP,BOTTOM
Y
0.089 MM
0.089 MM
0.220 MM
0.220 MM
NOTE: 100_DIFF_BGA is 100-ohms differential impedance on outer layers and 95-ohms on inner layers.
TABLE_PHYSICAL_RULE_HEAD
A
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
110_OHM_DIFF
*
N
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
110_OHM_DIFF
ISL3,ISL4,ISL9,ISL10
Y
0.065 MM
0.065 MM
0.2 MM
0.2 MM
110_OHM_DIFF
ISL2,ISL11
Y
0.065 MM
0.065 MM
0.2 MM
0.2 MM
110_OHM_DIFF
TOP,BOTTOM
Y
0.075 MM
0.075 MM
0.330 MM
0.330 MM
SYNC_MASTER=K18_MLB
TABLE_PHYSICAL_RULE_ITEM
SYNC_DATE=04/27/2010
PAGE TITLE
TABLE_PHYSICAL_RULE_ITEM
PCB Rule Definitions
DRAWING NUMBER
TABLE_PHYSICAL_RULE_ITEM
Apple Inc.
TABLE_PHYSICAL_RULE_ITEM
051-9585
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
3.0.0
BRANCH
PAGE
109 OF 132
SHEET
102 OF 105
1
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8
7
6
5
4
DDR 1.5V S3 (CPU & Memory) Current Sense (IM1C)
3
2
1
PCH Core (PCH VCCIO) Current Sense (ISBC)
Gain: 231.4x, EDP: 14.1 A
Gain: 100x, EDP: 11.4 A
Rsense: 0.001 (RD010)
Rsense: 0.002 (R9840)
V accross Rsense: 14.1 mV
V accross Rsense: 22.8 mV
Gain needed: 234.1x
104 103 49 7
XWLOADISNS:YES
=PP3V3_S3_ISNS
Gain needed: 144.7x
=PP3V3_S0_ISNS
104 103 50 49 7
N0STUFF
1
=PP1V5_S3_ISNS_R
XWLOADISNS:YES
D
XWD010
2
4.32K
NC_ISNS_PP1V5_S3P
1
1
2
SM
101 ISNS_PP1V5_S3_R_P
OUT =PP1V5_S3_ISNS
3
RD012
4.32K
NC_ISNS_PP1V5_S3N
1
5
+
2
OPA333DCKG4
4.53K
1
2
1%
1/20W
MF
201
2
1
XWLOADISNS:YES
OUT
NC_PCHVCCIOS0_CSN
46
CD019
5
IN-
4
IN+
SC70
6
OUT
N0STUFF
REF
1
ISNS_PP1V05_S0PCH_IOUT
4.53K
RD014
1M
20%
6.3V
X5R
0201
D
SMC_PCH_ISENSE
2
1
2
PLACE_NEAR=U4900.A8:5MM
1%
1/16W
MF-LF
2 402
46
CD039
0.22UF
GND
XWLOADISNS:YES
OUT
XWLOADISNS:YES
1%
1/20W
MF
201
1
0.22UF
2
1
PLACE_NEAR=U4900.A7:5MM
RD039
INA214
NC_PCHVCCIOS0_CSP
SMC_CPUMEM_ISENSE
ISNS_PP1V5_S3_R_N
2
1%
1/16W
MF-LF
402
N0STUFF
20%
10V
CERM
402
2
UD030
RD019
V-
-
V+
PLACE_NEAR=U4900.A8:5MM
4 ISNS_PP1V5_S3_IOUT
0.1UF
3
20%
10V
CERM
402
SC70-5
V+
1%
1/16W
MF-LF
402
1
7
UD010
RD011
CD030
2
IN
1
XWLOADISNS:YES
0.1UF
XWLOADISNS:YES
7
CD015
20%
6.3V
X5R
0201
PLACE_NEAR=U4900.A7:5MM
RD015
XWLOADISNS:YES
GND_SMC_AVSS
1M
1
2
45 46 49 50 103
XWLOADISNS:YES
1%
1/16W
MF-LF
402
SIGNAL_MODEL=EMPTY
GND_SMC_AVSS
45 46 49 50 103
HDD Current Sense (IHDC)
SIGNAL_MODEL=EMPTY
Gain: 1000x, EDP: 2.5 A (12.5 W)
Rsense: 0.001 (R4599)
V accross Rsense: 2.5 mV
GPU 1.05V Current Sense (IG1C)
Gain needed: 1320x
7
=PP5V_S0_ISNS
Gain: 649.35x, EDP: 4.9 A
104 103 50 49 7
V+
=PP3V3_S0_ISNS
LOADISNS:YES
1
LOADISNS:YES
UD020
RD021
IN
P1V05_GPU_CS_P
1
1.54K
2
8
101 ISNS_PP1V05_S0GPU_R_P
IN
P1V05_GPU_CS_N
1
1.54K
CD020
7 ISNS_PP1V05_S0GPU_IOUT
THRM
101 41
RD029
4.53K
1
2
1%
1/20W
MF
201
4
SMC_GPU_1V05_ISENSE
1
2
1
RD023
5
IN-
SC70
OUT
6
ISNS_HDD_IOUT
1M
OUT
IN
ISNS_HDD_P
4
IN+
REF
1
1
Airport Current Sense (IAPC)
45 46 49 50 103
2
Gain: 606x, EDP: 1 A
Rsense: 0.005 (R3552)
1%
1/20W
MF
201
LOADISNS:YES
V accross Rsense: 5 mV
SIGNAL_MODEL=EMPTY
Gain needed: 660x
XWLOADISNS:YES
=PP3V3_S3_ISNS
NC_ISNS_AIRPORTP
1.65K
1
1
2
101 ISNS_AIRPORT_R_P
1%
1/16W
MF-LF
402
V accross Rsense: 11 mV
=PP3V3_S0_ISNS
LOADISNS:YES
RD041
8
3.40K
2
IN
1
XWLOADISNS:YES
1
4.53K
THRM
1%
1/20W
MF
201
4
2
SMC_GPU_FB_ISENSE
1
ISNS_PPGPUFB_S0_R_N
2
1%
1/20W
MF
201
1
RD043
2
OUT
46
1
PLACE_NEAR=U4900.B8:5MM
RD069
SC70-5
4 ISNS_AIRPORT_IOUT
1
4.53K
2
1%
1/20W
MF
201
V2
RD063
1M
2
CD049
1%
1/16W
MF-LF
402
SMC_AIRPORT_ISENSE
1
PART NUMBER
CD069
0.22UF
20%
6.3V
X5R
0201
XWLOADISNS:YES
GND_SMC_AVSS
1M
1
2
SIGNAL_MODEL=EMPTY
DESCRIPTION
REFERENCE DES
2
RES,100K,201
CD029,CD049
CRITICAL
BOM OPTION
LOADISNS:NO
3
RES,100K,201
CD019,CD039,CD069
XWLOADISNS:NO
45 46 49 50 103
2
1%
1/20W
MF
201
QTY
117S0008
GND_SMC_AVSS
1M
1
LOADISNS:YES
SIGNAL_MODEL=EMPTY
B
45 46 49 50 103
XWLOADISNS:YES
1%
1/16W
MF-LF
402
117S0008
RD044
46
RD064
XWLOADISNS:YES
SIGNAL_MODEL=EMPTY
PLACE_NEAR=U4900.H2:5MM
1%
1/20W
MF
201
OUT
PLACE_NEAR=U4900.B8:5MM
20%
6.3V
X5R
0201
LOADISNS:YES
1M
LOADISNS:YES
1%
1/16W
MF-LF
402
0.22UF
9
2
OPA333DCKG4
5
XWLOADISNS:YES
20%
10V
CERM
402
ISNS_AIRPORT_R_N
RD049
1 ISNS_PPGPUFB_S0_IOUT
V-
3.40K
GPUFB_CS_N
OPA2333
V+
2
RD042
101 78
PLACE_NEAR=U4900.H2:5MM
DFN
3
101 ISNS_PPGPUFB_S0_R_P
2
-
2
2
LOADISNS:YES
UD020
1%
1/20W
MF
201
1.65K
1
+
V+
3
RD062
NC_ISNS_AIRPORTN
LOADISNS:YES
UD060
RD061
Gain: 294.12x, EDP: 11 A
CD060
0.1UF
XWLOADISNS:YES
Rsense: 0.001 (R8360)
1
45 46 49 50 103
PLACE_NEAR=U4900.B7:5MM
XWLOADISNS:YES
GPUFB_CS_P
C
20%
6.3V
X5R
0201
PLACE_NEAR=U4900.B4:5MM
GPU FB (1.35V/1.5V) Current Sense (IG3C)
IN
46
CD059
GND_SMC_AVSS
1
101 78
OUT
0.22UF
2
20%
6.3V
X5R
0201
104 103 49 7
B
1
CD029
GND_SMC_AVSS
1M
SIGNAL_MODEL=EMPTY
104 103 50 49 7
SMC_HDD_ISENSE
2
1%
1/20W
MF
201
GND
46
RD024
LOADISNS:YES
Gain needed: 300x
4.53K
1
LOADISNS:YES
1%
1/20W
MF
2 201
LOADISNS:YES
ISNS_HDD_N
0.22UF
ISNS_PP1V05_S0GPU_R_N
1%
1/20W
MF
201
OUT
PLACE_NEAR=U4900.B7:5MM
9
2
101 41
LOADISNS:YES
V-
6
RD059
INA212
20%
10V
CERM
402
DFN
V+
RD022
101 78
OPA2333
5
1%
1/20W
MF
201
2
PLACE_NEAR=U4900.B4:5MM
UD050
0.1UF
LOADISNS:YES
20%
10V
CERM
402
2
2
Gain needed: 673.47x
101 78
0.1UF
3
V accross Rsense: 4.9 mV
C
CD050
1
Rsense: 0.001 (RD8310)
LOADISNS:YES
SIGNAL_MODEL=EMPTY
GPU FB (1.35V/1.5V) Voltage Sense (VG3C)
XWD080
RD089
SM
78 7
=PP1V5R1V35_GPU_REG
1
2
GPUFBVSENSE_IN
PLACE_NEAR=R8360.2:5 MM
1
4.53K
1%
1/20W
MF
201
SMC_GPU_FB_VSENSE
2
46
CD089
0.22UF
PLACE_NEAR=U4900.G2:5MM
2
20%
6.3V
X5R
0201
GND_SMC_AVSS
A
OUT
PLACE_NEAR=U4900.G2:5MM
1
45 46 49 50 103
SYNC_MASTER=J31_YONAS
SYNC_DATE=09/12/2011
PAGE TITLE
Power Sensors: SMC Extended
DRAWING NUMBER
Apple Inc.
051-9585
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
3.0.0
BRANCH
PAGE
130 OF 132
SHEET
103 OF 105
1
A
8
7
6
10
=PP5V_S5_DEBUG_ADC_AVDD
1
5%
1/16W
MF-LF
402
1
DEBUG_ADC
CD100
CD101
1
1
10UF
20%
6.3V
X5R
603
20%
10V
CERM
402
2
Debug ADC
22
104
104
104
104
8
8
5
6
105
COM
23
24
1
2
3
4
SDA
SCL
14
DEBUG_ADC
1
D
17
16
5%
1/16W
MF-LF
402
ADC_SDA
ADC_SCL
33
=I2C_SMC_ADCS_SCL
2
IN
48
DEBUG_ADC
ADC_REFCOMP
1
THRM
PAD
CD104
1
PLACE_NEAR=U4900.L8:10MM
CD105
0.1UF
25
20
19
RD102
ADC_VREF
8
48
PLACE_NEAR=U4900.K8:10MM
5%
1/16W
MF-LF
402
7
BI
DEBUG_ADC
1
REFCOMP
18
=I2C_SMC_ADCS_SDA
2
15
VREF
11
20%
6.3V
X5R
603
33
DEBUG_ADC
GND
9
7
RD101
AD0
AD1
QFN
10
=PP5V_S5_DEBUG_ADC_DVDD
DVDD
LTC2309
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
2
5%
1/16W
MF-LF
402
10UF
UD100
ADC_CH0
ADC_CH1
ADC_CH2
ADC_CH3
ADC_CH4
ADC_CH5
ADC_CH6
ADC_CH7
104
1
10UF
20%
10V
CERM
402
20%
6.3V
X5R
603
2
2
DEBUG_ADC
CD106
2.2UF
2
DEBUG_ADC
20%
6.3V
CERM
402-LF
DEBUG_ADC
LCD Backlight Current Sense (IBLC)
3.3V S3 Current Sense (IR1C)
Gain: 500x. EDP: 0.7 A
C
Gain: 500x. EDP: 1.8 A
Rsense: 0.005 (RD120)
V across Rsense: 5.4 mV
104 103 50 49 7
Gain needed: 611x
=PP3V3_S0_ISNS
104 103 49 7
1
3
20%
10V
CERM
402
2
UD120
NC_ISNS_LCDBKLTN
2
5
IN-
SC70
DEBUG_ADC
OUT
RD129
ISNS_LCDBKLT_IOUT
6
324K
1
SM
NC_ISNS_LCDBKLTP
4
IN+
REF
1
1
UD160
XWD160
104
2
NC_ISNS_PP3V3_S3N
5
IN-
NC_ISNS_PP3V3_S3P
OUT
CD129
1.0UF
2
2
DEBUG_ADC
DEBUG_ADC
20%
10V
CERM
402
2
PLACE_NEAR=UD100.1:5MM
DEBUG_ADC
4
IN+
SC70
OUT
6
RD169
ISNS_PP3V3_S3_IOUT
1
SM
GND
PPBUS_SW_LCDBKLT_PWR
OUT =PP3V3_S3_ISNS
INA211
ADC_CH4
2
1%
1/20W
MF
201
1
IN
0.1UF
V+
104 103 49 7
INA211
XWD120
CD160
1
PLACE_NEAR=UD100.22:5MM
0.1UF
V+
OUT =PPBUS_SW_BKL
=PP3V3_S3_ISNS
DEBUG_ADC
CD120
3
Gain needed: 942x
90
C
Rsense: 0.003 (RD164)
V across Rsense: 3.5 mV
90 7
1
21
AVDD
I2C Address: 0x10 / 0x11
ADC Range: 0V to 4.096V
LSB: 0.001V
CD103
2
DEBUG_ADC
DEBUG_ADC
13
2
DEBUG_ADC
D
1
0.1UF
20%
10V
CERM
402
12
2
10
1
CD102
0.1UF
2
RD104
PP5V_S5_DEBUG_ADC_DVDD_FILT
PP5V_S5_DEBUG_ADC_AVDD_FILT
2
3
REF
324K
2
1%
1/20W
MF
201
1
ADC_CH3
1
GND
7
IN
=PP3V3_S3_ISNS_R
DEBUG_ADC
DEBUG_ADC
OUT
104
CD169
1.0UF
1
20%
6.3V
X5R
0201-MUR
2
2
7
4
DEBUG_ADC
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=5V
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=5V
RD103
5
20%
6.3V
X5R
0201-MUR
DEBUG_ADC
PLACE_NEAR=UD100.1:5MM
PLACE_NEAR=UD100.22:5MM
LCD Backlight Voltage Sense (VBLC)
T29 Current Sense (IHSP)
Divider: ~1/22
Gain: 215.5x. EDP: 3 A
XWD150
Rsense: 0.005 (RD140)
SM
85 8 6
PPVOUT_S0_LCDBKLT
1
2
V across Rsense: 15 mV
VOUT_S0_LCDBKLT_XW
Gain needed: 220x
104 103 50 49 7
B
1
=PP3V3_S0_ISNS
DEBUG_ADC
RD156
1
1M
1%
1/16W
MF-LF
2 402
DEBUG_ADC
PLACE_NEAR=UD100.2:5MM
DEBUG_ADC
1
VOUT_S0_LCDBKLT_DIV
1
7
RD159
324K
2
1%
1/20W
MF
201
RD157
ADC_CH0
1
OUT
DEBUG_ADC
2
NC_ISNS_TBTP
4.64K
1
SM
104
CD159
34 7
20%
6.3V
X5R
0201-MUR
OUT =PP1V05_TBT_RTR
2
PLACE_NEAR=UD100.2:5MM
ISNS_TBT_R_P
4.64K
1
1
2
+
-
2
OPA333DCKG4
5
4
20%
10V
CERM
402
DEBUG_ADC
PLACE_NEAR=UD100.24:5MM
RD149
SC70-5
V+
3
RD142
NC_ISNS_TBTN
ISNS_TBT_IOUT
1
324K
1%
1/20W
MF
201
V2
2
ADC_CH2
1
1
RD143
2
104
20%
6.3V
X5R
0201-MUR
DEBUG_ADC
1M
DEBUG_ADC
OUT
CD149
1.0UF
ISNS_TBT_R_N
2
1%
1/20W
MF
201
DEBUG_ADC
101
1%
1/20W
MF
201
1
1.0UF
2
UD140
RD141
XWD140
46.4K
1%
1/16W
MF-LF
2 402
IN
B
0.1UF
DEBUG_ADC
DEBUG_ADC
=PP1V05_TBT_RTR_R
CD140
PLACE_NEAR=UD100.24:5MM
1%
1/20W
MF
201
RD144
1M
1
2
DEBUG_ADC
SIGNAL_MODEL=EMPTY
1%
1/20W
MF
201
DEBUG_ADC
SIGNAL_MODEL=EMPTY
GPU 3.3V S0 Current Sense (IG2C)
Gain: 500x. EDP: 1.0 A
Rsense: 0.005 (RD170)
V across Rsense: 5 mV
Gain needed: 660x
104 103 50 49 7
=PP3V3_S0_ISNS
1
V+
7
OUT =PP3V3_S0GPU_ISNS
CD170
0.1UF
3
A
2
UD170
20%
10V
CERM
402
DEBUG_ADC
PLACE_NEAR=UD100.3:5MM
RD179
INA211
XWD170
2
NC_ISNS_PP3V3_S0GPUN
5
IN-
SC70
OUT
6
ISNS_PP3V3_S0GPU_IOUT
SM
NC_ISNS_PP3V3_S0GPUP
4
IN+
REF
324K
1
2
1%
1/20W
MF
201
1
GND
=PP3V3_S0GPU_ISNS_R
DEBUG_ADC
ADC_CH5
1
OUT
DRAWING NUMBER
104
Apple Inc.
CD179
20%
6.3V
X5R
0201-MUR
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
DEBUG_ADC
PLACE_NEAR=UD100.3:5MM
8
7
6
051-9585
5
4
3
2
SIZE
D
REVISION
R
1.0UF
2
2
IN
SYNC_DATE=09/12/2011
Power Sensors: Debug ADC
1
7
SYNC_MASTER=J31_YONAS
PAGE TITLE
DEBUG_ADC
3.0.0
BRANCH
PAGE
131 OF 132
SHEET
104 OF 105
1
A
8
7
6
5
4
3
2
1
www.qdzbwx.com
D
D
CPU Rippler Voltage Sense (VCRP)
LD200
120OHM-0.3A
7
=PP5V_S0_RMC
1
PP5V_S0_RMC_FLT
2
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=5V
0402
CPURIPPLE_ENG
1
PLACE_NEAR=CD310.1:2MM
CD210
XWD200
49 14 12 7
=PPVCORE_S0_CPU
2
1
PPVCORE_S0_RMC
1
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.1V
C
7
=PP1V05_S0_RMC
1
10UF
CPU_VCORE_C
10%
16V
X5R
402
RD206
1
CPURIPPLE_ENG
PP1V05_S0_RMC_R
2
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
5%
1/16W
MF-LF
402
10.2
CPURIPPLE_ENG
2
C
0.1%
1/16W
TF
402
PLACE_NEAR=RD305.1:5MM
RD200
100
2
CD200
20%
6.3V
2 CERM-X5R
0402
CPURIPPLE_ENG
1UF
SM
DD200
SOD-523
A
K
CPURIPPLE_ENG
CPURIPPLE_ENG
BAT54XV2T1
CD204
RD2011
1
RD203 1
11K
10UF
20%
6.3V
CERM-X5R 2
0402
CPURIPPLE_ENG
CD201
1.00K
0.1%
1/16W
MF
402 2
0.1%
1/16W
MF
402
10%
16V 2
X5R
402-1
CPURIPPLE_ENG
2
CPURIPPLE_ENG
CPURIPPLE_ENG
1
0.1UF
1V05_S0_RMC_DIV
NO_TEST=TRUE
1
RD2021
10%
16V 2
X5R
402-1
0.1%
1/16W
MF
402 2
CD205
CPURIPPLE_ENG
0.1%
1/16W
TF
402
RD204 1
11K
0.1UF
1.00K
0.1%
1/16W
MF
402
10.2
2
CPURIPPLE_ENG
OPA2365
DD201
SO-8
V+
1
RD205
1
SIGNAL_MODEL=EMPTY
UD200
8
3
COMP_CPU_VCORE_RMC
SOD-523
A
K
101
CPU_VCORE_RMC_P
8
5
NO_TEST=TRUE
CPU_VCORE_RMC_DIV
V-
2
NO_TEST=TRUE
CPURIPPLE_ENG
4
PLACE_NEAR=UD100.23:5MM
UD200
OPA2365
RD220
SO-8
V+
7
BAT54XV2T1
VSNS_CPU_VCORE_RMC_OUT
NO_TEST=TRUE
CPURIPPLE_ENG
101
CPU_VCORE_RMC_N
V-
6
NO_TEST=TRUE
4
1
324K
CPURIPPLE_ENG
CPURIPPLE_ENG
1
OUT
104
CD220
1.0UF
20%
6.3V
2 X5R
0201-MUR
CPURIPPLE_ENG
2
CPURIPPLE_ENG
CPURIPPLE_ENG
B
ADC_CH1
2
1%
1/20W
MF
201
PLACE_NEAR=UD100.23:5MM
RD207
10
1
B
RD208
2
1
5%
1/16W
MF-LF
402
1K
2
1%
1/16W
MF-LF
402
PLACE_NEAR=RD305.1:5MM
CPURIPPLE_ENG
CPURIPPLE_ENG
A
SYNC_MASTER=J31_YONAS
SYNC_DATE=08/24/2011
PAGE TITLE
Power Sensors: CPU Ripple
DRAWING NUMBER
Apple Inc.
051-9585
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
3.0.0
BRANCH
PAGE
132 OF 132
SHEET
105 OF 105
1
A