To jest wczesny bipolarny ośmiobitowy układ wejścia/wyjścia ze strobem i wyjściem do przerwania, opracowany przez Intel, był produkowany przez wiele firm, także w demoludach, w PRL bodajże jako UCY74S412. Datasheet Intel M8212 nie jest zbyt obszerny ani specjalnie czytelny, więc załączam PDF, który znalazłem w swoich zbiorach.
Schottky Bipolar 8212
EIGHT-BIT INPUT/OUTPUT PORT
• 3.65V Output High Voltage
for Direct Interface to 8080
CPU or 8008 CPU
• Asynchronous Register
Clear
• Replaces Buffers, Latches
and Multiplexers in Microcomputer Systems
• Reduces System Package
Count
• Fully Parallel 8-Bit Data
Register and Buffer
• Service Request Flip-Flop
for Interrupt Generation
• Low Input Load Current .25 mA Max.
• Three State Outputs
• Outputs Sink 1.5 mA
The 8212 input/output port consists of an 8-bit latch with 3-state output buffers along with control and device selection
logic. Also included is a service request flip-flop for the generation and control of interrupts to the microprocessor.
The device is multimode in nature. It can be used to implement latches, gated buffers or multiplexers. Thus, all of the principal peripheral and input/output functions of a microcomputer system can be implemented with this device.
PIN CONFIGURATI " ON
LOGIC DIAGRAM
SERVICE REQUEST FF
\
vee
OS1
MO
INT
01,
Dl a
DO,
OOa
01 2
01 7
0°2
0°7
01 3
01 6
00 3
0°6
01 4
015
0°4
I!D OS2
~ MO - - - - + -........L-~
[i & gt; STB - - - - . . . - - - -
CLR
GND
-~
[DOS1
0°5
STB
DEVICE SELECTION
DS 2
11 & gt; 01 3 - - - - - - -....................
[[ & gt; 01 4 ---------+--+-4
PIN NAMES
01,.01 &
[9DI5-------~
.......
DATA IN
oo,-DOa
DSi-DS2
MD
DATA OUT
STB
INT
CLR
DEVICE SELECT
MODE
STROBE
INTERRUPT (ACTIVE LOW)
CLEAR (ACTIVE LOW)
[g & gt; 01 8 - - - - - - - - - 1 -.......
(ACTIVE LOW)
5-101
OUTPUT
BUFFER
SCHOTTKY BIPOLAR 8212
Functional Description
Data Latch
The 8 flip-flops that make up the data latch are of a
" 0 " type design. The output (Q) of the flip-flop will
follow th~ data input (0) while the clock input (C) is
high. Latching will occur when the clock (C) returns
low.
The data latch is cleared by an asynchronous reset
input (CLR). (Note: Clock (C) Overides Reset (CLR).)
Output Buffer
The outputs of the data latch (Q) are connected to
3-state, non-inverting output buffers. These buffers
have a common control line (EN); this control line
either enables the buffer to transmit the data from
the outputs of the data latch (Q) or disables the
buffer; forcing the output into a high impedance
state. (3 -state)
This high-impedance state allows the designer to
connect the 8212 directly onto the microprocessor
bi-directional data bus.
Service Request Flip-Flop
The (SR) flip-flop is used to generate and control
interrupts in microcomputer systems. It is asynchronously set by the CLR input (active low). When
the (SR) flip-flop is.set it is in the non-interrupting
state.
The output of the (SR) flip-flop (Q) is connected to
an inverting input of a " NOR " gate. The other input
to the " NOR " gate is non-inverting and is connected
to the device selection logic (081 • 082). The output
of the " NOR " gate (INT) is active low (interrupting
state) for connection to active low input priority
generating circuits.
SERVICE REQUEST FF
\
DEVICE SELECTION
-~
[I & gt; OS1
[g & gt; OS2
~ MO - - - - t o 4 '_ _~
[ j j & gt; S T B - -............
OUTPUT
BUFFER
Control Logic
The 8212 has control inputs 051, 052, MO and
STB. These inputs are used to control device selection, data latching, output buffer state and service
request flip-flop.
DATA LATCH
[ [ & gt; 0 1 2 - - - - - - - - + -.....
DS1, DS2 (Device Select)
These 2 inputs are used for device selection. When
OS1 is low and OS2 is high (OS1 • OS2) the device is
selected. In the selected state the output buffer is
enabled and the service request flip-flop (SR) is
asynchronously set.
MD (Mode)
This input is used to control the state of the output
buffer and to determine the source of the clock input
(C) to the data latch.
When MO is high (output mode) the output buffers
are enabled and the source of clock (C) to the data
latch is from the device selection logic (051 • OS2).
When MD is low (input mode) the output buffer state
is det~rmined by the device selection logic (OS1 •
OS2) and the source of clock (C) to the data latch is
the.STB (Strobe) input.
ff§ & gt; D IS - - - - - - -..............
~ 01 7
~D18-------~.....
IE & gt; C L R - - - - - 0 0 1
~~_
.......--'
(ACTIVE LOW)
STB
~
MD
0
0
, ,
, ,
0
0
STB (Strobe)
This input is used as the clock (C) to the data latch
for the input mode MO = 0) and to synchronously
reset the service request flip-flop (SR).
-------+-1-1
0
5-102
,
,
, ,
, -,- ,
~
Note that the SR flip-flop is negative edge triggered.
0
0
(DS,-DS2)
0
0
0
0
0
C'i:R -
1---
DATA OUT EaUALS
3-STATE
3=STAte-----DATA LATCH
DATA LATCH
DATA LATCH
DATA IN
DATA IN
DATA IN
RESETS DATA LATCH
SETS SR FLlP·FLOP
(NO EFFECT ON OUTPUT BUFFER)
CLR
0
,
,
,
0
1
(OS1-0S2)
0
STB
1
1
0
'-
,
,
0
0
0
0
~I
, ,
,
, ,
-SR
0
1
1
-INTERNAL SR FLIP-FLOP
tNT
0
0
0
0
SCHOTTKY BIPOLAR 8212
Applications Of The 8212 -- For Microcomputer Systems
I
II
III
IV
V
VI
Basic Schematic Symbol
Gated Buffer
Bi-Directional Bus Driver
Interrupting Input Port
Interrupt Instruction Port
Output Port
VII
VIII
IX
8080 Status Latch
8008 System
8080 System:
8 Input Ports
8 Output Ports
8 Level Priority Interrupt
I. Basic Schematic Symbols
Two examples of ways to draw the 8212 on system
schematics-(1) the top being the detailed view
showing pin numbers, and (2) the bottom being the
symbolic view showing the system input or output
as a system bus (bus containing 8 parallel lines).
The output to the data bus is symbolic in referencing 8 parallel lines.
BASIC SCHEMATIC SYMBOLS
OUTPUT DEVICE
INPUT DEVICE
11~-~
3
5
3
01
5
7
9
16
7
9
16
18
8212
(DETAILED)
4
6
01 STB DO
8
10
8212
15
18
20
20
-
17
19
--
22 INT CLR 21
23 /
MD ' " 14
I~
DS 2
13
INPUT
STROBE
SYSTEM
INPUT
2
1
Vee
_ - - - . . . . - OUTPUT
FLAG
(SYMBOLIC)
8212
CLR
INT
INT
GND
DATA BUS
SYSTEM
OUTPUT
8212
CLR
DATA BUS
GATED BUFFER
II. Gated Buffer ( 3· STATE)
3-STATE
The simplest use of the 8212 is that of a gated
buffer. By tying the mode signal low and the strobe
input high, the data latch is acting as a straight
through gate. The output buffers are then enabled
from the device selection logic 051 and 052.
When the device selection logic is false, the outputs
Vee - - - - - - - . . - - - 8TB
INPUT
DATA
(250 ~A)
are 3-state.
When the device selection logic is true, the input
data from the system is directly transferred to the
output. The input data load is 250 micro amps. The
output data can sink 15 milli amps. The minimum
high output is 3.65 volts.
" " " '------C)I
8212
CLR
GATING {
CONTROL
(081-082)
5-103
---......--------'
OUTPUT
DATA
(15mA)
(3.65V MIN)
SCHOTTKY BIPOLAR 8212
III. Bi-Directional Bus Driver
BI-DIRECTIONAL BUS DRIVER
A pair of 8212's wired (back-to-back) can be used
as a symmetrical drive, bi-directional bus driver.
The devices are controlled by the data bus input
control which is connected to D81 on the first 8212
and to D82 on the second. One device is active, and
acting as a straight through buffer the other is in
3-state mode. This is a very useful circuit in small
system design.
STB
DATA---~
BUS
DATA BUS
CONTROL
(o= L - R)
(I = R -
1----'---......... OATA
8212
BUS
GND
L)
STB
8212
GND
INTERRUPTING INPUT PORT
IV. Interrupting Input Port
This use of an 8212 is that of a system input port
that accepts a strobe from the system input source,
which in turn clears the service request flip-flop
and interrupts the processor. The processor then
goes through a service routine, identifies the port,
and causes the device selection logic to go true enabling the system input data onto the data bus.
DATA
BUS
INPUT
STROBE
STB
SYSTEM
INPUT
SYSTEM
RESET
PORT
{
SELECTION
(DS1.DS2)
--------'
TO PRIORITY CKT
_ - . . . - (ACTIVE LOW)
OR .
TO CPU
INTERRUPT INPUT
INTERRUPT INSTRUCTION PORT
V. Interrupt Instruction Port
The 8212 can be used to gate the interrupt instruction, normally RESTART instructions, onto the data
bus. The device is enabled from the interrupt
acknowledge signal from the microprocessor and
from a port selection signal. This signal is normally
tied to ground. (081 could be used to multiplex a
variety of interrupt instruction ports onto a common bus).
DATA
BUS
STB
RESTART
INSTRUCTION
(RST 0 - RST 7)
(DSI) PORT SELECTION -
........~
INTERRUPT ACKNOWLEDGE - . . . - - _..........
5-104
SCHOTTKY BIPOLAR 8212
VI. Output Port (With Hand-Shaking)
OUTPUT PORT (WITH HAND-SHAKING)
The 8212 can be used to transmit data from the data
bus to a system output. The output strobe could be
a hand-shaking signal such as " reception of data "
from the device that the system is outputting to. It
in turn, can interrupt the system signifying the reception of data. The selection of the port comes
from the device selection logic. (OS1· OS2)
DATA
BUS
r----~-
OUTPUT STROBE
STB
8212
INT
SYSTEM
INTERRUPT
SYSTEM OUTPUT
CLR 11. & gt; ----...-- SYSTEM RESET
L..--
..._-
}
PORT SELECTION
(LATCH CONTROL)
(OS1.0S2)
VII. 8080 Status Latch
Note: The mode signal is tied high so that the output
on the latch is active and enabled all the time.
It is shown that the two areas of concern are the
bidirectional data bus of the microprocessor and the
control bus.
Here the 8212 is used as the status latch for an 8080
microcomputer system. The input to the 8212 latch
is directly from the 8080 data bus. Timing shows
that when the SYNC signal is true, which is connected to the OS2 input and the phase 1 signal is
true, which is a TTL level coming from the clock
generator; then, the status data will be latched into
the 8212.
8080 STATUS LATCH
DO
0,
SYNC
OBIN
19
-17
STATUS
LATCH
15
3
f\
ovJ
OATA BUS
& lt; / & gt; 2
22
12V
9
8
°2 7
°3 3
°4 4
Os
5
°6 6
°7
8080
& lt; / & gt; 1
10
" ' " '---
5
7
\.. -4 ~)
CLOCK GEN.
& DRIVER
9
--
( & lt; / & gt; 1TTL)
I " " --
16
18
20
22
0,
4
°0 I6 - - INTA
I - - - WO
STACK
~ HLTA
OUT
8212
17
~ M1
19
~ INP
21
I - - - MEMR
T1
L-
& lt; / & gt; 1
J..L
CLR
14 OS2 MO OS,
BASIC
& lt; / & gt; 2
CONTROL
BUS
SYNC
r & lt; :
·13 12
I
I
5-105
OATA
11
I
OBIN
STATUS
T2
SCHOTTKY BIPOLAR 8212
VIII. 8008 System
This shows the 8212 used in an 8008 microcomputer
system. They are used to multiplex the data from
three different sources onto the 8008 input data bus.
The three sources of data are: memory data, input
data, and the interrupt instruction. The 8212 is also
used as the uni-directional bus driver to provide a
proper drive to the address latches (both low order
and high order are also 8212's) and to provide adequate drive to the output data bus. The control of
these six 8212's in the 8008 system is provided by
the control logic and clock generator circuits. These
circuits consist of flip-flops, decoders, and gates to
generate the control functions necessary for 8008
microcomputer systems. Also note that the input
data port has a strobe input. This allows the proces-
sor to be interrupted from the input port directly.
The control of the input bus consists of the data bus
input signal, control logic, and the appropriate
status signal for bus discipline whether memory
read, input, or interrupt acknowledge. The combination of these four signals determines which one of
these three devices will have access to the input
data bus. The bus driver, which is implemented in
an 8212, is also controlled by the control logic and
clock generator so it can be 3-stated when necessary and also as a control transmission device to
the address latches. Note: The address latches can
be 3-stated for DMA purposes and they provide 15
miHi amps drive, sufficient for large bus systems.
8008 SYSTEM
INPUT
DATA
BUS
BUS
DRIVER
ADDRESS
LATCHES
LOW ORDER
(8 BITS)
MEMORY
DATA
------vee
INPUT
STROBE
00-07
INPUT
DATA
HIGH ORDER
(6 BITS)
SYNC
¢1
INT
READY ~
¢2
I
t
l
I • • • • • • DATA BUS
OUT
L-..----......----0111 MEM READ
" " " --'----------4----rJIII INPUT
- - - - - - - - - 4 - - - - - o I I I I N T ACK
INTERRUPT
INSTRUCTION
8212
- - - - - . . . . . . - - - - - t l D A T A BUS IN
' - f - - I - - - - - - - - - - - - . q , N T REO.
WAIT REQ.------l.MI
'-
(04,5,6,7)
I
b - - - - - - - - - . WR
..
I
.. OUT
I
J
CONTROL LOGIC
& CLOCK GEN.
5-106
SCHOTTKY BIPOLAR 8212 .
IX. 8080 System
This drawing shows the 8212 used in the I/O section
of an 8080 microcomputer system. The system consists of 8 input ports, 8 output ports, 8 level priority
systems, and a bidirectional bus driver. (The data
bus within the system is darkened for emphasis).
Basically, the operation would be as follows: The 8
ports, for example, could be connected to 8 keyboards, each keyboard having its own priority level.
The keyboard could provide a strobe input of its
own which would clear the service request flip-flop.
The INT signals are connected to an 8 level priority
encoding circuit. This circuit provides a positive
true level to the central processor (lNT) along with
a three-bit code to the interrupt instruction port for
the generation of RESTART instructions. Once the
processor has been interrupted and it acknowledges
the reception of the interrupt, the Interrupt Acknowledge signal is generated. This signal transfers data
in the form of a RESTART instruction onto the buffered data bus. When the DBIN signal is true this
RESTART instruction is gated into the microcomputer, in this case, the 8080 CPU. The 8080 then performs a software controlled interrupt service routine,
saving the status of its current operation in the
push-down stack and performing an INPUT instruction. The INPUT instruction thus sets the INP status
bit, which is common to all input ports.
Also present is the address of the device on the
8080 address bus which in this system is connected
to an 8205, one out of eight decoder with active low
outputs. These active low outputs will enable one of
the input ports, the one that interrupted the processor, to put its data onto the buffered data bus to be
transmitted to the CPU when the data bus input
signal is true. The processor can also output data
from the 8080 data bus to the buffered data bus
when the data bus input signal is false. Using the
same address selection technique from the 8205
decoder and the output status bit, we can select
with this system one of eight output ports to transmit the data to the system's output device structure.
Note: This basic I/O configuration for the 8080 can
be expanded to 256 input devices and 256 output
devices all using 8212 and, of course, the appropriate decoding.
5-107
Note that the 8080 is a 3.3-volt minimum high input
requirement and that the 8212 has a 3.65-volt minimum high output providing the designer with a 350
milli volt noise margin worst case for 8080 systems
when using the 8212.
SCHOTTKY BIPOLAR 8212
(See Note 1)
AO - '
A 1 --+8080
ADDRESS .:...
BUS
A 2 --+-
8205
ST;~;T:¢ ST:212 t :7: :~ l l ltn ~
::=:-
~ ~ E1
~ --0 E2
::Vee- .. 3_ _..
E_
~ ;:N~~-
I/O DEVICE
SELECTOR
:IIII[
INP - -......----t-t-t-t-t-+--+-t------------+-6
8212
_~L~ee?
= & gt; ~:~~T
STROBE 2 ---. STB
INPUT ~
PORT 2
L-Y
STATUS
BITS -
8212
8212
~ OUTPUT
PORT 2
W
~ CLR
_
INT
OUT ----t------r-t-t-t-t----ir+-t-----------+--+----1~:::::f_4
r-
D:J:~!I.
DalN-t?!NrJ
~
~
8212
I
8212
~
I
I
I
0 '1IO-++++----4~
1 IO-++++-.-.....~
2 1O-++++---oIt--.....
I
H
I
-
................
I
4
v~e
~
I:
I
L __ II_
8212
u
+--.s & gt;
GND
-----..----t:
INTERRUPT
INSTRUCTION
PORT (RST)
~
L-~
:111
8212
y
~ OUTPUT
W
PORT 4
_~L:ee y
ST;~;;~¢ ST:212 ~m:~~j!II!:w::7::~3 8212 t & gt; ~~~~~T
~ ~~~~_. I! ! -~~e I
I
I
..I
I
PRIORITY
ENCODER &
INTERRUPT
GENERATING
LOGIC CIRCUITS
(USER DESIGNED)
CLR
~f
:::::
i
I
GND
y
1G~D
I
ttm::zb ill\:,z:Zht~
8212
1O-++++---oIt--------- & lt; :::JIINT
5 1O-++++---oIt--_
=:
I
INPUT ~
PORT 4 L.-,I
3 IO-++++-.....-~
~
--I
-
Ill::
STROBE 4 --. STB
I
I
I
PORT 3
0- & lt; 1
-,
I
~
8080 --...J..
~ OUTPUT
I
I
I
Vee I
I
BUFFERED
DATA
BUS
INT
ACK
ST;;;;T::: ST:212 m::ili::~Jtmm:~ 8212 W
_----L.-,I- & lt; ~J11INT CLR -Y[[~\! . : CLR
. 1G~D L-_ :::[:[ ,_-.J Vee Y
--------004----------1
ST;;;;T:¢
ST:2~ : : : : : : : :~
.......------ & lt; =.11 INT CLR ~~
II::::::::::::::::::::?
:~:~:
8212
~ OUTPUT
hi " PORT 6
~ CLR
1G~D L-_ \l~\l -~ Vee I
BI-DI RECTIONAL
BUS DRIVER
STROBE 7 ---+- STB
8212
8212
~OUTPUT
PORT 7
W
SYSTEM--.....RESET
Note 1. This basic I/O configuration for the 8080 can be expanded to 256 input devices and 256 output devices all using 8212 and the appropriate decoding.
5-108
SCHOTTKY BIPOLAR 8212
Absolute Maximum Ratings·
Temperature Under Bias Plastic .. -65°C to + 75°C
Storage Temperature
-65°C to +160°C
All Output or Supply Voltages
- 0.5 to + 7 Volts
,All Input Voltages
*COMMENT: Stresses above those listed under " Absolute Maximum Ratings "
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or at any other condition above
those indicated in the operational sections of this specification is not implied.
-1.0 to 5.5 Volts
Output Currents
125 mA
D.C. Characteristics
= O°C to + 75°C 'Vee = +5V ±5°k
TA
Symbol
Parameter
Limits
Min.
Typ.
Unit
Test Conditions
Max.
IF
Input Load Current
ACK, 05 2 , CR, Oll-Ols Inputs
-.25
mA
VF = .45V
IF
Input Load Current
MO Input
-.75
mA
VF = .45V
IF
Input Load Current
OSI Input
-1.0
mA
VF = .45V
IR
Input Leakage Current
ACK, OS, CR, Oil-Dis Inputs
10
}lA
VR
= 5.25V
IR
Input Leakage Current
MO Input
30
JvtA
VR
= 5.25V
IR
Input Leakage Current
OSI Input
40
{tA
VR
= 5.25V
Vc
Input Forward Voltage Clamp
-1
V
Ie
= -5 mA
V1L
V1H
Input " Low " Voltage
.85
V
VOL
Output " Low " Voltage
VOH
Ise
Output " High " Voltage
3.65
Short Circuit Output Current
-15
Input " High " Voltage
11 01
Power Supply Current
V
.45
4.0
V
V
-75
20
Output Leakage Current
High Impedance State
lee
2.0
90
5-109
mA
130
mA
{tA
= 15 mA
10H = -1 mA
Va = OV
Va = .45V/ 5.25V
lal
SCHOTTKY BIPOLAR 8212
Typical Characteristics
INPUT CURRENT YS. INPUT YOLTAGE
o
r
Vee
Vee
(; "
....
z
TA =o°c " " ' "
'/
w
-150
«
E
= 25°C
V : / TA =75°C
V
/ TA
I-
z
w
I-
I:::J
~
60
a:
a:
:::J
u
u
a.
=+5.0V
801-----1----1----+--------4
I
« -100
..=:
~
100 ....----.,...----.,...----~--____.
~~~
=+5.0V
-50
:::J
OUTPUT CURRENT VS. OUTPUT " LOW " YOLTAGE
:;)
a.
....
:;)
-200
40
0
20
-250
-300
-3
-2
o
-1
+1
+2
O'---~~'-----'-----.L..------'
o
+3
.2
INPUT VOLTAGE (vt
DATA TO OUTPUT DELAY
YS. LOAD CAPACITANCE
O---.......---------------.--~-5
.8
.6
OUTPUT " LOW " VOLTAGE (V)
OUTPUT CURRENT YS.
OUTPUT " HIGH " YOLTAGE
Vee
.4
50
=+5.0V
I
Vee =- +5.0V
TA = 25°C
I-----+----+----+------#~----I
40
«
E.
-10
TA
!
=75 " C
& gt;
et
~
w
I-
z
w
a:
a:
TA = 25 " C
:::J
u
I-
::: & gt;
0
I:::J
CL
I:::J
-15
1----+------.,~~-4---= A =
T
-20
O " 'C
0
0
CL
......- ~
et
et
-'
I-
-25
.,.,- " " -
0
.,.,- " " -
~~
~.,.,-
.,.,---
-
\ ++ .,.,- " " .- .,.,20
I-
I:::J
0
30
~
.,.,-
.,.,-0iI'
~
10
-30
-35
O.
1.0
3.0
2.0
4.0
5.0
100
50
150
200
250
OUTPUT " HIGH " VOLTAGE (V)
22
LOAD CAPACITANCE (pF)
DATA TO OUTPUT DELAY
YS. TEMPERATURE
300
WRITE ENABLE TO OUTPUT DELAY
YS. TEMPERATURE
40
T
Vee = +5.0V
1
vee
=+5.0V
I
20
E.
et
«
18
CL
\.';,'c "
16
0
0
I-
et
et
w
c
,, " "
~ "
14
25
I:::J
CL
I:::J
"
-
30
o
o
I-
1..0'/
~
I:::J
~
//
~
w
0
I:::J
I
& gt;
III
.:
& gt;
35
t--
\.'c~
"
5TB & lt;
05 2
W
~
~
co
~
I-
20
w
w
0
--~
---- ... -------~----
" filii'
,,- " " - ____ f' " -\'
-\.'-,
.,.,-
~
--t +_
t-_
............
05, & lt; :: ~ ~
I-
~
~
12
10
-25
o
25
50
75
10
-25
100
TEMPERATURE (OC)
--
15
o
25
50
TEMPERATURE rc)
5-110
75
100
SCHOTTKY BIPOLAR 8212
Timing Diagram
1.5Vy----------y.5V
DATA
_____ -J.
I;==t
pw
1.5vl
STB or oSl • oS2
~twE=J
~I_
tH
:.j'----
' -1._5V
_
-/'10-:-------
OUTPUT
1.5Vj
oSl. OS2
________
l_tE_~ r
~E~~~W_)
_
X
OUTPUT
\1.5V
__
~-t-D-~----
~----,~t-
~tpw~
I
I
1.5V\.
eLR
.5fV
11.5V
~~~~~~~~~~~~1r-----
& gt; & lt; " -:._5V
DO
_____ J
r1.5V
.
_ _ _ _ _ _ _--+-_--_--_-_tS ET_-- '-_ "
__
__
STB or
_
1.SV X- - - ----------- -- 'i1
.5V
DATA
OS, •
DS2
~
'OUTPUT
-j
tPD-j
J{SV- - - - - - - - - --
_ _ _ _ _ _ _ .J
-----,I
STB
_
_'I~
tH
!--tpw
\~1.5V
_
1.5V
~tPw-~ts
I
NOTE: ALTERNATIVE TEST LOAD
Vcc
10K
OUT
0---....----.
CL
·lK
5-111
Y
VOH
VOL
SCHOTTKY BIPOLAR 8212
A.C. Characteristics
TA = O°C to + 75°C
Symbol
Vee
=
+5V ± 5%
Limits
Parameter
Typ.
Min.
Unit
Test Conditions
Max.
t pw
Pulse Width
t pd
Data To Output Delay
30
ns
t we
Write Enable To Output Delay
40
ns
t set
Data Setu·p Time
15
ns
th
Data Hold Time
20
ns
tr
Reset To Output Delay
40
ns
ts
Set To Output Delay
30
ns
te
Output Enable/Disable Time
45
ns
tc
Clear To Output Delay
55
ns
CAPACITANCE *
Symbol
F
30
= 1 MHz
VsrAs
= 2.5V
Vee
ns
=
Test
+5V
TA = 25°C
LIMITS
Typ.
Max.
CIN
DS I MD Input Capacitance
9 pF
12 pF
CIN
DS 2 , CK, ACK, Oil-Dis
Input Capacitance
5 pF
9 pF
COUT
DOl-DOs Output Capacitance
8 pF
12 pF
*This parameter is sampled and not 100% tested.
Switching Characteristics
TEST LOAD
CONDITIONS OF TEST
Input Pulse Amplitude = 2.5 V
Input Rise and Fall Times 5 ns
Between 1V and 2V Measurements made at 1.5V
with 15 rnA & 30 pF Test Load
15mA & 30pF
300
TO
D.U.T.
600
* INCLUDING JIG &
5-112
PROBE CAPACITANCE