2. Po sprawdzeniu napięć na wyjściu do MB jest 5.2V STB. Brak 13V/0.3A, +5V/4A oraz +12V/0.5A. Według manuala brak13V na wyjściu - problem zasilacza. Interesująca diagnoza. 3. W części ST BY na płycie głównej jest 5,2V STB oraz 3,3V. 3,3V spada przy przyciskaniu włączników na obudowie. Bardzo interesująca diagnoza. A tych włączników to ile jest? I co dalej?? Koniec pomiarów? Schemat mamy ci przeanalizować? (Już się zaczyna śmiecenie plikami). Ile tematów o tym TV, tym zasilaczu (i podobnych, opartych na takich układach) przeczytałeś na forum? To ja też sobie zaśmiecę.
MC34067, MC33067
High Performance
Resonant Mode Controllers
The MC34067/MC33067 are high performance zero voltage switch
resonant mode controllers designed for off–line and dc–to–dc
converter applications that utilize frequency modulated constant
off–time or constant deadtime control. These integrated circuits
feature a variable frequency oscillator, a precise retriggerable
one–shot timer, temperature compensated reference, high gain wide
bandwidth error amplifier, steering flip–flop, and dual high current
totem pole outputs ideally suited for driving power MOSFETs.
Also included are protective features consisting of a high speed fault
comparator and latch, programmable soft–start circuitry, input
undervoltage lockout with selectable thresholds, and reference
undervoltage lockout.
These devices are available in dual–in–line and surface mount
packages.
• Zero Voltage Switch Resonant Mode Operation
• Variable Frequency Oscillator with a Control Range Exceeding
1000:1
• Precision One–Shot Timer for Controlled Off–Time
• Internally Trimmed Bandgap Reference
• 4.0 MHz Error Amplifier
• Dual High Current Totem Pole Outputs
• Selectable Undervoltage Lockout Thresholds with Hysteresis
• Enable Input
• Programmable Soft–Start Circuitry
• Low Startup Current for Off–Line Operation
VCC
15
16
PDIP–16
P SUFFIX
CASE 648
16
MC3x067P
AWLYYWW
1
1
16
SO–16W
DW SUFFIX
CASE 751G
16
1
x
A
WL
YY
WW
MC3x067DW
AWLYYWW
1
= 3 or 4
= Assembly Location
= Wafer Lot
= Year
= Work Week
PIN CONNECTIONS
16 One-Shot RC
Osc Charge 1
15 VCC
Osc RC 2
14 Drive Output A
Gnd 4
VCC UVLO /
Enable
5
5.0 V
Reference
Vref
14
Steering
Flip-Flop
One-Shot
13 Power Gnd
Vref 5
12 Drive Output B
12
2.5 V
Clamp
13
Error Amp Out 6
11 CSoft-Start
Inverting Input 7
Vref UVLO
Variable
Frequency
Oscillator
16
Error Amp 6
Output
Noninverting 8
Input
Inverting Input 7
MARKING
DIAGRAMS
Osc Control Current 3
Enable / 9
UVLO Adjust
1
Osc Charge
2
Osc RC
Oscillator 3
Control Current
One-Shot
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10 Fault Input
Enable/UVLO
9
Adjust
Noninverting Input 8
Output A
(Top View)
Output B
Pwr Gnd
ORDERING INFORMATION
4
47 Units/Rail
SO–16W
1000 Tape & Reel
MC34067P
Ground
Fault Input
SO–16W
MC34067DWR2
10
Fault Detector/
Latch
MC34067DW
PDIP–16
25 Units/Rail
SO–16W
47 Units/Rail
SO–16W
1000 Tape & Reel
MC33067P
Soft-Start
Shipping
MC33067DWR2
11
Package
MC33067DW
Soft-Start
Device
Error
Amp
PDIP–16
25 Units/Rail
Figure 1. Simplified Block Diagram
© Semiconductor Components Industries, LLC, 2002
January, 2002– Rev. 4
1
Publication Order Number:
MC34067/D
MC34067, MC33067
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
VCC
Power Supply Voltage
20
V
Drive Output Current, Source or Sink (Note 1)
Continuous
Pulsed (0.5 µs, 25% Duty Cycle
IO
A
Error Amplifier, Fault, One–Shot, Oscillator and Soft–Start Inputs
Vin
– 1.0 to + 6.0
V
Vin(UVLO)
– 1.0 to VCC
V
PD
RθJA
862
145
mW
°C/W
PD
RθJA
1.25
100
W
°C/W
Operating Junction Temperature
TJ
+ 150
°C
Operating Ambient Temperature
MC34067
MC33067
TA
Storage Temperature
Tstg
0.3
1.5
UVLO Adjust Input
Power Dissipation and Thermal Characteristics
DW Suffix, Plastic Package, Case 751G
TA = 25°C
Thermal Resistance, Junction–to–Air
P Suffix, Plastic Package, Case 648
TA = 25°C
Thermal Resistance, Junction–to–Air
°C
0 to + 70
– 40 to + 85
– 55 to + 150
°C
ELECTRICAL CHARACTERISTICS
(VCC = 12 V [Note 2], ROSC= 18.2 k, RVFO = 2940 W, COSC = 300 pF, RT = 2370 W, CT = 300 pF, CL = 1.0 nF. For typical values
TA = 25°C, for min/max values TA is the operating ambient temperature range that applies [Note 3], unless otherwise noted.)
Symbol
Min
Typ
Max
Unit
Vref
5.0
5.1
5.2
V
Line Regulation (VCC = 10 V to 18 V)
Regline
–
1.0
20
mV
Load Regulation (IO = 0 mA to 10 mA)
Regload
–
1.0
20
mV
Vref
4.9
–
5.3
V
Output Short Circuit Current
IO
25
100
190
mA
Reference Undervoltage Lockout Threshold
Vth
3.8
4.3
4.8
V
Input Offset Voltage (VCM = 1.5 V)
VIO
–
1.0
10
mV
Input Bias Current (VCM = 1.5 V)
IIB
–
0.2
1.0
µA
Input Offset Current (VCM = 1.5 V)
IIO
–
0
0.5
µA
Open Loop Voltage Gain (VCM = 1.5 V, VO = 2.0 V)
AVOL
70
100
–
dB
Gain Bandwidth Product (f = 100 kHz)
GBW
3.0
5.0
–
MHz
Input Common Mode Rejection Ratio (VCM = 1.5 V to 5.0 V)
CMR
70
95
–
dB
Power Supply Rejection Ratio (VCC = 10 V to 18 V, f = 120 Hz)
PSR
80
100
–
dB
Output Voltage Swing
High State (Isource = 2.0 mA)
Low State (Isink = 4.0 mA)
VOH
VOL
2.8
–
3.2
0.6
–
0.8
Characteristic
REFERENCE SECTION
Reference Output Voltage (IO = 0 mA, TJ = 25°C)
Total Output Variation Over Line, Load, and Temperature
ERROR AMPLIFIER
1.
2.
3.
4.
V
Maximum package power dissipation limits must be observed.
Adjust VCC above the Startup Threshold voltage before setting to 12 V.
Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.
Thigh = + 70°C for MC34067
Tlow = 0°C for MC34067
= – 40°C for MC33067
= + 85°C for MC33067
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2
MC34067, MC33067
ELECTRICAL CHARACTERISTICS (continued) (VCC = 12 V [Note 6], ROSC= 18.2 k, RVFO = 2940 W, COSC = 300 pF,
RT = 2370 W, CT = 300 pF, CL = 1.0 nF. For typical values TA = 25°C, for min/max values TA is the operating ambient temperature range
that applies [Note 7], unless otherwise noted.)
Symbol
Min
Typ
Max
Frequency (Error Amp Output Low)
Total Variation (VCC = 10 V to 18 V, TA = TLow to THigh)
fOSC(low)
490
525
550
Frequency (Error Amp Output High)
Total Variation (VCC = 10 V to 18 V, TA = TLow to THigh)
fOSC(high)
1850
2050
2200
Vin
–
2.5
–
235
225
250
–
270
280
–
–
9.5
9.0
0.8
1.5
10.3
9.7
1.2
2.0
–
–
VOL(UVLO)
–
0.8
1.2
V
Output Voltage Rise Time (CL = 1.0 nF)
tr
–
20
50
ns
Output Voltage Fall Time (CL = 1.0 nF)
tf
–
15
50
ns
Input Threshold
Vth
0.93
1.0
1.07
V
Input Bias Current (VPin 10 = 0 V)
IIB
–
– 2.0
– 10
µA
tPLH(In/Out)
–
60
100
ns
Ichg
4.5
9.0
14
µA
Idischg
3.0
8.0
–
mA
14.8
8.0
16
9.0
17.2
10
8.0
7.6
9.0
8.6
10
9.6
7.0
–
Characteristic
Unit
OSCILLATOR
kHz
kHz
Oscillator Control Input Voltage, Pin 3
V
ONE–SHOT
tBlank
Drive Output Off–Time
TA = 25°C
Total Variation (VCC = 10 V to 18 V, TA = TLow to THigh)
ns
DRIVE OUTPUTS
V
Output Voltage
Low State (ISink = 20 mA)
Low State (ISink = 200 mA)
High State (ISource = 20 mA)
High State (ISource = 200 mA)
VOL
VOH
Output Voltage with UVLO Activated (VCC = 6.0 V, ISink = 1.0 mA)
FAULT COMPARATOR
Propagation Delay to Drive Outputs (100 mV Overdrive)
SOFT–START
Capacitor Charge Current (VPin 11 = 2.5 V)
Capacitor Discharge Current (VPin 11 = 2.5 V)
UNDERVOLTAGE LOCKOUT
Startup Threshold, VCC Increasing
Enable/UVLO Adjust Pin Open
Enable/UVLO Adjust Pin Connected to VCC
Vth(UVLO)
Minimum Operating Voltage After Turn–On, VCC Decreasing
Enable/UVLO Adjust Pin Open
Enable/UVLO Adjust Pin Connected to VCC
V
VCC(min)
V
Enable/UVLO Adjust Shutdown Threshold Voltage
Vth(Enable)
6.0
Enable/UVLO Adjust Input Current (Pin 9 = 0 V)
Iin(Enable)
–
– 0.2
– 1.0
–
–
0.5
27
0.8
35
V
mA
TOTAL DEVICE
ICC
Power Supply Current (Enable/UVLO Adjust Pin Open)
Startup (VCC = 13.5 V)
Operating (fOSC = 500 kHz) (Note 6)
5.
6.
7.
8.
mA
Maximum package power dissipation limits must be observed.
Adjust VCC above the Startup Threshold voltage before setting to 12 V.
Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.
Tlow = 0°C for MC34067
Thigh = + 70°C for MC34067
= – 40°C for MC33067
= + 85°C for MC33067
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3
MC34067, MC33067
COSC = 200 pF
400
COSC = 500 pF
300
VCC = 12 V
RVFO = ∞
RT = ∞
CT = 500 pF
TA = 25°C
200
100
0
3500
COSC = 300 pF
f OSC , OSCILLATOR FREQUENCY (kHz)
ROSC, OSCILLATOR TIMING RESISTOR (kΩ )
500
Oscillator Discharge Time is Measured at the Drive Outputs.
0
20
40
60
80
tdischg, OSCILLATOR DISCHARGE TIME (µs)
VCC = 12 V
TA = 25°C
ROSC = 18.2 k
3000
2500
2000
COSC = 300 pF
1500
1000
500
0
100
0
Figure 2. Oscillator Timing Resistor
versus Discharge Time
60
VOL, OUTPUT LOW STATE VOLTAGE (V)
RT, TIMING RESISTOR (k Ω )
0.30
0.25
0.20
0.15
0.10
0
0.5
1.0
1.5
2.0
2.5
IOSC, OSCILLATOR CONTROL CURRENT (mA)
30
20
60
70
20
80
10
90
Phase
0
100
Phase
Margin
= 64°
-10
10 k
10M
0
0.3
0.6
1.0
3.0
tOS, ONE-SHOT PERIOD (µs)
6.0
10
-Ă20
*Vref = 5.1 V
VCC = 12 V
RL = ∞
*Vref at TA = 25°C
-Ă30
-Ă40
-Ă50
120
*Vref = 5.0 V
-Ă10
-Ă55
∇
100 k
1.0M
f, FREQUENCY (Hz)
110
V ref , REFERENCE OUTPUT VOLTAGE CHANGE (mV)
Gain
30
One-Shot Period is Measured
at the Drive Outputs.
Figure 5. One–Shot Timing Resistor
versus Period
0, EXCESS PHASE (DEGREES)
A VOL, OPEN LOOP VOLTAGE GAIN (dB)
40
CT = 500 pF
6.0
3.0
0.1
50
VCC = 12 V
VO = 2.0 V
RL = 100 k
TA = 25°C
CT = 200 pF
CT = 300 pF
3.0
50
VCC = 12 V
COSC = 500 pF
ROSC = 100 k
TA = 25°C
10
Figure 4. Error Amp Output Low State Voltage
versus Oscillator Control Current
-Ă20
2000
Figure 3. Oscillator Frequency versus
Oscillator Control Current
0.35
0.05
400
800
1200
1600
IOSC, OSCILLATOR CONTROL CURRENT (mA)
Figure 6. Open Loop Voltage Gain and Phase
versus Frequency
*Vref = 5.2 V
-Ă25
0
25
50
75
TA, AMBIENT TEMPERATURE (°C)
100
Figure 7. Reference Output Voltage Change
versus Temperature
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4
125
0
V sat , OUTPUT SATURATION VOLTAGE (V)
V ref , REFERENCE OUTPUT VOLTAGE CHANGE (mV)
MC34067, MC33067
TA = -Ă40°C
-10
TA = -Ă20°C
-Ă20
-Ă50
VCC = 12 V
0
TA = 25°C
∇
20
40
60
80
Iref, REFERENCE SOURCE CURRENT (mA)
100
3.0
TA = -Ă40°C
2.0
TA = 25°C
1.0
0
Source Saturation
(Load to VCC)
0
CL = 1.0 nF
TA = 25 °C
10%
20 ns/DIV
2.4
1.6
0.8
0
VCC = 12 V
Pin 10 = Vref
TA = 25 °C
0
24
I CC, SUPPLY CURRENT (mA)
f, OPERATING FREQUENCY (kHz)
1200
800
400
0
30
40
50
60
70
ICC, SUPPLY CURRENT (mA)
80
1.0
2.0
4.0
6.0
8.0
Idchg, CAPACITOR DISCHARGE CURRENT (mA)
10
Figure 11. Soft–Start Saturation Voltage
versus Capacitor Discharge Current
VCC = 12 V
CL = 1.0 nF
TA = 25 °C
1600
0.4
0.6
0.8
IO, OUTPUT LOAD CURRENT (A)
3.2
Figure 10. Drive Output Waveform
2000
0.2
Gnd
Figure 9. Drive Output Saturation Voltage
versus Load Current
V OL , SOFT-START SATURATION VOLTAGE (V)
Figure 8. Reference Output Voltage Change
versus Source Current
90%
VCC = 12 V
80 µs Pulsed Load
120 Hz Rate
TA = -Ă40°C
-Ă3.0
-Ă30
Source Saturation
(Load to Ground)
VCC
-1.0
-Ă2.0
TA = -125°C
-Ă40
0
20
Figure 12. Operating Frequency
versus Supply Current
Enable/UVLO
Adjust Pin
Open
(Solid Line)
16
12
8.0
Enable/UVLO
Adjust Pin
to VCC
(Dashed Line)
4.0
0
90
TA = 25 °C
0
4.0
8.0
12
VCC, SUPPLY VOLTAGE (V)
16
20
Figure 13. Supply Current versus Supply Voltage
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5
MC34067, MC33067
VCC
15
50k
Enable /
UVLO Adjust
7.0k
7.0k
9
50k
5.1V
Reference
VCC UVLO
8.0V
Vref
5
Vref UVLO
Vref
OSC Charge
4.2/4.0V
D1
Q1
2
IOSC
One-Shot RC
CT
Oscillator 16
Control Current
RT
IOSC
Steering
Flip-Flop
Q
T
RQ
Oscillator
OSC RC
COSC
14
Q2
1
ROSC
Error Amp Output 6
8
Noninverting Input
Inverting Input
7
Soft-Start
4.9V/3.6V
3.1V
12
4.9V/3.6V
Q
Error Amp
Clamp
Error Amp
R
Fault Comparator
S
1.0V
Fault
Latch
9.0µA
Output A
Power
13 Ground
One-Shot
3
RVFO
Vref
10
Output B
Fault Input
11
4
Ground
Figure 14. MC34067 Representative Block Diagram
5.1 V
COSC
3. 6 V
One-Shot
5.1 V
3.6 V
Output A
Output B
tOS
tOS
tOS
tOS
High State Error Amp output, minimum IOSC current
occurring at minimum input voltage, maximum load.
tOS
tOS
Low State Error Amp output, maximum IOSC current
occurring at maximum input voltage, minimum load.
Figure 15. Timing Diagram
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6
MC34067, MC33067
OPERATING DESCRIPTION
Introduction
frequencies exceeding 1.0 MHz. The Error Amplifier can
control the oscillator frequency over a 1000:1 frequency
range, and both the minimum and maximum frequencies are
easily and accurately programmed by the proper selection of
external components.
The functional diagram of the Oscillator and One–Shot
timer is shown in Figure 16. The oscillator capacitor (COSC)
is initially charged by transistor Q1. When COSC exceeds the
4.9 V upper threshold of the oscillator comparator, the base
of Q1 is pulled low allowing COSC to discharge through the
external resistor, (ROSC), and the oscillator control current,
(IOSC). When the voltage on COSC falls below the
comparator’s 3.6 V lower threshold, Q1 turns on and again
charges COSC.
COSC charges from 3.6 V to 5.1 V in less than 50 ns. The
high slew rate of COSC and the propagation delay of the
comparator make it difficult to control the peak voltage. This
accuracy issue is overcome by clamping the base of Q1
through a diode to a voltage reference. The peak voltage of
the oscillator waveform is thereby precisely set at 5.1 V.
As power supply designers have strived to increase power
conversion efficiency and reduce passive component size,
high frequency resonant mode power converters have
emerged as attractive alternatives to conventional
pulse–width modulated control. When compared to
pulse–width modulated converters, resonant mode control
offers several benefits including lower switching losses,
higher efficiency, lower EMI emission, and smaller size. A
new integrated circuit has been developed to support this
trend in power supply design. The MC34067 Resonant
Mode Controller is a high performance bipolar IC dedicated
to variable frequency power control at frequencies
exceeding 1.0 MHz. This integrated circuit provides the
features and performance specifically for zero voltage
switching resonant mode power supply applications.
The primary purpose of the control chip is to provide a
fixed off–time to the gates of external power MOSFETs at
a repetition rate regulated by a feedback control loop.
Additional features of the IC ensure that system startup and
fault conditions are administered in a safe, controlled manner.
A simplified block diagram of the IC is shown on the front
page, which identifies the main functional blocks and the
block–to–block interconnects. Figure 14 is a detailed
functional diagram which accurately represents the internal
circuitry. The various functions can be divided into two
sections. The first section includes the primary control path
which produces precise output pulses at the desired
frequency. Included in this section are a variable frequency
Oscillator, a One–Shot, a pulse Steering Flip–Flop, a pair of
power MOSFET Drivers, and a wide bandwidth Error
Amplifier. The second section provides several peripheral
support functions including a voltage reference,
undervoltage lockout, Soft–Start circuit, and a fault detector.
VCC
OSC Charge
Q1
1
OSC RC
ROSC
COSC
2
RT
Oscillator 10
Control Current
IOSC
3
RVFO
6
Error Amp Output
VCC
D1
Oscillator
IOSC
4.9V/3.6V
One-Shot RC
CT
Vref
One-Shot
4.9V/3.6V
3.1V
Error Amp
Clamp
Figure 16. Oscillator and One–Shot Timer
Primary Control Path
The output pulse width and repetition rate are regulated
through the interaction of the variable frequency Oscillator,
One–Shot timer and Error Amplifier. The Oscillator triggers
the One–Shot which generates a pulse that is alternately
steered to a pair of totem pole output drivers by a toggle
Flip–Flop. The Error Amplifier monitors the output of the
regulator and modulates the frequency of the Oscillator.
High speed Schottky logic is used throughout the primary
control channel to minimize delays and enhance high
frequency characteristics.
The frequency of the Oscillator is modulated by varying
the current flowing out of the Oscillator Control Current
(IOSC) pin. The IOSC pin is the output of a voltage regulator.
The input of the voltage regulator is tied to the variable
frequency oscillator. The discharge current of the Oscillator
increases by increasing the current out of the IOSC pin.
Resistor RVFO is used in conjunction with the Error Amp
output to change the IOSC current. Maximum frequency
occurs when the Error Amplifier output is at its low state
with a saturation voltage of 0.1 V at 1.0 mA.
The minimum oscillator frequency will result when the
IOSC current is zero, and COSC is discharged through the
external resistor (ROSC). This occurs when the Error
Amplifier output is at its high state of 2.5 V. The minimum
and maximum oscillator frequencies are programmed by the
proper selection of resistor ROSC and RVFO. The minimum
frequency is programmed by ROSC using Equation 1:
Oscillator
The characteristics of the variable frequency Oscillator
are crucial for precise controller performance at high
operating frequencies. In addition to triggering the
One–Shot timer and initiating the output deadtime, the
oscillator also determines the initial voltage for the one–shot
capacitor. The Oscillator is designed to operate at
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7
MC34067, MC33067
1
– t PD
t (max) – 70 ns
ƒ(min)
=
R OSC =
0.348 C OSC
C OSC ȏ n 5.1
3.6
where tPD is the internal propagation delay.
Error Amplifier
A fully accessible high performance Error Amplifier is
provided for feedback control of the power supply system.
The Error Amplifier is internally compensated and features
dc open loop gain greater than 70 dB, input offset voltage of
less than 10 mV and a guaranteed minimum gain–bandwidth
product of 2.5 MHz. The input common mode range extends
from 1.5 V to 5.1 V, which includes the reference voltage.
(1)
ǒ Ǔ
The maximum oscillator frequency is set by the current
through resistor RVFO. The current required to discharge
COSC at the maximum oscillator frequency can be calculated
by Equation 2:
I (max) = C OSC
5.1 – 3.6
1
ƒ(max)
= 1.5COSC ƒ(max)
Oscillator
Control Current
(2)
IOSC
The discharge current through ROSC must also be known
and can be calculated by Equation 3:
ǒ
–
5.1 – 3.6
=
IR
ε
OSC
ROSC
ǒ
–
=
1.5
R OSC
ε
1
ƒ (min)
R OSC COSC
Error Amp
Clamp
Error Amp Output
Ǔ
Inverting Input
(3)
1
ƒ(min) R OSC COSC
8
7
Error
Amp
Figure 17. Error Amplifier and Clamp
When the Error Amplifier output is coupled to the IOSC
pin by RVFO, as illustrated in Figure 17, it provides the
Oscillator Control Current, IOSC. The output swing of the
Error Amplifier is restricted by a clamp circuit to improve
its transient recovery time.
Resistor RVFO can now be calculated by Equation 4:
2.5 – V EAsat
RVFO =
I(max) – I R
OSC
RVFO
6
Noninverting Input
Ǔ
3.1V
3
(4)
One–Shot Timer
Output Section
The One–Shot is designed to disable both outputs
simultaneously providing a deadtime before either output is
enabled. The One–Shot capacitor (CT) is charged
concurrently with the oscillator capacitor by transistor Q1,
as shown in Figure 16. The one–shot period begins when the
oscillator comparator turns off Q1, allowing CT to
discharge. The period ends when resistor RT discharges CT
to the threshold of the One–Shot comparator. The lower
threshold of the One–Shot is 3.6 V. By choosing CT, RT can
by solved by Equation 5:
The pulse(tOS), generated by the Oscillator and One–Shot
timer is gated to dual totem–pole output drives by the
Steering Flip–Flop shown in Figure 18. Positive transitions
of tOS toggle the Flip–Flop, which causes the pulses to
alternate between Output A and Output B. The flip–flop is
reset by the undervoltage lockout circuit during startup to
guarantee that the first pulse appears at Output A.
RT =
t OS
C T ȏn
ǒ 5.1 Ǔ
3.6
=
VCC
t OS
0.348 C T
(5)
Steering
Flip-Flop
Errors in the threshold voltage and propagation delays
through the output drivers will affect the One–Shot period.
To guarantee accuracy, the output pulse of the control chip
is trimmed to within 5% of 250 ns with nominal values of RT
and CT.
The outputs of the Oscillator and One–Shot comparators
are OR’d together to produce the pulse tOS, which drives the
Flip–Flop and output drivers. The output pulse (tOS) is
initiated by the Oscillator and terminated by the One–Shot
comparator. With zero–voltage resonant mode converters,
the oscillator discharge time should never be set less than the
one–shot period.
T
Q
14
Pwr
Gnd
13
Output A
Power Ground
VCC
RQ
12
Output B
Pwr
Gnd
Figure 18. Steering Flip–Flop and Output Drivers
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8
MC34067, MC33067
The MC34067 utilizes a unique design that virtually
eliminates cross conduction, thus controlling the chip power
dissipation at high frequencies. A separate power ground pin
is provided to isolate the sensitive analog circuitry from large
transient currents.
The totem–pole output drivers are ideally suited for driving
power MOSFETs and are capable of sourcing and sinking
1.5 A. Rise and fall times are typically 20 ns and 15 ns
respectfully when driving a 1.0 nF load. High source/sink
capability in a totem–pole driver normally increases the risk
of high cross conduction current during output transitions.
VCC
15
50k
Enable /
UVLO Adjust
7.0k
Vref
7.0k
9
50k
5.1V
Reference
8.0V
5
Vref UVLO
VCC UVLO
UVLO
Vref
4.2/4.0V
Figure 19. Undervoltage Lockout and Reference
PERIPHERAL SUPPORT FUNCTIONS
The MC34067 Resonant Controller provides a number of
support and protection functions including a precision
voltage reference, undervoltage lockout comparators,
soft–start circuitry, and a fault detector. These peripheral
circuits ensure that the power supply can be turned on and
off in a controlled manner and that the system will be quickly
disabled when a fault condition occurs.
The Reference Regulator provides a precise 5.1 V
reference to internal circuitry and can deliver up to 10 mA
to external loads. The reference is trimmed to better than 2%
initial accuracy and includes active short circuit protection.
Fault Detection
Converter protection from adverse operating conditions
can be implemented with proper use of the Fault Comparator
and Latch blocks that are illustrated in Figure 20. The Fault
Comparator has an input threshold of 1.0 V and when
exceeded, sets the Fault Latch and generates two logic
signals that simultaneously disable the primary control path.
The signal line labeled “Fault” connects directly to two gates
that control the output drivers. This direct path reduces the
driver turn–off propagation delay to approximately 70 ns.
The Fault Latch output is OR’ed with the UVLO output that
is derived from the Vref UVLO comparator, to produce the
logic output labeled “UVLO+Fault”. This signal disables
the Oscillator and the One–Shot by forcing both the COSC
and CT capacitors to be continually charged.
The Fault Latch is automatically reset during startup by a
logic “1” that appears at the Vref UVLO comparator output.
The latch can also be reset after startup by momentarily
pulling the Enable/UVLO Adjust pin low to disable the
Reference. Note that after activation, the Fault Latch will
remain in a set state only as long as VCC is provided to the
MC34067. Also, Drive Output B will assume a high state if
the Fault input signal drops below the 1.0 V threshold level
Undervoltage Lockout and Voltage Reference
Separate undervoltage lockout comparators sense the
input VCC voltage and the regulated reference voltage as
illustrated in Figure 19. When VCC increases to the upper
threshold voltage, the VCC UVLO comparator enables the
Reference Regulator. After the Vref output of the Reference
Regulator rises to 4.2 V, the Vref UVLO comparator switches
the UVLO signal to a logic zero state enabling the primary
control path. Reducing VCC to the lower threshold voltage
causes the VCC UVLO comparator to disable the Reference
Regulator. The Vref UVLO comparator then switches the
UVLO output to a logic one state disabling the controller.
The Enable/UVLO Adjust pin allows the power supply
designer to select the VCC UVLO threshold voltages. When
this pin is open, the comparator switches the controller on at
16 V and off at 9.0 V. If this pin is connected to the VCC
terminal, the upper and lower thresholds are reduced to
9.0 V and 8.6 V, respectively. Forcing the Enable/UVLO
Adjust pin low will pull the VCC UVLO comparator input
low (through an internal diode) turning off the controller.
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9
MC34067, MC33067
Soft–Start Circuit
even after the Fault Latch has been set. In some applications
this characteristic could be problematic but it can be easily
remedied by AC coupling Drive Output B.
The Soft–Start circuit shown in Figure 20 forces the
variable frequency Oscillator to start at the maximum
frequency and ramp downward until regulated by the
feedback control loop. The external capacitor at the
CSoft–Start terminal is initially discharged by the
UVLO+Fault signal. The low voltage on the capacitor
passes through the Soft–Start Buffer to hold the Error
Amplifier output low. After UVLO+Fault switches to a
logic zero, the soft–start capacitor is charged by a 9.0 µA
current source. The buffer allows the Error Amplifier output
to follow the soft–start capacitor until it is regulated by the
Error Amplifier inputs. The soft–start function is generally
applicable to controllers operating below resonance and can
be disabled by simply opening the CSoft–Start terminal.
Fault
UVLO
UVLO + Fault
Q
9.0µA
Fault
Fault
Comparator Input
S
Fault
Latch
Error Amp
Clamp
CSoft-Start
R
10
1.0V
Soft-Start
Buffer
11
6
Ground
Figure 20. Fault Detector and Soft–Start
APPLICATIONS INFORMATION
The MC34067 is specifically designed for zero voltage
switching (ZVS) quasi–resonant converter (QRC)
applications. The IC is optimized for double–ended
push–pull or bridge type converters operating in continuous
conduction mode. Operation of this type of ZVS with
resonant properties is similar to standard push–pull or bridge
circuits in that the energy is transferred during the transistor
on–time. The difference is that a series resonant tank is
usually introduced to shape the voltage across the power
transistor prior to turn–on. The resonant tank in this
topology is not used to deliver energy to the output as is the
case with zero current switch topologies. When the power
transistor is enabled the voltage across it should already be
zero, yielding minimal switching loss. Figure 21 shows a
timing diagram for a half–bridge ZVS QRC. An application
circuit is shown in Figure 22. The circuit built is a dc to dc
half–bridge converter delivering 75 W to the output from a
48 V source.
When building a zero voltage switch (ZVS) circuit, the
objective is to waveshape the power transistor’s voltage
waveform so that the voltage across the transistor is zero
when the device is turned on. The purpose of the control IC
is to allow a resonant tank to waveshape the voltage across
the power transistor while still maintaining regulation. This
is accomplished by maintaining a fixed deadtime and by
varying the frequency; thus the effective duty cycle is
changed.
Primary side resonance can be used with ZVS circuits. In
the application circuit, the elements that make the resonant
tank are the primary leakage inductance of the transformer
(LL) and the average output capacitance (COSS) of a power
MOSFET (CR). The desired resonant frequency for the
application circuit is calculated by Equation 6:
ƒr =
1
2π
(6)
L L 2C R
In the application circuit, the operating voltage is low and
the value of COSS versus Drain Voltage is known. Because
the COSS of a MOSFET changes with drain voltage, the
value of the CR is approximated as the average COSS of the
MOSFET. For the application circuit the average COSS can
be calculated by Equation 7:
CR =
2 * C OSS measured at
1
V
2 in
(7)
The MOSFET chosen fixes CR and that LL is adjusted to
achieve the desired resonant frequency.
However, the desired resonant frequency is less critical
than the leakage inductance. Figure 21 shows the primary
current ramping toward its peak value during the resonant
transition. During this time, there is circulating current
flowing through the secondary inductance, which
effectively makes the primary inductance appear shorted.
Therefore, the current through the primary will ramp to its
peak value at a rate controlled by the leakage inductance and
the applied voltage. Energy is not transferred to the
secondary during this stage, because the primary current has
not overcome the circulating current in the secondary. The
larger the leakage inductance, the longer it takes for the
primary current to slew. The practical effect of this is to
lower the duty cycle, thus reducing the operating range.
The maximum duty cycle is controlled by the leakage
inductance, not by the MC34067. The One–Shot in the
MC34067 only assures that the power switch is turned on
under a zero voltage condition. Adjust the one–shot period
so that the output switch is activated while the primary
current is slewing but before the current changes polarity.
The resonant stage should then be designed to be as long as
the time for the primary current to go to zero amps.
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10
MC34067, MC33067
5.1 V
COSC
3.6 V
5.1 V
3.6 V
One-Shot
Drive Output A
Drive Output B
Vin
1/2 Vin
Input Voltage
0V
+ Iprimary
Primary Current
0A
- Iprimary
Vin/Turns Ratio
Output Rectifier Voltage
Figure 21. Application Timing Diagram
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11
V
CC
15
10
Vin
36 V to 56 V
Reference
9
5
500pF 51/0.5W
1.0
100
T1
MTP33N10E
1
330pF
1N5819
18k
T2
T3
12
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1500pF
12
6
2
100
500pF 51/0.5W
1N5819 x 4
470pF
3.9k
470
8
16k
7
0.01
11
4
T1 = Primary: 12 turns #48 AWG (1300 strands litz wire)
Secondary: 6 turns center tapped #48 AWG (1300 strands litz wire)
Core: Philips 3F3 4312 020 4124
Bobbin: Philips 4322 021 3525
Primary Leakage Inductance = 1.0 µH
Test
Conditions
T2 = All windings: 8 turns #36 AWG
Core: Philips 3F3 EP7–3F3
Bobbin: Philips EP7PCB1–6
Results
Line Regulation
V in = 40 V to 56 V, IO =15 A
20 mV = ±0.198%
Load Regulation
V in = 48 V, IO = 10 A to 15 A
4.0 mV = ±0.039%
Output Ripple
V in = 48 V, I O = 15 A, fswitch = 1.0 MHz
25 mVp–p
Efficiency
V in = 48 V, I O = 10 A, fswitch = 1.7 MHz
V in = 48 V, I O = 15 A, fswitch = 1.0 MHz
83.5%
84.2%
T3 = Coilcraft D1870 (100 turns)
L1 = 2 turns #48 AWG (1300 strands litz wire)
Core: Philips 3F3 EP10–3F3
Bobbin: Philips EP10PCB1–8
Inductance = 1.8 µH
L2 = 5 turns #48 AWG (1300 strands litz wire)
Core: 0.5″ diameter air code
Inductance = 100 nH
Heatsinks = AAVID Engineering Inc. 533402B02552 with clip
MC34067–5803
Insulators = Berquist Sil–Pad 1500
Figure 22. Application Circuit
Vout
5.0 V
1N5819
10
220pF
L2
MC34067, MC33067
1.1k
10k
1.6k 330pF
1.0k
3
2.7k
30
13
16
100pF
L1
1.0k
14
2
MBR2535
CTL
1.0
MC34067, MC33067
(Top View)
(Bottom View)
5.0″
3.875″
Figure 23. Printed Circuit Board and Component Layout
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MC34067, MC33067
PACKAGE DIMENSIONS
PDIP–16
P SUFFIX
CASE 648–08
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
–A–
16
9
1
8
B
F
C
L
S
–T–
SEATING
PLANE
K
H
G
D
M
J
16 PL
0.25 (0.010)
M
T A
M
DIM
A
B
C
D
F
G
H
J
K
L
M
S
INCHES
MIN
MAX
0.740
0.770
0.250
0.270
0.145
0.175
0.015
0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008
0.015
0.110
0.130
0.295
0.305
0_
10 _
0.020
0.040
MILLIMETERS
MIN
MAX
18.80
19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0_
10 _
0.51
1.01
SO–16W
DW SUFFIX
CASE 751G–03
ISSUE B
A
D
9
1
8
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INLCUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS
OF THE B DIMENSION AT MAXIMUM MATERIAL
CONDITION.
16X
M
T A
S
B
h X 45 _
S
14X
e
L
A
0.25
B
B
A1
H
E
0.25
8X
M
B
M
16
q
SEATING
PLANE
T
C
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DIM
A
A1
B
C
D
E
e
H
h
L
q
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
10.15
10.45
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0_
7_
MC34067, MC33067
Notes
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15
MC34067, MC33067
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MC34067/D
This datasheet has been download from:
www.datasheetcatalog.com
Datasheets for electronics components.