TOSHIBA_Satellite_A200_A205_Compal_LA-3481P_-_Rev_2_0A.pdf

Toshiba Satellite Pro A200 - P造ta ISKAA LA-3481P - Brak procedury POST

P造ta: ISKAA LA-3481P Rev. 2.0A Obsada uk豉dowa: p馧noc - GM945 po逝dnie - ICH8-M KBC- KB926 P造ta ze zintegrowan grafik Intel'a. Witam. Siedz drugi dzie nad t p造t i brakuje mi ju pomys堯w. Problemem jest brak procedury POST. P造ta startuje, pob鏎 pr康u stopniowo wzrasta, osi庵a 766mA, po chwili spada do warto軼i 715mA i tak ju zostaje. Wszystkie napi璚ia zasilaj帷e prawid這we, jedynie nie podoba mi si +VCC_CORE - 960mV. Mimo to PU11 wystawia sygna PGOOD. Z tego co czyta貫m +VCC_CORE przy starcie p造ty powinno wynosi 1,2V. KBC otrzymuje sygna PWROK. Reset CMOS wykonany, BIOS przeprogramowany - bez zmian. Oscylacje obecne na wszystkich kwarcach poza X2 - tutaj oscylacje pojawiaj si na u豉mek sekundy po w陰czeniu, ale czyta貫m, 瞠 na tej p造cie to normalne przy braku POST. P造ta prawid這wo sygnalizuje brak pami璚i RAM. RAM i procesor oczywi軼ie podmienione, jedynie nie jestem pewien procesora - na podmian mam tylko T2370 i nie wiem czy ta p造ta obs逝篡 ten procesor. Bateria jest prawid這wo 豉dowana i p造ta startuje na samej baterii z tym samym skutkiem. Do嗆 mocno nagrzewa si ICH8-M - nie utrzymam na nim palca d逝瞠j ni przez kilka sekund. Na schemacie brak rozpiski poszczeg鏊nych sygna堯w zegarowych, co dodatkowo utrudnia spraw. Podejrzewam uszkodzone po逝dnie, ale mo瞠 kto przerabia ju ten temat i podpowie co nieco. Z g鏎y dzi瘯uj za wszelkie sugestie.


A

B

C

D

E

1

1

Compal confidential

2

2

ISKAA LA-3481P Schematics Document

Mobile Merom uFCPGA with Intel
Crestline_PM+ICH8-M core logic
3

3

2007-06-23
REV:2.0A

4

4

Compal Secret Data

Security Classification
2006/08/05

Issued Date

2007/08/05

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Compal Electronics, Inc.
Cover Sheet
Document Number

Rev
2.0

LA-3481P
Saturday, June 23, 2007

Sheet
E

1

of

47

A

B

C

D

E

ISKAA Sub-board

Compal confidential

ATI VGA/B LS-3481P Rev 1.0

Model : ISKAA
File Name : LA-3481P
1

ATI VGA/B LS-3486P Rev 1.0
SW/B LS-3482P Rev 1.0

Mobile Merom

Santa Rosa Platform

Fan Control

Thermal Sensor
ADM1032ARMZ

uFCPGA-478 CPU

page 4

Clock Generator
ICS 9LPR365

page 4

page 4,5,6

CRT/B LS-3483P Rev 1.0
1

USB/B LS-3484P Rev 1.0
Robson/B LS-3445P Rev 1.0

page 16

Finger Print/B LS-3401P Rev 1.0
H_A#(3..35)
H_D#(0..63)

HDMI Conn

LCD Conn.

page 18

CRT & TV-out

page 19

FSB
667/800MHz 1.05V

Intel Crestline MCH

page 17

FCBGA 1299
ATI M72/76
with 256/512
VRAM

2

VGA/B Conn.

3G

Int. Camera
USB x 1 page

USB port 7

Mini-Card

New Card socket

page 31

USB port 9

PCI-E BUS

3.3V 48MHz

USB port 2

USB

2.5GHz

Robson

PCI BUS

3

Azalia
SATA1.5GHz
PATA

WLAN

page 26

page 31

USB/B conn
33

USB2.0
Bluetooth Conn

page 33

page 20,21,22,23

page 31

USB port 4, 5

2

page 33

USB port 0, 1

USB port 8

3.3V 480MHz

3.3V ATA-100

RTL8111B/RTL8101E

mBGA-676

3.3V 33 MHz

10/100/1000 LAN

USB x 2
conn page

33

3.3V 24.576MHz/48Mhz

Mini-Card

page 14,15

DMI X4

page 30

Intel ICH8-M
Mini-Card

BANK 0, 1, 2, 3

Dual Channel

page 7,8,9,10,11,12,13

PCI-Express x 16

page 19

DDR2-SO-DIMM X2

DDR2 667MHz 1.8V

USB port 6

Tweeter/HP Amplifier
& Int-Mic

USB1.1
Finger Printer

page 28

APA2056

page 33

MDC V1.5
page 30

RJ45/11 CONN

3

page 26

LPC BUS

HD Audio Codec

3.3V 33 MHz

ALC268

page 27

CardBus Controller
TI PCI8412

SATA 0

SATA HDD Connector
page 32

page 24,25

LED

SATA 1

page 34

Slot 0

page 25

RTC CKT.

1394 port

page 24

5in1 Slot

ENE KB926

SATA HDD Connector

Audio Jack

page 32

page 24

page 28

page 29

page 21

PATA Slave

PATA ODD Connector

Power On/Off CKT.

page 32

page 34
4

Touch Pad
DC/DC Interface CKT.

page 34

Int.KBD

SPI BIOS
page 34

page 34

4

CIR
page 33

page 35
Compal Secret Data

Security Classification

Power Circuit DC/DC

2006/08/05

Issued Date

2007/08/05

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Page 36~43

Date:

A

B

C

D

Compal Electronics, Inc.
Block Diagram
Document Number

Rev
2.0

LA-3481P
Sheet

Tuesday, May 22, 2007
E

2

of

47

5

4

3

Voltage Rails

2

Board ID / SKU ID Table for AD channel
S0-S1

S3

Adapter power supply (18.5V)

N/A

N/A

N/A

B+

AC or battery power rail for power circuit

N/A

N/A

N/A

+VCC_CORE

Core voltage for CPU

ON

OFF

OFF

+0.9VS

0.9V switched power rail for DDRII Vtt

ON

OFF

OFF

+1.05VS

1.05V power rail for Processor I/O and MCH/ICH core power
ON

OFF

Vcc
Ra/Rc/Re

S5

OFF
OFF

Power Plane

Description

VIN

Board ID

D

+1.25VS

1.25V power rail for MCH/ICH core power

ON

OFF

+1.5VS

1.5V switched power rail for PCI-E interface

ON

OFF

1.8V power rail for DDRII

ON

ON

0
1
2
3
4
5
6
7

OFF

+1.8V

OFF
OFF

+1.8VS

1.8V switched power rail

ON

OFF

+2.5VS

2.5V switched power rail for MCH video PLL

ON

OFF

3.3V always on power rail

ON

ON

3.3V +/- 5%
100K +/- 1%
Rb / Rd / Rf
0
8.2K +/- 1%
18K +/- 1%
33K +/- 1%
56K +/- 1%
100K +/- 1%
200K +/- 1%
NC

V AD_BID min
0V
0.216 V
0.436 V
0.712 V
1.036 V
1.453 V
1.935 V
2.500 V

V AD_BID typ
0V
0.250 V
0.503 V
0.819 V
1.185 V
1.650 V
2.200 V
3.300 V

V AD_BID max
0.100 V
0.289 V
0.538 V
0.875 V
1.264 V
1.759 V
2.341 V
3.300 V

D

OFF

+3VALW

ON*

+3VS

3.3V switched power rail

ON

OFF

OFF

+5VALW

5V always on power rail

ON

ON

ON*

+5VS

5V switched power rail

ON

OFF

OFF

+RTC_VCC

RTC power

ON

ON

ON

BOARD ID Table
Board ID
0
1
2
3
4
5
6
7

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
C

External PCI Devices
DEVICE

PCI Device ID

IDSEL #

REQ/GNT #

PIRQ

1394

D0

AD20

2

A,B,C,D

CARD BUS

D4

AD20

2

D4

AD20

2

A,B,C,D

BTO Option Table
BTO Item
2nd HDD

BOM Structure
2HDD@
100M@
LAN
1000M@
WLAN
WLAN@
GM@
NB
PM@
BT
BT@
MIC
MIC@
CIR
CIR@
FINGER PRINT
FP@
HDMI
HDMI@

PCB Revision
0.1
0.2
0.3
0.4
1.0
2.0
2A

A,B,C,D

5IN1

SKU ID Table
SKU ID
0
1
2
3
4
5
6
7

KB926 I2C / SMBUS ADDRESSING
DEVICE

HEX

ADDRESS

SM1 24C16

A0H

1010000Xb

SM1 SMART BATTERY

16H

0001011Xb

SM2 ADM0132
CPU THERMAL MONITOR

B

1

98H

1001100Xb

Camera

Camera@

Robson

Robson@

Express Card

NEWCARD@

HD-DVD

SKU
10
10G

C

3G@
B

USB PORT LIST
ICH8-M SM Bus address
DEVICE

HEX

ADDRESS

DDR SO-DIMM 0

A0

10100000

DDR SO-DIMM 1

A4

10100100

CLOCK GENERATOR (EXT.)

D2

DEVICE

PORT
0
1
2
3
4
5
6
7
8
9

11010010

RIGHT USB Port (Samll Board)
RIGHT USB Port (Samll Board)
3G Card

N.C.
LEFT USB Port
LEFT USB Port

Fingerprint or Felica
Blue Tooth
Internal Camera
New Card

A

A

Compal Secret Data

Security Classification
2006/08/05

Issued Date

2007/08/05

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

Compal Electronics, Inc.
Notes List
Document Number

Rev
2.0

LA-3481P
Sheet

Tuesday, May 22, 2007
1

3

of

47

5

4

3

2

1

+5VS

7

2
B

Q53
FMMT619_SOT23
D1
1

R629
R629
100_0402_5%

E

4
2
10K_0402_5%

+3VS

2
1

R20
1 R20
2
8.2K_0402_5%

2
D2

R23
R23 1

H_IERR#

R14
R14

2

1

56_0402_5%

ITP_PREQ

R604 2

1

54.9_0402_1%

ITP_TDI

R11
R11

2

1

150_0402_1%

@ R605 2

1

54.9_0402_1%

Please add the 10uf capacitor if the
+5VS power source not stable.

JP2
JP2

ITP_TDO

1

1
2
3

1
2
3

4
5

GND
GND

D

ITP_TMS

R10

2

1

39_0402_1%

H_PROCHOT#

R310
R310 2

1

56_0402_5%

ITP_TCK

R22

2

1 27_0402_1%

ITP_TRST#

R21
R21

2

1 649_0402_5%

ACES_85205-03001

C13
@
2 1000P_0402_50V7K

2
10K_0402_5%

+1.05VS

Place close to CPU within 500mil

C926
1
2
@
10U_0805_10V4Z

+FAN1_VOUT

2

1
R19
R19

0.1U_0402_16V4Z

D

1

1N4148_SOT23

C925
@

1SS355_SOD323

P

C
0

-

1

PU5B

3

6

+

G

@ LM358DT_SO8
5

& lt; 29 & gt; EN_DFAN1

8

VS

& lt; 7 & gt;

H_A#[3..35]

H_A#[3..35]

& lt; 29 & gt; FAN_SPEED1
1
C14
1000P_0402_50V7K
JP1A

1

@
2 180P_0402_50V8J

H_INIT#

C2

1

@
2 180P_0402_50V8J

1

@
2 180P_0402_50V8J

D5
C6
B4
A3

1

H4

H_LOCK#

H_LOCK#

& lt; 7 & gt;

C1
F3
F4
G3
G2

H_RESET#
H_RS#0
H_RS#1
H_RS#2
H_TRDY#

H_RESET#
H_RS#0
H_RS#1
H_RS#2
H_TRDY#

& lt; 7 & gt;
& lt; 7 & gt;
& lt; 7 & gt;
& lt; 7 & gt;
& lt; 7 & gt;

G6
E4

H_HIT#
H_HITM#

H_HIT#
H_HITM#

& lt; 7 & gt;
& lt; 7 & gt;

H_PROCHOT#

C

1 OCP#
Q1
@ MMBT3904_SOT23
3

OCP#

& lt; 22 & gt;

+1.05VS

1

LOCK#

R16
@ 56_0402_5%
22

CONTROL

& lt; 21 & gt;

R304
@ 330_0402_5%
2

AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20

ITP_PREQ
ITP_TCK
ITP_TDI
ITP_TDO
ITP_TMS
ITP_TRST#
ITP_DBRESET#

2

XDP/ITP SIGNALS

BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
PRDY#
PREQ#
TCK
TDI
TDO
TMS
TRST#
DBR#

H_THERMTRIP#
ITP_DBRESET# & lt; 22 & gt;

3
1
Q51
@ MMBT3904_SOT23

MAINPWON & lt; 36,37,39 & gt;

THERMAL
PROCHOT#
THERMDA
THERMDC

STPCLK#
LINT0
LINT1
SMI#
RSVD[01]
RSVD[02]
RSVD[03]
RSVD[04]
RSVD[05]
RSVD[06]
RSVD[07]
RSVD[08]
RSVD[09]
RSVD[10]

& lt; 7 & gt;

H_INIT#

THERMTRIP#

D21
A24
B25

H_PROCHOT#
H_THERMDA
H_THERMDC

C7

H_THERMTRIP#

H_THERMDA, H_THERMDC routing together,
Trace width / Spacing = 10 / 10 mil
H_THERMTRIP# & lt; 8,21 & gt;
B

H CLK
BCLK[0]
BCLK[1]

A22
A21

CLK_CPU_BCLK
CLK_CPU_BCLK#

CLK_CPU_BCLK & lt; 16 & gt;
CLK_CPU_BCLK# & lt; 16 & gt;

Thermal Sensor ADM1032ARM
+3VS

1

H_INTR

2

H_A20M#

C3

H_STPCLK#
H_INTR
H_NMI
H_SMI#

H_BR0#

C

C1

H_STPCLK#
H_INTR
H_NMI
H_SMI#

H_IERR#
H_INIT#

E
E

& lt; 21 & gt;
& lt; 21 & gt;
& lt; 21 & gt;
& lt; 21 & gt;

A20M#
FERR#
IGNNE#

H_BR0#

D20
B3

ICH

B

A6
A5
C4

F1

+1.05VS

H_DEFER# & lt; 7 & gt;
H_DRDY# & lt; 7 & gt;
H_DBSY# & lt; 7 & gt;

HIT#
HITM#

A[17]#
A[18]#
A[19]#
A[20]#
A[21]#
A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
A[32]#
A[33]#
A[34]#
A[35]#
ADSTB[1]#

H_A20M#
H_FERR#
H_IGNNE#

H_DEFER#
H_DRDY#
H_DBSY#

& lt; 7 & gt;
& lt; 7 & gt;
& lt; 7 & gt;

RESET#
RS[0]#
RS[1]#
RS[2]#
TRDY#

REQ[0]#
REQ[1]#
REQ[2]#
REQ[3]#
REQ[4]#

M4
N5
T2
V3
B2
C3
D2
D22
D3
F6

& lt; 21 & gt; H_A20M#
& lt; 21 & gt; H_FERR#
& lt; 21 & gt; H_IGNNE#

H5
F21
E1

H_ADS#
H_BNR#
H_BPRI#

B

Y2
U5
R3
W6
U4
Y5
U1
R4
T5
T3
W2
W5
Y4
U2
V4
W3
AA4
AB2
AA3
V1

H_ADS#
H_BNR#
H_BPRI#

IERR#
INIT#

BR0#

ADDR GROUP 1
ADDR GROUP 1

& lt; 7 & gt; H_ADSTB#1

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADSTB#1

DEFER#
DRDY#
DBSY#

H1
E2
G5

C

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

K3
H2
K2
J3
L1

ADS#
BNR#
BPRI#

E
E

& lt; 7 & gt;
& lt; 7 & gt;
& lt; 7 & gt;
& lt; 7 & gt;
& lt; 7 & gt;

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

A[3]#
A[4]#
A[5]#
A[6]#
A[7]#
A[8]#
A[9]#
A[10]#
A[11]#
A[12]#
A[13]#
A[14]#
A[15]#
A[16]#
ADSTB[0]#

B

& lt; 7 & gt; H_ADSTB#0

J4
L5
L4
K5
M3
N2
J1
N3
P5
P2
L2
P4
P1
R1
M1

ADDR GROUP 0
ADDR GROUP 0

C

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_ADSTB#0

RESERVED

2

conn@ Merom Ball-out Rev 1a
C10

1

C9
C9
0.1U_0402_16V4Z

U1
H_THERMDA

2

D+

VDD1

H_THERMDC

3

D-

ALERT#

6

& lt; 19,29 & gt; EC_SMB_CK2

8

SCLK

THERM#

4

& lt; 19,29 & gt; EC_SMB_DA2

7

SDATA

GND

5

2200P_0402_50V7K

C4

1

@
2 180P_0402_50V8J

H_NMI

C5

1

@
2 180P_0402_50V8J

H_SMI#

C6

2

1

@
2 180P_0402_50V8J

H_STPCLK#

C7

1

@
2 180P_0402_50V8J

H_IGNNE#

C8

1

@
2 180P_0402_50V8J

1

H_FERR#

A

ADM1032ARMZ_RM8

A

Place Caps Close to CPU Socket
Compal Secret Data

Security Classification
2006/08/05

Issued Date

2007/08/05

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

Compal Electronics, Inc.
Merom(1/3)-AGTL+/XDP
Document Number

Rev
2.0

LA-3481P
Sheet

Tuesday, May 22, 2007
1

4

of

47

3

2

1

+VCC_CORE

1

R732
R732

+GTL_REF0
TEST1
TEST2
TEST4

@ 0_0402_5%
& lt; 16 & gt; CPU_BSEL0
& lt; 16 & gt; CPU_BSEL1
& lt; 16 & gt; CPU_BSEL2

GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6

B22
B23
C21

@ 0.1U_0402_16V4Z

2

AD26
C23
D25
C24
AF26
AF1
A26

BSEL[0]
BSEL[1]
BSEL[2]

COMP[0]
COMP[1]
COMP[2]
COMP[3]

R26
U26
AA1
Y1

DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#
PSI#

MISC

E5
B5
D24
D6
D7
AE6

COMP0
COMP1
COMP2
COMP3
H_DPSLP#
H_PWRGOOD
H_CPUSLP#

H_DPRSTP# & lt; 8,21,43 & gt;
H_DPSLP# & lt; 21 & gt;
H_DPWR# & lt; 7 & gt;
H_PWRGOOD & lt; 21 & gt;
H_CPUSLP# & lt; 7 & gt;
H_PSI#
& lt; 43 & gt;

conn@ Merom Ball-out Rev 1a

CPU_BSEL
166

B

200

CPU_BSEL2

CPU_BSEL1

CPU_BSEL0

0

1

Resistor placed within
0.5 " of CPU pin.Trace
should be at least 25
mils away from any other
toggling signal.
COMP[0,2] trace width is
18 mils. COMP[1,3] trace
width is 4 mils.

1

0

1

0

VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]
VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]

G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21

VCCA[01]
VCCA[02]

B26
C26

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

AD6
AF5
AE5
AF4
AE3
AF3
AE2

VCCSENSE

AF7

VCCSENSE

VSSSENSE

AE7

VSSSENSE

D

+1.05VS

C

1
+ C17
2

330U_D2E_2.5VM_R9
& lt; BOM Structure & gt;

+1.5VS
CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6

& lt; 43 & gt;
& lt; 43 & gt;
& lt; 43 & gt;
& lt; 43 & gt;
& lt; 43 & gt;
& lt; 43 & gt;
& lt; 43 & gt;

1

2

1

2

0.01U_0402_25V7K

C868

2 @ 1K_0402_5%
2 @ 1K_0402_5%

H_DSTBN#3 & lt; 7 & gt;
H_DSTBP#3 & lt; 7 & gt;
H_DINV#3 & lt; 7 & gt;

VCC[001]
VCC[002]
VCC[003]
VCC[004]
VCC[005]
VCC[006]
VCC[007]
VCC[008]
VCC[009]
VCC[010]
VCC[011]
VCC[012]
VCC[013]
VCC[014]
VCC[015]
VCC[016]
VCC[017]
VCC[018]
VCC[019]
VCC[020]
VCC[021]
VCC[022]
VCC[023]
VCC[024]
VCC[025]
VCC[026]
VCC[027]
VCC[028]
VCC[029]
VCC[030]
VCC[031]
VCC[032]
VCC[033]
VCC[034]
VCC[035]
VCC[036]
VCC[037]
VCC[038]
VCC[039]
VCC[040]
VCC[041]
VCC[042]
VCC[043]
VCC[044]
VCC[045]
VCC[046]
VCC[047]
VCC[048]
VCC[049]
VCC[050]
VCC[051]
VCC[052]
VCC[053]
VCC[054]
VCC[055]
VCC[056]
VCC[057]
VCC[058]
VCC[059]
VCC[060]
VCC[061]
VCC[062]
VCC[063]
VCC[064]
VCC[065]
VCC[066]
VCC[067]

AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20

Near pin B26

R707 1
R708 1

H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

A7
A9
A10
A12
A13
A15
A17
A18
A20
B7
B9
B10
B12
B14
B15
B17
B18
B20
C9
C10
C12
C13
C15
C17
C18
D9
D10
D12
D14
D15
D17
D18
E7
E9
E10
E12
E13
E15
E17
E18
E20
F7
F9
F10
F12
F14
F15
F17
F18
F20
AA7
AA9
AA10
AA12
AA13
AA15
AA17
AA18
AA20
AB9
AC10
AB10
AB12
AB14
AB15
AB17
AB18

C18
C18

& lt; 7 & gt; H_DSTBN#1
& lt; 7 & gt; H_DSTBP#1
& lt; 7 & gt;
H_DINV#1

AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20

R33
R33
27.4_0402_1%
2
1

C

D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#
DSTBN[3]#
DSTBP[3]#
DINV[3]#

DATA GRP 1
DATA GRP 1

Close to CPU pin AD26
within 500mils.

D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#

H_DSTBN#2 & lt; 7 & gt;
H_DSTBP#2 & lt; 7 & gt;
H_DINV#2 & lt; 7 & gt;
H_D#[48..63] & lt; 7 & gt;

R32
R32
54.9_0402_1%
2
1

1
2

R37
R37
2K_0402_1%

JP1C

H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47

R31
R31
27.4_0402_1%
2
1

2

& lt; 7 & gt; H_DSTBN#0
& lt; 7 & gt; H_DSTBP#0
& lt; 7 & gt;
H_DINV#0
& lt; 7 & gt; H_D#[16..31]

+GTL_REF0

D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#
DSTBN[2]#
DSTBP[2]#
DINV[2]#

Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22

DATA GRP 2

1
R35
R35
1K_0402_1%

DATA GRP 0
DATA GRP 0

+1.05VS

D[0]#
D[1]#
D[2]#
D[3]#
D[4]#
D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#

H_D#16 N22
H_D#17 K25
H_D#18 P26
H_D#19 R23
H_D#20 L23
H_D#21 M24
H_D#22 L22
H_D#23 M23
H_D#24 P25
H_D#25 P23
H_D#26 P22
H_D#27 T24
H_D#28 R24
H_D#29 L25
H_D#30 T25
H_D#31 N25
L26
M26
N24

D

+VCC_CORE

H_D#[32..47] & lt; 7 & gt;

JP1B
H_D#0 E22
H_D#1 F24
H_D#2 E26
H_D#3 G22
H_D#4 F23
H_D#5 G25
H_D#6 E25
H_D#7 E23
H_D#8 K24
H_D#9 G24
H_D#10 J24
H_D#11 J23
H_D#12 H22
H_D#13 F26
H_D#14 K22
H_D#15 H23
J26
H26
H25

R30
R30
54.9_0402_1%
2
1

H_D#[0..15]

DATA GRP 3

& lt; 7 & gt;

10U_0805_10V4Z
C19
C19

4

Near pin C26

5

VCCSENSE & lt; 43 & gt;
VSSSENSE & lt; 43 & gt;
B

conn@ Merom Ball-out Rev 1a
.

+VCC_CORE
R34
R34
100_0402_1%
2

VCCSENSE

R36
R36
100_0402_1%
1
2

VSSSENSE

1

Close to CPU pin
within 500mils.

Length match
within 25 mils.
The trace
width/space/other
is 20/7/25.

A

A

Compal Secret Data

Security Classification
2006/08/05

Issued Date

2007/08/05

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

Compal Electronics, Inc.
Merom(2/3)-AGTL+/PWR
Document Number

Rev
2.0

LA-3481P
Sheet

Tuesday, May 22, 2007
1

5

of

47

5

4

3

2

1

+VCC_CORE

1
Place these capacitors on L8
(North side,Secondary Layer)

2

1

C21
10U_0805_6.3V6M

2

1

C22
C22
10U_0805_6.3V6M

2

1

C23
C23
10U_0805_6.3V6M

2

1

C24
C24
10U_0805_6.3V6M

2

1

C25
C25
10U_0805_6.3V6M

2

1

C26
C26
10U_0805_6.3V6M

2

1

C27
C27
10U_0805_6.3V6M

2

C28
C28
10U_0805_6.3V6M

+VCC_CORE
D

D

JP1D
VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]

P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25

Place these capacitors on L8
(North side,Secondary Layer)

2

1

C29
C29
10U_0805_6.3V6M

2

1

C30
C30
10U_0805_6.3V6M

2

1

C31
C31
10U_0805_6.3V6M

2

1

C32
C32
10U_0805_6.3V6M

2

1

C33
C33
10U_0805_6.3V6M

2

1

C34
C34
10U_0805_6.3V6M

2

1

C35
C35
10U_0805_6.3V6M

2

C36
C36
10U_0805_6.3V6M

+VCC_CORE

1
Place these capacitors on L8
(Sorth side,Secondary Layer)

2

1

C37
C37
10U_0805_6.3V6M

2

1

C38
C38
10U_0805_6.3V6M

2

1

C39
C39
10U_0805_6.3V6M

2

1

C40
C40
10U_0805_6.3V6M

2

1

C41
C41
10U_0805_6.3V6M

2

1

C42
C42
10U_0805_6.3V6M

2

1

C43
C43
10U_0805_6.3V6M

2

C44
C44
10U_0805_6.3V6M

+VCC_CORE

1
Place these capacitors on L8
(Sorth side,Secondary Layer)

2

1

C45
C45
10U_0805_6.3V6M

2

1

C46
C46
10U_0805_6.3V6M

2

1

C47
C47
10U_0805_6.3V6M

2

1

C48
C48
10U_0805_6.3V6M

2

1

C49
C49
10U_0805_6.3V6M

2

1

C50
C50
10U_0805_6.3V6M

2

1

C51
C51
10U_0805_6.3V6M

2

C52
C52
10U_0805_6.3V6M

Mid Frequence Decoupling
C

+VCC_CORE
330U_D2E_2.5VM_R9

South Side Secondary
of CPU Socket
@ C53

1

1

+

C54

330U_D2E_2.5VM_R9
2

330U_D2E_2.5VM_R9

1

+

+

C55

2

1
C56

2

330U_D2E_2.5VM_R9

1

+

C57

2

330U_D2E_2.5VM_R9

+

1

@
C58

North Side Secondary
of CPU Socket

ESR & lt; = 1.5m ohm
Capacitor & gt; 1980uF

+

2

2

330uF ESR 7m ohm X 6 PCS

330U_D2E_2.5VM_R9

B

+1.05VS

1
C59

@

B

VSS[001]
VSS[002]
VSS[003]
VSS[004]
VSS[005]
VSS[006]
VSS[007]
VSS[008]
VSS[009]
VSS[010]
VSS[011]
VSS[012]
VSS[013]
VSS[014]
VSS[015]
VSS[016]
VSS[017]
VSS[018]
VSS[019]
VSS[020]
VSS[021]
VSS[022]
VSS[023]
VSS[024]
VSS[025]
VSS[026]
VSS[027]
VSS[028]
VSS[029]
VSS[030]
VSS[031]
VSS[032]
VSS[033]
VSS[034]
VSS[035]
VSS[036]
VSS[037]
VSS[038]
VSS[039]
VSS[040]
VSS[041]
VSS[042]
VSS[043]
VSS[044]
VSS[045]
VSS[046]
VSS[047]
VSS[048]
VSS[049]
VSS[050]
VSS[051]
VSS[052]
VSS[053]
VSS[054]
VSS[055]
VSS[056]
VSS[057]
VSS[058]
VSS[059]
VSS[060]
VSS[061]
VSS[062]
VSS[063]
VSS[064]
VSS[065]
VSS[066]
VSS[067]
VSS[068]
VSS[069]
VSS[070]
VSS[071]
VSS[072]
VSS[073]
VSS[074]
VSS[075]
VSS[076]
VSS[077]
VSS[078]
VSS[079]
VSS[080]
VSS[081]

+

2

conn@ Merom Ball-out Rev 1a
.

330U_D2E_2.5VM_R9

C

A4
A8
A11
A14
A16
A19
A23
AF2
B6
B8
B11
B13
B16
B19
B21
B24
C5
C8
C11
C14
C16
C19
C2
C22
C25
D1
D4
D8
D11
D13
D16
D19
D23
D26
E3
E6
E8
E11
E14
E16
E19
E21
E24
F5
F8
F11
F13
F16
F19
F2
F22
F25
G4
G1
G23
G26
H3
H6
H21
H24
J2
J5
J22
J25
K1
K4
K23
K26
L3
L6
L21
L24
M2
M5
M22
M25
N1
N4
N23
N26
P3

1

1

2

C60
C60
0.1U_0402_16V4Z

1

2

1

C61
C61
0.1U_0402_16V4Z

2

1

C62
C62
0.1U_0402_16V4Z

2

C63
C63
0.1U_0402_16V4Z

1

2

1

C64
C64
0.1U_0402_16V4Z

2

C65
C65
0.1U_0402_16V4Z

Place these inside socket
cavity on Bottom layer (North
side Secondary)

A

A

Compal Secret Data

Security Classification
2006/08/05

Issued Date

2007/08/05

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

Compal Electronics, Inc.
Merom(3/3)-GND & Bypass
Document Number

Rev
2.0

LA-3481P
Sheet

Tuesday, May 22, 2007
1

6

of

47

4

& lt; 5 & gt;

H_D#[0..63]

1
R40
R40

2

221_0603_1%

2

H_SWNG1

1

R41
R41

2

C66
C66
0.1U_0402_16V4Z

1

100_0402_1%

1

H_RCOMP

R42
R42

2

24.9_0402_1%

C

10-mil wide with 20-mil spacing

+1.05VS
R43
R43

2
R44
R44

2

54.9_0402_1%
1 H_SCOMP
54.9_0402_1%
1 H_SCOMP#

impedance is 55 ohm
Width is 10mil

E2
G2
G7
M6
H7
H3
G4
F3
N8
H2
M10
N12
N9
H5
P13
K9
M2
W10
Y8
V4
M3
J1
N5
N3
W6
W9
N2
Y7
Y9
P4
W3
N1
AD12
AE3
AD9
AC9
AC7
AC14
AD11
AC11
AB2
AD7
AB1
Y3
AC6
AE2
AC5
AG3
AJ9
AH8
AJ14
AE9
AE11
AH12
AJ5
AH5
AJ6
AE7
AJ7
AJ2
AE5
AJ3
AH2
AH13

H_A#[3..35]

H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63

H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35

B

H_SWNG1
H_RCOMP

H_AVREF

1

+1.05VS

B3
C2

H_SWING
H_RCOMP

H_SCOMP
H_SCOMP#
& lt; 4 & gt; H_RESET#
& lt; 5 & gt; H_CPUSLP#

2

U3A
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

+1.05VS

D

3

HOST

5

W1
W2

H_SCOMP
H_SCOMP#

H_RESET#
H_CPUSLP#

B6
E5

H_CPURST#
H_CPUSLP#

B9
A9

H_AVREF
H_DVREF

J13
B11
C11
M11
C15
F16
L13
G17
C14
K16
B13
L16
J17
B14
K19
P15
R17
B16
H20
L19
D17
M17
N16
J19
B18
E19
B17
B15
E17
C18
A19
B19
N19
G12
H17
G20
C8
E8
F12
D6
C10
AM5
AM7
H8
K7
E4
C6
G10
B7

H_ADS#
H_ADSTB#0
H_ADSTB#1
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DBSY#
CLK_MCH_BCLK
CLK_MCH_BCLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#

H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3

K5
L2
AD13
AE13

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3

M7
K3
AD2
AH11

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3

H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3

L7
K2
AC2
AJ10

H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4

M14
E13
A11
H13
B12

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_RS#_0
H_RS#_1
H_RS#_2

E12
D7
D8

H_RS#0
H_RS#1
H_RS#2

& lt; 4 & gt;

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

H_ADS#
H_ADSTB#_0
H_ADSTB#_1
H_BNR#
H_BPRI#
H_BREQ#
H_DEFER#
H_DBSY#
HPLL_CLK
HPLL_CLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#

1

D

H_ADS# & lt; 4 & gt;
H_ADSTB#0 & lt; 4 & gt;
H_ADSTB#1 & lt; 4 & gt;
H_BNR# & lt; 4 & gt;
H_BPRI# & lt; 4 & gt;
H_BR0#
& lt; 4 & gt;
H_DEFER# & lt; 4 & gt;
H_DBSY# & lt; 4 & gt;
CLK_MCH_BCLK & lt; 16 & gt;
CLK_MCH_BCLK# & lt; 16 & gt;
H_DPWR# & lt; 5 & gt;
H_DRDY# & lt; 4 & gt;
H_HIT#
& lt; 4 & gt;
H_HITM# & lt; 4 & gt;
H_LOCK# & lt; 4 & gt;
H_TRDY# & lt; 4 & gt;

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

& lt; 5 & gt;
& lt; 5 & gt;
& lt; 5 & gt;
& lt; 5 & gt;

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3

C

& lt; 5 & gt;
& lt; 5 & gt;
& lt; 5 & gt;
& lt; 5 & gt;

H_DSTBP#0 & lt; 5 & gt;
H_DSTBP#1 & lt; 5 & gt;
H_DSTBP#2 & lt; 5 & gt;
H_DSTBP#3 & lt; 5 & gt;
H_REQ#[0..4] & lt; 4 & gt;

H_RS#[0..2]

B

& lt; 4 & gt;

CRESTLINE ES_FCBGA1299
PMR3@

2

R211
R211
1K_0402_1%

1

H_AVREF

1

2

0.1U_0402_16V4Z

2

R212
R212
2K_0402_1%

C67
C67

A

A

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2006/08/05

Issued Date

Deciphered Date

2007/08/05

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

Crestline (1/7)
Document Number

Rev
2.0

LA-3481P
Tuesday, May 22, 2007

Sheet
1

7

of

47

4

3

* (Default)

1 = SDVO Device Present
& lt; 14 & gt; DDRA_SMA14
& lt; 15 & gt; DDRB_SMA14

DDRA_SMA14
DDRB_SMA14

MCH_CFG_5
@ 4.02K_0402_1%

MCH_CFG_9
@ 4.02K_0402_1%

R56
R56

@ 4.02K_0402_1%

R57
R57

@ 4.02K_0402_1%

MCH_CFG_12
MCH_CFG_13
C

MCH_CFG_16

MCH_CFG_19
R58

BK31
BL31

SM_RCOMP_VOH
SM_RCOMP_VOL

AR49
AW4

SM_VREF

SM_RCOMP_VOL

& lt; 14 & gt;
& lt; 14 & gt;
& lt; 15 & gt;
& lt; 15 & gt;

R50
R50
1K_0402_1%

SMRCOMPP
SMRCOMPN

MCH_CFG_19
MCH_CFG_20

R733
@ 56_0402_5%

CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20

SMRCOMPP

DPLL_REF_CLK
DPLL_REF_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#

B42
C42
H48
H47

CLK_DREF_96M
CLK_DREF_96M#
CLK_DREF_SSC
CLK_DREF_SSC#

K44
K45

CLK_MCH_3GPLL
CLK_MCH_3GPLL#

DMI_ITX_MRX_N0
DMI_ITX_MRX_N1
DMI_ITX_MRX_N2
DMI_ITX_MRX_N3

DMI_ITX_MRX_N0
DMI_ITX_MRX_N1
DMI_ITX_MRX_N2
DMI_ITX_MRX_N3

& lt; 22 & gt;
& lt; 22 & gt;
& lt; 22 & gt;
& lt; 22 & gt;

AM47
AJ39
AN41
AN45

DMI_ITX_MRX_P0
DMI_ITX_MRX_P1
DMI_ITX_MRX_P2
DMI_ITX_MRX_P3

DMI_ITX_MRX_P0
DMI_ITX_MRX_P1
DMI_ITX_MRX_P2
DMI_ITX_MRX_P3

AJ46
AJ41
AM40
AM44

DMI_MTX_IRX_N0
DMI_MTX_IRX_N1
DMI_MTX_IRX_N2
DMI_MTX_IRX_N3

DMI_MTX_IRX_N0
DMI_MTX_IRX_N1
DMI_MTX_IRX_N2
DMI_MTX_IRX_N3

& lt; 22 & gt;
& lt; 22 & gt;
& lt; 22 & gt;
& lt; 22 & gt;

DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3

AJ47
AJ42
AM39
AM43

DMI_MTX_IRX_P0
DMI_MTX_IRX_P1
DMI_MTX_IRX_P2
DMI_MTX_IRX_P3

DMI_MTX_IRX_P0
DMI_MTX_IRX_P1
DMI_MTX_IRX_P2
DMI_MTX_IRX_P3

& lt; 22 & gt;
& lt; 22 & gt;
& lt; 22 & gt;
& lt; 22 & gt;

R71
R71

2
2

PM_BMBUSY#_R
H_DPRSTP#_R
PM_EXTTS#0
PM_EXTTS#1_R

G41
L39
L36
0_0402_5%1
2
J36
AW49
MCH_RSTIN#
R70
AV20
100_0402_5% H_THERMTRIP#
N20
1
2 PM_DPRSLPVR_R G36
0_0402_5%

+3VS

PM_EXTTS#0
10K_0402_5%

+1.8V

R59
R59
1K_0402_1%
SM_VREF
C72
C72

R61
R61
1K_0402_1%

1

0.1U_0402_16V4Z
2

1
R734
1
R735
1
R736
1
R737

R64
R64
1K_0402_1%

2
@ 22K_0402_5%
2
@ 22K_0402_5%
2
@ 22K_0402_5%
2
@ 22K_0402_5%

E36

CL_VREF

R69
R69
392_0402_1%

1

0.1U_0402_16V4Z
2
CL_CLK
CL_DATA
CL_PWROK
CL_RST#
CL_VREF

AM49
AK50
AT43
AN49
AM50

SDVO_CTRL_CLK
SDVO_CTRL_DATA
CLK_REQ#
ICH_SYNC#

H35
K36
G39
G40

TEST_1
TEST_2

CL_CLK0 & lt; 22 & gt;
CL_DATA0 & lt; 22 & gt;
PWROK
& lt; 22,29 & gt;
CL_RST# & lt; 22 & gt;
CL_VREF

SDVO_SDAT
MCH_CLKREQ#
MCH_ICH_SYNC#

A37 MCH_TEST_1
R32 MCH_TEST_2

& lt; 22 & gt;

PM@
0_0402_5%
R757

1
R73

R72
R72

2 0_0402_5%

A

20K_0402_5%

CRESTLINE ES_FCBGA1299
PMR3@

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2006/08/05

Deciphered Date

2007/08/05

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

4

B

+3VS

C73
C73

Issued Date

5

C

SDVO_SDAT

PM_EXTTS#1_R
10K_0402_5%
MCH_CLKREQ#
10K_0402_5%

NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16

E35
A39
C38
B39

GFX_VR_EN

NC

BJ51
BK51
BK50
BL50
BL49
BL3
BL2
BK1
BJ1
E1
A5
C51
B50
A50
A49
BK2

PM_BM_BUSY#
PM_DPRSTP#
PM_EXT_TS#_0
PM_EXT_TS#_1
PWROK
RSTIN#
THERMTRIP#
DPRSLPVR

ME

R68
R68

0_0402_5%1
0_0402_5%1

GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3

MISC

R66
R66
R67
R67

PM

& lt; 14 & gt; PM_EXTTS#0
& lt; 15 & gt; PM_EXTTS#1
& lt; 22,29 & gt; PWROK
& lt; 20,22,26,30,31 & gt; PLT_RST#
& lt; 4,21 & gt; H_THERMTRIP#
& lt; 22,43 & gt; DPRSLPVR

2 20_0402_1%

& lt; 22 & gt;
& lt; 22 & gt;
& lt; 22 & gt;
& lt; 22 & gt;

DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3

2 20_0402_1%

1

CLK_MCH_3GPLL & lt; 16 & gt;
CLK_MCH_3GPLL# & lt; 16 & gt;

AN47
AJ38
AN42
AN46

1

R54
R54

CLK_DREF_96M & lt; 16 & gt;
CLK_DREF_96M# & lt; 16 & gt;
CLK_DREF_SSC & lt; 16 & gt;
CLK_DREF_SSC# & lt; 16 & gt;

PEG_CLK
PEG_CLK#

R52
R52

+1.25VS

2

& lt; 22 & gt; PM_BMBUSY#
& lt; 5,21,43 & gt; H_DPRSTP#

+1.8V

2

1

MCH_CFG_16

C71

1

+1.05VS

MCH_CFG_12
MCH_CFG_13

C70
C70

2.2U_0603_6.3V6K
0.01U_0402_25V7K

& lt; 14 & gt;
& lt; 14 & gt;
& lt; 15 & gt;
& lt; 15 & gt;

DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3

CFG

Refer Strap
Pin Table

D

2

MCH_CFG_9

P27
N27
N24
C21
C23
F23
N23
G23
J20
C20
R24
L23
J23
E23
E20
K23
M20
M24
L32
N33
L35

2.2U_0603_6.3V6K
0.01U_0402_25V7K

SMRCOMPN

DMI

MCH_CFG_5

R65

BL15
BK14

SM_VREF_0
SM_VREF_1

GRAPHICS VID

MCH_CLKSEL0
MCH_CLKSEL1
MCH_CLKSEL2

& lt; 16 & gt; MCH_CLKSEL0
& lt; 16 & gt; MCH_CLKSEL1
& lt; 16 & gt; MCH_CLKSEL2

CFG[19:18] have internal pull down

R63

DDRA_ODT0
DDRA_ODT1
DDRB_ODT0
DDRB_ODT1

SM_RCOMP_VOH
SM_RCOMP_VOL

@ 4.02K_0402_1%

CFG[17:3] have internal pull up

R62

BH18
BJ15
BJ14
BE16

SM_RCOMP
SM_RCOMP#

Intel recommend 4.02K_1%

A

DDRA_SCS0#
DDRA_SCS1#
DDRB_SCS0#
DDRB_SCS1#

SM_ODT_0
SM_ODT_1
SM_ODT_2
SM_ODT_3

MCH_CFG_20

B

BG20
BK16
BG16
BE13

+3VS

4.02K_0402_1%

R60
R60

SM_CS#_0
SM_CS#_1
SM_CS#_2
SM_CS#_3

R49
3.01K_0402_1%

& lt; 14 & gt;
& lt; 14 & gt;
& lt; 15 & gt;
& lt; 15 & gt;

DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3

@ 4.02K_0402_1%

R55

DDRA_CKE0
DDRA_CKE1
DDRB_CKE0
DDRB_CKE1

C69

2

R53

BE29
AY32
BD39
BG37

C68

2

R51
R51

SM_CKE_0
SM_CKE_1
SM_CKE_3
SM_CKE_4

SM_RCOMP_VOH

& lt; 14 & gt;
& lt; 14 & gt;
& lt; 15 & gt;
& lt; 15 & gt;

1

0 = No SDVO Device Present

DDRA_CLK0#
DDRA_CLK1#
DDRB_CLK0#
DDRB_CLK1#

R48
1K_0402_1%

1

SDVO_CTRLDATA

RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
RSVD28
RSVD29
RSVD30
RSVD31
RSVD32
RSVD33
RSVD34
RSVD35
RSVD36
RSVD37
RSVD38
RSVD39
RSVD40
RSVD41
RSVD42
RSVD43
RSVD44
RSVD45

AW30
BA23
AW25
AW23

& lt; 14 & gt;
& lt; 14 & gt;
& lt; 15 & gt;
& lt; 15 & gt;

1

CFG20
(PCIE/SDVO select)

H10
B51
BJ20
BK22
BF19
BH20
BK18
BJ18
BF23
BG23
BC23
BD24
BJ29
BE24
BH39
AW20
BK20
C48
D47
B44
C44
A35
B37
B36
B34
C34

DDRA_CLK0
DDRA_CLK1
DDRB_CLK0
DDRB_CLK1

2

CFG19

0 = Normal Operation
*(Default)
1 = DMI Lane Reversal Enable
0 = Only PCIE or SDVO is operational.
* (Default)
1 = PCIE/SDVO are operating simu.

AV29
BB23
BA25
AV23

SM_CK#_0
SM_CK#_1
SM_CK#_3
SM_CK#_4

MUXING

CFG16

SM_CK_0
SM_CK_1
SM_CK_3
SM_CK_4

RSVD

CFG[13:12]

RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14

CLK

CFG9
D

P36
P37
R35
N35
AR12
AR13
AM12
AN13
J12
AR37
AM36
AL36
AM37
D20

011 = 667MT/s FSB
010 = 800MT/s FSB
0 = DMI x 2
1 = DMI x 4
* (Default)
0 = Lane Reversal Enable
1 = Normal Operation * (Default)
00 = Reserved
01 = XOR Mode Enabled
10 = All Z Mode Enabled
11 = Normal Operation * (Default)
0 = Dynamic ODT Disabled
1 = Dynamic ODT Enabled * (Default)

CFG5

1

+1.8V

DDR

Strap Pin Table
CFG[2:0]

2

U3B

1

5

3

2

Crestline (2/7)
Document Number

Rev
2.0

LA-3481P
Sheet

Tuesday, May 22, 2007
1

8

of

47

5

4

DDRA_SDQ[0..63]

& lt; 14 & gt; DDRA_SDQ[0..63]

1

DDRB_SDM[0..7]

& lt; 15 & gt; DDRB_SDM[0..7]

DDRA_SMA[0..13]

& lt; 14 & gt; DDRA_SMA[0..13]

2

DDRB_SDQ[0..63]

& lt; 15 & gt; DDRB_SDQ[0..63]

DDRA_SDM[0..7]

& lt; 14 & gt; DDRA_SDM[0..7]

3

DDRB_SMA[0..13]

& lt; 15 & gt; DDRB_SMA[0..13]

D

D

B

U3E

DDRA_SDM0
DDRA_SDM1
DDRA_SDM2
DDRA_SDM3
DDRA_SDM4
DDRA_SDM5
DDRA_SDM6
DDRA_SDM7

SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7

AT46
BE48
BB43
BC37
BB16
BH6
BB2
AP3

DDRA_SDQS0
DDRA_SDQS1
DDRA_SDQS2
DDRA_SDQS3
DDRA_SDQS4
DDRA_SDQS5
DDRA_SDQS6
DDRA_SDQS7

SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7

AT47
BD47
BC41
BA37
BA16
BH7
BC1
AP2

DDRA_SDQS0#
DDRA_SDQS1#
DDRA_SDQS2#
DDRA_SDQS3#
DDRA_SDQS4#
DDRA_SDQS5#
DDRA_SDQS6#
DDRA_SDQS7#

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13

BJ19
BD20
BK27
BH28
BL24
BK28
BJ27
BJ25
BL28
BA28
BC19
BE28
BG30
BJ16

DDRA_SMA0
DDRA_SMA1
DDRA_SMA2
DDRA_SMA3
DDRA_SMA4
DDRA_SMA5
DDRA_SMA6
DDRA_SMA7
DDRA_SMA8
DDRA_SMA9
DDRA_SMA10
DDRA_SMA11
DDRA_SMA12
DDRA_SMA13

SA_CAS#
SA_RAS#
SA_WE#

BL17
BE18
BA19

SA_RCVEN#

AY20

MEMORY

DDRA_SDQS0
DDRA_SDQS1
DDRA_SDQS2
DDRA_SDQS3
DDRA_SDQS4
DDRA_SDQS5
DDRA_SDQS6
DDRA_SDQS7
DDRA_SDQS0#
DDRA_SDQS1#
DDRA_SDQS2#
DDRA_SDQS3#
DDRA_SDQS4#
DDRA_SDQS5#
DDRA_SDQS6#
DDRA_SDQS7#

& lt; 14 & gt;
& lt; 14 & gt;
& lt; 14 & gt;
& lt; 14 & gt;
& lt; 14 & gt;
& lt; 14 & gt;
& lt; 14 & gt;
& lt; 14 & gt;
& lt; 14 & gt;
& lt; 14 & gt;
& lt; 14 & gt;
& lt; 14 & gt;
& lt; 14 & gt;
& lt; 14 & gt;
& lt; 14 & gt;
& lt; 14 & gt;

DDRA_SCAS# & lt; 14 & gt;
DDRA_SRAS# & lt; 14 & gt;
DDRA_SWE# & lt; 14 & gt;

CRESTLINE ES_FCBGA1299
PMR3@

SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63

SB_BS_0
SB_BS_1
SB_BS_2

AY17
BG18
BG36

SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7

AR50
BD49
BK45
BL39
BH12
BJ7
BF3
AW2

DDRB_SDM0
DDRB_SDM1
DDRB_SDM2
DDRB_SDM3
DDRB_SDM4
DDRB_SDM5
DDRB_SDM6
DDRB_SDM7

SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7

AT50
BD50
BK46
BK39
BJ12
BL7
BE2
AV2

DDRB_SDQS0
DDRB_SDQS1
DDRB_SDQS2
DDRB_SDQS3
DDRB_SDQS4
DDRB_SDQS5
DDRB_SDQS6
DDRB_SDQS7

SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7

AU50
BC50
BL45
BK38
BK12
BK7
BF2
AV3

DDRB_SDQS0#
DDRB_SDQS1#
DDRB_SDQS2#
DDRB_SDQS3#
DDRB_SDQS4#
DDRB_SDQS5#
DDRB_SDQS6#
DDRB_SDQS7#

SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13

BC18
BG28
BG25
AW17
BF25
BE25
BA29
BC28
AY28
BD37
BG17
BE37
BA39
BG13

DDRB_SMA0
DDRB_SMA1
DDRB_SMA2
DDRB_SMA3
DDRB_SMA4
DDRB_SMA5
DDRB_SMA6
DDRB_SMA7
DDRB_SMA8
DDRB_SMA9
DDRB_SMA10
DDRB_SMA11
DDRB_SMA12
DDRB_SMA13

SB_CAS#
SB_RAS#
SB_WE#

BE17
AV16
BC17

SB_RCVEN#

B

AT45
BD44
BD42
AW38
AW13
BG8
AY5
AN6

AP49
AR51
AW50
AW51
AN51
AN50
AV50
AV49
BA50
BB50
BA49
BE50
BA51
AY49
BF50
BF49
BJ50
BJ44
BJ43
BL43
BK47
BK49
BK43
BK42
BJ41
BL41
BJ37
BJ36
BK41
BJ40
BL35
BK37
BK13
BE11
BK11
BC11
BC13
BE12
BC12
BG12
BJ10
BL9
BK5
BL5
BK9
BK10
BJ8
BJ6
BF4
BH5
BG1
BC2
BK3
BE4
BD3
BJ2
BA3
BB3
AR1
AT3
AY2
AY3
AU2
AT2

MEMORY

SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7

DDRB_SDQ0
DDRB_SDQ1
DDRB_SDQ2
DDRB_SDQ3
DDRB_SDQ4
DDRB_SDQ5
DDRB_SDQ6
DDRB_SDQ7
DDRB_SDQ8
DDRB_SDQ9
DDRB_SDQ10
DDRB_SDQ11
DDRB_SDQ12
DDRB_SDQ13
DDRB_SDQ14
DDRB_SDQ15
DDRB_SDQ16
DDRB_SDQ17
DDRB_SDQ18
DDRB_SDQ19
DDRB_SDQ20
DDRB_SDQ21
DDRB_SDQ22
DDRB_SDQ23
DDRB_SDQ24
DDRB_SDQ25
DDRB_SDQ26
DDRB_SDQ27
DDRB_SDQ28
DDRB_SDQ29
DDRB_SDQ30
DDRB_SDQ31
DDRB_SDQ32
DDRB_SDQ33
DDRB_SDQ34
DDRB_SDQ35
DDRB_SDQ36
DDRB_SDQ37
DDRB_SDQ38
DDRB_SDQ39
DDRB_SDQ40
DDRB_SDQ41
DDRB_SDQ42
DDRB_SDQ43
DDRB_SDQ44
DDRB_SDQ45
DDRB_SDQ46
DDRB_SDQ47
DDRB_SDQ48
DDRB_SDQ49
DDRB_SDQ50
DDRB_SDQ51
DDRB_SDQ52
DDRB_SDQ53
DDRB_SDQ54
DDRB_SDQ55
DDRB_SDQ56
DDRB_SDQ57
DDRB_SDQ58
DDRB_SDQ59
DDRB_SDQ60
DDRB_SDQ61
DDRB_SDQ62
DDRB_SDQ63

DDRA_SBS0# & lt; 14 & gt;
DDRA_SBS1# & lt; 14 & gt;
DDRA_SBS2# & lt; 14 & gt;

SYSTEM

BB19
BK19
BF29

A

SA_BS_0
SA_BS_1
SA_BS_2

SYSTEM

SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63

DDR

C

AR43
AW44
BA45
AY46
AR41
AR45
AT42
AW47
BB45
BF48
BG47
BJ45
BB47
BG50
BH49
BE45
AW43
BE44
BG42
BE40
BF44
BH45
BG40
BF40
AR40
AW40
AT39
AW36
AW41
AY41
AV38
AT38
AV13
AT13
AW11
AV11
AU15
AT11
BA13
BA11
BE10
BD10
BD8
AY9
BG10
AW9
BD7
BB9
BB5
AY7
AT5
AT7
AY6
BB7
AR5
AR8
AR9
AN3
AM8
AN10
AT9
AN9
AM9
AN11

DDR

U3D
DDRA_SDQ0
DDRA_SDQ1
DDRA_SDQ2
DDRA_SDQ3
DDRA_SDQ4
DDRA_SDQ5
DDRA_SDQ6
DDRA_SDQ7
DDRA_SDQ8
DDRA_SDQ9
DDRA_SDQ10
DDRA_SDQ11
DDRA_SDQ12
DDRA_SDQ13
DDRA_SDQ14
DDRA_SDQ15
DDRA_SDQ16
DDRA_SDQ17
DDRA_SDQ18
DDRA_SDQ19
DDRA_SDQ20
DDRA_SDQ21
DDRA_SDQ22
DDRA_SDQ23
DDRA_SDQ24
DDRA_SDQ25
DDRA_SDQ26
DDRA_SDQ27
DDRA_SDQ28
DDRA_SDQ29
DDRA_SDQ30
DDRA_SDQ31
DDRA_SDQ32
DDRA_SDQ33
DDRA_SDQ34
DDRA_SDQ35
DDRA_SDQ36
DDRA_SDQ37
DDRA_SDQ38
DDRA_SDQ39
DDRA_SDQ40
DDRA_SDQ41
DDRA_SDQ42
DDRA_SDQ43
DDRA_SDQ44
DDRA_SDQ45
DDRA_SDQ46
DDRA_SDQ47
DDRA_SDQ48
DDRA_SDQ49
DDRA_SDQ50
DDRA_SDQ51
DDRA_SDQ52
DDRA_SDQ53
DDRA_SDQ54
DDRA_SDQ55
DDRA_SDQ56
DDRA_SDQ57
DDRA_SDQ58
DDRA_SDQ59
DDRA_SDQ60
DDRA_SDQ61
DDRA_SDQ62
DDRA_SDQ63

AY18

DDRB_SBS0# & lt; 15 & gt;
DDRB_SBS1# & lt; 15 & gt;
DDRB_SBS2# & lt; 15 & gt;

DDRB_SDQS0
DDRB_SDQS1
DDRB_SDQS2
DDRB_SDQS3
DDRB_SDQS4
DDRB_SDQS5
DDRB_SDQS6
DDRB_SDQS7
DDRB_SDQS0#
DDRB_SDQS1#
DDRB_SDQS2#
DDRB_SDQS3#
DDRB_SDQS4#
DDRB_SDQS5#
DDRB_SDQS6#
DDRB_SDQS7#

& lt; 15 & gt;
& lt; 15 & gt;
& lt; 15 & gt;
& lt; 15 & gt;
& lt; 15 & gt;
& lt; 15 & gt;
& lt; 15 & gt;
& lt; 15 & gt;

C

& lt; 15 & gt;
& lt; 15 & gt;
& lt; 15 & gt;
& lt; 15 & gt;
& lt; 15 & gt;
& lt; 15 & gt;
& lt; 15 & gt;
& lt; 15 & gt;

B

DDRB_SCAS# & lt; 15 & gt;
DDRB_SRAS# & lt; 15 & gt;
DDRB_SWE# & lt; 15 & gt;

CRESTLINE ES_FCBGA1299
PMR3@

A

A

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2006/08/05

Issued Date

Deciphered Date

2007/08/05

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

Crestline (3/7)
Document Number

Rev
2.0

LA-3481P
Tuesday, May 22, 2007

Sheet
1

9

of

47

5

4

3

2

1

PCIE_MTX_C_GRX_N[0..15]
PCIE_MTX_C_GRX_P[0..15]

U3C

PCIE_GTX_C_MRX_N[0..15]

LVDS_IBG
LVDS_VBG
LVDS_VREFH
LVDS_VREFL
LVDSA_CLK#
LVDSA_CLK
LVDSB_CLK#
LVDSB_CLK

GMCH_TXOUT0GMCH_TXOUT1GMCH_TXOUT2-

G51
E51
F49

LVDSA_DATA#_0
LVDSA_DATA#_1
LVDSA_DATA#_2

GMCH_TXOUT0+
GMCH_TXOUT1+
GMCH_TXOUT2+

G50
E50
F48

LVDSA_DATA_0
LVDSA_DATA_1
LVDSA_DATA_2

GMCH_TZOUT0GMCH_TZOUT1GMCH_TZOUT2-

G44
B47
B45

LVDSB_DATA#_0
LVDSB_DATA#_1
LVDSB_DATA#_2

GMCH_TZOUT0+
GMCH_TZOUT1+
GMCH_TZOUT2+

GMCH_TXCLKGMCH_TXCLK+
GMCH_TZCLKGMCH_TZCLK+

& lt; 19 & gt; GMCH_TXOUT0 & lt; 19 & gt; GMCH_TXOUT1 & lt; 19 & gt; GMCH_TXOUT2 & lt; 19 & gt; GMCH_TXOUT0+
& lt; 19 & gt; GMCH_TXOUT1+
& lt; 19 & gt; GMCH_TXOUT2+
& lt; 19 & gt; GMCH_TZOUT0 & lt; 19 & gt; GMCH_TZOUT1 & lt; 19 & gt; GMCH_TZOUT2 & lt; 19 & gt; GMCH_TZOUT0+
& lt; 19 & gt; GMCH_TZOUT1+
& lt; 19 & gt; GMCH_TZOUT2+

C

E44
A47
A45

LVDSB_DATA_0
LVDSB_DATA_1
LVDSB_DATA_2

1

2 2.4K_0402_5%

R87
R87

1

2 75_0402_1% GMCH_TV_COMPS

1

2 150_0402_1% GMCH_TV_LUMA

R88
R88
R89
R89

LVDS_IBG

GMCH_TV_COMPS
GMCH_TV_LUMA
GMCH_TV_CRMA

2 150_0402_1% GMCH_TV_CRMA

1

TV_DCONSEL_0
TV_DCONSEL_1

R90
R90
2
R91
R91
2

150_0402_1%
GMCH_CRT_B
1
150_0402_1%
GMCH_CRT_G
1

& lt; 17 & gt; GMCH_CRT_B
& lt; 17 & gt; GMCH_CRT_G

1

M35
P33

GMCH_CRT_R

CRT_BLUE
CRT_BLUE#
CRT_GREEN
CRT_GREEN#
CRT_RED
CRT_RED#

B

& lt; 17 & gt;
& lt; 17 & gt;
& lt; 17 & gt;
& lt; 17 & gt;

GMCH_CRT_CLK
GMCH_CRT_DATA
GMCH_CRT_HSYNC
GMCH_CRT_VSYNC

GMCH_CRT_CLK
GMCH_CRT_DATA

1

R93

2 CRT_IREF
1.3K_0402_1%

C32

CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_VSYNC
CRT_TVO_IREF

J50
L50
M47
U44
T49
T41
W45
W41
AB50
Y48
AC45
AC41
AH47
AG49
AH45
AG42

PCIE_GTX_C_MRX_P0
PCIE_GTX_C_MRX_P1
PCIE_GTX_C_MRX_P2
PCIE_GTX_C_MRX_P3
PCIE_GTX_C_MRX_P4
PCIE_GTX_C_MRX_P5
PCIE_GTX_C_MRX_P6
PCIE_GTX_C_MRX_P7
PCIE_GTX_C_MRX_P8
PCIE_GTX_C_MRX_P9
PCIE_GTX_C_MRX_P10
PCIE_GTX_C_MRX_P11
PCIE_GTX_C_MRX_P12
PCIE_GTX_C_MRX_P13
PCIE_GTX_C_MRX_P14
PCIE_GTX_C_MRX_P15

PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9
PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15

N45
U39
U47
N51
R50
T42
Y43
W46
W38
AD39
AC46
AC49
AC42
AH39
AE49
AH44

PCIE_MTX_GRX_N0
PCIE_MTX_GRX_N1
PCIE_MTX_GRX_N2
PCIE_MTX_GRX_N3
PCIE_MTX_GRX_N4
PCIE_MTX_GRX_N5
PCIE_MTX_GRX_N6
PCIE_MTX_GRX_N7
PCIE_MTX_GRX_N8
PCIE_MTX_GRX_N9
PCIE_MTX_GRX_N10
PCIE_MTX_GRX_N11
PCIE_MTX_GRX_N12
PCIE_MTX_GRX_N13
PCIE_MTX_GRX_N14
PCIE_MTX_GRX_N15

M45
T38
T46
N50
R51
U43
W42
Y47
Y39
AC38
AD47
AC50
AD43
AG39
AE50
AH43

2

PCIE_GTX_C_MRX_P[0..15]

PCIE_GTX_C_MRX_N[0..15] & lt; 19 & gt;

PCIE_GTX_C_MRX_N0
PCIE_GTX_C_MRX_N1
PCIE_GTX_C_MRX_N2
PCIE_GTX_C_MRX_N3
PCIE_GTX_C_MRX_N4
PCIE_GTX_C_MRX_N5
PCIE_GTX_C_MRX_N6
PCIE_GTX_C_MRX_N7
PCIE_GTX_C_MRX_N8
PCIE_GTX_C_MRX_N9
PCIE_GTX_C_MRX_N10
PCIE_GTX_C_MRX_N11
PCIE_GTX_C_MRX_N12
PCIE_GTX_C_MRX_N13
PCIE_GTX_C_MRX_N14
PCIE_GTX_C_MRX_N15

PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8
PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15

1

PCIE_MTX_C_GRX_P[0..15] & lt; 19 & gt;

10mils

PCIE_MTX_GRX_P0
PCIE_MTX_GRX_P1
PCIE_MTX_GRX_P2
PCIE_MTX_GRX_P3
PCIE_MTX_GRX_P4
PCIE_MTX_GRX_P5
PCIE_MTX_GRX_P6
PCIE_MTX_GRX_P7
PCIE_MTX_GRX_P8
PCIE_MTX_GRX_P9
PCIE_MTX_GRX_P10
PCIE_MTX_GRX_P11
PCIE_MTX_GRX_P12
PCIE_MTX_GRX_P13
PCIE_MTX_GRX_P14
PCIE_MTX_GRX_P15

R75
R75

C85

24.9_0402_1%

+1.05VS

PCIE_GTX_C_MRX_P[0..15] & lt; 19 & gt;

D

C

Close to U41
1

C87

1

C89

1

C91

1

C93

1

C95

1

C97

1

C99

1

C84
2 PM@ 0.1U_0402_16V7K
C86
2 PM@ 0.1U_0402_16V7K
C88
2 PM@ 0.1U_0402_16V7K
C90
2 PM@ 0.1U_0402_16V7K
C92
2 PM@ 0.1U_0402_16V7K
C94
2 PM@ 0.1U_0402_16V7K
C96
2 PM@ 0.1U_0402_16V7K
C98
2 PM@ 0.1U_0402_16V7K

1
1
1
1
1
1
1
1

Close to U41

C101 1
C103 1
C105 1
C107 1
C109 1
C111 1
C113 1
C115 1

C100
2 PM@ 0.1U_0402_16V7K
C102
PM@ 0.1U_0402_16V7K
2
C104
2 PM@ 0.1U_0402_16V7K
C106
PM@ 0.1U_0402_16V7K
2
C108
2 PM@ 0.1U_0402_16V7K
C110
2 PM@ 0.1U_0402_16V7K
C112
2 PM@ 0.1U_0402_16V7K
C114
2 PM@ 0.1U_0402_16V7K

1
1
1
1
1
1
1
1

2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N0
PCIE_MTX_C_GRX_N1
2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_N3
PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N4
2
PCIE_MTX_C_GRX_N5
2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_N7
PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N8
2
PCIE_MTX_C_GRX_N9
2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N10
PCIE_MTX_C_GRX_N11
PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N12
2
PCIE_MTX_C_GRX_N13
2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_N15
2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_P1
2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_P3
2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_P5
2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_P7
2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_P9
2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_P11
2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_P13
PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P14
2
PCIE_MTX_C_GRX_P15

B

CRESTLINE ES_FCBGA1299
PMR3@

+3VS

R667 1

2 2.2K_0402_5%

GMCH_LCD_CLK

R669 1

2 2.2K_0402_5%

GMCH_LCD_DATA

R671 1

2 10K_0402_5%

LCTLB_DATA

R673 1

2 10K_0402_5%

LCTLA_CLK

R675 1

2 2.2K_0402_5%

GMCH_CRT_CLK

R677 1

2 2.2K_0402_5%

GMCH_CRT_DATA

R679
A

K33
G35
F33
E33

J51
L51
N47
T45
T50
U40
Y44
Y40
AB51
W49
AD44
AD40
AG46
AH49
AG45
AG41

PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8
PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15

TV_DCONSEL_0
TV_DCONSEL_1

H32
G32
K29
J29
F29
E29

GMCH_CRT_G

150_0402_1%

& lt; 17 & gt; GMCH_CRT_R

TVA_RTN
TVB_RTN
TVC_RTN

VGA

GMCH_CRT_R

2
R92
R92

GMCH_CRT_B

TVA_DAC
TVB_DAC
TVC_DAC

F27
J27
L27

& lt; 17 & gt; GMCH_TV_LUMA
& lt; 17 & gt; GMCH_TV_CRMA

E27
G27
K27

TV

R86
R86

GRAPHICS

& lt; 19 & gt;
& lt; 19 & gt;
& lt; 19 & gt;
& lt; 19 & gt;

N43
M43

PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8
PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15

PCI-EXPRESS

D46
C45
D44
E42

LVDS_IBG

PEG_COMP

PEG_COMPI
PEG_COMPO

LVDS

L41
L43
N41
N40

LCTLA_CLK
LCTLB_DATA
GMCH_LCD_CLK
GMCH_LCD_DATA

& lt; 19 & gt; GMCH_LCD_CLK
& lt; 19 & gt; GMCH_LCD_DATA
& lt; 19 & gt; GMCH_ENVDD

D

L_BKLT_CTRL
L_BKLT_EN
L_CTRL_CLK
L_CTRL_DATA
L_DDC_CLK
L_DDC_DATA
L_VDD_EN

GMCH_TXCLKGMCH_TXCLK+
GMCH_TZCLKGMCH_TZCLK+

& lt; 29 & gt; GMCH_ENBKL

J40
H39
E39
E40
C37
D35
K40

PCIE_MTX_C_GRX_N[0..15] & lt; 19 & gt;

2.2K_0402_5%

TV_DCONSEL_0

R681

2.2K_0402_5%

TV_DCONSEL_1

A

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2006/08/05

Issued Date

Deciphered Date

2007/08/05

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

Crestline(4/7)
Document Number

Rev
2.0

LA-3481P
Tuesday, May 22, 2007

Sheet
1

10

of

47

5

4

3

2

1

U3G

R20
T14
W13
W14
Y12
AA20
AA23
AA26
AA28
AB21
AB24
AB29
AC20
AC21
AC23
AC24
AC26
AC28
AC29
AD20
AD23
AD24
AD28
AF21
AF26
AA31
AH20
AH21
AH23
AH24
AH26
AD31
AJ20
AN14

+1.05VS

B

A

VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34

VCC GFX NCTF
VCC SM LF

C

VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35
VCC_SM_36

VCC GFX

AU32
AU33
AU35
AV33
AW33
AW35
AY35
BA32
BA33
BA35
BB33
BC32
BC33
BC35
BD32
BD35
BE32
BE33
BE35
BF33
BF34
BG32
BG33
BG35
BH32
BH34
BH35
BJ32
BJ33
BJ34
BK32
BK33
BK34
BK35
BL33
AU30

+1.8V

VCC SM

POWER

T17
T18
T19
T21
T22
T23
T25
U15
U16
U17
U19
U20
U21
U23
U26
V16
V17
V19
V20
V21
V23
V24
Y15
Y16
Y17
Y19
Y20
Y21
Y23
Y24
Y26
Y28
Y29
AA16
AA17
AB16
AB19
AC16
AC17
AC19
AD15
AD16
AD17
AF16
AF19
AH15
AH16
AH17
AH19
AJ16
AJ17
AJ19
AK16
AK19
AL16
AL17
AL19
AL20
AL21
AL23
AM15
AM16
AM19
AM20
AM21
AM23
AP15
AP16
AP17
AP19
AP20
AP21
AP23
AP24
AR20
AR21
AR23
AR24
AR26
V26
V28
V29
Y31

VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7

AW45
BC39
BE39
BD17
BD4
AW8
AT6

U3F
+1.05VS
+1.05VS

VCC: 1300mA
(220UF*1, 22UF*1, 0.22UF*1, 0.1UF*1)

+1.05VS

1
C116

1

+

C117
C117

C118

1

C119

C120
C120

@220U_D2_2VMR15
0.22U_0603_16V7K
0.1U_0402_16V4Z
2
2
2
22U_0805_6.3V6M
0.22U_0603_16V7K

VCC_SM: 2400mA
(330UF*1, 22UF*2, 0.1UF*1)

+1.8V

C121

1
1

+

1

C122
C122

1

C123
C123

C124
C124

330U_D2E_2.5VM_R9
22U_0805_6.3V6M
2
2
2
2
22U_0805_6.3V6M
0.1U_0402_16V4Z

VCC_AXG: 7700mA
(330UF*2, 22UF*1, 10UF*1, 1U*1, 0.47U*1, 0.1UF*2)

+1.05VS

C125

1

C126

+

1
+

330U_D2E_2.5VM_R9
2

2

C127
C127 1

22U_0805_6.3V6M
2

10U_0805_10V4Z

VCC_13

VCC_AXG_NCTF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8
VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52
VCC_AXG_NCTF_53
VCC_AXG_NCTF_54
VCC_AXG_NCTF_55
VCC_AXG_NCTF_56
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60
VCC_AXG_NCTF_61
VCC_AXG_NCTF_62
VCC_AXG_NCTF_63
VCC_AXG_NCTF_64
VCC_AXG_NCTF_65
VCC_AXG_NCTF_66
VCC_AXG_NCTF_67
VCC_AXG_NCTF_68
VCC_AXG_NCTF_69
VCC_AXG_NCTF_70
VCC_AXG_NCTF_71
VCC_AXG_NCTF_72
VCC_AXG_NCTF_73
VCC_AXG_NCTF_74
VCC_AXG_NCTF_75
VCC_AXG_NCTF_76
VCC_AXG_NCTF_77
VCC_AXG_NCTF_78
VCC_AXG_NCTF_79
VCC_AXG_NCTF_80
VCC_AXG_NCTF_81
VCC_AXG_NCTF_82
VCC_AXG_NCTF_83

C128
C128

R30

D

VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12

VCC CORE

AT35
AT34
AH28
AC32
AC31
AK32
AJ31
AJ28
AH32
AH31
AH29
AF32

+1.05VS

1

+1.05VM_AXM

1

+1.05VS

C130
C130

C131
C131 1

1U_0603_10V4Z

2

330U_D2E_2.5VM_R9

L71
L71

C129

C132
C132 1

0.1U_0402_16V4Z
2
2
0.1U_0402_16V4Z

0.47U_0603_16V4Z

VCC_AXM: 540mA
(22UF*2, 0.22UF*2, 0.1UF*2)

+1.05VM_AXM

2
1
MBK1608121YZF_0603
C133
C133

C134

C135

C136
C136

1

C137
C137

1

C138
C138

1

22U_0805_6.3V6M
0.22U_0603_16V7K
0.1U_0402_16V4Z
2
2
2
2
0.22U_0603_16V7K
0.1U_0402_16V4Z
0.1U_0402_16V4Z

AB33
AB36
AB37
AC33
AC35
AC36
AD35
AD36
AF33
AF36
AH33
AH35
AH36
AH37
AJ33
AJ35
AK33
AK35
AK36
AK37
AD33
AJ36
AM35
AL33
AL35
AA33
AA35
AA36
AP35
AP36
AR35
AR36
Y32
Y33
Y35
Y36
Y37
T30
T34
T35
U29
U31
U32
U33
U35
U36
V32
V33
V36
V37

AL24
AL26
AL28
AM26
AM28
AM29
AM31
AM32
AM33
AP29
AP31
AP32
AP33
AL29
AL31
AL32
AR31
AR32
AR33

VCC_NCTF_1
VCC_NCTF_2
VCC_NCTF_3
VCC_NCTF_4
VCC_NCTF_5
VCC_NCTF_6
VCC_NCTF_7
VCC_NCTF_8
VCC_NCTF_9
VCC_NCTF_10
VCC_NCTF_11
VCC_NCTF_12
VCC_NCTF_13
VCC_NCTF_14
VCC_NCTF_15
VCC_NCTF_16
VCC_NCTF_17
VCC_NCTF_18
VCC_NCTF_19
VCC_NCTF_20
VCC_NCTF_21
VCC_NCTF_22
VCC_NCTF_23
VCC_NCTF_24
VCC_NCTF_25
VCC_NCTF_26
VCC_NCTF_27
VCC_NCTF_28
VCC_NCTF_29
VCC_NCTF_30
VCC_NCTF_31
VCC_NCTF_32
VCC_NCTF_33
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
VCC_NCTF_37
VCC_NCTF_38
VCC_NCTF_39
VCC_NCTF_40
VCC_NCTF_41
VCC_NCTF_42
VCC_NCTF_43
VCC_NCTF_44
VCC_NCTF_45
VCC_NCTF_46
VCC_NCTF_47
VCC_NCTF_48
VCC_NCTF_49
VCC_NCTF_50

T27
T37
U24
U28
V31
V35
AA19
AB17
AB35
AD19
AD37
AF17
AF35
AK17
AM17
AM24
AP26
AP28
AR15
AR19
AR28

VSS_SCB1
VSS_SCB2
VSS_SCB3
VSS_SCB4
VSS_SCB5
VSS_SCB6

A3
B2
C1
BL1
BL51
A51

D

C

POWER

VCC_AXM_1
VCC_AXM_2
VCC_AXM_3
VCC_AXM_4
VCC_AXM_6
VCC_AXM_5
VCC_AXM_7

VCC_AXM_NCTF_1
VCC_AXM_NCTF_2
VCC_AXM_NCTF_3
VCC_AXM_NCTF_4
VCC_AXM_NCTF_5
VCC_AXM_NCTF_6
VCC_AXM_NCTF_7
VCC_AXM_NCTF_8
VCC_AXM_NCTF_9
VCC_AXM_NCTF_10
VCC_AXM_NCTF_11
VCC_AXM_NCTF_12
VCC_AXM_NCTF_13
VCC_AXM_NCTF_14
VCC_AXM_NCTF_15
VCC_AXM_NCTF_16
VCC_AXM_NCTF_17
VCC_AXM_NCTF_18
VCC_AXM_NCTF_19

AT33
AT31
AK29
AK24
AK23
AJ26
AJ23

+1.05VM_AXM

B

CRESTLINE ES_FCBGA1299
PMR3@

VCCSM_LF1
VCCSM_LF2
VCCSM_LF3
VCCSM_LF4
VCCSM_LF5
VCCSM_LF6
VCCSM_LF7
1
C139
C139

C140
C140

1

C141

C142

C143

C144

C145
C145
A

0.1U_0402_16V4Z
0.22U_0603_16V7K
0.47U_0603_16V4Z
1U_0603_10V4Z
2
2
0.1U_0402_16V4Z
0.22U_0603_16V7K
1U_0603_10V4Z

CRESTLINE ES_FCBGA1299
PMR3@

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2006/08/05

Issued Date

Deciphered Date

2007/08/05

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21

4

3

2

Crestline (5/7)
Document Number

Rev
2.0

LA-3481P
Tuesday, May 22, 2007

Sheet
1

11

of

47

5

4

1

VCCA_DPLLB

+1.25VM_HPLL

L59 1
2
MBK1608121YZF_0603
GM@
1

AL2

VCCA_HPLL

AM2
+1.25VM_MPLL
1
2
GM@ R688
1
C162
C162
R689 PM@
A41
0_0402_5%
1000P_0402_50V7K
0_0402_5%B41
2

VCCA_MPLL

R686 PM@

GM@ C744
0.1U_0402_16V4Z

2

2

R687 PM@

0.022U_0402_16V7K
0_0402_5%

VCCA_LVDS: 10mA
(0.1UF*1)

VCCA_LVDS
VSSA_LVDS

U51
+1.25VS_A_PEGPLL

VCCA_SM
(22UF*2, 4.7UF*1, 1UF*1)

+1.25VM_A_SM

1

C748
C748

C745

22U_0805_6.3V6M
2

C746
C746

4.7U_0603_6.3V6K~D
1U_0402_6.3V4Z

VCCA_SM_CK
(22UF*1, 1UF*2, 0.1UF*1)
L75
L75

+1.25VM_A_SM_CK

1

2
1
C750
C750
MBK1608121YZF_0603
22U_0805_6.3V6M

2

C752

1

C749
C749

1U_0402_6.3V4Z

1U_0402_6.3V4Z

2

BC29
BB29

+1.25VM_A_SM_CK

C751
C751

VCCA_TV_DAC: 40mA
(0.1UF*1, 0.022UF*1 for each DAC)

0.1U_0402_16V4Z

C25
B25
C27
B27
B28
A28

+3VS_A_TVDAC

+3VS_A_TVDAC
GM@
L60
1
2
+3VS
MBK1608121YZF_0603
GM@
C758
10U_0805_10V4Z

1
1
1
1
GM@ C756 GM@ C754 GM@
C757 GM@ C759 GM@ C753
PM@ R692
0.1U_0402_16V4Z
0.1U_0402_16V4Z 0_0402_5%
2
2
2
0.022U_0402_16V7K
0.1U_0402_16V4Z
0.022U_0402_16V7K

(0.1UF*1, 0.022UF*1)

GM@ 2

GM@
C948
C948

VCCD_CRT
VCCD_TVDAC

2

VCCA_HPLL:
1
C
C197
250mA(0.1UF*1) 197

+1.25VS_A_PEGPLL

1
+VCCD_LVDS
GM@ R695
0_0402_5%

VCC_AXD: 200mA
(22UF*1, 1UF*1)

VCCD_LVDS_1
VCCD_LVDS_2

2
PM@ R696

+1.25VS_AXF

+1.25VM_AXD

1

+1.25VS_AXF

VCC_AXF: 350mA
(10UF*1, 1UF*1)

2

+1.25VS

B23
B21
A21

1

C171
C171

2

A

+VCCD_LVDS

+1.25VS

MBK1608121YZF_0603

C169

C

1U_0402_6.3V4Z

+1.8V_SM_CK

AJ50

C181
C181

VCC_DMI: 100mA (0.1UF*1)
BK24
BK23
BJ24
BJ23

1

1

1
2
+1.8V
L9
L9
MBK1608121YZF_0603
C182
C182
1
2

C180
C180

R102
22U_0805_6.3V6M
2
2
1_0402_5%
0.1U_0402_16V4Z

+1.8V_SM_CK

10U_0805_10V4Z

VCC_SM_CK: 200mA (22UF*1, 0.1UF*1)
A43

+1.8V_TX_LVDS
C186

C40
B40

VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4
VCC_PEG_5

GM@

+3VS_HV

1

2

AD51
W50
W51
V49
V50

C206
C206
0.1U_0402_16V4Z
+1.25VS_PEG_DMI

CRESTLINE ES_FCBGA1299
PMR3@

VTTLF1
VTTLF2
VTTLF3

2

1
2
+1.8V
L61
L61
MBK1608121YZF_0603

1
C898

+

220U_D2_2VMR15
2
GM@

+1.25VS_PEG: 1200mA (220UF*1, 10UF*1)
1
C193

+

L12 1
2
KC FBM-L11-201209-221LMAT_0805

+1.25VS_DMI: 100mA (220UF*1, 10UF*1) 220U_D2_2VMR15
2
VCC_RXR_DMI_1
VCC_RXR_DMI_2

1

AH50
AH51

1

2

B

+1.05VS

+1.25VS_PEG_DMI

VTTLF_CAP1
A7
VTTLF_CAP2
F2
AH1 VTTLF_CAP3

+1.05VS
C203
C203

C204

C205
C205

0.47U_0402_10V4Z~D 0.47U_0402_10V4Z~D

+3VS_HV

+3VS

D50
D50
RB751V_SOD323

0.47U_0402_10V4Z~D
R721
R721

0_0402_5%

2

1

VCCD_LVDS: 150mA
(10UF*1, 0.1UF*1)

+1.25VS

L73
L73

1

0.1U_0402_16V4Z
2

VCC_HV: 100mA

VCCD_PEG_PLL

C198
1 C198
0.1U_0402_16V4Z
J41
H42
2

VCCA_PEG_PLL:
0.1U_0402_16V4Z
2 100mA (0.1UF*1)

C167

22U_0805_6.3V6M
2
1U_0402_6.3V4Z

VCCD_HPLL

U48

2
MBK1608121YZF_0603

+1.8V_TX_LVDS

VCC_HV_1
VCC_HV_2

VCCD_QDAC

2

1

330U_D2E_2.5VM_R9

2

+1.5VS_C
C946
C946

GM@

1

C954 +
@

0.022U_0402_16V7K

2

C947

10U_0805_10V4Z

1
C945 +
@

0.1U_0402_16V4Z

+1.5VS

330U_D2E_2.5VM_R9

1

VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4

1

C166
C166

+1.8V_TX_LVDS: 100mA (220UF*1, 1000PF*1)

VCCA_TVA_DAC_1
VCCA_TVA_DAC_2
VCCA_TVB_DAC_1
VCCA_TVB_DAC_2
VCCA_TVC_DAC_1
VCCA_TVC_DAC_2

N28

VCCD_QDAC: 5mA
(0.1UF*1, 0.022UF*1)

+1.25VS

VCC_DMI

VCCA_SM_CK_1
VCCA_SM_CK_2

AN2

+1.5VS_QDAC

1

2

GM@ R216 0_0402_5% +1.5VS_C
R216
M32
L29
VCCD_TVDAC: 60mA

+1.5VS

VCC_AXF_1
VCC_AXF_2
VCC_AXF_3

L72
L72

1

AR29

VCC_TX_LVDS

PM@ R693 0_0402_5%

2

B

VCCA_SM_1
VCCA_SM_2
VCCA_SM_3
VCCA_SM_4
VCCA_SM_5
VCCA_SM_7
VCCA_SM_8
VCCA_SM_9
VCCA_SM_10
VCCA_SM_11
VCCA_SM_NCTF_1
VCCA_SM_NCTF_2

0.47U_0402_10V4Z~D

R722
R722

1
0_0402_5%

2

1

+1.25VS

POWER

1

AW18
AV19
AU19
AU18
AU17
AT22
AT21
AT19
AT18
AT17
AR17
AR16

+1.25VM_A_SM

1
2
MBK1608121YZF_0603

VCCA_PEG_PLL

VCCA_PEG_PLL: 100mA
(0.1UF*1)

0_0402_5%

L74
L74
+1.25VS

0.1U_0402_16V4Z
@ R691

0_0402_5%

VCCA_PEG_BG:
(0.1UF*1)

VCCA_PEG_BG
VSSA_PEG_BG

PEG

@ R690

0.1U_0402_16V4Z

C165
C165
2

1

K50
K49
5mA

TV/CRT
DMI

2

2

C173
C173

1

C174
C174

1

1

10U_0805_10V4Z

R100
R100
1_0402_5%

C

+3VS

D

C155

+1.25VM_AXD

AT23
AU28
AU24
AT29
AT25
AT30

LVDS

+1.25VS_DPLLB

2

+1.25VS

+1.25VS_DPLLA

2

+1.25VS_A_PEGPLL

L10
L10
1
2
MBK1608121YZF_0603

VCC_AXD_1
VCC_AXD_2
VCC_AXD_3
VCC_AXD_4
VCC_AXD_5
VCC_AXD_6

VCC_AXD_NCTF

1

1

0.1U_0402_16V4Z
0.022U_0402_16V7K 0_0402_5%
GM@ 2
GM@

GM@
C743

2

C741

+1.8V_TX_LVDS

1

2

+3VS

C154

2

H49

C153

C168
C168

+1.25VS_DPLLB

C152

10U_0805_10V4Z

VCCA_DPLLA

+

220U_D2_2VMR15
4.7U_0603_6.3V6K~D
2
4.7U_0603_6.3V6K~D
2.2U_0603_6.3V6K

1000P_0402_50V7K

+1.25VS_DPLLA

GM@ L58
4.7_0603_5%
1
C742

VSSA_DAC_BG

B49

+3VS_CRTDAC

+3VS

VCCA_DAC_BG

B32

VCCA_DAC_BG: 5mA
(0.1UF*1, 0.022UF*1)

1
C151

10U_0805_10V4Z

+3VS_DACBG

2

A30

+3VS_DACBG

2
0.1U_0402_16V4Z

U13
U12
U11
U9
U8
U7
U5
U3
U2
U1
T13
T11
T10
T9
T7
T6
T5
T3
T2
R3
R2
R1

C194
C194

C172
C172

1

VCCA_CRT_DAC: 80mA
(0.1UF*1, 0.022UF*1)

1

VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8
VTT_9
VTT_10
VTT_11
VTT_12
VTT_13
VTT_14
VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22

AXD

VCCA_MPLL: 150mA
(10UF*1, 0.1UF*1)

VCCA_CRT_DAC_1
VCCA_CRT_DAC_2

VTTLF

1

A33
B33

CRT

C164
C164

22U_0805_6.3V6M 0.1U_0402_16V4Z
2
2

VCCSYNC

VTT

C170
C170
R99
R99
0.5_0603_1%

VTT: 850mA
(220UF*1, 4.7UF*21, 2.2UF*1, 0.47UF*1)

+1.05VS

J32

+3VS_CRTDAC

10U_0805_10V4Z

(22UF*1, 0.1UF*1)

U3H

VCC_SYNC: 10mA (0.1UF*1)

L7
L7 1
2
MBK1608121YZF_0603

+1.25VS

0.1U_0402_16V4Z

2

LVDS

+1.25VS

C146

0.1U_0402_16V4Z
2

+1.25VM_MPLL

L5
L5 1
2
MBK1608121YZF_0603
1
C163
C163
VCCA_HPLL: 50mA

1

+3VS

C157

PLL

2

1

AXF

VCCA_DPLLB: 80mA
(470UF*1, 0.1UF*1)

SM

1
2
MBK1608121YZF_0603 1

L3

C148

0.1U_0402_16V4Z
2

+1.25VM_HPLL

D

2

CLK

2

+1.25VS

1

10U_0805_10V4Z

VCCA_DPLLA: 80mA
(470UF*1, 0.1UF*1)

1

C156
C156

C147
C147

1
2
MBK1608121YZF_0603

L1

10U_0805_10V4Z

+1.25VS

3

+1.25VS_DPLLB

TV
PEG

+1.25VS_DPLLA

1
10_0402_5%
A

+1.5VS_QDAC

C760
C760

1

2

1

2 0.1U_0402_16V4Z

2

+1.5VS
C761
C761

100_0603_5%
C201

1

GM@ C202

GM@
2
0.1U_0402_16V4Z

PM@ R694

0.022U_0402_16V7K

0_0402_5%

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2006/08/05

Issued Date

Deciphered Date

2007/08/05

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

Crestline (6/7)

1

+1.8V

10U_0805_10V4Z

GM@ L15
L15

3

2

Document Number

Rev
2.0

LA-3481P
Saturday, June 23, 2007

Sheet
1

12

of

47

5

4

3

U3I

A13
A15
A17
A24
AA21
AA24
AA29
AB20
AB23
AB26
AB28
AB31
AC10
AC13
AC3
AC39
AC43
AC47
AD1
AD21
AD26
AD29
AD3
AD41
AD45
AD49
AD5
AD50
AD8
AE10
AE14
AE6
AF20
AF23
AF24
AF31
AG2
AG38
AG43
AG47
AG50
AH3
AH40
AH41
AH7
AH9
AJ11
AJ13
AJ21
AJ24
AJ29
AJ32
AJ43
AJ45
AJ49
AK20
AK21
AK26
AK28
AK31
AK51
AL1
AM11
AM13
AM3
AM4
AM41
AM45
AN1
AN38
AN39
AN43
AN5
AN7
AP4
AP48
AP50
AR11
AR2
AR39
AR44
AR47
AR7
AT10
AT14
AT41
AT49
AU1
AU23
AU29
AU3
AU36
AU49
AU51
AV39
AV48
AW1
AW12
AW16

D

C

B

A

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99

2

1

U3J

VSS

VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198

AW24
AW29
AW32
AW5
AW7
AY10
AY24
AY37
AY42
AY43
AY45
AY47
AY50
B10
B20
B24
B29
B30
B35
B38
B43
B46
B5
B8
BA1
BA17
BA18
BA2
BA24
BB12
BB25
BB40
BB44
BB49
BB8
BC16
BC24
BC25
BC36
BC40
BC51
BD13
BD2
BD28
BD45
BD48
BD5
BE1
BE19
BE23
BE30
BE42
BE51
BE8
BF12
BF16
BF36
BG19
BG2
BG24
BG29
BG39
BG48
BG5
BG51
BH17
BH30
BH44
BH46
BH8
BJ11
BJ13
BJ38
BJ4
BJ42
BJ46
BK15
BK17
BK25
BK29
BK36
BK40
BK44
BK6
BK8
BL11
BL13
BL19
BL22
BL37
BL47
C12
C16
C19
C28
C29
C33
C36
C41

C46
C50
C7
D13
D24
D3
D32
D39
D45
D49
E10
E16
E24
E28
E32
E47
F19
F36
F4
F40
F50
G1
G13
G16
G19
G24
G28
G29
G33
G42
G45
G48
G8
H24
H28
H4
H45
J11
J16
J2
J24
J28
J33
J35
J39

VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243

K12
K47
K8
L1
L17
L20
L24
L28
L3
L33
L49
M28
M42
M46
M49
M5
M50
M9
N11
N14
N17
N29
N32
N36
N39
N44
N49
N7
P19
P2
P23
P3
P50
R49
T39
T43
T47
U41
U45
U50
V2
V3

VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305

W11
W39
W43
W47
W5
W7
Y13
Y2
Y41
Y45
Y49
Y5
Y50
Y11
P29
T29
T31
T33
R28

VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313

AA32
AB32
AD32
AF28
AF29
AT27
AV25
H50

VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273
VSS_274
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286

D

VSS
C

B

CRESTLINE ES_FCBGA1299
PMR3@

A

CRESTLINE ES_FCBGA1299
PMR3@

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2006/08/05

Issued Date

Deciphered Date

2007/08/05

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

Crestline (7/7)
Document Number

Rev
2.0

LA-3481P
Tuesday, May 22, 2007

Sheet
1

13

of

47

5

4

+1.8V

3

2

1

+1.8V
+1.8V

DDRA_SDQ2
DDRA_SDQ3
DDRA_SDQ8
DDRA_SDQ14

D

& lt; 9 & gt; DDRA_SDQS1#
& lt; 9 & gt; DDRA_SDQS1

DDRA_SDQS1#
DDRA_SDQS1
DDRA_SDQ9
DDRA_SDQ15

DDRA_SDQ16
DDRA_SDQ17
& lt; 9 & gt; DDRA_SDQS2#
& lt; 9 & gt; DDRA_SDQS2

DDRA_SDQS2#
DDRA_SDQS2
DDRA_SDQ18
DDRA_SDQ19
DDRA_SDQ29
DDRA_SDQ24
DDRA_SDM3
DDRA_SDQ26
DDRA_SDQ27

& lt; 8 & gt; DDRA_CKE0
C

& lt; 9 & gt; DDRA_SBS2#

DDRA_CKE0
DDRA_SBS2#
DDRA_SMA12
DDRA_SMA9
DDRA_SMA8
DDRA_SMA5
DDRA_SMA3
DDRA_SMA1

& lt; 9 & gt; DDRA_SBS0#
& lt; 9 & gt; DDRA_SWE#
& lt; 9 & gt; DDRA_SCAS#
& lt; 8 & gt; DDRA_SCS1#
& lt; 8 & gt; DDRA_ODT1

DDRA_SMA10
DDRA_SBS0#
DDRA_SWE#
DDRA_SCAS#
DDRA_SCS1#
DDRA_ODT1
DDRA_SDQ37
DDRA_SDQ36

& lt; 9 & gt; DDRA_SDQS4#
& lt; 9 & gt; DDRA_SDQS4

DDRA_SDQS4#
DDRA_SDQS4
DDRA_SDQ35
DDRA_SDQ32
DDRA_SDQ40
DDRA_SDQ44
DDRA_SDM5

B

DDRA_SDQ41
DDRA_SDQ46
DDRA_SDQ49
DDRA_SDQ48

& lt; 9 & gt; DDRA_SDQS6#
& lt; 9 & gt; DDRA_SDQS6

DDRA_SDQS6#
DDRA_SDQS6
DDRA_SDQ54
DDRA_SDQ50
DDRA_SDQ60
DDRA_SDQ61
DDRA_SDM7
DDRA_SDQ59
DDRA_SDQ58

& lt; 15,16 & gt; DDR_SMBDATA
& lt; 15,16 & gt; DDR_SMBCLK

DDR_SMBDATA
DDR_SMBCLK
+3VS

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD

VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
SA1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DDRA_SDQ6
DDRA_SDQ0

R105
R105

DDRA_SDM0

1K_0402_1%

20mils

DDRA_SDQ5
DDRA_SDQ7

+1.8V

2

DDRA_SDQS0#
DDRA_SDQS0

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS

+DIMM_VREF
1

1

& lt; 9 & gt; DDRA_SDQS0#
& lt; 9 & gt; DDRA_SDQS0

VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS

1

DDRA_SDQ13
DDRA_SDQ12

2

DDRA_SDM1

C209
C209

C210

R106
R106

0.1U_0402_16V4Z

C729 +

1K_0402_1%
2.2U_0603_6.3V6K

C727
C727

1

1

C730
C730

2
2
330U_D2E_2.5VM_R9
0.1U_0402_16V4Z

2

DDRA_SDQ4
DDRA_SDQ1

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

1

JP3
JP3
+DIMM_VREF

2

1

1

2

C728
C728

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C731
C731
D

0.1U_0402_16V4Z

DDRA_CLK0 & lt; 8 & gt;
DDRA_CLK0# & lt; 8 & gt;
DDRA_SDQ11
DDRA_SDQ10
DDRA_SMA[0..14]

& lt; 8,9 & gt; DDRA_SMA[0..14]
DDRA_SDQ20
DDRA_SDQ21
R107
R107 1
DDRA_SDM2

DDRA_SDQ[0..63]

& lt; 9 & gt; DDRA_SDQ[0..63]
0_0402_5%
2

DDRA_SDM[0..7]

& lt; 9 & gt; DDRA_SDM[0..7]
PM_EXTTS#0 & lt; 8 & gt;

+1.8V

DDRA_SDQ23
DDRA_SDQ22
DDRA_SDQ28
DDRA_SDQ25
DDRA_SDQS3#
DDRA_SDQS3

C211

C212

DDRA_SDQS3# & lt; 9 & gt;
DDRA_SDQS3 & lt; 9 & gt;

2.2U_0603_6.3V6K

C213

C214

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

C215
2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

DDRA_SDQ31
DDRA_SDQ30
DDRA_CKE1

+0.9VS

DDRA_CKE1 & lt; 8 & gt;
DDRA_SBS2#
1
DDRA_CKE0
2
RP1
RP1
DDRA_SMA9
1
DDRA_SMA12
2
RP2
RP2

4
3
56_0404_4P2R_5%

1
2

4
3
56_0404_4P2R_5%

+0.9VS

4
3
56_0404_4P2R_5%

1

DDRA_SCAS#
1
DDRA_SWE#
2
RP6
RP6

4
3
56_0404_4P2R_5%

2

DDRA_ODT1
1
DDRA_SCS1#
2
RP7
RP7

4
3
56_0404_4P2R_5%

DDRA_CKE1
1
DDRA_SMA11
2
RP8
RP8

DDRA_SMA4
DDRA_SMA2
DDRA_SMA0

1
2

DDRA_SBS0#
1
DDRA_SMA10
2
RP5
RP5

DDRA_SMA11
DDRA_SMA7
DDRA_SMA6

4
3
56_0404_4P2R_5%

DDRA_SMA5
DDRA_SMA8

DDRA_SMA14

4
3
56_0404_4P2R_5%

4
3
56_0404_4P2R_5%

RP3
RP3
DDRA_SBS1#
DDRA_SRAS#
DDRA_SCS0#
DDRA_ODT0
DDRA_SMA13

DDRA_SBS1# & lt; 9 & gt;
DDRA_SRAS# & lt; 9 & gt;
DDRA_SCS0# & lt; 8 & gt;

DDRA_SMA1
DDRA_SMA3
RP4
RP4

DDRA_ODT0 & lt; 8 & gt;

DDRA_SDQ39
DDRA_SDQ38

C

C220
C220
0.1U_0402_16V4Z

1

2

1

C221
C221
0.1U_0402_16V4Z

2

1

C222
C222
0.1U_0402_16V4Z

2

1

C223
C223
0.1U_0402_16V4Z

2

C224
C224
0.1U_0402_16V4Z

DDRA_SDM4
DDRA_SDQ34
DDRA_SDQ33

+0.9VS

DDRA_SDQ45
DDRA_SDQ43
DDRA_SDQS5#
DDRA_SDQS5

DDRA_SDQS5# & lt; 9 & gt;
DDRA_SDQS5 & lt; 9 & gt;

DDRA_SDQ47
DDRA_SDQ42

DDRA_SMA7
DDRA_SMA6

0.1U_0402_16V4Z

4
3
56_0404_4P2R_5%

1
2
RP10
RP10

4
3
56_0404_4P2R_5%
4
3
56_0404_4P2R_5%

1

DDRA_SRAS#
1
DDRA_SCS0#
2
RP12
RP12

4
3
56_0404_4P2R_5%

DDRA_ODT0
1
DDRA_SMA13
2
RP13
RP13

DDRA_SDM6
DDRA_SDQ51
DDRA_SDQ55
DDRA_SDQ57
DDRA_SDQ56
DDRA_SDQS7# & lt; 9 & gt;
DDRA_SDQS7 & lt; 9 & gt;

1

2

1

C226
C226
0.1U_0402_16V4Z

2

1

C227
C227
0.1U_0402_16V4Z

2

1

C228
C228
0.1U_0402_16V4Z

2

C229
C229
B

0.1U_0402_16V4Z

+0.9VS

DDRA_SMA0
1
DDRA_SBS1#
2
RP11
RP11

4
3
56_0404_4P2R_5%

DDRA_SMA4
DDRA_SMA2
DDRA_CLK1 & lt; 8 & gt;
DDRA_CLK1# & lt; 8 & gt;

2

C230
C230
0.1U_0402_16V4Z

1

2

1

C231
C231
0.1U_0402_16V4Z

2

C232
C232
0.1U_0402_16V4Z

R647

DDRA_SDQ62
DDRA_SDQ63
R108
R108
1
R109
R109
1

2

C225
C225

1
2

RP9
RP9
DDRA_SDQ52
DDRA_SDQ53

DDRA_SDQS7#
DDRA_SDQS7

1

DDRA_SMA14

2 10K_0402_5%
2 10K_0402_5%

1

2
56_0402_5%

P-TWO_A5692B-A0G16-P

DIMM0 STD H:9.2mm (BOT)

A

A

2006/08/05

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2007/08/05

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

DDRII-SODIMM0
Document Number

Rev
2.0

LA-3481P
Sheet

Tuesday, May 22, 2007
1

14

of

47

A

B

+1.8V

C

JP4
+DIMM_VREF
DDRB_SDQ0
DDRB_SDQ1
& lt; 9 & gt; DDRB_SDQS0#
& lt; 9 & gt; DDRB_SDQS0

DDRB_SDQS0#
DDRB_SDQS0
DDRB_SDQ2
DDRB_SDQ3
DDRB_SDQ8
DDRB_SDQ9

1

& lt; 9 & gt; DDRB_SDQS1#
& lt; 9 & gt; DDRB_SDQS1

DDRB_SDQS1#
DDRB_SDQS1
DDRB_SDQ10
DDRB_SDQ11

DDRB_SDQ17
DDRB_SDQ20
& lt; 9 & gt; DDRB_SDQS2#
& lt; 9 & gt; DDRB_SDQS2

DDRB_SDQS2#
DDRB_SDQS2
DDRB_SDQ18
DDRB_SDQ19
DDRB_SDQ28
DDRB_SDQ25
DDRB_SDM3
DDRB_SDQ30
DDRB_SDQ31

& lt; 8 & gt; DDRB_CKE0
2

& lt; 9 & gt; DDRB_SBS2#

DDRB_CKE0
DDRB_SBS2#
DDRB_SMA12
DDRB_SMA9
DDRB_SMA8
DDRB_SMA5
DDRB_SMA3
DDRB_SMA1

& lt; 9 & gt; DDRB_SBS0#
& lt; 9 & gt; DDRB_SWE#
& lt; 9 & gt; DDRB_SCAS#
& lt; 8 & gt; DDRB_SCS1#
& lt; 8 & gt; DDRB_ODT1

DDRB_SMA10
DDRB_SBS0#
DDRB_SWE#
DDRB_SCAS#
DDRB_SCS1#
DDRB_ODT1
DDRB_SDQ32
DDRB_SDQ33

& lt; 9 & gt; DDRB_SDQS4#
& lt; 9 & gt; DDRB_SDQS4

DDRB_SDQS4#
DDRB_SDQS4
DDRB_SDQ34
DDRB_SDQ35
DDRB_SDQ40
DDRB_SDQ41
DDRB_SDM5

3

DDRB_SDQ42
DDRB_SDQ43
DDRB_SDQ48
DDRB_SDQ49

& lt; 9 & gt; DDRB_SDQS6#
& lt; 9 & gt; DDRB_SDQS6

DDRB_SDQS6#
DDRB_SDQS6
DDRB_SDQ51
DDRB_SDQ50
DDRB_SDQ56
DDRB_SDQ61
DDRB_SDM7
DDRB_SDQ59
DDRB_SDQ58

& lt; 14,16 & gt; DDR_SMBDATA
& lt; 14,16 & gt; DDR_SMBCLK

DDR_SMBDATA
DDR_SMBCLK
+3VS

D

E

+1.8V

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS
VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
SA1

+DIMM_VREF

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

+1.8V

DDRB_SDQ5
DDRB_SDQ4
DDRB_SDM0
C235

C236
C236

DDRB_SDQ6
DDRB_SDQ7
2.2U_0603_6.3V6K

1

C237
C237

2 0.1U_0402_16V4Z

1

1

C238
C238

C239
C239

1

1

C240
C240

2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z

DDRB_SDQ12
DDRB_SDQ13
1

DDRB_SDM1
DDRB_CLK1 & lt; 8 & gt;
DDRB_CLK1# & lt; 8 & gt;

+1.8V

DDRB_SDQ14
DDRB_SDQ15

C241
DDRB_SDQ21
DDRB_SDQ16
R110
R110 1
DDRB_SDM2

& lt; 8,9 & gt; DDRB_SMA[0..14]
0_0402_5%
2

PM_EXTTS#1 & lt; 8 & gt;

& lt; 9 & gt; DDRB_SDQ[0..63]
& lt; 9 & gt; DDRB_SDM[0..7]

C242

C243

C244

C245

DDRB_SMA[0..14]
DDRB_SDQ[0..63]

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

DDRB_SDM[0..7]

DDRB_SDQ22
DDRB_SDQ23
DDRB_SDQ26
DDRB_SDQ24
DDRB_SDQS3#
DDRB_SDQS3

DDRB_SDQS3# & lt; 9 & gt;
DDRB_SDQS3 & lt; 9 & gt;

DDRB_SDQ29
DDRB_SDQ27
DDRB_CKE1

DDRB_CKE1 & lt; 8 & gt;

+0.9VS
2

DDRB_SMA14
DDRB_SBS2#
DDRB_CKE0

1
2
RP16
RP16

4
3
56_0404_4P2R_5%

DDRB_SMA1
DDRB_SMA3

1
2
RP17
RP17

4
3
56_0404_4P2R_5%

1
2
RP18
RP18

4
3
56_0404_4P2R_5%

DDRB_SCAS#
DDRB_SWE#

1
2
RP19
RP19

4
3
56_0404_4P2R_5%

DDRB_ODT1
DDRB_SCS1#

1
2
RP20
RP20

4
3
56_0404_4P2R_5%

DDRB_CKE1
DDRB_SMA11

1
2
RP21
RP21

4
3
56_0404_4P2R_5%

DDRB_SMA7
DDRB_SMA6

1
2
RP22
RP22

4
3
56_0404_4P2R_5%

DDRB_SMA4
DDRB_SMA2

1
2
RP23
RP23

4
3
56_0404_4P2R_5%

DDRB_SMA0
DDRB_SBS1#

1
2
RP24
RP24

4
3
56_0404_4P2R_5%

DDRB_SRAS#
DDRB_SCS0#

1
2
RP25
RP25

4
3
56_0404_4P2R_5%

DDRB_ODT0
DDRB_SMA13

DDRB_ODT0 & lt; 8 & gt;

4
3
56_0404_4P2R_5%

1
2
RP26
RP26

4
3
56_0404_4P2R_5%

DDRB_SMA14

DDRB_ODT0
DDRB_SMA13

DDRB_SBS1# & lt; 9 & gt;
DDRB_SRAS# & lt; 9 & gt;
DDRB_SCS0# & lt; 8 & gt;

1
2
RP15
RP15

DDRB_SBS0#
DDRB_SMA10

DDRB_SBS1#
DDRB_SRAS#
DDRB_SCS0#

4
3
56_0404_4P2R_5%

DDRB_SMA5
DDRB_SMA8

DDRB_SMA4
DDRB_SMA2
DDRB_SMA0

1
2
RP14
RP14

DDRB_SMA9
DDRB_SMA12

DDRB_SMA11
DDRB_SMA7
DDRB_SMA6

1

DDRB_SDQ36
DDRB_SDQ37
DDRB_SDM4
DDRB_SDQ39
DDRB_SDQ38
DDRB_SDQ44
DDRB_SDQ45
DDRB_SDQS5#
DDRB_SDQS5

DDRB_SDQS5# & lt; 9 & gt;
DDRB_SDQS5 & lt; 9 & gt;

DDRB_SDQ46
DDRB_SDQ47
DDRB_SDQ52
DDRB_SDQ53
DDRB_CLK0 & lt; 8 & gt;
DDRB_CLK0# & lt; 8 & gt;
DDRB_SDM6
DDRB_SDQ54
DDRB_SDQ55
DDRB_SDQ60
DDRB_SDQ57
DDRB_SDQS7#
DDRB_SDQS7

DDRB_SDQS7# & lt; 9 & gt;
DDRB_SDQS7 & lt; 9 & gt;

DDRB_SDQ62
DDRB_SDQ63
1
R111
R111
1
R112
R112

2
2 10K_0402_5%
10K_0402_5%

+0.9VS

1

C250
C250

C251
C251

1

C252
C252

1

C253
C253

1

C254
C254

1

0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
2
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

+0.9VS

1

C255
C255

C256
C256

1

C257
C257

1

C258
C258

1

C259
C259

1

3

0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
2
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z

+0.9VS

C260
C260

1

C261
C261

1

C262
C262

1

0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
2
0.1U_0402_16V4Z

R648
2

56_0402_5%

+3VS

PTI_A5652D-A0G16-P

DIMM1 STD H:5.2mm (BOT)

4

4

2006/08/05

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2007/08/05

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

DDRII-SODIMM1
Document Number

Rev
2.0

LA-3481P
Sheet

Tuesday, May 22, 2007
E

15

of

47

4

3

+3VS

CLKSEL0

CPU
MHz

SRC
MHz

PCI
MHz

0

1

0

0

1

1

200

100

33.3

166

100

33.3

R130

1

C269
C269
0.1U_0402_16V4Z
1
1

C271
C271
0.1U_0402_16V4Z
1
1

C273
C273
0.1U_0402_16V4Z
1
1

@ 0_0402_5%
1
2
1
2
@ 0_0402_5%

R144

1
CHB1608U301_0603

2
1

2

2

2
2
C270
C270
0.1U_0402_16V4Z

2
2
C272
C272
0.1U_0402_16V4Z

ICH_SMBDATA
ICH_SMBCLK
C274
C274
0.1U_0402_16V4Z

R739
R740

DDR_SMBDATA
DDR_SMBCLK

2

+3VS
+3VS
1

FSLA

CLKSEL1

10U_0805_10V4Z

FSLB

CLKSEL2

2

+3VM_CK505

C268
C268

FSLC

L76
L76

1

5

FSB Frequency Selet:
+1.25VM_CK505

R1696

R1734

R1737

R1694

R1705

R1716

R1719

R1734

R1737

C278
C278

2

2
C280
C280
0.1U_0402_16V4Z

2

1

2
C282
C282
0.1U_0402_16V4Z

2

2
1

& lt; 22,30,31 & gt; ICH_SMBDATA

3

D

DDR_SMBDATA

2N7002_SOT23
Q61

2

& lt; 22,30,31 & gt; ICH_SMBCLK

1

DDR_SMBCLK

3
2N7002_SOT23
Q62

No Stuff

R1689

R1694

R1696

R1705

R1716

R1726

R1719

+3VM_CK505

2
1

DDR_SMBCLK & lt; 14,15 & gt;
DDR_SMBDATA & lt; 14,15 & gt;

PCI_STOP#
CPU_STOP#

38
37

H_STP_PCI# & lt; 22 & gt;
H_STP_CPU# & lt; 22 & gt;

CPU0
CPU0#

54
53

CLK_CPU_BCLK & lt; 4 & gt;
CLK_CPU_BCLK# & lt; 4 & gt;

51
50

CLK_MCH_BCLK & lt; 7 & gt;
CLK_MCH_BCLK# & lt; 7 & gt;

47
46

CLK_MCH_3GPLL & lt; 8 & gt;
CLK_MCH_3GPLL# & lt; 8 & gt;

SRC10
SRC10#

34
35

CLK_PCIE_LAN & lt; 26 & gt;
CLK_PCIE_LAN# & lt; 26 & gt;

SRC11/CR#_H
SRC11#/CR#_G

33
32

CLK_PCIE_VGA & lt; 19 & gt;
CLK_PCIE_VGA# & lt; 19 & gt;

SRC9
SRC9#

30
31

CLK_PCIE_NAND & lt; 31 & gt;
CLK_PCIE_NAND# & lt; 31 & gt;

44
43

CLK_PCIE_HDDVD & lt; 31 & gt;
CLK_PCIE_HDDVD# & lt; 31 & gt;

SRC6
SRC6#

41
40

CLK_PCIE_MCARD & lt; 31 & gt;
CLK_PCIE_MCARD# & lt; 31 & gt;

SRC4
SRC4#

VDDSRC_IO
VDDCPU_IO

64
63

27
28

CLK_PCIE_CARD & lt; 30 & gt;
CLK_PCIE_CARD# & lt; 30 & gt;

VDD96_IO
VDDPLL3_IO
VDDSRC_IO

36
49

SCLK
SDATA

SRC7/CR#_F
SRC7#/CR#_E

MCH_CLKSEL0 & lt; 8 & gt;

48

SRC8/CPU2_ITP
SRC8#/CPU2_ITP#

2

VDDSRC
VDDCPU

12
20
26

+1.25VM_CK505

R117
1K_0402_1%

2

VDDPCI
VDD48
VDDPLL3
VDDREF

C

1

1
R118
R118
0_0402_5%

CPU_BSEL0

CLK_Rd
1

PCI_CLK0
1
10K_0402_5%
PCI_CLK1
1
10K_0402_5%

2
R743
2
R744

NC

CPU1_F
CPU1#_F

+3VS

@ R115
56_0402_5%
R116
2.2K_0402_5%
FSA 2
1

U4
2
9
16
61
39
55

+1.05VS

& lt; 5 & gt;

2

R1726

1

C283
C283
0.1U_0402_16V4Z
1

D

Stuff

1

C279
C279
0.1U_0402_16V4Z
1
1

S

R1689

1
2
CHB1608U301_0603

D

R145

2
G

R124

No Stuff

800MHz

R742
4.7K_0402_5%

S

R119

Stuff
667MHz

R115

10U_0805_10V4Z

No Stuff

*(Default)

C

R741
4.7K_0402_5%

L77
L77

C281
C281

R118

Stuff

10U_0805_10V4Z

CPU Driven

2
G

+1.25VS
D

CLK_Ra

R119

2

@ 1K_0402_1%

R120 2

& lt; 30 & gt; EXP_CLKREQ#

PCI0/CR#_A

R121 2

& lt; 22 & gt; SATA_CLKREQ#

+1.05VS

1 560_0402_5% PCI_CLK0 1
1 560_0402_5% PCI_CLK1 3

PCI1/CR#_B

& lt; 35 & gt; CLK_PCI_SIO
& lt; 29 & gt; CLK_PCI_EC

CLK_PCI_SIO
CLK_PCI_EC

R745
R746

& lt; 24 & gt; CLK_PCI_PCM
& lt; 20 & gt; CLK_PCI_ICH

CLK_PCI_PCM
CLK_PCI_ICH

1
1

R747
R748

PCI2_TME
2 33_0402_5%
PCI_CLK3
2 33_0402_5%

1
1

2 33_0402_5% 27_SEL
2 33_0402_5% ITP_EN

2
FSB

1

1
R130
R130
0_0402_5%

CPU_BSEL1

2

PCI4/27_Select

7

PCI_F5/ITP_EN

MCH_CLKSEL1 & lt; 8 & gt;
CLK_XTAL_IN

CLK_Rb

60

X1

CLK_XTAL_OUT

R129
R129
1K_0402_1%

2
1

& lt; 5 & gt;

PCI3

6

1

@ 1K_0402_1%

PCI2/TME

5

R124

4

59

X2

@ R133

2

0_0402_5%

CLK_Re

B

& lt; 22 & gt; CLK_48M_ICH
& lt; 24 & gt; CLK_48M_CB

2 15_0402_1%FSA
2 15_0402_1%

10

USB_48MHZ/FSLA

FSB
CLK_14M_ICH

57

FSLB/TEST_MODE

2 33_0402_5%FSC

62

45

VDDSRC_IO

SRC3/CR#_C
SRC3#/CR#_D

24
25

CLK_PCIE_ICH & lt; 22 & gt;
CLK_PCIE_ICH# & lt; 22 & gt;

For SRC5_EN, 0 = Enable DOT96 & SRC1

42

GNDSRC

SRC2/SATA
SRC2#/SATA#

21
22

CLK_PCIE_SATA & lt; 21 & gt;
CLK_PCIE_SATA# & lt; 21 & gt;

1 = Enable SRC0 & 27MHz

8

GNDPCI

11

GND48

SRC1/SE1/27MHz_NonSS
SRC1#/SE2/27MHz_SS

17
18

CLK_PCIE0
CLK_PCIE0#

15

1 GM@ 2
R751 1 GM@ 2
0_0402_5%
R752
0_0402_5%

CLK_DREF_SSC & lt; 8 & gt;
CLK_DREF_SSC# & lt; 8 & gt;

GND

19

R138

CPU_BSEL2

CLK_Rc

GND
SRC0/DOT96
SRC0#/DOT96#

13
14

R_CLK_DOT
R_CLK_DOT#

1 GM@ 2
R753 1 GM@ 2
0_0402_5%
R754
0_0402_5%

CLK_DREF_96M & lt; 8 & gt;
CLK_DREF_96M# & lt; 8 & gt;

1

1
1

2

R143
R143
1K_0402_1%

2

@ R145

For ITP_EN, 0 =SRC8/SRC8#; 1 = ITP/ITP#

2

0_0402_5%

CLK_Rf

+1.25VM_CK505

MCH_CLKSEL2 & lt; 8 & gt;

For PCI2_EN, 0 = Overclocking of CPU and SRC Allowed

GNDCPU

23

GNDSRC

1

GNDSRC

29

CK_PWRGD

R152
@ 10K_0402_5%

R153
@10K_0402_5%

R154
R154
10K_0402_5%
1

1

1

58
ITP_EN

27_SEL

R755
R755
@ 1K_0402_5%

C879
@ 0.1U_0402_16V4Z

2

1

52

2

CLK_XTAL_IN

+3VS

2

CLK_XTAL_OUT

+3VS

CK_PWRGD/PD#

56

CK_PWRGD

CK_PWRGD & lt; 22 & gt;

A

GNDREF
ICS9LPRS365BGLFT_TSSOP64

PCI2_TME

2

1

C284
1

2
R156
10K_0402_5%

R157
@10K_0402_5%

1

2006/08/05

Issued Date
C285
C285
22P_0402_50V8J

Compal Secret Data

Security Classification

2007/08/05

Deciphered Date

Title

1

22P_0402_50V8J

R155
10K_0402_5%
2
1

2

2

2

Y1

1

A

14.31818MHZ_20P_1BX14318BE1A

+3VS
2

1 = Overclocking of CPU and SRC NOT allowed

2

& lt; 5 & gt;

1
R144
R144
0_0402_5%

R139

@ 1K_0402_1%

1

FSC

R142
R142
10K_0402_5%
2
1

B

REF0/FSLC/TEST_SEL

R749 1
R750 1

2

CLK_48M_ICH
CLK_48M_CB

& lt; 22 & gt; CLK_14M_ICH

+1.05VS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

Compal Electronics, Inc.
CLOCK GENERATOR
Document Number

Rev
2.0

LA-3481P
Sheet

Tuesday, May 22, 2007
1

16

of

47

A

B

C

D

E

CRT CONNECTOR

CRT_R_L

+5VS

0.1U_0402_16V4Z

C291

1

GM@
2

1
C292

1

C293

GM@
2

GM@
2

+CRT_VCC

2
C295

1

GM@
2

2

C294

1

GM@
2

1

1
2
3
4
5
6
7
8
9
10
11
12

CRT_DDC_CLK
CRT_DDC_DAT
VSYNC
HSYNC
CRT_R_L
CRT_G_L
CRT_B_L

6P_0402_50V8K

2

1

CRT_B_L
6P_0402_50V8K

1

JP39

+CRT_VCC
F1

1

CH491D_SC59
1
1A_6VDC_MINISMDC110 C286

CRT_G_L

6P_0402_50V8K

GM@

2

C290

6P_0402_50V8K

GM@

2

1

C289

6P_0402_50V8K

1
C288

R166

6P_0402_50V8K

R165

GM@

R164

2
1
150_0402_1%
GM@

& lt; 10 & gt; GMCH_CRT_B

L18
1
2
FCM2012C-800_0805
GM@

2
1
150_0402_1%
GM@

L17
1
2
FCM2012C-800_0805
GM@

2
1
150_0402_1%
GM@

& lt; 10 & gt; GMCH_CRT_G

+R_CRT_VCC
D3

2

68P_0402_50V8K

L16
1
2
FCM2012C-800_0805
GM@

& lt; 10 & gt; GMCH_CRT_R

68P_0402_50V8K

1

ACES_85201-1205
GM@

+CRT_VCC

+CRT_VCC

L19 2
GM@ 10_0402_5%

HSYNC

D_CRT_VSYNC

1

L20 2
GM@ 10_0402_5%

VSYNC

2

Y

GM@

2

2

2

2

10P_0402_50V8J

5
1
P
OE#

3

G

A

GM@

4

1

CRT_DDC_DAT

3

& lt; 10 & gt; GMCH_CRT_CLK

Q4
1 2N7002_SOT23-3
GM@

CRT_DDC_CLK

D

2

& lt; 10 & gt; GMCH_CRT_VSYNC

C299

S
S

2
0.1U_0402_16V4Z
GM@

1

3

& lt; 10 & gt; GMCH_CRT_DATA

GM@
R174
4.7K_0402_5%

G

1
C297

C298

10P_0402_50V8J

+CRT_VCC

GM@
R173
4.7K_0402_5%
Q3
1 2N7002_SOT23-3
GM@

2

1
1

D

D_CRT_HSYNC

4

U5 GM@
SN74AHCT1G125GW_SOT353-5

S

2

Y

2

5
1
P
OE#

3

G

A

G

2

& lt; 10 & gt; GMCH_CRT_HSYNC

2 GM@ 1
R167
10K_0402_5%

1

+3VS

1
2
C296
0.1U_0402_16V4Z
GM@

U6
GM@
SN74AHCT1G125GW_SOT353-5

3

3

3

2

3

2

1

D8
@ DAN217_SC59

1

D7
@ DAN217_SC59

+3VS

2 C300
@ 22P_0402_50V8J

1

1
R180
1
R181

& lt; 19 & gt; VGA_TV_CRMA
& lt; 10 & gt; GMCH_TV_CRMA

2
PM@
2
GM@

0_0402_5%
TV_LUMA
0_0402_5%

L21
TV_CRMA

0_0402_5%

L22

1
1

TV@
TV@

2
MBK1608121YZF_0603
2
MBK1608121YZF_0603

1

& lt; 10 & gt; GMCH_TV_LUMA

2
PM@
2
GM@

0_0402_5%

JP6

1

1
R178
1
R179

& lt; 19 & gt; VGA_TV_LUMA

2

TV@

2

R183
150_0402_1%

R182
150_0402_1%
TV@

1

1

1

C302
100P_0402_50V8J
2 TV@

C303
100P_0402_50V8J
2 TV@

2 C301
@ 22P_0402_50V8J
1
C304
TV@

2
100P_0402_50V8J

TV_CRMA_L
TV_LUMA_L

1

4
3
2
1

C305
TV@

2
100P_0402_50V8J

4
3
2
1

6
5

ALLTO_C10877-104A1-L_4P
TV@

4

TV-OUT Conn.
1.
2.
3.
4.

ground
ground
(luminance+sync)
(crominance)

4

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

Y
C
Y
C

2006/08/05

Deciphered Date

2007/08/05

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

CRT & TVout Connector
Document Number

Rev
2.0

LA-3481P
Wednesday, May 23, 2007

Sheet
E

17

of

47

5

4

3

+3VS

2

1

+3VS
+3VS

+HDMI_5V_OUT
1

1
R960
2K_0402_1%
HDMI@

3
P

LM339MTX_TSSOP14~D
R74
HDMI@
3.01K_0402_1%
HDMI@

13

+
-

HDMI_SDA

11

G

U55D

R962
4.64K_0603_1%
HDMI@

10

O

2

12

2

VREF1

12

4

O

+HDMI_5V_OUT

1

HDMI_SCL

5

-

DVI_SDATA

2

R958
2K_0402_1%
HDMI@

2

3
P

1

+

G

U55B
2

R959
27.4K_0402_1%
HDMI@

2

R956
4.99K_0402_1%
HDMI@

0.1U_0402_16V7K

R961
4.64K_0603_1%
HDMI@

D

1

C953HDMI@
1
2

2

DVI_SCLK

1

R955
27.4K_0402_1%
HDMI@

2

1

+HDMI_5V_OUT
+HDMI_5V_OUT

D

VREF1
J4

LM339MTX_TSSOP14~D
HDMI@

1

1

2

2

@ JUMP_43X79
HDMI@
2
1
D62
CH491D_SC59

+5VS

P

U55A

-

G

LM339MTX_TSSOP14~D
HDMI@

9
1

+

+HDMI_5V_OUT

U55C

8

VREF2

-

1

C921
0.1U_0402_16V7K
HDMI@

LM339MTX_TSSOP14~D
HDMI@

14

O

1

12

O

P

+

6

12

1

2

G

7
VREF2

2

F2
1A_6VDC_MINISMDC110
HDMI@

3

+HDMI_5V_OUT

3

+HDMI_5V_OUT

1

2

R957
1.1K_0402_5%
HDMI@

HDMI Connector

2

C968
0.1U_0402_16V7K
HDMI@

1

Reserve Level Shifting Circuit
+3VS

R621 HDMI@
100K_0402_5%

C

+HDMI_5V_OUT

1

C842
0.1U_0402_16V7K
HDMI@

C

1

2

2

1

1

1
@

2

2

2

HDMI_SDA
HDMI_SCL
DVI_TXC-

HDMI_SCL

G
G

2

D

S

DVI_TXC+
DVI_TXD0-

2N7002_SOT23-3
@

Q135
1

3

HDMI_SDA

DVI_TXD0+
DVI_TXD1-

D

S

& lt; 19 & gt; DVI_SDATA

@

19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

+HDMI_5V_OUT

R705
19.1K_0402_5%

Q134
1

3

& lt; 19 & gt; DVI_SCLK

HDMI_DET

R706
19.1K_0402_5%
G

& lt; 19 & gt; VGA_HPD

R843
24K_0402_5%
@
2

2

1

JP7
R842
24K_0402_5%
@
2

HDMI@
R723
2.2K_0402_5%

2N7002_SOT23-3
DVI_TXD1+
DVI_TXD2-

@
R460
R442
1

1

2
@ 0_0402_5%

L66
2

2

DVI_TXC-

4

& lt; 19 & gt; VGA_DVI_TXC+
B

1
4

3

3

DVI_TXC+

1

& lt; 19 & gt; VGA_DVI_TXD1+

WCM2012F2S-900T04_0805
R441
HDMI@
1
2
@ 0_0402_5%

1

2

2

DVI_TXD1-

4

& lt; 19 & gt; VGA_DVI_TXD1-

4

3

3

DVI_TXD1+

R444

2
@ 0_0402_5%

1

L67
& lt; 19 & gt; VGA_DVI_TXD0-

1

& lt; 19 & gt; VGA_DVI_TXD0+

4

B

WCM2012F2S-900T04_0805
R459
HDMI@
1
2
@ 0_0402_5%

R443
1

20
21
22
23

TYCO_1939864-1_19P
HDMI@

L68

1

& lt; 19 & gt; VGA_DVI_TXC-

DVI_TXD2+

2
@ 0_0402_5%

HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKGND
CK_shield GND
CK+
GND
D0GND
D0_shield
D0+
D1D1_shield
D1+
D2D2_shield
D2+

2
@ 0_0402_5%

L69
2

4

2

DVI_TXD0-

3

1

3

DVI_TXD0+

& lt; 19 & gt; VGA_DVI_TXD2-

1

& lt; 19 & gt; VGA_DVI_TXD2+

4

WCM2012F2S-900T04_0805
HDMI@
R438
1
2
@ 0_0402_5%

1
4

2

2

DVI_TXD2-

3

3

DVI_TXD2+

WCM2012F2S-900T04_0805
HDMI@ R451
1
2
@ 0_0402_5%

+HDMI_5V_OUT

2

HDMI_DET

1

A

A

4

VGA_HPD

Y

U54
SN74AHCT1G125GW_SOT353-5
HDMI@

12

A

13

B

U13D

P

14

3

A

G

2

P
OE#

5
1

C966
0.1U_0402_16V4Z
HDMI@

7

2006/06/30

Issued Date

SN74LVC08APW_TSSOP14

For HDMI Hot Plug Issue

Compal Electronics, Inc.

Compal Secret Data

Security Classification

11

G

O

2007/06/30

Deciphered Date

Title

SiI1392 & HDMI Connector

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
2.0

LA-3481P

Date:

5

4

3

2

Sheet

Saturday, June 23, 2007
1

18

of

47

5

4

3

2

1

LCD POWER CIRCUIT

JP8

VGA BOARD Conn.

GM@

1

& lt; 10 & gt; GMCH_ENVDD

VGA_ENVDD
2
R489 0_0402_5%

PCIE_MTX_C_GRX_N[0..15]

& lt; 10 & gt; PCIE_MTX_C_GRX_N[0..15]

PCIE_MTX_C_GRX_P[0..15]

& lt; 10 & gt; PCIE_MTX_C_GRX_P[0..15]

5
1
G

& lt; 10 & gt; PCIE_GTX_C_MRX_P[0..15]

SN74AHCT1G125GW_SOT353-5

Y

4

U44
+3VS

2
R567
R567
100_0402_5%

JP42
VGA_TZOUT1-

1
R351

VGA_TXOUT0+
VGA_TXOUT0VGA_TXOUT1+
VGA_TXOUT1VGA_TXOUT2VGA_TXOUT2+

+3VS

470_0805_5%

3

Q45
2N7002_SOT23-3

2
G

S

12

W=60mils

D

2

Q43
VGA_LCD_CLK
VGA_LCD_DATA
+LCDVDD_C
+LCDVDD_C

AOS 3401_SOT23

3

S

0.047U_0402_16V7K

W=60mils

+1.5VS

30
28
26
24
22
20
18
16
14
12
10
8
6
4
2

0.1U_0402_16V4Z

2

B+

VGA_TZCLKVGA_TXCLKVGA_TXCLK+

2
RB751V_SOD323

VGA_TXOUT0+
VGA_TXOUT0VGA_TXOUT1+
VGA_TXOUT1VGA_TXOUT2VGA_TXOUT2+

DAC_BRIG
+LCDVDD

KC FBM-L11-201209-221LMAT_0805
L83 1
2
L31 1
2
KC FBM-L11-201209-221LMAT_0805

VGA_LCD_CLK
VGA_LCD_DATA
+LCDVDD_C
+LCDVDD_C

1

@
2 C797 68P_0402_50V8K

INVT_PWM

1

@
2 C798 68P_0402_50V8K

DISPOFF#

C331
C331

1

@
2 C799 68P_0402_50V8K

VGA_LCD_CLK

@
2 C800 68P_0402_50V8K

39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1

39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1

40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2

PCEI_GTX_C_MRX_P6
PCEI_GTX_C_MRX_N6
PCEI_GTX_C_MRX_P5
PCEI_GTX_C_MRX_N5

+3VS

PCEI_GTX_C_MRX_P4
PCEI_GTX_C_MRX_N4

DISPOFF#
DAC_BRIG
INVT_PWM

1
DAC_BRIG & lt; 29 & gt;
INVT_PWM & lt; 29 & gt;

2

VGA_TXCLKVGA_TXCLK+

VGA_TXOUT1+
VGA_TXOUT1-

GMCH_LCD_CLK
GMCH_LCD_DATA

PCEI_GTX_C_MRX_P3
PCEI_GTX_C_MRX_N3

C330
C330
0.1U_0402_16V4Z

PCEI_GTX_C_MRX_P2
PCEI_GTX_C_MRX_N2
PCEI_GTX_C_MRX_P1
PCEI_GTX_C_MRX_N1

+INV

PCEI_GTX_C_MRX_P0
PCEI_GTX_C_MRX_N0

ACES_88242-4001~N

1

& lt; 18 & gt; VGA_HPD
& lt; 18 & gt; DVI_SCLK
& lt; 18 & gt; DVI_SDATA
& lt; 18 & gt; VGA_DVI_TXD0 & lt; 18 & gt; VGA_DVI_TXD0+
& lt; 18 & gt; VGA_DVI_TXD1 & lt; 18 & gt; VGA_DVI_TXD1+

ALL R CLOSE TO VGA CONNECTOR

VGA_TXOUT0+
VGA_TXOUT0-

PCEI_GTX_C_MRX_P8
PCEI_GTX_C_MRX_N8

VGA_TZCLK+
VGA_TZCLK-

VGA_LCD_DATA

VGA_LCD_CLK
VGA_LCD_DATA

PCEI_GTX_C_MRX_P9
PCEI_GTX_C_MRX_N9

PCEI_GTX_C_MRX_P7
PCEI_GTX_C_MRX_N7

40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2

22U_0805_6.3V6M
2

1

B

PCEI_GTX_C_MRX_P10
PCEI_GTX_C_MRX_N10

2
6P_0402_50V8K
2
6P_0402_50V8K
2
6P_0402_50V8K
2
6P_0402_50V8K

JP9
JP9
VGA_TZOUT0VGA_TZOUT0+
VGA_TZOUT2VGA_TZOUT2+
VGA_TZOUT1+
VGA_TZOUT1-

2
R949 0_0402_5%

@
2 C796 68P_0402_50V8K

1
C958
1
C959
1
C960
1
C961

DISPOFF#

+INV
L29 KC FBM-L11-201209-221LMAT_0805
1
2
1
C918
1
C795
@
0.1U_0402_16V4Z
2
68P_0402_50V8K
2

1

PCEI_GTX_C_MRX_P13
PCEI_GTX_C_MRX_N13

PCEI_GTX_C_MRX_P11
PCEI_GTX_C_MRX_N11
VGA_TZCLK+

1
2
1

PCEI_GTX_C_MRX_P14
PCEI_GTX_C_MRX_N14
+INV

4.7K_0402_5%

@ D11

1

+2.5VS
PCEI_GTX_C_MRX_P15
PCEI_GTX_C_MRX_N15

PCEI_GTX_C_MRX_P12
PCEI_GTX_C_MRX_N12

R209
R209

BKOFF#

DAC_BRIG & lt; 29 & gt;
INVT_PWM & lt; 29 & gt;

VGA_TXCLKVGA_TXCLK+

1

C725
C725

+3VS

BKOFF#

DISPOFF#
DAC_BRIG
INVT_PWM

C726

C

& lt; 29 & gt;

+3VS

ACES_88242-3000

4.7U_0805_10V4Z

1

C724

1

1

G

100K_0402_5%
R337
R337

2

+LCDVDD
D

2

29
27
25
23
21
19
17
15
13
11
9
7
5
3
1

@

+LCDVDD

@

C914
0.01U_0402_16V7K

A

PCEI_GTX_C_MRX_P[0..15]

3

D

P
OE#

2
1

1 GM@
R777 1 GM@
R778

2
0_0402_5%
2
0_0402_5%

1 GM@
R779 1 GM@
R781

2
0_0402_5%
2
0_0402_5%

GMCH_TXOUT0+ & lt; 10 & gt;
GMCH_TXOUT0- & lt; 10 & gt;

1 GM@
R783 1 GM@
R785

2
0_0402_5%
2
0_0402_5%

GMCH_TXOUT1+ & lt; 10 & gt;
GMCH_TXOUT1- & lt; 10 & gt;

& lt; 18 & gt; VGA_DVI_TXD2 & lt; 18 & gt; VGA_DVI_TXD2+

GMCH_LCD_CLK & lt; 10 & gt;
GMCH_LCD_DATA & lt; 10 & gt;

& lt; 18 & gt; VGA_DVI_TXC+
& lt; 18 & gt; VGA_DVI_TXCVGA_TZOUT0+
VGA_TZOUT0-

VGA_TZOUT1+
VGA_TZOUT1-

1 GM@
R780 1 GM@
R782

2
0_0402_5%
2
0_0402_5%

GMCH_TZOUT0+ & lt; 10 & gt;
GMCH_TZOUT0- & lt; 10 & gt;

1 GM@
R784 1 GM@
R786

2
0_0402_5%
2
0_0402_5%

GMCH_TZOUT1+ & lt; 10 & gt;
GMCH_TZOUT1- & lt; 10 & gt;

& lt; 4,29 & gt; EC_SMB_CK2
& lt; 4,29 & gt; EC_SMB_DA2
+5VALW
+CRT_VCC
& lt; 27,29,30,35,38,40,41,42 & gt;

VGA_TXOUT2+
VGA_TXOUT2-

VGA_TXCLK+
VGA_TXCLK-

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
205

B+

PCEI_GTX_C_MRX_N[0..15]

& lt; 10 & gt; PCIE_GTX_C_MRX_N[0..15]
+3VS

1 GM@
R787 1 GM@
R789

2
0_0402_5%
2
0_0402_5%

1 GM@
R791 1 GM@
R793

2
0_0402_5%
2
0_0402_5%

GMCH_TXOUT2+ & lt; 10 & gt;
GMCH_TXOUT2- & lt; 10 & gt;

GMCH_TXCLK+ & lt; 10 & gt;
GMCH_TXCLK- & lt; 10 & gt;

VGA_TZOUT2+
VGA_TZOUT2-

VGA_TZCLK+
VGA_TZCLK-

1 GM@
R788 1 GM@
R790

2
0_0402_5%
2
0_0402_5%

GMCH_TZOUT2+ & lt; 10 & gt;
GMCH_TZOUT2- & lt; 10 & gt;

1 GM@
R792 1 GM@
R794

2
0_0402_5%
2
0_0402_5%

SUSP#

VGA_ENVDD
VGA_ENBKL

GMCH_TZCLK+ & lt; 10 & gt;
GMCH_TZCLK- & lt; 10 & gt;

& lt; 29 & gt; VGA_ENBKL
& lt; 17 & gt; VGA_TV_LUMA
& lt; 17 & gt; VGA_TV_CRMA

VGA_TV_LUMA
VGA_TV_CRMA

A

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
205

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206

+1.8VS

D

+2.5VS
PCIE_MTX_C_GRX_P15
PCIE_MTX_C_GRX_N15
PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_N13
PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_N11
PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_N10
C

PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_N9
PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_N8
PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_N7
PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_N5
PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_N4
PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_N3
PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_N1
PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_N0
CLK_PCIE_VGA
CLK_PCIE_VGA#

CLK_PCIE_VGA & lt; 16 & gt;
CLK_PCIE_VGA# & lt; 16 & gt;
SPDIF
& lt; 27 & gt;
PLTRST_VGA# & lt; 20 & gt;

PLTRST_VGA#
VGA_LCD_DATA
VGA_LCD_CLK

B

VGA_TXCLKVGA_TXCLK+
VGA_TXOUT0VGA_TXOUT0+
VGA_TXOUT1VGA_TXOUT1+
VGA_TXOUT2VGA_TXOUT2+
VGA_TZOUT0VGA_TZOUT0+
VGA_TZOUT1VGA_TZOUT1+
VGA_TZOUT2VGA_TZOUT2+
VGA_TZCLKVGA_TZCLK+

A

JAE_WB3F200VD1R1000~D

Compal Secret Data

Security Classification
Issued Date

2006/08/05

Deciphered Date

2007/08/05

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

Compal Electronics, Inc.
VGA CONN
Document Number

Rev
2.0

LA-3481P
Saturday, June 23, 2007

Sheet
1

19

of

47

5

4

3

2

1

+3VS

RP50
D

1
2
3
4

PCI_REQ#2
PCI_REQ#1
PCI_DEVSEL#
PCI_FRAME#

8
7
6
5

8.2K_0804_8P4R_5%
RP51
1
8
2
7
3
6
4
5

PCI_STOP#
PCI_REQ#3
PCI_PIRQD#
PCI_TRDY#

8.2K_0804_8P4R_5%
RP52
1
8
2
7
3
6
4
5

PCI_IRDY#
PCI_PLOCK#
PCI_PERR#
PCI_PIRQE#

8.2K_0804_8P4R_5%
RP53
1
8
2
7
3
6
4
5

C

D

& lt; 24 & gt; PCI_AD[0..31]

PCI_PIRQB#
PCI_PIRQC#
PCI_REQ#0
PCI_PIRQH#

8.2K_0804_8P4R_5%
RP54
1
8
2
7
3
6
4
5

PCI_PIRQG#
PCI_PIRQF#
PCI_SERR#
PCI_PIRQA#

8.2K_0804_8P4R_5%
R649 1

@
2 8.2K_0402_5%

PME#

& lt; 24 & gt; PCI_PIRQA#
& lt; 24 & gt; PCI_PIRQB#
& lt; 24 & gt; PCI_PIRQC#

U10B
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

D20
E19
D19
A20
D17
A21
A19
C19
A18
B16
A12
E16
A14
G16
A15
B6
C11
A9
D11
B12
C12
D10
C7
F13
E11
E13
E12
D8
A6
E8
D6
A3

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

F9
B5
C5
A10

PIRQA#
PIRQB#
PIRQC#
PIRQD#

PCI_REQ#0
PCI_GNT#0
PCI_REQ#1

REQ0#
GNT0#
REQ1#/GPIO50
GNT1#/GPIO51
REQ2#/GPIO52
GNT2#/GPIO53
REQ3#/GPIO54
GNT3#/GPIO55
C/BE0#
C/BE1#
C/BE2#
C/BE3#

C17
E15
F16
E17

PCI_CBE#0
PCI_CBE#1
PCI_CBE#2
PCI_CBE#3

IRDY#
PAR
PCIRST#
DEVSEL#
PERR#
PLOCK#
SERR#
STOP#
TRDY#
FRAME#

C8
D9
G6
D16
A7
B7
F10
C16
C9
A17

PCI_IRDY#
PCI_PAR
PCI_RST#
PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#

PLTRST#
PCICLK
PME#

PCI

A4
D7
E18
C18
B19
F18
A11
C10

AG24
B10
G7

PCI_PLTRST#
CLK_PCI_ICH
PME#
Internal pull-up 18K

F8
G11
F12
B3

PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#

Interrupt I/F
PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5

PCI_REQ#2
PCI_GNT#2
PCI_REQ#3

PCI_REQ#2 & lt; 24 & gt;
PCI_GNT#2 & lt; 24 & gt;

PCI_CBE#0
PCI_CBE#1
PCI_CBE#2
PCI_CBE#3

& lt; 24 & gt;
& lt; 24 & gt;
& lt; 24 & gt;
& lt; 24 & gt;

PCI_IRDY# & lt; 24 & gt;
PCI_PAR & lt; 24 & gt;
PCI_RST# & lt; 24,29,35 & gt;
PCI_DEVSEL# & lt; 24 & gt;
PCI_PERR# & lt; 24 & gt;
PCI_SERR# & lt; 24 & gt;
PCI_STOP# & lt; 24 & gt;
PCI_TRDY# & lt; 24 & gt;
PCI_FRAME# & lt; 24 & gt;
CLK_PCI_ICH

C

& lt; 16 & gt;

PCI_PIRQE# & lt; 24 & gt;
PCI_PIRQF# & lt; 24 & gt;
PCI_PIRQG# & lt; 24 & gt;

ICH8M_BGA676~D
ICH8MR3@

U48

Y

Boot BIOS Location

4

PLT_RST# & lt; 8,22,26,30,31 & gt;

@ TC7SH08FU_SSOP5

1

SPI_CS#0

A

3

PCI_GNT0#

B

2
B

1

P

PCI_PLTRST#

Boot BIOS Strap

G

5

+3VS

B

R836
100K_0402_5%

0
1

LPC *

+3VS

R709
R709
10_0402_5%

P
G

4
Y PM@

PLTRST_VGA# & lt; 19 & gt;

TC7SH08FU_SSOP5

R858
100K_0402_5%
R859

2

1 @ 0_0402_5%

1

R305
@ 1K_0402_5%

U50

2

1

1
R290
@ 1K_0402_5%

A

2

CLK_PCI_ICH

& lt; 22 & gt; SPI_CS1#_R

B

3

1
2

PCI_GNT#0

0_0402_5%

1

PCI

1

2

2

1

R837

SPI

1

1

5

0

2

2

1

2

C869
C869
22P_0402_50V8J

A

A

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2006/08/05

Issued Date

Deciphered Date

2007/08/05

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

ICH8-M(1/4)
Document Number

Rev
2.0

LA-3481P
Tuesday, May 22, 2007

Sheet
1

20

of

47

5

4

3

2

1

+RTCVCC

C333
C333
12P_0402_50V8J
2
1

ICH_RTCX1

1

D

2

AG25
AF24

ICH_RTCRST#

AF23
AD22

INTRUDER#

ICH_INTVRMEN
LAN100_SLP

AF25
AD21

INTVRMEN
LAN100_SLP

1
@ JOPEN

close to RAM door

& lt; 30 & gt; ICH_BITCLK_MDC

R285

& lt; 30 & gt; ICH_SYNC_MDC

R286

& lt; 30 & gt; ICH_RST_MDC#

R287
R288

& lt; 30 & gt; ICH_SDOUT_MDC

RTCX1
RTCX2

B24

ICH_AC_SYNC_R
2
33_0402_5%

D21
E20
C20
AH21

1
1

2

ICH_AC_RST_R#
33_0402_5%

1

2

ICH_AC_SDOUT_R
33_0402_5%

1 R795
2
24.9_0402_1%

+1.5VS

ICH_AC_BITCLK
33_0402_5%

1

2

1

AE14

2 ICH_AC_SYNC_R
33_0402_5%

HDA_SDIN0
HDA_SDIN1
HDA_SDIN2
HDA_SDIN3

AE13

HDA_SDOUT

AE10
AG14

HDA_DOCK_EN#/GPIO33
HDA_DOCK_RST#/GPIO34

AF10

SATALED#

AF6
AF5
AH5
AH6

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP

SATA_DTX_C_IRX_N2
SATA_DTX_C_IRX_P2
SATA_ITX_DRX_N2
SATA_ITX_DRX_P2

AF2
AF1
AE4
AE3

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

CLK_PCIE_SATA#
CLK_PCIE_SATA

AB7
AC6

SATA_CLKN
SATA_CLKP

AG1
AG2

SATARBIAS#
SATARBIAS

ICH_AC_SDOUT_R
& lt; 27 & gt; ICH_RST_AUDIO#

R294

& lt; 27 & gt; ICH_SDOUT_AUDIO

R295

1
1

2

ICH_AC_RST_R#
33_0402_5%

2 ICH_AC_SDOUT_R
33_0402_5%

& lt; 30 & gt; MDC_RST#
& lt; 32 & gt; ODD_RST#
HDD_LED#

& lt; 34 & gt; HDD_LED#

SATA_DTX_C_IRX_N0
SATA_DTX_C_IRX_P0
SATA_ITX_DRX_N0
SATA_ITX_DRX_P0

& lt; 32 & gt; SATA_DTX_C_IRX_N0
& lt; 32 & gt; SATA_DTX_C_IRX_P0

Main HDD

& lt; 32 & gt; SATA_DTX_C_IRX_N2
& lt; 32 & gt; SATA_DTX_C_IRX_P2

Second HDD

B

& lt; 16 & gt; CLK_PCIE_SATA#
& lt; 16 & gt; CLK_PCIE_SATA

1
R301
R301

SATARBIAS

2
24.9_0402_1%

10mils

AE24
AC20
AH14

H_INIT#
H_INTR
EC_KBRST#

AD23
AG28

H_NMI
H_SMI#

AA24

H_STPCLK#

AE27

THRMTRIP_ICH#

TP8

1
C336
C336

SATA_ITX_C_DRX_N0
2
3900P_0402_50V7K

1
C337
C337

SATA_ITX_C_DRX_P0
2
3900P_0402_50V7K

2 10K_0402_5%

R289
R289 1

2 10K_0402_5%

+1.05VS

AA23

H_FERR# & lt; 4 & gt;

DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9
DD10
DD11
DD12
DD13
DD14
DD15

V1
U2
V3
T1
V4
T5
AB2
T6
T3
R2
T4
V6
V5
U1
V2
U6
AA4
AA1
AB3
Y6
Y5

1 56_0402_5%

2

1 56_0402_5%

& lt; 4 & gt;
& lt; 4 & gt;
C

H_STPCLK# & lt; 4 & gt;
R291
R291 1

2 24.9_0402_1%

IDE_DD[0..15]

IDE_DCS1#
IDE_DCS3#

W4
W3
Y2
Y3
Y1
W5

2

R15
R15

H_INIT#
& lt; 4 & gt;
H_INTR
& lt; 4 & gt;
EC_KBRST# & lt; 29 & gt;

IDE_DA0
IDE_DA1
IDE_DA2

DCS1#
DCS3#

R24
R24

H_THERMTRIP#

H_IGNNE# & lt; 4 & gt;

IDE_DD0
IDE_DD1
IDE_DD2
IDE_DD3
IDE_DD4
IDE_DD5
IDE_DD6
IDE_DD7
IDE_DD8
IDE_DD9
IDE_DD10
IDE_DD11
IDE_DD12
IDE_DD13
IDE_DD14
IDE_DD15

DA0
DA1
DA2

H_FERR#

H_PWRGOOD & lt; 5 & gt;

IDE_DIOR#
IDE_DIOW#
IDE_DDACK#
IDE_IRQ
IDE_DIORDY
IDE_DDREQ

H_THERMTRIP#

H_THERMTRIP# & lt; 4,8 & gt;

& lt; 32 & gt;

RTC Battery
Layout Note:
1. Under BATT1 battery Body, no Trace no Via
2. BATT1 + - PIN keep out 80mil from other component ,trace and via

IDE_DA[0..2]

-

& lt; 32 & gt;

+

BATT1

2
IDE_DCS1# & lt; 32 & gt;
IDE_DCS3# & lt; 32 & gt;

1

+RTCBATT

+RTCBATT

B

45@ RTCBATT

IDE_DIOR# & lt; 32 & gt;
IDE_DIOW# & lt; 32 & gt;
IDE_DDACK# & lt; 32 & gt;
IDE_IRQ
& lt; 32 & gt;
IDE_DIORDY & lt; 32 & gt;
IDE_DDREQ & lt; 32 & gt;

D12
BAS40-04_SOT23
+RTCVCC
+CHGRTC

1

SATA_ITX_C_DRX_N0 & lt; 32 & gt;

SATA_ITX_DRX_P0

R282
R282 1

D

H_DPRSTP# & lt; 5,8,43 & gt;

ICH8M_BGA676~D
ICH8MR3@
SATA_ITX_DRX_N0

2 8.2K_0402_5%

GATEA20

2 0_0402_5%
H_DPSLP# & lt; 5 & gt;

H_NMI
H_SMI#

DIOR#
DIOW#
DDACK#
IDEIRQ
IORDY
DDREQ

IDE

R293

H_IGNNE#

INIT#
INTR
RCIN#

2 4.7K_0402_5%

R302
R302 1

GATEA20 & lt; 29 & gt;
H_A20M# & lt; 4 & gt;
R283
1 R283

H_PWRGOOD

AF27

2 10K_0402_5%

R300
R300 1

LPC_DRQ#1 & lt; 35 & gt;

H_FERR#

HDA_RST#

AJ17
AH17
AH15
AD13

& lt; 27 & gt; ICH_AC_SDIN0
& lt; 30 & gt; ICH_AC_SDIN1

AD24
AG29

IGNNE#

IHDA

& lt; 27 & gt; ICH_SYNC_AUDIO

FERR#

SATA

R292

DPRSTP#
H_DPSLP#

CPUPWRGD/GPIO49

HDA_BIT_CLK
HDA_SYNC

AG3
AG4
AJ4
AJ3

& lt; 27 & gt; ICH_BITCLK_AUDIO

AF26
AE26

R860
R860 1

IDE_IRQ

& lt; 29,35 & gt;
& lt; 29,35 & gt;
& lt; 29,35 & gt;
& lt; 29,35 & gt;

LPC_FRAME# & lt; 29,35 & gt;

GATEA20
H_A20M#

STPCLK#

AJ16
AJ15

ICH_AC_RST_R#

AF13
AG26

THRMTRIP#

GLAN_COMPI
GLAN_COMPO

C

For Audio code use

LPC_DRQ#1

NMI
SMI#

GLAN_DOCK#/GPIO13

D25
C25
ICH_AC_BITCLK
ICH_AC_SYNC_R

LPC_FRAME#

G9
E6

DPRSTP#
DPSLP#

LAN_TXD_0
LAN_TXD_1
LAN_TXD_2

ICH_AC_BITCLK
33_0402_5%

C4

LDRQ0#
LDRQ1#/GPIO23

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

A20GATE
A20M#

LAN_RXD0
LAN_RXD1
LAN_RXD2

2

FWH4/LFRAME#

LAN_RSTSYNC

C21
B21
C22

1

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

IDE_DIORDY

EC_KBRST#

E5
F5
G8
F6

FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3

GLAN_CLK

D22

C335
C335
1U_0603_10V4Z
1
2

For Modem Use

HDD_LED#

RTCRST#

SM_INTRUDER#

1
2
+RTCVCC
R281
R281
20K_0402_5%

J1

U10A

ICH_RTCX2

1

IN

C334
C334
12P_0402_50V8J
2
1

LPC

NC

+3VS

2

4

2

32.768KHZ_12.5P_1TJS125DJ2A073

OUT

LAN / GLAN

LAN100_SLP
1
2
R606
R606 332K_0402_1%

NC

CPU

3

3

X1

RTC

ICH_INTVRMEN
1
2
R278
R278 332K_0402_1%

R279
R279
10M_0402_5%
2
1

SM_INTRUDER#
1
2
R277
R277 1M_0402_5%

C355
C355
0.1U_0402_16V4Z

SATA_ITX_C_DRX_P0 & lt; 32 & gt;

SATA_ITX_DRX_N2
SATA_ITX_DRX_P2

2HDD@
SATA_ITX_C_DRX_N1
1
2
C338
3900P_0402_50V7K
2HDD@
SATA_ITX_C_DRX_P1
1
2
C339
3900P_0402_50V7K

2

SATA_ITX_C_DRX_N2 & lt; 32 & gt;
SATA_ITX_C_DRX_P2 & lt; 32 & gt;
+3VS

close ICH8
A

R303
1K_0402_1%
@

XOR Chain Entrance Strap
ICH_TP3

HDA_SDOUT

Description

0

0
1

Enter XOR Chain

1

0

Normal Operation

1

1

ICH_AC_SDOUT_R

RSVD

0

A

Set PCIE port config bit 1

Compal Secret Data

Security Classification
& lt; 22 & gt; ICH_TP3

2006/08/05

Issued Date
R307
1K_0402_1%
@

Deciphered Date

2007/08/05

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

Compal Electronics, Inc.
ICH8-M(2/4)
Document Number

Rev
2.0

LA-3481P
Tuesday, May 22, 2007

Sheet
1

21

of

47

5

4

3

2

1

+3V_SB

& lt; 33 & gt; BT_DET#
SERIRQ

R609
R609
1

& lt; 16 & gt; SATA_CLKREQ#
& lt; 25 & gt; PCM_DISABLE#

ICH_VGATE
OCP#

& lt; 27 & gt;

& lt; 21 & gt;

10K_0402_5%
2

SB_SPKR

SB_SPKR

VRMPWRGD

AD9

SPKR
MCH_SYNC#

AJ21

ICH_TP3

TP3

PWROK

PWROK

DPRSLPVR/GPIO16

AJ14

DPRSLPVR

BATLOW#

AE21

PBTN_OUT#

PWRBTN#

10K_0402_5%
R703
R703 1
2

BT_DET#

R731 332K_0402_1%
1
2

ACIN_D

H_STP_CPU#

E1

F23
AE18
F22
AF19

AJ23

CL_RST#

MEM_LED/GPIO24
ME_EC_ALERT/GPIO10
EC_ME_ALERT/GPIO14
WOL_EN/GPIO9

AJ27
AJ24
AF22
AG19

1 0.1U_0402_16V7K
1 0.1U_0402_16V7K

PCIE_PTX_C_IRX_N2
PCIE_PTX_C_IRX_P2
PCIE_ITX_PRX_N2
PCIE_ITX_PRX_P2

M27
M26
L29
L28

WLAN

& lt; 31 & gt;
& lt; 31 & gt;
& lt; 31 & gt;
& lt; 31 & gt;

PCIE_PTX_C_IRX_N3
PCIE_PTX_C_IRX_P3
PCIE_ITX_C_PRX_N3
PCIE_ITX_C_PRX_P3

C349 2
C350 2

1 0.1U_0402_16V7K
1 0.1U_0402_16V7K

PCIE_PTX_C_IRX_N3
PCIE_PTX_C_IRX_P3
PCIE_ITX_PRX_N3
PCIE_ITX_PRX_P3

K27
K26
J29
J28

PERN3
PERP3
PETN3
PETP3

C351 2
C352 2

1 0.1U_0402_16V7K
1 0.1U_0402_16V7K

PCIE_PTX_C_IRX_N4
PCIE_PTX_C_IRX_P4
PCIE_ITX_PRX_N4
PCIE_ITX_PRX_P4

H27
H26
G29
G28

PERN4
PERP4
PETN4
PETP4

C927 2
C928 2

1 0.1U_0402_16V7K
1 0.1U_0402_16V7K

PCIE_PTX_C_IRX_N5
PCIE_PTX_C_IRX_P5
PCIE_ITX_PRX_N5
PCIE_ITX_PRX_P5

F27
F26
E29
E28

PERN5
PERP5
PETN5
PETP5

& lt; 31 & gt;
& lt; 31 & gt;
& lt; 31 & gt;
& lt; 31 & gt;

PCIE_PTX_C_IRX_N5
PCIE_PTX_C_IRX_P5
PCIE_ITX_C_PRX_N5
PCIE_ITX_C_PRX_P5

P27
P26
N29
N28

SPI_CS0#
R903

@ 100K_0402_5%
1
2 CIR_EN#

R927
R927 1K_0402_1%
1
2
CIR@

1
R341
R341

2
10K_0402_5%

A

SPI_CLK
SPI_CS0#
SPI_CS1#

D23
F21

SPI_MOSI
SPI_MISO

& lt; 30 & gt; EXP_CPPE#

USB_OC#0
USB_OC#1
USB_OC#2
USB_OC#3
USB_OC#4
USB_OC#5
USB_OC#6

EXP_CPPE#
USB_OC#8
USB_OC#9

AJ19
AG16
AG15
AE15
AF15
AG17
AD12
AJ18
AD14
AH18

OC0#
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43
OC5#/GPIO29
OC6#/GPIO30
OC7#/GPIO31
OC8#
OC9#

EC_SMI#

DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP

DMI_MTX_IRX_N3
DMI_MTX_IRX_P3
DMI_ITX_MRX_N3
DMI_ITX_MRX_P3

DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP

Y27
Y26
W29
W28

DMI_MTX_IRX_N2
DMI_MTX_IRX_P2
DMI_ITX_MRX_N2
DMI_ITX_MRX_P2

DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP

AB26
AB25
AA29
AA28

DMI_MTX_IRX_N1
DMI_MTX_IRX_P1
DMI_ITX_MRX_N1
DMI_ITX_MRX_P1

DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP

AD27
AD26
AC29
AC28

DMI_MTX_IRX_N0
DMI_MTX_IRX_P0
DMI_ITX_MRX_N0
DMI_ITX_MRX_P0

DMI_CLKN
DMI_CLKP

T26
T25

CLK_PCIE_ICH#
CLK_PCIE_ICH

Y23
Y24

DMI_IRCOMP

USB

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P

G3
G2
H5
H4
H2
H1
J3
J2
K5
K4
K2
K1
L3
L2
M5
M4
M2
M1
N3
N2
F2
F3

USBRBIAS

DMI_MTX_IRX_N3
DMI_MTX_IRX_P3
DMI_ITX_MRX_N3
DMI_ITX_MRX_P3

DMI_MTX_IRX_N1
DMI_MTX_IRX_P1
DMI_ITX_MRX_N1
DMI_ITX_MRX_P1

& lt; 8 & gt;
& lt; 8 & gt;
& lt; 8 & gt;
& lt; 8 & gt;

DMI_MTX_IRX_N0
DMI_MTX_IRX_P0
DMI_ITX_MRX_N0
DMI_ITX_MRX_P0

& lt; 8 & gt;
& lt; 8 & gt;
& lt; 8 & gt;
& lt; 8 & gt;

2
1

SUS_CLK

2006/08/05

@
1 10K_0402_5%

R336
R336 1

2 100K_0402_5%

PWROK

R321
R321 1

2 10K_0402_5%

RSMRST#

R326
R326 1

2 10K_0402_5%

CLK_PCIE_ICH# & lt; 16 & gt;
CLK_PCIE_ICH & lt; 16 & gt;
R340
R340 24.9_0402_1%
1
2
USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N6
USB20_P6
USB20_N7
USB20_P7
USB20_N8
USB20_P8
USB20_N9
USB20_P9

B

+3VS

Within 500 mils
+1.5VS

& lt; 33 & gt;
RIGHT USB Port (Samll Board)
& lt; 33 & gt;
& lt; 33 & gt;
RIGHT USB Port (Samll Board)
& lt; 33 & gt;
& lt; 31 & gt;
3G Card
& lt; 31 & gt;
& lt; 31 & gt;
2
& lt; 31 & gt;
& lt; 43 & gt; CLK_ENABLE#
G
& lt; 33 & gt;
2N7002_SOT23-3
LEFT USB Port
& lt; 33 & gt;
& lt; 33 & gt;
LEFT USB Port
& lt; 33 & gt;
& lt; 33 & gt;
Fingerprint
& lt; 33 & gt;
& lt; 33 & gt;
Blue Tooth
& lt; 33 & gt;
& lt; 33 & gt;
Internal Camera
& lt; 33 & gt;
& lt; 30 & gt;
Express Card
& lt; 30 & gt;

R800
330_0402_5%

1
R801

2 CK_PWRGD
0_0402_5%

1
R802

D

2 ICH_VGATE
@ 0_0402_5%

S Q63
1
C894
@ 0.1U_0402_16V4Z

2

Add for find
tune
timing.(glich
issue 7/28)

R342
R342 22.6_0402_1%
1
2

A

Within 500 mils

2007/08/05

Deciphered Date

Title

Date:

3

R798 2

DPRSLPVR

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

7

& lt; 8 & gt;
& lt; 8 & gt;
& lt; 8 & gt;
& lt; 8 & gt;

Compal Secret Data

Security Classification

5

R325
R325 8.2K_0402_5%
2
1

& lt; 8 & gt;
& lt; 8 & gt;
& lt; 8 & gt;
& lt; 8 & gt;

DMI_MTX_IRX_N2
DMI_MTX_IRX_P2
DMI_ITX_MRX_N2
DMI_ITX_MRX_P2

USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N6
USB20_P6
USB20_N7
USB20_P7
USB20_N8
USB20_P8
USB20_N9
USB20_P9

ICH8M_BGA676~D
ICH8MR3@

Issued Date

+3V_SB

PM_BATLOW#
V27
V26
U29
U28

USBRBIAS#
USBRBIAS

+3V_SB

@ 10K_0402_5%
R328 1
SPI_MISO
2

10K_0402_5%
R803 1
2

C23
B23
E22

SPI_MOSI
SPI_MISO

@ 10K_0402_5%
R327 1
SPI_MOSI
2

@ 10K_0402_5%
SPI_CS0#
R329 1
2

PERN6/GLAN_RXN
PERP6/GLAN_RXP
PETN6/GLAN_TXN
PETP6/GLAN_TXP

& lt; 20 & gt; SPI_CS1#_R

C

SPK_SEL_CODEC & lt; 27 & gt;

DMI_ZCOMP
DMI_IRCOMP

PERN1
PERP1
PETN1
PETP1

D27
D26
C29
C28
+3V_SB

R334
453_0402_1%

CL_RST# & lt; 8 & gt;

SPK_SEL_CODEC

ICH8M_BGA676~D
ICH8MR3@

PERN2
PERP2
PETN2
PETP2

HD DVD card

1

C343
C343

0.1U_0402_16V4Z
2

CL_DATA0 & lt; 8 & gt;

D24
AH23

C346 2
C347 2

Robson

CL_CLK0 & lt; 8 & gt;

CL_RST#

PCIE_PTX_C_IRX_N2
PCIE_PTX_C_IRX_P2
PCIE_ITX_C_PRX_N2
PCIE_ITX_C_PRX_P2

ROB@
ROB@

CL_VREF0_ICH

AJ25

CL_VREF0
CL_VREF1

& lt; 26 & gt;
& lt; 26 & gt;
& lt; 26 & gt;
& lt; 26 & gt;

PCIE_PTX_C_IRX_N4
PCIE_PTX_C_IRX_P4
PCIE_ITX_C_PRX_N4
PCIE_ITX_C_PRX_P4

R330
R330
3.24K_0402_1%

CK_PWRGD & lt; 16 & gt;

CL_VREF0_ICH

1 0.1U_0402_16V7K
1 0.1U_0402_16V7K

& lt; 31 & gt;
& lt; 31 & gt;
& lt; 31 & gt;
& lt; 31 & gt;

+3V_SB

PWROK

CL_DATA0
CL_DATA1

NEWCARD@ C344 2
NEWCARD@ C345 2

R950
R950 100K_0402_5%
CIR_EN#
1
2

C871
22P_0402_50V8J
@

2

RSMRST# & lt; 29 & gt;

CK_PWRGD

SLP_M#

PCIE_PTX_C_IRX_N1
PCIE_PTX_C_IRX_P1
PCIE_ITX_C_PRX_N1
PCIE_ITX_C_PRX_P1

WLAN@
WLAN@

2

PLT_RST# & lt; 8,20,26,30,31 & gt;

E3

CL_CLK0
CL_CLK1

& lt; 30 & gt;
& lt; 30 & gt;
& lt; 30 & gt;
& lt; 30 & gt;

H_STP_PCI#

10K_0402_5%
R799
R799 1
2

& lt; 8,29 & gt;

PBTN_OUT# & lt; 29 & gt;

RSMRST#

CLPWROK

PCIE_PTX_C_IRX_N1
PCIE_PTX_C_IRX_P1
PCIE_ITX_PRX_N1
PCIE_ITX_PRX_P1

NEW Card

1
C870
22P_0402_50V8J
@

DPRSLPVR & lt; 8,43 & gt;

AH20
AG27

PWROK

CK_PWRGD

LAN

10K_0402_5%
R797
R797 1
2

C2

LAN_RST#

U10D
SATA

R711
10_0402_5%
@

PM_BATLOW#

SB_SPKR

8.2K_0402_5%
R650
R650 1
2

2

AH27
AE23

RSMRST#

TACH1/GPIO1
TACH2/GPIO6
TACH3/GPIO7
GPIO8
GPIO12
TACH0/GPIO17
GPIO18
GPIO20
SCLOCK/GPIO22
QRT_STATE0/GPIO27
QRT_STATE1/GPIO28
SATACLKREQ#/GPIO35
SLOAD/GPIO38
SDATAOUT0/GPIO39
SDATAOUT1/GPIO48

R710
10_0402_5%
@

PM_SLP_S3# & lt; 29 & gt;
1

S4_STATE#/GPIO26

TP7

AJ13

& lt; 8 & gt; MCH_ICH_SYNC#

MCH_ICH_SYNC#

AJ20

CLK_48M_ICH

2

10K_0402_5%
R796
R796 1
2

EC_SMI#
EC_SCI#

& lt; 34 & gt; SB_Sattlate_LED#

PM_CLKRUN#

WAKE#
SERIRQ
THRM#

OCP#
AJ8
ACIN_D
AJ9
1
2
D52
D52
RB751V_SOD323 AH9
EC_SMI#
AE16
EC_SCI#
AC19
AG8
AH12
2HDD_DET#
AE11
BT_DET#
AG10
AH25
AD16
SATA_CLKREQ#
AG13
AF9
CIR_EN#
AJ11
AD10

& lt; 4 & gt;
OCP#
& lt; 29,36,38 & gt; PACIN
& lt; 29 & gt;
& lt; 29 & gt;

CLKRUN#/GPIO32

AE17
AF12
AC13

AJ22

PAD

PM_SLP_S3#
SLP_S4#
SLP_S5#

CLK_14M_ICH

1

T34
T34

EC_THERM#

10K_0402_5%
R331
R331 1
2

AH11

1 ICH_VGATE
0_0402_5%

SUS_CLK

AG23
AF21
AD18

D

CLK_14M_ICH & lt; 16 & gt;
CLK_48M_ICH & lt; 16 & gt;

1

@ 10K_0402_5%
R316 1
2

STP_PCI#/GPIO15
STP_CPU#/GPIO25

2
R324
R324

D3

SLP_S3#
SLP_S4#
SLP_S5#

PM_SLP_S5# & lt; 29 & gt;

3

R608
R608 1
2
8.2K_0402_5%
10K_0402_5%
R309
R309 1
2

SMBALERT#/GPIO11

AE20
AG18

EC_SWI#
SERIRQ
EC_THERM#

& lt; 29,43 & gt; VGATE

FOR 2ND HDD DETECTION
1: SINGLE HDD
0: DUAL HDD
10K_0402_5%
R861
R861 1
2

AG22

H_STP_PCI#
H_STP_CPU#

& lt; 29,30,31 & gt; EC_SWI#
& lt; 24,29,35 & gt; SERIRQ
& lt; 29 & gt; EC_THERM#

SUSCLK

BMBUSY#/GPIO0

PM_CLKRUN#

CLK_14M_ICH
CLK_48M_ICH

3

1

10K_0402_5%
EC_LID_OUT#
2

AG12

EC_LID_OUT#

& lt; 16 & gt; H_STP_PCI#
& lt; 16 & gt; H_STP_CPU#

R332
R332 100K_0402_5%
R333 1K_0402_1%
2HDD_DET#
1
2
1
2
2HDD@

B

PM_BMBUSY#

& lt; 29 & gt; EC_LID_OUT#

+3VS

C

SUS_STAT#/LPCPD#
SYS_RESET#

B

SN74LVC08APW_TSSOP14

AG9
G5

CLK14
CLK48

clocks

U13A
O

2

SATA

AJ12
AJ10
AF11
AG11

Direct Media Interface

1K_0402_1%
EC_SWI#
2

R607
R607 1

F4
AD15

ITP_DBRESET#

& lt; 8 & gt; PM_BMBUSY#

10K_0402_5%
ITP_DBRESET#
2

R323
R323 1

RI#

& lt; 4 & gt; ITP_DBRESET#

RI#

R322
R322 1

AF17

PCI - Express

10K_0402_5%
2

RI#

SATA0GP/GPIO21
SATA1GP/GPIO19
SATA2GP/GPIO36
SATA3GP/GPIO37

SPI

R317
R317 1

LINKALERT#
ICH_SMLINK0
ICH_SMLINK1

SMBCLK
SMBDATA
LINKALERT#
SMLINK0
SMLINK1

A

14

10K_0402_5%
ICH_SMLINK1
2

SLP_S4#

AJ26
AD19
AG21
AC17
AE19

SATA
GPIO

R319
R319 1

1

P

10K_0402_5%
ICH_SMLINK0
2

ICH_SMBCLK
ICH_SMBDATA

& lt; 16,30,31 & gt; ICH_SMBCLK
& lt; 16,30,31 & gt; ICH_SMBDATA

Power MGT

R318
R318 1

D

10K_0402_5%
LINKALERT#
2

SLP_S5#
U10C

SMB

R320
R320 1

1

0.1U_0402_16V4Z

SYS / GPIO

R335
R335 1

2.2K_0402_5%
ICH_SMBDATA
2

MISC
GPIO
Controller Link

R314
R314 1

C342
C342 2

2.2K_0402_5%
ICH_SMBCLK
2

G

+3V_SB

2

Compal Electronics, Inc.
ICH8-M(3/4)
Document Number

Rev
2.0

LA-3481P
Sheet

Saturday, June 23, 2007
1

22

of

47

5

+3VS

2

2

+5V_SB +3V_SB

D14
D14

1

RB751V_SOD323

2

1

+ICH_V5REF_SUS
C363
C363
0.1U_0402_16V4Z
+1.5VS_PCIE_ICH

(220UF*1, 22UF*2, 2.2UF*1)

+1.5VS

L33
L33 2
1
KC FBM-L11-201209-221LMAT_0805
1
C365

+

C366
C366

1

C367
C367

1

C368

220U_D2_2VMR15
22U_0805_6.3V6M
2
2
2
22U_0805_6.3V6M 2.2U_0603_6.3V6K

+1.5VS_SATAPLL_R

R347
1_0603_1%

L34
L34 1
2
MBK1608121YZF_0603
1
C372
C372

+1.5VS

+1.5VS_SATAPLL_ICH

2

(10UF*1, 1UF*1)

10U_0805_10V4Z

C

C373

1U_0603_10V4Z

C380
C380

C381

1U_0603_10V4Z
1U_0603_10V4Z

close to AC1

AC10
AC9

C384
C384

1

C385
C385

AC7
AD7

0.1U_0402_16V4Z
2
2
0.1U_0402_16V4Z

2
0.1U_0402_16V4Z

2

2.2U_0603_6.3V6K

C392
C392

(10UF*1, 1UF*1)

10U_0805_10V4Z

R352
1_0603_1%

+VCC_GLANPLL_R 1
+VCC_GLANPLL_ICH
2
MBK1608121YZF_0603 1
L35
L35
C393

+1.5VS_PCIE_ICH
C394

(220UF*1, 1UF*1) 4.7U_0805_10V4Z

F17
G18

VCCLAN1_05[1]
VCCLAN1_05[2]

F19
G20

TP_VCCLAN1_05_ICH_1
TP_VCCLAN1_05_ICH_2

PAD
PAD

VCC1_5_A[25]

VCCLAN3_3[1]
VCCLAN3_3[2]

A24

VCCGLANPLL

A26
A27
B26
B27
B28

VCCGLAN1_5[1]
VCCGLAN1_5[2]
VCCGLAN1_5[3]
VCCGLAN1_5[4]
VCCGLAN1_5[5]

B25

22U_0805_6.3V6M
2

R29
AE28
AE29
AC23
AC24
AF29
AD2

VCC3_3[03]
VCC3_3[04]
VCC3_3[05]
VCC3_3[06]

AC8
AD8
AE8
AF8

VCC3_3[07]
VCC3_3[08]
VCC3_3[09]
VCC3_3[10]
VCC3_3[11]
VCC3_3[12]
VCC3_3[13]

AA3
U7
V7
W1
W6
W7
Y7

VCC3_3[14]
VCC3_3[15]
VCC3_3[16]
VCC3_3[17]
VCC3_3[18]
VCC3_3[19]
VCC3_3[20]
VCC3_3[21]
VCC3_3[22]
VCC3_3[23]
VCC3_3[24]

A8
B15
B18
B4
B9
C15
D13
D5
E10
E7
F11

+1.05VS
C369
C369

C370
C370

1

1

C371
C371

(4.7UF*1, 0.1UF*2)

4.7U_0805_10V4Z

0.1U_0402_16V4Z
2
2
0.1U_0402_16V4Z

close to AD2
+3VS
C374
C374

1

C375
C375

1

C376
C376

1

0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
2
0.1U_0402_16V4Z

close to AF29

close to AA3
+3VS

C377
C377

1

C378
C378

1

C379
C379

+VCC_HDA_ICH

1

R348
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
2
0.1U_0402_16V4Z

C382
C382

0_0603_1%

+3VS

1

0.1U_0402_16V4Z
2
+VCCSUS_HDA_ICH

AC12
AD11

R350

TP_VCCSUS1_05_ICH_1
J6
AF20 TP_VCCSUS1_05_ICH_2

PAD
PAD

T35
T35
T36
T36

AC16 TP_VCCSUS1_5_ICH_1

PAD

T37
T37

TP_VCCSUS1_5_ICH_2

PAD

0_0603_1%

+3V_SB

1

T38
T38

J7

AC18
AC21
AC22
AG20
AH28

VCCSUS3_3[07]
VCCSUS3_3[08]
VCCSUS3_3[09]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]
VCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]

P6
P7
C1
N7
P1
P2
P3
P4
P5
R1
R3
R5
R6

0.1U_0402_16V4Z
2

C3

VCCSUS3_3[02]
VCCSUS3_3[03]
VCCSUS3_3[04]
VCCSUS3_3[05]
VCCSUS3_3[06]

C383
C383

+3V_SB
C386
C386

C387
C387

1

C388
C388

1

A23
A5
AA2
AA7
A25
AB1
AB24
AC11
AC14
AC25
AC26
AC27
AD17
AD20
AD28
AD29
AD3
AD4
AD6
AE1
AE12
AE2
AE22
AD1
AE25
AE5
AE6
AE9
AF14
AF16
AF18
AF3
AF4
AG5
AG6
AH10
AH13
AH16
AH19
AH2
AF28
AH22
AH24
AH26
AH3
AH4
AH8
AJ5
B11
B14
B17
B2
B20
B22
B8
C24
C26
C27
C6
D12
D15
D18
D2
D4
E21
E24
E4
E9
F15
E23
F28
F29
F7
G1
E2
G10
G13
G19
G23
G25
G26
G27
H25
H28
H29
H3
H6
J1
J25
J26
J27
J4
J5
K23
K28
K29
K3
K6

VCCCL1_05

0.1U_0402_16V4Z
2
2
0.1U_0402_16V4Z

close to P6

G22 TP_VCCCL1_05_ICH

VCCCL1_5

A22

VCCCL3_3[1]
VCCCL3_3[2]

F20
G21

ICH8M_BGA676~D
ICH8MR3@

+3VS

4.7U_0805_10V4Z

1
C895

(0.1UF*1, 0.022UF*2)

close to AC18

K7
L1
L13
L15
L26
L27
L4
L5
M12
M13
M14
M15
M16
M17
M23
M28
M29
M3
N1
N11
N12
N13
N14
N15
N16
N17
N18
N26
N27
N4
N5
N6
P12
P13
P14
P15
P16
P17
P23
P28
P29
R11
R12
R13
R14
R15
R16
R17
R18
R28
R4
T12
T13
T14
T15
T16
T17
T2
U12
U13
U14
U15
U16
U17
U23
U26
U27
U3
U5
V13
V15
V28
V29
W2
W26
W27
Y28
Y29
Y4
AB4
AB23
AB5
AB6
AD5
U4
W24

VSS_NCTF[01]
VSS_NCTF[02]
VSS_NCTF[03]
VSS_NCTF[04]
VSS_NCTF[05]
VSS_NCTF[06]
VSS_NCTF[07]
VSS_NCTF[08]
VSS_NCTF[09]
VSS_NCTF[10]
VSS_NCTF[11]
VSS_NCTF[12]

PAD

T41
T41

A1
A2
A28
A29
AH1
AH29
AJ1
AJ2
AJ28
AJ29
B1
B29

D

C

B

ICH8M_BGA676~D
ICH8MR3@

2
@ 1U_0402_6.3V4Z

Compal Secret Data

Security Classification
2006/08/05

Issued Date

Deciphered Date

2007/08/05

Title

Date:

4

A

+3VS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]

VSS[001]
VSS[002]
VSS[003]
VSS[004]
VSS[005]
VSS[006]
VSS[007]
VSS[008]
VSS[009]
VSS[010]
VSS[011]
VSS[012]
VSS[013]
VSS[014]
VSS[015]
VSS[016]
VSS[017]
VSS[018]
VSS[019]
VSS[020]
VSS[021]
VSS[022]
VSS[023]
VSS[024]
VSS[025]
VSS[026]
VSS[027]
VSS[028]
VSS[029]
VSS[030]
VSS[031]
VSS[032]
VSS[033]
VSS[034]
VSS[035]
VSS[036]
VSS[037]
VSS[038]
VSS[039]
VSS[040]
VSS[041]
VSS[042]
VSS[043]
VSS[044]
VSS[045]
VSS[046]
VSS[047]
VSS[048]
VSS[049]
VSS[050]
VSS[051]
VSS[052]
VSS[053]
VSS[054]
VSS[055]
VSS[056]
VSS[057]
VSS[058]
VSS[059]
VSS[060]
VSS[061]
VSS[062]
VSS[063]
VSS[064]
VSS[065]
VSS[066]
VSS[067]
VSS[068]
VSS[069]
VSS[070]
VSS[071]
VSS[072]
VSS[073]
VSS[074]
VSS[075]
VSS[076]
VSS[077]
VSS[078]
VSS[079]
VSS[080]
VSS[081]
VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]

VCCGLAN3_3

GLAN POWER

+1.5VS

T39
T40
T40

+1.25VS

VCCSUS1_5[2]

USB CORE

C389
C389

1

VCC1_5_A[20]
VCC1_5_A[21]
VCC1_5_A[22]
VCC1_5_A[23]
VCC1_5_A[24]

+1.5VS

(22UF*1, 0.1UF*1)

1

VCCSUS1_05[1]
VCCSUS1_05[2]

VCCUSBPLL

1_0603_1%

(10UF*1, 0.01UF*1)

C362

C364
C364

VCCHDA

VCC1_5_A[18]
VCC1_5_A[19]

W23

close to D1

2

R345

0.01U_0402_25V7K

VCCSUS3_3[01]

F1
L6
L7
M6
M7

+3VS

+1.5VS_DMIPLL_R

VCCSUS1_5[1]

D1

close to F1

1

VCCSUSHDA

VCC1_5_A[15]
VCC1_5_A[16]
VCC1_5_A[17]

1

(47UF*1, 0.047UF*1, 0.022UF*1)

1

L32
L32 1
2
MBK1608121YZF_0603

VCC3_3[02]

VCC1_5_A[13]
VCC1_5_A[14]

G12
G17
H7

+1.5VS

C359
C359

+1.5VS_DMIPLL_ICH

VCC3_3[01]

VCC1_5_A[11]
VCC1_5_A[12]

AA5
AA6

B

A

VCC1_5_A[06]
VCC1_5_A[07]
VCC1_5_A[08]
VCC1_5_A[09]
VCC1_5_A[10]

1

0.1U_0402_16V4Z
2
2
0.1U_0402_16V4Z

V_CPU_IO[1]
V_CPU_IO[2]

ATX

close to AE7

AC1
AC2
AC3
AC4
AC5

C358
C358

VCCDMIPLL

VCCSATAPLL
VCC1_5_A[01]
VCC1_5_A[02]
VCC1_5_A[03]
VCC1_5_A[04]
VCC1_5_A[05]

+1.05VS

VCC_DMI[1]
VCC_DMI[2]

ARX

AJ6
AE7
AF7
AG7
AH7
AJ7

+1.5VS

VCCA3GP

10_0402_5%
1

R346
R346

VCC1_5_B[01]
VCC1_5_B[02]
VCC1_5_B[03]
VCC1_5_B[04]
VCC1_5_B[05]
VCC1_5_B[06]
VCC1_5_B[07]
VCC1_5_B[08]
VCC1_5_B[09]
VCC1_5_B[10]
VCC1_5_B[11]
VCC1_5_B[12]
VCC1_5_B[13]
VCC1_5_B[14]
VCC1_5_B[15]
VCC1_5_B[16]
VCC1_5_B[17]
VCC1_5_B[18]
VCC1_5_B[19]
VCC1_5_B[20]
VCC1_5_B[21]
VCC1_5_B[22]
VCC1_5_B[23]
VCC1_5_B[24]
VCC1_5_B[25]
VCC1_5_B[26]
VCC1_5_B[27]
VCC1_5_B[28]
VCC1_5_B[29]
VCC1_5_B[30]
VCC1_5_B[31]
VCC1_5_B[32]
VCC1_5_B[33]
VCC1_5_B[34]
VCC1_5_B[35]
VCC1_5_B[36]
VCC1_5_B[37]
VCC1_5_B[38]
VCC1_5_B[39]
VCC1_5_B[40]
VCC1_5_B[41]
VCC1_5_B[42]
VCC1_5_B[43]
VCC1_5_B[44]
VCC1_5_B[45]
VCC1_5_B[46]

A13
B13
C13
C14
D14
E14
F14
G14
L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18

10U_0805_10V4Z

C360
1U_0402_6.3V4Z

V5REF_SUS

VCC1_05[01]
VCC1_05[02]
VCC1_05[03]
VCC1_05[04]
VCC1_05[05]
VCC1_05[06]
VCC1_05[07]
VCC1_05[08]
VCC1_05[09]
VCC1_05[10]
VCC1_05[11]
VCC1_05[12]
VCC1_05[13]
VCC1_05[14]
VCC1_05[15]
VCC1_05[16]
VCC1_05[17]
VCC1_05[18]
VCC1_05[19]
VCC1_05[20]
VCC1_05[21]
VCC1_05[22]
VCC1_05[23]
VCC1_05[24]
VCC1_05[25]
VCC1_05[26]
VCC1_05[27]
VCC1_05[28]

C361
C361

2

G4
AA25
AA26
AA27
AB27
AB28
AB29
D28
D29
E25
E26
E27
F24
F25
G24
H23
H24
J23
J24
K24
K25
L23
L24
L25
M24
M25
N23
N24
N25
P24
P25
R24
R25
R26
R27
T23
T24
T27
T28
T29
U24
U25
V23
V24
V25
W25
Y25

CORE

1

+ICH_V5REF

V5REF[1]
V5REF[2]

VCCP_CORE

100_0402_5%
1

0.1U_0402_16V4Z
2
+ICH_V5REF_SUS
1U_0603_10V4Z

A16
T7

IDE

+ICH_V5REF

PCI

C357
C357

RB751V_SOD323

1

1

U10E

VCCRTC

VCCPSUS

2

2

C356

1

D13
D13

D

2

U10F
AD25

+RTCVCC
R344

3

VCCPUSB

+5VS

4

3

2

Compal Electronics, Inc.
ICH8-M(4/4)
Document Number

Rev
2.0

LA-3481P
Sheet

Monday, May 28, 2007
1

23

of

47

5

4

+3VS

3

2

+3VS

1

C397
C397

2

1

2

0.01U_0402_25V7K
C400
C400
1
2 VSSPLL
0.1U_0402_16V4Z

1

C398
C398

PCI8412:6IN1 + 1394 + CardBus
PCI8402:6IN1 + 1394

0.1U_0402_16V4Z
2

2

0.1U_0402_16V4Z

C399
C399

4.7U_0805_10V4Z
+3VS

470_0805_5%

D

2
1U_0603_10V4Z
0.1U_0402_16V4Z
1

P1
W8

K1
K19

VCCP
VCCP

MS_CLK/SD_CLK/SM_EL_WP#
MS_BS/SD_CMD/SM_WE#
MS_DATA3/SD_DAT3/SM_D3
MS_DATA2/SD_DAT2/SM_D2
MS_DATA1/SD_DAT1/SM_D1
MS_SDIO(DATA0)/SD_DAT0/SM_D0

A4
C5
C6
A5
B5
E6
E7

SD_CLK/SM_RE#
SD_CMD/SM_ALE
SD_DAT0/SM_D4
SD_DAT1/SM_D5
SD_DAT2/SM_D6
SD_DAT3/SM_D7
SD_WP/SM_CE#

G5

SMELWP#

R360 1
2
33_0402_5%

SMRE
SDCMD_SMALE
SDD0_SMD4
SDD1_SMD5
SDD2_SMD6
SDD3_SMD7
SDWP#_SMCE#

place near Chip 8412
SMCLE
XD_CD#

SM_CLE
XD_CD#/SM_PHYS_WP#

R364 1
& lt; 16 & gt; CLK_48M_CB

B

AMP_440168-2

2

1
2

1
2
1

2 1K_0402_1% P12
F1
P17
2 4.7K_0402_5%

R365
R365 1

R368
56.2_0603_1%

4
3
2
1

R367
56.2_0603_1%

5
6
7
8

R379
R371
5.1K_0603_1% 56.2_0603_1%
2
1
2
1

1
JP10

C419
R370
220P_0402_50V7K 56.2_0603_1%
2
1

2

C417
1U_0603_10V4Z

+3VS

6.34K_0402_1%
T18
2
T19
XTPBIAS0
R13
XTPA0+
V14
XTPA0W14
XTPB0+
V13
XTPB0W13
W17
2
1U_0603_10V4Z
V16
W16
2 1K_0402_1% V15
2 1K_0402_1%W15
CPS
R12

PCI7412

1

1

R373 1
R374 1

X_OUT R18
X_IN
R19

L1
K3
K5
L5

SUSPEND#

J5

SPKROUT

SCL
SDA

VSSPLL

1

6 In 1 Card Power Switch

5IN1_LED

D
Q8
2N7002_SOT23-3

2
G

R354
R354
10K_0402_5%

+VCC_5IN1
C

R363
R363
10K_0402_5%

S
MC_PWRON#

U15
1
2
3
4

GND
IN
IN
EN#

2

C872
C872
22P_0402_50V8J

SMELWP#

PCI_PAR & lt; 20 & gt;
PCI_FRAME# & lt; 20 & gt;
PCI_TRDY# & lt; 20 & gt;
PCI_IRDY# & lt; 20 & gt;
PCI_STOP# & lt; 20 & gt;
DEVICE_ID
PCI_DEVSEL# & lt; 20 & gt;

PCI_AD20

PCI_PERR#
PCI_SERR#
PCI_REQ#2
PCI_GNT#2

R601
R601
10K_0402_5%

MSCLK_SDCLK2

C416
C416

C415
2

MSCLK_SDCLK1

R715
@ 4.7_0402_5%

8412@

R714
@ 4.7_0402_5%

1

& lt; 20 & gt;
& lt; 20 & gt;
& lt; 20 & gt;
& lt; 20 & gt;

R602
100_0402_5%
8402@

R713
@ 4.7_0402_5%

CLK_PCI_PCM & lt; 16 & gt;
PCI_RST# & lt; 20,29,35 & gt;

2

1
C877
@1P_0402_50V8C

2

1
C875
@1P_0402_50V8C

For EMI
6 in 1 CardReader Conn.

2

C873
@1P_0402_50V8C

JP11
R372
1
2
43K_0402_5%

+VCC_5IN1

PIRQA
PIRQB
PIRQC

R375
R376
R377
R378

1
2
2
2

2
1
1
1

DEVICE_ID
5IN1_LED

1
R383
1 R383
R384
R384

2
R381
R381
2
2 300_0402_5%
300_0402_5%

1
10K_0402_5%

+3VS

1

XD-D0
XD-D1
XD-D2
XD-D3
XD-D4
XD-D5
XD-D6
XD-D7

30
31
29
23
25
26
27
28

XD-WE
XD-WP
XD-ALE
XD-CD
XD-R/B
XD-RE
XD-CE
XD-CLE

32
24

PCI_PIRQA# & lt; 20 & gt;
PCI_PIRQB# & lt; 20 & gt;
PCI_PIRQC# & lt; 20 & gt;
SERIRQ & lt; 22,29,35 & gt;

XD-VCC

33
34
35
36
37
38
39
40

MSBS_SDCMD_SMWE#
SMELWP#
SDCMD_SMALE
XD_CD#
SM_RB
SMRE
SDWP#_SMCE#
SMCLE

PCM_SPK & lt; 27 & gt;

43K_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%

41

MSD0_SDD0_SMD0
MSD1_SDD1_SMD1
MSD2_SDD2_SMD2
MSD3_SDD3_SMD3
SDD0_SMD4
SDD1_SMD5
SDD2_SMD6
SDD3_SMD7

+3VS

XD-GND
XD-GND

C421
C421
0.1U_0402_16V4Z

2

42
18

SD-VCC
MS-VCC

4 IN 1 CONN
IN

N.C.
N.C.

PIRQA
PIRQB
PIRQC

R729
R729
10_0402_5%

R387 2
R388 2
R389 2

@
@
@

1 0_0402_5%
1 0_0402_5%
1 0_0402_5%

15
9

SD_CLK
SD-DAT0
SD-DAT1
SD-DAT2
SD-DAT3
SD-CMD
SD-CD-SW
SD-CD-COM
SD-WP-SW
SD-WP-COM

16
19
20
11
12
13
21
22
43
44

MS-SCLK
MS-DATA0
MS-DATA1
MS-DATA2
MS-DATA3
MS-INS
MS-BS
SD-GND
SD-GND
MS-GND
MS-GND

8
4
3
5
7
6
2
14
17
1
10

2

MSCLK_SDCLK2
MSD0_SDD0_SMD0
MSD1_SDD1_SMD1
MSD2_SDD2_SMD2
MSD3_SDD3_SMD3
MS_CD#
MSBS_SDCMD_SMWE#

SDWP#_SMCE#

A

Bottom Side, Normal Insertion

C878
C878
22P_0402_50V8J

Compal Secret Data
2006/08/05

1

Issued Date

2007/08/05

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

3

B

MSCLK_SDCLK1
MSD0_SDD0_SMD0
MSD1_SDD1_SMD1
MSD2_SDD2_SMD2
MSD3_SDD3_SMD3
MSBS_SDCMD_SMWE#
SD_CD#

+VCC_5IN1

PCI_PIRQE# & lt; 20 & gt;
PCI_PIRQF# & lt; 20 & gt;
PCI_PIRQG# & lt; 20 & gt;

Date:

5

1

C414
C414
0.1U_0402_16V4Z

4.7U_0805_10V4Z
1U_0603_10V4Z
+5VS

Security Classification
X_IN

C422
C422

8
7
6
5

1

X2
24.576MHz_16P_3XG-24576-43E1
18P_0402_50V8J

OUT
OUT
OUT
FLG

G528_SO8

1
X_OUT

C420

2
22K_0402_5%

1

1

2

18P_0402_50V8J

1

CLOSE TO CHIP

1
R359

D15
+3VS

2

2

A

2
100K_0402_5%

SM_RB

TAITW_R007-530-L3
CLK_PCI_PCM

2
100K_0402_5%

1
R357

HT-191NB_BLUE_0603

R385
1K_0402_1%

R712
33_0402_5%

1
R356

120_0402_5%
R353
R353

CLK_PCI_PCM
PCI_RST#

VSSPLL

CLK_48M_CB

2
100K_0402_5%

SDWP#_SMCE#

+5VS

1
R355

SMRE

6 IN 1 LED

K2

PCI7412ZHK_PBGA257

R17

AGND
AGND
AGND
R14
U13
U14

8412@

G2
G3

VR_EN#

XO
XI

G1
H5
H2
H1
J1
J2
J3

+VCC_5IN1

C411
1U_0603_10V4Z

MSBS_SDCMD_SMWE#

R366
R366
100_0402_5%

H3

MFUNC0
MFUNC1
MFUNC2
MFUNC3
MFUNC4
MFUNC5
MFUNC6

+3VS

R382
R382 1
2 CPS
4.7K_0402_5%

U7
R6
W5
V5
V6
U6
N5
R7
W6
L3
L2

PCLK
PRST#
GRST#
RI_OUT#/PME#

R0
R1
TPBIAS0
TPA0P
TPA0N
TPB0P
TPB0N
TPBIAS1
TPA1P
TPA1N
TPB1P
TPB1N
CPS

1

PCI_CBE#3
PCI_CBE#2
PCI_CBE#1
PCI_CBE#0

PAR
FRAME#
TRDY#
IRDY#
STOP#
DEVSEL#
IDSEL
PERR#
SERR#
REQ#
GNT#

TEST0
CLK_48
PHY_TEST_MA

R369

C418

P2
U5
V7
W10

SC_PWR_CTRL

B4
A3

C

2
0.01U_0402_25V7K

22

A7
E8
B6
A6
C7
B7

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0

C/BE3#
C/BE2#
C/BE1#
C/BE0#

SD_CD#
MS_CD#
SM_CD#

2

2

MSCLK_SDCLK2 2
R874 1
33_0402_5%

MC_PWR_CTRL_0
MC_PWR_CTRL_1/SM_R/B#

M1
M2
M3
M6
M5
N1
N2
N3
P3
R1
R2
P5
R3
T1
T2
W4
W7
R8
U8
V8
W9
V9
U9
R9
V10
U10
R10
W11
V11
U11
P11
R11

2
0.1U_0402_16V4Z

2
C410
C410

11

MSCLK_SDCLK_SMELWP#
MSBS_SDCMD_SMWE#
MSD3_SDD3_SMD3
MSD2_SDD2_SMD2
MSD1_SDD1_SMD1
MSD0_SDD0_SMD0

AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0

1

C409
C409

2

MSCLK_SDCLK1 2
R358 1
33_0402_5%

E9
A8
B8

2

C408
C408

1

SD_CD#
MS_CD#

C8
F8

1

C407
C407

2

MC_PWRON#
SM_RB

VR_PORT
VR_PORT

AVDD_33
AVDD_33
AVDD_33

U14B

VDDPLL_33
VDDPLL_15

3

P13
P14
U15

U19
P15

Q9
MC_PWRON#
2
2N7002_SOT23-3
G
S

0.01U_0402_25V7K
1

2

D

3

1
C406

12

D

C424
C423

0.1U_0402_16V4Z

1

R386
R386

2

1

C396
C396

2

2

0.01U_0402_25V7K

1

1

2

1

GND
GND

C404
C404

47
48

2

1

2

2

C403
C403

1

1

2

2

1

0.1U_0402_16V4Z

1

1

+VCC_5IN1

C402
C402

L36

1

1

C401
C401

+3VS

CHB1608U301_0603
1
2

0.01U_0402_25V7K

C395
C395

L37

0.01U_0402_25V7K

C405
C405

0.1U_0402_16V4Z

10U_0805_10V4Z

CHB1608U301_0603
2
1

PCI_CBE#[0..3]

10U_0805_10V4Z

PCI_AD[0..31]

& lt; 20 & gt; PCI_AD[0..31]
& lt; 20 & gt; PCI_CBE#[0..3]

1

+AVDD_7412

2

Compal Electronics, Inc.
TI PCI8412 PCI/1394/5IN1
Document Number

Rev
2.0

LA-3481P
Sheet

Tuesday, May 22, 2007
1

24

of

47

5

4

3

2

1

CardBus Power Switch
+S1_VCC

U16

+S1_VCC

0.1U_0402_16V4Z
0.1U_0402_16V4Z
PCMCIA@ C430
C431
C431

C432
C432

C433
C433

C434
C434

+5VS
5
6

C435

S1_CD1#
1
100P_0402_50V8J

CCD1#/CD1#
CCD2#/CD2#
CVS1/VS1#
CVS2/VS2#

E10

A_USB_EN#

S1_CD2#
1
100P_0402_50V8J

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

PCMCIA@
2
C443

D

VCCD0#
VCCD1#
VPPD0
VPPD1

8

TPS2211AIDBR_SSOP16
PCMCIA@

1

CAUDIO/BVD2(SPKR#)

N15
B11
A13
B16

F7
F10
F13
G14
H6
K6
K14
M14
N6
P7
P9

PCMCIA@

JP12
2

VCCD1#
+3VS

A2
A17
A18
B1
B2
B3
B17
B18
B19
C1
C2
C3
C16
C17
C18
C19
D2
D3
D17
D18
E5
N14
P18
T3
T17
U1
U2
U3
U4
U12
U16
U17
U18
V1
V2
V3
V4
V12
V17
V18
V19
W2
W3
W12
W18

1

0_0402_5%
1

R393
43K_0402_5%

PCMCIA@

Near to PCMCIA slot.
+S1_VCC

1

2

10U_0805_10V4Z

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

B10 S1_D2
C4
D1
E1
E2
E3
F2
F3
R394
F5
G6
2
H17 S1_A18
M19 S1_D14

C438

PCI
PCI 7412

CRST#/RESET

B12

S1_CD1#
S1_CD2#
S1_VS1
S1_VS2

2
C442

C15

S1_BVD2

RSVD/D2
RSVD/VD0/VCCD1#
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

1

C439

0.1U_0402_16V4Z
2 PCMCIA@

PCMCIA@

+S1_VPP

1

2

10U_0805_10V4Z

S1_A16_C

OC

1
2@
C425 0.1U_0402_16V4Z
@
C426 0.1U_0402_16V4Z
1
2@
C427 10U_0805_10V4Z
+S1_VPP
1
2
C428 0.01U_0402_25V7K
20mil
@
C429
1U_0603_10V4Z
@

40mil

PCM_DISABLE# & lt; 22 & gt;

C440

B

R391
10K_0402_5%
PCMCIA@

3.3V
3.3V

SHDN

CPAR/A13
CFRAME#/A23
CTRDY#/A22
CIRDY#/A15
CSTOP#/A20
CDEVSEL#/A21
CBLOCK#/A19
CPERR#/A14
CSERR#/WAIT#
CREQ#/INPACK#
CGNT#/WE#
CSTSCHG/BVD1(STSCHG#/RI#)
CCLKRUN#/WP(IOIS16#)
CCLK/A16
CINT#/READY(IREQ#)

VPPD1
VCCD0#
VPPD0

B9
A9
C9

3
4

GND

H14
E19
G15
F17
G18
F19
H15
G19
C12
C14
G17
A12
A11
F18
E12

S1_A13
S1_A23
S1_A22
S1_A15
S1_A20
S1_A21
S1_A19
S1_A14
S1_WAIT#
S1_INPACK#
S1_WE#
S1_BVD1
R395
S1_WP
1
2 S1_A16
33_0402_5% S1_RDY#
PCMCIA@
S1_RST

DATA/VD2/VPPD1
CLOCK/VD1/VCCD0#
LATCH/VD3/VPPD0

4.7U_0805_10V4Z

7

CC/BE3#/REG#
CC/BE2#/A12
CC/BE1#/A8
CC/BE0#/CE1#

C437@

+3VS
0.1U_0402_16V4Z

2

E13
E18
H18
L17

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

S1_REG#
S1_A12
S1_A8
S1_CE1#

C

CAD31/D10
CAD30/D9
CAD29/D1
CAD28/D8
CAD27/D0
CAD26/A0
CAD25/A1
CAD24/A2
CAD23/A3
CAD22/A4
CAD21/A5
CAD20/A6
CAD19/A25
CAD18/A7
CAD17/A24
CAD16/A17
CAD15/IOWR#
CAD14/A9
CAD13/IORD#
CAD12/A11
CAD11/OE#
CAD10/CE2#
CAD9/A10
CAD8/D15
CAD7/D7
CAD6/D13
CAD5/D6
CAD4/D12
CAD3/D5
CAD2/D11
CAD1/D4
CAD0/D3

PCMCIA@
C436
C436

F6
F9
F12
F14
J6
J14
L6
L14
P6
P8
P10

A15
J19
VCCB
VCCB

U14A

0.1U_0402_16V4Z

16

0.1U_0402_16V4Z

C10
A10
F11
E11
C11
B13
C13
A14
B14
B15
E14
A16
D19
E17
F15
H19
J17
J15
J18
K15
K17
K18
L15
L18
L19
M17
M18
N19
M15
N17
N18
P19

1
2
15
14

5V
5V

@ 4.7U_0805_10V4Z

S1_D10
S1_D9
S1_D1
S1_D8
S1_D0
S1_A0
S1_A1
S1_A2
S1_A3
S1_A4
S1_A5
S1_A6
S1_A25
S1_A7
S1_A24
S1_A17
S1_IOWR#
S1_A9
S1_IORD#
S1_A11
S1_OE#
S1_CE2#
S1_A10
S1_D15
S1_D7
S1_D13
S1_D6
S1_D12
S1_D5
S1_D11
S1_D4
S1_D3

10

VCCD0
VCCD1
VPPD0
VPPD1

12V

13
12
11

+3VS

D

0.1U_0402_16V4Z
PCMCIA@

VCC
VCC
VCC

VPP

9

1

C441

0.1U_0402_16V4Z
2 PCMCIA@

PCMCIA@

85
86
87
88

PCI7412ZHK_PBGA257
69
70

A

GND
GND
DATA3
CD1#
DATA4
DATA11
DATA5
DATA12
DATA6
DATA13
DATA7
DATA14
CE1#
DATA15
ADD10
CE2#
OE#
VS1#
ADD11
IORD#
ADD9
IOWR#
ADD8
ADD17
ADD13
ADD18
ADD14
ADD19
WE#
ADD20
READY
ADD21
VCC
VCC
VPP
VPP
ADD16
ADD22
ADD15
ADD23
ADD12
ADD24
ADD7
ADD25
ADD6
VS2#
ADD5
RESET
ADD4
WAIT#
ADD3
INPACK#
ADD2
REG#
GND
ADD1
GND
BVD2
GND
ADD0
GND
BVD1
DATA0
DATA8
DATA1
GND DATA9
GND DATA2
DATA10
WP
CD2#
GND
GND

1
35
2
36
3
37
4
38
5
39
6
40
7
41
8
42
9
43
10
44
11
45
12
46
13
47
14
48
15
49
16
50
17
51
18
52
19
53
20
54
21
55
22
56
23
57
24
58
25
59
26
60
27
61
28
62
29
63
30
64
31
65
32
66
33
67
34
68

S1_D3
S1_CD1#
S1_D4
S1_D11
S1_D5
S1_D12
S1_D6
S1_D13
S1_D7
S1_D14
S1_CE1#
S1_D15
S1_A10
S1_CE2#
S1_OE#
S1_VS1
S1_A11
S1_IORD#
S1_A9
S1_IOWR#
S1_A8
S1_A17
S1_A13
S1_A18
S1_A14
S1_A19
S1_WE#
S1_A20
S1_RDY#
S1_A21
+S1_VCC

C

+S1_VCC

+S1_VPP
S1_A16_C
S1_A22
S1_A15
S1_A23
S1_A12
S1_A24
S1_A7
S1_A25
S1_A6
S1_VS2
S1_A5
S1_RST
S1_A4
S1_WAIT#
S1_A3
S1_INPACK#
S1_A2
S1_REG#
S1_A1
S1_BVD2
S1_A0
S1_BVD1
S1_D0
S1_D8
S1_D1
S1_D9
S1_D2
S1_D10
S1_WP
S1_CD2#

+S1_VPP
B

A

SANTA_130606-1_LT
PCMCIA@

Compal Secret Data

Security Classification
2006/08/05

Issued Date

2007/08/05

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

Compal Electronics, Inc.
TI PCI8412/CB socket
Document Number

Rev
2.0

LA-3481P
Sheet

Tuesday, May 22, 2007
1

25

of

47

5

4

3

1

2
R396
3.6K_0402_5%

2

+3V_LAN

+3V_LAN
+3V_LAN

U37
U18
PCIE_PTX_IRX_P2

29

HSOP

& lt; 22 & gt; PCIE_PTX_C_IRX_N2

C445 1

2 0.1U_0402_16V7K

PCIE_PTX_IRX_N2

30
23

& lt; 22 & gt; PCIE_ITX_C_PRX_N2

HSIN

8111C@ 1

2

C446
C446

1

1
0.1U_0402_16V4Z

+3V_LAN

LAN_MDI0+
LAN_MDI0LAN_MDI1+
LAN_MDI1-

100M@
1000M@

1

LAN_CTRL15

63

9
10
12
13

LAN_MDI2+
LAN_MDI2LAN_MDI3+
LAN_MDI3-

R397 1
2
R638

VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15

15
21
32
33
38
41
43
49
52
58

2 1K_0402_1%

VCTRL15
RSET

16
37
53
46

LANWAKEB

36

1

2

2

1

8111B@

2

C447
C447
0.1U_0402_16V4Z

2

C448
C448
0.1U_0402_16V4Z

1

1

2

C449
C449
0.1U_0402_16V4Z

1

2

C450
C450
0.1U_0402_16V4Z

65

EXPOSE_PAD

25

EGND

VDD33
VDD33
VDD33
VDD33

EGND

AVDD33

1

2

C949
C949
0.1U_0402_16V4Z

1

2

C950
C950
0.1U_0402_16V4Z

1

2

C951
C951

0.1U_0402_16V4Z

+LAN_VDD18

0.1U_0402_16V4Z

1

AVDD18
C952
C952

R637

2

0.1U_0402_16V4Z

1

2

C452
C452
0.1U_0402_16V4Z

1

2

C453
C453
0.1U_0402_16V4Z

1

2

C454
C454
0.1U_0402_16V4Z

1

2

C455
C455
0.1U_0402_16V4Z

1

0_0603_1%
2

C456
C456
0.1U_0402_16V4Z

1

C457
C457
0.1U_0402_16V4Z

+LAN_VDD15

8111B@
2 R942
1
0_0402_5%
2 R944
1
0_0402_5%
8111C@

2

+LAN_VDD18

+3V_LAN

59

NC
NC
NC
NC
NC
NC
NC
NC
NC

C451
C451

D

2

8111B@
2 R938
1
0_0402_5%

2

AVDD33
17
18
35
34
39
40
42
50
51

1

1

2

C458
C458
0.1U_0402_16V4Z

1

2

C459
C459
0.1U_0402_16V4Z

2

C460
C460
0.1U_0402_16V4Z

1

1

2

C461
C461
0.1U_0402_16V4Z

1

2

C462
C462
0.1U_0402_16V4Z

1

C463
C463
0.1U_0402_16V4Z

R947 close to C474
Don't near to L92

AVDD33

22

AVDD18

+3V_LAN

+LAN_VDD18

28

Mount for 8111B & 8100E
3

EVDD18

+3V_LAN

5
8
11
14

EVDD18

C469
C469

AVDD18
AVDD18
AVDD18
AVDD18

8111C@
2 R947
1
0_0402_5%
2
1
R948 8111B@ 0_0402_5%

27P_0402_50V8J
RTL8111B_QFN64

3

2

1

+LAN_VDD15

GVDD

R945
@ 0_0402_5%

2

0.1U_0402_16V4Z

+LAN_VDD18
LAN_CTRL18

40mil

1000M@
+LAN_VDD15

LAN_CTRL18

L92
L92 8111C@
1
2
4.7UH_1098AS-4R7M_1.3A_20%

L92 close to U37(Pin 1)

C

L40
100M@
1
2
1 BLM18AG601SN1D_0603
C470
C471

2

C965
C965
8111C@

Q11
MMJT9435T1G_SOT223
1000M@

1

40mil

+LAN_VDD18

1

C

8111C@
1 R946
2
0_0402_5%

LAN_CTRL15

Q10
MMJT9435T1G_SOT223
1000M@

1

100M@ 22U_0805_6.3V6M
2
22U_0805_6.3V6M

L41
100M@
1
2
1 BLM18AG601SN1D_0603
C473
C474

40mil
+LAN_VDD18

1

2

2

1

C472
C472
0.1U_0402_16V4Z

Mount for 8101E

40mil
1

2

100M@ 22U_0805_6.3V6M
2
22U_0805_6.3V6M

1
C475
2

Mount for 8101E

+LAN_VDD15

1000P_0402_50V7K

1

CKXTAL2

31

2
C465

1
2
BLM18AG601SN1D_0603
C467
C467

2
4

1000P_0402_50V7K

25MHZ_20P_6X25000017
Y2
Y2
LAN_X1
LAN_X2

61

2

8111B@ 1
C464

C962,C963,C964
close to U37(Pin 63)

CKXTAL1

LAN_X2

1

1

15K_0402_5%

R941 1
0_0402_5%
8111C@

0.1U_0402_16V4Z

2

60

62

+3V_LAN

ISOLATEB

LAN_X1
R401
R401

2

+LAN_VDD15

VCTRL18

2K_0402_1%64
2
1
2.49K_0402_1%
19

EC_PME#

2

2
4

R400
R400 1

LAN_CTRL18

47U_6.3V_M_1206_H1.6

2
C963
47U_6.3V_M_1206_H1.6
8111C@
+3V_LAN
R937
0_0603_1%
C962
C962
0.47U_0603_16V4Z
8111C@
1
2
8111C@ C964
& lt; 29 & gt;
47U_6.3V_M_1206_H1.6

27P_0402_50V8J

5
6
7
8

GND
NC
NC
VCC

LAN_LINK#
LAN_ACTIVITY#

3
4
6
7

MDIP2
MDIN2
MDIP3
MDIN3

PERSTB

& lt; 16 & gt; CLK_PCIE_LAN

C468
C468

DO
DI
SK
CS

REFCLK_N

20

LED3
LED2
LED1
LED0

REFCLK_P

27

54
55
56
57

MDIP0
MDIN0
MDIP1
MDIN1

26

& lt; 16 & gt; CLK_PCIE_LAN#

+3VS

4
3
2
1

AT93C46-10SI-2.7_SO8

& lt; 8,20,22,30,31 & gt; PLT_RST#

D

45
47
48
44

HSIP

24

EEDO
EDDI/AUX
EESK
EECS

HSON

& lt; 22 & gt; PCIE_ITX_C_PRX_P2

L39
L39
AVDD33
C466
C466

2 0.1U_0402_16V7K

10U_0805_10V4Z

& lt; 22 & gt; PCIE_PTX_C_IRX_P2

C444 1

1

B

B

Mount for 8101E

1
R912
R912

100M@
C476 2
1

R402
2
R403
2

4

4

3

3

Choke_LAN_MDI3P

LAN_MDI3-

LAN_MDI0LAN_MDI0+

1

1

2

2

Choke_LAN_MDI3N

@ WCM2012F2S-900T04_0805

100M@

100M@ R404 2
C477 2
1 R407 2

100M@
R406
0_0402_5%

0.01U_0402_25V7K

1 49.9_0402_1%
1 49.9_0402_1%

1
R913
R913

LAN_MDI1LAN_MDI1+

1
R914
R914

100M@

Place Close to Chip

2

2

1 49.9_0402_1%
1 49.9_0402_1%

100M@

1

1

0.01U_0402_25V7K

100M@
R405
0_0402_5%

LAN_MDI3+

100M@

+LAN_VDD18

LAN_MDI0+
LAN_MDI0-

U19
Choke_LAN_MDI3N
Choke_LAN_MDI3P

1
2
3

TCT1
TD1+
TD1-

MCT1
MX1+
MX1-

24
23
22

RJ45_MIDI3RJ45_MIDI3+

Choke_LAN_MDI2N
Choke_LAN_MDI2P

4
5
6

TCT2
TD2+
TD2-

MCT2
MX2+
MX2-

21
20
19

RJ45_MIDI2RJ45_MIDI2+

Choke_LAN_MDI1N
Choke_LAN_MDI1P

7
8
9

TCT3
TD3+
TD3-

MCT3
MX3+
MX3-

18
17
16

RJ45_MIDI1RJ45_MIDI1+

MCT4
MX4+
MX4-

15
14
13

TCT4
TD4+
TD4-

2

2

R408
R408
LAN_ACTIVITY#
C478
68P_0402_50V8K

2

R412
R412

Amber LED+

SHLD2

1

1
L90

2

2

5
4

PR3+

3

PR2+

RJ45_MIDI0-

2

PR1-

RJ45_MIDI0+

1

PR1+

Choke_LAN_MDI1N

2
68P_0402_50V8K

2
2 0_0402_5%
0_0402_5%

C479

1
2
R409
R409

LAN_LINK#

10

1

2

2

4

3

3

Green LED+

300_0402_5%

Choke_LAN_MDI2N

4

Green LED-

9

1
+3V_LAN

1

Choke_LAN_MDI2P

75_0402_1%

RJ45_GND

C482
C482
1
2
1000P_1206_2KV7K

@ WCM2012F2S-900T04_0805

SUYIN_100073FR012S100ZL
LANGND
1
1
C485
C485
C486
C486

2

RJ45_GND

1
R919
R919

13

PR3-

RJ45_MIDI2+

Choke_LAN_MDI1P

14

SHLD1

PR2-

RJ45_MIDI2@ WCM2012F2S-900T04_0805
44
33

15

PR4+

6

16

SHLD3

PR4-

7

R413
R413

75_0402_1%

SHLD4

8

RJ45_MIDI1-

LAN_MDI2-

1

75_0402_1%

Amber LED-

11

RJ45_MIDI3-

2
0_0402_5%

LAN_MDI2+

75_0402_1%

C484
C484
0.01U_0402_25V7K

12

+3V_LAN

RJ45_MIDI3+

R411
R411

1

1000M@

1

2

JP13

1 300_0402_5%

2
1

2
0_0402_5%

L91

1
C483
C483
0.01U_0402_25V7K

R410
R410

2

2

Choke_LAN_MDI0N

1
L89

1
R917
R917
1
R918
R918

2

2

0.5u_GST5009
C481
C481
0.01U_0402_25V7K

1

RJ45_MIDI0RJ45_MIDI0+

2

A

C480
C480
0.01U_0402_25V7K

1

Choke_LAN_MDI0P

RJ45_MIDI1+
LAN_MDI1-

2

1

LAN Conn.

@ WCM2012F2S-900T04_0805
44
33

1
R915
R915
1
R916
R916
LAN_MDI1+

1

Choke_LAN_MDI0N
Choke_LAN_MDI0P

2
0_0402_5%
2
0_0402_5%

2

1

10
11
12

2
0_0402_5%

L88

Place Close to Chip

0.1U_0402_16V4Z

2

A

4.7U_0805_10V4Z

2
0_0402_5%

Place these components
colsed to LAN chip

GST5009 for GIGA LAN
TST1284 for 10/100 LAN

Compal Secret Data

Security Classification
Issued Date

2006/08/05

Deciphered Date

2007/08/05

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

Compal Electronics, Inc.
RTL8111B/8101E 10/100/1000 LAN
Document Number

Rev
2.0

LA-3481P
Tuesday, May 22, 2007

Sheet
1

26

of

47

5

4

3

2

1

HD Audio Codec
+AVDD_AC97

35

LINE_OUT_R

36

NC
NC

CD_GND

MIC1_R
PCBEEP

SPK_SEL_CODEC_R

10mil
10mil
10mil

28
32

MIC2_VREFO

30

VREF

27

ACZ_VREF

JDREF

40

48

ICH_AC_SDIN0

& lt; 21 & gt;

& lt; 21 & gt;
2 @R930 1
10K_0402_5%
1 @R931 2
0_0402_5%

DVSS1
DVSS2

+MIC1_VREFO_R
+MIC2_VREFO

10mil
1

SPDIFO

NC

33

AVSS1
AVSS2

26
42

1

C524

1

R426
R426
2

ALC268-GR_LQFP48

DGND

AGND

2

ICH_BITCLK_AUDIO
1

R423
10_0402_5%
@

C523
2

1

100P_0402_50V8J

100P_0402_50V8J

C518
10P_0402_50V8J
@

2

SENSE_A

Codec Signals

Regulator for CODEC

PORT-B (PIN 21, 22)
PORT-C (PIN 23, 24)

+5VALW

39.2K
20K

PORT-F (PIN 16, 17)

10K

SENSE B

2

DELAY SENSE or ADJ
ERROR

CNOISE

1

GND

3

& lt; 29,30,35,40 & gt; SYSON

PORT-H (PIN 45, 46)

& lt; 19,29,30,35,38,40,41,42 & gt;

SUSP#

+VDDA

6

7

VOUT

@ C526
C526

PORT-G (PIN 43, 44)

5.1K

SENSE FOR HP

C525
C525

PORT-E (PIN 14, 15)

VIN

5
2

PORT-D (PIN 35, 36)

4

8
4.7U_0805_10V4Z

SD

SI9182DH-AD_MSOP8

2
1
R430
R430
0_0402_5%
2
1
R431 @ 0_0402_5%

R427
69.8K_0603_1%
1

5.1K

+VDDA

U21
L44 1
2
FBM-L11-160808-800LMT_0603

R432
SENSE_B

Adjustable Output

+5VALW_VDDA

C527
C527
4.7U_0805_10V4Z

1

10K

B

R429
24K _0402_1%
2

20K

SENSE A

PORT-A (PIN 39, 41)

0.1U_0402_16V4Z

Impedance
39.2K

SENSE FOR Int. Mic.

C

+3VS_DVDD

ACZ_JDREF 20K_0402_1%

EAPD

Sense Pin

2
20K_0402_1%
MIC@

RB751V_SOD323

+MIC1_VREFO_L

B

1

D16

C528
C528

2
20K_0402_1%

E

@ R421
10K_0402_5%

SPK_SEL_CODEC_R

MIC1_VREFO_R

47

1
2
MBK1608121YZF_0603
SPDIF
SPDIF

R428
R428
1

Q52

2
B

31

SDATA_OUT
GPIO0
GPIO3
SENSE A
SENSE B

SENSE FOR Ext. Mic.

& lt; 28 & gt; MIC_SENSE

R420
1
2
560_0402_5%
PCMCIA@

29

GPIO1

2 33_0402_5%

1

MIC1_VREFO_L

4
7

& lt; 19 & gt;

2

C513
0.01U_0402_25V7K
PCMCIA@

37

LINE1_VREFO

ICH_BITCLK_AUDIO
R424

0.1U_0402_16V4Z

C924

C510 1
1U_0402_6.3V4Z
2 PCMCIA@

1

C522
C522

1
@

SDATA_IN
MONO_OUT

2
3
13
34

L84
L84

2
10P_0402_50V8J

CardBus Beep

AMP_HP_R & lt; 28 & gt;

& lt; 24 & gt; PCM_SPK

8

SYNC

5

& lt; 21 & gt; ICH_SDOUT_AUDIO

EAPD

R419
1
2
560_0402_5%

MONO_IN

2SC2411KT146_SOT23-3

AMP_HP_L & lt; 28 & gt;

6

RESET#

10

SENSE_A
SENSE_B
& lt; 29 & gt;

BIT_CLK

11

& lt; 21 & gt; ICH_SYNC_AUDIO

R935 2
1
0_0402_5%

C

2

12

C500
C500
1
2

1U_0402_6.3V4Z
1
2
R418
2.4K_0402_5%

MIC1_L

22

2

D

1

21

C519
C519 4.7U_0603_6.3V6K~D
MONO_IN
1
2 100P_0402_50V8J
C520
1
2 100P_0402_50V8J
C521
& lt; 21 & gt; ICH_RST_AUDIO#

SPK_SEL_CODEC

C506
C506 1
1U_0402_6.3V4Z

SB_SPKR

44

MIC1_C_R

HIGH: HARMAN
LOW: NO-BRAND

& lt; 22 & gt;
AMP_RIGHT & lt; 28 & gt;

43

CD_R

AMP_LEFT & lt; 28 & gt;

46

CD_L

1
2
560_0402_5%

3

DMIC_CLK

2

PCI Beep

45

LINE1_R

R414
R414
20K_0402_5%

R810
R810
10K_0402_5%

1

NC

BEEP#

R416

2

LINE1_L

2

10P_0402_50V8J

AMP_HP_R

19

MIC1_R

& lt; 22 & gt; SPK_SEL_CODEC

41

MIC1_C_L

C

SPK_SEL

39

HP_OUT_R

18

C517
C517 4.7U_0603_6.3V6K~D

MIC1_R

HP_OUT_L

MIC2_R

2

C499
C499 1
1U_0402_6.3V4Z

C503
C503

2

& lt; 28 & gt;

MIC2_L

24

2 100P_0402_50V8J

1
C516

1

AMP_HP_L

23

MIC1_L

MIC1_L

1

& lt; 29 & gt;

AMP_RIGHT

17

2
100P_0402_50V8J

EC Beep

1

LINE_OUT_L

NC

+VDDA

2

NC

20

1
C515

100P_0402_50V8J

9

1
DVDD

AVDD1

C502
C502

16

2
100P_0402_50V8J

+3VS

2

680P_0402_50V7K

10P_0402_50V8J
AMP_LEFT

15

MIC2_L
2
100P_0402_50V8J
2
1U_0402_6.3V4Z
MIC2_R
2
1U_0402_6.3V4Z

1
C497

C496

10U_0805_10V4Z

1
C501
C505
INT_MIC
1
1
C504
1
2
2
1
C507
C507
ACES_85204-0200
220P_0402_50V7K
MIC@
MIC@
1
C508
JP40

& lt; 28 & gt;

2

C495
C495

1

2

14

Int MIC Conn.

R417
R417 4.7K_0402_5%

1

0.1U_0402_16V4Z

DVDD_IO

+MIC2_VREFO

2

1
C493
C493

2

U20

1

1
C492
C492

1

20mil

2

C491

2
100P_0402_50V8J

L43
1
2
+3VS
FBM-L11-160808-800LMT_0603

680P_0402_50V7K

10U_0805_10V4Z

C490
C490

C494
C494

C489
C489

2
0.1U_0402_16V4Z

0.1U_0402_16V4Z

38

D

2

1

25

2

1

+3VS_DVDD

40mil

680P_0402_50V7K

AVDD2

C487
C487

+VDDA

10U_0805_10V4Z

0.1U_0402_16V4Z
1
1
C488
C488

L42 1
2
FBM-L11-160808-800LMT_0603

R436
& lt; 28 & gt; HP_SENSE

2

A

1
39.2K_0402_1%

SENSE_A

Moat Bridge
1
R433
1
R434
R434
1
R435
R435
1
R437
R437

2
0_0603_1%
2
0_0603_1%
2
0_0603_1%
2
0_0603_1%

A

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2006/08/05

Issued Date

2007/08/05

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

HD Audio Codec_ALC268
Document Number

Rev
2.0

LA-3481P
Tuesday, May 22, 2007

Sheet
1

27

of

47

B

0_0603_1%
0_0603_1%

+MIC1_VREFO_L +MIC1_VREFO_R

C540
C540 2.2U_0603_6.3V6K
1
1U_0402_6.3V4Z

2
C543
C543

AMP_CP+
AMP_CP2.2U_0603_6.3V6K
AMP_BIAS
2.2U_0603_6.3V6K
1
0.1U_0402_16V4Z

C545
C545
2

INR_H
INL_H

HP_R
HP_L

/SD
BEEP

CVSS

12
14

BIAS

2
23
7
13

2
SM05_SOT23

1

1

1
2

2

1
2
2
5

& lt; 27 & gt;

R856
HP_R

1

HP_L

1
1

2 20_0402_1%

4

HP_SENSE

8

HPR

2 20_0402_1%

R857

HPL

1

R450
0_0402_5%
@

C541
C541

2

2

R449
0_0402_5%
@

L47 1
2
KC FBM-L11-160808-121LMT 0603
L48 1
2
KC FBM-L11-160808-121LMT 0603

Q15

0_0402_5%
2
1
R840 @

AGND
J2
JUMP_43X39
@

HEADPHONE
OUT JACK

2

1
3

R452
1 R452
2EC_EAPD#
100K_0402_5%

S

J3
JUMP_43X39
@

JP15

HP_EN

2
G

D17

C546
2.2U_0603_6.3V6K

D
2N7002_SOT23-3

+5VS

EC_EAPD

FOX_JA6033L-5S1-TR

CVSS

1

2

EC_EAPD

@

16

GND
PGND
PGND
CGND

CP+
CP-

25

15

VSS

IN_A Gain = 10dB (Internal Speaker)
IN_H Gain = 0dB (Headphone)

& lt; 29 & gt;

2

1

7

HP_R
HP_L

HP EN

APA2056_TSSOP28

0_0402_5%
2
1
R453 @

1
C530

1

17
18

3

1
VDD

19

20
10

INTSPK_L1
INTSPK_L2

28

C544

PVDD
PVDD

11

8
9

26

AMP_BEEP

C547
C547

LOUT+
LOUT-

3
6
2
1

MIC1_L_1

2

INTSPK_R1
INTSPK_R2

8

MIC1_R_1

1

22
21

4
6

EC_EAPD#

L45
1
2
KC FBM-L11-160808-121LMT 0603
L46
1
2
KC FBM-L11-160808-121LMT 0603

MIC1_L

1
C542
C542

2

3
6
2
1
2

& lt; 27 & gt; AMP_HP_L

MIC1_L

C529

ROUT+
ROUT-

24

R447 2 INR_H
1
24K_0402_5%
R448
R448 2 INL_H
1
24K_0402_5%

C539 2.2U_0603_6.3V6K

U22

MIC1_R

MIC1_R

& lt; 27 & gt;

3

+5VS
& lt; 27 & gt; AMP_HP_R

HP_EN

& lt; 27 & gt; MIC_SENSE

/AMP EN

AMP_EN#27

2 100K_0402_5%

4

2

7
FOX_JA6033L-5S1-TR

D18
@

AGND

SM05_SOT23
1

R446
R446 1

5

10P_0402_50V8J

& lt; 27 & gt; AMP_LEFT

4.7K_0402_5%

R440
R440
JP14

INR_A
INL_A

3
5

MICROPHONE
IN JACK

10mil

10P_0402_50V8J

AMPR
C535
C535 0.22U_0603_16V7K
AMPL
C537 0.22U_0603_16V7K
R445
R445 1
2 100K_0402_5%

& lt; 27 & gt; AMP_RIGHT

R439
R439
4.7K_0402_5%

& lt; 27 & gt;

HVDD

2

1

CVDD

1

1
C534
C534

2

10U_0805_10V4Z

2

C533
C533

1U_0402_6.3V4Z

1

0.1U_0402_16V4Z

680P_0402_50V7K

C929
C929
1

C930 C532
C930 C532

2

220P_0402_50V7K

W=40mil

+5VS for SA00001G200
+3VS for SA00001G210

1U_0402_6.3V4Z

10mil

220P_0402_50V7K

R863
R863 @

+5VS

1

R862

E

2

+3VS
+5VS

D

1

APA2056 SPK/HP Amplifier

C

2

A

1

2

C916
C916
0.1U_0402_16V4Z

Right Speaker Connector

@ SM05_SOT23 D19
2
1

1
C917
C917

2
0.1U_0402_16V4Z

3
INTSPK_L1
INTSPK_L2

L49 1
L50 1

2 0_0603_1%
2 0_0603_1%

JP16
JP16
SPK_L1
SPK_L2

1
2
ACES_85204-0200

Left Speaker Connector
INTSPK_R1
INTSPK_R2

JP17
JP17
L51 1
L52 1

2 0_0603_1%
2 0_0603_1%

SPK_R1
SPK_R2

1
2
ACES_85204-0200

3
1

3

3

2
@ SM05_SOT23 D20

Volume Control
+3VS

P
2
1
2
R457
R457 10K_0402_5%
U23
U23

1
C550
C550
2

0.01U_0402_25V7K

4

1
2
R458
R458 10K_0402_5%
0.01U_0402_25V7K

3

4

SW_XRE094_3P

1

B
DIP

COM

A
G

2

1
C551
C551
2

2

0.1U_0402_16V4Z
Y

1

+3VS

4

74LVC1G14GW_SOT353-5

0.1U_0402_16V4Z
C549
C549
1
C552
C552

2

2
0.1U_0402_16V4Z

U24

3

A

2
1

5

+3VS

2

2

C548
C548
1

NC

R456
R456
10K_0402_5%

5

R455
R455
10K_0402_5%

DIP

SW1

R454
R454
100K_0402_5%

1

1

1

+3VS

1
2
3
4
5
6
7

CD1#
D1
CP1
SD1#
Q1
Q1#
GND

VCC
CD2#
D2
CP2
SD2#
Q2
Q2#

14
13
12
11
10
9
8

74LCX74MTC_TSSOP14
4

ENCODER_DIR & lt; 29 & gt;
ENCODER_PULSE & lt; 29 & gt;

2006/08/05

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2007/08/05

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

AMP/VR/Audio Jack
Document Number

Rev
2.0

LA-3481P
Sheet

Saturday, June 02, 2007
E

28

of

47

5

4

3

2

1

+3VALW

1

0.1U_0402_16V4Z
C933
1 C933
1

C932
C932

C934
C934

2
2
0.1U_0402_16V4Z

L86
L86
1
2
2 FBM-L11-160808-800LMT_0603

0.1U_0402_16V4Z
1
2
C935
C935

2
2
0.1U_0402_16V4Z

C936
C936
1000P_0402_50V7K
1
1

For EC Tools

+EC_VCCA
KSI[0..7]

1

C937
C937
1000P_0402_50V7K

KSI[0..7]

KSO[0..17]

KSO[0..17]

C938
C938

2

JP50

& lt; 32,34 & gt;

1
2
3
4

1
2
3
4

& lt; 32,34 & gt;

0.1U_0402_16V4Z

+5VALW

E51_RXD
E51_TXD

@ ACES_85205-0400

67

D

& lt; 34,37 & gt;
& lt; 34,37 & gt;
& lt; 4,19 & gt;
& lt; 4,19 & gt;

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

& lt; 22 & gt; PM_SLP_S3#
& lt; 22 & gt; PM_SLP_S5#
& lt; 22 & gt; EC_SMI#
& lt; 34 & gt; LID_SW#
& lt; 19,27,30,35,38,40,41,42 & gt; SUSP#
& lt; 22 & gt; PBTN_OUT#

Strap
4.7K_0402_5%
ENBKL
2
100K_0402_5%
SYSON
2
100K_0402_5%
SUSP#
2
100K_0402_5%

2

& lt; 31 & gt; PCIE_WAKE#

PCIE_WAKE#

2

PM_SLP_S3#
PM_SLP_S5#
EC_SMI#
LID_SW#
SUSP#
PBTN_OUT#
EC_PME#
R900 10_0402_5%

6
14
15
16
17
18
19
25
28
29
E51_TXD
30
E51_RXD
31
ON/OFFBTN#
32
PWR_SUSP_LED 34
NUM_LED#
36

& lt; 4 & gt; FAN_SPEED1
& lt; 31,35 & gt; E51_TXD
& lt; 31,35 & gt; E51_RXD
& lt; 34 & gt; ON/OFFBTN#
& lt; 34 & gt; PWR_SUSP_LED
& lt; 32 & gt; NUM_LED#

122
123

12

2

4

5

2

D63A
@ BAV99DW-7_SOT363

6

R882

2

@ 2.2K_0402_5%

EC_EAPD & lt; 28 & gt;
USB_EN# & lt; 33 & gt;
WL_BT_LED# & lt; 34 & gt;
Sattlate_LED# & lt; 34 & gt;
TP_CLK & lt; 34 & gt;
TP_DATA & lt; 34 & gt;

C

97
98
99
109

Strap

SPIDI/RD#
SPIDO/WR#
SPICLK/GPIO58
SPICS#

119
120
126
128

FWR#SPI_SI
FRD#SPI_SO
EC_SPICLK
FSEL#SPICS#

CIR_RX/GPIO40
CIR_RLC_TX/GPIO41
FSTCHG/SELIO#/GPIO50
BATT_CHGI_LED#/GPIO52
CAPS_LED#/GPIO53
BATT_LOW_LED#/GPIO54
SUSP_LED#/GPIO55
SYSON/GPIO56
VR_ON/XCLK32K/GPIO57
AC_IN/GPIO59

73
74
89
90
91
92
93
95
121
127

EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04
EC_ON/GPXO05
EC_SWI#/GPXO06
ICH_PWROK/GPXO06
GPO
BKOFF#/GPXO08
WL_OFF#/GPXO09
GPXO10
GPXO11

100
101
102
103
104
105
106
107
108

PM_SLP_S4#/GPXID1
ENBKL/GPXID2
GPXID3
GPXID4
GPXID5
GPXID6
GPXID7

110
112
114
115
116
117
118

V18R

124

SPI Flash ROM

+3V_LAN

2

STB_LAN & lt; 47 & gt;
STB_SB & lt; 47 & gt;
VGATE & lt; 22,43 & gt;

R883
10K_0402_5%

FWR#SPI_SI & lt; 34 & gt;
FRD#SPI_SO & lt; 34 & gt;
EC_SPICLK & lt; 34 & gt;
FSEL#SPICS# & lt; 34 & gt;

1

SPI Device Interface

EC_PME#

EC_PME# & lt; 26 & gt;

+3VALW

GPIO
SM Bus

PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
GPIO
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A

GPI

XCLK1
XCLK0

11
24
35
94
113

GND
GND
GND
GND
GND

CRY1
CRY2

R881
@ 2.2K_0402_5%

3

SCL1/GPIO44
SDA1/GPIO45
SCL2/GPIO46
SDA2/GPIO47

& lt; 22 & gt;

1

77
78
79
80

RSMRST#

CIR_IN
ENCODER_PULSE
FSTCHG
BATT_FULL_LED#
CAPS_LED#
BATT_CHG_LOW_LED#
POWER_LED#
SYSON
VR_ON

CIR_IN & lt; 33 & gt;
ENCODER_PULSE & lt; 28 & gt;
FSTCHG & lt; 38 & gt;
BATT_FULL_LED# & lt; 34 & gt;
CAPS_LED# & lt; 32 & gt;
BATT_CHG_LOW_LED# & lt; 34 & gt;
POWER_LED# & lt; 34 & gt;
SYSON
& lt; 27,30,35,40 & gt;
VR_ON
& lt; 43 & gt;

+5VS
R952
332K_0402_1%

RB751V_SOD323
EC_RSMRST#
EC_LID_OUT#
EC_ON
EC_SWI#
PWROK
BKOFF#

ENBKL
EAPD
EC_THERM#
IE_BTN#

EC_LID_OUT# & lt; 22 & gt;
EC_ON
& lt; 34 & gt;
EC_SWI# & lt; 22,30,31 & gt;
PWROK & lt; 8,22 & gt;
BKOFF#
& lt; 19 & gt;
WL_OFF# & lt; 31 & gt;
ALI/MH# & lt; 37,38 & gt;
Cursor_LED & lt; 32 & gt;

TP_CLK

1
R887
TP_DATA 1
R890
2

0_0402_5% 2
@

1
D64

1

PACIN

& lt; 22,36,38 & gt;

ACIN

& lt; 34,36 & gt;

2
4.7K_0402_5%
2
4.7K_0402_5%

0_0402_5%

R953
ENBKL

PM@
2

1 R895

VGA_ENBKL & lt; 19 & gt;

0_0402_5%

GM@
2

1 R897

GMCH_ENBKL & lt; 10 & gt;

CRY1

EAPD
& lt; 27 & gt;
EC_THERM# & lt; 22 & gt;
BT_PWR & lt; 33 & gt;
BT_RST# & lt; 33 & gt;
IE_BTN# & lt; 34 & gt;

1
C943
KB926QFA1_LQFP128_14X14

1 R899
2CRY2
@ 20M_0603_5%

1

2

L87
ECAGND
2
1
FBM-L11-160808-800LMT_0603

2

B

X3

2

C944
C944
15P_0402_50V8J

B

1
R904
1
R894
R894
1
R896
1
R898

2
2 4.7K_0402_5%
2 4.7K_0402_5%
2 4.7K_0402_5%
4.7K_0402_5%

0.22U_0603_16V7K

1

SDICS#/GPXOA00
SDICLK/GPXOA01
SDIDO/GPXOA02
SDIDI/GPXID0

+5VALW

1
R888
1
R889
1
R891
1
R892

C941
C941

DAC_BRIG & lt; 19 & gt;
EN_DFAN1 & lt; 4 & gt;
IREF
& lt; 38 & gt;

OSC

IE_BTN#
2
10K_0402_5%

1

@ MMBT3906_SOT23

NC

1

PS2 Interface

& lt; 38 & gt;

4

MODE#
1
10K_0402_5%

EC_EAPD
USB_EN#
WL_BT_LED#
Sattlate_LED#
TP_CLK
TP_DATA

ADP_I

OSC

2

PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D
TP_CLK/PSCLK3/GPIO4E
TP_DATA/PSDAT3/GPIO4F

83
84
85
86
87
88

Q79

2
100K_0402_5%

NC

R886

BUTTON_ID
2
100K_0402_5%

KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49

1
R879

EC_RSMRST#
3
D63B
@ BAV99DW-7_SOT363

3

R885

CIR_IN
2
100K_0402_5%

1

55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82

MODE# & lt; 34 & gt;
KILL_SW# & lt; 31 & gt;
BUTTON_ID & lt; 34 & gt;

BATT_TEMPA & lt; 37 & gt;

1

R884

1
NOCIR@

DAC_BRIG
EN_DFAN1
IREF

MODE#
KILL_SW#
BUTTON_ID

1

ECAGND
2
1
C939 0.01U_0402_16V7K
BATT_OVP & lt; 38 & gt;

15P_0402_50V8J

C

DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D
IREF/DA2/GPIO3E
DA3/GPIO3F

68
70
71
72

DA Output

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

& lt; 32,34 & gt; EC_REVBTN#
+3VALW

R928

AD

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17

& lt; 32,34 & gt; EC_PLAYBTN#
& lt; 32,34 & gt; EC_STOPBTN#
& lt; 32,34 & gt; EC_FRDBTN#

BATT_TEMPA
BATT_OVP

0_0402_5%
2

2

C942
C942
0.1U_0402_16V4Z

63
64
65
66
75
76

R877

1

2

EC_RST#
EC_SCI#

EC_SCI#
STB_WLAN

BATT_TEMP/AD0/GPIO38
BATT_OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
Input
AD3/GPIO3B
AD4/GPIO42
SELIO2#/AD5/GPIO43

PWM Output

INVT_PWM & lt; 19 & gt;
BEEP#
& lt; 27 & gt;
ENCODER_DIR & lt; 28 & gt;
ACOFF & lt; 38 & gt;

B
B

& lt; 22 & gt;
& lt; 47 & gt;

1

PCICLK
PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D

INVT_PWM
BEEP#
ENCODER_DIR
ACOFF

E
E

1
47K_0402_5%

12
13
37
20
38

21
23
26
27

INVT_PWM/PWM1/GPIO0F
BEEP#/PWM2/GPIO10
FANPWM1/GPIO12
ACOFF/FANPWM2/GPIO13

C

& lt; 16 & gt; CLK_PCI_EC
& lt; 20,24,35 & gt; PCI_RST#
2
+3VALW
R880
R880

1 @ 33_0402_5%

GA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LFRAME#
LAD3
LAD2
LAD1
LPC
LAD0 LPC & MISC

RSMRST circuit

AGND

R878 2

LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

1
2
3
4
5
7
8
10

69

C940
@ 22P_0402_50V8J
2
1

& lt; 21 & gt; GATEA20
& lt; 21 & gt; EC_KBRST#
& lt; 22,24,35 & gt; SERIRQ
& lt; 21,35 & gt; LPC_FRAME#
& lt; 21,35 & gt; LPC_AD3
& lt; 21,35 & gt; LPC_AD2
& lt; 21,35 & gt; LPC_AD1
& lt; 21,35 & gt; LPC_AD0

AVCC

VCC
VCC
VCC
VCC
VCC
VCC

D

9
22
33
96
111
125

U53

ECAGND

32.768KHZ_12.5PF_9H03200413
A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2006/06/30

Deciphered Date

2007/06/30

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

ENE-KB926
Document Number

Rev
2.0

LA-3481P
Tuesday, May 22, 2007

Sheet
1

29

of

47

A

B

C

D

E

+3VS

New Card

C568

+3V_SB

1

C569
@

U26

5
6

+3VS
1

3.3Vout1
3.3Vout2

7
8

Aux_out

20

1.5Vout1
1.5Vout2

3.3Vin1
3.3Vin2

16
17

60mils

1

C570

2 0.1U_0402_16V4Z 2 10U_0805_10V4Z

+3VS_CARD

+1.5VS

1

C571
@

1

C572

2 0.1U_0402_16V4Z 2 10U_0805_10V4Z

1

C573
@

1

2 0.1U_0402_16V4Z 2 10U_0805_10V4Z
1

+3V_SB

21

+3V_SB
NEWCARD@
1
2 CP_USB#
R566 100K_0402_5%

3.3Vaux_in

CP_USB#
EXP_CPPE#

1
2EXP_CPPE#
R490
R490 100K_0402_5%
& lt; 19,27,29,35,38,40,41,42 & gt; SUSP#
& lt; 27,29,35,40 & gt; SYSON
& lt; 8,20,22,26,31 & gt; PLT_RST#

1.5Vin1
1.5Vin2

14
15
4
3
2

CPUSB#
CPPE#
STBY#
SHDN#
SYSRST#

PLT_RST#

RCLKEN
PERST#

+3VS_CARD

Imax = 0.275A

C574

23
22
9

+3VALW_CARD
+1.5VS_CARD

RCLKEN
PERST#

1

2

C575
NEWCARD@
10U_0805_10V4Z

1

2

C576
NEWCARD@
0.1U_0402_16V4Z

1

2

C577
NEWCARD@
10U_0805_10V4Z

1

2

I0

O
I1

3

D
Q16
2N7002_SOT23-3
NEWCARD@

4

PERST#
CLKREQ#
EXP_CPPE#

& lt; 22 & gt; EXP_CPPE#
& lt; 16 & gt; CLK_PCIE_CARD#
& lt; 16 & gt; CLK_PCIE_CARD

EXP_CLKREQ# & lt; 16 & gt;

G

1
1

CP_USB#

+3VS_CARD

U27

2

CLKREQ#

5

2

2

& lt; 22,29,31 & gt; EC_SWI#
+3VALW_CARD

C580
0.1U_0402_16V4Z
NEWCARD@

P

1
R492
NEWCARD@ 10K_0402_5%

3

USB20_N9
USB20_P9

& lt; 16,22,31 & gt; ICH_SMBCLK
& lt; 16,22,31 & gt; ICH_SMBDATA
+1.5VS_CARD

+3VS

R491
10K_0402_5%
NEWCARD@

S

2

C578
NEWCARD@
0.1U_0402_16V4Z

1

+3VS

2
G

1

1

2

C579
NEWCARD@
10U_0805_10V4Z

1

2

NEWCARD@
0.1U_0402_16V4Z

JP19

2

RCLKEN

Imax = 0.75A

NEWCARD@ TPS2231PWPR_PWP24

& lt; 22 & gt;
& lt; 22 & gt;

+3VS

+1.5VS_CARD

Imax = 1.35A

1
10
12
13
24

11

GND

share with USB OC PIN
need always pull high

OC#

+3VALW_CARD

40mil

NC1
NC2
NC3
NC4
NC5

+1.5VS

18
19

40mil

TC7SH32FU_SSOP5
NEWCARD@

& lt; 22 & gt; PCIE_PTX_C_IRX_N1
& lt; 22 & gt; PCIE_PTX_C_IRX_P1
& lt; 22 & gt; PCIE_ITX_C_PRX_N1
& lt; 22 & gt; PCIE_ITX_C_PRX_P1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

GND
USB_DUSB_D+
CPUSB#
RSV
RSV
SMB_CLK
SMB_DATA
+1.5V
+1.5V
WAKE#
+3.3VAUX
PERST#
+3.3V
+3.3V
CLKREQ#
CPPE#
REFCLK- GND
REFCLK+ GND
GND
PERn0
PERp0
GND
GND
PETn0
GND
PETp0
GND

2

31
32

29
30

GND
GND
TYCO_1759056-1 NEWCARD@

3

+3V_SB

MDC

3

MDC Conn.

1
C695
C695
1000P_0402_50V7K
2

1

C696
C696

2
0.1U_0402_16V4Z

C697
4.7U_0805_10V4Z

JP38

& lt; 21 & gt; ICH_SDOUT_MDC
& lt; 21 & gt; ICH_SYNC_MDC
& lt; 21 & gt; ICH_AC_SDIN1

ICH_SDOUT_MDC
ICH_SYNC_MDC
R541 1
2 33_0402_5%
MDC_RESET#

1
3
5
7
9
11

GND1
RES0
IAC_SDATA_OUT
RES1
GND2
3.3V
IAC_SYNC
GND3
IAC_SDATA_IN
GND4
IAC_RESET#
IAC_BITCLK

2
4
6
8
10
12

20mil
+3V_SB
ICH_BITCLK_MDC

ICH_BITCLK_MDC

& lt; 21 & gt;

R543
R543

13
14
15
16
17
18

GND
GND
GND
GND
GND
GND

2

11

2

10_0402_5% C693 22P_0402_50V8J
C693
ACES_88018-124G

+3V_SB

ICH_RST_MDC#

& lt; 21 & gt; ICH_RST_MDC#

10

A

U13C

O
B

8

4

MDC_RESET#

G

9

& lt; 21 & gt; MDC_RST#

7

4

P

14

Connector
Connector for MDC Rev1.5

C919
C919
680P_0603_50V7K
@

SN74LVC08APW_TSSOP14

Compal Secret Data

Security Classification
2006/08/05

Issued Date

Deciphered Date

2007/08/05

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Compal Electronics, Inc.
New Card & MDC
Document Number

Rev
2.0

LA-3481P
Tuesday, May 22, 2007

Sheet
E

30

of

47

A

B

C

NAND mini Card(Robson support)

D

E

Mini-Express Card for 3G
C956
3G@0.1U_0402_16V4Z

+3VS

2

+1.5VS

1 R932
2
3G@
0_1206_5%

1

+3VS

+1.5VS

C957
3G@4.7U_0805_10V4Z

1

JP20

1

ROB@

1

C587
2 0.01U_0402_25V7K

2

ROB@
C588
0.1U_0402_16V4Z

ROB@
C589
4.7U_0805_10V4Z

53

ROB@

1

C592

ROB@
C590

C591

2 0.01U_0402_25V7K

4.7U_0805_10V4Z

1
& lt; 16 & gt; CLK_PCIE_HDDVD#
& lt; 16 & gt; CLK_PCIE_HDDVD

2 0.1U_0402_16V4Z

& lt; 22 & gt; PCIE_PTX_C_IRX_N5
& lt; 22 & gt; PCIE_PTX_C_IRX_P5
& lt; 22 & gt; PCIE_ITX_C_PRX_N5
& lt; 22 & gt; PCIE_ITX_C_PRX_P5

+3VS +1.5VS
JP21

& lt; 16 & gt; CLK_PCIE_NAND#
& lt; 16 & gt; CLK_PCIE_NAND

& lt; 22 & gt; PCIE_PTX_C_IRX_N4
& lt; 22 & gt; PCIE_PTX_C_IRX_P4
& lt; 22 & gt; PCIE_ITX_C_PRX_N4
& lt; 22 & gt; PCIE_ITX_C_PRX_P4
2

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

53

GND1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
GND2

+3VS

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

GND1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

GND2

54

+UIM_PWR
1

D53

@ 1N4148_SOT23
3G_OFF#
2

1

PLT_RST#

R936
R807
R808

@ 0_0402_5%
@ 0_0402_5%

XMIT_OFF#

@ 0_0402_5%

ICH_SMBCLK
ICH_SMBDATA

ICH_SMBCLK & lt; 16,22,30 & gt;
ICH_SMBDATA & lt; 16,22,30 & gt;

USB20_N2 & lt; 22 & gt;
USB20_P2 & lt; 22 & gt;
3G_LED#

54

PLT_RST#

C582

+3VS
+UIM_PWR
UIM_DATA
UIM_CLK
UIM_RESET

3G_LED#

& lt; 34 & gt;

3G@ FOX_AS0B226-S40N-7F

PLT_RST# & lt; 8,20,22,26,30 & gt;

1

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

Small/B already had ESD IC

+UIM_PWR

+UIM_PWR
1

R718
4.7K_0402_5%
@

1
2
3
4
5
6

UIM_RESET
UIM_CLK
C874
UIM_DATA

0.1U_0402_16V4Z
2
@

2

JP22

2

ROB@
1

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

1 R954
2
3G@4.7K_0402_5%
CLK_PCIE_HDDVD#
CLK_PCIE_HDDVD

1

C581

4.7U_0805_10V4Z
0.1U_0402_16V4Z
2 3G@
2 3G@

ACES_85201-0605
@

FOX_AS0B226-S40N-7F
ROB@

+3VS_MINI

Mini-Express Card for WLAN
1

C593
0.01U_0402_25V7K

2

C594
0.1U_0402_16V4Z

WLAN@

+3VS

+1.5VS

R929
1 R929
2
0_1206_5%
WLAN@

1

C596
C595
C595
4.7U_0805_10V4Z

2

WLAN@

1

0.01U_0402_25V7K
WLAN@ 2

C597

+3V_WLAN

1

1
C598
4.7U_0805_10V4Z

0.1U_0402_16V4Z
WLAN@ 2

C599
0.1U_0402_16V4Z
WLAN@ 2

WLAN@

WLAN@

+3VS_MINI

R875
R876

& lt; 29,35 & gt; E51_TXD
& lt; 29,35 & gt; E51_RXD

@ 0_0402_5%
@ 0_0402_5%

4

54

USB20_N3
USB20_P3

1BS003-1211L_3P

5
2

B

KILL_SW#

U28
Y

A

2 0.1U_0402_16V4Z
WLAN@
D23

P

KILL_SW# 2

3

R494
100K_0402_5%
1

ICH_SMBCLK & lt; 16,22,30 & gt;
ICH_SMBDATA & lt; 16,22,30 & gt;
USB20_N3 & lt; 22 & gt;
USB20_P3 & lt; 22 & gt;

WL_OFF# 1

& lt; 29 & gt; KILL_SW#
PLT_RST# & lt; 8,20,22,26,30 & gt;
+3V_WLAN

ICH_SMBCLK
ICH_SMBDATA

& lt; 29 & gt; WL_OFF#

+3V_WLAN

XMIT_OFF#

1

4

3G_OFF#

G

D22
DAN217_SC59
@

2

C600

1

GND2

+3V_WLAN

+3V_WLAN

1

2

XMIT_OFF#

RB751V_SOD323
TC7SH08FU_SSOP5
WLAN@

WLAN@

KILL_SW# & lt; 29 & gt;

1

GND1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

1

& lt; 22 & gt; PCIE_ITX_C_PRX_N3
& lt; 22 & gt; PCIE_ITX_C_PRX_P3

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

2

& lt; 22 & gt; PCIE_PTX_C_IRX_N3
& lt; 22 & gt; PCIE_PTX_C_IRX_P3

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

3

CLK_PCIE_MCARD#
CLK_PCIE_MCARD

& lt; 16 & gt; CLK_PCIE_MCARD#
& lt; 16 & gt; CLK_PCIE_MCARD

Kill SWITCH

JP23
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53

& lt; 29 & gt; PCIE_WAKE#
& lt; 33 & gt; WLAN_BT_DATA
& lt; 33 & gt; WLAN_BT_CLK

3

+1.5VS

***

2

@
D57
2
1
CH751H-40_SC76
PCIE_WAKE#
WLAN_BT_DATA
WLAN_BT_CLK

+3V_WLAN

3

& lt; 22,29,30 & gt; EC_SWI#

2
R818

3

1
10K_0402_5%

3

SW2
WLAN@

4

FOX_AS0B226-S40N-7F
WLAN@

Compal Secret Data

Security Classification
2006/08/05

Issued Date

2007/08/05

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Compal Electronics, Inc.
PCI-E Mini Card I/F
Document Number

Rev
2.0

LA-3481P
Sheet

Tuesday, May 22, 2007
E

31

of

47

2

1

C604

0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
2
2HDD@
2HDD@
2HDD@

2

2HDD@

1

1

C606

C607

1

1

C608

0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
2
2HDD@
2HDD@
2HDD@

2

+5VS

10U_0805_10V4Z

1

C603

C609

1

C602

C605

1

1

+3VS

10U_0805_10V4Z

2

10U_0805_10V4Z

C601

1

3

1

C610

0.1U_0402_16V4Z
2

1

2

1

C611
0.1U_0402_16V4Z

2

C612

0.1U_0402_16V4Z

1

2

10U_0805_10V4Z

4

+5VS

C613

5

+3VS

1

2

1

C614
0.1U_0402_16V4Z

2

1

C615
0.1U_0402_16V4Z

2

C616
0.1U_0402_16V4Z

2HDD@

Place Components closely to SATA Conn.

Place Components closely to SATA Conn.

D

D

SATA HDD Conn.
SATA HDD-2 Conn.

JP24

S1
S2
S3
S4
S5
S6
S7

SATA_ITX_C_DRX_P2
SATA_ITX_C_DRX_N2

& lt; 21 & gt; SATA_ITX_C_DRX_P2
& lt; 21 & gt; SATA_ITX_C_DRX_N2

SATA_DTX_C_IRX_N2
SATA_DTX_C_IRX_P2

& lt; 21 & gt; SATA_DTX_C_IRX_N2
& lt; 21 & gt; SATA_DTX_C_IRX_P2

3900P_0402_50V7K
C617
1
2
2HDD@SATA_DTX_IRX_N2
1
2
2HDD@SATA_DTX_IRX_P2
C619
3900P_0402_50V7K

P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15

+3VS

+5VS

C

JP29
JP29

GND
A+
AGND
BB+
GND
V33
V33
V33
GND
GND
GND
V5
V5
V5
GND
Reserved
GND
V12
V12
V12

& lt; 21 & gt; SATA_ITX_C_DRX_P0
& lt; 21 & gt; SATA_ITX_C_DRX_N0
& lt; 21 & gt; SATA_DTX_C_IRX_N0
& lt; 21 & gt; SATA_DTX_C_IRX_P0

1
2
3
4
5
6
7

SATA_ITX_C_DRX_P0
SATA_ITX_C_DRX_N0
SATA_DTX_C_IRX_N0
SATA_DTX_C_IRX_P0

C618 3900P_0402_50V7K
SATA_DTX_IRX_N0
1
2
SATA_DTX_IRX_P0
1
2
C620 3900P_0402_50V7K

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

+3VS

GND
GND

18
19
+5VS

SUYIN_127072FR022G210ZR_RV
2HDD@

GND
A+
AGND
BB+
GND
V33
V33
V33
GND
GND
GND
V5
V5
V5
GND
Reserved
GND
V12
V12
V12

C

GND
GND

24
23

OCTEK_SAT-22SO1G_RV

IDE_DD[0..15]

& lt; 21 & gt; IDE_DD[0..15]

IDE_DA[0..2]

& lt; 21 & gt; IDE_DA[0..2]

KEYBOARD CONN.
KSI[0..7]
KSO[0..15]
+5VS

KSI[0..7]

& lt; 29,34 & gt;

KSO[0..15] & lt; 29,34 & gt;

C621
C621

1

B

ODD CONN

2

10U_0805_10V4Z

ACES_88170-3400

1
C622
C622

1
C623
C623

1
C624
C624

2

0.1U_0402_16V4Z
2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

Place Components closely to ODD Conn.

& lt; 21 & gt; IDE_DCS1#
2
+5VS
R500
R500

1

R501
2 R501
1
470_0805_5%

1
C691
@ 100P_0402_50V8J

2

GND

A

GND

& lt; 21 & gt; IDE_DIOW#
& lt; 21 & gt; IDE_DIORDY
& lt; 21 & gt; IDE_IRQ

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

52

& lt; 21 & gt; ODD_RST#

@ 100P_0402_50V8J
2
1
C698
JP26
JP26
2
1
11
C699
3
@ 100P_0402_50V8J 3
55
IDE_DD7
77
IDE_DD6
99
IDE_DD5
11 11
IDE_DD4
13 13
IDE_DD3
15 15
IDE_DD2
17 17
IDE_DD1
19 19
IDE_DD0
21 21
23 23
IDE_DIOW#
25 25
IDE_DIORDY
27 27
IDE_IRQ
29 29
IDE_DA1
31 31
IDE_DA0
33 33
IDE_DCS#1
35 35
100K_0402_5%
37 37
39 39
+5VS
41 41
+5VS
43 43
45 45
SEC_CSEL
47 47
49 49

51

C915
C915
680P_0402_50V7K

1
C688
1
C689

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

IDE_DD8
IDE_DD9
IDE_DD10
IDE_DD11
IDE_DD12
IDE_DD13
IDE_DD14
IDE_DD15
IDE_DDREQ
IDE_DIOR#

2
@ 100P_0402_50V8J
2
@ 100P_0402_50V8J

IDE_DDREQ & lt; 21 & gt;
IDE_DIOR# & lt; 21 & gt;

IDE_DDACK#

IDE_DDACK#

& lt; 21 & gt;

IDE_PDIAG#
1
2
+5VS
IDE_DA2 100K_0402_5% R499
R499
IDE_DCS#3
IDE_DCS3# & lt; 21 & gt;
W=80mils
+5VS
+5VS
+5VS
2
1

1
2
C702 @ 100P_0402_50V8J

34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
JP35

1
2
R534 300_0402_5%

KSO2
KSO1
KSO0
KSO4
KSO3
KSO5
KSO14
KSO6
KSO7
KSO13
KSO8
KSO9
KSO10
KSO11
KSO12
KSO15
KSI7
KSI2
KSI3
KSI4
KSI0
KSI5
KSI6
KSI1
CAPS_LED#
Cursor_LED
NUM_LED#

+3VS

1
2
R838 300_0402_5%

+3VS

2
1
R535 300_0402_5%

+3VS
CAPS_LED# & lt; 29 & gt;
Cursor_LED & lt; 29 & gt;
NUM_LED# & lt; 29 & gt;

2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J

1 KSO14
C651
1 KSO11
C653
1 KSO9
C655
KSI7
1
C657
1 KSO7
C659
KSI4
1
C661
KSI5
1
C663
1 KSO5
C665
KSI0
1
C667
1 KSO1
C669
KSI2
1
C671
1 KSO4
C673
1 Cursor_LED
C675

2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J
2
100P_0402_50V8J

B

For EMI Request

20070718 change new KB define

A

C625
C625 0.1U_0402_16V4Z

2

Compal Secret Data

Security Classification

1
C690
@
100P_0402_50V8J

OCTEK_CDR-50JL1G

2006/08/05

Issued Date

Deciphered Date

2007/08/05

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

NUM_LED# 1
C650
CAPS_LED# 1
C652
KSO15
1
C654
KSO10
1
C656
KSO8
1
C658
KSO13
1
C660
KSO3
1
C662
KSO12
1
C664
KSI6
1
C666
KSO6
1
C668
KSI3
1
C670
KSO0
1
C672
KSI1
1
C674
KSO2
1
C676

4

3

2

Compal Electronics, Inc.
SATA & ODD
Document Number

Rev
2.0

LA-3481P
Tuesday, May 22, 2007

Sheet
1

32

of

47

5

4

+5VALW

@ 0_0603_1%
R502

Camera@

0_0603_1%

2

USB CONN. 1

+3VS
+USB_VCCC
C626 Camera@
0.1U_0402_16V4Z

USB20_N8 & lt; 22 & gt;
USB20_P8 & lt; 22 & gt;

1

1

2
0.1U_0402_16V4Z

2

C639
C639
1000P_0402_50V7K
D

ACES_85201-0505
& lt; 22 & gt;
& lt; 22 & gt;

1
2
3
4
5
6

USB20_N4
USB20_P4

USB20_N4
USB20_P4

3

3

C638
C638

JP31
JP31

1

D25
PSOT24C_SOT23
@

1

CIR

+

2

D24
SM05_SOT23
@

D38
@
SM05_SOT23

ACES_88266-05001
Camera@

3

1
2
3
4
5
6
7

2

+5VALW

+5VALW

VCC
DD+
GND
GND
GND

GND
GND

7
8

P-TWO_CU304D-A0G1G-P

+USB_VCCC

CIR@
R503
100_0805_5%

2

U29

2

3

GND

2
CIR_IN

C

C629
4.7U_0805_10V4Z
CIR@

1

VCC

1

Vout

4

& lt; 29 & gt;

C637

GND
IN
IN
EN#

OUT
OUT
OUT
FLG

8
7
6
5

USB CONN.2

G528_SO8

+USB_VCCC

GND

& lt; 29 & gt;

1

USB_EN#

USB_EN#

W=60mils

150U_D_6.3VM
C642

IRM-V538/TR1_3P
CIR@

+

2

C643
C643

1

1

2
0.1U_0402_16V4Z

2

C644
C644
1000P_0402_50V7K

C

JP33
JP33
USB20_N5
USB20_P5

1
2
3
4
5
6

USB20_N5
USB20_P5

3

& lt; 22 & gt;
& lt; 22 & gt;

2

1

U30

1
2
3
4

1U_0805_16V7K

1
2
3
4
5
GND1
GND2

150U_D_6.3VM
C636

5
4
3
2
1

USB20_N6
USB20_P6

2

& lt; 22 & gt;
& lt; 22 & gt;

1

FP@
JP28

2
FP@

JP27

W=60mils

1

C627
0.1U_0402_16V4Z

D

1

Fingerprint Conn

W=20mils

+CAM_VDD
1

R951

2

1

+5VS

3

2

Int. Camera Conn

D26
PSOT24C_SOT23
@

GND
GND

7
8

P-TWO_CU304D-A0G1G-P

1

BlueTooth Interface

VCC
DD+
GND
GND
GND

+3VS

2

+5VS

S

2
G

BT_PWR

3

1000P_0402_50V7K
BT@

Q18
2N7002_SOT23-3
BT@

USB Small Board

Q17
BT@AO3413_SOT23

B

+BT_VCC
+5VALW

Module ID
Indication for polarity of reset
Reset input High Active -- & gt; Low ,
Reset input Low Active -- & gt; Open
JP30

2
0_0402_5%

BT@
A

0.1U_0402_16V4Z

C634

4.7U_0805_10V4Z

& lt; 31 & gt; WLAN_BT_DATA
(MAX=200mA)
+BT_VCC
C931
1
2
+3VS
R925
@
4.7K_0402_5%
BT@
0.1U_0402_16V4Z
C635
C635
BT@

2

BT_RST#

1
R730

1

& lt; 22 & gt; USB20_P7
& lt; 22 & gt; USB20_N7
& lt; 31 & gt; WLAN_BT_CLK
& lt; 22 & gt; BT_DET#
& lt; 29 & gt;

+USB_VCCA
U31

1
2
3
4
5
6
7
8
9
10

2

1
2
3
4
5
6
7
8
9
10

C876

& lt; 29 & gt;

USB_EN#

1

1U_0805_16V7K

& lt; 29 & gt;

1

1

1
1
3

C631
D

C630
0.1U_0402_16V4Z
BT@

G
G

B

2

D
D

R507
1
2
BT@ 100K_0402_5%
2

S

R506
1M_0402_5%
BT@

1
2
3
4

GND
IN
IN
EN#

OUT
OUT
OUT
FLG

8
7
6
5

+USB_VCCA

G528_SO8
JP32

USB_EN#

& lt; 22 & gt;
& lt; 22 & gt;

ACES_87213-1000
BT@

USB20_P1
USB20_N1

& lt; 22 & gt;
& lt; 22 & gt;

1
2
3
4
5
6
7
8
9
10
11
12

USB20_P0
USB20_N0

BT@
R926
4.7K_0402_5%

ACES_85201-1205
A

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2006/08/05

Issued Date

Deciphered Date

2007/08/05

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

USB Conn./BT/Camera/CIR
Document Number

Rev
2.0

LA-3481P
Tuesday, May 22, 2007

Sheet
1

33

of

47

4

ON/OFF BUTTON
+3VALW

+3VALW
1

100K_0402_5%
1
1
& lt; 29 & gt;

D

EC_ON

S

1

R537
R537
10K_0402_5%

0_0402_5%
@ R933
2

D41
D41
2

1
HT-191UD_AMBER_0603

10K

2

1

2
0_0402_5%

1

Sattlate_LED# & lt; 29 & gt;

Q58

+5VALW

R592
R592

BATT_CHG_LOW_LED# & lt; 29 & gt;

BATT_FULL_LED#
1
HT-191NB_BLUE_0603

2
2
120_0402_5%

4
SMT1-05_4P

1
R839
SAT@

2
2
120_0402_5%

MODE#

C683
33P_0402_50V8J
@

D34
DAN202U_SC70

ON/OFF
IEBTN#
KSO0
MODEBTN#
EC_PLAYBTN#
EC_STOPBTN#
EC_FRDBTN#
EC_REVBTN#
BUTTON_ID

KSO0

1
2
3
4
5
6
7
8
9
10
11
12

SAT@
1

1
R934

2

IEBTN# 1
1

& lt; 29 & gt;

51_ON#

3

& lt; 29,32 & gt;
KSI1
& lt; 29,32 & gt;
KSI2
& lt; 29,32 & gt;
KSI3
& lt; 29,32 & gt;
KSI5
& lt; 29 & gt; BUTTON_ID

D58

BATT_FULL_LED# & lt; 29 & gt;

2

2

2
B
1
3
Q80
MMBT3904_SOT23 @

SAT@

D44
D44
1
R594
R594

1

12-21-BHC-ZL1M2RY-2C_BLUE
BATT_CHG_LOW_LED#
1
HT-191UD_AMBER_0603

2

1

& lt; 29,32 & gt;

VF=2.8V

2
2
120_0402_5%

D

2

IE_BTN#

& lt; 29 & gt;

51_ON#

3

D35
DAN202U_SC70

JP37
JP37

C

1
R717
SAT@

14

3

SMT1-05_4P

SB_Sattlate_LED# & lt; 22 & gt;
D47

D43
D43

13

E & T_6701-Q12N-00R

1

4

C682
33P_0402_50V8J
@

SAT@

BATT CHARGE/FULL LED

1 G1
2
3
4
5
6
7
8
9
10
11
12 G2

SW/LED Connector

R901 SAT@

SAT@

2
2
300_0402_5%

SW_R

3

MODEBTN#
1

1
HT-191NB_BLUE_0603

C

SW4

1

E

2

1

SW_L

2

D42
D42
PWR_LED_0#

SW_R

3

& lt; 29,36 & gt;

1

1
ACIN

TP_DATA
TP_CLK

SW_L

SW3

RLZ20A_LL34

47K

POWER/SUSPEND LED
PWR_SUSPLED1#

2
0.01U_0402_25V7K

& lt; 29 & gt;
& lt; 29 & gt;

TP_DATA
TP_CLK

TP Button
D37

Satellite LED

S

1

2
G

1
HT-191NB_BLUE_0603

DTA114YKA_SOT23

2
2
120_0402_5%

Q50
3 2N7002_SOT23-3

D

D46
D46
1
R596
R596

C692
C692

+5VS

AC IN LED
+5VALW

1

Q25

2
G

6
5

2

C649

TP_CLK

& lt; 36 & gt;

1
2
3
4
5
6
7
8
9
10
11
12

+5VS

2

2

51_ON#

DAN202U_SC70

3

1

& lt; 29 & gt;

2

2

NC

ON/OFFBTN# & lt; 29 & gt;
51_ON#

2N7002_SOT23-3

2
NC

LID_SW#

10P_0402_50V8J

4

TP_DATA

2
1
3

LID_SW#

1

GND

1

VDD OUTPUT

3

C648
C648

0.1U_0402_16V4Z

5

D36
ON/OFF

2@
33P_0402_50V8J
2@
33P_0402_50V8J
2@
33P_0402_50V8J
2@
33P_0402_50V8J

1
C677
1
C678
1
C679
1
C680

SW_L
R524
47K_0402_5%

1

JP36
JP36
SW_R
R536
R536

U35
A3212EEH_MLP6

D

2

TP CONN.

2

Lid SW

3

+3VALW

6
5

5

2
0_0402_5%

1
2
3
4
5
6
7
8
9
10
GND
GND

EC_PLAYBTN#
EC_STOPBTN#
EC_FRDBTN#
EC_REVBTN#

2@
33P_0402_50V8J
2@
33P_0402_50V8J
2@
33P_0402_50V8J
2@
33P_0402_50V8J

1
C685
1
C687
1
C684
1
C686

C

For EMI

ACES_85201-1005N
12-21-BHC-ZL1M2RY-2C_BLUE

3G LED

HDD LED
S

1
R595
R595

2
2
1
1
120_0402_5%
HT-191NB_BLUE_0603

3

+3VS

2N7002_SOT23-3
Q54

3

2N7002_SOT23-3
Q55

2
G

1

1

D

R905
2 R905
1
100K_0402_5%

S

2
G

+5VS

D

D45
D45

@

HDD_LED# & lt; 21 & gt;
2

120_0402_5%
R716

WL & BT LED
1
2
2
R591 KS@ 300_0402_5%

SPI Flash (8Mb*1)

VF=1.9V
1
KS@HT-191UD_AMBER_0603

WL_BT_LED# & lt; 29 & gt;

2

D40
+5VALW

D49
HT-191NB_BLUE_0603
@

+5VALW

+3VALW
C681

3

47K

10K

2

PWR_SUSP_LED & lt; 29 & gt;

0.1U_0402_16V4Z

& lt; 29 & gt; FSEL#SPICS#

1

Q46
DTA114YKA_SOT23
R593
R593 1

& lt; 29 & gt; EC_SPICLK

2 300_0402_5%

& lt; 31 & gt;

PWR_SUSPLED1#

W=20mils
U52

3G_LED#

& lt; 29 & gt; FRD#SPI_SO

FSEL#SPICS# 1
R870
R870
EC_SPICLK
1
R871
R871
2
0_0402_5%

8

HOLD
S

6

C

5

SPI_CS#
2
0_0402_5%
SPI_CLK_R
2
0_0402_5%
SPI_SO
1
R873
R873

VSS

D

4

Q

2

B

W

1

2

VCC

3
7

VF=2.8V

1

B

1

SPI_SI
2
0_0402_5%

1 FWR#SPI_SI
R872
R872

FWR#SPI_SI & lt; 29 & gt;

SST25LF080A_SO8-200mil
+5VALW
47K

3

JP49
SPI_CS#
SPI_SI

10K

2

1
3
5
7

+3VALW

POWER_LED# & lt; 29 & gt;

1
3
5
7

2
4
6
8

2
4
6
8

+3VALW
SPI_CLK_R
SPI_SO

PWR_LED_0#

+5VALW

+5VALW
A

0.1U_0402_16V4Z C646
C646
1
2

EEPROM

1

A

R521
R521
U34

& lt; 29,37 & gt; EC_SMB_CK1
& lt; 29,37 & gt; EC_SMB_DA1

8
7
6
5

VCC
WP
SCL
SDA

100K_0402_5%
A0
A1
A2
GND

1
2
3
4

R523
R523

2

1

@ E & T_2941-G08N-00E~D
Q48
DTA114YKA_SOT23
1
2
R597
R597
120_0402_5%

AT24C16AN-10SU-2.7_SO8~N

1

2
100K_0402_5%

2006/08/05

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2007/08/05

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

EEPROM/TP/LID/KB/LED/SW-B
Document Number

Rev
2.0

LA-3481P
Saturday, June 23, 2007

Sheet
1

34

of

47

B

C

+1.8VS

R806
2 R806
1
100K_0402_5%

3VS_GATE
1

+VSB
1

D

2

Q30
2N7002_SOT23-3

2

Q64
2N7002_SOT23-3

2
G
3

S

SUSP
0.1U_0603_25V7K

C896
C896

2

S

18@

18@

2

1

2

@
470_0805_5%
R559

D

1

2N7002_SOT23-3
Q36
@
S

1.8VS_GATE

2
G

SUSP

1
C723
18@
Q37
0.1U_0603_25V7K
2N7002_SOT23-3 2
18@

D

S

2
G

2

2

D

470_0805_5%
R564
R564
1

470_0805_5%
R563
R563
1

1

+0.9VS

Q38 S

1

1

D

Q40

S

D
2 SUSP
G
2N7002_SOT23-3

Q41 S

2 SUSP
G
2N7002_SOT23-3

2

2 SUSP
G
2N7002_SOT23-3

3

3

Q39 S

SYSON#
2
G
Q42 S @ 2N7002_SOT23-3

3

S

D
2 SUSP
G
2N7002_SOT23-3

1

2

D

Q27
2N7002_SOT23-3

R551
100K_0402_5%

2

470_0805_5%
R561

3

S

R557
100K_0402_5%

+1.05VS

D

2
G

1

3

SYSON

& lt; 27,29,30,40 & gt; SYSON

+1.5VS

1

Q32
2N7002_SOT23-3

1

1

D

2
G

SUSP#
1

9,30,38,40,41,42 & gt;

3

1

2

@
470_0805_5%
R565

2

2
470_0805_5%
R562
R562
1

SYSON#

+1.8V

3

SUSP

1

1

R547
R547
100K_0402_5%

2

+2.5VS

SUSP

18@ 2

SI4856ADY_SO8

C720

+5VALW

R554
R554
100K_0402_5%

& lt; 42 & gt;

SUSP

0.1U_0603_25V7K

1

SI4856/AO4430

R560 18@
2
1
84.5K_0402_1%

1

+5VALW
2

3

2
G

1
2
3
4

S
S
S
G

2

SUSP

1U_0603_10V4Z

D
D
D
D

1

Q33 SUSP
2
2N7002_SOT23-3
G
@

@

8
7
6
5

3

C708
C708

3

S
+VSB

18@ 2

D

1
C722

2
1U_0603_10V4Z

1

10U_0805_10V4Z

2

1

10U_0805_10V4Z

AO4422_SO8

AOS 4422

C711
C711

@
470_0805_5%
R555
C721

1

2

1
2
3
4

C710
C710

S
S
S
G

11

2

D
D
D
D

10U_0805_10V4Z

C715
@

10U_0805_10V4Z

Q29 SUSP
2
G
2N7002_SOT23-3
@

1

8
7
6
5

U40

1

S
1

D

2

D

5VS_GATE

2
1
R552 47K_0402_5%

10U_0805_10V4Z

2
2
1U_0603_10V4Z

1
C714
C714

2

& lt; BOM Structure & gt;

1

1

AO4422_SO8

AOS 4422

C701
C701

@
470_0805_5%
R548

1

1

3

2

1
2
3
4

S
S
S
G

10U_0805_10V4Z

@

D
D
D
D

C700
C700

C705

1

1

+VSB

10U_0805_10V4Z

1

2

10U_0805_10V4Z

C704
C704

1

+1.8V

+3VS
U38
U38

1

+3VALW

3

+5VS
U36
8
7
6
5

E

+1.8V to +1.8VS

10U_0805_10V4Z

+5VALW

D

+3VALW TO +3VS

C719

A

+5VALW TO +5VS

Debug Port
New LPC Debug Pad ---- MB side For EE
H1

5

SERIRQ

7

4

2
R540
R540
0_0402_5%
PCI_RST#

8

3

LPC_AD2

2

LPC_DRQ#1 & lt; 21 & gt;
PCI_RST# & lt; 20,24,29 & gt;
U13B
LPC_AD2 & lt; 21,29 & gt;
6

& lt; 21,29 & gt; LPC_AD1

LPC_AD1

& lt; 21,29 & gt; LPC_FRAME#

LPC_FRAME#

9

2

10

LPC_AD0

1

LPC_AD0 & lt; 21,29 & gt;

CLK_PCI_SIO2

1

DEBUG_PAD-MB

A

4

B

5

O

SN74LVC08APW_TSSOP14

CLK_PCI_SIO & lt; 16 & gt;

R544
R544
@

14

1
R542
R542
0_0402_5%

LPC_AD3

3

1

P

& lt; 22,24,29 & gt; SERIRQ
& lt; 21,29 & gt; LPC_AD3

6

E51_TXD & lt; 29,31 & gt;

LPC_DRQ#1

G

& lt; 29,31 & gt; E51_RXD

R538
@ 0_0402_5%
2 E51_TXD

7

3

1

+3VALW
R539
@ 0_0402_5%
E51_RXD
1
2

C694
C694
21

2

10_0402_5% 10P_0402_50V8J

Under DDR ME Assigment Area

4

Keep Resistor near Debug Pad and in the same side
Reverse Side DIMM ---- Pin 1 keep away DIMM

4

Compal Secret Data

Security Classification
2006/08/05

Issued Date

2007/08/05

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Compal Electronics, Inc.
DC/DC I/F & Debug Pad
Document Number

Rev
2.0

LA-3481P
Sheet

Tuesday, May 22, 2007
E

35

of

47

A

B

C

D

VS
VIN

1
PR2
PR2
5.6K_0402_5%
2
-

4

LM393DG_SO8

2

PC6
PC6
0.1U_0402_16V7K

2
0.068U_0402_10V6K

2

1
PR8
PR8
10K_0402_1%

2

VIN

PR10
PR10
68_1206_5%

N1

3

1
2
PR11
PR11
1K_1206_5%

2

2

PR12
PR12
200_0603_5%
1
2

1

VS

1

1

1

PD4
PD4
2

1

N3

RLS4148_LLDS2

1
2
PR13
PR13
1K_1206_5%

B+

2

2

2

2

PC7
PC7
0.22U_1206_25V7K

2

PR14
PR14
100K_0402_1%

VIN

PC8
PC8
0.1U_0603_25V7K

2

1

2
PR15
PR15
22K_0402_1%

51_ON#

High 18.384 17.901 17.430
Low 17.728 17.257 16.976

1
PR9
PR9
68_1206_5%
PQ1
PQ1

& lt; 34 & gt;

1

Vin Detector

RTCVREF

3.3V

PD2
PD2
RLS4148_LLDS2

1

1

RLS4148_LLDS2

CHGRTCP

& lt; 22,29,38 & gt;

1

PD3
PD3
2

BATT+

PACIN

PR7
PR7
10K_0402_1%

PD1
PD1
RLZ4.3B_LL34

2

2

PC5
PC5

PACIN

1

O

1

1
1

PR6
PR6
20K_0402_1%

& lt; 29,34 & gt;

1

+

2

1

3

ACIN

PU1A
PU1A

1

@ SINGA_2DW-0005-B03

PR4
PR4
10K_0402_1%
1
2

P

PC4
PC4
100P_0402_50V8J

8

PR5
PR5
22K_0402_1%
1
2

2

PC3
PC3
1000P_0402_50V7K

2

2

PC2
PC2
100P_0402_50V8J

1

4

1

3

-

PC1
PC1
1000P_0402_50V7K

2

-

1

2

2

+

VS
PR3
PR3
84.5K_0402_1%

10A_125V_451010MRL

1

1

+

2

DC_IN_S2

2

PJP1

G

1

1

DC_IN_S1

PR1
PR1
1M_0402_1%
1
2

VIN

PL1
PL1
HCB4532KF-800T90_1812
1
2

PF1
PF1

1
2
PR16
PR16
1K_1206_5%

TP0610K-T1-E3_SOT23-3

PR20
PR20
499K_0402_1%

LM393DG_SO8

2
2

1 VL

PR23
PR23
34K_0402_1%

PC13
PC13
1000P_0402_50V7K

1

6

PR25
PR25
66.5K_0402_1%
2

PC12
PC12
1000P_0402_50V7K

5

-

PR24
PR24
499K_0402_1%
PR26
PR26
191K_0402_1%

PC11
PC11
1000P_0402_50V7K

2

RB715F_SOT323-3

+

O

2

3

1

7

1

ACON

1

1

& lt; 38 & gt;

PU1B
PU1B

2

2

& lt; 4,37,39 & gt; MAINPWON

PD5
@ RLZ16B_LL34
2

PC10
PC10
1U_0805_25V4Z

8

PD6
PD6

1

1
2

1
2

GND
PC9
PC9
10U_0805_6.3V6M

P

N2

G

2

4

IN

1

OUT

2

3

PR19
PR19
2.2M_0402_5%
2
1

2

3.3V

PR18
PR18
100K_0402_1%
1
2

1

VL

PU2
PU2 G920AT24U_SOT89-3

1

+CHGRTC

PR22
PR22
560_0603_5%
1
2

2

PR17
PR17
200_0603_5%
PR21
PR21
560_0603_5%
1
2

1

1

RTCVREF

3

3

PJ1
PJ1

2

1

1

2

+1.8VP

PJ4
PJ4
2
@

2

1

+5VALW

1

1

+1.8V

PR27
PR27
47K_0402_1%
2
1

D

2
G

2

2

PQ3
PQ3
DTC115EUA_SC70-3

+1.25VS

1

1

RHU002N06_SOT323-3

2

@ JUMP_43X118
1

1

+VSB

+5VALWP

(3.0A,120mils ,Via NO.=6)
3

@ JUMP_43X39

PACIN

S

PJ5
PJ5
+1.25VSP

PJ6
2

2

(12A,480mils ,Via NO.= 24)

JUMP_43X118

2

PQ2

Precharge detector
15.97V/14.84V FOR
ADAPTOR

@ JUMP_43X118
1

(5A,200mils ,Via NO.= 10)
+VSBP

1

PJ3
PJ3

(5A,200mils ,Via NO.= 10)
+5VALWP

2

@ JUMP_43X118

+3VALW

JUMP_43X118

1

2
@

1

PJ2
PJ2
+3VALWP

1

3

2

PJ7

(120mA,40mils ,Via NO.= 2)
+0.9VSP

2

2

1

1

+0.9VS

@ JUMP_43X79
PJ8
PJ8
2

2

(2A,80mils ,Via NO.= 4)
1

1

@ JUMP_43X118

PJ9
PJ9
+1.5VSP

PJ10
PJ10
4

+1.05VSP

2

2

1

1

@ JUMP_43X118

2

1

1

+1.5VS

@ JUMP_43X118

+1.05VS

(10A,400mils ,Via NO.= 20)

2

4

(6.0A,240mils ,Via NO.=12)

PJ11
+2.5VSP

2

2

1

1

+2.5VS

Issued Date

(0.35A,40mils ,Via NO.=2)

Compal Electronics, Inc.

Compal Secret Data

Security Classification

@ JUMP_43X39

2006/05/18

Deciphered Date

2007/05/18

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

DCIN & DETECTOR
Document Number

Rev
2.0
Sheet

Tuesday, May 22, 2007
D

36

of

47

A

B

C

D

PH1 under CPU botten side :
CPU thermal protection at 92 degree C
Recovery at 56 degree C
VS

VL
2

VL
VMB

PR28
PR28
47K_0402_1%

1
PC14
PC14
0.1U_0603_25V7K

PR31
PR31
47K_0402_1%
1
2

PR33
PR33
1K_0402_1%

PC15
PC15
1000P_0402_50V7K

PC16
PC16
0.01U_0402_25V7K

8
3

+

2

TM_REF1

-

PU3A
PU3A
2

1

2

1SS355_SOD323-2

1

VL

PR37
PR37
100K_0402_1%
1

2

1

3

4

LM393DG_SO8

2

PR39
PR39
100K_0402_1%
2

1

+3VALWP

PC18
PC18
1000P_0402_50V7K

1

1
2

PR36
PR36
15.4K_0402_1%

PR38
PR38
6.49K_0402_1%
2
1

2

& lt; 29,38 & gt;

1

1

ALI/MH#

PC17
PC17
0.22U_0805_16V7K

2

2

2

PR35
PR35
100_0402_1%

PD7
PD7
1

O

@ OCTEK_BTJ-09HA1G

PR34
PR34
100_0402_1%

1

PQ4
PQ4
DTC115EUA_SC70-3

P

1

PR32
PR32
13.7K_0402_1%
1
2

MAINPWON & lt; 4,36,39 & gt;

G

1

1

2

+3VALWP

1

PH1
PH1
100K_0603_1%_TH11-4H104FT

1

BATT+

2

PL2
PL2
HCB4532KF-800T90_1812
1
2

2

GND
GND

BATT_S1

1
2
3
4
5
6
7
8
9

2

10
11

1
2
3
4
5
6
7
8
9

1

PF2
PF2
15A_65V_451015MRL
1
2
PR29
PR29 1K_0402_1%
1
2
1
2
PR30
PR30
47K_0402_1%

PJP2
1

2

PR40
PR40
1K_0402_1%

PH2 near main Battery CONN :
BAT. thermal protection at 92 degree C
Recovery at 47 degree C

BATT_TEMPA & lt; 29 & gt;
2

EC_SMB_DA1 & lt; 29,34 & gt;

2

EC_SMB_CK1 & lt; 29,34 & gt;

8
-

1

PD8
PD8
O

4

PR44
PR44
20K_0402_1%

PU3B
PU3B
7

2

G

1

+

6

P

5
TM_REF1

1
PC19
PC19
0.22U_0805_16V7K

@

2

1
2
2

1
2

PC20
0.22U_1206_25V7K

PR43
PR43
15K_0402_1%
1
2

1
1SS355_SOD323-2

LM393DG_SO8

D

S

PQ6
RHU002N06_SOT323-3

2
G

2

3

@

PR42
PR42
47K_0402_1%
1
2

2
1

PR48
PR48
0_0402_5%
2

3

1

POK

1

& lt; 39 & gt;

PC22
0.1U_0402_16V7K

1
2
PR47
PR47
100K_0402_1%

VL

2
1
PR45
PR45
100K_0402_1%

PR46
PR46
22K_0402_1%
1
2

+VSBP

1
PC21
0.1U_0603_25V7K

3

B+

PR41
PR41
47K_0402_1%

PH2
PH2
100K_0603_1%_TH11-4H104FT
2

PQ5
PQ5 TP0610K-T1-E3_SOT23-3

2

VL

1

VL

3

@

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2006/05/18

Deciphered Date

2007/05/18

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

BATTERY CONN / OTP
Document Number

Rev
2.0
Sheet

Tuesday, May 22, 2007
D

37

of

47

A

B

C

D

PQ19

75W Iadapter=0~3.947A PR49=0.02 ohm CP=3.71A PR66=10.7K

@ AO4407_SO8
1
2
3

90W Iadapter=0~4.737A PR49=0.015 ohm CP=4.459A PR66=19.6K
P3

B+

3

PJ13
PJ13
2

PR49
PR49
0.02_2512_1%

@

2

1

1

2

1

2

21

5

ICOMP

CSIN

20

VCOMP

CSIP

19

7

ICM

PHASE

18

VREF

UGATE

17

1

ACOFF 2

0.1U_0603_25V7K

D
D
D
D

2
G

6251VDDP

RHU002N06_SOT323-3

2

4

2

CH751H-40PT_SOD323-2
PD10
PD10
1
26251VDD
4.7_0603_5%
PR67
PR67

PC37
PC37
4.7U_0805_6.3V6K

BATT+

3

PR62
PR62
0.02_2512_1%
PQ18
PQ18
SI4800BDY-T1-E3_SO8

PC38
PC38

DL_CHG

ISL6251AHAZ-T_QSOP24

PACIN

SI4800BDY-T1-E3_SO8

PL3
PL3
16UH_D104C-919AS-160M_3.7A_20%
CHG
1
2
1

PC36
PC36
BST_CHGA 2
1
0.1U_0603_25V7K

PQ20

S

G
S
S
S

14

PGND

BST_CHG 1
2
2.2_0603_5%

13

GND

D

PC109
PC109

2

LGATE

2
1

5
6
7
8

2

4
3
2
1
VADJ

12

DTC115EUA_SC70-3

5
6
7
8

VDDP

15

VIN

200K_0402_1%

D
D
D
D

16

ACLIM

11

PR69
2 PR69
1
10K_0402_1%

2

PQ41
PQ41
DTC115EUA_SC70-3

BOOT

CHLIM

10

2

PR68
PR68
10K_0402_1%

1

ACON

ACON

10.7K_0402_1%
6251VREF 1 PR66
PR66
2

1

PQ16
PQ16

G
S
S
S

RHU002N06_SOT323-3
& lt; 36 & gt;

PR63
PR63
9

0.1U_0402_16V7K

2

15.4K_0402_1%

2

4
3
2
1

PR65
PR65
1

IREF

S

PR61
@ 0_0402_5%

2

& lt; 29 & gt;

PC35
PC35
1
2

1

2
G

1

PACIN 1
2
PR64
PR64
22K_0402_1%

3

& lt; 22,29,36 & gt; PACIN

ADP_I

2

1

& lt; 29 & gt;
D PQ17

1

DH_CHG

1

2

2

PD15
PD15
1SS355_SOD323-2

CSOP

LX_CHG

8

PR60
1 PR60
2
100_0402_1%
6251VREF

PQ14
PQ14

PC32
PC32 0.1U_0603_25V7K
1
2
PR135
PR135 2.2_0603_5%

1

2

0.01U_0402_25V7K

PR72
PR72
1

1

CSOP

& lt; 29 & gt;

PC39
PC39

2

CELLS

2 CSON
20_0603_5%

3

4

6

PR59
1 PR59
2
10K_0402_1%
1
2
PC34
PC34
100P_0402_50V8J

1

PC29
PC29
1U_0603_16V6K
1
2
PR56
PR56 20_0603_5%
PR57
PR57 20_0603_5%
2
1

3

1

PC33
PC33
1
2

S

ACOFF

1

2

1

CSON

2

1SS355_SOD323-2

ACOFF#
PR185
PR185

1
2
PC31
PC31 6800P_0402_25V7K

PR58
PR58
150K_0402_1%

0.1U_0603_25V7K

10U_1206_25V6M

22

1

BATT+

10U_1206_25V6M

EN

2

1

1

1

ACSET ACPRN

DCIN 1

23

3

PC30
@ 680P_0402_50V7K
CSON1
2

PQ13
PQ13

3

1
3

24

VDD

PC105
PC105

PQ12
PQ12
DTC115EUA_SC70-3

2

& lt; 29,37 & gt; ALI/MH#

PD14
PD14

10K_0402_1%
DCIN

2

2

1

6251VDD 1

VIN

PU4
PU4

PC27
PC27
1
2.2U_0603_6.3V6K

1

PR53
2 PR53
1
0_0402_5%

FSTCHG

1

& lt; 29 & gt;

PR55
PR55
10K_0402_1%

RHU002N06_SOT323-3

4.7U_1206_25V6K

4.7U_1206_25V6K

1

2

4.7U_1206_25V6K

2

1
2

1
2

2

PC142
PC142
5600P_0402_25V7K
6251VDD

PC26
PC26
0.1U_0603_25V7K

DTC115EUA_SC70-3

D

1

PR51
PR51
47K_0402_1%
1
2
PR54
PR54

DTA144EUA_SC70-3

PQ15
2
G

PC25
PC25

PC23
PC23

6251_EN
2

PC24
PC24

8
7
6
5
4

4

4
3

1

PR50
PR50
200K_0402_1%

PR52
PR52
47K_0402_1%
2

1
2
3

CSIN

1

PQ11
PQ11

PQ7
PQ7
AO4407_SO8

B++
CSIP

JUMP_43X118

2

8
7
6
5

2

1
2
3

1

1
2
3

1

8
7
6
5

VIN

4

2

PQ9
PQ9
AO4407_SO8

2

P2

8
7
6
5

3

1
PQ8
PQ8
AO4407_SO8

120W Iadapter=0~6.315A PR49=0.010 ohm CP=5.936A PR66=19.6K

4

Iadp=0~3.6A

PR70
3

1

1

3

6251VREF

1

@

2

28.7K_0402_1%

PR71
PQ40
PQ40

2

2

@ 47K_0402_1%
@ SI2301BDS-T1-E3_SOT23-3

BATT Type

IREF=1.016*Icharge
IREF=0.508V~3.048V

ALI/MH#

Charge Current

CC=0.5~3A
CV=12.6V(6 CELLS LI-ION)

IREF

3 CELL

3.3V

1.5.A

1.524V

6 CELL

3.3V

3.0A

3.048V

9 CELL

3.3V

3.0A

3.048V

3

3

VS

3FSTCHG
1
& lt; 19,27,29,30,35,40,41,42 & gt;

RB715F_SOT323-3
PR184
PR184
P
BATT_OVP

1

2

1

10K_0402_1%

-

2

LM358DT_SO8

1

PR133
PR133

4

6251_EN

PU5A
PU5A
3

+

0
G

& lt; 29 & gt;

2

100K_0402_1%

1

8

DTC115EUA_SC70-3

6251VREF

LI-3S :13.5V----BATT-OVP=1.5V
BATT-OVP=0.111*BATT+

2

SUSP#

1

1

PC96
PC96
CSON

2

4

2

C PQ31
@

2
B

4

2SC2411KT146_SOT23-3

1

3

E
0.01U_0402_25V7K

PC41
PC41
0.01U_0402_25V7K

2

100K_0402_1%
2

2

PR132
PR132
1

3

2

2

2

1
PR75
PR75
105K_0402_1%

1

PD9
PD9

0.1U_0603_25V7K

1

2

1
PR131
PR131
100K_0402_1%

PQ29
PQ29

PC28
PC28

PC40
PC40
0.01U_0402_25V7K

DCIN

1

1

3

P3

2

TP0610K-T1-E3_SOT23-3

1
2
1
PR74
PR74
PR73
PR73
499K_0402_1% 340K_0402_1%

VMB
PQ10
PQ10

PR134
PR134

2006/05/18

Deciphered Date

2007/05/18

Title

2

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

20K_0402_1%

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

CHARGER
Document Number

Rev
2.0

Tuesday, May 22, 2007

Sheet
D

38

of

47

5

4

3

2

1

PJ18
PJ18

2

1

1

DRVL2

VO1

PGND2

VFB1
COMP1
COMP2
CS1
CS2
VREF2
TONSEL
GND
PGOOD1
PGOOD2

EN3

2

2

1

RLZ5.1B_LL34

B

TPS51120_CS1
TPS51120_CS2

2

TPS51120RHBR_QFN32_5X5

+

2

C

1
2

+VCC_TPS51120

1

1

+3VALWP
PR90
PR90
100K_0402_1%
1
2

1

2

10K_0402_1%

FB5

PR85
PR85
10K_0402_1%

PC56
PC56
10U_0805_6.3V6M
2
1

PR89
2 1 PR89

PC58
2.2U_0805_25V6K

1
2

806K_0603_1%

PD11
PD11

1

33

VREG3

+3.3V_RTC_LDO

VS

1
2

EN2
EN1

19

32

0_0402_5%

3
2
7
23
18
4
31
5
30
11

1

@

1

PAD

VFB2

SKIPSEL

VO2

6
12
29

2

24

PC51
1000P_0402_50V7K
PC52
330U_D3L_6.3VM_R25M

16

PGND1

PC79
PC79
@ 680P_0603_50V8J

PR87
PR87
0_0402_5%
2

LL2

PQ23
PQ23
SI4810BDY-T1-E3_SO8

4
3
2
1

D
D
D
D

15

VL

PR86
PR86

5
6
7
8

DL_5V

PR78
PR78
10K_0402_1%
2

25

1

DRVL1

PR81
PR81
2.49K_0402_1%
1
2

DRVH2

PR129
@ 4.7_1206_5%

12

14

5
6
7
8

LX_5V

8
2

PR82
PR82
4.22K_0402_1%
1
2

D
D
D
D
G
S
S
S

26

FB3

PR105
PR105

PC57
PC57
0.047U_0603_16V7K

PC45
PC45
4.7U_1206_25V6K
2
1

4
3
2
1

32 QFN 5X5 LL1

D
D
D
D

VBST2

2

G
S
S
S

13

17

1

PR88
PR88
0_0402_5%
2
1

PC44
PC44
4.7U_1206_25V6K
2
1

DH_5V

PR84
PR84
14.7K_0402_1%
1
2

8
7
6
5

27

10

& lt; 4,36,37 & gt; MAINPWON

OCP=8A
+5VALWP
PL5
PL5
3.3UH_SIL1045R-3R3PF_8.2A_30%
1
2

PR83
PR83
14.7K_0402_1%
1
2

1
2
3
4
1

28

DRVH1

DL_3V

2

2

PC78
@ 680P_0603_50V8J

VBST1

EN5

LX_3V

S
S
S
G

@

DH_3V
PQ24
PQ24
SI4810BDY-T1-E3_SO8

V5FILT

9

1
2
3
4

2

PR128
PR128
@ 4.7_1206_5%

1

+

PR80
PR80
10K_0402_1%

1

PQ21
PQ21
SI4800BDY-T1-E3_SO8

PC49
PC49
0.1U_0603_25V7K
1
2

PC55
PC55
1000P_0402_50V7K
2
1

S
S
S
G

20
PC50
PC50
PR79
PR79
0.1U_0603_25V7K 0_0603_5%
2
1
1
2

VIN

VREG5

21

PR77
PR77
0_0603_5%
1

22

PL6
PL6
3.3UH_SIL1045R-3R3PF_8.2A_30%
2
1

1

1000P_0402_50V7K
PC53
2
1

C

PC54
330U_D3L_6.3VM_R25M

+3VALWP

D

PU6
PU6

SI4800BDY-T1-E3_SO8

OCP=8A

VL

PR76
PR76
5.1_0603_5%
2
1

PC47
PC47
10U_0805_6.3V6M
2
1

PC48
PC48
0.1U_0603_25V7K
2
1

8
7
6
5
D
D
D
D

PQ22
PQ22

+VCC_TPS51120

PC46
PC46
1U_0603_10V6K
2
1

2
PC143
680P_0603_50V8J

D

PC43
PC43
4.7U_1206_25V6K
2
1

1

PC146
680P_0603_50V8J

PC42
PC42
4.7U_1206_25V6K
2
1

JUMP_43X118

2

@

1

2

B+

B

@
POK

& lt; 37 & gt;

A

A

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2006/05/18

Issued Date

Deciphered Date

2007/05/18

Title

+5V/+3V

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Tuesday, May 22, 2007
Date:

Rev
2.0

LA-3481P

5

4

3

2

Sheet
1

39

of

47

A

B

C

D

PJ14
PJ14

LGATE2

3

PGND1

PGND2

26

9
10
8
15

VOUT1
VSEN1
EN1
PG1

VOUT2
VSEN2
EN2
PG2/REF

20
19
21
16

11

OCSET1

OCSET2

PQ28
PQ28
SI4800BDY-T1-E3_SO8

27

1

1
PC74
PC74
0.01U_0402_25V7K

PR104
PR104
6.81K_0402_1%
2

PC73
220U_D2_4VM_R15

1

4
3
2
1

SUSP#

& lt; 19,27,29,30,35,38,41,42 & gt;

2

2
PR106
PR106
0_0402_5%

ISL6227CAZ-T_SSOP28

PR109
@ 0_0402_5%

1

13

1

1

+

VSE_1.5V
1

1

DDR

DL_1.5V

PR112
PR112
100K_0402_1%

PC77
@ 0.1U_0402_16V7K

PR110
PR110
10K_0402_1%

2

2

2

PR113
PR113
100K_0402_1%

2

PC76
@ 0.1U_0402_16V7K

1

2

PR111
@ 0_0402_5%

1

2

PR108
PR108
10K_0402_1%

PR103
PR103
0_0402_5%
PC75
680P_0603_50V8J

18

GND

VSE_1.8V
2
PR107
PR107
0_0402_5%

1

1

& lt; 27,29,30,35 & gt; SYSON

2

1

2

LGATE1

PR99
4.7_1206_5%

1

2

PR101
PR101
2.26K_0402_1%
1
2

1

DL_1.8V

PR102
PR102
0_0402_5%

ISE_1.5V

LX_1.5V

2

22

+1.5VSP

PL8
PL8
4.7U_LF919AS-4R7M-P3_5.2A_20%
1
2

2

ISEN2

PR97
PR97
2.2_0603_5%

DH_1.5V-2

1

ISEN1

2

2

7

1

1

ISE_1.8V

5
6
7
8
D
D
D
D

25

+1.5VSP

G
S
S
S

VCC

PHASE2

PQ26
PQ26
SI4800BDY-T1-E3_SO8

4
3
2
1

28

14
VIN

UGATE2

PHASE1

1
2
3
4

UGATE1

24

4

PR96
PR96
2.2_0603_5%

PR100
PR100
2.26K_0402_1%
PQ27
PQ27
1
2
SI4810BDY-T1-E3_SO8

DH_1.5V-1

5

PC69
PC69
0.1U_0402_16V7K
2
1

2

2

DH_1.8V-1

BST_1.5V-2
1
PR94
PR94
0_0603_5%

21

S
S
S
G

2

23

5
6
7
8

PR93
PR93
0_0603_5%

BOOT2

BOOT1

D
D
D
D

1

SOFT2

PC67
PC67
0.01U_0402_25V7K
1
17 2

G
S
S
S

2

2
2

PC72
680P_0603_50V8J

2

PC71
PC71
0.01U_0402_25V7K

1

1

1

1

2
PR98
PR98
10K_0402_1%

PC65
PC65
2.2U_0805_10V6K

2

PR92
PR92
2.2_0603_5%
1

2BST_1.8V-2 6

1

2

1

1

2
8
7
6
5

PR95
4.7_1206_5%

3

2
PC68
PC68
0.1U_0402_16V7K
2
1

2
PC70
220U_D2_4VM_R15

PC62
PC62
4.7U_1206_25V6K

DAP202U_SOT323-3

PC66
PC66
PU7
0.01U_0402_25V7K PU7
2
1
12 SOFT1

D
D
D
D

+

BST_1.8V-1

S
S
S
G
PL7
PL7
1.8UH_SIL104R-1R8PF_9.5A_30%
1
2 LX_1.8V

1

B+

1

BST_1.5V-1

1
2
3
4

+1.8VP

1

JUMP_43X118

2

PC64
PC64
0.1U_0603_25V7K

8
7
6
5
D
D
D
D
PQ25
PQ25
SI4800BDY-T1-E3_SO8

+1.8VP

2

1
PC61
PC61
4.7U_1206_25V6K
+5VALWP

1

1

PD12
PD12

2

PC63
PC63
4.7U_0805_6.3V6K

1

1

2

2

PR91
PR91
0_1206_5%

1

1

PC60
PC60
4.7U_1206_25V6K

2

@

2

PC59
PC59
4.7U_1206_25V6K

1
2

1

2

3

3

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2006/05/18

Deciphered Date

2007/05/18

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

1.8V / 1.2V
Document Number

Rev
2.0

Tuesday, May 22, 2007

Sheet
D

40

of

47

5

4

3

2

1

PL14
PL14
1

B+

2

PHASE_1.05V
PR130
1 PR130

4

UG

BOOT
PVCC

VCC

11

5
6
7
8

2.2U_0603_6.3V6K
LG_1.05V

PL10
PL10
1.8UH_SIL104R-1R8PF_9.5A_30%
1
2

+1.05VSP

PC90
680P_0603_50V8J

2

21

PC89
220U_D2_4VM_R15

2

PR122
PR122
2.26K_0402_1%

1

PQ32
PQ32
SI4810BDY-T1-E3_SO8

4
3
2
1
10

9

7

6

2

ISL6268CAZ-T_SSOP16

C

PC88
PC88
0.01U_0402_25V7K

1

2

2

PR121
PR121
PC87
PC87

1

2

1

1

PR120
PR120
49.9K_0402_1%

2

6800P_0402_25V7K

1
2

PC86
PC86

22P_0402_50V8J

1

1

C

+

D
D
D
D

ISEN_1.05V
1
2
PR119
PR119
8.66K_0402_1%

VO

FB

PC85
PC85
0.1U_0402_16V7K

1

PR124
4.7_1206_5%

G
S
S
S

EN
COMP

1

5

FSET

PR118
PR118
22K_0402_1%
1
2

& lt; 19,27,29,30,35,38,40,42 & gt; SUSP#

+1.05VS

2

PC84
PC84
2.2U_0603_6.3V6K

5
6
7
8

2

1

6269_1.05V

PQ30
PQ30
SI4800BDY-T1-E3_SO8

12

ISEN

PC83
PC83
1
2

13

PGND

PR116
PR116
0_0603_5%
PR117
PR117
4.7_0603_5%
1
2 6269_1.05V

14

LG

D

PC82
PC82 0.1U_0603_25V7K

4
3
2
1

VIN

PHASE

3

PGOOD

GND

2

15

1

16

2

8

PU8
PU8

UG_1.05V
2

1

2

0_0603_5%
+5VALW
BOOT_1.05V

2

0_0603_5%1
2

D
D
D
D

PR114
1 PR114

PR115
PR115
10K_0402_1%

G
S
S
S

6269_1.05V
1

1
2

2

@
D

PC80
PC80
10U_1206_25V6M

1

PC81
PC81
10U_1206_25V6M

FBMA-L18-453215-900LMA90T_1812

57.6K_0402_1%

2

PR123
PR123
3K_0402_1%

+1.5VSP

2

PC95
PC95
1U_0603_6.3V6M

B

2

8
7

EN
POK

VOUT
VOUT
FB

2

+1.25VSP

1

PC94
PC94
2

22U_1206_6.3V6M

1
PC93
PC93
2

1.15K_0402_1%
2

1

1

PR125
PR125

APL5913-KAC-TRL_SO8

2

PC92
PC92
1U_0603_10V6K

3
4
1

12K_0402_1%
1
2

& lt; 19,27,29,30,35,38,40,42 & gt; SUSP#

VCNTL
VIN
VIN

1

PR127
PR127

PU12
PU12
6
5
9

GND

PC91
PC91
4.7U_0805_6.3V6K

1

2

2

B

PJ19
JUMP_43X79
@

1

1

1

+5VALW

0.01U_0402_25V7K

2

PR126
PR126
2K_0402_1%

A

A

2006/05/18

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2007/05/18

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

1.05V / 1.25V
Document Number

Rev
2.0

Tuesday, May 22, 2007

Sheet
1

41

of

47

5

4

3

2

1

+3VALW

1

+1.8V

1

+5VALW

1

PJ16
@ JUMP_43X79

VOUT
VOUT
FB

2

2

7
8

TP

9

1

NC

2

PC98
PC98
1U_0603_6.3V6M

1
PR137
PR137
1K_0402_1%

+0.9VSP
1

PC99
PC99
2

2
G
S

2

PQ33

2

3

PC101
@ 0.1U_0402_16V7K

D

1

1

PR138
PR138
0_0402_5%
1
2

SUSP

1

& lt; 35 & gt;

PC100
PC100
10U_1206_6.3V7K

2

2

NC

VOUT

APL5331KAC-TRL_SO8
22U_1206_6.3V6M

1

PC104
PC104
2

1

1
2.15K_0402_1%

PC106
PC106

2

GND
1

1

PR140
PR140

VREF

+3VALWP

1

+2.5VSP

APL5913-KAC-TRL_SO8

5

2

EN
POK

6

NC

4

1

8
7

3
4

VCNTL

GND

3

PR136
PR136
1K_0402_1%

2

VCNTL
VIN
VIN

VIN

2

1

1
2

1

6
5
9

2

PC107
PC107
1U_0603_10V6K

PU9
PU9
1

1U_0603_6.3V6M
PC97
PC97
4.7U_0805_6.3V6K

PR139
PR139
12K_0402_1%
1
2

& lt; 19,27,29,30,35,38,40,41 & gt; SUSP#

PC102
PC102

PU10
PU10
2

PC103
PC103
4.7U_0805_6.3V6K

D

2

PJ17
JUMP_43X79
@

2

2

1

D

0.01U_0402_25V7K
0.1U_0402_16V7K
RHU002N06_SOT323-3

2

PR141
PR141
1K_0402_1%

C

C

B

B

A

A

2006/05/18

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2007/05/18

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

1.05V / 0.9V / 1.5V
Document Number

Rev
2.0

Tuesday, May 22, 2007

Sheet
1

42

of

47

5

4

3

2

1

2

& lt; 5 & gt;

+CPU_B+

PHASE1

34

PGND1

33

LGATE1

32

PVCC

30

12

FB2

NC

25

1

2

680P_0402_50V7K
1
2

PC145
PC145

1

68U_25V_M_R0.44

PC148

100U_25V_M

68U_25V_M_R0.44

PC108

PC112
PC112
10U_1206_25V6M
2
1

PC111
PC111
10U_1206_25V6M
2
1

5

1
2

3
2
1

PR152
2

1
2

1

1

5
6
7
8
3
2
1

1
2

3
2
1

1

PR163

VSUM

2

PR164
PR164
1_0402_5%

PR165 @ 0_0603_5%
1
2
PC130
PC130
1
2
0.22U_0603_10V7K

IRF8113PBF_SO8

1

B

ISEN2
2

+CPU_B+

PC134
PC134 10_0603_5%
2

2
PC135
PC135 0.018U_0603_50V7J
1
2

2

1

VCC_PRM
PC140
PC140
0.22U_0603_10V7K

2

5.36K_0402_1%
PC139
PC139 0.1U_0402_16V7K
1
2
1

2.61K_0402_1%

1

2

PR180
PR180

11K_0402_1%

2

1

PR179
PR179 1K_0402_1%

2

20_0402_5%

PR178
PR178

1

1
2
PR176
PR176 0_0402_5%
PC138
PC138 180P_0402_50V8J
1
2

PR177
PR177

2

PR175
PR175

PC137
PC137
0.018U_0603_50V7J

2

2

PC136
PC136
0.018U_0603_50V7J

1

VSUM

1

0_0402_5%

+VCC_CORE
1
2
PR174
PR174 20_0402_5%
& lt; 5 & gt; VSSSENSE

0.1U_0603_25V7K

2

2
1

PR173
PR173

IRF8113PBF_SO8

1

VCC_PRM

PR172
PR172 1.82K_0402_1%
1

+5VS

PC128
680P_0603_50V8J

PL13
PL13

PH4
PH4
10KB_0603_5%_ERTJ1VR103J
1

PR170
PR170 1

4

PR171
PR171

PC133
PC133 470P_0402_50V7K
1
2

1

3.4K_0402_1%
1
2

ISEN1
ISEN2
2

PR160
4.7_1206_5%

PQ39
PQ39

4

2

@ 0_0402_5%

390P_0402_50V7K

2

PC125
PC125
0.22U_0603_10V7K

PR166
PR166 1_0603_5%
PC131
PC131
1U_0402_6.3V4Z

2

2

1

1

0.36UH_MPC1040LR36_24A_20%

PQ38
PQ38

1

PR168
@ 0_0402_5%
PR169

UGATE_CPU2-2

2
5
6
7
8

1

12

ISEN1

2

PU11

24

ISEN2
23

22

VDD

GND
21

VIN

VSUM

20

19

VO
18

17

DFB

DROOP

RTN
15

16

VSEN

VDIFF

BOOT_CPU2
1
PR159
PR159
0_0603_5%

1

26

2

27

BOOT2

1

UGATE2

FB

4

2

COMP

C

+CPU_B+

PC122
PC122
10U_1206_25V6M

10

PHASE_CPU2
PR183
PR183
UGATE_CPU2-10_0603_5%2
1

+VCC_CORE
PR154
PR154
1_0402_5%

PR162
PR162
10K_0402_1%
2
1

28

PC127
PC127 5600P_0402_25V7K

VCCSENSE

PC116
PC116
1U_0603_6.3V6M

29

PHASE2

ISL6262ACRZ-T_QFN48_7X7
ISL6262ACRZ-T_QFN48_7X7

3.65K_0805_1%

PGND2

VW

PQ37
PQ37
SI7840DP-T1-E3_SO8

LGATE_CPU2

1

OCSET

9

PR167
PR167 61.9K_0402_1% PC129 1500P_0402_50V7K
PC129
1
2
2
1

PC144
PC144
680P_0402_50V7K

IRF8113PBF_SO8

IRF8113PBF_SO8

2

8

2

+
2

D

PR155 @ 0_0603_5%
1
2
PC120
PC120
1
2
VCC_PRM
ISEN1
0.22U_0603_10V7K

VSUM

PC121
PC121
10U_1206_25V6M
2
1

SOFT

13

1

1

1
PL12
PL12

LGATE_CPU1
5

NTC

7

1
2
1000P_0402_50V7K PC126
PC126
PR161
PR161 3.57K_0402_1%
1
2

& lt; 5 & gt;

5
6
7
8

31

LGATE2

VR_TT#

6

2

PR158
PR158 13K_0402_1%
1
2

PC132
PC132

PC115
PC115
2
1

PHASE_CPU1

RBIAS

PC119
680P_0603_50V8J

PR153
PR153
10K_0402_1%
2
1

PMON

14

21

@ 100K_0603_1%_TH11-4H104FT
1
2
@ 0.015U_0402_16V7K
PC123
0.022U_0603_25V7K PC124
PC124
1
2

B

0.01U_0402_25V7K

UGATE_CPU1-1

3.65K_0805_1%

35

2

UGATE1

4

12

38

37

PQ36
PQ36
36

5

PH3

PR151
4.7_1206_5%

4

BOOT1

11

PR157

+
2

2

0_0603_5% 0.22U_0603_10V7K
PR182
PR182
1
2
PQ35
PQ35
0_0603_5%

VID0

39

VID1

VID2

40
VID3

42

41
VID4

VID5

43
VID6

44

45

46
DPRSTP#

48

47

3V3

4

PC118
PC118
21
2

3
2
1

VR_TT#
@ 4.22K_0402_1%
1

1
PR146
PR146
2

1
2
49
GND

3
2
147K_0402_1%

+
2

3
2
1

2
0_0402_5%
1
PR156
PR156

PSI#

1

0.36UH_MPC1040LR36_24A_20%
PR148
PR148
1

3
2
1

1
PR181
PR181

1

PQ34
PQ34
SI7840DP-T1-E3_SO8

5
6
7
8

PGD_IN
C

2

H_PSI#

PGOOD

DPRSLPVR

& lt; 5 & gt;

1

VGATE

CLK_EN#

& lt; 22,29 & gt;

PL11
PL11
FBMA-L18-453215-900LMA90T_1812
1
2
B+

UGATE_CPU1-2 4

BOOT_CPU1

1

2

PC117
PC117
1U_0603_6.3V6M

PR149
PR149

PR150
PR150
499_0402_1%

1.91K_0402_1%

2

1

+3VS

0_0402_5%
2

0_0402_5%
2

0_0402_5%

PR145
PR145
1

PR147
PR147
1

0_0402_5%
2

VR_ON

& lt; 5,8,21 & gt; H_DPRSTP#
& lt; 22 & gt; CLK_ENABLE#

+3VS

0_0402_5%
2

1
PR144
PR144
1

PC114
PC114
1U_0603_6.3V6M
2
1

PR143
PR143
& lt; 8,22 & gt; DPRSLPVR

PC113
PC113
0.01U_0402_25V7K
2
1

1

PR142
PR142
1_0603_5%

PC147

& lt; 5 & gt;

& lt; 5 & gt;

CPU_VID4
& lt; 29 & gt;
CPU_VID3
& lt; 5 & gt;
CPU_VID2
& lt; 5 & gt;
CPU_VID1
& lt; 5 & gt;
CPU_VID0
& lt; 5 & gt;

CPU_VID5

VR_ON

D

CPU_VID6

+5VS

PC141
PC141 0.22U_0402_6.3V6K
2
1

A

A

2005/06/23

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2006/06/23

Deciphered Date

Title

+CPU_CORE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Tuesday, May 22, 2007
Date:

Rev
2.0

LA-3481P

5

4

3

2

Sheet
1

43

of

47

5

4

HW4 Product Improvement Record (P.I.R.)
ISKAA LA-3481P SCHEMATIC CHANGE LIST
REVISION CHANGE: 0.1 TO 2A

D

C

B

A

Rev 0.1 to 0.2
NO
PAGE MODIFICATION LIST
PURPOSE
-----------------------------------------------------------------------------------------------1
17
Add JP39
Add CRT Board
2
22
Change R322 from 150 ohm to 10K ohm
From Intel recommend
3
12
Delete L13, L14, C199, C140
1.25VS_DMI share with 1.25VS_PEG
4
31
Modify PCI-E for WLAN and Robson
Design issue
5
15
Delete C234
Share with C729

Rev 0.2 to 0.3
NO
PAGE MODIFICATION LIST
PURPOSE
-----------------------------------------------------------------------------------------------From Intel recommend
1
11
Remove C116
2
16
Change EXP_CLKREQ# from U4.44 to U4.3
Common design with ISRAA
3
16
Change CLK_MCH_3GPLL from U4.27 to U4.47
Common design with ISRAA
4
16
Change CLK_PCIE_CARD from U4.47 to U4.27
Common design with ISRAA
5
19
Add R949 and Remove D11
Design change
6
19
Add JP42
Co-layout 30 pin LVDS connector
7
24
Add R874
Reserve the resister for EMI
8
29
Change EC from KB910 to KB926
Design change
9
34
Change SPI BIOS U52
Design change
10
34
Add Q54, Q55
HDD LED controlled by SB
11
47
Add Energy Star circuit
Design change
12
10
Change C84~C115 from Y5V to X7R
For VGA thermal issue

3

2

1

Rev 1.0 to 2.0
NO
PAGE MODIFICATION LIST
PURPOSE
-----------------------------------------------------------------------------------------------1
18
Add U54 and C966
For HDMI hot plug issue
2
18
Remove 1932 circuit
M72 and M76 has internal HDMI
3
18
Remove CMD circuit
For EMI issue
4
18
Add L66, L67, L68, L69
For EMI issue
5
18
Add Q134,Q135 level-shifting circuit
For HDMI level-shifting
6
18
Change R705 and R706 to 19.1K ohm
From ATI recommend
7
24
Reserve R713, R714, R715, C873, C875, C877
For EMI issue
8
32
Reserve C650~C676
For EMI issue
9
34
Reserve C682~C687
For EMI issue
10
18
Change R621 to 100K ohm and R723 to 2.2K ohm
For HDMI level-shifting

D

Rev 2.0 to 2A
NO
PAGE MODIFICATION LIST
PURPOSE
-----------------------------------------------------------------------------------------------1
18
Add U55 level-shifting circuit
For HDMI level-shifting
2
29
Change C943 and C944 from 10pf to 15pf
From ENE recommend for crystal issue
3
23
Change C360 from 0.1uf to 1uf
From Intel recommend for boot-up issue
4
22
Remove R327, R328, R329
For leakage issue

C

Rev 0.3 to 0.4
NO
PAGE MODIFICATION LIST
PURPOSE
-----------------------------------------------------------------------------------------------1
12
Modify L58 to 4.7 ohm
For TV-out wave line issue
2
12
Change R686 to 2.2uf
For TV-out wave line issue
3
12
Modify L15 to 100 ohm
from Intel recommend for new chip set
4
12
Change R694 to 1uf
from Intel recommend for new chip set
5
26
Reserve L92,R941,R944,R946,R947,
Reserve for LAN controller 8111C
C965,C963,R937,C962,C964
6
33
Modify Camera power from +5Vs to +5VALW
Change for Camera can't detect
from S3 resume
7
29
Add R928
For CIR issue
7
22
Add R903 and R927
For CIR issue

B

Rev 0.4 to 1.0
NO
PAGE MODIFICATION LIST
PURPOSE
-----------------------------------------------------------------------------------------------Change PCB 0.4 to 1.0
Modify Revision for MP
1
27
Add R935
Design for speaker select
2
28
Change L49, L50, L51, L52 to 0 ohm
For speaker issue
3
27
Change C517 and C519 from 1uf to 4.7uf
From Realtek recommend for THD+N issue
4
31
Add R954
For HD-DVD function

A

Compal Secret Data

Security Classification
Issued Date

2006/06/30

Deciphered Date

2008/05/21

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

Compal Electronics, Inc.
P.I.R.
Document Number

Rev
2.0

LA-3481P
Sheet

Saturday, June 23, 2007
1

44

of

47

5

4

3

2

1

Screw Hole
GL960_R3
GLR3@

H7
H_C217D118

D

CF2
1
@

CF7
1
@

CF1

@

1
@

U37

@

H15
H_C236D43

100M
100M@

2.2U_0402_6.3VM
GM@

H22
H_C276D158

100M
100M@

H23
H_C276D158
@

1

@

H21
H_C315D165

@

@

C

H32
H_C276D158
@

1

TRANSFORMER

@
1

U19

@

H20
H_C315D165

1

@

C

H19
H_C315D165

@

H31
H_C236D122

@
1

H18
H_C315D165

R686

H30
H_C236D122

@

H17
H_C236D43

@
1

1U_0402_6.3V4Z
GM@

H14
H_C236D146

@

H16
H_C236D43

@

LAN

H13
H_C236D122

1

CF8
1
@

H12
H_C236D122

1

CF4
1
@

D

@

1

H11
H_C236D122

R694

@

1

@

1

@

1
@

ICH8M
ICH8M_R1
ICH8MR1@

H10
H_C276D118

1

1
@

H9
H_C276D118

1

1
@

H8
H_C217D118

@

CF9
1

1
@

CF3

@

1

1
@

CF10

@

1

U10

CF6

1

CF5

H5
H6
H_C276D118 H_C276D118

1

@

H4
H_C276D118

1

@

H3
H_C276D118

1

@

H2
H_C276D118

1

965PM_R1
PMR1@

@

FD3

1

965GM_R1
GMR1@

@

FD1

1

965GM_R3
GMR3@

@

FD2

1

@
1

@

FD5

1

NB

FD6

1

FD4

1

U3

1

U3

1

U3

1

U3

PCBA
H24
H_C118D118N

1

H28
H_S315D118

1

@

H29
H_S315D118
@

1

@

CARDBUS

@
1

H27
H_S315D118

U14

B

@
1

@
LA-3481P_DAZ

H26
H_O197X55D158X16

B

1

PCB

H25
H_O118X197D118X197N

TI8402
8402@

PJP1

DC-JACK
SINGA_2DW-0005-B03
45@

A

A

Compal Secret Data

Security Classification
Issued Date

2006/08/05

Deciphered Date

2007/08/05

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

5

4

3

2

Compal Electronics, Inc.
ISPD & Screw Hole
Document Number

Rev
2.0

LA-3481P
Tuesday, May 22, 2007

Sheet
1

45

of

47

NO DATE
PAGE
MODIFICATION LIST
PURPOSE
------------------------------------------------------------------------------------------------------------9/14

P.39

Change PACIN to GND

Change to AUTO-SKIP mode

9/14

P.39

Add PR105

Reserve control sequence pin

9/14

P.37

Change PF2 to 15A

Increase design margine

10/24

P.36,37,43

Change PL1,PL2,PL11 to Tai-Tech

Buyer request

10/24

P.39,43

Add PC143,PC144,PC145

EMI request

10/24

P.41,43

Add snubber PR124,PC90,PR151,PC119,PR160,PC128

EMI request

10/24

P.41

Change PR119 to 5.49K

Modify 1.05V OCP point

10/24

P.40

Change PC70 to 330U_D2_9m ohm

Reduce the 1.8V ripple

0_0402_5%

Compal Secret Data

Security Classification
Issued Date

2005/06/01

Deciphered Date

2006/06/01

Title
Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Compal Electronics, Inc.
Power PIR
Document Number

Rev
2.0

LA-3481P
Tuesday, May 22, 2007

Sheet

46

of

47

A

B

C

+3VALW TO +3V_SB
+3VALW

D

+5VALW TO +5V_SB
+5VALW

+3V_SB
PJ12
2

2

E

R852
1

1

1

2
0_0402_5%

@ JUMP_43X79

@

C901

3

1

2

2 STB_SB#
G
2N7002_SOT23-3

Q67

1

C922
@ 4.7U_0805_10V4Z

2

C923 @
0.1U_0402_16V4Z

1
C907 @
Q69
2N7002_SOT23-3
0.1U_0603_25V7K
2
@

D

3

3

1

D

@S

@

+5V_SB

R824
2
1U_0603_10V4Z
@

2
1
R826 47K_0402_5%
STB_SB#

1

1

2
@

AOS 4422

2

AO3413_SOT23

2

@
470_0805_5%

1

AO4422_SO8

1

1

1

10U_0805_10V4Z

2

1
2
3
4

S
S
S
G

C899

C903
@

10U_0805_10V4Z

C900
+VSB

2

10U_0805_10V4Z

@

1

D
D
D
D

D
D

1

8
7
6
5

G

STB_SB#

U42
1

Q77

S
S

@

S

2
G

2

2

+3VALW TO +3V_LAN
+3VALW TO +3V_WLAN
+3VALW

+3V_WLAN

+3VALW

+3V_LAN

PJ21
1

2

Q71
SI3456BDV-T1-E3_TSOP6

1
D

2 STB_WLAN#
G
2N7002_SOT23-3

+VSB

2

S

Q73
2N7002_SOT23-3
0.1U_0603_25V7K
2
@

STB_LAN#

2

2
1U_0603_10V4Z

Q68

STB_WLAN_R

STB_WLAN_R

1 R848
2
@ 0_0402_5%

STB_SB_R

S

3

1
STB_WLAN#

1

D
STB_LAN

STB_LAN

3

S
2N7002_SOT23-3

STB_LAN_R
1 R850
2
0_0402_5%
@

Q75
@

2
G

R834
100K_0402_5%

@

D
& lt; 29 & gt; STB_WLAN

STB_WLAN

S
2N7002_SOT23-3

3

& lt; 29 & gt;

1

Q74
@

R832
100K_0402_5%

@

1

1

R831
100K_0402_5%
@
STB_LAN#

2
G

R833
100K_0402_5%

+5VALW
2

+5VALW

1
STB_SB_R
1

1 R849
2
0_0402_5%
@

2 STB_LAN#
G
2N7002_SOT23-3

1
@
C908
Q70
2N7002_SOT23-3
0.1U_0603_25V7K
2
@

D

2
G

STB_SB#
STB_SB

1 R847
2
@ 0_0402_5%

D

2

C913 @

2

R830
100K_0402_5%
@

STB_SB

STB_LAN_R

@
470_0805_5%
R825

+5VALW

& lt; 29 & gt;

STB_LAN_R

2

STB_WLAN# 2
G
3

1

1

@

@1
C906

@S

3

D

1

2
1
R827 47K_0402_5%
@

@

1 R846
2
@ 0_0402_5%

1

3

@S

@

AO4422_SO8
@

1
2
3
4

1 R851
2
0_0402_5%
@

STB_WLAN_R

R835
100K_0402_5%

@

D

Q76
@
S
2N7002_SOT23-3

2
G

3

Q72

2

S
S
S
G

1

2
1
R829 47K_0402_5%

@

D
D
D
D

3

R828
2
1U_0603_10V4Z

1

10U_0805_10V4Z

1

C905

@
470_0805_5%

10U_0805_10V4Z

@

C904

2
1

1

2

10U_0805_10V4Z

C911

G

@

C912

8
7
6
5

1

S

1
@

1

STB_SB_R

4

3

C910

2

1

U43

D
3

@

6
5
2
1

1

+VSB

2

1

10U_0805_10V4Z

C909
@

10U_0805_10V4Z

1

2

@ JUMP_43X79

1

1

C902

2

@ JUMP_43X79

10U_0805_10V4Z

2

PJ20

@

Compal Secret Data

Security Classification
2006/06/30

Issued Date

2

2

4

2

4

2007/06/30

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

A

B

C

D

Compal Electronics, Inc.
DC/DC I/F & Screw
Document Number

Rev
2.0

LA-3481P
Sheet

Tuesday, May 22, 2007
E

47

of

47


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