Witam, Nie spotkałem się jeszcze z takim problemem. Wrzucam przez JTAGa openOCD bootloadera i aplikację główną według skryptu: init reset init flash erase_sector 0 0 29 sleep 10 echo "\nKASOWANIE PAMIECI\n" flash erase_check 0 sleep 10 echo "\nZAPIS BOOTLOADERA\n" flash write_image boot_lapoC.hex 0x00000000 bin echo "\nZAPISANO BOOTLOADER\n" sleep 10 echo "\nZAPIS PROGRAMU\n" flash write_image lapoC.hex 0x00008000 bin echo "\nZAPISANO PROGRAM\n" reset run Bootloader uruchamia aplikację i ta działa poprawnie. Robię dumpa całego flasha do pliku. Następnie wrzucam aplikację poprzez bootloader (w załączniku). Bootloader uruchamia aplikację która wysypuje się w różnych miejscach. Robię dumpa do pliku i oba pliki zrzutów pamięci są identyczne! Aplikacja wiadomo korzysta z ustawień w zewnętrznym flashu czy w pamięci RTC ale bootloader ich nie rusza... Jeśli ponownie wrzucę aplikację przez JTAGa to wszystko działa. Pomocy !
/*
* main.h
*
* Created on: 11 janv. 2010
* Author: nio
*/
#ifndef MAIN_H_
#define MAIN_H_
#define byte unsigned char
// bit-banding helpers
#define BITBAND_SRAM_REF 0x20000000
#define BITBAND_SRAM_BASE 0x22000000
#define BITBAND_SRAM(a,b) ((BITBAND_SRAM_BASE + (a-BITBAND_SRAM_REF)*32 + (b*4))) // Convert SRAM address
#define BITBAND_PERI_REF 0x40000000
#define BITBAND_PERI_BASE 0x42000000
#define BITBAND_PERI(a,b) ((BITBAND_PERI_BASE + (a-BITBAND_PERI_REF)*32 + (b*4))) // Convert Peripheral address
#endif /* MAIN_H_ */
/******************** (C) COPYRIGHT 2003 STMicroelectronics ********************
* File Name : 71x_type.h
* Author : MCD Application Team
* Date First Issued : 05/16/2003
* Description : Common data types
********************************************************************************
* History:
* 24/05/2005 : V3.0
* 30/11/2004 : V2.0
* 14/07/2004 : V1.3
* 01/01/2004 : V1.2
*******************************************************************************
THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
#ifndef _71x_type_H
#define _71x_type_H
typedef unsigned long u32;
typedef unsigned short u16;
typedef unsigned char u8;
typedef signed long s32;
typedef signed short s16;
typedef signed char s8;
typedef volatile unsigned long vu32;
typedef volatile unsigned short vu16;
typedef volatile unsigned char vu8;
typedef volatile signed long vs32;
typedef volatile signed short vs16;
typedef volatile signed char vs8;
#ifndef NULL
#define NULL 0
#endif
typedef enum { false = 0, true = !false } bool;
/*===================================================================*/
typedef enum { INDIRECT = 0, DIRECT = !INDIRECT} RegisterAccess;
/*===================================================================*/
#endif /* _71x_type_H */
/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/
/**************************************************************************//**
* @file core_cm3.h
* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
* @version V1.30
* @date 30. October 2009
*
* @note
* Copyright (C) 2009 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED " AS IS " . NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#ifndef __CM3_CORE_H__
#define __CM3_CORE_H__
/** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration
*
* List of Lint messages which will be suppressed and not shown:
* - Error 10: \n
* register uint32_t __regBasePri __asm( " basepri " ); \n
* Error 10: Expecting ';'
* .
* - Error 530: \n
* return(__regBasePri); \n
* Warning 530: Symbol '__regBasePri' (line 264) not initialized
* .
* - Error 550: \n
* __regBasePri = (basePri & 0x1ff); \n
* Warning 550: Symbol '__regBasePri' (line 271) not accessed
* .
* - Error 754: \n
* uint32_t RESERVED0[24]; \n
* Info 754: local structure member ' & lt; some, not used in the HAL & gt; ' (line 109, file ./cm3_core.h) not referenced
* .
* - Error 750: \n
* #define __CM3_CORE_H__ \n
* Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced
* .
* - Error 528: \n
* static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n
* Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced
* .
* - Error 751: \n
* } InterruptType_Type; \n
* Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced
* .
* Note: To re-enable a Message, insert a space before 'lint' *
*
*/
/*lint -save */
/*lint -e10 */
/*lint -e530 */
/*lint -e550 */
/*lint -e754 */
/*lint -e750 */
/*lint -e528 */
/*lint -e751 */
/** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions
This file defines all structures and symbols for CMSIS core:
- CMSIS version number
- Cortex-M core registers and bitfields
- Cortex-M core peripheral base address
@{
*/
#ifdef __cplusplus
extern " C " {
#endif
#define __CM3_CMSIS_VERSION_MAIN (0x01) /*! & lt; [31:16] CMSIS HAL main version */
#define __CM3_CMSIS_VERSION_SUB (0x30) /*! & lt; [15:0] CMSIS HAL sub version */
#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN & lt; & lt; 16) | __CM3_CMSIS_VERSION_SUB) /*! & lt; CMSIS HAL version number */
#define __CORTEX_M (0x03) /*! & lt; Cortex core */
#include & lt; stdint.h & gt; /* Include standard types */
#if defined (__ICCARM__)
#include & lt; intrinsics.h & gt; /* IAR Intrinsics */
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 4 /*! & lt; standard definition for NVIC Priority Bits */
#endif
/**
* IO definitions
*
* define access restrictions to peripheral registers
*/
#ifdef __cplusplus
#define __I volatile /*! & lt; defines 'read only' permissions */
#else
#define __I volatile const /*! & lt; defines 'read only' permissions */
#endif
#define __O volatile /*! & lt; defines 'write only' permissions */
#define __IO volatile /*! & lt; defines 'read / write' permissions */
/*******************************************************************************
* Register Abstraction
******************************************************************************/
/** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register
@{
*/
/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC
memory mapped structure for Nested Vectored Interrupt Controller (NVIC)
@{
*/
typedef struct
{
__IO uint32_t ISER[8]; /*! & lt; Offset: 0x000 Interrupt Set Enable Register */
uint32_t RESERVED0[24];
__IO uint32_t ICER[8]; /*! & lt; Offset: 0x080 Interrupt Clear Enable Register */
uint32_t RSERVED1[24];
__IO uint32_t ISPR[8]; /*! & lt; Offset: 0x100 Interrupt Set Pending Register */
uint32_t RESERVED2[24];
__IO uint32_t ICPR[8]; /*! & lt; Offset: 0x180 Interrupt Clear Pending Register */
uint32_t RESERVED3[24];
__IO uint32_t IABR[8]; /*! & lt; Offset: 0x200 Interrupt Active bit Register */
uint32_t RESERVED4[56];
__IO uint8_t IP[240]; /*! & lt; Offset: 0x300 Interrupt Priority Register (8Bit wide) */
uint32_t RESERVED5[644];
__O uint32_t STIR; /*! & lt; Offset: 0xE00 Software Trigger Interrupt Register */
} NVIC_Type;
/*@}*/ /* end of group CMSIS_CM3_NVIC */
/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB
memory mapped structure for System Control Block (SCB)
@{
*/
typedef struct
{
__I uint32_t CPUID; /*! & lt; Offset: 0x00 CPU ID Base Register */
__IO uint32_t ICSR; /*! & lt; Offset: 0x04 Interrupt Control State Register */
__IO uint32_t VTOR; /*! & lt; Offset: 0x08 Vector Table Offset Register */
__IO uint32_t AIRCR; /*! & lt; Offset: 0x0C Application Interrupt / Reset Control Register */
__IO uint32_t SCR; /*! & lt; Offset: 0x10 System Control Register */
__IO uint32_t CCR; /*! & lt; Offset: 0x14 Configuration Control Register */
__IO uint8_t SHP[12]; /*! & lt; Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15) */
__IO uint32_t SHCSR; /*! & lt; Offset: 0x24 System Handler Control and State Register */
__IO uint32_t CFSR; /*! & lt; Offset: 0x28 Configurable Fault Status Register */
__IO uint32_t HFSR; /*! & lt; Offset: 0x2C Hard Fault Status Register */
__IO uint32_t DFSR; /*! & lt; Offset: 0x30 Debug Fault Status Register */
__IO uint32_t MMFAR; /*! & lt; Offset: 0x34 Mem Manage Address Register */
__IO uint32_t BFAR; /*! & lt; Offset: 0x38 Bus Fault Address Register */
__IO uint32_t AFSR; /*! & lt; Offset: 0x3C Auxiliary Fault Status Register */
__I uint32_t PFR[2]; /*! & lt; Offset: 0x40 Processor Feature Register */
__I uint32_t DFR; /*! & lt; Offset: 0x48 Debug Feature Register */
__I uint32_t ADR; /*! & lt; Offset: 0x4C Auxiliary Feature Register */
__I uint32_t MMFR[4]; /*! & lt; Offset: 0x50 Memory Model Feature Register */
__I uint32_t ISAR[5]; /*! & lt; Offset: 0x60 ISA Feature Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24 /*! & lt; SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFul & lt; & lt; SCB_CPUID_IMPLEMENTER_Pos) /*! & lt; SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20 /*! & lt; SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFul & lt; & lt; SCB_CPUID_VARIANT_Pos) /*! & lt; SCB CPUID: VARIANT Mask */
#define SCB_CPUID_PARTNO_Pos 4 /*! & lt; SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFul & lt; & lt; SCB_CPUID_PARTNO_Pos) /*! & lt; SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0 /*! & lt; SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFul & lt; & lt; SCB_CPUID_REVISION_Pos) /*! & lt; SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31 /*! & lt; SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1ul & lt; & lt; SCB_ICSR_NMIPENDSET_Pos) /*! & lt; SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28 /*! & lt; SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1ul & lt; & lt; SCB_ICSR_PENDSVSET_Pos) /*! & lt; SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27 /*! & lt; SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1ul & lt; & lt; SCB_ICSR_PENDSVCLR_Pos) /*! & lt; SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26 /*! & lt; SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1ul & lt; & lt; SCB_ICSR_PENDSTSET_Pos) /*! & lt; SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25 /*! & lt; SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1ul & lt; & lt; SCB_ICSR_PENDSTCLR_Pos) /*! & lt; SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23 /*! & lt; SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1ul & lt; & lt; SCB_ICSR_ISRPREEMPT_Pos) /*! & lt; SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22 /*! & lt; SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1ul & lt; & lt; SCB_ICSR_ISRPENDING_Pos) /*! & lt; SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12 /*! & lt; SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFul & lt; & lt; SCB_ICSR_VECTPENDING_Pos) /*! & lt; SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_RETTOBASE_Pos 11 /*! & lt; SCB ICSR: RETTOBASE Position */
#define SCB_ICSR_RETTOBASE_Msk (1ul & lt; & lt; SCB_ICSR_RETTOBASE_Pos) /*! & lt; SCB ICSR: RETTOBASE Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0 /*! & lt; SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFul & lt; & lt; SCB_ICSR_VECTACTIVE_Pos) /*! & lt; SCB ICSR: VECTACTIVE Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_VTOR_TBLBASE_Pos 29 /*! & lt; SCB VTOR: TBLBASE Position */
#define SCB_VTOR_TBLBASE_Msk (0x1FFul & lt; & lt; SCB_VTOR_TBLBASE_Pos) /*! & lt; SCB VTOR: TBLBASE Mask */
#define SCB_VTOR_TBLOFF_Pos 7 /*! & lt; SCB VTOR: TBLOFF Position */
#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFul & lt; & lt; SCB_VTOR_TBLOFF_Pos) /*! & lt; SCB VTOR: TBLOFF Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16 /*! & lt; SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFul & lt; & lt; SCB_AIRCR_VECTKEY_Pos) /*! & lt; SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*! & lt; SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul & lt; & lt; SCB_AIRCR_VECTKEYSTAT_Pos) /*! & lt; SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15 /*! & lt; SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1ul & lt; & lt; SCB_AIRCR_ENDIANESS_Pos) /*! & lt; SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_PRIGROUP_Pos 8 /*! & lt; SCB AIRCR: PRIGROUP Position */
#define SCB_AIRCR_PRIGROUP_Msk (7ul & lt; & lt; SCB_AIRCR_PRIGROUP_Pos) /*! & lt; SCB AIRCR: PRIGROUP Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*! & lt; SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1ul & lt; & lt; SCB_AIRCR_SYSRESETREQ_Pos) /*! & lt; SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*! & lt; SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul & lt; & lt; SCB_AIRCR_VECTCLRACTIVE_Pos) /*! & lt; SCB AIRCR: VECTCLRACTIVE Mask */
#define SCB_AIRCR_VECTRESET_Pos 0 /*! & lt; SCB AIRCR: VECTRESET Position */
#define SCB_AIRCR_VECTRESET_Msk (1ul & lt; & lt; SCB_AIRCR_VECTRESET_Pos) /*! & lt; SCB AIRCR: VECTRESET Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4 /*! & lt; SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1ul & lt; & lt; SCB_SCR_SEVONPEND_Pos) /*! & lt; SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2 /*! & lt; SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1ul & lt; & lt; SCB_SCR_SLEEPDEEP_Pos) /*! & lt; SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1 /*! & lt; SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1ul & lt; & lt; SCB_SCR_SLEEPONEXIT_Pos) /*! & lt; SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9 /*! & lt; SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1ul & lt; & lt; SCB_CCR_STKALIGN_Pos) /*! & lt; SCB CCR: STKALIGN Mask */
#define SCB_CCR_BFHFNMIGN_Pos 8 /*! & lt; SCB CCR: BFHFNMIGN Position */
#define SCB_CCR_BFHFNMIGN_Msk (1ul & lt; & lt; SCB_CCR_BFHFNMIGN_Pos) /*! & lt; SCB CCR: BFHFNMIGN Mask */
#define SCB_CCR_DIV_0_TRP_Pos 4 /*! & lt; SCB CCR: DIV_0_TRP Position */
#define SCB_CCR_DIV_0_TRP_Msk (1ul & lt; & lt; SCB_CCR_DIV_0_TRP_Pos) /*! & lt; SCB CCR: DIV_0_TRP Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3 /*! & lt; SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1ul & lt; & lt; SCB_CCR_UNALIGN_TRP_Pos) /*! & lt; SCB CCR: UNALIGN_TRP Mask */
#define SCB_CCR_USERSETMPEND_Pos 1 /*! & lt; SCB CCR: USERSETMPEND Position */
#define SCB_CCR_USERSETMPEND_Msk (1ul & lt; & lt; SCB_CCR_USERSETMPEND_Pos) /*! & lt; SCB CCR: USERSETMPEND Mask */
#define SCB_CCR_NONBASETHRDENA_Pos 0 /*! & lt; SCB CCR: NONBASETHRDENA Position */
#define SCB_CCR_NONBASETHRDENA_Msk (1ul & lt; & lt; SCB_CCR_NONBASETHRDENA_Pos) /*! & lt; SCB CCR: NONBASETHRDENA Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_USGFAULTENA_Pos 18 /*! & lt; SCB SHCSR: USGFAULTENA Position */
#define SCB_SHCSR_USGFAULTENA_Msk (1ul & lt; & lt; SCB_SHCSR_USGFAULTENA_Pos) /*! & lt; SCB SHCSR: USGFAULTENA Mask */
#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*! & lt; SCB SHCSR: BUSFAULTENA Position */
#define SCB_SHCSR_BUSFAULTENA_Msk (1ul & lt; & lt; SCB_SHCSR_BUSFAULTENA_Pos) /*! & lt; SCB SHCSR: BUSFAULTENA Mask */
#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*! & lt; SCB SHCSR: MEMFAULTENA Position */
#define SCB_SHCSR_MEMFAULTENA_Msk (1ul & lt; & lt; SCB_SHCSR_MEMFAULTENA_Pos) /*! & lt; SCB SHCSR: MEMFAULTENA Mask */
#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*! & lt; SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1ul & lt; & lt; SCB_SHCSR_SVCALLPENDED_Pos) /*! & lt; SCB SHCSR: SVCALLPENDED Mask */
#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*! & lt; SCB SHCSR: BUSFAULTPENDED Position */
#define SCB_SHCSR_BUSFAULTPENDED_Msk (1ul & lt; & lt; SCB_SHCSR_BUSFAULTPENDED_Pos) /*! & lt; SCB SHCSR: BUSFAULTPENDED Mask */
#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*! & lt; SCB SHCSR: MEMFAULTPENDED Position */
#define SCB_SHCSR_MEMFAULTPENDED_Msk (1ul & lt; & lt; SCB_SHCSR_MEMFAULTPENDED_Pos) /*! & lt; SCB SHCSR: MEMFAULTPENDED Mask */
#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*! & lt; SCB SHCSR: USGFAULTPENDED Position */
#define SCB_SHCSR_USGFAULTPENDED_Msk (1ul & lt; & lt; SCB_SHCSR_USGFAULTPENDED_Pos) /*! & lt; SCB SHCSR: USGFAULTPENDED Mask */
#define SCB_SHCSR_SYSTICKACT_Pos 11 /*! & lt; SCB SHCSR: SYSTICKACT Position */
#define SCB_SHCSR_SYSTICKACT_Msk (1ul & lt; & lt; SCB_SHCSR_SYSTICKACT_Pos) /*! & lt; SCB SHCSR: SYSTICKACT Mask */
#define SCB_SHCSR_PENDSVACT_Pos 10 /*! & lt; SCB SHCSR: PENDSVACT Position */
#define SCB_SHCSR_PENDSVACT_Msk (1ul & lt; & lt; SCB_SHCSR_PENDSVACT_Pos) /*! & lt; SCB SHCSR: PENDSVACT Mask */
#define SCB_SHCSR_MONITORACT_Pos 8 /*! & lt; SCB SHCSR: MONITORACT Position */
#define SCB_SHCSR_MONITORACT_Msk (1ul & lt; & lt; SCB_SHCSR_MONITORACT_Pos) /*! & lt; SCB SHCSR: MONITORACT Mask */
#define SCB_SHCSR_SVCALLACT_Pos 7 /*! & lt; SCB SHCSR: SVCALLACT Position */
#define SCB_SHCSR_SVCALLACT_Msk (1ul & lt; & lt; SCB_SHCSR_SVCALLACT_Pos) /*! & lt; SCB SHCSR: SVCALLACT Mask */
#define SCB_SHCSR_USGFAULTACT_Pos 3 /*! & lt; SCB SHCSR: USGFAULTACT Position */
#define SCB_SHCSR_USGFAULTACT_Msk (1ul & lt; & lt; SCB_SHCSR_USGFAULTACT_Pos) /*! & lt; SCB SHCSR: USGFAULTACT Mask */
#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*! & lt; SCB SHCSR: BUSFAULTACT Position */
#define SCB_SHCSR_BUSFAULTACT_Msk (1ul & lt; & lt; SCB_SHCSR_BUSFAULTACT_Pos) /*! & lt; SCB SHCSR: BUSFAULTACT Mask */
#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*! & lt; SCB SHCSR: MEMFAULTACT Position */
#define SCB_SHCSR_MEMFAULTACT_Msk (1ul & lt; & lt; SCB_SHCSR_MEMFAULTACT_Pos) /*! & lt; SCB SHCSR: MEMFAULTACT Mask */
/* SCB Configurable Fault Status Registers Definitions */
#define SCB_CFSR_USGFAULTSR_Pos 16 /*! & lt; SCB CFSR: Usage Fault Status Register Position */
#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFul & lt; & lt; SCB_CFSR_USGFAULTSR_Pos) /*! & lt; SCB CFSR: Usage Fault Status Register Mask */
#define SCB_CFSR_BUSFAULTSR_Pos 8 /*! & lt; SCB CFSR: Bus Fault Status Register Position */
#define SCB_CFSR_BUSFAULTSR_Msk (0xFFul & lt; & lt; SCB_CFSR_BUSFAULTSR_Pos) /*! & lt; SCB CFSR: Bus Fault Status Register Mask */
#define SCB_CFSR_MEMFAULTSR_Pos 0 /*! & lt; SCB CFSR: Memory Manage Fault Status Register Position */
#define SCB_CFSR_MEMFAULTSR_Msk (0xFFul & lt; & lt; SCB_CFSR_MEMFAULTSR_Pos) /*! & lt; SCB CFSR: Memory Manage Fault Status Register Mask */
/* SCB Hard Fault Status Registers Definitions */
#define SCB_HFSR_DEBUGEVT_Pos 31 /*! & lt; SCB HFSR: DEBUGEVT Position */
#define SCB_HFSR_DEBUGEVT_Msk (1ul & lt; & lt; SCB_HFSR_DEBUGEVT_Pos) /*! & lt; SCB HFSR: DEBUGEVT Mask */
#define SCB_HFSR_FORCED_Pos 30 /*! & lt; SCB HFSR: FORCED Position */
#define SCB_HFSR_FORCED_Msk (1ul & lt; & lt; SCB_HFSR_FORCED_Pos) /*! & lt; SCB HFSR: FORCED Mask */
#define SCB_HFSR_VECTTBL_Pos 1 /*! & lt; SCB HFSR: VECTTBL Position */
#define SCB_HFSR_VECTTBL_Msk (1ul & lt; & lt; SCB_HFSR_VECTTBL_Pos) /*! & lt; SCB HFSR: VECTTBL Mask */
/* SCB Debug Fault Status Register Definitions */
#define SCB_DFSR_EXTERNAL_Pos 4 /*! & lt; SCB DFSR: EXTERNAL Position */
#define SCB_DFSR_EXTERNAL_Msk (1ul & lt; & lt; SCB_DFSR_EXTERNAL_Pos) /*! & lt; SCB DFSR: EXTERNAL Mask */
#define SCB_DFSR_VCATCH_Pos 3 /*! & lt; SCB DFSR: VCATCH Position */
#define SCB_DFSR_VCATCH_Msk (1ul & lt; & lt; SCB_DFSR_VCATCH_Pos) /*! & lt; SCB DFSR: VCATCH Mask */
#define SCB_DFSR_DWTTRAP_Pos 2 /*! & lt; SCB DFSR: DWTTRAP Position */
#define SCB_DFSR_DWTTRAP_Msk (1ul & lt; & lt; SCB_DFSR_DWTTRAP_Pos) /*! & lt; SCB DFSR: DWTTRAP Mask */
#define SCB_DFSR_BKPT_Pos 1 /*! & lt; SCB DFSR: BKPT Position */
#define SCB_DFSR_BKPT_Msk (1ul & lt; & lt; SCB_DFSR_BKPT_Pos) /*! & lt; SCB DFSR: BKPT Mask */
#define SCB_DFSR_HALTED_Pos 0 /*! & lt; SCB DFSR: HALTED Position */
#define SCB_DFSR_HALTED_Msk (1ul & lt; & lt; SCB_DFSR_HALTED_Pos) /*! & lt; SCB DFSR: HALTED Mask */
/*@}*/ /* end of group CMSIS_CM3_SCB */
/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick
memory mapped structure for SysTick
@{
*/
typedef struct
{
__IO uint32_t CTRL; /*! & lt; Offset: 0x00 SysTick Control and Status Register */
__IO uint32_t LOAD; /*! & lt; Offset: 0x04 SysTick Reload Value Register */
__IO uint32_t VAL; /*! & lt; Offset: 0x08 SysTick Current Value Register */
__I uint32_t CALIB; /*! & lt; Offset: 0x0C SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16 /*! & lt; SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1ul & lt; & lt; SysTick_CTRL_COUNTFLAG_Pos) /*! & lt; SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2 /*! & lt; SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1ul & lt; & lt; SysTick_CTRL_CLKSOURCE_Pos) /*! & lt; SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1 /*! & lt; SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1ul & lt; & lt; SysTick_CTRL_TICKINT_Pos) /*! & lt; SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0 /*! & lt; SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1ul & lt; & lt; SysTick_CTRL_ENABLE_Pos) /*! & lt; SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0 /*! & lt; SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul & lt; & lt; SysTick_LOAD_RELOAD_Pos) /*! & lt; SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0 /*! & lt; SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul & lt; & lt; SysTick_VAL_CURRENT_Pos) /*! & lt; SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31 /*! & lt; SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1ul & lt; & lt; SysTick_CALIB_NOREF_Pos) /*! & lt; SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30 /*! & lt; SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1ul & lt; & lt; SysTick_CALIB_SKEW_Pos) /*! & lt; SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0 /*! & lt; SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul & lt; & lt; SysTick_VAL_CURRENT_Pos) /*! & lt; SysTick CALIB: TENMS Mask */
/*@}*/ /* end of group CMSIS_CM3_SysTick */
/** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM
memory mapped structure for Instrumentation Trace Macrocell (ITM)
@{
*/
typedef struct
{
__O union
{
__O uint8_t u8; /*! & lt; Offset: ITM Stimulus Port 8-bit */
__O uint16_t u16; /*! & lt; Offset: ITM Stimulus Port 16-bit */
__O uint32_t u32; /*! & lt; Offset: ITM Stimulus Port 32-bit */
} PORT [32]; /*! & lt; Offset: 0x00 ITM Stimulus Port Registers */
uint32_t RESERVED0[864];
__IO uint32_t TER; /*! & lt; Offset: ITM Trace Enable Register */
uint32_t RESERVED1[15];
__IO uint32_t TPR; /*! & lt; Offset: ITM Trace Privilege Register */
uint32_t RESERVED2[15];
__IO uint32_t TCR; /*! & lt; Offset: ITM Trace Control Register */
uint32_t RESERVED3[29];
__IO uint32_t IWR; /*! & lt; Offset: ITM Integration Write Register */
__IO uint32_t IRR; /*! & lt; Offset: ITM Integration Read Register */
__IO uint32_t IMCR; /*! & lt; Offset: ITM Integration Mode Control Register */
uint32_t RESERVED4[43];
__IO uint32_t LAR; /*! & lt; Offset: ITM Lock Access Register */
__IO uint32_t LSR; /*! & lt; Offset: ITM Lock Status Register */
uint32_t RESERVED5[6];
__I uint32_t PID4; /*! & lt; Offset: ITM Peripheral Identification Register #4 */
__I uint32_t PID5; /*! & lt; Offset: ITM Peripheral Identification Register #5 */
__I uint32_t PID6; /*! & lt; Offset: ITM Peripheral Identification Register #6 */
__I uint32_t PID7; /*! & lt; Offset: ITM Peripheral Identification Register #7 */
__I uint32_t PID0; /*! & lt; Offset: ITM Peripheral Identification Register #0 */
__I uint32_t PID1; /*! & lt; Offset: ITM Peripheral Identification Register #1 */
__I uint32_t PID2; /*! & lt; Offset: ITM Peripheral Identification Register #2 */
__I uint32_t PID3; /*! & lt; Offset: ITM Peripheral Identification Register #3 */
__I uint32_t CID0; /*! & lt; Offset: ITM Component Identification Register #0 */
__I uint32_t CID1; /*! & lt; Offset: ITM Component Identification Register #1 */
__I uint32_t CID2; /*! & lt; Offset: ITM Component Identification Register #2 */
__I uint32_t CID3; /*! & lt; Offset: ITM Component Identification Register #3 */
} ITM_Type;
/* ITM Trace Privilege Register Definitions */
#define ITM_TPR_PRIVMASK_Pos 0 /*! & lt; ITM TPR: PRIVMASK Position */
#define ITM_TPR_PRIVMASK_Msk (0xFul & lt; & lt; ITM_TPR_PRIVMASK_Pos) /*! & lt; ITM TPR: PRIVMASK Mask */
/* ITM Trace Control Register Definitions */
#define ITM_TCR_BUSY_Pos 23 /*! & lt; ITM TCR: BUSY Position */
#define ITM_TCR_BUSY_Msk (1ul & lt; & lt; ITM_TCR_BUSY_Pos) /*! & lt; ITM TCR: BUSY Mask */
#define ITM_TCR_ATBID_Pos 16 /*! & lt; ITM TCR: ATBID Position */
#define ITM_TCR_ATBID_Msk (0x7Ful & lt; & lt; ITM_TCR_ATBID_Pos) /*! & lt; ITM TCR: ATBID Mask */
#define ITM_TCR_TSPrescale_Pos 8 /*! & lt; ITM TCR: TSPrescale Position */
#define ITM_TCR_TSPrescale_Msk (3ul & lt; & lt; ITM_TCR_TSPrescale_Pos) /*! & lt; ITM TCR: TSPrescale Mask */
#define ITM_TCR_SWOENA_Pos 4 /*! & lt; ITM TCR: SWOENA Position */
#define ITM_TCR_SWOENA_Msk (1ul & lt; & lt; ITM_TCR_SWOENA_Pos) /*! & lt; ITM TCR: SWOENA Mask */
#define ITM_TCR_DWTENA_Pos 3 /*! & lt; ITM TCR: DWTENA Position */
#define ITM_TCR_DWTENA_Msk (1ul & lt; & lt; ITM_TCR_DWTENA_Pos) /*! & lt; ITM TCR: DWTENA Mask */
#define ITM_TCR_SYNCENA_Pos 2 /*! & lt; ITM TCR: SYNCENA Position */
#define ITM_TCR_SYNCENA_Msk (1ul & lt; & lt; ITM_TCR_SYNCENA_Pos) /*! & lt; ITM TCR: SYNCENA Mask */
#define ITM_TCR_TSENA_Pos 1 /*! & lt; ITM TCR: TSENA Position */
#define ITM_TCR_TSENA_Msk (1ul & lt; & lt; ITM_TCR_TSENA_Pos) /*! & lt; ITM TCR: TSENA Mask */
#define ITM_TCR_ITMENA_Pos 0 /*! & lt; ITM TCR: ITM Enable bit Position */
#define ITM_TCR_ITMENA_Msk (1ul & lt; & lt; ITM_TCR_ITMENA_Pos) /*! & lt; ITM TCR: ITM Enable bit Mask */
/* ITM Integration Write Register Definitions */
#define ITM_IWR_ATVALIDM_Pos 0 /*! & lt; ITM IWR: ATVALIDM Position */
#define ITM_IWR_ATVALIDM_Msk (1ul & lt; & lt; ITM_IWR_ATVALIDM_Pos) /*! & lt; ITM IWR: ATVALIDM Mask */
/* ITM Integration Read Register Definitions */
#define ITM_IRR_ATREADYM_Pos 0 /*! & lt; ITM IRR: ATREADYM Position */
#define ITM_IRR_ATREADYM_Msk (1ul & lt; & lt; ITM_IRR_ATREADYM_Pos) /*! & lt; ITM IRR: ATREADYM Mask */
/* ITM Integration Mode Control Register Definitions */
#define ITM_IMCR_INTEGRATION_Pos 0 /*! & lt; ITM IMCR: INTEGRATION Position */
#define ITM_IMCR_INTEGRATION_Msk (1ul & lt; & lt; ITM_IMCR_INTEGRATION_Pos) /*! & lt; ITM IMCR: INTEGRATION Mask */
/* ITM Lock Status Register Definitions */
#define ITM_LSR_ByteAcc_Pos 2 /*! & lt; ITM LSR: ByteAcc Position */
#define ITM_LSR_ByteAcc_Msk (1ul & lt; & lt; ITM_LSR_ByteAcc_Pos) /*! & lt; ITM LSR: ByteAcc Mask */
#define ITM_LSR_Access_Pos 1 /*! & lt; ITM LSR: Access Position */
#define ITM_LSR_Access_Msk (1ul & lt; & lt; ITM_LSR_Access_Pos) /*! & lt; ITM LSR: Access Mask */
#define ITM_LSR_Present_Pos 0 /*! & lt; ITM LSR: Present Position */
#define ITM_LSR_Present_Msk (1ul & lt; & lt; ITM_LSR_Present_Pos) /*! & lt; ITM LSR: Present Mask */
/*@}*/ /* end of group CMSIS_CM3_ITM */
/** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type
memory mapped structure for Interrupt Type
@{
*/
typedef struct
{
uint32_t RESERVED0;
__I uint32_t ICTR; /*! & lt; Offset: 0x04 Interrupt Control Type Register */
#if ((defined __CM3_REV) & & (__CM3_REV & gt; = 0x200))
__IO uint32_t ACTLR; /*! & lt; Offset: 0x08 Auxiliary Control Register */
#else
uint32_t RESERVED1;
#endif
} InterruptType_Type;
/* Interrupt Controller Type Register Definitions */
#define InterruptType_ICTR_INTLINESNUM_Pos 0 /*! & lt; InterruptType ICTR: INTLINESNUM Position */
#define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful & lt; & lt; InterruptType_ICTR_INTLINESNUM_Pos) /*! & lt; InterruptType ICTR: INTLINESNUM Mask */
/* Auxiliary Control Register Definitions */
#define InterruptType_ACTLR_DISFOLD_Pos 2 /*! & lt; InterruptType ACTLR: DISFOLD Position */
#define InterruptType_ACTLR_DISFOLD_Msk (1ul & lt; & lt; InterruptType_ACTLR_DISFOLD_Pos) /*! & lt; InterruptType ACTLR: DISFOLD Mask */
#define InterruptType_ACTLR_DISDEFWBUF_Pos 1 /*! & lt; InterruptType ACTLR: DISDEFWBUF Position */
#define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul & lt; & lt; InterruptType_ACTLR_DISDEFWBUF_Pos) /*! & lt; InterruptType ACTLR: DISDEFWBUF Mask */
#define InterruptType_ACTLR_DISMCYCINT_Pos 0 /*! & lt; InterruptType ACTLR: DISMCYCINT Position */
#define InterruptType_ACTLR_DISMCYCINT_Msk (1ul & lt; & lt; InterruptType_ACTLR_DISMCYCINT_Pos) /*! & lt; InterruptType ACTLR: DISMCYCINT Mask */
/*@}*/ /* end of group CMSIS_CM3_InterruptType */
#if defined (__MPU_PRESENT) & & (__MPU_PRESENT == 1)
/** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU
memory mapped structure for Memory Protection Unit (MPU)
@{
*/
typedef struct
{
__I uint32_t TYPE; /*! & lt; Offset: 0x00 MPU Type Register */
__IO uint32_t CTRL; /*! & lt; Offset: 0x04 MPU Control Register */
__IO uint32_t RNR; /*! & lt; Offset: 0x08 MPU Region RNRber Register */
__IO uint32_t RBAR; /*! & lt; Offset: 0x0C MPU Region Base Address Register */
__IO uint32_t RASR; /*! & lt; Offset: 0x10 MPU Region Attribute and Size Register */
__IO uint32_t RBAR_A1; /*! & lt; Offset: 0x14 MPU Alias 1 Region Base Address Register */
__IO uint32_t RASR_A1; /*! & lt; Offset: 0x18 MPU Alias 1 Region Attribute and Size Register */
__IO uint32_t RBAR_A2; /*! & lt; Offset: 0x1C MPU Alias 2 Region Base Address Register */
__IO uint32_t RASR_A2; /*! & lt; Offset: 0x20 MPU Alias 2 Region Attribute and Size Register */
__IO uint32_t RBAR_A3; /*! & lt; Offset: 0x24 MPU Alias 3 Region Base Address Register */
__IO uint32_t RASR_A3; /*! & lt; Offset: 0x28 MPU Alias 3 Region Attribute and Size Register */
} MPU_Type;
/* MPU Type Register */
#define MPU_TYPE_IREGION_Pos 16 /*! & lt; MPU TYPE: IREGION Position */
#define MPU_TYPE_IREGION_Msk (0xFFul & lt; & lt; MPU_TYPE_IREGION_Pos) /*! & lt; MPU TYPE: IREGION Mask */
#define MPU_TYPE_DREGION_Pos 8 /*! & lt; MPU TYPE: DREGION Position */
#define MPU_TYPE_DREGION_Msk (0xFFul & lt; & lt; MPU_TYPE_DREGION_Pos) /*! & lt; MPU TYPE: DREGION Mask */
#define MPU_TYPE_SEPARATE_Pos 0 /*! & lt; MPU TYPE: SEPARATE Position */
#define MPU_TYPE_SEPARATE_Msk (1ul & lt; & lt; MPU_TYPE_SEPARATE_Pos) /*! & lt; MPU TYPE: SEPARATE Mask */
/* MPU Control Register */
#define MPU_CTRL_PRIVDEFENA_Pos 2 /*! & lt; MPU CTRL: PRIVDEFENA Position */
#define MPU_CTRL_PRIVDEFENA_Msk (1ul & lt; & lt; MPU_CTRL_PRIVDEFENA_Pos) /*! & lt; MPU CTRL: PRIVDEFENA Mask */
#define MPU_CTRL_HFNMIENA_Pos 1 /*! & lt; MPU CTRL: HFNMIENA Position */
#define MPU_CTRL_HFNMIENA_Msk (1ul & lt; & lt; MPU_CTRL_HFNMIENA_Pos) /*! & lt; MPU CTRL: HFNMIENA Mask */
#define MPU_CTRL_ENABLE_Pos 0 /*! & lt; MPU CTRL: ENABLE Position */
#define MPU_CTRL_ENABLE_Msk (1ul & lt; & lt; MPU_CTRL_ENABLE_Pos) /*! & lt; MPU CTRL: ENABLE Mask */
/* MPU Region Number Register */
#define MPU_RNR_REGION_Pos 0 /*! & lt; MPU RNR: REGION Position */
#define MPU_RNR_REGION_Msk (0xFFul & lt; & lt; MPU_RNR_REGION_Pos) /*! & lt; MPU RNR: REGION Mask */
/* MPU Region Base Address Register */
#define MPU_RBAR_ADDR_Pos 5 /*! & lt; MPU RBAR: ADDR Position */
#define MPU_RBAR_ADDR_Msk (0x7FFFFFFul & lt; & lt; MPU_RBAR_ADDR_Pos) /*! & lt; MPU RBAR: ADDR Mask */
#define MPU_RBAR_VALID_Pos 4 /*! & lt; MPU RBAR: VALID Position */
#define MPU_RBAR_VALID_Msk (1ul & lt; & lt; MPU_RBAR_VALID_Pos) /*! & lt; MPU RBAR: VALID Mask */
#define MPU_RBAR_REGION_Pos 0 /*! & lt; MPU RBAR: REGION Position */
#define MPU_RBAR_REGION_Msk (0xFul & lt; & lt; MPU_RBAR_REGION_Pos) /*! & lt; MPU RBAR: REGION Mask */
/* MPU Region Attribute and Size Register */
#define MPU_RASR_XN_Pos 28 /*! & lt; MPU RASR: XN Position */
#define MPU_RASR_XN_Msk (1ul & lt; & lt; MPU_RASR_XN_Pos) /*! & lt; MPU RASR: XN Mask */
#define MPU_RASR_AP_Pos 24 /*! & lt; MPU RASR: AP Position */
#define MPU_RASR_AP_Msk (7ul & lt; & lt; MPU_RASR_AP_Pos) /*! & lt; MPU RASR: AP Mask */
#define MPU_RASR_TEX_Pos 19 /*! & lt; MPU RASR: TEX Position */
#define MPU_RASR_TEX_Msk (7ul & lt; & lt; MPU_RASR_TEX_Pos) /*! & lt; MPU RASR: TEX Mask */
#define MPU_RASR_S_Pos 18 /*! & lt; MPU RASR: Shareable bit Position */
#define MPU_RASR_S_Msk (1ul & lt; & lt; MPU_RASR_S_Pos) /*! & lt; MPU RASR: Shareable bit Mask */
#define MPU_RASR_C_Pos 17 /*! & lt; MPU RASR: Cacheable bit Position */
#define MPU_RASR_C_Msk (1ul & lt; & lt; MPU_RASR_C_Pos) /*! & lt; MPU RASR: Cacheable bit Mask */
#define MPU_RASR_B_Pos 16 /*! & lt; MPU RASR: Bufferable bit Position */
#define MPU_RASR_B_Msk (1ul & lt; & lt; MPU_RASR_B_Pos) /*! & lt; MPU RASR: Bufferable bit Mask */
#define MPU_RASR_SRD_Pos 8 /*! & lt; MPU RASR: Sub-Region Disable Position */
#define MPU_RASR_SRD_Msk (0xFFul & lt; & lt; MPU_RASR_SRD_Pos) /*! & lt; MPU RASR: Sub-Region Disable Mask */
#define MPU_RASR_SIZE_Pos 1 /*! & lt; MPU RASR: Region Size Field Position */
#define MPU_RASR_SIZE_Msk (0x1Ful & lt; & lt; MPU_RASR_SIZE_Pos) /*! & lt; MPU RASR: Region Size Field Mask */
#define MPU_RASR_ENA_Pos 0 /*! & lt; MPU RASR: Region enable bit Position */
#define MPU_RASR_ENA_Msk (0x1Ful & lt; & lt; MPU_RASR_ENA_Pos) /*! & lt; MPU RASR: Region enable bit Disable Mask */
/*@}*/ /* end of group CMSIS_CM3_MPU */
#endif
/** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug
memory mapped structure for Core Debug Register
@{
*/
typedef struct
{
__IO uint32_t DHCSR; /*! & lt; Offset: 0x00 Debug Halting Control and Status Register */
__O uint32_t DCRSR; /*! & lt; Offset: 0x04 Debug Core Register Selector Register */
__IO uint32_t DCRDR; /*! & lt; Offset: 0x08 Debug Core Register Data Register */
__IO uint32_t DEMCR; /*! & lt; Offset: 0x0C Debug Exception and Monitor Control Register */
} CoreDebug_Type;
/* Debug Halting Control and Status Register */
#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*! & lt; CoreDebug DHCSR: DBGKEY Position */
#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul & lt; & lt; CoreDebug_DHCSR_DBGKEY_Pos) /*! & lt; CoreDebug DHCSR: DBGKEY Mask */
#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*! & lt; CoreDebug DHCSR: S_RESET_ST Position */
#define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul & lt; & lt; CoreDebug_DHCSR_S_RESET_ST_Pos) /*! & lt; CoreDebug DHCSR: S_RESET_ST Mask */
#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*! & lt; CoreDebug DHCSR: S_RETIRE_ST Position */
#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul & lt; & lt; CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*! & lt; CoreDebug DHCSR: S_RETIRE_ST Mask */
#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*! & lt; CoreDebug DHCSR: S_LOCKUP Position */
#define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul & lt; & lt; CoreDebug_DHCSR_S_LOCKUP_Pos) /*! & lt; CoreDebug DHCSR: S_LOCKUP Mask */
#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*! & lt; CoreDebug DHCSR: S_SLEEP Position */
#define CoreDebug_DHCSR_S_SLEEP_Msk (1ul & lt; & lt; CoreDebug_DHCSR_S_SLEEP_Pos) /*! & lt; CoreDebug DHCSR: S_SLEEP Mask */
#define CoreDebug_DHCSR_S_HALT_Pos 17 /*! & lt; CoreDebug DHCSR: S_HALT Position */
#define CoreDebug_DHCSR_S_HALT_Msk (1ul & lt; & lt; CoreDebug_DHCSR_S_HALT_Pos) /*! & lt; CoreDebug DHCSR: S_HALT Mask */
#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*! & lt; CoreDebug DHCSR: S_REGRDY Position */
#define CoreDebug_DHCSR_S_REGRDY_Msk (1ul & lt; & lt; CoreDebug_DHCSR_S_REGRDY_Pos) /*! & lt; CoreDebug DHCSR: S_REGRDY Mask */
#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*! & lt; CoreDebug DHCSR: C_SNAPSTALL Position */
#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1ul & lt; & lt; CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*! & lt; CoreDebug DHCSR: C_SNAPSTALL Mask */
#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*! & lt; CoreDebug DHCSR: C_MASKINTS Position */
#define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul & lt; & lt; CoreDebug_DHCSR_C_MASKINTS_Pos) /*! & lt; CoreDebug DHCSR: C_MASKINTS Mask */
#define CoreDebug_DHCSR_C_STEP_Pos 2 /*! & lt; CoreDebug DHCSR: C_STEP Position */
#define CoreDebug_DHCSR_C_STEP_Msk (1ul & lt; & lt; CoreDebug_DHCSR_C_STEP_Pos) /*! & lt; CoreDebug DHCSR: C_STEP Mask */
#define CoreDebug_DHCSR_C_HALT_Pos 1 /*! & lt; CoreDebug DHCSR: C_HALT Position */
#define CoreDebug_DHCSR_C_HALT_Msk (1ul & lt; & lt; CoreDebug_DHCSR_C_HALT_Pos) /*! & lt; CoreDebug DHCSR: C_HALT Mask */
#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*! & lt; CoreDebug DHCSR: C_DEBUGEN Position */
#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul & lt; & lt; CoreDebug_DHCSR_C_DEBUGEN_Pos) /*! & lt; CoreDebug DHCSR: C_DEBUGEN Mask */
/* Debug Core Register Selector Register */
#define CoreDebug_DCRSR_REGWnR_Pos 16 /*! & lt; CoreDebug DCRSR: REGWnR Position */
#define CoreDebug_DCRSR_REGWnR_Msk (1ul & lt; & lt; CoreDebug_DCRSR_REGWnR_Pos) /*! & lt; CoreDebug DCRSR: REGWnR Mask */
#define CoreDebug_DCRSR_REGSEL_Pos 0 /*! & lt; CoreDebug DCRSR: REGSEL Position */
#define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful & lt; & lt; CoreDebug_DCRSR_REGSEL_Pos) /*! & lt; CoreDebug DCRSR: REGSEL Mask */
/* Debug Exception and Monitor Control Register */
#define CoreDebug_DEMCR_TRCENA_Pos 24 /*! & lt; CoreDebug DEMCR: TRCENA Position */
#define CoreDebug_DEMCR_TRCENA_Msk (1ul & lt; & lt; CoreDebug_DEMCR_TRCENA_Pos) /*! & lt; CoreDebug DEMCR: TRCENA Mask */
#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*! & lt; CoreDebug DEMCR: MON_REQ Position */
#define CoreDebug_DEMCR_MON_REQ_Msk (1ul & lt; & lt; CoreDebug_DEMCR_MON_REQ_Pos) /*! & lt; CoreDebug DEMCR: MON_REQ Mask */
#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*! & lt; CoreDebug DEMCR: MON_STEP Position */
#define CoreDebug_DEMCR_MON_STEP_Msk (1ul & lt; & lt; CoreDebug_DEMCR_MON_STEP_Pos) /*! & lt; CoreDebug DEMCR: MON_STEP Mask */
#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*! & lt; CoreDebug DEMCR: MON_PEND Position */
#define CoreDebug_DEMCR_MON_PEND_Msk (1ul & lt; & lt; CoreDebug_DEMCR_MON_PEND_Pos) /*! & lt; CoreDebug DEMCR: MON_PEND Mask */
#define CoreDebug_DEMCR_MON_EN_Pos 16 /*! & lt; CoreDebug DEMCR: MON_EN Position */
#define CoreDebug_DEMCR_MON_EN_Msk (1ul & lt; & lt; CoreDebug_DEMCR_MON_EN_Pos) /*! & lt; CoreDebug DEMCR: MON_EN Mask */
#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*! & lt; CoreDebug DEMCR: VC_HARDERR Position */
#define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul & lt; & lt; CoreDebug_DEMCR_VC_HARDERR_Pos) /*! & lt; CoreDebug DEMCR: VC_HARDERR Mask */
#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*! & lt; CoreDebug DEMCR: VC_INTERR Position */
#define CoreDebug_DEMCR_VC_INTERR_Msk (1ul & lt; & lt; CoreDebug_DEMCR_VC_INTERR_Pos) /*! & lt; CoreDebug DEMCR: VC_INTERR Mask */
#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*! & lt; CoreDebug DEMCR: VC_BUSERR Position */
#define CoreDebug_DEMCR_VC_BUSERR_Msk (1ul & lt; & lt; CoreDebug_DEMCR_VC_BUSERR_Pos) /*! & lt; CoreDebug DEMCR: VC_BUSERR Mask */
#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*! & lt; CoreDebug DEMCR: VC_STATERR Position */
#define CoreDebug_DEMCR_VC_STATERR_Msk (1ul & lt; & lt; CoreDebug_DEMCR_VC_STATERR_Pos) /*! & lt; CoreDebug DEMCR: VC_STATERR Mask */
#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*! & lt; CoreDebug DEMCR: VC_CHKERR Position */
#define CoreDebug_DEMCR_VC_CHKERR_Msk (1ul & lt; & lt; CoreDebug_DEMCR_VC_CHKERR_Pos) /*! & lt; CoreDebug DEMCR: VC_CHKERR Mask */
#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*! & lt; CoreDebug DEMCR: VC_NOCPERR Position */
#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1ul & lt; & lt; CoreDebug_DEMCR_VC_NOCPERR_Pos) /*! & lt; CoreDebug DEMCR: VC_NOCPERR Mask */
#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*! & lt; CoreDebug DEMCR: VC_MMERR Position */
#define CoreDebug_DEMCR_VC_MMERR_Msk (1ul & lt; & lt; CoreDebug_DEMCR_VC_MMERR_Pos) /*! & lt; CoreDebug DEMCR: VC_MMERR Mask */
#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*! & lt; CoreDebug DEMCR: VC_CORERESET Position */
#define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul & lt; & lt; CoreDebug_DEMCR_VC_CORERESET_Pos) /*! & lt; CoreDebug DEMCR: VC_CORERESET Mask */
/*@}*/ /* end of group CMSIS_CM3_CoreDebug */
/* Memory mapping of Cortex-M3 Hardware */
#define SCS_BASE (0xE000E000) /*! & lt; System Control Space Base Address */
#define ITM_BASE (0xE0000000) /*! & lt; ITM Base Address */
#define CoreDebug_BASE (0xE000EDF0) /*! & lt; Core Debug Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010) /*! & lt; SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100) /*! & lt; NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00) /*! & lt; System Control Block Base Address */
#define InterruptType ((InterruptType_Type *) SCS_BASE) /*! & lt; Interrupt Type Register */
#define SCB ((SCB_Type *) SCB_BASE) /*! & lt; SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE) /*! & lt; SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE) /*! & lt; NVIC configuration struct */
#define ITM ((ITM_Type *) ITM_BASE) /*! & lt; ITM configuration struct */
#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*! & lt; Core Debug configuration struct */
#if defined (__MPU_PRESENT) & & (__MPU_PRESENT == 1)
#define MPU_BASE (SCS_BASE + 0x0D90) /*! & lt; Memory Protection Unit */
#define MPU ((MPU_Type*) MPU_BASE) /*! & lt; Memory Protection Unit */
#endif
/*@}*/ /* end of group CMSIS_CM3_core_register */
/*******************************************************************************
* Hardware Abstraction Layer
******************************************************************************/
#if defined ( __CC_ARM )
#define __ASM __asm /*! & lt; asm keyword for ARM Compiler */
#define __INLINE __inline /*! & lt; inline keyword for ARM Compiler */
#elif defined ( __ICCARM__ )
#define __ASM __asm /*! & lt; asm keyword for IAR Compiler */
#define __INLINE inline /*! & lt; inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
#elif defined ( __GNUC__ )
#define __ASM __asm /*! & lt; asm keyword for GNU Compiler */
#define __INLINE inline /*! & lt; inline keyword for GNU Compiler */
#elif defined ( __TASKING__ )
#define __ASM __asm /*! & lt; asm keyword for TASKING Compiler */
#define __INLINE inline /*! & lt; inline keyword for TASKING Compiler */
#endif
/* ################### Compiler specific Intrinsics ########################### */
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#define __enable_fault_irq __enable_fiq
#define __disable_fault_irq __disable_fiq
#define __NOP __nop
#define __WFI __wfi
#define __WFE __wfe
#define __SEV __sev
#define __ISB() __isb(0)
#define __DSB() __dsb(0)
#define __DMB() __dmb(0)
#define __REV __rev
#define __RBIT __rbit
#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr))
#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr))
#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr))
#define __STREXB(value, ptr) __strex(value, ptr)
#define __STREXH(value, ptr) __strex(value, ptr)
#define __STREXW(value, ptr) __strex(value, ptr)
/* intrinsic unsigned long long __ldrexd(volatile void *ptr) */
/* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */
/* intrinsic void __enable_irq(); */
/* intrinsic void __disable_irq(); */
/**
* @brief Return the Process Stack Pointer
*
* @return ProcessStackPointer
*
* Return the actual process stack pointer
*/
extern uint32_t __get_PSP(void);
/**
* @brief Set the Process Stack Pointer
*
* @param topOfProcStack Process Stack Pointer
*
* Assign the value ProcessStackPointer to the MSP
* (process stack pointer) Cortex processor register
*/
extern void __set_PSP(uint32_t topOfProcStack);
/**
* @brief Return the Main Stack Pointer
*
* @return Main Stack Pointer
*
* Return the current value of the MSP (main stack pointer)
* Cortex processor register
*/
extern uint32_t __get_MSP(void);
/**
* @brief Set the Main Stack Pointer
*
* @param topOfMainStack Main Stack Pointer
*
* Assign the value mainStackPointer to the MSP
* (main stack pointer) Cortex processor register
*/
extern void __set_MSP(uint32_t topOfMainStack);
/**
* @brief Reverse byte order in unsigned short value
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in unsigned short value
*/
extern uint32_t __REV16(uint16_t value);
/**
* @brief Reverse byte order in signed short value with sign extension to integer
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in signed short value with sign extension to integer
*/
extern int32_t __REVSH(int16_t value);
#if (__ARMCC_VERSION & lt; 400000)
/**
* @brief Remove the exclusive lock created by ldrex
*
* Removes the exclusive lock which is created by ldrex.
*/
extern void __CLREX(void);
/**
* @brief Return the Base Priority value
*
* @return BasePriority
*
* Return the content of the base priority register
*/
extern uint32_t __get_BASEPRI(void);
/**
* @brief Set the Base Priority value
*
* @param basePri BasePriority
*
* Set the base priority register
*/
extern void __set_BASEPRI(uint32_t basePri);
/**
* @brief Return the Priority Mask value
*
* @return PriMask
*
* Return state of the priority mask bit from the priority mask register
*/
extern uint32_t __get_PRIMASK(void);
/**
* @brief Set the Priority Mask value
*
* @param priMask PriMask
*
* Set the priority mask bit in the priority mask register
*/
extern void __set_PRIMASK(uint32_t priMask);
/**
* @brief Return the Fault Mask value
*
* @return FaultMask
*
* Return the content of the fault mask register
*/
extern uint32_t __get_FAULTMASK(void);
/**
* @brief Set the Fault Mask value
*
* @param faultMask faultMask value
*
* Set the fault mask register
*/
extern void __set_FAULTMASK(uint32_t faultMask);
/**
* @brief Return the Control Register value
*
* @return Control value
*
* Return the content of the control register
*/
extern uint32_t __get_CONTROL(void);
/**
* @brief Set the Control Register value
*
* @param control Control value
*
* Set the control register
*/
extern void __set_CONTROL(uint32_t control);
#else /* (__ARMCC_VERSION & gt; = 400000) */
/**
* @brief Remove the exclusive lock created by ldrex
*
* Removes the exclusive lock which is created by ldrex.
*/
#define __CLREX __clrex
/**
* @brief Return the Base Priority value
*
* @return BasePriority
*
* Return the content of the base priority register
*/
static __INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM( " basepri " );
return(__regBasePri);
}
/**
* @brief Set the Base Priority value
*
* @param basePri BasePriority
*
* Set the base priority register
*/
static __INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM( " basepri " );
__regBasePri = (basePri & 0xff);
}
/**
* @brief Return the Priority Mask value
*
* @return PriMask
*
* Return state of the priority mask bit from the priority mask register
*/
static __INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM( " primask " );
return(__regPriMask);
}
/**
* @brief Set the Priority Mask value
*
* @param priMask PriMask
*
* Set the priority mask bit in the priority mask register
*/
static __INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM( " primask " );
__regPriMask = (priMask);
}
/**
* @brief Return the Fault Mask value
*
* @return FaultMask
*
* Return the content of the fault mask register
*/
static __INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM( " faultmask " );
return(__regFaultMask);
}
/**
* @brief Set the Fault Mask value
*
* @param faultMask faultMask value
*
* Set the fault mask register
*/
static __INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM( " faultmask " );
__regFaultMask = (faultMask & 1);
}
/**
* @brief Return the Control Register value
*
* @return Control value
*
* Return the content of the control register
*/
static __INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM( " control " );
return(__regControl);
}
/**
* @brief Set the Control Register value
*
* @param control Control value
*
* Set the control register
*/
static __INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM( " control " );
__regControl = control;
}
#endif /* __ARMCC_VERSION */
#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#define __enable_irq __enable_interrupt /*! & lt; global Interrupt enable */
#define __disable_irq __disable_interrupt /*! & lt; global Interrupt disable */
static __INLINE void __enable_fault_irq() { __ASM ( " cpsie f " ); }
static __INLINE void __disable_fault_irq() { __ASM ( " cpsid f " ); }
#define __NOP __no_operation /*! & lt; no operation intrinsic in IAR Compiler */
static __INLINE void __WFI() { __ASM ( " wfi " ); }
static __INLINE void __WFE() { __ASM ( " wfe " ); }
static __INLINE void __SEV() { __ASM ( " sev " ); }
static __INLINE void __CLREX() { __ASM ( " clrex " ); }
/* intrinsic void __ISB(void) */
/* intrinsic void __DSB(void) */
/* intrinsic void __DMB(void) */
/* intrinsic void __set_PRIMASK(); */
/* intrinsic void __get_PRIMASK(); */
/* intrinsic void __set_FAULTMASK(); */
/* intrinsic void __get_FAULTMASK(); */
/* intrinsic uint32_t __REV(uint32_t value); */
/* intrinsic uint32_t __REVSH(uint32_t value); */
/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */
/* intrinsic unsigned long __LDREX(unsigned long *); */
/**
* @brief Return the Process Stack Pointer
*
* @return ProcessStackPointer
*
* Return the actual process stack pointer
*/
extern uint32_t __get_PSP(void);
/**
* @brief Set the Process Stack Pointer
*
* @param topOfProcStack Process Stack Pointer
*
* Assign the value ProcessStackPointer to the MSP
* (process stack pointer) Cortex processor register
*/
extern void __set_PSP(uint32_t topOfProcStack);
/**
* @brief Return the Main Stack Pointer
*
* @return Main Stack Pointer
*
* Return the current value of the MSP (main stack pointer)
* Cortex processor register
*/
extern uint32_t __get_MSP(void);
/**
* @brief Set the Main Stack Pointer
*
* @param topOfMainStack Main Stack Pointer
*
* Assign the value mainStackPointer to the MSP
* (main stack pointer) Cortex processor register
*/
extern void __set_MSP(uint32_t topOfMainStack);
/**
* @brief Reverse byte order in unsigned short value
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in unsigned short value
*/
extern uint32_t __REV16(uint16_t value);
/**
* @brief Reverse bit order of value
*
* @param value value to reverse
* @return reversed value
*
* Reverse bit order of value
*/
extern uint32_t __RBIT(uint32_t value);
/**
* @brief LDR Exclusive (8 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 8 bit values)
*/
extern uint8_t __LDREXB(uint8_t *addr);
/**
* @brief LDR Exclusive (16 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 16 bit values
*/
extern uint16_t __LDREXH(uint16_t *addr);
/**
* @brief LDR Exclusive (32 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 32 bit values
*/
extern uint32_t __LDREXW(uint32_t *addr);
/**
* @brief STR Exclusive (8 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 8 bit values
*/
extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
/**
* @brief STR Exclusive (16 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 16 bit values
*/
extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
/**
* @brief STR Exclusive (32 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 32 bit values
*/
extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
static __INLINE void __enable_irq() { __ASM volatile ( " cpsie i " ); }
static __INLINE void __disable_irq() { __ASM volatile ( " cpsid i " ); }
static __INLINE void __enable_fault_irq() { __ASM volatile ( " cpsie f " ); }
static __INLINE void __disable_fault_irq() { __ASM volatile ( " cpsid f " ); }
static __INLINE void __NOP() { __ASM volatile ( " nop " ); }
static __INLINE void __WFI() { __ASM volatile ( " wfi " ); }
static __INLINE void __WFE() { __ASM volatile ( " wfe " ); }
static __INLINE void __SEV() { __ASM volatile ( " sev " ); }
static __INLINE void __ISB() { __ASM volatile ( " isb " ); }
static __INLINE void __DSB() { __ASM volatile ( " dsb " ); }
static __INLINE void __DMB() { __ASM volatile ( " dmb " ); }
static __INLINE void __CLREX() { __ASM volatile ( " clrex " ); }
/**
* @brief Return the Process Stack Pointer
*
* @return ProcessStackPointer
*
* Return the actual process stack pointer
*/
extern uint32_t __get_PSP(void);
/**
* @brief Set the Process Stack Pointer
*
* @param topOfProcStack Process Stack Pointer
*
* Assign the value ProcessStackPointer to the MSP
* (process stack pointer) Cortex processor register
*/
extern void __set_PSP(uint32_t topOfProcStack);
/**
* @brief Return the Main Stack Pointer
*
* @return Main Stack Pointer
*
* Return the current value of the MSP (main stack pointer)
* Cortex processor register
*/
extern uint32_t __get_MSP(void);
/**
* @brief Set the Main Stack Pointer
*
* @param topOfMainStack Main Stack Pointer
*
* Assign the value mainStackPointer to the MSP
* (main stack pointer) Cortex processor register
*/
extern void __set_MSP(uint32_t topOfMainStack);
/**
* @brief Return the Base Priority value
*
* @return BasePriority
*
* Return the content of the base priority register
*/
extern uint32_t __get_BASEPRI(void);
/**
* @brief Set the Base Priority value
*
* @param basePri BasePriority
*
* Set the base priority register
*/
extern void __set_BASEPRI(uint32_t basePri);
/**
* @brief Return the Priority Mask value
*
* @return PriMask
*
* Return state of the priority mask bit from the priority mask register
*/
extern uint32_t __get_PRIMASK(void);
/**
* @brief Set the Priority Mask value
*
* @param priMask PriMask
*
* Set the priority mask bit in the priority mask register
*/
extern void __set_PRIMASK(uint32_t priMask);
/**
* @brief Return the Fault Mask value
*
* @return FaultMask
*
* Return the content of the fault mask register
*/
extern uint32_t __get_FAULTMASK(void);
/**
* @brief Set the Fault Mask value
*
* @param faultMask faultMask value
*
* Set the fault mask register
*/
extern void __set_FAULTMASK(uint32_t faultMask);
/**
* @brief Return the Control Register value
*
* @return Control value
*
* Return the content of the control register
*/
extern uint32_t __get_CONTROL(void);
/**
* @brief Set the Control Register value
*
* @param control Control value
*
* Set the control register
*/
extern void __set_CONTROL(uint32_t control);
/**
* @brief Reverse byte order in integer value
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in integer value
*/
extern uint32_t __REV(uint32_t value);
/**
* @brief Reverse byte order in unsigned short value
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in unsigned short value
*/
extern uint32_t __REV16(uint16_t value);
/**
* @brief Reverse byte order in signed short value with sign extension to integer
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in signed short value with sign extension to integer
*/
extern int32_t __REVSH(int16_t value);
/**
* @brief Reverse bit order of value
*
* @param value value to reverse
* @return reversed value
*
* Reverse bit order of value
*/
extern uint32_t __RBIT(uint32_t value);
/**
* @brief LDR Exclusive (8 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 8 bit value
*/
extern uint8_t __LDREXB(uint8_t *addr);
/**
* @brief LDR Exclusive (16 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 16 bit values
*/
extern uint16_t __LDREXH(uint16_t *addr);
/**
* @brief LDR Exclusive (32 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 32 bit values
*/
extern uint32_t __LDREXW(uint32_t *addr);
/**
* @brief STR Exclusive (8 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 8 bit values
*/
extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
/**
* @brief STR Exclusive (16 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 16 bit values
*/
extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
/**
* @brief STR Exclusive (32 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 32 bit values
*/
extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use " carm -?i " to get an up to date list of all instrinsics,
* Including the CMSIS ones.
*/
#endif
/** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface
Core Function Interface containing:
- Core NVIC Functions
- Core SysTick Functions
- Core Reset Functions
*/
/*@{*/
/* ########################## NVIC functions #################################### */
/**
* @brief Set the Priority Grouping in NVIC Interrupt Controller
*
* @param PriorityGroup is priority grouping field
*
* Set the priority grouping field using the required unlock sequence.
* The parameter priority_grouping is assigned to the field
* SCB- & gt; AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used.
* In case of a conflict between priority grouping and available
* priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
*/
static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
reg_value = SCB- & gt; AIRCR; /* read old register configuration */
reg_value & = ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
reg_value = (reg_value |
(0x5FA & lt; & lt; SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp & lt; & lt; 8)); /* Insert write key and priorty group */
SCB- & gt; AIRCR = reg_value;
}
/**
* @brief Get the Priority Grouping from NVIC Interrupt Controller
*
* @return priority grouping field
*
* Get the priority grouping from NVIC Interrupt Controller.
* priority grouping is SCB- & gt; AIRCR [10:8] PRIGROUP field.
*/
static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
{
return ((SCB- & gt; AIRCR & SCB_AIRCR_PRIGROUP_Msk) & gt; & gt; SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
}
/**
* @brief Enable Interrupt in NVIC Interrupt Controller
*
* @param IRQn The positive number of the external interrupt to enable
*
* Enable a device specific interupt in the NVIC interrupt controller.
* The interrupt number cannot be a negative value.
*/
static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
NVIC- & gt; ISER[((uint32_t)(IRQn) & gt; & gt; 5)] = (1 & lt; & lt; ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
}
/**
* @brief Disable the interrupt line for external interrupt specified
*
* @param IRQn The positive number of the external interrupt to disable
*
* Disable a device specific interupt in the NVIC interrupt controller.
* The interrupt number cannot be a negative value.
*/
static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
NVIC- & gt; ICER[((uint32_t)(IRQn) & gt; & gt; 5)] = (1 & lt; & lt; ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
}
/**
* @brief Read the interrupt pending bit for a device specific interrupt source
*
* @param IRQn The number of the device specifc interrupt
* @return 1 = interrupt pending, 0 = interrupt not pending
*
* Read the pending register in NVIC and return 1 if its status is pending,
* otherwise it returns 0
*/
static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
return((uint32_t) ((NVIC- & gt; ISPR[(uint32_t)(IRQn) & gt; & gt; 5] & (1 & lt; & lt; ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
}
/**
* @brief Set the pending bit for an external interrupt
*
* @param IRQn The number of the interrupt for set pending
*
* Set the pending bit for the specified interrupt.
* The interrupt number cannot be a negative value.
*/
static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
NVIC- & gt; ISPR[((uint32_t)(IRQn) & gt; & gt; 5)] = (1 & lt; & lt; ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
}
/**
* @brief Clear the pending bit for an external interrupt
*
* @param IRQn The number of the interrupt for clear pending
*
* Clear the pending bit for the specified interrupt.
* The interrupt number cannot be a negative value.
*/
static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
NVIC- & gt; ICPR[((uint32_t)(IRQn) & gt; & gt; 5)] = (1 & lt; & lt; ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
}
/**
* @brief Read the active bit for an external interrupt
*
* @param IRQn The number of the interrupt for read active bit
* @return 1 = interrupt active, 0 = interrupt not active
*
* Read the active register in NVIC and returns 1 if its status is active,
* otherwise it returns 0.
*/
static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
{
return((uint32_t)((NVIC- & gt; IABR[(uint32_t)(IRQn) & gt; & gt; 5] & (1 & lt; & lt; ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
}
/**
* @brief Set the priority for an interrupt
*
* @param IRQn The number of the interrupt for set priority
* @param priority The priority to set
*
* Set the priority for the specified interrupt. The interrupt
* number can be positive to specify an external (device specific)
* interrupt, or negative to specify an internal (core) interrupt.
*
* Note: The priority cannot be set for every core interrupt.
*/
static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if(IRQn & lt; 0) {
SCB- & gt; SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority & lt; & lt; (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */
else {
NVIC- & gt; IP[(uint32_t)(IRQn)] = ((priority & lt; & lt; (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
}
/**
* @brief Read the priority for an interrupt
*
* @param IRQn The number of the interrupt for get priority
* @return The priority for the interrupt
*
* Read the priority for the specified interrupt. The interrupt
* number can be positive to specify an external (device specific)
* interrupt, or negative to specify an internal (core) interrupt.
*
* The returned priority value is automatically aligned to the implemented
* priority bits of the microcontroller.
*
* Note: The priority cannot be set for every core interrupt.
*/
static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
if(IRQn & lt; 0) {
return((uint32_t)(SCB- & gt; SHP[((uint32_t)(IRQn) & 0xF)-4] & gt; & gt; (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */
else {
return((uint32_t)(NVIC- & gt; IP[(uint32_t)(IRQn)] & gt; & gt; (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
}
/**
* @brief Encode the priority for an interrupt
*
* @param PriorityGroup The used priority group
* @param PreemptPriority The preemptive priority value (starting from 0)
* @param SubPriority The sub priority value (starting from 0)
* @return The encoded priority for the interrupt
*
* Encode the priority for an interrupt with the given priority group,
* preemptive priority value and sub priority value.
* In case of a conflict between priority grouping and available
* priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
*
* The returned priority value can be used for NVIC_SetPriority(...) function
*/
static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7 - PriorityGroupTmp) & gt; __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) & lt; 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
return (
((PreemptPriority & ((1 & lt; & lt; (PreemptPriorityBits)) - 1)) & lt; & lt; SubPriorityBits) |
((SubPriority & ((1 & lt; & lt; (SubPriorityBits )) - 1)))
);
}
/**
* @brief Decode the priority of an interrupt
*
* @param Priority The priority for the interrupt
* @param PriorityGroup The used priority group
* @param pPreemptPriority The preemptive priority value (starting from 0)
* @param pSubPriority The sub priority value (starting from 0)
*
* Decode an interrupt priority value with the given priority group to
* preemptive priority value and sub priority value.
* In case of a conflict between priority grouping and available
* priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
*
* The priority value can be retrieved with NVIC_GetPriority(...) function
*/
static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7 - PriorityGroupTmp) & gt; __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) & lt; 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
*pPreemptPriority = (Priority & gt; & gt; SubPriorityBits) & ((1 & lt; & lt; (PreemptPriorityBits)) - 1);
*pSubPriority = (Priority ) & ((1 & lt; & lt; (SubPriorityBits )) - 1);
}
/* ################################## SysTick function ############################################ */
#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0)
/**
* @brief Initialize and start the SysTick counter and its interrupt.
*
* @param ticks number of ticks between two interrupts
* @return 1 = failed, 0 = successful
*
* Initialise the system tick timer and its interrupt and start the
* system tick timer / counter in free running mode to generate
* periodical interrupts.
*/
static __INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if (ticks & gt; SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
SysTick- & gt; LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1 & lt; & lt; __NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */
SysTick- & gt; VAL = 0; /* Load the SysTick Counter Value */
SysTick- & gt; CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0); /* Function successful */
}
#endif
/* ################################## Reset function ############################################ */
/**
* @brief Initiate a system reset request.
*
* Initiate a system reset request to reset the MCU
*/
static __INLINE void NVIC_SystemReset(void)
{
SCB- & gt; AIRCR = ((0x5FA & lt; & lt; SCB_AIRCR_VECTKEY_Pos) |
(SCB- & gt; AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
__DSB(); /* Ensure completion of memory access */
while(1); /* wait until reset */
}
/*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */
/* ##################################### Debug In/Output function ########################################### */
/** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface
Core Debug Interface containing:
- Core Debug Receive / Transmit Functions
- Core Debug Defines
- Core Debug Variables
*/
/*@{*/
extern volatile int ITM_RxBuffer; /*! & lt; variable to receive characters */
#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*! & lt; value identifying ITM_RxBuffer is ready for next character */
/**
* @brief Outputs a character via the ITM channel 0
*
* @param ch character to output
* @return character to output
*
* The function outputs a character via the ITM channel 0.
* The function returns when no debugger is connected that has booked the output.
* It is blocking when a debugger is connected, but the previous character send is not transmitted.
*/
static __INLINE uint32_t ITM_SendChar (uint32_t ch)
{
if ((CoreDebug- & gt; DEMCR & CoreDebug_DEMCR_TRCENA_Msk) & & /* Trace enabled */
(ITM- & gt; TCR & ITM_TCR_ITMENA_Msk) & & /* ITM enabled */
(ITM- & gt; TER & (1ul & lt; & lt; 0) ) ) /* ITM Port #0 enabled */
{
while (ITM- & gt; PORT[0].u32 == 0);
ITM- & gt; PORT[0].u8 = (uint8_t) ch;
}
return (ch);
}
/**
* @brief Inputs a character via variable ITM_RxBuffer
*
* @return received character, -1 = no character received
*
* The function inputs a character via variable ITM_RxBuffer.
* The function returns when no debugger is connected that has booked the output.
* It is blocking when a debugger is connected, but the previous character send is not transmitted.
*/
static __INLINE int ITM_ReceiveChar (void) {
int ch = -1; /* no character available */
if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
ch = ITM_RxBuffer;
ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
}
return (ch);
}
/**
* @brief Check if a character via variable ITM_RxBuffer is available
*
* @return 1 = character available, 0 = no character available
*
* The function checks variable ITM_RxBuffer whether a character is available or not.
* The function returns '1' if a character is available and '0' if no character is available.
*/
static __INLINE int ITM_CheckChar (void) {
if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
return (0); /* no character available */
} else {
return (1); /* character available */
}
}
/*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */
#ifdef __cplusplus
}
#endif
/*@}*/ /* end of group CMSIS_CM3_core_definitions */
#endif /* __CM3_CORE_H__ */
/*lint -restore */
/***********************************************************************//**
* @file : lpc17xx_nvic.h
* @brief : Contains all macro definitions and function prototypes
* support for Nesting Vectored Interrupt firmware library
* on LPC17xx
* @version : 1.0
* @date : 18. Mar. 2009
* @author : HieuNguyen
**************************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied " AS IS " without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**************************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup NVIC
* @ingroup LPC1700CMSIS_FwLib_Drivers
* @{
*/
#ifndef LPC17XX_NVIC_H_
#define LPC17XX_NVIC_H_
/* Includes ------------------------------------------------------------------- */
#include " LPC177x_8x.h "
#ifdef __cplusplus
extern " C "
{
#endif
/* Public Functions ----------------------------------------------------------- */
/** @defgroup NVIC_Public_Functions
* @{
*/
void NVIC_DeInit(void);
void NVIC_SCBDeInit(void);
void NVIC_SetVTOR(uint32_t offset);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* LPC17XX_NVIC_H_ */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */
/***********************************************************************//**
* @file system_LPC177x_8x.h
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File
* for the NXP LPC177x_8x Device Series
* @version V1.11
* @date 10. November. 2010
* @author NXP MCU SW Application Team
**************************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied " AS IS " without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
#ifndef __SYSTEM_LPC177x_8x_H
#define __SYSTEM_LPC177x_8x_H
#ifdef __cplusplus
extern " C " {
#endif
#include & lt; stdint.h & gt;
extern uint32_t SystemCoreClock; /*! & lt; System Clock Frequency (Core Clock) */
extern uint32_t PeripheralClock; /*! & lt; Peripheral Clock Frequency (Pclk) */
extern uint32_t EMCClock; /*! & lt; EMC Clock */
extern uint32_t USBClock; /*! & lt; USB Frequency */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#define XTAL (16000000UL) /* Oscillator frequency */
#define OSC_CLK ( XTAL) /* Main oscillator frequency */
#define RTC_CLK ( 32768UL) /* RTC oscillator frequency */
#define IRC_OSC (12000000UL) /* Internal RC oscillator frequency */
#define WDT_OSC ( 500000UL) /* Internal WDT oscillator frequency */
/*
//-------- & lt; & lt; & lt; end of configuration section & gt; & gt; & gt; ------------------------------
*/
#ifdef __cplusplus
}
#endif
#endif /* __SYSTEM_LPC177x_8x_H */
/***********************************************************************//**
* @file system_LPC177x_8x.c
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File
* for the NXP LPC177x_8x Device Series
* @version V1.11
* @date 10. November. 2010
* @author NXP MCU SW Application Team
**************************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied " AS IS " without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
#include & lt; stdint.h & gt;
#include " LPC177x_8x.h "
#include " system_LPC177x_8x.h "
/*
//-------- & lt; & lt; & lt; Use Configuration Wizard in Context Menu & gt; & gt; & gt; ------------------
*/
/*--------------------- Clock Configuration ----------------------------------
//
// & lt; e & gt; Clock Configuration
// & lt; h & gt; System Controls and Status Register (SCS)
// & lt; o1.0 & gt; EMC_SHIFT: EMC Shift enable
// & lt; 0= & gt; Static CS addresses match bus width; AD[1] = 0 for 32 bit, AD[0] = 0 for 16+32 bit
// & lt; 1= & gt; Static CS addresses start at LSB 0 regardless of memory width
// & lt; o1.1 & gt; EMC_RESET: EMC Reset disable
// & lt; 0= & gt; EMC will be reset by any chip reset
// & lt; 1= & gt; Portions of EMC will only be reset by POR or BOR
// & lt; o1.2 & gt; EMC_BURST: EMC Burst disable
// & lt; o1.3 & gt; MCIPWR_LEVEL: SD card interface signal SD_PWR Active Level selection
// & lt; 0= & gt; SD_PWR is active low
// & lt; 1= & gt; SD_PWR is active high
// & lt; o1.4 & gt; OSCRANGE: Main Oscillator Range Select
// & lt; 0= & gt; 1 MHz to 20 MHz
// & lt; 1= & gt; 15 MHz to 25 MHz
// & lt; o1.5 & gt; OSCEN: Main Oscillator enable
// & lt; /h & gt;
//
// & lt; h & gt; Clock Source Select Register (CLKSRCSEL)
// & lt; o2.0 & gt; CLKSRC: sysclk and PLL0 clock source selection
// & lt; 0= & gt; Internal RC oscillator
// & lt; 1= & gt; Main oscillator
// & lt; /h & gt;
//
// & lt; e3 & gt; PLL0 Configuration (Main PLL)
// & lt; h & gt; PLL0 Configuration Register (PLL0CFG)
// & lt; i & gt; PLL out clock = (F_cco / (2 * P))
// & lt; i & gt; F_cco = (F_in * M * 2 * P)
// & lt; i & gt; F_in must be in the range of 1 MHz to 25 MHz
// & lt; i & gt; F_cco must be in the range of 9.75 MHz to 160 MHz
// & lt; o4.0..4 & gt; MSEL: PLL Multiplier Selection
// & lt; i & gt; M Value
// & lt; 1-32 & gt; & lt; #-1 & gt;
// & lt; o4.5..6 & gt; PSEL: PLL Divider Selection
// & lt; i & gt; P Value
// & lt; 0= & gt; 1
// & lt; 1= & gt; 2
// & lt; 2= & gt; 4
// & lt; 3= & gt; 8
// & lt; /h & gt;
// & lt; /e & gt;
//
// & lt; e5 & gt; PLL1 Configuration (Alt PLL)
// & lt; h & gt; PLL1 Configuration Register (PLL1CFG)
// & lt; i & gt; PLL out clock = (F_cco / (2 * P))
// & lt; i & gt; F_cco = (F_in * M * 2 * P)
// & lt; i & gt; F_in must be in the range of 1 MHz to 25 MHz
// & lt; i & gt; F_cco must be in the range of 9.75 MHz to 160 MHz
// & lt; o6.0..4 & gt; MSEL: PLL Multiplier Selection
// & lt; i & gt; M Value
// & lt; 1-32 & gt; & lt; #-1 & gt;
// & lt; o6.5..6 & gt; PSEL: PLL Divider Selection
// & lt; i & gt; P Value
// & lt; 0= & gt; 1
// & lt; 1= & gt; 2
// & lt; 2= & gt; 4
// & lt; 3= & gt; 8
// & lt; /h & gt;
// & lt; /e & gt;
//
// & lt; h & gt; CPU Clock Selection Register (CCLKSEL)
// & lt; o7.0..4 & gt; CCLKDIV: CPU clock (CCLK) divider
// & lt; i & gt; 0: The divider is turned off. No clock will be provided to the CPU
// & lt; i & gt; n: The input clock is divided by n to produce the CPU clock
// & lt; 0-31 & gt;
// & lt; o7.8 & gt; CCLKSEL: CPU clock divider input clock selection
// & lt; 0= & gt; sysclk clock
// & lt; 1= & gt; PLL0 clock
// & lt; /h & gt;
//
// & lt; h & gt; USB Clock Selection Register (USBCLKSEL)
// & lt; o8.0..4 & gt; USBDIV: USB clock (source PLL0) divider selection
// & lt; 0= & gt; USB clock off
// & lt; 4= & gt; PLL0 / 4 (PLL0 must be 192Mhz)
// & lt; 6= & gt; PLL0 / 6 (PLL0 must be 288Mhz)
// & lt; o8.8..9 & gt; USBSEL: USB clock divider input clock selection
// & lt; i & gt; When CPU clock is selected, the USB can be accessed
// & lt; i & gt; by software but cannot perform USB functions
// & lt; 0= & gt; CPU clock
// & lt; 1= & gt; PLL0 clock
// & lt; 2= & gt; PLL1 clock
// & lt; /h & gt;
//
// & lt; h & gt; EMC Clock Selection Register (EMCCLKSEL)
// & lt; o9.0 & gt; EMCDIV: EMC clock selection
// & lt; 0= & gt; CPU clock
// & lt; 1= & gt; CPU clock / 2
// & lt; /h & gt;
//
// & lt; h & gt; Peripheral Clock Selection Register (PCLKSEL)
// & lt; o10.0..4 & gt; PCLKDIV: APB Peripheral clock divider
// & lt; i & gt; 0: The divider is turned off. No clock will be provided to APB peripherals
// & lt; i & gt; n: The input clock is divided by n to produce the APB peripheral clock
// & lt; 0-31 & gt;
// & lt; /h & gt;
//
// & lt; h & gt; Power Control for Peripherals Register (PCONP)
// & lt; o11.0 & gt; PCLCD: LCD controller power/clock enable
// & lt; o11.1 & gt; PCTIM0: Timer/Counter 0 power/clock enable
// & lt; o11.2 & gt; PCTIM1: Timer/Counter 1 power/clock enable
// & lt; o11.3 & gt; PCUART0: UART 0 power/clock enable
// & lt; o11.4 & gt; PCUART1: UART 1 power/clock enable
// & lt; o11.5 & gt; PCPWM0: PWM0 power/clock enable
// & lt; o11.6 & gt; PCPWM1: PWM1 power/clock enable
// & lt; o11.7 & gt; PCI2C0: I2C 0 interface power/clock enable
// & lt; o11.8 & gt; PCUART4: UART 4 power/clock enable
// & lt; o11.9 & gt; PCRTC: RTC and Event Recorder power/clock enable
// & lt; o11.10 & gt; PCSSP1: SSP 1 interface power/clock enable
// & lt; o11.11 & gt; PCEMC: External Memory Controller power/clock enable
// & lt; o11.12 & gt; PCADC: A/D converter power/clock enable
// & lt; o11.13 & gt; PCCAN1: CAN controller 1 power/clock enable
// & lt; o11.14 & gt; PCCAN2: CAN controller 2 power/clock enable
// & lt; o11.15 & gt; PCGPIO: IOCON, GPIO, and GPIO interrupts power/clock enable
// & lt; o11.17 & gt; PCMCPWM: Motor Control PWM power/clock enable
// & lt; o11.18 & gt; PCQEI: Quadrature encoder interface power/clock enable
// & lt; o11.19 & gt; PCI2C1: I2C 1 interface power/clock enable
// & lt; o11.20 & gt; PCSSP2: SSP 2 interface power/clock enable
// & lt; o11.21 & gt; PCSSP0: SSP 0 interface power/clock enable
// & lt; o11.22 & gt; PCTIM2: Timer 2 power/clock enable
// & lt; o11.23 & gt; PCTIM3: Timer 3 power/clock enable
// & lt; o11.24 & gt; PCUART2: UART 2 power/clock enable
// & lt; o11.25 & gt; PCUART3: UART 3 power/clock enable
// & lt; o11.26 & gt; PCI2C2: I2C 2 interface power/clock enable
// & lt; o11.27 & gt; PCI2S: I2S interface power/clock enable
// & lt; o11.28 & gt; PCSDC: SD Card interface power/clock enable
// & lt; o11.29 & gt; PCGPDMA: GPDMA function power/clock enable
// & lt; o11.30 & gt; PCENET: Ethernet block power/clock enable
// & lt; o11.31 & gt; PCUSB: USB interface power/clock enable
// & lt; /h & gt;
//
// & lt; h & gt; Clock Output Configuration Register (CLKOUTCFG)
// & lt; o12.0..3 & gt; CLKOUTSEL: Clock Source for CLKOUT Selection
// & lt; 0= & gt; CPU clock
// & lt; 1= & gt; Main Oscillator
// & lt; 2= & gt; Internal RC Oscillator
// & lt; 3= & gt; USB clock
// & lt; 4= & gt; RTC Oscillator
// & lt; 5= & gt; unused
// & lt; 6= & gt; Watchdog Oscillator
// & lt; o12.4..7 & gt; CLKOUTDIV: Output Clock Divider
// & lt; 1-16 & gt; & lt; #-1 & gt;
// & lt; o12.8 & gt; CLKOUT_EN: CLKOUT enable
// & lt; /h & gt;
//
// & lt; /e & gt;
*/
#define CLOCK_SETUP 1
#define SCS_Val 0x00000021
#define CLKSRCSEL_Val 0x00000001
#define PLL0_SETUP 1
//#define PLL0CFG_Val 0x00000006 // 112MHz
#define PLL0CFG_Val 0x00000005 // 112MHz
#define PLL1_SETUP 0
#define PLL1CFG_Val 0x00000023
#define CCLKSEL_Val (0x00000001|(1 & lt; & lt; 8))
#define USBCLK_SETUP 1
#define USBCLKSEL_Val (0x00000001|(0x02 & lt; & lt; 8))
#define EMCCLKSEL_Val 0x00000001
#define PCLKSEL_Val 0x00000002
#define PCONP_Val 0x042887DE
#define CLKOUTCFG_Val 0x00000100
/*--------------------- Flash Accelerator Configuration ----------------------
//
// & lt; e & gt; Flash Accelerator Configuration
// & lt; o1.12..15 & gt; FLASHTIM: Flash Access Time
// & lt; 0= & gt; 1 CPU clock (for CPU clock up to 20 MHz)
// & lt; 1= & gt; 2 CPU clocks (for CPU clock up to 40 MHz)
// & lt; 2= & gt; 3 CPU clocks (for CPU clock up to 60 MHz)
// & lt; 3= & gt; 4 CPU clocks (for CPU clock up to 80 MHz)
// & lt; 4= & gt; 5 CPU clocks (for CPU clock up to 100 MHz)
// & lt; 5= & gt; 6 CPU clocks (for any CPU clock)
// & lt; /e & gt;
*/
#define FLASH_SETUP 1
#define FLASHCFG_Val 0x00005000
/*----------------------------------------------------------------------------
Check the register settings
*----------------------------------------------------------------------------*/
#define CHECK_RANGE(val, min, max) ((val & lt; min) || (val & gt; max))
#define CHECK_RSVD(val, mask) (val & mask)
/* Clock Configuration -------------------------------------------------------*/
#if (CHECK_RSVD((SCS_Val), ~0x0000003F))
#error " SCS: Invalid values of reserved bits! "
#endif
#if (CHECK_RANGE((CLKSRCSEL_Val), 0, 1))
#error " CLKSRCSEL: Value out of range! "
#endif
#if (CHECK_RSVD((PLL0CFG_Val), ~0x0000007F))
#error " PLL0CFG: Invalid values of reserved bits! "
#endif
#if (CHECK_RSVD((PLL1CFG_Val), ~0x0000007F))
#error " PLL1CFG: Invalid values of reserved bits! "
#endif
#if (CHECK_RSVD((CCLKSEL_Val), ~0x0000011F))
#error " CCLKSEL: Invalid values of reserved bits! "
#endif
#if (CHECK_RSVD((USBCLKSEL_Val), ~0x0000031F))
#error " USBCLKSEL: Invalid values of reserved bits! "
#endif
#if (CHECK_RSVD((EMCCLKSEL_Val), ~0x00000001))
#error " EMCCLKSEL: Invalid values of reserved bits! "
#endif
#if (CHECK_RSVD((PCLKSEL_Val), ~0x0000001F))
#error " PCLKSEL: Invalid values of reserved bits! "
#endif
#if (CHECK_RSVD((PCONP_Val), ~0xFFFEFFFF))
#error " PCONP: Invalid values of reserved bits! "
#endif
#if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF))
#error " CLKOUTCFG: Invalid values of reserved bits! "
#endif
/* Flash Accelerator Configuration -------------------------------------------*/
#if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F000))
#warning " FLASHCFG: Invalid values of reserved bits! "
#endif
/*----------------------------------------------------------------------------
DEFINES
*----------------------------------------------------------------------------*/
/* pll_out_clk = F_cco / (2 × P)
F_cco = pll_in_clk × M × 2 × P */
#define __M ((PLL0CFG_Val & 0x1F) + 1)
#define __PLL0_CLK(__F_IN) (__F_IN * __M)
#define __CCLK_DIV (CCLKSEL_Val & 0x1F)
#define __PCLK_DIV (PCLKSEL_Val & 0x1F)
#define __ECLK_DIV ((EMCCLKSEL_Val & 0x01) + 1)
/* Determine core clock frequency according to settings */
#if (CLOCK_SETUP) /* Clock Setup */
#if ((CLKSRCSEL_Val & 0x01) == 1) & & ((SCS_Val & 0x20)== 0)
#error " Main Oscillator is selected as clock source but is not enabled! "
#endif
#if ((CCLKSEL_Val & 0x100) == 0x100) & & (PLL0_SETUP == 0)
#error " Main PLL is selected as clock source but is not enabled! "
#endif
#if ((CCLKSEL_Val & 0x100) == 0) /* cclk = sysclk */
#if ((CLKSRCSEL_Val & 0x01) == 0) /* sysclk = irc_clk */
#define __CORE_CLK (IRC_OSC / __CCLK_DIV)
#define __PER_CLK (IRC_OSC/ __PCLK_DIV)
#define __EMC_CLK (IRC_OSC/ __ECLK_DIV)
#else /* sysclk = osc_clk */
#define __CORE_CLK (OSC_CLK / __CCLK_DIV)
#define __PER_CLK (OSC_CLK/ __PCLK_DIV)
#define __EMC_CLK (OSC_CLK/ __ECLK_DIV)
#endif
#else /* cclk = pll_clk */
#if ((CLKSRCSEL_Val & 0x01) == 0) /* sysclk = irc_clk */
#define __CORE_CLK (__PLL0_CLK(IRC_OSC) / __CCLK_DIV)
#define __PER_CLK (__PLL0_CLK(IRC_OSC) / __PCLK_DIV)
#define __EMC_CLK (__PLL0_CLK(IRC_OSC) / __ECLK_DIV)
#else /* sysclk = osc_clk */
#define __CORE_CLK (__PLL0_CLK(OSC_CLK) / __CCLK_DIV)
#define __PER_CLK (__PLL0_CLK(OSC_CLK) / __PCLK_DIV)
#define __EMC_CLK (__PLL0_CLK(OSC_CLK) / __ECLK_DIV)
#endif
#endif
#else
#define __CORE_CLK (IRC_OSC)
#define __PER_CLK (IRC_OSC)
#define __EMC_CLK (IRC_OSC)
#endif
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = __CORE_CLK;/*! & lt; System Clock Frequency (Core Clock)*/
uint32_t PeripheralClock = __PER_CLK; /*! & lt; Peripheral Clock Frequency (Pclk) */
uint32_t EMCClock = __EMC_CLK; /*! & lt; EMC Clock Frequency */
uint32_t USBClock = (48000000UL); /*! & lt; USB Clock Frequency - this value will
be updated after call SystemCoreClockUpdate, should be 48MHz*/
/*----------------------------------------------------------------------------
Clock functions
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
{
/* Determine clock frequency according to clock register values */
if ((SC- & gt; CCLKSEL & 0x100) == 0) { /* cclk = sysclk */
if ((SC- & gt; CLKSRCSEL & 0x01) == 0) { /* sysclk = irc_clk */
SystemCoreClock = (IRC_OSC / (SC- & gt; CCLKSEL & 0x1F));
PeripheralClock = (IRC_OSC / (SC- & gt; PCLKSEL & 0x1F));
EMCClock = (IRC_OSC / ((SC- & gt; EMCCLKSEL & 0x01)+1));
}
else { /* sysclk = osc_clk */
if ((SC- & gt; SCS & 0x40) == 0) {
SystemCoreClock = 0; /* this should never happen! */
PeripheralClock = 0;
EMCClock = 0;
}
else {
SystemCoreClock = (OSC_CLK / (SC- & gt; CCLKSEL & 0x1F));
PeripheralClock = (OSC_CLK / (SC- & gt; PCLKSEL & 0x1F));
EMCClock = (OSC_CLK / ((SC- & gt; EMCCLKSEL & 0x01)+1));
}
}
}
else { /* cclk = pll_clk */
if ((SC- & gt; PLL0STAT & 0x100) == 0) { /* PLL0 not enabled */
SystemCoreClock = 0; /* this should never happen! */
PeripheralClock = 0;
EMCClock = 0;
}
else {
if ((SC- & gt; CLKSRCSEL & 0x01) == 0) { /* sysclk = irc_clk */
SystemCoreClock = (IRC_OSC * ((SC- & gt; PLL0STAT & 0x1F) + 1) / (SC- & gt; CCLKSEL & 0x1F));
PeripheralClock = (IRC_OSC * ((SC- & gt; PLL0STAT & 0x1F) + 1) / (SC- & gt; PCLKSEL & 0x1F));
EMCClock = (IRC_OSC * ((SC- & gt; PLL0STAT & 0x1F) + 1) / ((SC- & gt; EMCCLKSEL & 0x01)+1));
}
else { /* sysclk = osc_clk */
if ((SC- & gt; SCS & 0x40) == 0) {
SystemCoreClock = 0; /* this should never happen! */
PeripheralClock = 0;
EMCClock = 0;
}
else {
SystemCoreClock = (OSC_CLK * ((SC- & gt; PLL0STAT & 0x1F) + 1) / (SC- & gt; CCLKSEL & 0x1F));
PeripheralClock = (OSC_CLK * ((SC- & gt; PLL0STAT & 0x1F) + 1) / (SC- & gt; PCLKSEL & 0x1F));
EMCClock = (OSC_CLK * ((SC- & gt; PLL0STAT & 0x1F) + 1) / ((SC- & gt; EMCCLKSEL & 0x01)+1));
}
}
}
}
/* ---update USBClock------------------*/
if(SC- & gt; USBCLKSEL & (0x01 & lt; & lt; 8))//Use PLL0 as the input to the USB clock divider
{
switch (SC- & gt; USBCLKSEL & 0x1F)
{
case 0:
USBClock = 0; //no clock will be provided to the USB subsystem
break;
case 4:
case 6:
if(SC- & gt; CLKSRCSEL & 0x01) //pll_clk_in = main_osc
USBClock = (OSC_CLK * ((SC- & gt; PLL0STAT & 0x1F) + 1) / (SC- & gt; USBCLKSEL & 0x1F));
else //pll_clk_in = irc_clk
USBClock = (IRC_OSC * ((SC- & gt; PLL0STAT & 0x1F) + 1) / (SC- & gt; USBCLKSEL & 0x1F));
break;
default:
USBClock = 0; /* this should never happen! */
}
}
else if(SC- & gt; USBCLKSEL & (0x02 & lt; & lt; 8))//usb_input_clk = alt_pll (pll1)
{
if(SC- & gt; CLKSRCSEL & 0x01) //pll1_clk_in = main_osc
USBClock = (OSC_CLK * ((SC- & gt; PLL1STAT & 0x1F) + 1));
else //pll1_clk_in = irc_clk
USBClock = (IRC_OSC * ((SC- & gt; PLL0STAT & 0x1F) + 1));
}
else
USBClock = 0; /* this should never happen! */
}
/* Determine clock frequency according to clock register values */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System.
*/
void SystemInit (void)
{
#if (CLOCK_SETUP) /* Clock Setup */
SC- & gt; SCS = SCS_Val;
if (SCS_Val & (1 & lt; & lt; 5)) { // If Main Oscillator is enabled
while ((SC- & gt; SCS & (1 & lt; & lt; 6)) == 0); // Wait for Oscillator to be ready
}
SC- & gt; CLKSRCSEL = CLKSRCSEL_Val; /* Select Clock Source for sysclk/PLL0*/
#if (PLL0_SETUP)
SC- & gt; PLL0CFG = PLL0CFG_Val;
SC- & gt; PLL0CON = 0x01; // PLL0 Enable
SC- & gt; PLL0FEED = 0xAA;
SC- & gt; PLL0FEED = 0x55;
while (!(SC- & gt; PLL0STAT & (1 & lt; & lt; 10)));// Wait for PLOCK0
#endif
SC- & gt; CCLKSEL = CCLKSEL_Val; // Setup Clock Divider
SC- & gt; USBCLKSEL = USBCLKSEL_Val; // Setup USB Clock Divider
SC- & gt; EMCCLKSEL = EMCCLKSEL_Val; // EMC Clock Selection
SC- & gt; PCLKSEL = PCLKSEL_Val; // Peripheral Clock Selection
SC- & gt; PCONP = PCONP_Val; // Power Control for Peripherals
SC- & gt; CLKOUTCFG = CLKOUTCFG_Val; // Clock Output Configuration
#endif
#if (FLASH_SETUP == 1) // Flash Accelerator Setup
SC- & gt; FLASHCFG = FLASHCFG_Val|0x03A;
#endif
SCB- & gt; VTOR = 0x00000000 & 0x3FFFFF80;
}
//*****************************************************************************
// +--+
// | ++----+
// +-++ |
// | |
// +-+--+ |
// | +--+--+
// +----+ Copyright (c) 2011 Code Red Technologies Ltd.
//
// Wrapper for system_LPC177x_8x.h header (added due to name change)
//
// Software License Agreement
//
// The software is owned by Code Red Technologies and/or its suppliers, and is
// protected under applicable copyright laws. All rights are reserved. Any
// use in violation of the foregoing restrictions may subject the user to criminal
// sanctions under applicable laws, as well as to civil liability for the breach
// of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED " AS IS " . NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// USE OF THIS SOFTWARE FOR COMMERCIAL DEVELOPMENT AND/OR EDUCATION IS SUBJECT
// TO A CURRENT END USER LICENSE AGREEMENT (COMMERCIAL OR EDUCATIONAL) WITH
// CODE RED TECHNOLOGIES LTD.
//
//*****************************************************************************
#ifndef CR_SYSTEM_LPC178x_H_
#define CR_SYSTEM_LPC178x_H_
// NXP have changed the name of the CMSIS header files for LPC177x / LPC178x
// parts. This header is provided to act as a wrapper such that code that
// uses the old header filename will redirect automatically to the new
// header. A warning message will also be emitted.
#warning ** Using wrapper header - change your code to include system_LPC177x_8x.h directly **
#include " system_LPC177x_8x.h "
#endif /* CR_SYSTEM_LPC178x_H_ */
/****************************************************************************//**
* @file : startup_LPC17xx.c
* @brief : CMSIS Cortex-M3 Core Device Startup File
* @version : V1.01
* @date : 4. Feb. 2009
*
*----------------------------------------------------------------------------
*
* Copyright (C) 2009 ARM Limited. All rights reserved.
*
* ARM Limited (ARM) is supplying this software for use with Cortex-Mx
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* THIS SOFTWARE IS PROVIDED " AS IS " . NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
// Mod by nio for the .fastcode part
#include " LPC177x_8x.h "
#define WEAK __attribute__ ((weak))
//*****************************************************************************
//
// Forward declaration of the default fault handlers.
//
//*****************************************************************************
/* System exception vector handler */
void WEAK Reset_Handler(void); /* Reset Handler */
void WEAK NMI_Handler(void); /* NMI Handler */
void WEAK HardFault_Handler(void); /* Hard Fault Handler */
void WEAK MemManage_Handler(void); /* MPU Fault Handler */
void WEAK BusFault_Handler(void); /* Bus Fault Handler */
void WEAK UsageFault_Handler(void); /* Usage Fault Handler */
void WEAK SVC_Handler(void); /* SVCall Handler */
void WEAK DebugMon_Handler(void); /* Debug Monitor Handler */
void WEAK PendSV_Handler(void); /* PendSV Handler */
void WEAK SysTick_Handler(void); /* SysTick Handler */
/* External interrupt vector handler */
void WEAK WDT_IRQHandler(void); /* Watchdog Timer */
void WEAK TIMER0_IRQHandler(void); /* Timer0 */
void WEAK TIMER1_IRQHandler(void); /* Timer1 */
void WEAK TIMER2_IRQHandler(void); /* Timer2 */
void WEAK TIMER3_IRQHandler(void); /* Timer3 */
void WEAK UART0_IRQHandler(void); /* UART0 */
void WEAK UART1_IRQHandler(void); /* UART1 */
void WEAK UART2_IRQHandler(void); /* UART2 */
void WEAK UART3_IRQHandler(void); /* UART3 */
void WEAK PWM1_IRQHandler(void); /* PWM1 */
void WEAK I2C0_IRQHandler(void); /* I2C0 */
void WEAK I2C1_IRQHandler(void); /* I2C1 */
void WEAK I2C2_IRQHandler(void); /* I2C2 */
void WEAK SPI_IRQHandler(void); /* SPI */
void WEAK SSP0_IRQHandler(void); /* SSP0 */
void WEAK SSP1_IRQHandler(void); /* SSP1 */
void WEAK PLL0_IRQHandler(void); /* PLL0 (Main PLL) */
void WEAK RTC_IRQHandler(void); /* Real Time Clock */
void WEAK EINT0_IRQHandler(void); /* External Interrupt 0 */
void WEAK EINT1_IRQHandler(void); /* External Interrupt 1 */
void WEAK EINT2_IRQHandler(void); /* External Interrupt 2 */
void WEAK EINT3_IRQHandler(void); /* External Interrupt 3 */
void WEAK ADC_IRQHandler(void); /* A/D Converter */
void WEAK BOD_IRQHandler(void); /* Brown Out Detect */
void WEAK USB_IRQHandler(void); /* USB */
void WEAK CAN_IRQHandler(void); /* CAN */
void WEAK DMA_IRQHandler(void); /* GP DMA */
void WEAK I2S_IRQHandler(void); /* I2S */
void WEAK ENET_IRQHandler(void); /* Ethernet */
void WEAK MCI_IRQHandler(void); /* Repetitive Interrupt Timer */
void WEAK MCPWM_IRQHandler(void); /* Motor Control PWM */
void WEAK QEI_IRQHandler(void); /* Quadrature Encoder Interface */
void WEAK PLL1_IRQHandler(void); /* PLL1 (USB PLL) */
void WEAK USBActivity_IRQHandler(void);
void WEAK CANActivity_IRQHandler(void);
void WEAK UART4_IRQHandler(void);
void WEAK SSP2_IRQHandler(void);
void WEAK LCD_IRQHandler(void);
void WEAK GPIO_IRQHandler(void);
void WEAK PWM0_IRQHandler(void);
void WEAK EEPROM_IRQHandler(void);
/* Exported types --------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
extern unsigned long _etext;
extern unsigned long _sidata; /* start address for the initialization values of the .data section. defined in linker script */
extern unsigned long _sdata; /* start address for the .data section. defined in linker script */
extern unsigned long _edata; /* end address for the .data section. defined in linker script */
extern unsigned long _sifastcode; /* start address for the initialization values of the .fastcode section. defined in linker script */
extern unsigned long _sfastcode; /* start address for the .fastcode section. defined in linker script */
extern unsigned long _efastcode; /* end address for the .fastcode section. defined in linker script */
extern unsigned long _sbss; /* start address for the .bss section. defined in linker script */
extern unsigned long _ebss; /* end address for the .bss section. defined in linker script */
extern unsigned long _sdodatkowy; /* start address for the .bss section. defined in linker script */
extern unsigned long _edodatkowy; /* end address for the .bss section. defined in linker script */
extern void _estack; /* init value for the stack pointer. defined in linker script */
/* Private typedef -----------------------------------------------------------*/
/* function prototypes ------------------------------------------------------*/
void Reset_Handler(void) __attribute__((__interrupt__));
extern int main(void);
/******************************************************************************
*
* The minimal vector table for a Cortex M3. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
#define STACK_SIZE 0x00000200
__attribute__ ((section( " .stackarea " )))
/* static */ unsigned long pulStack[STACK_SIZE];
__attribute__ ((section( " .isr_vector " )))
void (* const g_pfnVectors[])(void) =
{
/* & _estack, // The initial stack pointer */
(void (*)(void))((unsigned long)pulStack + sizeof(pulStack)), // The initial stack pointer
Reset_Handler, /* Reset Handler */
NMI_Handler, /* NMI Handler */
HardFault_Handler, /* Hard Fault Handler */
MemManage_Handler, /* MPU Fault Handler */
BusFault_Handler, /* Bus Fault Handler */
UsageFault_Handler, /* Usage Fault Handler */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
SVC_Handler, /* SVCall Handler */
DebugMon_Handler, /* Debug Monitor Handler */
0, /* Reserved */
PendSV_Handler, /* PendSV Handler */
SysTick_Handler, /* SysTick Handler */
// External Interrupts
WDT_IRQHandler, /* Watchdog Timer */
TIMER0_IRQHandler, /* Timer0 */
TIMER1_IRQHandler, /* Timer1 */
TIMER2_IRQHandler, /* Timer2 */
TIMER3_IRQHandler, /* Timer3 */
UART0_IRQHandler, /* UART0 */
UART1_IRQHandler, /* UART1 */
UART2_IRQHandler, /* UART2 */
UART3_IRQHandler, /* UART3 */
PWM1_IRQHandler, /* PWM1 */
I2C0_IRQHandler, /* I2C0 */
I2C1_IRQHandler, /* I2C1 */
I2C2_IRQHandler, /* I2C2 */
SPI_IRQHandler, /* SPI */
SSP0_IRQHandler, /* SSP0 */
SSP1_IRQHandler, /* SSP1 */
PLL0_IRQHandler, /* PLL0 (Main PLL) */
RTC_IRQHandler, /* Real Time Clock */
EINT0_IRQHandler, /* External Interrupt 0 */
EINT1_IRQHandler, /* External Interrupt 1 */
EINT2_IRQHandler, /* External Interrupt 2 */
EINT3_IRQHandler, /* External Interrupt 3 */
ADC_IRQHandler, /* A/D Converter */
BOD_IRQHandler, /* Brown Out Detect */
USB_IRQHandler, /* USB */
CAN_IRQHandler, /* CAN */
DMA_IRQHandler, /* GP DMA */
I2S_IRQHandler, /* I2S */
ENET_IRQHandler, /* Ethernet */
MCI_IRQHandler, /* SD MCI */
MCPWM_IRQHandler, /* Motor Control PWM */
QEI_IRQHandler, /* Quadrature Encoder Interface */
PLL1_IRQHandler, /* PLL1 (USB PLL) */
USBActivity_IRQHandler,
CANActivity_IRQHandler,
UART4_IRQHandler,
SSP2_IRQHandler,
LCD_IRQHandler,
GPIO_IRQHandler,
PWM0_IRQHandler,
EEPROM_IRQHandler,
};
/*******************************************************************************
* Function Name : Reset_Handler
* Description : This is the code that gets called when the processor first starts execution
* following a reset event. Only the absolutely necessary set is performed,
* after which the application supplied main() routine is called.
* Input :
* Output :
* Return :
*******************************************************************************/
#include " system_LPC177x_8x.h "
void Reset_Handler(void)
{
unsigned long *pulDest;
unsigned long *pulSrc;
asm( " mov R0, #0x00 " );
asm( " msr CONTROL, R0 " );
SystemInit();
// Copy the data segment initializers from flash to SRAM in ROM mode
if ( & _sidata != & _sdata) { // only if needed
pulSrc = & _sidata;
for(pulDest = & _sdata; pulDest & lt; & _edata; ) {
*(pulDest++) = *(pulSrc++);
}
}
// Copy the .fastcode code from ROM to SRAM
if ( & _sifastcode != & _sfastcode) { // only if needed
pulSrc = & _sifastcode;
for(pulDest = & _sfastcode; pulDest & lt; & _efastcode; ) {
*(pulDest++) = *(pulSrc++);
}
}
// Zero fill the bss segment.
for(pulDest = & _sbss; pulDest & lt; & _ebss; )
*(pulDest++) = 0;
// for(pulDest = & _sdodatkowy; pulDest & lt; & _edodatkowy; )
// *(pulDest++) = 0;
main();
}
//*****************************************************************************
//
// Provide weak aliases for each Exception handler to the Default_Handler.
// As they are weak aliases, any function with the same name will override
// this definition.
//
//*****************************************************************************
#pragma weak MemManage_Handler = Default_Handler /* MPU Fault Handler */
#pragma weak BusFault_Handler = Default_Handler /* Bus Fault Handler */
#pragma weak UsageFault_Handler = Default_Handler /* Usage Fault Handler */
#pragma weak SVC_Handler = Default_Handler /* SVCall Handler */
#pragma weak DebugMon_Handler = Default_Handler /* Debug Monitor Handler */
#pragma weak PendSV_Handler = Default_Handler /* PendSV Handler */
#pragma weak SysTick_Handler = Default_Handler /* SysTick Handler */
/* External interrupt vector handler */
#pragma weak WDT_IRQHandler = Default_Handler /* Watchdog Timer */
#pragma weak TIMER0_IRQHandler = Default_Handler /* Timer0 */
#pragma weak TIMER1_IRQHandler = Default_Handler /* Timer1 */
#pragma weak TIMER2_IRQHandler = Default_Handler /* Timer2 */
#pragma weak TIMER3_IRQHandler = Default_Handler /* Timer3 */
#pragma weak UART0_IRQHandler = Default_Handler /* UART0 */
#pragma weak UART1_IRQHandler = Default_Handler /* UART1 */
#pragma weak UART2_IRQHandler = Default_Handler /* UART2 */
#pragma weak UART3_IRQHandler = Default_Handler /* UART3 */
#pragma weak PWM1_IRQHandler = Default_Handler /* PWM1 */
#pragma weak I2C0_IRQHandler = Default_Handler /* I2C0 */
#pragma weak I2C1_IRQHandler = Default_Handler /* I2C1 */
#pragma weak I2C2_IRQHandler = Default_Handler /* I2C2 */
#pragma weak SPI_IRQHandler = Default_Handler /* SPI */
#pragma weak SSP0_IRQHandler = Default_Handler /* SSP0 */
#pragma weak SSP1_IRQHandler = Default_Handler /* SSP1 */
#pragma weak PLL0_IRQHandler = Default_Handler /* PLL0 (Main PLL) */
#pragma weak RTC_IRQHandler = Default_Handler /* Real Time Clock */
#pragma weak EINT0_IRQHandler = Default_Handler /* External Interrupt 0 */
#pragma weak EINT1_IRQHandler = Default_Handler /* External Interrupt 1 */
#pragma weak EINT2_IRQHandler = Default_Handler /* External Interrupt 2 */
#pragma weak EINT3_IRQHandler = Default_Handler /* External Interrupt 3 */
#pragma weak ADC_IRQHandler = Default_Handler /* A/D Converter */
#pragma weak BOD_IRQHandler = Default_Handler /* Brown Out Detect */
#pragma weak USB_IRQHandler = Default_Handler /* USB */
#pragma weak CAN_IRQHandler = Default_Handler /* CAN */
#pragma weak DMA_IRQHandler = Default_Handler /* GP DMA */
#pragma weak I2S_IRQHandler = Default_Handler /* I2S */
#pragma weak ENET_IRQHandler = Default_Handler /* Ethernet */
#pragma weak MCI_IRQHandler = Default_Handler /* Repetitive Interrupt Timer */
#pragma weak MCPWM_IRQHandler = Default_Handler /* Motor Control PWM */
#pragma weak QEI_IRQHandler = Default_Handler /* Quadrature Encoder Interface */
#pragma weak PLL1_IRQHandler = Default_Handler /* PLL1 (USB PLL) */
#pragma weak UART4_IRQHandler = Default_Handler
#pragma weak SSP2_IRQHandler= Default_Handler
#pragma weak LCD_IRQHandler= Default_Handler
#pragma weak GPIO_IRQHandler= Default_Handler
#pragma weak PWM0_IRQHandler= Default_Handler
#pragma weak EEPROM_IRQHandler= Default_Handler
//*****************************************************************************
//
// This is the code that gets called when the processor receives an unexpected
// interrupt. This simply enters an infinite loop, preserving the system state
// for examination by a debugger.
//
//*****************************************************************************
void Default_Handler(void) {
// Go into an infinite loop.
//
while (1) {
}
}
/***********************************************************************
* $Id: LPC177x_8x.h 6698 2011-03-03 21:20:50Z nxp21346 $
*
* Project: LPC177x_8x CMSIS Package
*
* Description: Cortex-M3 Core Peripheral Access Layer Header File for
* NXP LPC177x_8x Series.
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied " AS IS " without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
#ifndef __LPC177x_8x_H__
#define __LPC177x_8x_H__
/*
* ==========================================================================
* ---------- Interrupt Number Definition -----------------------------------
* ==========================================================================
*/
typedef enum IRQn
{
/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
NonMaskableInt_IRQn = -14, /*! & lt; 2 Non Maskable Interrupt */
MemoryManagement_IRQn = -12, /*! & lt; 4 Cortex-M3 Memory Management Interrupt */
BusFault_IRQn = -11, /*! & lt; 5 Cortex-M3 Bus Fault Interrupt */
UsageFault_IRQn = -10, /*! & lt; 6 Cortex-M3 Usage Fault Interrupt */
SVCall_IRQn = -5, /*! & lt; 11 Cortex-M3 SV Call Interrupt */
DebugMonitor_IRQn = -4, /*! & lt; 12 Cortex-M3 Debug Monitor Interrupt */
PendSV_IRQn = -2, /*! & lt; 14 Cortex-M3 Pend SV Interrupt */
SysTick_IRQn = -1, /*! & lt; 15 Cortex-M3 System Tick Interrupt */
/****** LPC177x_8x Specific Interrupt Numbers *******************************************************/
WDT_IRQn = 0, /*! & lt; Watchdog Timer Interrupt */
TIMER0_IRQn = 1, /*! & lt; Timer0 Interrupt */
TIMER1_IRQn = 2, /*! & lt; Timer1 Interrupt */
TIMER2_IRQn = 3, /*! & lt; Timer2 Interrupt */
TIMER3_IRQn = 4, /*! & lt; Timer3 Interrupt */
UART0_IRQn = 5, /*! & lt; UART0 Interrupt */
UART1_IRQn = 6, /*! & lt; UART1 Interrupt */
UART2_IRQn = 7, /*! & lt; UART2 Interrupt */
UART3_IRQn = 8, /*! & lt; UART3 Interrupt */
PWM1_IRQn = 9, /*! & lt; PWM1 Interrupt */
I2C0_IRQn = 10, /*! & lt; I2C0 Interrupt */
I2C1_IRQn = 11, /*! & lt; I2C1 Interrupt */
I2C2_IRQn = 12, /*! & lt; I2C2 Interrupt */
Reserved0_IRQn = 13, /*! & lt; Reserved */
SSP0_IRQn = 14, /*! & lt; SSP0 Interrupt */
SSP1_IRQn = 15, /*! & lt; SSP1 Interrupt */
PLL0_IRQn = 16, /*! & lt; PLL0 Lock (Main PLL) Interrupt */
RTC_IRQn = 17, /*! & lt; Real Time Clock Interrupt */
EINT0_IRQn = 18, /*! & lt; External Interrupt 0 Interrupt */
EINT1_IRQn = 19, /*! & lt; External Interrupt 1 Interrupt */
EINT2_IRQn = 20, /*! & lt; External Interrupt 2 Interrupt */
EINT3_IRQn = 21, /*! & lt; External Interrupt 3 Interrupt */
ADC_IRQn = 22, /*! & lt; A/D Converter Interrupt */
BOD_IRQn = 23, /*! & lt; Brown-Out Detect Interrupt */
USB_IRQn = 24, /*! & lt; USB Interrupt */
CAN_IRQn = 25, /*! & lt; CAN Interrupt */
DMA_IRQn = 26, /*! & lt; General Purpose DMA Interrupt */
I2S_IRQn = 27, /*! & lt; I2S Interrupt */
ENET_IRQn = 28, /*! & lt; Ethernet Interrupt */
MCI_IRQn = 29, /*! & lt; SD/MMC card I/F Interrupt */
MCPWM_IRQn = 30, /*! & lt; Motor Control PWM Interrupt */
QEI_IRQn = 31, /*! & lt; Quadrature Encoder Interface Interrupt */
PLL1_IRQn = 32, /*! & lt; PLL1 Lock (USB PLL) Interrupt */
USBActivity_IRQn = 33, /*! & lt; USB Activity interrupt */
CANActivity_IRQn = 34, /*! & lt; CAN Activity interrupt */
UART4_IRQn = 35, /*! & lt; UART4 Interrupt */
SSP2_IRQn = 36, /*! & lt; SSP2 Interrupt */
LCD_IRQn = 37, /*! & lt; LCD Interrupt */
GPIO_IRQn = 38, /*! & lt; GPIO Interrupt */
PWM0_IRQn = 39, /*! & lt; PWM0 Interrupt */
EEPROM_IRQn = 40, /*! & lt; EEPROM Interrupt */
} IRQn_Type;
/*
* ==========================================================================
* ----------- Processor and Core Peripheral Section ------------------------
* ==========================================================================
*/
/* Configuration of the Cortex-M3 Processor and Core Peripherals */
#define __MPU_PRESENT 1 /*! & lt; MPU present or not */
#define __NVIC_PRIO_BITS 5 /*! & lt; Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*! & lt; Set to 1 if different SysTick Config is used */
#include " core_cm3.h " /* Cortex-M3 processor and core peripherals */
//#include " system_LPC177x_8x.h " /* System Header */
/******************************************************************************/
/* Device Specific Peripheral registers structures */
/******************************************************************************/
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/*------------- System Control (SC) ------------------------------------------*/
typedef struct
{
__IO uint32_t FLASHCFG; /*! & lt; Offset: 0x000 (R/W) Flash Accelerator Configuration Register */
uint32_t RESERVED0[31];
__IO uint32_t PLL0CON; /*! & lt; Offset: 0x080 (R/W) PLL0 Control Register */
__IO uint32_t PLL0CFG; /*! & lt; Offset: 0x084 (R/W) PLL0 Configuration Register */
__I uint32_t PLL0STAT; /*! & lt; Offset: 0x088 (R/ ) PLL0 Status Register */
__O uint32_t PLL0FEED; /*! & lt; Offset: 0x08C ( /W) PLL0 Feed Register */
uint32_t RESERVED1[4];
__IO uint32_t PLL1CON; /*! & lt; Offset: 0x0A0 (R/W) PLL1 Control Register */
__IO uint32_t PLL1CFG; /*! & lt; Offset: 0x0A4 (R/W) PLL1 Configuration Register */
__I uint32_t PLL1STAT; /*! & lt; Offset: 0x0A8 (R/ ) PLL1 Status Register */
__O uint32_t PLL1FEED; /*! & lt; Offset: 0x0AC ( /W) PLL1 Feed Register */
uint32_t RESERVED2[4];
__IO uint32_t PCON; /*! & lt; Offset: 0x0C0 (R/W) Power Control Register */
__IO uint32_t PCONP; /*! & lt; Offset: 0x0C4 (R/W) Power Control for Peripherals Register */
uint32_t RESERVED3[14];
__IO uint32_t EMCCLKSEL; /*! & lt; Offset: 0x100 (R/W) External Memory Controller Clock Selection Register */
__IO uint32_t CCLKSEL; /*! & lt; Offset: 0x104 (R/W) CPU Clock Selection Register */
__IO uint32_t USBCLKSEL; /*! & lt; Offset: 0x108 (R/W) USB Clock Selection Register */
__IO uint32_t CLKSRCSEL; /*! & lt; Offset: 0x10C (R/W) Clock Source Select Register */
__IO uint32_t CANSLEEPCLR; /*! & lt; Offset: 0x110 (R/W) CAN Sleep Clear Register */
__IO uint32_t CANWAKEFLAGS; /*! & lt; Offset: 0x114 (R/W) CAN Wake-up Flags Register */
uint32_t RESERVED4[10];
__IO uint32_t EXTINT; /*! & lt; Offset: 0x140 (R/W) External Interrupt Flag Register */
uint32_t RESERVED5[1];
__IO uint32_t EXTMODE; /*! & lt; Offset: 0x148 (R/W) External Interrupt Mode Register */
__IO uint32_t EXTPOLAR; /*! & lt; Offset: 0x14C (R/W) External Interrupt Polarity Register */
uint32_t RESERVED6[12];
__IO uint32_t RSID; /*! & lt; Offset: 0x180 (R/W) Reset Source Identification Register */
uint32_t RESERVED7[7];
__IO uint32_t SCS; /*! & lt; Offset: 0x1A0 (R/W) System Controls and Status Register */
__IO uint32_t IRCTRIM; /*! & lt; Offset: 0x1A4 (R/W) Clock Dividers */
__IO uint32_t PCLKSEL; /*! & lt; Offset: 0x1A8 (R/W) Peripheral Clock Selection Register */
uint32_t RESERVED8[3];
__IO uint32_t LCD_CFG; /*! & lt; Offset: 0x1B8 (R/W) LCD Configuration and clocking control Register */
uint32_t RESERVED9[1];
__IO uint32_t USBIntSt; /*! & lt; Offset: 0x1C0 (R/W) USB Interrupt Status Register */
__IO uint32_t DMAREQSEL; /*! & lt; Offset: 0x1C4 (R/W) DMA Request Select Register */
__IO uint32_t CLKOUTCFG; /*! & lt; Offset: 0x1C8 (R/W) Clock Output Configuration Register */
__IO uint32_t RSTCON0; /*! & lt; Offset: 0x1CC (R/W) RESET Control0 Register */
__IO uint32_t RSTCON1; /*! & lt; Offset: 0x1D0 (R/W) RESET Control1 Register */
uint32_t RESERVED10[2];
__IO uint32_t EMCDLYCTL; /*! & lt; Offset: 0x1DC (R/W) SDRAM programmable delays */
__IO uint32_t EMCCAL; /*! & lt; Offset: 0x1E0 (R/W) Calibration of programmable delays */
} SC_TypeDef;
/*------------- Pin Connect Block (PINCON) -----------------------------------*/
typedef struct
{
__IO uint32_t P0_0; /* 0x000 */
__IO uint32_t P0_1;
__IO uint32_t P0_2;
__IO uint32_t P0_3;
__IO uint32_t P0_4;
__IO uint32_t P0_5;
__IO uint32_t P0_6;
__IO uint32_t P0_7;
__IO uint32_t P0_8; /* 0x020 */
__IO uint32_t P0_9;
__IO uint32_t P0_10;
__IO uint32_t P0_11;
__IO uint32_t P0_12;
__IO uint32_t P0_13;
__IO uint32_t P0_14;
__IO uint32_t P0_15;
__IO uint32_t P0_16; /* 0x040 */
__IO uint32_t P0_17;
__IO uint32_t P0_18;
__IO uint32_t P0_19;
__IO uint32_t P0_20;
__IO uint32_t P0_21;
__IO uint32_t P0_22;
__IO uint32_t P0_23;
__IO uint32_t P0_24; /* 0x060 */
__IO uint32_t P0_25;
__IO uint32_t P0_26;
__IO uint32_t P0_27;
__IO uint32_t P0_28;
__IO uint32_t P0_29;
__IO uint32_t P0_30;
__IO uint32_t P0_31;
__IO uint32_t P1_0; /* 0x080 */
__IO uint32_t P1_1;
__IO uint32_t P1_2;
__IO uint32_t P1_3;
__IO uint32_t P1_4;
__IO uint32_t P1_5;
__IO uint32_t P1_6;
__IO uint32_t P1_7;
__IO uint32_t P1_8; /* 0x0A0 */
__IO uint32_t P1_9;
__IO uint32_t P1_10;
__IO uint32_t P1_11;
__IO uint32_t P1_12;
__IO uint32_t P1_13;
__IO uint32_t P1_14;
__IO uint32_t P1_15;
__IO uint32_t P1_16; /* 0x0C0 */
__IO uint32_t P1_17;
__IO uint32_t P1_18;
__IO uint32_t P1_19;
__IO uint32_t P1_20;
__IO uint32_t P1_21;
__IO uint32_t P1_22;
__IO uint32_t P1_23;
__IO uint32_t P1_24; /* 0x0E0 */
__IO uint32_t P1_25;
__IO uint32_t P1_26;
__IO uint32_t P1_27;
__IO uint32_t P1_28;
__IO uint32_t P1_29;
__IO uint32_t P1_30;
__IO uint32_t P1_31;
__IO uint32_t P2_0; /* 0x100 */
__IO uint32_t P2_1;
__IO uint32_t P2_2;
__IO uint32_t P2_3;
__IO uint32_t P2_4;
__IO uint32_t P2_5;
__IO uint32_t P2_6;
__IO uint32_t P2_7;
__IO uint32_t P2_8; /* 0x120 */
__IO uint32_t P2_9;
__IO uint32_t P2_10;
__IO uint32_t P2_11;
__IO uint32_t P2_12;
__IO uint32_t P2_13;
__IO uint32_t P2_14;
__IO uint32_t P2_15;
__IO uint32_t P2_16; /* 0x140 */
__IO uint32_t P2_17;
__IO uint32_t P2_18;
__IO uint32_t P2_19;
__IO uint32_t P2_20;
__IO uint32_t P2_21;
__IO uint32_t P2_22;
__IO uint32_t P2_23;
__IO uint32_t P2_24; /* 0x160 */
__IO uint32_t P2_25;
__IO uint32_t P2_26;
__IO uint32_t P2_27;
__IO uint32_t P2_28;
__IO uint32_t P2_29;
__IO uint32_t P2_30;
__IO uint32_t P2_31;
__IO uint32_t P3_0; /* 0x180 */
__IO uint32_t P3_1;
__IO uint32_t P3_2;
__IO uint32_t P3_3;
__IO uint32_t P3_4;
__IO uint32_t P3_5;
__IO uint32_t P3_6;
__IO uint32_t P3_7;
__IO uint32_t P3_8; /* 0x1A0 */
__IO uint32_t P3_9;
__IO uint32_t P3_10;
__IO uint32_t P3_11;
__IO uint32_t P3_12;
__IO uint32_t P3_13;
__IO uint32_t P3_14;
__IO uint32_t P3_15;
__IO uint32_t P3_16; /* 0x1C0 */
__IO uint32_t P3_17;
__IO uint32_t P3_18;
__IO uint32_t P3_19;
__IO uint32_t P3_20;
__IO uint32_t P3_21;
__IO uint32_t P3_22;
__IO uint32_t P3_23;
__IO uint32_t P3_24; /* 0x1E0 */
__IO uint32_t P3_25;
__IO uint32_t P3_26;
__IO uint32_t P3_27;
__IO uint32_t P3_28;
__IO uint32_t P3_29;
__IO uint32_t P3_30;
__IO uint32_t P3_31;
__IO uint32_t P4_0; /* 0x200 */
__IO uint32_t P4_1;
__IO uint32_t P4_2;
__IO uint32_t P4_3;
__IO uint32_t P4_4;
__IO uint32_t P4_5;
__IO uint32_t P4_6;
__IO uint32_t P4_7;
__IO uint32_t P4_8; /* 0x220 */
__IO uint32_t P4_9;
__IO uint32_t P4_10;
__IO uint32_t P4_11;
__IO uint32_t P4_12;
__IO uint32_t P4_13;
__IO uint32_t P4_14;
__IO uint32_t P4_15;
__IO uint32_t P4_16; /* 0x240 */
__IO uint32_t P4_17;
__IO uint32_t P4_18;
__IO uint32_t P4_19;
__IO uint32_t P4_20;
__IO uint32_t P4_21;
__IO uint32_t P4_22;
__IO uint32_t P4_23;
__IO uint32_t P4_24; /* 0x260 */
__IO uint32_t P4_25;
__IO uint32_t P4_26;
__IO uint32_t P4_27;
__IO uint32_t P4_28;
__IO uint32_t P4_29;
__IO uint32_t P4_30;
__IO uint32_t P4_31;
__IO uint32_t P5_0; /* 0x280 */
__IO uint32_t P5_1;
__IO uint32_t P5_2;
__IO uint32_t P5_3;
__IO uint32_t P5_4; /* 0x290 */
} IOCON_TypeDef;
/*------------- General Purpose Input/Output (GPIO) --------------------------*/
typedef struct
{
__IO uint32_t FIODIR;
uint32_t RESERVED0[3];
__IO uint32_t MASK;
__IO uint32_t FIOPIN;
__IO uint32_t FIOSET;
__O uint32_t FIOCLR;
} GPIO_TypeDef;
typedef struct
{
__I uint32_t IntStatus;
__I uint32_t IO0IntStatR;
__I uint32_t IO0IntStatF;
__O uint32_t IO0IntClr;
__IO uint32_t IO0IntEnR;
__IO uint32_t IO0IntEnF;
uint32_t RESERVED0[3];
__I uint32_t IO2IntStatR;
__I uint32_t IO2IntStatF;
__O uint32_t IO2IntClr;
__IO uint32_t IO2IntEnR;
__IO uint32_t IO2IntEnF;
} GPIOINT_TypeDef;
/*------------- Timer (TIM) --------------------------------------------------*/
typedef struct
{
__IO uint32_t IR; /*! & lt; Offset: 0x000 Interrupt Register (R/W) */
__IO uint32_t TCR; /*! & lt; Offset: 0x004 Timer Control Register (R/W) */
__IO uint32_t TC; /*! & lt; Offset: 0x008 Timer Counter Register (R/W) */
__IO uint32_t PR; /*! & lt; Offset: 0x00C Prescale Register (R/W) */
__IO uint32_t PC; /*! & lt; Offset: 0x010 Prescale Counter Register (R/W) */
__IO uint32_t MCR; /*! & lt; Offset: 0x014 Match Control Register (R/W) */
__IO uint32_t MR0; /*! & lt; Offset: 0x018 Match Register 0 (R/W) */
__IO uint32_t MR1; /*! & lt; Offset: 0x01C Match Register 1 (R/W) */
__IO uint32_t MR2; /*! & lt; Offset: 0x020 Match Register 2 (R/W) */
__IO uint32_t MR3; /*! & lt; Offset: 0x024 Match Register 3 (R/W) */
__IO uint32_t CCR; /*! & lt; Offset: 0x028 Capture Control Register (R/W) */
__I uint32_t CR0; /*! & lt; Offset: 0x02C Capture Register 0 (R/ ) */
__I uint32_t CR1; /*! & lt; Offset: 0x030 Capture Register 1 (R/ ) */
uint32_t RESERVED0[2];
__IO uint32_t EMR; /*! & lt; Offset: 0x03C External Match Register (R/W) */
uint32_t RESERVED1[12];
__IO uint32_t CTCR; /*! & lt; Offset: 0x070 Count Control Register (R/W) */
} TIM_TypeDef;
/*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
typedef struct
{
__IO uint32_t IR; /*! & lt; Offset: 0x000 Interrupt Register (R/W) */
__IO uint32_t TCR; /*! & lt; Offset: 0x004 Timer Control Register (R/W) */
__IO uint32_t TC; /*! & lt; Offset: 0x008 Timer Counter Register (R/W) */
__IO uint32_t PR; /*! & lt; Offset: 0x00C Prescale Register (R/W) */
__IO uint32_t PC; /*! & lt; Offset: 0x010 Prescale Counter Register (R/W) */
__IO uint32_t MCR; /*! & lt; Offset: 0x014 Match Control Register (R/W) */
__IO uint32_t MR0; /*! & lt; Offset: 0x018 Match Register 0 (R/W) */
__IO uint32_t MR1; /*! & lt; Offset: 0x01C Match Register 1 (R/W) */
__IO uint32_t MR2; /*! & lt; Offset: 0x020 Match Register 2 (R/W) */
__IO uint32_t MR3; /*! & lt; Offset: 0x024 Match Register 3 (R/W) */
__IO uint32_t CCR; /*! & lt; Offset: 0x028 Capture Control Register (R/W) */
__I uint32_t CR0; /*! & lt; Offset: 0x02C Capture Register 0 (R/ ) */
__I uint32_t CR1; /*! & lt; Offset: 0x030 Capture Register 1 (R/ ) */
__I uint32_t CR2; /*! & lt; Offset: 0x034 Capture Register 2 (R/ ) */
__I uint32_t CR3; /*! & lt; Offset: 0x038 Capture Register 3 (R/ ) */
uint32_t RESERVED0;
__IO uint32_t MR4; /*! & lt; Offset: 0x040 Match Register 4 (R/W) */
__IO uint32_t MR5; /*! & lt; Offset: 0x044 Match Register 5 (R/W) */
__IO uint32_t MR6; /*! & lt; Offset: 0x048 Match Register 6 (R/W) */
__IO uint32_t PCR; /*! & lt; Offset: 0x04C PWM Control Register (R/W) */
__IO uint32_t LER; /*! & lt; Offset: 0x050 Load Enable Register (R/W) */
uint32_t RESERVED1[7];
__IO uint32_t CTCR; /*! & lt; Offset: 0x070 Counter Control Register (R/W) */
} PWM_TypeDef;
/*------------- Universal Asynchronous Receiver Transmitter (UARTx) -----------*/
/* There are three types of UARTs on the chip:
(1) UART0,UART2, and UART3 are the standard UART.
(2) UART1 is the standard with modem capability.
(3) USART(UART4) is the sync/async UART with smart card capability.
More details can be found on the Users Manual. */
#if 0
typedef struct
{
union {
__I uint8_t RBR;
__O uint8_t THR;
__IO uint8_t DLL;
uint32_t RESERVED0;
};
union {
__IO uint8_t DLM;
__IO uint32_t IER;
};
union {
__I uint32_t IIR;
__O uint8_t FCR;
};
__IO uint8_t LCR;
uint8_t RESERVED1[7];
__I uint8_t LSR;
uint8_t RESERVED2[7];
__IO uint8_t SCR;
uint8_t RESERVED3[3];
__IO uint32_t ACR;
__IO uint8_t ICR;
uint8_t RESERVED4[3];
__IO uint8_t FDR;
uint8_t RESERVED5[7];
__IO uint8_t TER;
uint8_t RESERVED6[39];
__I uint8_t FIFOLVL;
} UART_TypeDef;
#else
typedef struct
{
union
{
__I uint8_t RBR;
__O uint8_t THR;
__IO uint8_t DLL;
uint32_t RESERVED0;
};
union
{
__IO uint8_t DLM;
__IO uint32_t IER;
};
union
{
__I uint32_t IIR;
__O uint8_t FCR;
};
__IO uint8_t LCR;
uint8_t RESERVED1[7];//Reserved
__I uint8_t LSR;
uint8_t RESERVED2[7];//Reserved
__IO uint8_t SCR;
uint8_t RESERVED3[3];//Reserved
__IO uint32_t ACR;
__IO uint8_t ICR;
uint8_t RESERVED4[3];//Reserved
__IO uint8_t FDR;
uint8_t RESERVED5[7];//Reserved
__IO uint8_t TER;
uint8_t RESERVED8[27];//Reserved
__IO uint8_t RS485CTRL;
uint8_t RESERVED9[3];//Reserved
__IO uint8_t ADRMATCH;
uint8_t RESERVED10[3];//Reserved
__IO uint8_t RS485DLY;
uint8_t RESERVED11[3];//Reserved
__I uint8_t FIFOLVL;
}UART_TypeDef;
#endif
typedef struct
{
union {
__I uint8_t RBR;
__O uint8_t THR;
__IO uint8_t DLL;
uint32_t RESERVED0;
};
union {
__IO uint8_t DLM;
__IO uint32_t IER;
};
union {
__I uint32_t IIR;
__O uint8_t FCR;
};
__IO uint8_t LCR;
uint8_t RESERVED1[3];
__IO uint8_t MCR;
uint8_t RESERVED2[3];
__I uint8_t LSR;
uint8_t RESERVED3[3];
__I uint8_t MSR;
uint8_t RESERVED4[3];
__IO uint8_t SCR;
uint8_t RESERVED5[3];
__IO uint32_t ACR;
uint32_t RESERVED6;
__IO uint32_t FDR;
uint32_t RESERVED7;
__IO uint8_t TER;
uint8_t RESERVED8[27];
__IO uint8_t RS485CTRL;
uint8_t RESERVED9[3];
__IO uint8_t ADRMATCH;
uint8_t RESERVED10[3];
__IO uint8_t RS485DLY;
uint8_t RESERVED11[3];
__I uint8_t FIFOLVL;
} UART1_TypeDef;
typedef struct
{
union {
__I uint32_t RBR; /*! & lt; Offset: 0x000 Receiver Buffer Register (R/ ) */
__O uint32_t THR; /*! & lt; Offset: 0x000 Transmit Holding Register ( /W) */
__IO uint32_t DLL; /*! & lt; Offset: 0x000 Divisor Latch LSB (R/W) */
};
union {
__IO uint32_t DLM; /*! & lt; Offset: 0x004 Divisor Latch MSB (R/W) */
__IO uint32_t IER; /*! & lt; Offset: 0x000 Interrupt Enable Register (R/W) */
};
union {
__I uint32_t IIR; /*! & lt; Offset: 0x008 Interrupt ID Register (R/ ) */
__O uint32_t FCR; /*! & lt; Offset: 0x008 FIFO Control Register ( /W) */
};
__IO uint32_t LCR; /*! & lt; Offset: 0x00C Line Control Register (R/W) */
__IO uint32_t MCR; /*! & lt; Offset: 0x010 Modem control Register (R/W) */
__I uint32_t LSR; /*! & lt; Offset: 0x014 Line Status Register (R/ ) */
__I uint32_t MSR; /*! & lt; Offset: 0x018 Modem status Register (R/ ) */
__IO uint32_t SCR; /*! & lt; Offset: 0x01C Scratch Pad Register (R/W) */
__IO uint32_t ACR; /*! & lt; Offset: 0x020 Auto-baud Control Register (R/W) */
__IO uint32_t ICR; /*! & lt; Offset: 0x024 irDA Control Register (R/W) */
__IO uint32_t FDR; /*! & lt; Offset: 0x028 Fractional Divider Register (R/W) */
__IO uint32_t OSR; /*! & lt; Offset: 0x02C Over sampling Register (R/W) */
__O uint32_t POP; /*! & lt; Offset: 0x030 NHP Pop Register (W) */
__IO uint32_t MODE; /*! & lt; Offset: 0x034 NHP Mode selection Register (W) */
uint32_t RESERVED0[2];
__IO uint32_t HDEN; /*! & lt; Offset: 0x040 Half duplex Enable Register (R/W) */
uint32_t RESERVED1;
__IO uint32_t SCI_CTRL; /*! & lt; Offset: 0x048 Smart card Interface Control Register (R/W) */
__IO uint32_t RS485CTRL; /*! & lt; Offset: 0x04C RS-485/EIA-485 Control Register (R/W) */
__IO uint32_t ADRMATCH; /*! & lt; Offset: 0x050 RS-485/EIA-485 address match Register (R/W) */
__IO uint32_t RS485DLY; /*! & lt; Offset: 0x054 RS-485/EIA-485 direction control delay Register (R/W) */
__IO uint32_t SYNCCTRL; /*! & lt; Offset: 0x058 Synchronous Mode Control Register (R/W ) */
__IO uint32_t TER; /*! & lt; Offset: 0x05C Transmit Enable Register (R/W) */
uint32_t RESERVED2[989];
__I uint32_t CFG; /*! & lt; Offset: 0xFD4 Configuration Register (R) */
__O uint32_t INTCE; /*! & lt; Offset: 0xFD8 Interrupt Clear Enable Register (W) */
__O uint32_t INTSE; /*! & lt; Offset: 0xFDC Interrupt Set Enable Register (W) */
__I uint32_t INTS; /*! & lt; Offset: 0xFE0 Interrupt Status Register (R) */
__I uint32_t INTE; /*! & lt; Offset: 0xFE4 Interrupt Enable Register (R) */
__O uint32_t INTCS; /*! & lt; Offset: 0xFE8 Interrupt Clear Status Register (W) */
__O uint32_t INTSS; /*! & lt; Offset: 0xFEC Interrupt Set Status Register (W) */
uint32_t RESERVED3[3];
__I uint32_t MID; /*! & lt; Offset: 0xFFC Module Identification Register (R) */
} UART4_TypeDef;
/*------------- Synchronous Serial Communication (SSP) -----------------------*/
typedef struct
{
__IO uint32_t CR0; /*! & lt; Offset: 0x000 Control Register 0 (R/W) */
__IO uint32_t CR1; /*! & lt; Offset: 0x004 Control Register 1 (R/W) */
__IO uint32_t DR; /*! & lt; Offset: 0x008 Data Register (R/W) */
__I uint32_t SR; /*! & lt; Offset: 0x00C Status Registe (R/ ) */
__IO uint32_t CPSR; /*! & lt; Offset: 0x010 Clock Prescale Register (R/W) */
__IO uint32_t IMSC; /*! & lt; Offset: 0x014 Interrupt Mask Set and Clear Register (R/W) */
__IO uint32_t RIS; /*! & lt; Offset: 0x018 Raw Interrupt Status Register (R/W) */
__IO uint32_t MIS; /*! & lt; Offset: 0x01C Masked Interrupt Status Register (R/W) */
__IO uint32_t ICR; /*! & lt; Offset: 0x020 SSPICR Interrupt Clear Register (R/W) */
__IO uint32_t DMACR;
} SSP_TypeDef;
/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
typedef struct
{
__IO uint32_t CONSET; /*! & lt; Offset: 0x000 I2C Control Set Register (R/W) */
__I uint32_t STAT; /*! & lt; Offset: 0x004 I2C Status Register (R/ ) */
__IO uint32_t DAT; /*! & lt; Offset: 0x008 I2C Data Register (R/W) */
__IO uint32_t ADR0; /*! & lt; Offset: 0x00C I2C Slave Address Register 0 (R/W) */
__IO uint32_t SCLH; /*! & lt; Offset: 0x010 SCH Duty Cycle Register High Half Word (R/W) */
__IO uint32_t SCLL; /*! & lt; Offset: 0x014 SCL Duty Cycle Register Low Half Word (R/W) */
__O uint32_t CONCLR; /*! & lt; Offset: 0x018 I2C Control Clear Register ( /W) */
__IO uint32_t MMCTRL; /*! & lt; Offset: 0x01C Monitor mode control register (R/W) */
__IO uint32_t ADR1; /*! & lt; Offset: 0x020 I2C Slave Address Register 1 (R/W) */
__IO uint32_t ADR2; /*! & lt; Offset: 0x024 I2C Slave Address Register 2 (R/W) */
__IO uint32_t ADR3; /*! & lt; Offset: 0x028 I2C Slave Address Register 3 (R/W) */
__I uint32_t DATA_BUFFER; /*! & lt; Offset: 0x02C Data buffer register ( /W) */
__IO uint32_t MASK0; /*! & lt; Offset: 0x030 I2C Slave address mask register 0 (R/W) */
__IO uint32_t MASK1; /*! & lt; Offset: 0x034 I2C Slave address mask register 1 (R/W) */
__IO uint32_t MASK2; /*! & lt; Offset: 0x038 I2C Slave address mask register 2 (R/W) */
__IO uint32_t MASK3; /*! & lt; Offset: 0x03C I2C Slave address mask register 3 (R/W) */
} I2C_TypeDef;
/*------------- Inter IC Sound (I2S) -----------------------------------------*/
typedef struct
{
__IO uint32_t DAO;
__IO uint32_t DAI;
__O uint32_t TXFIFO;
__I uint32_t RXFIFO;
__I uint32_t STATE;
__IO uint32_t DMA1;
__IO uint32_t DMA2;
__IO uint32_t IRQ;
__IO uint32_t TXRATE;
__IO uint32_t RXRATE;
__IO uint32_t TXBITRATE;
__IO uint32_t RXBITRATE;
__IO uint32_t TXMODE;
__IO uint32_t RXMODE;
} I2S_TypeDef;
/*------------- Real-Time Clock (RTC) ----------------------------------------*/
typedef struct
{
__IO uint8_t ILR;
uint8_t RESERVED0[7];
__IO uint8_t CCR;
uint8_t RESERVED1[3];
__IO uint8_t CIIR;
uint8_t RESERVED2[3];
__IO uint8_t AMR;
uint8_t RESERVED3[3];
__I uint32_t CTIME0;
__I uint32_t CTIME1;
__I uint32_t CTIME2;
__IO uint8_t SEC;
uint8_t RESERVED4[3];
__IO uint8_t MIN;
uint8_t RESERVED5[3];
__IO uint8_t HOUR;
uint8_t RESERVED6[3];
__IO uint8_t DOM;
uint8_t RESERVED7[3];
__IO uint8_t DOW;
uint8_t RESERVED8[3];
__IO uint16_t DOY;
uint16_t RESERVED9;
__IO uint8_t MONTH;
uint8_t RESERVED10[3];
__IO uint16_t YEAR;
uint16_t RESERVED11;
__IO uint32_t CALIBRATION;
__IO uint32_t GPREG0;
__IO uint32_t GPREG1;
__IO uint32_t GPREG2;
__IO uint32_t GPREG3;
__IO uint32_t GPREG4;
__IO uint8_t RTC_AUXEN;
uint8_t RESERVED12[3];
__IO uint8_t RTC_AUX;
uint8_t RESERVED13[3];
__IO uint8_t ALSEC;
uint8_t RESERVED14[3];
__IO uint8_t ALMIN;
uint8_t RESERVED15[3];
__IO uint8_t ALHOUR;
uint8_t RESERVED16[3];
__IO uint8_t ALDOM;
uint8_t RESERVED17[3];
__IO uint8_t ALDOW;
uint8_t RESERVED18[3];
__IO uint16_t ALDOY;
uint16_t RESERVED19;
__IO uint8_t ALMON;
uint8_t RESERVED20[3];
__IO uint16_t ALYEAR;
uint16_t RESERVED21;
__IO uint32_t ERSTATUS;
__IO uint32_t ERCONTROL;
__IO uint32_t ERCOUNTERS;
uint32_t RESERVED22;
__IO uint32_t ERFIRSTSTAMP0;
__IO uint32_t ERFIRSTSTAMP1;
__IO uint32_t ERFIRSTSTAMP2;
uint32_t RESERVED23;
__IO uint32_t ERLASTSTAMP0;
__IO uint32_t ERLASTSTAMP1;
__IO uint32_t ERLASTSTAMP2;
} RTC_TypeDef;
/*------------- Watchdog Timer (WDT) -----------------------------------------*/
typedef struct
{
__IO uint8_t MOD;
uint8_t RESERVED0[3];
__IO uint32_t TC;
__O uint8_t FEED;
uint8_t RESERVED1[3];
__I uint32_t TV;
uint32_t RESERVED2;
__IO uint32_t WARNINT;
__IO uint32_t WINDOW;
} WDT_TypeDef;
/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
typedef struct
{
__IO uint32_t CR; /*! & lt; Offset: 0x000 A/D Control Register (R/W) */
__IO uint32_t GDR; /*! & lt; Offset: 0x004 A/D Global Data Register (R/W) */
uint32_t RESERVED0;
__IO uint32_t INTEN; /*! & lt; Offset: 0x00C A/D Interrupt Enable Register (R/W) */
__IO uint32_t DR[8]; /*! & lt; Offset: 0x010-0x02C A/D Channel 0..7 Data Register (R/W) */
__I uint32_t STAT; /*! & lt; Offset: 0x030 A/D Status Register (R/ ) */
__IO uint32_t ADTRM;
} ADC_TypeDef;
/*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
typedef struct
{
__IO uint32_t CR;
__IO uint32_t CTRL;
__IO uint32_t CNTVAL;
} DAC_TypeDef;
/*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
typedef struct
{
__I uint32_t CON;
__O uint32_t CON_SET;
__O uint32_t CON_CLR;
__I uint32_t CAPCON;
__O uint32_t CAPCON_SET;
__O uint32_t CAPCON_CLR;
__IO uint32_t TC0;
__IO uint32_t TC1;
__IO uint32_t TC2;
__IO uint32_t LIM0;
__IO uint32_t LIM1;
__IO uint32_t LIM2;
__IO uint32_t MAT0;
__IO uint32_t MAT1;
__IO uint32_t MAT2;
__IO uint32_t DT;
__IO uint32_t CP;
__IO uint32_t CAP0;
__IO uint32_t CAP1;
__IO uint32_t CAP2;
__I uint32_t INTEN;
__O uint32_t INTEN_SET;
__O uint32_t INTEN_CLR;
__I uint32_t CNTCON;
__O uint32_t CNTCON_SET;
__O uint32_t CNTCON_CLR;
__I uint32_t INTF;
__O uint32_t INTF_SET;
__O uint32_t INTF_CLR;
__O uint32_t CAP_CLR;
} MCPWM_TypeDef;
/*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
typedef struct
{
__O uint32_t CON;
__I uint32_t STAT;
__IO uint32_t CONF;
__I uint32_t POS;
__IO uint32_t MAXPOS;
__IO uint32_t CMPOS0;
__IO uint32_t CMPOS1;
__IO uint32_t CMPOS2;
__I uint32_t INXCNT;
__IO uint32_t INXCMP0;
__IO uint32_t LOAD;
__I uint32_t TIME;
__I uint32_t VEL;
__I uint32_t CAP;
__IO uint32_t VELCOMP;
__IO uint32_t FILTERPHA;
__IO uint32_t FILTERPHB;
__IO uint32_t FILTERINX;
__IO uint32_t WINDOW;
__IO uint32_t INXCMP1;
__IO uint32_t INXCMP2;
uint32_t RESERVED0[993];
__O uint32_t IEC;
__O uint32_t IES;
__I uint32_t INTSTAT;
__I uint32_t IE;
__O uint32_t CLR;
__O uint32_t SET;
} QEI_TypeDef;
/*------------- SD/MMC card Interface (MCI)-----------------------------------*/
typedef struct
{
__IO uint32_t POWER;
__IO uint32_t CLOCK;
__IO uint32_t ARGUMENT;
__IO uint32_t COMMAND;
__I uint32_t RESP_CMD;
__I uint32_t RESP0;
__I uint32_t RESP1;
__I uint32_t RESP2;
__I uint32_t RESP3;
__IO uint32_t DATATMR;
__IO uint32_t DATALEN;
__IO uint32_t DATACTRL;
__I uint32_t DATACNT;
__I uint32_t STATUS;
__O uint32_t CLEAR;
__IO uint32_t MASK0;
uint32_t RESERVED0[2];
__I uint32_t FIFOCNT;
uint32_t RESERVED1[13];
__IO uint32_t FIFO;
} MCI_TypeDef;
/*------------- Controller Area Network (CAN) --------------------------------*/
typedef struct
{
__IO uint32_t mask[512]; /* ID Masks */
} CANAF_RAM_TypeDef;
typedef struct /* Acceptance Filter Registers */
{
__IO uint32_t AFMR;
__IO uint32_t SFF_sa;
__IO uint32_t SFF_GRP_sa;
__IO uint32_t EFF_sa;
__IO uint32_t EFF_GRP_sa;
__IO uint32_t ENDofTable;
__I uint32_t LUTerrAd;
__I uint32_t LUTerr;
__IO uint32_t FCANIE;
__IO uint32_t FCANIC0;
__IO uint32_t FCANIC1;
} CANAF_TypeDef;
typedef struct /* Central Registers */
{
__I uint32_t TxSR;
__I uint32_t RxSR;
__I uint32_t MSR;
} CANCR_TypeDef;
typedef struct /* Controller Registers */
{
__IO uint32_t MOD;
__O uint32_t CMR;
__IO uint32_t GSR;
__I uint32_t ICR;
__IO uint32_t IER;
__IO uint32_t BTR;
__IO uint32_t EWL;
__I uint32_t SR;
__IO uint32_t RFS;
__IO uint32_t RID;
__IO uint32_t RDA;
__IO uint32_t RDB;
__IO uint32_t TFI1;
__IO uint32_t TID1;
__IO uint32_t TDA1;
__IO uint32_t TDB1;
__IO uint32_t TFI2;
__IO uint32_t TID2;
__IO uint32_t TDA2;
__IO uint32_t TDB2;
__IO uint32_t TFI3;
__IO uint32_t TID3;
__IO uint32_t TDA3;
__IO uint32_t TDB3;
} CAN_TypeDef;
/*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
typedef struct /* Common Registers */
{
__I uint32_t DMACIntStat;
__I uint32_t DMACIntTCStat;
__O uint32_t DMACIntTCClear;
__I uint32_t DMACIntErrStat;
__O uint32_t DMACIntErrClr;
__I uint32_t DMACRawIntTCStat;
__I uint32_t DMACRawIntErrStat;
__I uint32_t DMACEnbldChns;
__IO uint32_t DMACSoftBReq;
__IO uint32_t DMACSoftSReq;
__IO uint32_t DMACSoftLBReq;
__IO uint32_t DMACSoftLSReq;
__IO uint32_t DMACConfig;
__IO uint32_t DMACSync;
} GPDMA_TypeDef;
typedef struct /* Channel Registers */
{
__IO uint32_t DMACCSrcAddr;
__IO uint32_t DMACCDestAddr;
__IO uint32_t DMACCLLI;
__IO uint32_t DMACCControl;
__IO uint32_t DMACCConfig;
} GPDMACH_TypeDef;
/*------------- Universal Serial Bus (USB) -----------------------------------*/
typedef struct
{
__I uint32_t Revision; /* USB Host Registers */
__IO uint32_t Control;
__IO uint32_t CommandStatus;
__IO uint32_t InterruptStatus;
__IO uint32_t InterruptEnable;
__IO uint32_t InterruptDisable;
__IO uint32_t HCCA;
__I uint32_t PeriodCurrentED;
__IO uint32_t ControlHeadED;
__IO uint32_t ControlCurrentED;
__IO uint32_t BulkHeadED;
__IO uint32_t BulkCurrentED;
__I uint32_t DoneHead;
__IO uint32_t FmInterval;
__I uint32_t FmRemaining;
__I uint32_t FmNumber;
__IO uint32_t PeriodicStart;
__IO uint32_t LSTreshold;
__IO uint32_t RhDescriptorA;
__IO uint32_t RhDescriptorB;
__IO uint32_t RhStatus;
__IO uint32_t RhPortStatus1;
__IO uint32_t RhPortStatus2;
uint32_t RESERVED0[40];
__I uint32_t Module_ID;
__I uint32_t IntSt; /* USB On-The-Go Registers */
__IO uint32_t IntEn;
__O uint32_t IntSet;
__O uint32_t IntClr;
__IO uint32_t StCtrl;
__IO uint32_t Tmr;
uint32_t RESERVED1[58];
__I uint32_t DevIntSt; /* USB Device Interrupt Registers */
__IO uint32_t DevIntEn;
__O uint32_t DevIntClr;
__O uint32_t DevIntSet;
__O uint32_t CmdCode; /* USB Device SIE Command Registers */
__I uint32_t CmdData;
__I uint32_t RxData; /* USB Device Transfer Registers */
__O uint32_t TxData;
__I uint32_t RxPLen;
__O uint32_t TxPLen;
__IO uint32_t Ctrl;
__O uint32_t DevIntPri;
__I uint32_t EpIntSt; /* USB Device Endpoint Interrupt Regs */
__IO uint32_t EpIntEn;
__O uint32_t EpIntClr;
__O uint32_t EpIntSet;
__O uint32_t EpIntPri;
__IO uint32_t ReEp; /* USB Device Endpoint Realization Reg*/
__O uint32_t EpInd;
__IO uint32_t MaxPSize;
__I uint32_t DMARSt; /* USB Device DMA Registers */
__O uint32_t DMARClr;
__O uint32_t DMARSet;
uint32_t RESERVED2[9];
__IO uint32_t UDCAH;
__I uint32_t EpDMASt;
__O uint32_t EpDMAEn;
__O uint32_t EpDMADis;
__I uint32_t DMAIntSt;
__IO uint32_t DMAIntEn;
uint32_t RESERVED3[2];
__I uint32_t EoTIntSt;
__O uint32_t EoTIntClr;
__O uint32_t EoTIntSet;
__I uint32_t NDDRIntSt;
__O uint32_t NDDRIntClr;
__O uint32_t NDDRIntSet;
__I uint32_t SysErrIntSt;
__O uint32_t SysErrIntClr;
__O uint32_t SysErrIntSet;
uint32_t RESERVED4[15];
union {
__I uint32_t I2C_RX; /* USB OTG I2C Registers */
__O uint32_t I2C_TX;
};
__IO uint32_t I2C_STS;
__IO uint32_t I2C_CTL;
__IO uint32_t I2C_CLKHI;
__O uint32_t I2C_CLKLO;
uint32_t RESERVED5[824];
union {
__IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
__IO uint32_t OTGClkCtrl;
};
union {
__I uint32_t USBClkSt;
__I uint32_t OTGClkSt;
};
} USB_TypeDef;
/*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
typedef struct
{
__IO uint32_t MAC1; /* MAC Registers */
__IO uint32_t MAC2;
__IO uint32_t IPGT;
__IO uint32_t IPGR;
__IO uint32_t CLRT;
__IO uint32_t MAXF;
__IO uint32_t SUPP;
__IO uint32_t TEST;
__IO uint32_t MCFG;
__IO uint32_t MCMD;
__IO uint32_t MADR;
__O uint32_t MWTD;
__I uint32_t MRDD;
__I uint32_t MIND;
uint32_t RESERVED0[2];
__IO uint32_t SA0;
__IO uint32_t SA1;
__IO uint32_t SA2;
uint32_t RESERVED1[45];
__IO uint32_t Command; /* Control Registers */
__I uint32_t Status;
__IO uint32_t RxDescriptor;
__IO uint32_t RxStatus;
__IO uint32_t RxDescriptorNumber;
__I uint32_t RxProduceIndex;
__IO uint32_t RxConsumeIndex;
__IO uint32_t TxDescriptor;
__IO uint32_t TxStatus;
__IO uint32_t TxDescriptorNumber;
__IO uint32_t TxProduceIndex;
__I uint32_t TxConsumeIndex;
uint32_t RESERVED2[10];
__I uint32_t TSV0;
__I uint32_t TSV1;
__I uint32_t RSV;
uint32_t RESERVED3[3];
__IO uint32_t FlowControlCounter;
__I uint32_t FlowControlStatus;
uint32_t RESERVED4[34];
__IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
__I uint32_t RxFilterWoLStatus;
__O uint32_t RxFilterWoLClear;
uint32_t RESERVED5;
__IO uint32_t HashFilterL;
__IO uint32_t HashFilterH;
uint32_t RESERVED6[882];
__I uint32_t IntStatus; /* Module Control Registers */
__IO uint32_t IntEnable;
__O uint32_t IntClear;
__O uint32_t IntSet;
uint32_t RESERVED7;
__IO uint32_t PowerDown;
uint32_t RESERVED8;
__IO uint32_t Module_ID;
} EMAC_TypeDef;
/*------------- LCD controller (LCD) -----------------------------------------*/
typedef struct
{
__IO uint32_t TIMH; /* LCD Registers */
__IO uint32_t TIMV;
__IO uint32_t POL;
__IO uint32_t LE;
__IO uint32_t UPBASE;
__IO uint32_t LPBASE;
__IO uint32_t CTRL;
__IO uint32_t INTMSK;
__I uint32_t INTRAW;
__I uint32_t INTSTAT;
__O uint32_t INTCLR;
__I uint32_t UPCURR;
__I uint32_t LPCURR;
uint32_t RESERVED0[115];
__IO uint32_t PAL[128];
uint32_t RESERVED1[256];
__IO uint32_t CRSR_IMG[256];
__IO uint32_t CRSR_CTRL;
__IO uint32_t CRSR_CFG;
__IO uint32_t CRSR_PAL0;
__IO uint32_t CRSR_PAL1;
__IO uint32_t CRSR_XY;
__IO uint32_t CRSR_CLIP;
uint32_t RESERVED2[2];
__IO uint32_t CRSR_INTMSK;
__O uint32_t CRSR_INTCLR;
__I uint32_t CRSR_INTRAW;
__I uint32_t CRSR_INTSTAT;
} LCD_TypeDef;
/*------------- External Memory Controller (EMC) -----------------------------*/
typedef struct
{
__IO uint32_t Control;
__I uint32_t Status;
__IO uint32_t Config;
uint32_t RESERVED0[5];
__IO uint32_t DynamicControl;
__IO uint32_t DynamicRefresh;
__IO uint32_t DynamicReadConfig;
uint32_t RESERVED1[1];
__IO uint32_t DynamicRP;
__IO uint32_t DynamicRAS;
__IO uint32_t DynamicSREX;
__IO uint32_t DynamicAPR;
__IO uint32_t DynamicDAL;
__IO uint32_t DynamicWR;
__IO uint32_t DynamicRC;
__IO uint32_t DynamicRFC;
__IO uint32_t DynamicXSR;
__IO uint32_t DynamicRRD;
__IO uint32_t DynamicMRD;
uint32_t RESERVED2[9];
__IO uint32_t StaticExtendedWait;
uint32_t RESERVED3[31];
__IO uint32_t DynamicConfig0;
__IO uint32_t DynamicRasCas0;
uint32_t RESERVED4[6];
__IO uint32_t DynamicConfig1;
__IO uint32_t DynamicRasCas1;
uint32_t RESERVED5[6];
__IO uint32_t DynamicConfig2;
__IO uint32_t DynamicRasCas2;
uint32_t RESERVED6[6];
__IO uint32_t DynamicConfig3;
__IO uint32_t DynamicRasCas3;
uint32_t RESERVED7[38];
__IO uint32_t StaticConfig0;
__IO uint32_t StaticWaitWen0;
__IO uint32_t StaticWaitOen0;
__IO uint32_t StaticWaitRd0;
__IO uint32_t StaticWaitPage0;
__IO uint32_t StaticWaitWr0;
__IO uint32_t StaticWaitTurn0;
uint32_t RESERVED8[1];
__IO uint32_t StaticConfig1;
__IO uint32_t StaticWaitWen1;
__IO uint32_t StaticWaitOen1;
__IO uint32_t StaticWaitRd1;
__IO uint32_t StaticWaitPage1;
__IO uint32_t StaticWaitWr1;
__IO uint32_t StaticWaitTurn1;
uint32_t RESERVED9[1];
__IO uint32_t StaticConfig2;
__IO uint32_t StaticWaitWen2;
__IO uint32_t StaticWaitOen2;
__IO uint32_t StaticWaitRd2;
__IO uint32_t StaticWaitPage2;
__IO uint32_t StaticWaitWr2;
__IO uint32_t StaticWaitTurn2;
uint32_t RESERVED10[1];
__IO uint32_t StaticConfig3;
__IO uint32_t StaticWaitWen3;
__IO uint32_t StaticWaitOen3;
__IO uint32_t StaticWaitRd3;
__IO uint32_t StaticWaitPage3;
__IO uint32_t StaticWaitWr3;
__IO uint32_t StaticWaitTurn3;
} EMC_TypeDef;
/*------------- CRC Engine (CRC) -----------------------------------------*/
typedef struct
{
__IO uint32_t MODE;
__IO uint32_t SEED;
union {
__I uint32_t SUM;
__O uint32_t WR_DATA_DWORD;
__O uint16_t WR_DATA_WORD;
uint16_t RESERVED_WORD;
__O uint8_t WR_DATA_BYTE;
uint8_t RESERVED_BYTE[3];
};
} CRC_TypeDef;
/*------------- EEPROM Controller (EEPROM) -----------------------------------*/
typedef struct
{
__IO uint32_t CMD; /* 0x0080 */
__IO uint32_t ADDR;
__IO uint32_t WDATA;
__IO uint32_t RDATA;
__IO uint32_t WSTATE; /* 0x0090 */
__IO uint32_t CLKDIV;
__IO uint32_t PWRDWN; /* 0x0098 */
uint32_t RESERVED0[975];
__IO uint32_t INT_CLR_ENABLE; /* 0x0FD8 */
__IO uint32_t INT_SET_ENABLE;
__IO uint32_t INT_STATUS; /* 0x0FE0 */
__IO uint32_t INT_ENABLE;
__IO uint32_t INT_CLR_STATUS;
__IO uint32_t INT_SET_STATUS;
} EEPROM_TypeDef;
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
/******************************************************************************/
/* Peripheral memory map */
/******************************************************************************/
/* Base addresses */
#define FLASH_BASE (0x00000000UL)
#define RAM_BASE (0x10000000UL)
#define PERI_RAM_BASE (0x20000000UL)
#define APB0_BASE (0x40000000UL)
#define APB1_BASE (0x40080000UL)
#define AHBRAM1_BASE (0x20004000UL)
#define AHB_BASE (0x20080000UL)
#define CM3_BASE (0xE0000000UL)
/* APB0 peripherals */
#define WDT_BASE (APB0_BASE + 0x00000)
#define TIM0_BASE (APB0_BASE + 0x04000)
#define TIM1_BASE (APB0_BASE + 0x08000)
#define UART0_BASE (APB0_BASE + 0x0C000)
#define UART1_BASE (APB0_BASE + 0x10000)
#define PWM0_BASE (APB0_ BASE + 0x14000)
#define PWM1_BASE (APB0_BASE + 0x18000)
#define I2C0_BASE (APB0_BASE + 0x1C000)
#define RTC_BASE (APB0_BASE + 0x24000)
#define GPIOINT_BASE (APB0_BASE + 0x28080)
#define IOCON_BASE (APB0_BASE + 0x2C000)
#define SSP1_BASE (APB0_BASE + 0x30000)
#define ADC_BASE (APB0_BASE + 0x34000)
#define CANAF_RAM_BASE (APB0_BASE + 0x38000)
#define CANAF_BASE (APB0_BASE + 0x3C000)
#define CANCR_BASE (APB0_BASE + 0x40000)
#define CAN1_BASE (APB0_BASE + 0x44000)
#define CAN2_BASE (APB0_BASE + 0x48000)
#define I2C1_BASE (APB0_BASE + 0x5C000)
/* APB1 peripherals */
#define SSP0_BASE (APB1_BASE + 0x08000)
#define DAC_BASE (APB1_BASE + 0x0C000)
#define TIM2_BASE (APB1_BASE + 0x10000)
#define TIM3_BASE (APB1_BASE + 0x14000)
#define UART2_BASE (APB1_BASE + 0x18000)
#define UART3_BASE (APB1_BASE + 0x1C000)
#define I2C2_BASE (APB1_BASE + 0x20000)
#define UART4_BASE (APB1_BASE + 0x24000)
#define I2S_BASE (APB1_BASE + 0x28000)
#define SSP2_BASE (APB1_BASE + 0x2C000)
#define MCPWM_BASE (APB1_BASE + 0x38000)
#define QEI_BASE (APB1_BASE + 0x3C000)
#define MCI_BASE (APB1_BASE + 0x40000)
#define SC_BASE (APB1_BASE + 0x7C000)
/* AHB peripherals */
#define GPDMA_BASE (AHB_BASE + 0x00000)
#define GPDMACH0_BASE (AHB_BASE + 0x00100)
#define GPDMACH1_BASE (AHB_BASE + 0x00120)
#define GPDMACH2_BASE (AHB_BASE + 0x00140)
#define GPDMACH3_BASE (AHB_BASE + 0x00160)
#define GPDMACH4_BASE (AHB_BASE + 0x00180)
#define GPDMACH5_BASE (AHB_BASE + 0x001A0)
#define GPDMACH6_BASE (AHB_BASE + 0x001C0)
#define GPDMACH7_BASE (AHB_BASE + 0x001E0)
#define EMAC_BASE (AHB_BASE + 0x04000)
#define LCD_BASE (AHB_BASE + 0x08000)
#define USB_BASE (AHB_BASE + 0x0C000)
#define CRC_BASE (AHB_BASE + 0x10000)
#define GPIO0_BASE (AHB_BASE + 0x18000)
#define GPIO1_BASE (AHB_BASE + 0x18020)
#define GPIO2_BASE (AHB_BASE + 0x18040)
#define GPIO3_BASE (AHB_BASE + 0x18060)
#define GPIO4_BASE (AHB_BASE + 0x18080)
#define GPIO5_BASE (AHB_BASE + 0x180A0)
#define EMC_BASE (AHB_BASE + 0x1C000)
#define EEPROM_BASE (FLASH_BASE+ 0x200080)
/******************************************************************************/
/* Peripheral declaration */
/******************************************************************************/
#define SC ((SC_TypeDef *) SC_BASE )
#define WDT ((WDT_TypeDef *) WDT_BASE )
#define TIM0 ((TIM_TypeDef *) TIM0_BASE )
#define TIM1 ((TIM_TypeDef *) TIM1_BASE )
#define TIM2 ((TIM_TypeDef *) TIM2_BASE )
#define TIM3 ((TIM_TypeDef *) TIM3_BASE )
#define UART0 ((UART_TypeDef *) UART0_BASE )
#define UART1 ((UART1_TypeDef *) UART1_BASE )
#define UART2 ((UART_TypeDef *) UART2_BASE )
#define UART3 ((UART_TypeDef *) UART3_BASE )
#define UART4 ((UART4_TypeDef *) UART4_BASE )
#define PWM0 ((PWM_TypeDef *) PWM0_BASE )
#define PWM1 ((PWM_TypeDef *) PWM1_BASE )
#define I2C0 ((I2C_TypeDef *) I2C0_BASE )
#define I2C1 ((I2C_TypeDef *) I2C1_BASE )
#define I2C2 ((I2C_TypeDef *) I2C2_BASE )
#define I2S ((I2S_TypeDef *) I2S_BASE )
#define RTC ((RTC_TypeDef *) RTC_BASE )
#define GPIOINT ((GPIOINT_TypeDef *) GPIOINT_BASE )
#define IOCON ((IOCON_TypeDef *) IOCON_BASE )
#define SSP0 ((SSP_TypeDef *) SSP0_BASE )
#define SSP1 ((SSP_TypeDef *) SSP1_BASE )
#define SSP2 ((SSP_TypeDef *) SSP2_BASE )
#define ADC ((ADC_TypeDef *) ADC_BASE )
#define DAC ((DAC_TypeDef *) DAC_BASE )
#define CANAF_RAM ((CANAF_RAM_TypeDef *) CANAF_RAM_BASE)
#define CANAF ((CANAF_TypeDef *) CANAF_BASE )
#define CANCR ((CANCR_TypeDef *) CANCR_BASE )
#define CAN1 ((CAN_TypeDef *) CAN1_BASE )
#define CAN2 ((CAN_TypeDef *) CAN2_BASE )
#define MCPWM ((MCPWM_TypeDef *) MCPWM_BASE )
#define QEI ((QEI_TypeDef *) QEI_BASE )
#define MCI ((MCI_TypeDef *) MCI_BASE )
#define GPDMA ((GPDMA_TypeDef *) GPDMA_BASE )
#define GPDMACH0 ((GPDMACH_TypeDef *) GPDMACH0_BASE )
#define GPDMACH1 ((GPDMACH_TypeDef *) GPDMACH1_BASE )
#define GPDMACH2 ((GPDMACH_TypeDef *) GPDMACH2_BASE )
#define GPDMACH3 ((GPDMACH_TypeDef *) GPDMACH3_BASE )
#define GPDMACH4 ((GPDMACH_TypeDef *) GPDMACH4_BASE )
#define GPDMACH5 ((GPDMACH_TypeDef *) GPDMACH5_BASE )
#define GPDMACH6 ((GPDMACH_TypeDef *) GPDMACH6_BASE )
#define GPDMACH7 ((GPDMACH_TypeDef *) GPDMACH7_BASE )
#define EMAC ((EMAC_TypeDef *) EMAC_BASE )
#define LCD ((LCD_TypeDef *) LCD_BASE )
#define USB ((USB_TypeDef *) USB_BASE )
#define GPIO0 ((GPIO_TypeDef *) GPIO0_BASE )
#define GPIO1 ((GPIO_TypeDef *) GPIO1_BASE )
#define GPIO2 ((GPIO_TypeDef *) GPIO2_BASE )
#define GPIO3 ((GPIO_TypeDef *) GPIO3_BASE )
#define GPIO4 ((GPIO_TypeDef *) GPIO4_BASE )
#define GPIO5 ((GPIO_TypeDef *) GPIO5_BASE )
#define EMC ((EMC_TypeDef *) EMC_BASE )
#define CRC ((CRC_TypeDef *) CRC_BASE )
#define EEPROM ((EEPROM_TypeDef *) EEPROM_BASE )
#endif // __LPC177x_8x_H__
/**************************************************************************//**
* @file core_cm3.c
* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File
* @version V1.30
* @date 30. October 2009
*
* @note
* Copyright (C) 2009 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED " AS IS " . NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#include & lt; stdint.h & gt;
/* define compiler specific symbols */
#if defined ( __CC_ARM )
#define __ASM __asm /*! & lt; asm keyword for ARM Compiler */
#define __INLINE __inline /*! & lt; inline keyword for ARM Compiler */
#elif defined ( __ICCARM__ )
#define __ASM __asm /*! & lt; asm keyword for IAR Compiler */
#define __INLINE inline /*! & lt; inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
#elif defined ( __GNUC__ )
#define __ASM __asm /*! & lt; asm keyword for GNU Compiler */
#define __INLINE inline /*! & lt; inline keyword for GNU Compiler */
#elif defined ( __TASKING__ )
#define __ASM __asm /*! & lt; asm keyword for TASKING Compiler */
#define __INLINE inline /*! & lt; inline keyword for TASKING Compiler */
#endif
/* ################### Compiler specific Intrinsics ########################### */
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
/**
* @brief Return the Process Stack Pointer
*
* @return ProcessStackPointer
*
* Return the actual process stack pointer
*/
__ASM uint32_t __get_PSP(void)
{
mrs r0, psp
bx lr
}
/**
* @brief Set the Process Stack Pointer
*
* @param topOfProcStack Process Stack Pointer
*
* Assign the value ProcessStackPointer to the MSP
* (process stack pointer) Cortex processor register
*/
__ASM void __set_PSP(uint32_t topOfProcStack)
{
msr psp, r0
bx lr
}
/**
* @brief Return the Main Stack Pointer
*
* @return Main Stack Pointer
*
* Return the current value of the MSP (main stack pointer)
* Cortex processor register
*/
__ASM uint32_t __get_MSP(void)
{
mrs r0, msp
bx lr
}
/**
* @brief Set the Main Stack Pointer
*
* @param topOfMainStack Main Stack Pointer
*
* Assign the value mainStackPointer to the MSP
* (main stack pointer) Cortex processor register
*/
__ASM void __set_MSP(uint32_t mainStackPointer)
{
msr msp, r0
bx lr
}
/**
* @brief Reverse byte order in unsigned short value
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in unsigned short value
*/
__ASM uint32_t __REV16(uint16_t value)
{
rev16 r0, r0
bx lr
}
/**
* @brief Reverse byte order in signed short value with sign extension to integer
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in signed short value with sign extension to integer
*/
__ASM int32_t __REVSH(int16_t value)
{
revsh r0, r0
bx lr
}
#if (__ARMCC_VERSION & lt; 400000)
/**
* @brief Remove the exclusive lock created by ldrex
*
* Removes the exclusive lock which is created by ldrex.
*/
__ASM void __CLREX(void)
{
clrex
}
/**
* @brief Return the Base Priority value
*
* @return BasePriority
*
* Return the content of the base priority register
*/
__ASM uint32_t __get_BASEPRI(void)
{
mrs r0, basepri
bx lr
}
/**
* @brief Set the Base Priority value
*
* @param basePri BasePriority
*
* Set the base priority register
*/
__ASM void __set_BASEPRI(uint32_t basePri)
{
msr basepri, r0
bx lr
}
/**
* @brief Return the Priority Mask value
*
* @return PriMask
*
* Return state of the priority mask bit from the priority mask register
*/
__ASM uint32_t __get_PRIMASK(void)
{
mrs r0, primask
bx lr
}
/**
* @brief Set the Priority Mask value
*
* @param priMask PriMask
*
* Set the priority mask bit in the priority mask register
*/
__ASM void __set_PRIMASK(uint32_t priMask)
{
msr primask, r0
bx lr
}
/**
* @brief Return the Fault Mask value
*
* @return FaultMask
*
* Return the content of the fault mask register
*/
__ASM uint32_t __get_FAULTMASK(void)
{
mrs r0, faultmask
bx lr
}
/**
* @brief Set the Fault Mask value
*
* @param faultMask faultMask value
*
* Set the fault mask register
*/
__ASM void __set_FAULTMASK(uint32_t faultMask)
{
msr faultmask, r0
bx lr
}
/**
* @brief Return the Control Register value
*
* @return Control value
*
* Return the content of the control register
*/
__ASM uint32_t __get_CONTROL(void)
{
mrs r0, control
bx lr
}
/**
* @brief Set the Control Register value
*
* @param control Control value
*
* Set the control register
*/
__ASM void __set_CONTROL(uint32_t control)
{
msr control, r0
bx lr
}
#endif /* __ARMCC_VERSION */
#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#pragma diag_suppress=Pe940
/**
* @brief Return the Process Stack Pointer
*
* @return ProcessStackPointer
*
* Return the actual process stack pointer
*/
uint32_t __get_PSP(void)
{
__ASM( " mrs r0, psp " );
__ASM( " bx lr " );
}
/**
* @brief Set the Process Stack Pointer
*
* @param topOfProcStack Process Stack Pointer
*
* Assign the value ProcessStackPointer to the MSP
* (process stack pointer) Cortex processor register
*/
void __set_PSP(uint32_t topOfProcStack)
{
__ASM( " msr psp, r0 " );
__ASM( " bx lr " );
}
/**
* @brief Return the Main Stack Pointer
*
* @return Main Stack Pointer
*
* Return the current value of the MSP (main stack pointer)
* Cortex processor register
*/
uint32_t __get_MSP(void)
{
__ASM( " mrs r0, msp " );
__ASM( " bx lr " );
}
/**
* @brief Set the Main Stack Pointer
*
* @param topOfMainStack Main Stack Pointer
*
* Assign the value mainStackPointer to the MSP
* (main stack pointer) Cortex processor register
*/
void __set_MSP(uint32_t topOfMainStack)
{
__ASM( " msr msp, r0 " );
__ASM( " bx lr " );
}
/**
* @brief Reverse byte order in unsigned short value
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in unsigned short value
*/
uint32_t __REV16(uint16_t value)
{
__ASM( " rev16 r0, r0 " );
__ASM( " bx lr " );
}
/**
* @brief Reverse bit order of value
*
* @param value value to reverse
* @return reversed value
*
* Reverse bit order of value
*/
uint32_t __RBIT(uint32_t value)
{
__ASM( " rbit r0, r0 " );
__ASM( " bx lr " );
}
/**
* @brief LDR Exclusive (8 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 8 bit values)
*/
uint8_t __LDREXB(uint8_t *addr)
{
__ASM( " ldrexb r0, [r0] " );
__ASM( " bx lr " );
}
/**
* @brief LDR Exclusive (16 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 16 bit values
*/
uint16_t __LDREXH(uint16_t *addr)
{
__ASM( " ldrexh r0, [r0] " );
__ASM( " bx lr " );
}
/**
* @brief LDR Exclusive (32 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 32 bit values
*/
uint32_t __LDREXW(uint32_t *addr)
{
__ASM( " ldrex r0, [r0] " );
__ASM( " bx lr " );
}
/**
* @brief STR Exclusive (8 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 8 bit values
*/
uint32_t __STREXB(uint8_t value, uint8_t *addr)
{
__ASM( " strexb r0, r0, [r1] " );
__ASM( " bx lr " );
}
/**
* @brief STR Exclusive (16 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 16 bit values
*/
uint32_t __STREXH(uint16_t value, uint16_t *addr)
{
__ASM( " strexh r0, r0, [r1] " );
__ASM( " bx lr " );
}
/**
* @brief STR Exclusive (32 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 32 bit values
*/
uint32_t __STREXW(uint32_t value, uint32_t *addr)
{
__ASM( " strex r0, r0, [r1] " );
__ASM( " bx lr " );
}
#pragma diag_default=Pe940
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/**
* @brief Return the Process Stack Pointer
*
* @return ProcessStackPointer
*
* Return the actual process stack pointer
*/
uint32_t __get_PSP(void) __attribute__( ( naked ) );
uint32_t __get_PSP(void)
{
uint32_t result=0;
__ASM volatile ( " MRS %0, psp\n\t "
" MOV r0, %0 \n\t "
" BX lr \n\t " : " =r " (result) );
return(result);
}
/**
* @brief Set the Process Stack Pointer
*
* @param topOfProcStack Process Stack Pointer
*
* Assign the value ProcessStackPointer to the MSP
* (process stack pointer) Cortex processor register
*/
void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) );
void __set_PSP(uint32_t topOfProcStack)
{
__ASM volatile ( " MSR psp, %0\n\t "
" BX lr \n\t " : : " r " (topOfProcStack) );
}
/**
* @brief Return the Main Stack Pointer
*
* @return Main Stack Pointer
*
* Return the current value of the MSP (main stack pointer)
* Cortex processor register
*/
uint32_t __get_MSP(void) __attribute__( ( naked ) );
uint32_t __get_MSP(void)
{
uint32_t result=0;
__ASM volatile ( " MRS %0, msp\n\t "
" MOV r0, %0 \n\t "
" BX lr \n\t " : " =r " (result) );
return(result);
}
/**
* @brief Set the Main Stack Pointer
*
* @param topOfMainStack Main Stack Pointer
*
* Assign the value mainStackPointer to the MSP
* (main stack pointer) Cortex processor register
*/
void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) );
void __set_MSP(uint32_t topOfMainStack)
{
__ASM volatile ( " MSR msp, %0\n\t "
" BX lr \n\t " : : " r " (topOfMainStack) );
}
/**
* @brief Return the Base Priority value
*
* @return BasePriority
*
* Return the content of the base priority register
*/
uint32_t __get_BASEPRI(void)
{
uint32_t result=0;
__ASM volatile ( " MRS %0, basepri_max " : " =r " (result) );
return(result);
}
/**
* @brief Set the Base Priority value
*
* @param basePri BasePriority
*
* Set the base priority register
*/
void __set_BASEPRI(uint32_t value)
{
__ASM volatile ( " MSR basepri, %0 " : : " r " (value) );
}
/**
* @brief Return the Priority Mask value
*
* @return PriMask
*
* Return state of the priority mask bit from the priority mask register
*/
uint32_t __get_PRIMASK(void)
{
uint32_t result=0;
__ASM volatile ( " MRS %0, primask " : " =r " (result) );
return(result);
}
/**
* @brief Set the Priority Mask value
*
* @param priMask PriMask
*
* Set the priority mask bit in the priority mask register
*/
void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile ( " MSR primask, %0 " : : " r " (priMask) );
}
/**
* @brief Return the Fault Mask value
*
* @return FaultMask
*
* Return the content of the fault mask register
*/
uint32_t __get_FAULTMASK(void)
{
uint32_t result=0;
__ASM volatile ( " MRS %0, faultmask " : " =r " (result) );
return(result);
}
/**
* @brief Set the Fault Mask value
*
* @param faultMask faultMask value
*
* Set the fault mask register
*/
void __set_FAULTMASK(uint32_t faultMask)
{
__ASM volatile ( " MSR faultmask, %0 " : : " r " (faultMask) );
}
/**
* @brief Return the Control Register value
*
* @return Control value
*
* Return the content of the control register
*/
uint32_t __get_CONTROL(void)
{
uint32_t result=0;
__ASM volatile ( " MRS %0, control " : " =r " (result) );
return(result);
}
/**
* @brief Set the Control Register value
*
* @param control Control value
*
* Set the control register
*/
void __set_CONTROL(uint32_t control)
{
__ASM volatile ( " MSR control, %0 " : : " r " (control) );
}
/**
* @brief Reverse byte order in integer value
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in integer value
*/
uint32_t __REV(uint32_t value)
{
uint32_t result=0;
__ASM volatile ( " rev %0, %1 " : " =r " (result) : " r " (value) );
return(result);
}
/**
* @brief Reverse byte order in unsigned short value
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in unsigned short value
*/
uint32_t __REV16(uint16_t value)
{
uint32_t result=0;
__ASM volatile ( " rev16 %0, %1 " : " =r " (result) : " r " (value) );
return(result);
}
/**
* @brief Reverse byte order in signed short value with sign extension to integer
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in signed short value with sign extension to integer
*/
int32_t __REVSH(int16_t value)
{
uint32_t result=0;
__ASM volatile ( " revsh %0, %1 " : " =r " (result) : " r " (value) );
return(result);
}
/**
* @brief Reverse bit order of value
*
* @param value value to reverse
* @return reversed value
*
* Reverse bit order of value
*/
uint32_t __RBIT(uint32_t value)
{
uint32_t result=0;
__ASM volatile ( " rbit %0, %1 " : " =r " (result) : " r " (value) );
return(result);
}
/**
* @brief LDR Exclusive (8 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 8 bit value
*/
uint8_t __LDREXB(uint8_t *addr)
{
uint8_t result=0;
__ASM volatile ( " ldrexb %0, [%1] " : " =r " (result) : " r " (addr) );
return(result);
}
/**
* @brief LDR Exclusive (16 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 16 bit values
*/
uint16_t __LDREXH(uint16_t *addr)
{
uint16_t result=0;
__ASM volatile ( " ldrexh %0, [%1] " : " =r " (result) : " r " (addr) );
return(result);
}
/**
* @brief LDR Exclusive (32 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 32 bit values
*/
uint32_t __LDREXW(uint32_t *addr)
{
uint32_t result=0;
__ASM volatile ( " ldrex %0, [%1] " : " =r " (result) : " r " (addr) );
return(result);
}
/**
* @brief STR Exclusive (8 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 8 bit values
*/
uint32_t __STREXB(uint8_t value, uint8_t *addr)
{
uint32_t result=0;
__ASM volatile ( " strexb %0, %2, [%1] " : " =r " (result) : " r " (addr), " r " (value) );
return(result);
}
/**
* @brief STR Exclusive (16 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 16 bit values
*/
uint32_t __STREXH(uint16_t value, uint16_t *addr)
{
uint32_t result=0;
__ASM volatile ( " strexh %0, %2, [%1] " : " =r " (result) : " r " (addr), " r " (value) );
return(result);
}
/**
* @brief STR Exclusive (32 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 32 bit values
*/
uint32_t __STREXW(uint32_t value, uint32_t *addr)
{
uint32_t result=0;
__ASM volatile ( " strex %0, %2, [%1] " : " =r " (result) : " r " (addr), " r " (value) );
return(result);
}
#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use " carm -?i " to get an up to date list of all instrinsics,
* Including the CMSIS ones.
*/
#endif
#include " LPC177x_8x.h "
#include " timers.h "
#include " sys.h "
volatile uint32_t msTicks;
void timers_control(void);
// SysTick Interrupt Handler
__attribute__ ((section( " .fastcode " )))
__attribute__((noinline))
void SysTick_Handler(void) {
msTicks++;
/*
static u32 ss=0;
ss++;
if((ss%10) == 0)
{
sprintf((u8*)debug_buf, " tick %d " ,ss);
print_buf((u8*)debug_buf,8,8,0);
}
*/
timers_control();
}
void systick_delay(u32 delayTicks) {
uint32_t currentTicks;
currentTicks = msTicks;
while ((msTicks - currentTicks) & lt; delayTicks);
}
static u8 timers_cnt = 0;
volatile timer_struct_t *volatile timers[MAX_TIMERS]; // wskazniki na timery
/*
problem z one shot mode timer... przy 2 uruchomieniu timera nie wchodzi w funkcje callback ?
*/
void register_timer(timer_struct_t *timer)
{
u8 i;
if(timers_cnt == MAX_TIMERS)
{
while(1);
}
for(i=0;i & lt; MAX_TIMERS;i++)
if(timers[i] == NULL)
{
timers[i] = timer;
break;
}
timers_cnt++;
timer- & gt; t = 0;
}
void unregister_timer(timer_struct_t *timer)
{
u8 i;
if(timer == 0)
{
while(1);
}
for(i=0;i & lt; MAX_TIMERS;i++)
if(timers[i] == timer)
{
timers[i] = NULL;
timers_cnt--;
break;
}
}
void start_timer(timer_struct_t *volatile timer)
{
timer- & gt; enabled = true;
}
void stop_timer(timer_struct_t *volatile timer)
{
timer- & gt; enabled = false;
timer- & gt; t = 0;
}
// funkcja wywolywana w przerwaniu timera sprzetowego co 1 ms
void timers_control(void)
{
u8 i;
for(i=0;i & lt; MAX_TIMERS;i++)
{
if(timers[i] != NULL)
{
if(timers[i]- & gt; enabled == true)
{
timers[i]- & gt; t++;
if(timers[i]- & gt; t == timers[i]- & gt; period)
{
if(timers[i]- & gt; callback != NULL)
timers[i]- & gt; callback(); // wywolaj funkcje powrotu
// else
// print_buf((s8*) " TCB ERROR " ,100,100,0,OR,0);
if(timers[i]- & gt; mode == ONE_SHOT_MODE_TIMER)
stop_timer((volatile timer_struct_t*) & timers[i]);
else
timers[i]- & gt; t = 0;
}
}
}
}
}