Odpowiednikami są dostępne IPD04N03LA oraz IRLR8743PbF SMD https://obrazki.elektroda.pl/4839977600_1637604885_thumb.jpg https://obrazki.elektroda.pl/1529347000_1637605052_thumb.jpg
PD - 96123
IRLR8743PbF
IRLU8743PbF
Applications
l High Frequency Synchronous Buck
Converters for Computer Processor Power
l High Frequency Isolated DC-DC
Converters with Synchronous Rectification
for Telecom and Industrial Use
l Lead-Free
HEXFET® Power MOSFET
VDSS
RDS(on) max
3.1m:
30V
Qg
39nC
D
Benefits
Very Low RDS(on) at 4.5V VGS
l Ultra-Low Gate Impedance
l Fully Characterized Avalanche Voltage
and Current
S
l
S
D
G
G
D-Pak
I-Pak
IRLR8743PbF IRLU8743PbF
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Parameter
Max.
Units
30
V
VDS
Drain-to-Source Voltage
VGS
Gate-to-Source Voltage
Continuous Drain Current, VGS @ 10V
± 20
160
113
IDM
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
PD @TC = 25°C
Maximum Power Dissipation
ID @ TC = 25°C
ID @ TC = 100°C
PD @TC = 100°C
Linear Derating Factor
Operating Junction and
TSTG
A
640
g
Maximum Power Dissipation g
TJ
f
f
Storage Temperature Range
W
135
68
W/°C
°C
0.90
-55 to + 175
Soldering Temperature, for 10 seconds
300 (1.6mm from case)
Thermal Resistance
Parameter
RθJC
RθJA
Junction-to-Case
Junction-to-Ambient (PCB Mount)
RθJA
Junction-to-Ambient
Typ.
gÃ
Max.
–––
1.11
–––
50
–––
Units
110
°C/W
Notes through
are on page 11
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1
08/15/07
IRLR/U8743PbF
Static @ TJ = 25°C (unless otherwise specified)
Parameter
BVDSS
∆ΒVDSS/∆TJ
RDS(on)
Min. Typ. Max. Units
30
–––
–––
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
–––
–––
20
2.4
Gate Threshold Voltage
–––
1.35
3.0
1.9
mV/°C Reference to 25°C, ID = 1mA
VGS = 10V, ID = 25A
mΩ
3.9
VGS = 4.5V, ID = 20A
2.35
V VDS = VGS, ID = 100µA
Gate Threshold Voltage Coefficient
Drain-to-Source Leakage Current
–––
–––
-6.4
–––
–––
1.0
Gate-to-Source Forward Leakage
–––
–––
–––
–––
150
100
Gate-to-Source Reverse Leakage
Forward Transconductance
–––
89
–––
–––
-100
–––
Total Gate Charge
Pre-Vth Gate-to-Source Charge
–––
–––
39
10
59
–––
Post-Vth Gate-to-Source Charge
Gate-to-Drain Charge
–––
–––
3.9
13
–––
–––
Qgodr
Qsw
Gate Charge Overdrive
Switch Charge (Qgs2 + Qgd)
–––
–––
12
17
–––
–––
Qoss
Output Charge
Gate Resistance
VGS(th)
∆VGS(th)/∆TJ
IDSS
IGSS
gfs
Qg
Qgs1
Qgs2
Qgd
V
Conditions
Drain-to-Source Breakdown Voltage
VGS = 0V, ID = 250µA
–––
3.1
e
e
mV/°C
µA
nA
S
VDS = 24V, VGS = 0V
VDS = 24V, VGS = 0V, TJ = 125°C
VGS = 20V
VGS = -20V
VDS = 15V, ID = 20A
VDS = 15V
nC
VGS = 4.5V
ID = 20A
See Fig. 16
–––
21
–––
nC
0.85
19
35
1.5
–––
–––
Ω
Turn-On Delay Time
Rise Time
–––
–––
–––
td(off)
tf
Turn-Off Delay Time
Fall Time
–––
–––
21
17
–––
–––
Ciss
Coss
Input Capacitance
Output Capacitance
–––
–––
4880
950
–––
–––
Crss
Reverse Transfer Capacitance
–––
470
–––
RG
td(on)
tr
ns
pF
VDS = 16V, VGS = 0V
VDD = 15V, VGS = 4.5V
ID = 20A
e
RG = 1.8Ω
See Fig. 14
VGS = 0V
VDS = 15V
ƒ = 1.0MHz
Avalanche Characteristics
Parameter
EAS
Single Pulse Avalanche Energy
IAR
EAR
Avalanche Current
Repetitive Avalanche Energy
Ã
Typ.
–––
Max.
250
Units
mJ
–––
–––
d
20
13.5
A
mJ
Diode Characteristics
Parameter
Min. Typ. Max. Units
IS
Continuous Source Current
(Body Diode)
–––
–––
ISM
Pulsed Source Current
(Body Diode)
–––
–––
VSD
trr
Diode Forward Voltage
Reverse Recovery Time
–––
–––
–––
18
Qrr
Reverse Recovery Charge
–––
32
ton
Forward Turn-On Time
2
Ã
160
f
Conditions
MOSFET symbol
A
showing the
integral reverse
1.0
27
V
ns
48
nC
p-n junction diode.
TJ = 25°C, IS = 20A, VGS = 0V
TJ = 25°C, IF = 20A, VDD = 15V
di/dt = 300A/µs
640
e
e
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
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IRLR/U8743PbF
1000
1000
100
BOTTOM
10
1
2.5V
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
VGS
10V
4.5V
3.7V
3.5V
3.3V
3.0V
2.7V
2.5V
100
BOTTOM
10
2.5V
≤60µs PULSE WIDTH
≤60µs PULSE WIDTH
Tj = 175°C
Tj = 25°C
0.1
0.1
1
1
10
0.1
100
1
10
100
V DS, Drain-to-Source Voltage (V)
V DS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
2.0
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID, Drain-to-Source Current (A)
VGS
10V
4.5V
3.7V
3.5V
3.3V
3.0V
2.7V
2.5V
100
T J = 175°C
10
T J = 25°C
1
VDS = 15V
≤60µs PULSE WIDTH
0.1
ID = 25A
VGS = 10V
1.5
1.0
0.5
0
2
4
6
VGS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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8
-60 -40 -20 0 20 40 60 80 100120140160180
T J , Junction Temperature (°C)
Fig 4. Normalized On-Resistance
vs. Temperature
3
IRLR/U8743PbF
5.0
100000
VGS = 0V,
f = 1 MHZ
C iss = C gs + C gd, C ds SHORTED
C rss = C gd
VGS, Gate-to-Source Voltage (V)
ID= 20A
C, Capacitance (pF)
C oss = C ds + C gd
10000
Ciss
Coss
1000
Crss
4.0
3.0
2.0
1.0
0.0
100
1
10
0
100
10000
ID, Drain-to-Source Current (A)
1000
ISD, Reverse Drain Current (A)
10 15 20 25 30 35 40 45 50
Fig 6. Typical Gate Charge vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance vs.
Drain-to-Source Voltage
T J = 175°C
100
5
QG, Total Gate Charge (nC)
VDS, Drain-to-Source Voltage (V)
T J = 25°C
10
1
OPERATION IN THIS AREA
LIMITED BY R DS(on)
1000
100µsec
1msec
100
10msec
10
1
Tc = 25°C
Tj = 175°C
Single Pulse
VGS = 0V
0.1
0.1
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VSD, Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
VDS= 24V
VDS= 15V
4.0
0
1
10
100
VDS, Drain-to-Source Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRLR/U8743PbF
180
2.5
VGS(th) , Gate Threshold Voltage (V)
Limited By Package
160
ID, Drain Current (A)
140
120
100
80
60
40
20
2.0
ID = 100µA
1.5
1.0
0.5
0
25
50
75
100
125
150
-75 -50 -25 0
175
25 50 75 100 125 150 175 200
T J , Temperature ( °C )
T C , Case Temperature (°C)
Fig 9. Maximum Drain Current vs.
Case Temperature
Fig 10. Threshold Voltage vs. Temperature
Thermal Response ( Z thJC ) °C/W
10
1
D = 0.50
0.20
0.10
0.1
0.05
τJ
0.02
0.01
0.01
R1
R1
τJ
τ1
R2
R2
R3
R3
τC
τ1
τ2
τ2
τ3
Ci= τi/Ri
Ci i/Ri
1E-005
0.0001
τ3
τ4
τ4
τi (sec)
0.02879
0.000017
τ
0.25773
0.000143
0.48255
0.001411
0.34135 0.010617
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
SINGLE PULSE
( THERMAL RESPONSE )
0.001
1E-006
Ri (°C/W)
R4
R4
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRLR/U8743PbF
D.U.T
RG
20V
VGS
+
V
- DD
IAS
A
0.01Ω
tp
ID
2.7A
3.7A
BOTTOM 20A
TOP
1000
DRIVER
L
VDS
EAS , Single Pulse Avalanche Energy (mJ)
1200
15V
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS
tp
800
600
400
200
0
25
50
75
100
125
150
175
Starting T J , Junction Temperature (°C)
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
I AS
Fig 12b. Unclamped Inductive Waveforms
V DS
V GS
RG
Current Regulator
Same Type as D.U.T.
D.U.T.
+
-V DD
VGS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
50KΩ
12V
RD
.2µF
Fig 14a. Switching Time Test Circuit
.3µF
D.U.T.
+
V
- DS
VDS
90%
VGS
3mA
IG
ID
Current Sampling Resistors
10%
VGS
td(on)
Fig 13. Gate Charge Test Circuit
6
tr
t d(off)
tf
Fig 14b. Switching Time Waveforms
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IRLR/U8743PbF
D.U.T
Driver Gate Drive
P.W.
+
+
-
-
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
+
RG
•
•
•
•
dv/dt controlled by RG
Driver same type as D.U.T.
I SD controlled by Duty Factor " D "
D.U.T. - Device Under Test
V DD
P.W.
Period
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
D=
Period
+
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
-
Body Diode
VDD
Forward Drop
Inductor Curent
Ripple ≤ 5%
ISD
* VGS = 5V for Logic Level Devices
Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
Id
Vds
Vgs
Vgs(th)
Qgodr
Qgd
Qgs2 Qgs1
Fig 16. Gate Charge Waveform
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IRLR/U8743PbF
Power MOSFET Selection for Non-Isolated DC/DC Converters
Control FET
Synchronous FET
Special attention has been given to the power losses
in the switching elements of the circuit - Q1 and Q2.
Power losses in the high side switch Q1, also called
the Control FET, are impacted by the Rds(on) of the
MOSFET, but these conduction losses are only about
one half of the total losses.
The power loss equation for Q2 is approximated
by;
*
Ploss = Pconduction + P + Poutput
drive
(
2
Ploss = Irms × Rds(on)
)
Power losses in the control switch Q1 are given
by;
+ ( g × Vg × f )
Q
Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput
⎛Q
⎞
+ ⎜ oss × Vin × f + (Qrr × Vin × f )
⎝ 2
⎠
This can be expanded and approximated by;
*dissipated primarily in Q1.
Ploss = (Irms 2 × Rds(on ) )
⎛
Qgd
+⎜I ×
× Vin ×
ig
⎝
⎞ ⎛
Qgs 2
⎞
f⎟ + ⎜ I ×
× Vin × f ⎟
ig
⎠ ⎝
⎠
+ (Qg × Vg × f )
+
⎛ Qoss
× Vin × f ⎞
⎝ 2
⎠
This simplified loss equation includes the terms Qgs2
and Qoss which are new to Power MOSFET data sheets.
Qgs2 is a sub element of traditional gate-source
charge that is included in all MOSFET data sheets.
The importance of splitting this gate-source charge
into two sub elements, Qgs1 and Qgs2, can be seen from
Fig 16.
Qgs2 indicates the charge that must be supplied by
the gate driver between the time that the threshold
voltage has been reached and the time the drain current rises to Idmax at which time the drain voltage begins to change. Minimizing Q gs2 is a critical factor in
reducing switching losses in Q1.
Qoss is the charge that must be supplied to the output capacitance of the MOSFET during every switching cycle. Figure A shows how Qoss is formed by the
parallel combination of the voltage dependant (nonlinear) capacitances Cds and Cdg when multiplied by
the power supply input buss voltage.
For the synchronous MOSFET Q2, Rds(on) is an important characteristic; however, once again the importance of gate charge must not be overlooked since
it impacts three critical areas. Under light load the
MOSFET must still be turned on and off by the control IC so the gate drive losses become much more
significant. Secondly, the output charge Qoss and reverse recovery charge Qrr both generate losses that
are transfered to Q1 and increase the dissipation in
that device. Thirdly, gate charge will impact the
MOSFETs’ susceptibility to Cdv/dt turn on.
The drain of Q2 is connected to the switching node
of the converter and therefore sees transitions between ground and Vin. As Q1 turns on and off there is
a rate of change of drain voltage dV/dt which is capacitively coupled to the gate of Q2 and can induce
a voltage spike on the gate that is sufficient to turn
the MOSFET on, resulting in shoot-through current .
The ratio of Qgd/Qgs1 must be minimized to reduce the
potential for Cdv/dt turn on.
Figure A: Qoss Characteristic
8
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IRLR/U8743PbF
D-Pak (TO-252AA) Package Outline
Dimensions are shown in millimeters (inches)
D-Pak (TO-252AA) Part Marking Information
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9
IRLR/U8743PbF
I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)
I-Pak (TO-251AA) Part Marking Information
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Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
10
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IRLR/U8743PbF
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR
TRR
16.3 ( .641 )
15.7 ( .619 )
12.1 ( .476 )
11.9 ( .469 )
FEED DIRECTION
TRL
16.3 ( .641 )
15.7 ( .619 )
8.1 ( .318 )
7.9 ( .312 )
FEED DIRECTION
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
13 INCH
16 mm
NOTES :
1. OUTLINE CONFORMS TO EIA-481.
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
Notes:
Repetitive rating; pulse width limited by
max. junction temperature.
Starting TJ = 25°C, L = 1.252mH, RG = 25Ω,
IAS = 20A.
Pulse width ≤ 400µs; duty cycle ≤ 2%.
Calculated continuous current based on maximum allowable
junction temperature. Package limitation current is 50A.
When mounted on 1 " square PCB (FR-4 or G-10 Material).
For recommended footprint and soldering techniques refer to
application note #AN-994.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.08/2007
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11