ssr_test.zip

STM32F072CBTx hard fault przy czytaniu rejestrów flash

Nawet przy czytaniu rejestrów flash, np. READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY) wyrzuca hard_fault. Przecież ten kod generuje Cube, Clocki zmieniałem wewnętrzne HSI, zewnętrzne HSE. Taki sam objaw, Dodano po 1 19 : Udostępniam w załączniku pusty projekt z tym problemem. Cały kod wygenerowany tylko przez CubeIde. Pomóżcie :).

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ssr_test.zip > stm32f0xx_hal_flash_ex.h

/**
******************************************************************************
* @file stm32f0xx_hal_flash_ex.h
* @author MCD Application Team
* @brief Header file of Flash HAL Extended module.
******************************************************************************
* @attention
*
* & lt; h2 & gt; & lt; center & gt; & copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved. & lt; /center & gt; & lt; /h2 & gt;
*
* This software component is licensed by ST under BSD 3-Clause license,
* the " License " ; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/

/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F0xx_HAL_FLASH_EX_H
#define __STM32F0xx_HAL_FLASH_EX_H

#ifdef __cplusplus
extern " C " {
#endif

/* Includes ------------------------------------------------------------------*/
#include " stm32f0xx_hal_def.h "

/** @addtogroup STM32F0xx_HAL_Driver
* @{
*/

/** @addtogroup FLASHEx
* @{
*/

/** @addtogroup FLASHEx_Private_Macros
* @{
*/
#define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || \
((VALUE) == FLASH_TYPEERASE_MASSERASE))

#define IS_OPTIONBYTE(VALUE) ((VALUE) & lt; = (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_DATA))

#define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || \
((VALUE) == OB_WRPSTATE_ENABLE))

#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == OB_DATA_ADDRESS_DATA0) || ((ADDRESS) == OB_DATA_ADDRESS_DATA1))

#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\
((LEVEL) == OB_RDP_LEVEL_1))/*||\
((LEVEL) == OB_RDP_LEVEL_2))*/

#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))

#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))

#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))

#define IS_OB_BOOT1(BOOT1) (((BOOT1) == OB_BOOT1_RESET) || ((BOOT1) == OB_BOOT1_SET))

#define IS_OB_VDDA_ANALOG(ANALOG) (((ANALOG) == OB_VDDA_ANALOG_ON) || ((ANALOG) == OB_VDDA_ANALOG_OFF))

#define IS_OB_SRAM_PARITY(PARITY) (((PARITY) == OB_SRAM_PARITY_SET) || ((PARITY) == OB_SRAM_PARITY_RESET))

#if defined(FLASH_OBR_BOOT_SEL)
#define IS_OB_BOOT_SEL(BOOT_SEL) (((BOOT_SEL) == OB_BOOT_SEL_RESET) || ((BOOT_SEL) == OB_BOOT_SEL_SET))
#define IS_OB_BOOT0(BOOT0) (((BOOT0) == OB_BOOT0_RESET) || ((BOOT0) == OB_BOOT0_SET))
#endif /* FLASH_OBR_BOOT_SEL */


#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000U))

#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 & lt; = FLASH_BANK1_END)

#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) & gt; = FLASH_BASE) & & ((ADDRESS) & lt; = FLASH_BANK1_END))

/**
* @}
*/

/* Exported types ------------------------------------------------------------*/
/** @defgroup FLASHEx_Exported_Types FLASHEx Exported Types
* @{
*/
/**
* @brief FLASH Erase structure definition
*/
typedef struct
{
uint32_t TypeErase; /*! & lt; TypeErase: Mass erase or page erase.
This parameter can be a value of @ref FLASHEx_Type_Erase */

uint32_t PageAddress; /*! & lt; PageAdress: Initial FLASH page address to erase when mass erase is disabled
This parameter must be a number between Min_Data = FLASH_BASE and Max_Data = FLASH_BANK1_END */

uint32_t NbPages; /*! & lt; NbPages: Number of pagess to be erased.
This parameter must be a value between Min_Data = 1 and Max_Data = (max number of pages - value of initial page)*/

} FLASH_EraseInitTypeDef;

/**
* @brief FLASH Options bytes program structure definition
*/
typedef struct
{
uint32_t OptionType; /*! & lt; OptionType: Option byte to be configured.
This parameter can be a value of @ref FLASHEx_OB_Type */

uint32_t WRPState; /*! & lt; WRPState: Write protection activation or deactivation.
This parameter can be a value of @ref FLASHEx_OB_WRP_State */

uint32_t WRPPage; /*! & lt; WRPPage: specifies the page(s) to be write protected
This parameter can be a value of @ref FLASHEx_OB_Write_Protection */

uint8_t RDPLevel; /*! & lt; RDPLevel: Set the read protection level..
This parameter can be a value of @ref FLASHEx_OB_Read_Protection */

uint8_t USERConfig; /*! & lt; USERConfig: Program the FLASH User Option Byte:
IWDG / STOP / STDBY / BOOT1 / VDDA_ANALOG / SRAM_PARITY
This parameter can be a combination of @ref FLASHEx_OB_IWatchdog, @ref FLASHEx_OB_nRST_STOP,
@ref FLASHEx_OB_nRST_STDBY, @ref FLASHEx_OB_BOOT1, @ref FLASHEx_OB_VDDA_Analog_Monitoring and
@ref FLASHEx_OB_RAM_Parity_Check_Enable */

uint32_t DATAAddress; /*! & lt; DATAAddress: Address of the option byte DATA to be programmed
This parameter can be a value of @ref FLASHEx_OB_Data_Address */

uint8_t DATAData; /*! & lt; DATAData: Data to be stored in the option byte DATA
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
} FLASH_OBProgramInitTypeDef;
/**
* @}
*/

/* Exported constants --------------------------------------------------------*/
/** @defgroup FLASHEx_Exported_Constants FLASHEx Exported Constants
* @{
*/

/** @defgroup FLASHEx_Page_Size FLASHEx Page Size
* @{
*/
#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) \
|| defined(STM32F051x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F058xx) || defined(STM32F070x6)
#define FLASH_PAGE_SIZE 0x400U
#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F051x8 || STM32F042x6 || STM32F048xx || STM32F058xx || STM32F070x6 */

#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) \
|| defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
#define FLASH_PAGE_SIZE 0x800U
#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx || STM32F030xC */
/**
* @}
*/

/** @defgroup FLASHEx_Type_Erase FLASH Type Erase
* @{
*/
#define FLASH_TYPEERASE_PAGES (0x00U) /*! & lt; Pages erase only*/
#define FLASH_TYPEERASE_MASSERASE (0x01U) /*! & lt; Flash mass erase activation*/

/**
* @}
*/

/** @defgroup FLASHEx_OptionByte_Constants Option Byte Constants
* @{
*/

/** @defgroup FLASHEx_OB_Type Option Bytes Type
* @{
*/
#define OPTIONBYTE_WRP (0x01U) /*! & lt; WRP option byte configuration*/
#define OPTIONBYTE_RDP (0x02U) /*! & lt; RDP option byte configuration*/
#define OPTIONBYTE_USER (0x04U) /*! & lt; USER option byte configuration*/
#define OPTIONBYTE_DATA (0x08U) /*! & lt; DATA option byte configuration*/

/**
* @}
*/

/** @defgroup FLASHEx_OB_WRP_State Option Byte WRP State
* @{
*/
#define OB_WRPSTATE_DISABLE (0x00U) /*! & lt; Disable the write protection of the desired pages*/
#define OB_WRPSTATE_ENABLE (0x01U) /*! & lt; Enable the write protection of the desired pagess*/

/**
* @}
*/

/** @defgroup FLASHEx_OB_Write_Protection FLASHEx OB Write Protection
* @{
*/
#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) \
|| defined(STM32F051x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F058xx) || defined(STM32F070x6)
#define OB_WRP_PAGES0TO3 (0x00000001U) /* Write protection of page 0 to 3 */
#define OB_WRP_PAGES4TO7 (0x00000002U) /* Write protection of page 4 to 7 */
#define OB_WRP_PAGES8TO11 (0x00000004U) /* Write protection of page 8 to 11 */
#define OB_WRP_PAGES12TO15 (0x00000008U) /* Write protection of page 12 to 15 */
#define OB_WRP_PAGES16TO19 (0x00000010U) /* Write protection of page 16 to 19 */
#define OB_WRP_PAGES20TO23 (0x00000020U) /* Write protection of page 20 to 23 */
#define OB_WRP_PAGES24TO27 (0x00000040U) /* Write protection of page 24 to 27 */
#define OB_WRP_PAGES28TO31 (0x00000080U) /* Write protection of page 28 to 31 */
#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx)
#define OB_WRP_PAGES32TO35 (0x00000100U) /* Write protection of page 32 to 35 */
#define OB_WRP_PAGES36TO39 (0x00000200U) /* Write protection of page 36 to 39 */
#define OB_WRP_PAGES40TO43 (0x00000400U) /* Write protection of page 40 to 43 */
#define OB_WRP_PAGES44TO47 (0x00000800U) /* Write protection of page 44 to 47 */
#define OB_WRP_PAGES48TO51 (0x00001000U) /* Write protection of page 48 to 51 */
#define OB_WRP_PAGES52TO57 (0x00002000U) /* Write protection of page 52 to 57 */
#define OB_WRP_PAGES56TO59 (0x00004000U) /* Write protection of page 56 to 59 */
#define OB_WRP_PAGES60TO63 (0x00008000U) /* Write protection of page 60 to 63 */
#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */

#if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) \
|| defined(STM32F051x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F058xx) || defined(STM32F070x6)
#define OB_WRP_PAGES0TO31MASK (0x000000FFU)
#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F051x8 || STM32F042x6 || STM32F048xx || STM32F038xx || STM32F058xx || STM32F070x6 */

#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx)
#define OB_WRP_PAGES32TO63MASK (0x0000FF00U)
#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */

#if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F038xx)|| defined(STM32F070x6)
#define OB_WRP_ALLPAGES (0x000000FFU) /*! & lt; Write protection of all pages */
#endif /* STM32F030x6 || STM32F031x6 || STM32F042x6 || STM32F048xx || STM32F038xx || STM32F070x6 */

#if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx)
#define OB_WRP_ALLPAGES (0x0000FFFFU) /*! & lt; Write protection of all pages */
#endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */
#endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F051x8 || STM32F042x6 || STM32F048xx || STM32F038xx || STM32F058xx || STM32F070x6 */

#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) \
|| defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
#define OB_WRP_PAGES0TO1 (0x00000001U) /* Write protection of page 0 to 1 */
#define OB_WRP_PAGES2TO3 (0x00000002U) /* Write protection of page 2 to 3 */
#define OB_WRP_PAGES4TO5 (0x00000004U) /* Write protection of page 4 to 5 */
#define OB_WRP_PAGES6TO7 (0x00000008U) /* Write protection of page 6 to 7 */
#define OB_WRP_PAGES8TO9 (0x00000010U) /* Write protection of page 8 to 9 */
#define OB_WRP_PAGES10TO11 (0x00000020U) /* Write protection of page 10 to 11 */
#define OB_WRP_PAGES12TO13 (0x00000040U) /* Write protection of page 12 to 13 */
#define OB_WRP_PAGES14TO15 (0x00000080U) /* Write protection of page 14 to 15 */
#define OB_WRP_PAGES16TO17 (0x00000100U) /* Write protection of page 16 to 17 */
#define OB_WRP_PAGES18TO19 (0x00000200U) /* Write protection of page 18 to 19 */
#define OB_WRP_PAGES20TO21 (0x00000400U) /* Write protection of page 20 to 21 */
#define OB_WRP_PAGES22TO23 (0x00000800U) /* Write protection of page 22 to 23 */
#define OB_WRP_PAGES24TO25 (0x00001000U) /* Write protection of page 24 to 25 */
#define OB_WRP_PAGES26TO27 (0x00002000U) /* Write protection of page 26 to 27 */
#define OB_WRP_PAGES28TO29 (0x00004000U) /* Write protection of page 28 to 29 */
#define OB_WRP_PAGES30TO31 (0x00008000U) /* Write protection of page 30 to 31 */
#define OB_WRP_PAGES32TO33 (0x00010000U) /* Write protection of page 32 to 33 */
#define OB_WRP_PAGES34TO35 (0x00020000U) /* Write protection of page 34 to 35 */
#define OB_WRP_PAGES36TO37 (0x00040000U) /* Write protection of page 36 to 37 */
#define OB_WRP_PAGES38TO39 (0x00080000U) /* Write protection of page 38 to 39 */
#define OB_WRP_PAGES40TO41 (0x00100000U) /* Write protection of page 40 to 41 */
#define OB_WRP_PAGES42TO43 (0x00200000U) /* Write protection of page 42 to 43 */
#define OB_WRP_PAGES44TO45 (0x00400000U) /* Write protection of page 44 to 45 */
#define OB_WRP_PAGES46TO47 (0x00800000U) /* Write protection of page 46 to 47 */
#define OB_WRP_PAGES48TO49 (0x01000000U) /* Write protection of page 48 to 49 */
#define OB_WRP_PAGES50TO51 (0x02000000U) /* Write protection of page 50 to 51 */
#define OB_WRP_PAGES52TO53 (0x04000000U) /* Write protection of page 52 to 53 */
#define OB_WRP_PAGES54TO55 (0x08000000U) /* Write protection of page 54 to 55 */
#define OB_WRP_PAGES56TO57 (0x10000000U) /* Write protection of page 56 to 57 */
#define OB_WRP_PAGES58TO59 (0x20000000U) /* Write protection of page 58 to 59 */
#define OB_WRP_PAGES60TO61 (0x40000000U) /* Write protection of page 60 to 61 */
#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)
#define OB_WRP_PAGES62TO63 (0x80000000U) /* Write protection of page 62 to 63 */
#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB */
#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
#define OB_WRP_PAGES62TO127 (0x80000000U) /* Write protection of page 62 to 127 */
#endif /* STM32F091xC || STM32F098xx || STM32F030xC */

#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) \
|| defined(STM32F091xC) || defined(STM32F098xx)|| defined(STM32F030xC)
#define OB_WRP_PAGES0TO15MASK (0x000000FFU)
#define OB_WRP_PAGES16TO31MASK (0x0000FF00U)
#define OB_WRP_PAGES32TO47MASK (0x00FF0000U)
#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx || STM32F070xB || STM32F030xC */

#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)
#define OB_WRP_PAGES48TO63MASK (0xFF000000U)
#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB */
#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
#define OB_WRP_PAGES48TO127MASK (0xFF000000U)
#endif /* STM32F091xC || STM32F098xx || STM32F030xC */

#define OB_WRP_ALLPAGES (0xFFFFFFFFU) /*! & lt; Write protection of all pages */
#endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx || STM32F030xC || STM32F070xB */

/**
* @}
*/

/** @defgroup FLASHEx_OB_Read_Protection Option Byte Read Protection
* @{
*/
#define OB_RDP_LEVEL_0 ((uint8_t)0xAAU)
#define OB_RDP_LEVEL_1 ((uint8_t)0xBBU)
#define OB_RDP_LEVEL_2 ((uint8_t)0xCCU) /*! & lt; Warning: When enabling read protection level 2
it's no more possible to go back to level 1 or 0 */
/**
* @}
*/

/** @defgroup FLASHEx_OB_IWatchdog Option Byte IWatchdog
* @{
*/
#define OB_IWDG_SW ((uint8_t)0x01U) /*! & lt; Software IWDG selected */
#define OB_IWDG_HW ((uint8_t)0x00U) /*! & lt; Hardware IWDG selected */
/**
* @}
*/

/** @defgroup FLASHEx_OB_nRST_STOP Option Byte nRST STOP
* @{
*/
#define OB_STOP_NO_RST ((uint8_t)0x02U) /*! & lt; No reset generated when entering in STOP */
#define OB_STOP_RST ((uint8_t)0x00U) /*! & lt; Reset generated when entering in STOP */
/**
* @}
*/

/** @defgroup FLASHEx_OB_nRST_STDBY Option Byte nRST STDBY
* @{
*/
#define OB_STDBY_NO_RST ((uint8_t)0x04U) /*! & lt; No reset generated when entering in STANDBY */
#define OB_STDBY_RST ((uint8_t)0x00U) /*! & lt; Reset generated when entering in STANDBY */
/**
* @}
*/

/** @defgroup FLASHEx_OB_BOOT1 Option Byte BOOT1
* @{
*/
#define OB_BOOT1_RESET ((uint8_t)0x00U) /*! & lt; BOOT1 Reset */
#define OB_BOOT1_SET ((uint8_t)0x10U) /*! & lt; BOOT1 Set */
/**
* @}
*/

/** @defgroup FLASHEx_OB_VDDA_Analog_Monitoring Option Byte VDDA Analog Monitoring
* @{
*/
#define OB_VDDA_ANALOG_ON ((uint8_t)0x20U) /*! & lt; Analog monitoring on VDDA Power source ON */
#define OB_VDDA_ANALOG_OFF ((uint8_t)0x00U) /*! & lt; Analog monitoring on VDDA Power source OFF */
/**
* @}
*/

/** @defgroup FLASHEx_OB_RAM_Parity_Check_Enable Option Byte SRAM Parity Check Enable
* @{
*/
#define OB_SRAM_PARITY_SET ((uint8_t)0x00U) /*! & lt; SRAM parity check enable set */
#define OB_SRAM_PARITY_RESET ((uint8_t)0x40U) /*! & lt; SRAM parity check enable reset */
/**
* @}
*/

#if defined(FLASH_OBR_BOOT_SEL)
/** @defgroup FLASHEx_OB_BOOT_SEL FLASHEx Option Byte BOOT SEL
* @{
*/
#define OB_BOOT_SEL_RESET ((uint8_t)0x00U) /*! & lt; BOOT_SEL Reset */
#define OB_BOOT_SEL_SET ((uint8_t)0x80U) /*! & lt; BOOT_SEL Set */
/**
* @}
*/

/** @defgroup FLASHEx_OB_BOOT0 FLASHEx Option Byte BOOT0
* @{
*/
#define OB_BOOT0_RESET ((uint8_t)0x00U) /*! & lt; BOOT0 Reset */
#define OB_BOOT0_SET ((uint8_t)0x08U) /*! & lt; BOOT0 Set */
/**
* @}
*/
#endif /* FLASH_OBR_BOOT_SEL */


/** @defgroup FLASHEx_OB_Data_Address Option Byte Data Address
* @{
*/
#define OB_DATA_ADDRESS_DATA0 (0x1FFFF804U)
#define OB_DATA_ADDRESS_DATA1 (0x1FFFF806U)
/**
* @}
*/

/**
* @}
*/

/**
* @}
*/

/* Exported functions --------------------------------------------------------*/
/** @addtogroup FLASHEx_Exported_Functions
* @{
*/

/** @addtogroup FLASHEx_Exported_Functions_Group1
* @{
*/
/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError);
HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);

/**
* @}
*/

/** @addtogroup FLASHEx_Exported_Functions_Group2
* @{
*/
/* Peripheral Control functions ***********************************************/
HAL_StatusTypeDef HAL_FLASHEx_OBErase(void);
HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
uint32_t HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress);

/**
* @}
*/

/**
* @}
*/

/**
* @}
*/

/**
* @}
*/

#ifdef __cplusplus
}
#endif

#endif /* __STM32F0xx_HAL_FLASH_EX_H */

/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

ssr_test.zip > stm32f0xx_hal_i2c_ex.h

/**
******************************************************************************
* @file stm32f0xx_hal_i2c_ex.h
* @author MCD Application Team
* @brief Header file of I2C HAL Extended module.
******************************************************************************
* @attention
*
* & lt; h2 & gt; & lt; center & gt; & copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved. & lt; /center & gt; & lt; /h2 & gt;
*
* This software component is licensed by ST under BSD 3-Clause license,
* the " License " ; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/

/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F0xx_HAL_I2C_EX_H
#define STM32F0xx_HAL_I2C_EX_H

#ifdef __cplusplus
extern " C " {
#endif

/* Includes ------------------------------------------------------------------*/
#include " stm32f0xx_hal_def.h "

/** @addtogroup STM32F0xx_HAL_Driver
* @{
*/

/** @addtogroup I2CEx
* @{
*/

/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/

/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants
* @{
*/

/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter
* @{
*/
#define I2C_ANALOGFILTER_ENABLE 0x00000000U
#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
/**
* @}
*/

/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus
* @{
*/
#define I2C_FMP_NOT_SUPPORTED 0xAAAA0000U /*! & lt; Fast Mode Plus not supported */
#if defined(SYSCFG_CFGR1_I2C_FMP_PA9)
#define I2C_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_FMP_PA9 /*! & lt; Enable Fast Mode Plus on PA9 */
#define I2C_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_FMP_PA10 /*! & lt; Enable Fast Mode Plus on PA10 */
#else
#define I2C_FASTMODEPLUS_PA9 (uint32_t)(0x00000001U | I2C_FMP_NOT_SUPPORTED) /*! & lt; Fast Mode Plus PA9 not supported */
#define I2C_FASTMODEPLUS_PA10 (uint32_t)(0x00000002U | I2C_FMP_NOT_SUPPORTED) /*! & lt; Fast Mode Plus PA10 not supported */
#endif
#define I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_FMP_PB6 /*! & lt; Enable Fast Mode Plus on PB6 */
#define I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_FMP_PB7 /*! & lt; Enable Fast Mode Plus on PB7 */
#define I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_FMP_PB8 /*! & lt; Enable Fast Mode Plus on PB8 */
#define I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_FMP_PB9 /*! & lt; Enable Fast Mode Plus on PB9 */
#if defined(SYSCFG_CFGR1_I2C_FMP_I2C1)
#define I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C_FMP_I2C1 /*! & lt; Enable Fast Mode Plus on I2C1 pins */
#else
#define I2C_FASTMODEPLUS_I2C1 (uint32_t)(0x00000100U | I2C_FMP_NOT_SUPPORTED) /*! & lt; Fast Mode Plus I2C1 not supported */
#endif
#if defined(SYSCFG_CFGR1_I2C_FMP_I2C2)
#define I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C_FMP_I2C2 /*! & lt; Enable Fast Mode Plus on I2C2 pins */
#else
#define I2C_FASTMODEPLUS_I2C2 (uint32_t)(0x00000200U | I2C_FMP_NOT_SUPPORTED) /*! & lt; Fast Mode Plus I2C2 not supported */
#endif
/**
* @}
*/

/**
* @}
*/

/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/

/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions
* @{
*/

/** @addtogroup I2CEx_Exported_Functions_Group1 Extended features functions
* @brief Extended features functions
* @{
*/

/* Peripheral Control functions ************************************************/
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c,
uint32_t AnalogFilter);
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c,
uint32_t DigitalFilter);
#if defined(I2C_CR1_WUPEN)
HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c);
#endif
void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);

/* Private constants ---------------------------------------------------------*/
/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants
* @{
*/

/**
* @}
*/

/* Private macros ------------------------------------------------------------*/
/** @defgroup I2CEx_Private_Macro I2C Extended Private Macros
* @{
*/
#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
((FILTER) == I2C_ANALOGFILTER_DISABLE))

#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) & lt; = 0x0000000FU)

#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FMP_NOT_SUPPORTED) != I2C_FMP_NOT_SUPPORTED) & & \
((((__CONFIG__) & (I2C_FASTMODEPLUS_PA9)) == I2C_FASTMODEPLUS_PA9) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_PA10)) == I2C_FASTMODEPLUS_PA10) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_PB6)) == I2C_FASTMODEPLUS_PB6) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_PB7)) == I2C_FASTMODEPLUS_PB7) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_PB8)) == I2C_FASTMODEPLUS_PB8) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_PB9)) == I2C_FASTMODEPLUS_PB9) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2)))
/**
* @}
*/

/* Private Functions ---------------------------------------------------------*/
/** @defgroup I2CEx_Private_Functions I2C Extended Private Functions
* @{
*/
/* Private functions are defined in stm32f0xx_hal_i2c_ex.c file */
/**
* @}
*/

/**
* @}
*/

/**
* @}
*/

/**
* @}
*/

/**
* @}
*/

#ifdef __cplusplus
}
#endif

#endif /* STM32F0xx_HAL_I2C_EX_H */

/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

ssr_test.zip > stm32f0xx_hal_gpio.h

/**
******************************************************************************
* @file stm32f0xx_hal_gpio.h
* @author MCD Application Team
* @brief Header file of GPIO HAL module.
******************************************************************************
* @attention
*
* & lt; h2 & gt; & lt; center & gt; & copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved. & lt; /center & gt; & lt; /h2 & gt;
*
* This software component is licensed by ST under BSD 3-Clause license,
* the " License " ; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/

/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F0xx_HAL_GPIO_H
#define __STM32F0xx_HAL_GPIO_H

#ifdef __cplusplus
extern " C " {
#endif

/* Includes ------------------------------------------------------------------*/
#include " stm32f0xx_hal_def.h "

/** @addtogroup STM32F0xx_HAL_Driver
* @{
*/

/** @addtogroup GPIO
* @{
*/

/* Exported types ------------------------------------------------------------*/

/** @defgroup GPIO_Exported_Types GPIO Exported Types
* @{
*/
/**
* @brief GPIO Init structure definition
*/
typedef struct
{
uint32_t Pin; /*! & lt; Specifies the GPIO pins to be configured.
This parameter can be any value of @ref GPIO_pins */

uint32_t Mode; /*! & lt; Specifies the operating mode for the selected pins.
This parameter can be a value of @ref GPIO_mode */

uint32_t Pull; /*! & lt; Specifies the Pull-up or Pull-Down activation for the selected pins.
This parameter can be a value of @ref GPIO_pull */

uint32_t Speed; /*! & lt; Specifies the speed for the selected pins.
This parameter can be a value of @ref GPIO_speed */

uint32_t Alternate; /*! & lt; Peripheral to be connected to the selected pins
This parameter can be a value of @ref GPIOEx_Alternate_function_selection */
}GPIO_InitTypeDef;

/**
* @brief GPIO Bit SET and Bit RESET enumeration
*/
typedef enum
{
GPIO_PIN_RESET = 0U,
GPIO_PIN_SET
}GPIO_PinState;
/**
* @}
*/

/* Exported constants --------------------------------------------------------*/
/** @defgroup GPIO_Exported_Constants GPIO Exported Constants
* @{
*/
/** @defgroup GPIO_pins GPIO pins
* @{
*/
#define GPIO_PIN_0 ((uint16_t)0x0001U) /* Pin 0 selected */
#define GPIO_PIN_1 ((uint16_t)0x0002U) /* Pin 1 selected */
#define GPIO_PIN_2 ((uint16_t)0x0004U) /* Pin 2 selected */
#define GPIO_PIN_3 ((uint16_t)0x0008U) /* Pin 3 selected */
#define GPIO_PIN_4 ((uint16_t)0x0010U) /* Pin 4 selected */
#define GPIO_PIN_5 ((uint16_t)0x0020U) /* Pin 5 selected */
#define GPIO_PIN_6 ((uint16_t)0x0040U) /* Pin 6 selected */
#define GPIO_PIN_7 ((uint16_t)0x0080U) /* Pin 7 selected */
#define GPIO_PIN_8 ((uint16_t)0x0100U) /* Pin 8 selected */
#define GPIO_PIN_9 ((uint16_t)0x0200U) /* Pin 9 selected */
#define GPIO_PIN_10 ((uint16_t)0x0400U) /* Pin 10 selected */
#define GPIO_PIN_11 ((uint16_t)0x0800U) /* Pin 11 selected */
#define GPIO_PIN_12 ((uint16_t)0x1000U) /* Pin 12 selected */
#define GPIO_PIN_13 ((uint16_t)0x2000U) /* Pin 13 selected */
#define GPIO_PIN_14 ((uint16_t)0x4000U) /* Pin 14 selected */
#define GPIO_PIN_15 ((uint16_t)0x8000U) /* Pin 15 selected */
#define GPIO_PIN_All ((uint16_t)0xFFFFU) /* All pins selected */

#define GPIO_PIN_MASK (0x0000FFFFU) /* PIN mask for assert test */
/**
* @}
*/

/** @defgroup GPIO_mode GPIO mode
* @brief GPIO Configuration Mode
* Elements values convention: 0xX0yz00YZ
* - X : GPIO mode or EXTI Mode
* - y : External IT or Event trigger detection
* - z : IO configuration on External IT or Event
* - Y : Output type (Push Pull or Open Drain)
* - Z : IO Direction mode (Input, Output, Alternate or Analog)
* @{
*/
#define GPIO_MODE_INPUT (0x00000000U) /*! & lt; Input Floating Mode */
#define GPIO_MODE_OUTPUT_PP (0x00000001U) /*! & lt; Output Push Pull Mode */
#define GPIO_MODE_OUTPUT_OD (0x00000011U) /*! & lt; Output Open Drain Mode */
#define GPIO_MODE_AF_PP (0x00000002U) /*! & lt; Alternate Function Push Pull Mode */
#define GPIO_MODE_AF_OD (0x00000012U) /*! & lt; Alternate Function Open Drain Mode */
#define GPIO_MODE_ANALOG (0x00000003U) /*! & lt; Analog Mode */
#define GPIO_MODE_IT_RISING (0x10110000U) /*! & lt; External Interrupt Mode with Rising edge trigger detection */
#define GPIO_MODE_IT_FALLING (0x10210000U) /*! & lt; External Interrupt Mode with Falling edge trigger detection */
#define GPIO_MODE_IT_RISING_FALLING (0x10310000U) /*! & lt; External Interrupt Mode with Rising/Falling edge trigger detection */
#define GPIO_MODE_EVT_RISING (0x10120000U) /*! & lt; External Event Mode with Rising edge trigger detection */
#define GPIO_MODE_EVT_FALLING (0x10220000U) /*! & lt; External Event Mode with Falling edge trigger detection */
#define GPIO_MODE_EVT_RISING_FALLING (0x10320000U) /*! & lt; External Event Mode with Rising/Falling edge trigger detection */
/**
* @}
*/

/** @defgroup GPIO_speed GPIO speed
* @brief GPIO Output Maximum frequency
* @{
*/
#define GPIO_SPEED_FREQ_LOW (0x00000000U) /*! & lt; range up to 2 MHz, please refer to the product datasheet */
#define GPIO_SPEED_FREQ_MEDIUM (0x00000001U) /*! & lt; range 4 MHz to 10 MHz, please refer to the product datasheet */
#define GPIO_SPEED_FREQ_HIGH (0x00000003U) /*! & lt; range 10 MHz to 50 MHz, please refer to the product datasheet */
/**
* @}
*/

/** @defgroup GPIO_pull GPIO pull
* @brief GPIO Pull-Up or Pull-Down Activation
* @{
*/
#define GPIO_NOPULL (0x00000000U) /*! & lt; No Pull-up or Pull-down activation */
#define GPIO_PULLUP (0x00000001U) /*! & lt; Pull-up activation */
#define GPIO_PULLDOWN (0x00000002U) /*! & lt; Pull-down activation */
/**
* @}
*/

/**
* @}
*/

/* Exported macro ------------------------------------------------------------*/
/** @defgroup GPIO_Exported_Macros GPIO Exported Macros
* @{
*/

/**
* @brief Check whether the specified EXTI line flag is set or not.
* @param __EXTI_LINE__ specifies the EXTI line flag to check.
* This parameter can be GPIO_PIN_x where x can be(0..15)
* @retval The new state of __EXTI_LINE__ (SET or RESET).
*/
#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI- & gt; PR & (__EXTI_LINE__))

/**
* @brief Clear the EXTI's line pending flags.
* @param __EXTI_LINE__ specifies the EXTI lines flags to clear.
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
* @retval None
*/
#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI- & gt; PR = (__EXTI_LINE__))

/**
* @brief Check whether the specified EXTI line is asserted or not.
* @param __EXTI_LINE__ specifies the EXTI line to check.
* This parameter can be GPIO_PIN_x where x can be(0..15)
* @retval The new state of __EXTI_LINE__ (SET or RESET).
*/
#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI- & gt; PR & (__EXTI_LINE__))

/**
* @brief Clear the EXTI's line pending bits.
* @param __EXTI_LINE__ specifies the EXTI lines to clear.
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
* @retval None
*/
#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI- & gt; PR = (__EXTI_LINE__))

/**
* @brief Generate a Software interrupt on selected EXTI line.
* @param __EXTI_LINE__ specifies the EXTI line to check.
* This parameter can be GPIO_PIN_x where x can be(0..15)
* @retval None
*/
#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI- & gt; SWIER |= (__EXTI_LINE__))

/**
* @}
*/

/* Private macros ------------------------------------------------------------*/
/** @addtogroup GPIO_Private_Macros GPIO Private Macros
* @{
*/
#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))

#define IS_GPIO_PIN(__PIN__) (((((uint32_t)__PIN__) & GPIO_PIN_MASK) != 0x00U) & & \
((((uint32_t)__PIN__) & ~GPIO_PIN_MASK) == 0x00U))

#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\
((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\
((__MODE__) == GPIO_MODE_OUTPUT_OD) ||\
((__MODE__) == GPIO_MODE_AF_PP) ||\
((__MODE__) == GPIO_MODE_AF_OD) ||\
((__MODE__) == GPIO_MODE_IT_RISING) ||\
((__MODE__) == GPIO_MODE_IT_FALLING) ||\
((__MODE__) == GPIO_MODE_IT_RISING_FALLING) ||\
((__MODE__) == GPIO_MODE_EVT_RISING) ||\
((__MODE__) == GPIO_MODE_EVT_FALLING) ||\
((__MODE__) == GPIO_MODE_EVT_RISING_FALLING) ||\
((__MODE__) == GPIO_MODE_ANALOG))

#define IS_GPIO_SPEED(__SPEED__) (((__SPEED__) == GPIO_SPEED_FREQ_LOW) ||\
((__SPEED__) == GPIO_SPEED_FREQ_MEDIUM) ||\
((__SPEED__) == GPIO_SPEED_FREQ_HIGH))

#define IS_GPIO_PULL(__PULL__) (((__PULL__) == GPIO_NOPULL) ||\
((__PULL__) == GPIO_PULLUP) || \
((__PULL__) == GPIO_PULLDOWN))
/**
* @}
*/

/* Include GPIO HAL Extended module */
#include " stm32f0xx_hal_gpio_ex.h "

/* Exported functions --------------------------------------------------------*/
/** @addtogroup GPIO_Exported_Functions GPIO Exported Functions
* @{
*/

/** @addtogroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions
* @brief Initialization and Configuration functions
* @{
*/

/* Initialization and de-initialization functions *****************************/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init);
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);

/**
* @}
*/

/** @addtogroup GPIO_Exported_Functions_Group2 IO operation functions
* @{
*/

/* IO operation functions *****************************************************/
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);

/**
* @}
*/

/**
* @}
*/

/**
* @}
*/

/**
* @}
*/

#ifdef __cplusplus
}
#endif

#endif /* __STM32F0xx_HAL_GPIO_H */

/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

ssr_test.zip > stm32f0xx_hal_pwr_ex.h

/**
******************************************************************************
* @file stm32f0xx_hal_pwr_ex.h
* @author MCD Application Team
* @brief Header file of PWR HAL Extension module.
******************************************************************************
* @attention
*
* & lt; h2 & gt; & lt; center & gt; & copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved. & lt; /center & gt; & lt; /h2 & gt;
*
* This software component is licensed by ST under BSD 3-Clause license,
* the " License " ; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/

/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F0xx_HAL_PWR_EX_H
#define __STM32F0xx_HAL_PWR_EX_H

#ifdef __cplusplus
extern " C " {
#endif

/* Includes ------------------------------------------------------------------*/
#include " stm32f0xx_hal_def.h "

/** @addtogroup STM32F0xx_HAL_Driver
* @{
*/

/** @addtogroup PWREx
* @{
*/

/* Exported types ------------------------------------------------------------*/

/** @defgroup PWREx_Exported_Types PWREx Exported Types
* @{
*/

#if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \
defined (STM32F071xB) || defined (STM32F072xB) || \
defined (STM32F091xC)

/**
* @brief PWR PVD configuration structure definition
*/
typedef struct
{
uint32_t PVDLevel; /*! & lt; PVDLevel: Specifies the PVD detection level
This parameter can be a value of @ref PWREx_PVD_detection_level */

uint32_t Mode; /*! & lt; Mode: Specifies the operating mode for the selected pins.
This parameter can be a value of @ref PWREx_PVD_Mode */
}PWR_PVDTypeDef;

#endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */
/* defined (STM32F071xB) || defined (STM32F072xB) || */
/* defined (STM32F091xC) */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/

/** @defgroup PWREx_Exported_Constants PWREx Exported Constants
* @{
*/


/** @defgroup PWREx_WakeUp_Pins PWREx Wakeup Pins
* @{
*/
#if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
defined (STM32F091xC) || defined (STM32F098xx)
#define PWR_WAKEUP_PIN1 ((uint32_t)PWR_CSR_EWUP1)
#define PWR_WAKEUP_PIN2 ((uint32_t)PWR_CSR_EWUP2)
#define PWR_WAKEUP_PIN3 ((uint32_t)PWR_CSR_EWUP3)
#define PWR_WAKEUP_PIN4 ((uint32_t)PWR_CSR_EWUP4)
#define PWR_WAKEUP_PIN5 ((uint32_t)PWR_CSR_EWUP5)
#define PWR_WAKEUP_PIN6 ((uint32_t)PWR_CSR_EWUP6)
#define PWR_WAKEUP_PIN7 ((uint32_t)PWR_CSR_EWUP7)
#define PWR_WAKEUP_PIN8 ((uint32_t)PWR_CSR_EWUP8)

#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
((PIN) == PWR_WAKEUP_PIN2) || \
((PIN) == PWR_WAKEUP_PIN3) || \
((PIN) == PWR_WAKEUP_PIN4) || \
((PIN) == PWR_WAKEUP_PIN5) || \
((PIN) == PWR_WAKEUP_PIN6) || \
((PIN) == PWR_WAKEUP_PIN7) || \
((PIN) == PWR_WAKEUP_PIN8))

#elif defined(STM32F030xC) || defined (STM32F070xB)
#define PWR_WAKEUP_PIN1 ((uint32_t)PWR_CSR_EWUP1)
#define PWR_WAKEUP_PIN2 ((uint32_t)PWR_CSR_EWUP2)
#define PWR_WAKEUP_PIN4 ((uint32_t)PWR_CSR_EWUP4)
#define PWR_WAKEUP_PIN5 ((uint32_t)PWR_CSR_EWUP5)
#define PWR_WAKEUP_PIN6 ((uint32_t)PWR_CSR_EWUP6)
#define PWR_WAKEUP_PIN7 ((uint32_t)PWR_CSR_EWUP7)

#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
((PIN) == PWR_WAKEUP_PIN2) || \
((PIN) == PWR_WAKEUP_PIN4) || \
((PIN) == PWR_WAKEUP_PIN5) || \
((PIN) == PWR_WAKEUP_PIN6) || \
((PIN) == PWR_WAKEUP_PIN7))

#elif defined(STM32F042x6) || defined (STM32F048xx)
#define PWR_WAKEUP_PIN1 ((uint32_t)PWR_CSR_EWUP1)
#define PWR_WAKEUP_PIN2 ((uint32_t)PWR_CSR_EWUP2)
#define PWR_WAKEUP_PIN4 ((uint32_t)PWR_CSR_EWUP4)
#define PWR_WAKEUP_PIN6 ((uint32_t)PWR_CSR_EWUP6)
#define PWR_WAKEUP_PIN7 ((uint32_t)PWR_CSR_EWUP7)

#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
((PIN) == PWR_WAKEUP_PIN2) || \
((PIN) == PWR_WAKEUP_PIN4) || \
((PIN) == PWR_WAKEUP_PIN6) || \
((PIN) == PWR_WAKEUP_PIN7))

#else
#define PWR_WAKEUP_PIN1 ((uint32_t)PWR_CSR_EWUP1)
#define PWR_WAKEUP_PIN2 ((uint32_t)PWR_CSR_EWUP2)


#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
((PIN) == PWR_WAKEUP_PIN2))

#endif

/**
* @}
*/

/** @defgroup PWREx_EXTI_Line PWREx EXTI Line
* @{
*/
#if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \
defined (STM32F071xB) || defined (STM32F072xB) || \
defined (STM32F091xC)

#define PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR_MR16) /*! & lt; External interrupt line 16 Connected to the PVD EXTI Line */

#endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */
/* defined (STM32F071xB) || defined (STM32F072xB) || */
/* defined (STM32F091xC) */

#if defined (STM32F042x6) || defined (STM32F048xx) || \
defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
defined (STM32F091xC) || defined (STM32F098xx)

#define PWR_EXTI_LINE_VDDIO2 ((uint32_t)EXTI_IMR_MR31) /*! & lt; External interrupt line 31 Connected to the Vddio2 Monitor EXTI Line */

#endif /* defined (STM32F042x6) || defined (STM32F048xx) ||\
defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
defined (STM32F091xC) || defined (STM32F098xx) ||*/
/**
* @}
*/

#if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \
defined (STM32F071xB) || defined (STM32F072xB) || \
defined (STM32F091xC)
/** @defgroup PWREx_PVD_detection_level PWREx PVD detection level
* @{
*/
#define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0
#define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1
#define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2
#define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3
#define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4
#define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5
#define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6
#define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7
#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
/**
* @}
*/

/** @defgroup PWREx_PVD_Mode PWREx PVD Mode
* @{
*/
#define PWR_PVD_MODE_NORMAL (0x00000000U) /*! & lt; basic mode is used */
#define PWR_PVD_MODE_IT_RISING (0x00010001U) /*! & lt; External Interrupt Mode with Rising edge trigger detection */
#define PWR_PVD_MODE_IT_FALLING (0x00010002U) /*! & lt; External Interrupt Mode with Falling edge trigger detection */
#define PWR_PVD_MODE_IT_RISING_FALLING (0x00010003U) /*! & lt; External Interrupt Mode with Rising/Falling edge trigger detection */
#define PWR_PVD_MODE_EVENT_RISING (0x00020001U) /*! & lt; Event Mode with Rising edge trigger detection */
#define PWR_PVD_MODE_EVENT_FALLING (0x00020002U) /*! & lt; Event Mode with Falling edge trigger detection */
#define PWR_PVD_MODE_EVENT_RISING_FALLING (0x00020003U) /*! & lt; Event Mode with Rising/Falling edge trigger detection */

#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
((MODE) == PWR_PVD_MODE_NORMAL))
/**
* @}
*/
#endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */
/* defined (STM32F071xB) || defined (STM32F072xB) || */
/* defined (STM32F091xC) */

/** @defgroup PWREx_Flag PWREx Flag
* @{
*/
#if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \
defined (STM32F071xB) || defined (STM32F072xB) || \
defined (STM32F091xC)

#define PWR_FLAG_WU PWR_CSR_WUF
#define PWR_FLAG_SB PWR_CSR_SBF
#define PWR_FLAG_PVDO PWR_CSR_PVDO
#define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF
#elif defined (STM32F070x6) || defined (STM32F070xB) || defined (STM32F030xC)
#define PWR_FLAG_WU PWR_CSR_WUF
#define PWR_FLAG_SB PWR_CSR_SBF
#define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF
#else
#define PWR_FLAG_WU PWR_CSR_WUF
#define PWR_FLAG_SB PWR_CSR_SBF

#endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */
/* defined (STM32F071xB) || defined (STM32F072xB) || */
/* defined (STM32F091xC) */
/**
* @}
*/

/**
* @}
*/

/* Exported macro ------------------------------------------------------------*/
/** @defgroup PWREx_Exported_Macros PWREx Exported Macros
* @{
*/
#if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \
defined (STM32F071xB) || defined (STM32F072xB) || \
defined (STM32F091xC)
/**
* @brief Enable interrupt on PVD Exti Line 16.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_ENABLE_IT() (EXTI- & gt; IMR |= (PWR_EXTI_LINE_PVD))

/**
* @brief Disable interrupt on PVD Exti Line 16.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_DISABLE_IT() (EXTI- & gt; IMR & = ~(PWR_EXTI_LINE_PVD))

/**
* @brief Enable event on PVD Exti Line 16.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() (EXTI- & gt; EMR |= (PWR_EXTI_LINE_PVD))

/**
* @brief Disable event on PVD Exti Line 16.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() (EXTI- & gt; EMR & = ~(PWR_EXTI_LINE_PVD))

/**
* @brief Disable the PVD Extended Interrupt Rising Trigger.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI- & gt; RTSR, PWR_EXTI_LINE_PVD)

/**
* @brief Disable the PVD Extended Interrupt Falling Trigger.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI- & gt; FTSR, PWR_EXTI_LINE_PVD)

/**
* @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
* @retval None
*/
#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();


/**
* @brief PVD EXTI line configuration: set falling edge trigger.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() EXTI- & gt; FTSR |= (PWR_EXTI_LINE_PVD)

/**
* @brief PVD EXTI line configuration: set rising edge trigger.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() EXTI- & gt; RTSR |= (PWR_EXTI_LINE_PVD)

/**
* @brief Enable the PVD Extended Interrupt Rising & Falling Trigger.
* @retval None
*/
#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();

/**
* @brief Check whether the specified PVD EXTI interrupt flag is set or not.
* @retval EXTI PVD Line Status.
*/
#define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI- & gt; PR & (PWR_EXTI_LINE_PVD))

/**
* @brief Clear the PVD EXTI flag.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI- & gt; PR = (PWR_EXTI_LINE_PVD))

/**
* @brief Generate a Software interrupt on selected EXTI line.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI- & gt; SWIER |= (PWR_EXTI_LINE_PVD))

#endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */
/* defined (STM32F071xB) || defined (STM32F072xB) || */
/* defined (STM32F091xC) */


#if defined (STM32F042x6) || defined (STM32F048xx) || \
defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
defined (STM32F091xC) || defined (STM32F098xx)
/**
* @brief Enable interrupt on Vddio2 Monitor Exti Line 31.
* @retval None.
*/
#define __HAL_PWR_VDDIO2_EXTI_ENABLE_IT() (EXTI- & gt; IMR |= (PWR_EXTI_LINE_VDDIO2))

/**
* @brief Disable interrupt on Vddio2 Monitor Exti Line 31.
* @retval None.
*/
#define __HAL_PWR_VDDIO2_EXTI_DISABLE_IT() (EXTI- & gt; IMR & = ~(PWR_EXTI_LINE_VDDIO2))

/**
* @brief Vddio2 Monitor EXTI line configuration: clear falling edge and rising edge trigger.
* @retval None.
*/
#define __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE() \
do{ \
EXTI- & gt; FTSR & = ~(PWR_EXTI_LINE_VDDIO2); \
EXTI- & gt; RTSR & = ~(PWR_EXTI_LINE_VDDIO2); \
} while(0)

/**
* @brief Vddio2 Monitor EXTI line configuration: set falling edge trigger.
* @retval None.
*/
#define __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE() EXTI- & gt; FTSR |= (PWR_EXTI_LINE_VDDIO2)

/**
* @brief Check whether the specified VDDIO2 monitor EXTI interrupt flag is set or not.
* @retval EXTI VDDIO2 Monitor Line Status.
*/
#define __HAL_PWR_VDDIO2_EXTI_GET_FLAG() (EXTI- & gt; PR & (PWR_EXTI_LINE_VDDIO2))

/**
* @brief Clear the VDDIO2 Monitor EXTI flag.
* @retval None.
*/
#define __HAL_PWR_VDDIO2_EXTI_CLEAR_FLAG() (EXTI- & gt; PR = (PWR_EXTI_LINE_VDDIO2))

/**
* @brief Generate a Software interrupt on selected EXTI line.
* @retval None.
*/
#define __HAL_PWR_VDDIO2_EXTI_GENERATE_SWIT() (EXTI- & gt; SWIER |= (PWR_EXTI_LINE_VDDIO2))


#endif /* defined (STM32F042x6) || defined (STM32F048xx) ||\
defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
defined (STM32F091xC) || defined (STM32F098xx) */

/**
* @}
*/

/* Exported functions --------------------------------------------------------*/

/** @addtogroup PWREx_Exported_Functions PWREx Exported Functions
* @{
*/

/** @addtogroup PWREx_Exported_Functions_Group1
* @{
*/
/* I/O operation functions ***************************************************/
#if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \
defined (STM32F071xB) || defined (STM32F072xB) || \
defined (STM32F091xC)
void HAL_PWR_PVD_IRQHandler(void);
void HAL_PWR_PVDCallback(void);
#endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */
/* defined (STM32F071xB) || defined (STM32F072xB) || */
/* defined (STM32F091xC) */

#if defined (STM32F042x6) || defined (STM32F048xx) || \
defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
defined (STM32F091xC) || defined (STM32F098xx)
void HAL_PWREx_Vddio2Monitor_IRQHandler(void);
void HAL_PWREx_Vddio2MonitorCallback(void);
#endif /* defined (STM32F042x6) || defined (STM32F048xx) || \
defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
defined (STM32F091xC) || defined (STM32F098xx) */

/* Peripheral Control functions **********************************************/
#if defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || \
defined (STM32F071xB) || defined (STM32F072xB) || \
defined (STM32F091xC)
void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
void HAL_PWR_EnablePVD(void);
void HAL_PWR_DisablePVD(void);
#endif /* defined (STM32F031x6) || defined (STM32F042x6) || defined (STM32F051x8) || */
/* defined (STM32F071xB) || defined (STM32F072xB) || */
/* defined (STM32F091xC) */

#if defined (STM32F042x6) || defined (STM32F048xx) || \
defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
defined (STM32F091xC) || defined (STM32F098xx)
void HAL_PWREx_EnableVddio2Monitor(void);
void HAL_PWREx_DisableVddio2Monitor(void);
#endif /* defined (STM32F042x6) || defined (STM32F048xx) || \
defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \
defined (STM32F091xC) || defined (STM32F098xx) */

/**
* @}
*/

/**
* @}
*/

/**
* @}
*/

/**
* @}
*/

#ifdef __cplusplus
}
#endif

#endif /* __STM32F0xx_HAL_PWR_EX_H */

/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

ssr_test.zip > stm32f0xx_hal_rcc.h

/**
******************************************************************************
* @file stm32f0xx_hal_rcc.h
* @author MCD Application Team
* @brief Header file of RCC HAL module.
******************************************************************************
* @attention
*
* & lt; h2 & gt; & lt; center & gt; & copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved. & lt; /center & gt; & lt; /h2 & gt;
*
* This software component is licensed by ST under BSD 3-Clause license,
* the " License " ; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/

/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F0xx_HAL_RCC_H
#define __STM32F0xx_HAL_RCC_H

#ifdef __cplusplus
extern " C " {
#endif

/* Includes ------------------------------------------------------------------*/
#include " stm32f0xx_hal_def.h "

/** @addtogroup STM32F0xx_HAL_Driver
* @{
*/

/** @addtogroup RCC
* @{
*/

/** @addtogroup RCC_Private_Constants
* @{
*/

/** @defgroup RCC_Timeout RCC Timeout
* @{
*/

/* Disable Backup domain write protection state change timeout */
#define RCC_DBP_TIMEOUT_VALUE (100U) /* 100 ms */
/* LSE state change timeout */
#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
#define CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */
#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
#define HSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */
#define LSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */
#define PLL_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */
#define HSI14_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */
#if defined(RCC_HSI48_SUPPORT)
#define HSI48_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */
#endif /* RCC_HSI48_SUPPORT */
/**
* @}
*/

/** @defgroup RCC_Register_Offset Register offsets
* @{
*/
#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
#define RCC_CR_OFFSET 0x00
#define RCC_CFGR_OFFSET 0x04
#define RCC_CIR_OFFSET 0x08
#define RCC_BDCR_OFFSET 0x20
#define RCC_CSR_OFFSET 0x24

/**
* @}
*/


/* CR register byte 2 (Bits[23:16]) base address */
#define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U))

/* CIR register byte 1 (Bits[15:8]) base address */
#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U))

/* CIR register byte 2 (Bits[23:16]) base address */
#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U))

/* Defines used for Flags */
#define CR_REG_INDEX ((uint8_t)1U)
#define CR2_REG_INDEX ((uint8_t)2U)
#define BDCR_REG_INDEX ((uint8_t)3U)
#define CSR_REG_INDEX ((uint8_t)4U)

/* Bits position in in the CFGR register */
#define RCC_CFGR_PLLMUL_BITNUMBER 18U
#define RCC_CFGR_HPRE_BITNUMBER 4U
#define RCC_CFGR_PPRE_BITNUMBER 8U
/* Flags in the CFGR2 register */
#define RCC_CFGR2_PREDIV_BITNUMBER 0
/* Flags in the CR register */
#define RCC_CR_HSIRDY_BitNumber 1
#define RCC_CR_HSERDY_BitNumber 17
#define RCC_CR_PLLRDY_BitNumber 25
/* Flags in the CR2 register */
#define RCC_CR2_HSI14RDY_BitNumber 1
#define RCC_CR2_HSI48RDY_BitNumber 16
/* Flags in the BDCR register */
#define RCC_BDCR_LSERDY_BitNumber 1
/* Flags in the CSR register */
#define RCC_CSR_LSIRDY_BitNumber 1
#define RCC_CSR_V18PWRRSTF_BitNumber 23
#define RCC_CSR_RMVF_BitNumber 24
#define RCC_CSR_OBLRSTF_BitNumber 25
#define RCC_CSR_PINRSTF_BitNumber 26
#define RCC_CSR_PORRSTF_BitNumber 27
#define RCC_CSR_SFTRSTF_BitNumber 28
#define RCC_CSR_IWDGRSTF_BitNumber 29
#define RCC_CSR_WWDGRSTF_BitNumber 30
#define RCC_CSR_LPWRRSTF_BitNumber 31
/* Flags in the HSITRIM register */
#define RCC_CR_HSITRIM_BitNumber 3
#define RCC_HSI14TRIM_BIT_NUMBER 3
#define RCC_FLAG_MASK ((uint8_t)0x1FU)

/**
* @}
*/

/** @addtogroup RCC_Private_Macros
* @{
*/
#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
((__HSE__) == RCC_HSE_BYPASS))
#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
((__LSE__) == RCC_LSE_BYPASS))
#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
#define IS_RCC_HSI14(__HSI14__) (((__HSI14__) == RCC_HSI14_OFF) || ((__HSI14__) == RCC_HSI14_ON) || ((__HSI14__) == RCC_HSI14_ADC_CONTROL))
#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) & lt; = 0x1FU)
#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \
((__PLL__) == RCC_PLL_ON))
#define IS_RCC_PREDIV(__PREDIV__) (((__PREDIV__) == RCC_PREDIV_DIV1) || ((__PREDIV__) == RCC_PREDIV_DIV2) || \
((__PREDIV__) == RCC_PREDIV_DIV3) || ((__PREDIV__) == RCC_PREDIV_DIV4) || \
((__PREDIV__) == RCC_PREDIV_DIV5) || ((__PREDIV__) == RCC_PREDIV_DIV6) || \
((__PREDIV__) == RCC_PREDIV_DIV7) || ((__PREDIV__) == RCC_PREDIV_DIV8) || \
((__PREDIV__) == RCC_PREDIV_DIV9) || ((__PREDIV__) == RCC_PREDIV_DIV10) || \
((__PREDIV__) == RCC_PREDIV_DIV11) || ((__PREDIV__) == RCC_PREDIV_DIV12) || \
((__PREDIV__) == RCC_PREDIV_DIV13) || ((__PREDIV__) == RCC_PREDIV_DIV14) || \
((__PREDIV__) == RCC_PREDIV_DIV15) || ((__PREDIV__) == RCC_PREDIV_DIV16))

#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL2) || ((__MUL__) == RCC_PLL_MUL3) || \
((__MUL__) == RCC_PLL_MUL4) || ((__MUL__) == RCC_PLL_MUL5) || \
((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL7) || \
((__MUL__) == RCC_PLL_MUL8) || ((__MUL__) == RCC_PLL_MUL9) || \
((__MUL__) == RCC_PLL_MUL10) || ((__MUL__) == RCC_PLL_MUL11) || \
((__MUL__) == RCC_PLL_MUL12) || ((__MUL__) == RCC_PLL_MUL13) || \
((__MUL__) == RCC_PLL_MUL14) || ((__MUL__) == RCC_PLL_MUL15) || \
((__MUL__) == RCC_PLL_MUL16))
#define IS_RCC_CLOCKTYPE(__CLK__) ((((__CLK__) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \
(((__CLK__) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \
(((__CLK__) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1))
#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \
((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \
((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \
((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
((__HCLK__) == RCC_SYSCLK_DIV512))
#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
((__PCLK__) == RCC_HCLK_DIV16))
#define IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO)
#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \
((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32))
#define IS_RCC_USART1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK1) || \
((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \
((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \
((__SOURCE__) == RCC_USART1CLKSOURCE_HSI))
#define IS_RCC_I2C1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI) || \
((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK))

/**
* @}
*/

/* Exported types ------------------------------------------------------------*/

/** @defgroup RCC_Exported_Types RCC Exported Types
* @{
*/

/**
* @brief RCC PLL configuration structure definition
*/
typedef struct
{
uint32_t PLLState; /*! & lt; PLLState: The new state of the PLL.
This parameter can be a value of @ref RCC_PLL_Config */

uint32_t PLLSource; /*! & lt; PLLSource: PLL entry clock source.
This parameter must be a value of @ref RCC_PLL_Clock_Source */

uint32_t PLLMUL; /*! & lt; PLLMUL: Multiplication factor for PLL VCO input clock
This parameter must be a value of @ref RCC_PLL_Multiplication_Factor*/

uint32_t PREDIV; /*! & lt; PREDIV: Predivision factor for PLL VCO input clock
This parameter must be a value of @ref RCC_PLL_Prediv_Factor */

} RCC_PLLInitTypeDef;

/**
* @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
*/
typedef struct
{
uint32_t OscillatorType; /*! & lt; The oscillators to be configured.
This parameter can be a value of @ref RCC_Oscillator_Type */

uint32_t HSEState; /*! & lt; The new state of the HSE.
This parameter can be a value of @ref RCC_HSE_Config */

uint32_t LSEState; /*! & lt; The new state of the LSE.
This parameter can be a value of @ref RCC_LSE_Config */

uint32_t HSIState; /*! & lt; The new state of the HSI.
This parameter can be a value of @ref RCC_HSI_Config */

uint32_t HSICalibrationValue; /*! & lt; The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1FU */

uint32_t HSI14State; /*! & lt; The new state of the HSI14.
This parameter can be a value of @ref RCC_HSI14_Config */

uint32_t HSI14CalibrationValue; /*! & lt; The HSI14 calibration trimming value (default is RCC_HSI14CALIBRATION_DEFAULT).
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1FU */

uint32_t LSIState; /*! & lt; The new state of the LSI.
This parameter can be a value of @ref RCC_LSI_Config */

#if defined(RCC_HSI48_SUPPORT)
uint32_t HSI48State; /*! & lt; The new state of the HSI48.
This parameter can be a value of @ref RCC_HSI48_Config */

#endif /* RCC_HSI48_SUPPORT */
RCC_PLLInitTypeDef PLL; /*! & lt; PLL structure parameters */

} RCC_OscInitTypeDef;

/**
* @brief RCC System, AHB and APB busses clock configuration structure definition
*/
typedef struct
{
uint32_t ClockType; /*! & lt; The clock to be configured.
This parameter can be a value of @ref RCC_System_Clock_Type */

uint32_t SYSCLKSource; /*! & lt; The clock source (SYSCLKS) used as system clock.
This parameter can be a value of @ref RCC_System_Clock_Source */

uint32_t AHBCLKDivider; /*! & lt; The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
This parameter can be a value of @ref RCC_AHB_Clock_Source */

uint32_t APB1CLKDivider; /*! & lt; The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
This parameter can be a value of @ref RCC_APB1_Clock_Source */

} RCC_ClkInitTypeDef;

/**
* @}
*/

/* Exported constants --------------------------------------------------------*/
/** @defgroup RCC_Exported_Constants RCC Exported Constants
* @{
*/

/** @defgroup RCC_PLL_Clock_Source PLL Clock Source
* @{
*/

#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV /*! & lt; HSE clock selected as PLL entry clock source */

/**
* @}
*/

/** @defgroup RCC_Oscillator_Type Oscillator Type
* @{
*/
#define RCC_OSCILLATORTYPE_NONE (0x00000000U)
#define RCC_OSCILLATORTYPE_HSE (0x00000001U)
#define RCC_OSCILLATORTYPE_HSI (0x00000002U)
#define RCC_OSCILLATORTYPE_LSE (0x00000004U)
#define RCC_OSCILLATORTYPE_LSI (0x00000008U)
#define RCC_OSCILLATORTYPE_HSI14 (0x00000010U)
#if defined(RCC_HSI48_SUPPORT)
#define RCC_OSCILLATORTYPE_HSI48 (0x00000020U)
#endif /* RCC_HSI48_SUPPORT */
/**
* @}
*/

/** @defgroup RCC_HSE_Config HSE Config
* @{
*/
#define RCC_HSE_OFF (0x00000000U) /*! & lt; HSE clock deactivation */
#define RCC_HSE_ON (0x00000001U) /*! & lt; HSE clock activation */
#define RCC_HSE_BYPASS (0x00000005U) /*! & lt; External clock source for HSE clock */
/**
* @}
*/

/** @defgroup RCC_LSE_Config LSE Config
* @{
*/
#define RCC_LSE_OFF (0x00000000U) /*! & lt; LSE clock deactivation */
#define RCC_LSE_ON (0x00000001U) /*! & lt; LSE clock activation */
#define RCC_LSE_BYPASS (0x00000005U) /*! & lt; External clock source for LSE clock */

/**
* @}
*/

/** @defgroup RCC_HSI_Config HSI Config
* @{
*/
#define RCC_HSI_OFF (0x00000000U) /*! & lt; HSI clock deactivation */
#define RCC_HSI_ON RCC_CR_HSION /*! & lt; HSI clock activation */

#define RCC_HSICALIBRATION_DEFAULT (0x10U) /* Default HSI calibration trimming value */

/**
* @}
*/

/** @defgroup RCC_HSI14_Config RCC HSI14 Config
* @{
*/
#define RCC_HSI14_OFF (0x00000000U)
#define RCC_HSI14_ON RCC_CR2_HSI14ON
#define RCC_HSI14_ADC_CONTROL (~RCC_CR2_HSI14DIS)

#define RCC_HSI14CALIBRATION_DEFAULT (0x10U) /* Default HSI14 calibration trimming value */
/**
* @}
*/

/** @defgroup RCC_LSI_Config LSI Config
* @{
*/
#define RCC_LSI_OFF (0x00000000U) /*! & lt; LSI clock deactivation */
#define RCC_LSI_ON RCC_CSR_LSION /*! & lt; LSI clock activation */

/**
* @}
*/

#if defined(RCC_HSI48_SUPPORT)
/** @defgroup RCC_HSI48_Config HSI48 Config
* @{
*/
#define RCC_HSI48_OFF ((uint8_t)0x00U)
#define RCC_HSI48_ON ((uint8_t)0x01U)

/**
* @}
*/
#endif /* RCC_HSI48_SUPPORT */

/** @defgroup RCC_PLL_Config PLL Config
* @{
*/
#define RCC_PLL_NONE (0x00000000U) /*! & lt; PLL is not configured */
#define RCC_PLL_OFF (0x00000001U) /*! & lt; PLL deactivation */
#define RCC_PLL_ON (0x00000002U) /*! & lt; PLL activation */

/**
* @}
*/

/** @defgroup RCC_System_Clock_Type System Clock Type
* @{
*/
#define RCC_CLOCKTYPE_SYSCLK (0x00000001U) /*! & lt; SYSCLK to configure */
#define RCC_CLOCKTYPE_HCLK (0x00000002U) /*! & lt; HCLK to configure */
#define RCC_CLOCKTYPE_PCLK1 (0x00000004U) /*! & lt; PCLK1 to configure */

/**
* @}
*/

/** @defgroup RCC_System_Clock_Source System Clock Source
* @{
*/
#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*! & lt; HSI selected as system clock */
#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*! & lt; HSE selected as system clock */
#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*! & lt; PLL selected as system clock */

/**
* @}
*/

/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
* @{
*/
#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*! & lt; HSI used as system clock */
#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*! & lt; HSE used as system clock */
#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*! & lt; PLL used as system clock */

/**
* @}
*/

/** @defgroup RCC_AHB_Clock_Source AHB Clock Source
* @{
*/
#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*! & lt; SYSCLK not divided */
#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*! & lt; SYSCLK divided by 2 */
#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*! & lt; SYSCLK divided by 4 */
#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*! & lt; SYSCLK divided by 8 */
#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*! & lt; SYSCLK divided by 16 */
#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*! & lt; SYSCLK divided by 64 */
#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*! & lt; SYSCLK divided by 128 */
#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*! & lt; SYSCLK divided by 256 */
#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*! & lt; SYSCLK divided by 512 */

/**
* @}
*/

/** @defgroup RCC_APB1_Clock_Source RCC APB1 Clock Source
* @{
*/
#define RCC_HCLK_DIV1 RCC_CFGR_PPRE_DIV1 /*! & lt; HCLK not divided */
#define RCC_HCLK_DIV2 RCC_CFGR_PPRE_DIV2 /*! & lt; HCLK divided by 2 */
#define RCC_HCLK_DIV4 RCC_CFGR_PPRE_DIV4 /*! & lt; HCLK divided by 4 */
#define RCC_HCLK_DIV8 RCC_CFGR_PPRE_DIV8 /*! & lt; HCLK divided by 8 */
#define RCC_HCLK_DIV16 RCC_CFGR_PPRE_DIV16 /*! & lt; HCLK divided by 16 */

/**
* @}
*/

/** @defgroup RCC_RTC_Clock_Source RTC Clock Source
* @{
*/
#define RCC_RTCCLKSOURCE_NO_CLK (0x00000000U) /*! & lt; No clock */
#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE /*! & lt; LSE oscillator clock used as RTC clock */
#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI /*! & lt; LSI oscillator clock used as RTC clock */
#define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL_HSE /*! & lt; HSE oscillator clock divided by 32 used as RTC clock */
/**
* @}
*/

/** @defgroup RCC_PLL_Multiplication_Factor RCC PLL Multiplication Factor
* @{
*/
#define RCC_PLL_MUL2 RCC_CFGR_PLLMUL2
#define RCC_PLL_MUL3 RCC_CFGR_PLLMUL3
#define RCC_PLL_MUL4 RCC_CFGR_PLLMUL4
#define RCC_PLL_MUL5 RCC_CFGR_PLLMUL5
#define RCC_PLL_MUL6 RCC_CFGR_PLLMUL6
#define RCC_PLL_MUL7 RCC_CFGR_PLLMUL7
#define RCC_PLL_MUL8 RCC_CFGR_PLLMUL8
#define RCC_PLL_MUL9 RCC_CFGR_PLLMUL9
#define RCC_PLL_MUL10 RCC_CFGR_PLLMUL10
#define RCC_PLL_MUL11 RCC_CFGR_PLLMUL11
#define RCC_PLL_MUL12 RCC_CFGR_PLLMUL12
#define RCC_PLL_MUL13 RCC_CFGR_PLLMUL13
#define RCC_PLL_MUL14 RCC_CFGR_PLLMUL14
#define RCC_PLL_MUL15 RCC_CFGR_PLLMUL15
#define RCC_PLL_MUL16 RCC_CFGR_PLLMUL16

/**
* @}
*/

/** @defgroup RCC_PLL_Prediv_Factor RCC PLL Prediv Factor
* @{
*/

#define RCC_PREDIV_DIV1 RCC_CFGR2_PREDIV_DIV1
#define RCC_PREDIV_DIV2 RCC_CFGR2_PREDIV_DIV2
#define RCC_PREDIV_DIV3 RCC_CFGR2_PREDIV_DIV3
#define RCC_PREDIV_DIV4 RCC_CFGR2_PREDIV_DIV4
#define RCC_PREDIV_DIV5 RCC_CFGR2_PREDIV_DIV5
#define RCC_PREDIV_DIV6 RCC_CFGR2_PREDIV_DIV6
#define RCC_PREDIV_DIV7 RCC_CFGR2_PREDIV_DIV7
#define RCC_PREDIV_DIV8 RCC_CFGR2_PREDIV_DIV8
#define RCC_PREDIV_DIV9 RCC_CFGR2_PREDIV_DIV9
#define RCC_PREDIV_DIV10 RCC_CFGR2_PREDIV_DIV10
#define RCC_PREDIV_DIV11 RCC_CFGR2_PREDIV_DIV11
#define RCC_PREDIV_DIV12 RCC_CFGR2_PREDIV_DIV12
#define RCC_PREDIV_DIV13 RCC_CFGR2_PREDIV_DIV13
#define RCC_PREDIV_DIV14 RCC_CFGR2_PREDIV_DIV14
#define RCC_PREDIV_DIV15 RCC_CFGR2_PREDIV_DIV15
#define RCC_PREDIV_DIV16 RCC_CFGR2_PREDIV_DIV16

/**
* @}
*/


/** @defgroup RCC_USART1_Clock_Source RCC USART1 Clock Source
* @{
*/
#define RCC_USART1CLKSOURCE_PCLK1 RCC_CFGR3_USART1SW_PCLK
#define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
#define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
#define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI

/**
* @}
*/

/** @defgroup RCC_I2C1_Clock_Source RCC I2C1 Clock Source
* @{
*/
#define RCC_I2C1CLKSOURCE_HSI RCC_CFGR3_I2C1SW_HSI
#define RCC_I2C1CLKSOURCE_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK

/**
* @}
*/
/** @defgroup RCC_MCO_Index MCO Index
* @{
*/
#define RCC_MCO1 (0x00000000U)
#define RCC_MCO RCC_MCO1 /*! & lt; MCO1 to be compliant with other families with 2 MCOs*/

/**
* @}
*/

/** @defgroup RCC_MCO_Clock_Source RCC MCO Clock Source
* @{
*/
#define RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCO_NOCLOCK
#define RCC_MCO1SOURCE_LSI RCC_CFGR_MCO_LSI
#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO_LSE
#define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK
#define RCC_MCO1SOURCE_HSI RCC_CFGR_MCO_HSI
#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO_HSE
#define RCC_MCO1SOURCE_PLLCLK_DIV2 RCC_CFGR_MCO_PLL
#define RCC_MCO1SOURCE_HSI14 RCC_CFGR_MCO_HSI14

/**
* @}
*/

/** @defgroup RCC_Interrupt Interrupts
* @{
*/
#define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF) /*! & lt; LSI Ready Interrupt flag */
#define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF) /*! & lt; LSE Ready Interrupt flag */
#define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF) /*! & lt; HSI Ready Interrupt flag */
#define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF) /*! & lt; HSE Ready Interrupt flag */
#define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF) /*! & lt; PLL Ready Interrupt flag */
#define RCC_IT_HSI14RDY ((uint8_t)RCC_CIR_HSI14RDYF) /*! & lt; HSI14 Ready Interrupt flag */
#if defined(RCC_CIR_HSI48RDYF)
#define RCC_IT_HSI48RDY ((uint8_t)RCC_CIR_HSI48RDYF) /*! & lt; HSI48 Ready Interrupt flag */
#endif
#define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF) /*! & lt; Clock Security System Interrupt flag */
/**
* @}
*/

/** @defgroup RCC_Flag Flags
* Elements values convention: XXXYYYYYb
* - YYYYY : Flag position in the register
* - XXX : Register index
* - 001: CR register
* - 010: CR2 register
* - 011: BDCR register
* - 0100: CSR register
* @{
*/
/* Flags in the CR register */
#define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX & lt; & lt; 5U) | RCC_CR_HSIRDY_BitNumber))
#define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX & lt; & lt; 5U) | RCC_CR_HSERDY_BitNumber))
#define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX & lt; & lt; 5U) | RCC_CR_PLLRDY_BitNumber))
/* Flags in the CR2 register */
#define RCC_FLAG_HSI14RDY ((uint8_t)((CR2_REG_INDEX & lt; & lt; 5U) | RCC_CR2_HSI14RDY_BitNumber))

/* Flags in the CSR register */
#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX & lt; & lt; 5U) | RCC_CSR_LSIRDY_BitNumber))
#if defined(RCC_CSR_V18PWRRSTF)
#define RCC_FLAG_V18PWRRST ((uint8_t)((CSR_REG_INDEX & lt; & lt; 5U) | RCC_CSR_V18PWRRSTF_BitNumber))
#endif
#define RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX & lt; & lt; 5U) | RCC_CSR_OBLRSTF_BitNumber))
#define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX & lt; & lt; 5U) | RCC_CSR_PINRSTF_BitNumber)) /*! & lt; PIN reset flag */
#define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX & lt; & lt; 5U) | RCC_CSR_PORRSTF_BitNumber)) /*! & lt; POR/PDR reset flag */
#define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX & lt; & lt; 5U) | RCC_CSR_SFTRSTF_BitNumber)) /*! & lt; Software Reset flag */
#define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX & lt; & lt; 5U) | RCC_CSR_IWDGRSTF_BitNumber)) /*! & lt; Independent Watchdog reset flag */
#define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX & lt; & lt; 5U) | RCC_CSR_WWDGRSTF_BitNumber)) /*! & lt; Window watchdog reset flag */
#define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX & lt; & lt; 5U) | RCC_CSR_LPWRRSTF_BitNumber)) /*! & lt; Low-Power reset flag */

/* Flags in the BDCR register */
#define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX & lt; & lt; 5U) | RCC_BDCR_LSERDY_BitNumber)) /*! & lt; External Low Speed oscillator Ready */

/**
* @}
*/

/**
* @}
*/

/* Exported macro ------------------------------------------------------------*/

/** @defgroup RCC_Exported_Macros RCC Exported Macros
* @{
*/

/** @defgroup RCC_AHB_Clock_Enable_Disable RCC AHB Clock Enable Disable
* @brief Enable or disable the AHB peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
* using it.
* @{
*/
#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC- & gt; AHBENR, RCC_AHBENR_GPIOAEN);\
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC- & gt; AHBENR, RCC_AHBENR_GPIOAEN);\
UNUSED(tmpreg); \
} while(0U)
#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC- & gt; AHBENR, RCC_AHBENR_GPIOBEN);\
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC- & gt; AHBENR, RCC_AHBENR_GPIOBEN);\
UNUSED(tmpreg); \
} while(0U)
#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC- & gt; AHBENR, RCC_AHBENR_GPIOCEN);\
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC- & gt; AHBENR, RCC_AHBENR_GPIOCEN);\
UNUSED(tmpreg); \
} while(0U)
#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC- & gt; AHBENR, RCC_AHBENR_GPIOFEN);\
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC- & gt; AHBENR, RCC_AHBENR_GPIOFEN);\
UNUSED(tmpreg); \
} while(0U)
#define __HAL_RCC_CRC_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC- & gt; AHBENR, RCC_AHBENR_CRCEN);\
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC- & gt; AHBENR, RCC_AHBENR_CRCEN);\
UNUSED(tmpreg); \
} while(0U)
#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC- & gt; AHBENR, RCC_AHBENR_DMA1EN);\
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC- & gt; AHBENR, RCC_AHBENR_DMA1EN);\
UNUSED(tmpreg); \
} while(0U)
#define __HAL_RCC_SRAM_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC- & gt; AHBENR, RCC_AHBENR_SRAMEN);\
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC- & gt; AHBENR, RCC_AHBENR_SRAMEN);\
UNUSED(tmpreg); \
} while(0U)
#define __HAL_RCC_FLITF_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC- & gt; AHBENR, RCC_AHBENR_FLITFEN);\
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC- & gt; AHBENR, RCC_AHBENR_FLITFEN);\
UNUSED(tmpreg); \
} while(0U)

#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC- & gt; AHBENR & = ~(RCC_AHBENR_GPIOAEN))
#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC- & gt; AHBENR & = ~(RCC_AHBENR_GPIOBEN))
#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC- & gt; AHBENR & = ~(RCC_AHBENR_GPIOCEN))
#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC- & gt; AHBENR & = ~(RCC_AHBENR_GPIOFEN))
#define __HAL_RCC_CRC_CLK_DISABLE() (RCC- & gt; AHBENR & = ~(RCC_AHBENR_CRCEN))
#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC- & gt; AHBENR & = ~(RCC_AHBENR_DMA1EN))
#define __HAL_RCC_SRAM_CLK_DISABLE() (RCC- & gt; AHBENR & = ~(RCC_AHBENR_SRAMEN))
#define __HAL_RCC_FLITF_CLK_DISABLE() (RCC- & gt; AHBENR & = ~(RCC_AHBENR_FLITFEN))
/**
* @}
*/

/** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status
* @brief Get the enable or disable status of the AHB peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
* using it.
* @{
*/
#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC- & gt; AHBENR & (RCC_AHBENR_GPIOAEN)) != RESET)
#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC- & gt; AHBENR & (RCC_AHBENR_GPIOBEN)) != RESET)
#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC- & gt; AHBENR & (RCC_AHBENR_GPIOCEN)) != RESET)
#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC- & gt; AHBENR & (RCC_AHBENR_GPIOFEN)) != RESET)
#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC- & gt; AHBENR & (RCC_AHBENR_CRCEN)) != RESET)
#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC- & gt; AHBENR & (RCC_AHBENR_DMA1EN)) != RESET)
#define __HAL_RCC_SRAM_IS_CLK_ENABLED() ((RCC- & gt; AHBENR & (RCC_AHBENR_SRAMEN)) != RESET)
#define __HAL_RCC_FLITF_IS_CLK_ENABLED() ((RCC- & gt; AHBENR & (RCC_AHBENR_FLITFEN)) != RESET)
#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC- & gt; AHBENR & (RCC_AHBENR_GPIOAEN)) == RESET)
#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC- & gt; AHBENR & (RCC_AHBENR_GPIOBEN)) == RESET)
#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC- & gt; AHBENR & (RCC_AHBENR_GPIOCEN)) == RESET)
#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC- & gt; AHBENR & (RCC_AHBENR_GPIOFEN)) == RESET)
#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC- & gt; AHBENR & (RCC_AHBENR_CRCEN)) == RESET)
#define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC- & gt; AHBENR & (RCC_AHBENR_DMA1EN)) == RESET)
#define __HAL_RCC_SRAM_IS_CLK_DISABLED() ((RCC- & gt; AHBENR & (RCC_AHBENR_SRAMEN)) == RESET)
#define __HAL_RCC_FLITF_IS_CLK_DISABLED() ((RCC- & gt; AHBENR & (RCC_AHBENR_FLITFEN)) == RESET)
/**
* @}
*/

/** @defgroup RCC_APB1_Clock_Enable_Disable RCC APB1 Clock Enable Disable
* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
* using it.
* @{
*/
#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC- & gt; APB1ENR, RCC_APB1ENR_TIM3EN);\
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC- & gt; APB1ENR, RCC_APB1ENR_TIM3EN);\
UNUSED(tmpreg); \
} while(0U)
#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC- & gt; APB1ENR, RCC_APB1ENR_TIM14EN);\
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC- & gt; APB1ENR, RCC_APB1ENR_TIM14EN);\
UNUSED(tmpreg); \
} while(0U)
#define __HAL_RCC_WWDG_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC- & gt; APB1ENR, RCC_APB1ENR_WWDGEN);\
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC- & gt; APB1ENR, RCC_APB1ENR_WWDGEN);\
UNUSED(tmpreg); \
} while(0U)
#define __HAL_RCC_I2C1_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC- & gt; APB1ENR, RCC_APB1ENR_I2C1EN);\
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC- & gt; APB1ENR, RCC_APB1ENR_I2C1EN);\
UNUSED(tmpreg); \
} while(0U)
#define __HAL_RCC_PWR_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC- & gt; APB1ENR, RCC_APB1ENR_PWREN);\
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC- & gt; APB1ENR, RCC_APB1ENR_PWREN);\
UNUSED(tmpreg); \
} while(0U)

#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC- & gt; APB1ENR & = ~(RCC_APB1ENR_TIM3EN))
#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC- & gt; APB1ENR & = ~(RCC_APB1ENR_TIM14EN))
#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC- & gt; APB1ENR & = ~(RCC_APB1ENR_WWDGEN))
#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC- & gt; APB1ENR & = ~(RCC_APB1ENR_I2C1EN))
#define __HAL_RCC_PWR_CLK_DISABLE() (RCC- & gt; APB1ENR & = ~(RCC_APB1ENR_PWREN))
/**
* @}
*/

/** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
* @brief Get the enable or disable status of the APB1 peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
* using it.
* @{
*/
#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC- & gt; APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC- & gt; APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
#define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC- & gt; APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC- & gt; APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC- & gt; APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC- & gt; APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC- & gt; APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
#define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC- & gt; APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC- & gt; APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC- & gt; APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
/**
* @}
*/


/** @defgroup RCC_APB2_Clock_Enable_Disable RCC APB2 Clock Enable Disable
* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
* using it.
* @{
*/
#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC- & gt; APB2ENR, RCC_APB2ENR_SYSCFGEN);\
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC- & gt; APB2ENR, RCC_APB2ENR_SYSCFGEN);\
UNUSED(tmpreg); \
} while(0U)
#define __HAL_RCC_ADC1_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC- & gt; APB2ENR, RCC_APB2ENR_ADC1EN);\
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC- & gt; APB2ENR, RCC_APB2ENR_ADC1EN);\
UNUSED(tmpreg); \
} while(0U)
#define __HAL_RCC_TIM1_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC- & gt; APB2ENR, RCC_APB2ENR_TIM1EN);\
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC- & gt; APB2ENR, RCC_APB2ENR_TIM1EN);\
UNUSED(tmpreg); \
} while(0U)
#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC- & gt; APB2ENR, RCC_APB2ENR_SPI1EN);\
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC- & gt; APB2ENR, RCC_APB2ENR_SPI1EN);\
UNUSED(tmpreg); \
} while(0U)
#define __HAL_RCC_TIM16_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC- & gt; APB2ENR, RCC_APB2ENR_TIM16EN);\
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC- & gt; APB2ENR, RCC_APB2ENR_TIM16EN);\
UNUSED(tmpreg); \
} while(0U)
#define __HAL_RCC_TIM17_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC- & gt; APB2ENR, RCC_APB2ENR_TIM17EN);\
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC- & gt; APB2ENR, RCC_APB2ENR_TIM17EN);\
UNUSED(tmpreg); \
} while(0U)
#define __HAL_RCC_USART1_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC- & gt; APB2ENR, RCC_APB2ENR_USART1EN);\
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC- & gt; APB2ENR, RCC_APB2ENR_USART1EN);\
UNUSED(tmpreg); \
} while(0U)
#define __HAL_RCC_DBGMCU_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC- & gt; APB2ENR, RCC_APB2ENR_DBGMCUEN);\
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC- & gt; APB2ENR, RCC_APB2ENR_DBGMCUEN);\
UNUSED(tmpreg); \
} while(0U)

#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC- & gt; APB2ENR & = ~(RCC_APB2ENR_SYSCFGEN))
#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC- & gt; APB2ENR & = ~(RCC_APB2ENR_ADC1EN))
#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC- & gt; APB2ENR & = ~(RCC_APB2ENR_TIM1EN))
#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC- & gt; APB2ENR & = ~(RCC_APB2ENR_SPI1EN))
#define __HAL_RCC_TIM16_CLK_DISABLE() (RCC- & gt; APB2ENR & = ~(RCC_APB2ENR_TIM16EN))
#define __HAL_RCC_TIM17_CLK_DISABLE() (RCC- & gt; APB2ENR & = ~(RCC_APB2ENR_TIM17EN))
#define __HAL_RCC_USART1_CLK_DISABLE() (RCC- & gt; APB2ENR & = ~(RCC_APB2ENR_USART1EN))
#define __HAL_RCC_DBGMCU_CLK_DISABLE() (RCC- & gt; APB2ENR & = ~(RCC_APB2ENR_DBGMCUEN))
/**
* @}
*/

/** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
* @brief Get the enable or disable status of the APB2 peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
* using it.
* @{
*/
#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC- & gt; APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET)
#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC- & gt; APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
#define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC- & gt; APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC- & gt; APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
#define __HAL_RCC_TIM16_IS_CLK_ENABLED() ((RCC- & gt; APB2ENR & (RCC_APB2ENR_TIM16EN)) != RESET)
#define __HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC- & gt; APB2ENR & (RCC_APB2ENR_TIM17EN)) != RESET)
#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC- & gt; APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
#define __HAL_RCC_DBGMCU_IS_CLK_ENABLED() ((RCC- & gt; APB2ENR & (RCC_APB2ENR_DBGMCUEN)) != RESET)
#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC- & gt; APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET)
#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC- & gt; APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
#define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC- & gt; APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC- & gt; APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
#define __HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC- & gt; APB2ENR & (RCC_APB2ENR_TIM16EN)) == RESET)
#define __HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC- & gt; APB2ENR & (RCC_APB2ENR_TIM17EN)) == RESET)
#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC- & gt; APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
#define __HAL_RCC_DBGMCU_IS_CLK_DISABLED() ((RCC- & gt; APB2ENR & (RCC_APB2ENR_DBGMCUEN)) == RESET)
/**
* @}
*/

/** @defgroup RCC_AHB_Force_Release_Reset RCC AHB Force Release Reset
* @brief Force or release AHB peripheral reset.
* @{
*/
#define __HAL_RCC_AHB_FORCE_RESET() (RCC- & gt; AHBRSTR = 0xFFFFFFFFU)
#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC- & gt; AHBRSTR |= (RCC_AHBRSTR_GPIOARST))
#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC- & gt; AHBRSTR |= (RCC_AHBRSTR_GPIOBRST))
#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC- & gt; AHBRSTR |= (RCC_AHBRSTR_GPIOCRST))
#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC- & gt; AHBRSTR |= (RCC_AHBRSTR_GPIOFRST))

#define __HAL_RCC_AHB_RELEASE_RESET() (RCC- & gt; AHBRSTR = 0x00000000U)
#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC- & gt; AHBRSTR & = ~(RCC_AHBRSTR_GPIOARST))
#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC- & gt; AHBRSTR & = ~(RCC_AHBRSTR_GPIOBRST))
#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC- & gt; AHBRSTR & = ~(RCC_AHBRSTR_GPIOCRST))
#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC- & gt; AHBRSTR & = ~(RCC_AHBRSTR_GPIOFRST))
/**
* @}
*/

/** @defgroup RCC_APB1_Force_Release_Reset RCC APB1 Force Release Reset
* @brief Force or release APB1 peripheral reset.
* @{
*/
#define __HAL_RCC_APB1_FORCE_RESET() (RCC- & gt; APB1RSTR = 0xFFFFFFFFU)
#define __HAL_RCC_TIM3_FORCE_RESET() (RCC- & gt; APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
#define __HAL_RCC_TIM14_FORCE_RESET() (RCC- & gt; APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
#define __HAL_RCC_WWDG_FORCE_RESET() (RCC- & gt; APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
#define __HAL_RCC_I2C1_FORCE_RESET() (RCC- & gt; APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
#define __HAL_RCC_PWR_FORCE_RESET() (RCC- & gt; APB1RSTR |= (RCC_APB1RSTR_PWRRST))

#define __HAL_RCC_APB1_RELEASE_RESET() (RCC- & gt; APB1RSTR = 0x00000000U)
#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC- & gt; APB1RSTR & = ~(RCC_APB1RSTR_TIM3RST))
#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC- & gt; APB1RSTR & = ~(RCC_APB1RSTR_TIM14RST))
#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC- & gt; APB1RSTR & = ~(RCC_APB1RSTR_WWDGRST))
#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC- & gt; APB1RSTR & = ~(RCC_APB1RSTR_I2C1RST))
#define __HAL_RCC_PWR_RELEASE_RESET() (RCC- & gt; APB1RSTR & = ~(RCC_APB1RSTR_PWRRST))
/**
* @}
*/

/** @defgroup RCC_APB2_Force_Release_Reset RCC APB2 Force Release Reset
* @brief Force or release APB2 peripheral reset.
* @{
*/
#define __HAL_RCC_APB2_FORCE_RESET() (RCC- & gt; APB2RSTR = 0xFFFFFFFFU)
#define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC- & gt; APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
#define __HAL_RCC_ADC1_FORCE_RESET() (RCC- & gt; APB2RSTR |= (RCC_APB2RSTR_ADC1RST))
#define __HAL_RCC_TIM1_FORCE_RESET() (RCC- & gt; APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
#define __HAL_RCC_SPI1_FORCE_RESET() (RCC- & gt; APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
#define __HAL_RCC_USART1_FORCE_RESET() (RCC- & gt; APB2RSTR |= (RCC_APB2RSTR_USART1RST))
#define __HAL_RCC_TIM16_FORCE_RESET() (RCC- & gt; APB2RSTR |= (RCC_APB2RSTR_TIM16RST))
#define __HAL_RCC_TIM17_FORCE_RESET() (RCC- & gt; APB2RSTR |= (RCC_APB2RSTR_TIM17RST))
#define __HAL_RCC_DBGMCU_FORCE_RESET() (RCC- & gt; APB2RSTR |= (RCC_APB2RSTR_DBGMCURST))

#define __HAL_RCC_APB2_RELEASE_RESET() (RCC- & gt; APB2RSTR = 0x00000000U)
#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC- & gt; APB2RSTR & = ~(RCC_APB2RSTR_SYSCFGRST))
#define __HAL_RCC_ADC1_RELEASE_RESET() (RCC- & gt; APB2RSTR & = ~(RCC_APB2RSTR_ADC1RST))
#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC- & gt; APB2RSTR & = ~(RCC_APB2RSTR_TIM1RST))
#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC- & gt; APB2RSTR & = ~(RCC_APB2RSTR_SPI1RST))
#define __HAL_RCC_USART1_RELEASE_RESET() (RCC- & gt; APB2RSTR & = ~(RCC_APB2RSTR_USART1RST))
#define __HAL_RCC_TIM16_RELEASE_RESET() (RCC- & gt; APB2RSTR & = ~(RCC_APB2RSTR_TIM16RST))
#define __HAL_RCC_TIM17_RELEASE_RESET() (RCC- & gt; APB2RSTR & = ~(RCC_APB2RSTR_TIM17RST))
#define __HAL_RCC_DBGMCU_RELEASE_RESET() (RCC- & gt; APB2RSTR & = ~(RCC_APB2RSTR_DBGMCURST))
/**
* @}
*/
/** @defgroup RCC_HSI_Configuration HSI Configuration
* @{
*/

/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
* @note HSI can not be stopped if it is used as system clock source. In this case,
* you have to select another source of the system clock then stop the HSI.
* @note After enabling the HSI, the application software should wait on HSIRDY
* flag to be set indicating that HSI clock is stable and can be used as
* system clock source.
* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
* clock cycles.
*/
#define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC- & gt; CR, RCC_CR_HSION)
#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC- & gt; CR, RCC_CR_HSION)

/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
* @note The calibration is used to compensate for the variations in voltage
* and temperature that influence the frequency of the internal HSI RC.
* @param _HSICALIBRATIONVALUE_ specifies the calibration trimming value.
* (default is RCC_HSICALIBRATION_DEFAULT).
* This parameter must be a number between 0 and 0x1F.
*/
#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \
MODIFY_REG(RCC- & gt; CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) & lt; & lt; RCC_CR_HSITRIM_BitNumber)

/**
* @}
*/

/** @defgroup RCC_LSI_Configuration LSI Configuration
* @{
*/

/** @brief Macro to enable the Internal Low Speed oscillator (LSI).
* @note After enabling the LSI, the application software should wait on
* LSIRDY flag to be set indicating that LSI clock is stable and can
* be used to clock the IWDG and/or the RTC.
*/
#define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC- & gt; CSR, RCC_CSR_LSION)

/** @brief Macro to disable the Internal Low Speed oscillator (LSI).
* @note LSI can not be disabled if the IWDG is running.
* @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
* clock cycles.
*/
#define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC- & gt; CSR, RCC_CSR_LSION)

/**
* @}
*/

/** @defgroup RCC_HSE_Configuration HSE Configuration
* @{
*/

/**
* @brief Macro to configure the External High Speed oscillator (HSE).
* @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
* supported by this macro. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
* software should wait on HSERDY flag to be set indicating that HSE clock
* is stable and can be used to clock the PLL and/or system clock.
* @note HSE state can not be changed if it is used directly or through the
* PLL as system clock. In this case, you have to select another source
* of the system clock then change the HSE state (ex. disable it).
* @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
* @note This function reset the CSSON bit, so if the clock security system(CSS)
* was previously enabled you have to enable it again after calling this
* function.
* @param __STATE__ specifies the new state of the HSE.
* This parameter can be one of the following values:
* @arg @ref RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after
* 6 HSE oscillator clock cycles.
* @arg @ref RCC_HSE_ON turn ON the HSE oscillator
* @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock
*/
#define __HAL_RCC_HSE_CONFIG(__STATE__) \
do{ \
if ((__STATE__) == RCC_HSE_ON) \
{ \
SET_BIT(RCC- & gt; CR, RCC_CR_HSEON); \
} \
else if ((__STATE__) == RCC_HSE_OFF) \
{ \
CLEAR_BIT(RCC- & gt; CR, RCC_CR_HSEON); \
CLEAR_BIT(RCC- & gt; CR, RCC_CR_HSEBYP); \
} \
else if ((__STATE__) == RCC_HSE_BYPASS) \
{ \
SET_BIT(RCC- & gt; CR, RCC_CR_HSEBYP); \
SET_BIT(RCC- & gt; CR, RCC_CR_HSEON); \
} \
else \
{ \
CLEAR_BIT(RCC- & gt; CR, RCC_CR_HSEON); \
CLEAR_BIT(RCC- & gt; CR, RCC_CR_HSEBYP); \
} \
}while(0U)

/**
* @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.
* @note Predivision factor can not be changed if PLL is used as system clock
* In this case, you have to select another source of the system clock, disable the PLL and
* then change the HSE predivision factor.
* @param __HSE_PREDIV_VALUE__ specifies the division value applied to HSE.
* This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16.
*/
#define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) \
MODIFY_REG(RCC- & gt; CFGR2, RCC_CFGR2_PREDIV, (uint32_t)(__HSE_PREDIV_VALUE__))

/**
* @}
*/

/** @defgroup RCC_LSE_Configuration LSE Configuration
* @{
*/

/**
* @brief Macro to configure the External Low Speed oscillator (LSE).
* @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
* @note As the LSE is in the Backup domain and write access is denied to
* this domain after reset, you have to enable write access using
* @ref HAL_PWR_EnableBkUpAccess() function before to configure the LSE
* (to be done once after reset).
* @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
* software should wait on LSERDY flag to be set indicating that LSE clock
* is stable and can be used to clock the RTC.
* @param __STATE__ specifies the new state of the LSE.
* This parameter can be one of the following values:
* @arg @ref RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after
* 6 LSE oscillator clock cycles.
* @arg @ref RCC_LSE_ON turn ON the LSE oscillator.
* @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock.
*/
#define __HAL_RCC_LSE_CONFIG(__STATE__) \
do{ \
if ((__STATE__) == RCC_LSE_ON) \
{ \
SET_BIT(RCC- & gt; BDCR, RCC_BDCR_LSEON); \
} \
else if ((__STATE__) == RCC_LSE_OFF) \
{ \
CLEAR_BIT(RCC- & gt; BDCR, RCC_BDCR_LSEON); \
CLEAR_BIT(RCC- & gt; BDCR, RCC_BDCR_LSEBYP); \
} \
else if ((__STATE__) == RCC_LSE_BYPASS) \
{ \
SET_BIT(RCC- & gt; BDCR, RCC_BDCR_LSEBYP); \
SET_BIT(RCC- & gt; BDCR, RCC_BDCR_LSEON); \
} \
else \
{ \
CLEAR_BIT(RCC- & gt; BDCR, RCC_BDCR_LSEON); \
CLEAR_BIT(RCC- & gt; BDCR, RCC_BDCR_LSEBYP); \
} \
}while(0U)

/**
* @}
*/

/** @defgroup RCC_HSI14_Configuration RCC_HSI14_Configuration
* @{
*/

/** @brief Macro to enable the Internal 14Mhz High Speed oscillator (HSI14).
* @note After enabling the HSI14 with @ref __HAL_RCC_HSI14_ENABLE(), the application software
* should wait on HSI14RDY flag to be set indicating that HSI clock is stable and can be
* used as system clock source. This is not necessary if @ref HAL_RCC_OscConfig() is used.
* clock cycles.
*/
#define __HAL_RCC_HSI14_ENABLE() SET_BIT(RCC- & gt; CR2, RCC_CR2_HSI14ON)

/** @brief Macro to disable the Internal 14Mhz High Speed oscillator (HSI14).
* @note The HSI14 is stopped by hardware when entering STOP and STANDBY modes.
* @note HSI14 can not be stopped if it is used as system clock source. In this case,
* you have to select another source of the system clock then stop the HSI14.
* @note When the HSI14 is stopped, HSI14RDY flag goes low after 6 HSI14 oscillator
* clock cycles.
*/
#define __HAL_RCC_HSI14_DISABLE() CLEAR_BIT(RCC- & gt; CR2, RCC_CR2_HSI14ON)

/** @brief Macro to enable the Internal 14Mhz High Speed oscillator (HSI14) used by ADC.
*/
#define __HAL_RCC_HSI14ADC_ENABLE() CLEAR_BIT(RCC- & gt; CR2, RCC_CR2_HSI14DIS)

/** @brief Macro to disable the Internal 14Mhz High Speed oscillator (HSI14) used by ADC.
*/
#define __HAL_RCC_HSI14ADC_DISABLE() SET_BIT(RCC- & gt; CR2, RCC_CR2_HSI14DIS)

/** @brief Macro to adjust the Internal 14Mhz High Speed oscillator (HSI) calibration value.
* @note The calibration is used to compensate for the variations in voltage
* and temperature that influence the frequency of the internal HSI14 RC.
* @param __HSI14CALIBRATIONVALUE__ specifies the calibration trimming value
* (default is RCC_HSI14CALIBRATION_DEFAULT).
* This parameter must be a number between 0 and 0x1F.
*/
#define __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(__HSI14CALIBRATIONVALUE__) \
MODIFY_REG(RCC- & gt; CR2, RCC_CR2_HSI14TRIM, (uint32_t)(__HSI14CALIBRATIONVALUE__) & lt; & lt; RCC_HSI14TRIM_BIT_NUMBER)
/**
* @}
*/

/** @defgroup RCC_USARTx_Clock_Config RCC USARTx Clock Config
* @{
*/

/** @brief Macro to configure the USART1 clock (USART1CLK).
* @param __USART1CLKSOURCE__ specifies the USART1 clock source.
* This parameter can be one of the following values:
* @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
* @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock
* @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock
* @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock
*/
#define __HAL_RCC_USART1_CONFIG(__USART1CLKSOURCE__) \
MODIFY_REG(RCC- & gt; CFGR3, RCC_CFGR3_USART1SW, (uint32_t)(__USART1CLKSOURCE__))

/** @brief Macro to get the USART1 clock source.
* @retval The clock source can be one of the following values:
* @arg @ref RCC_USART1CLKSOURCE_PCLK1 PCLK1 selected as USART1 clock
* @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock
* @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock
* @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock
*/
#define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC- & gt; CFGR3, RCC_CFGR3_USART1SW)))

/**
* @}
*/

/** @defgroup RCC_I2Cx_Clock_Config RCC I2Cx Clock Config
* @{
*/

/** @brief Macro to configure the I2C1 clock (I2C1CLK).
* @param __I2C1CLKSOURCE__ specifies the I2C1 clock source.
* This parameter can be one of the following values:
* @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock
* @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock
*/
#define __HAL_RCC_I2C1_CONFIG(__I2C1CLKSOURCE__) \
MODIFY_REG(RCC- & gt; CFGR3, RCC_CFGR3_I2C1SW, (uint32_t)(__I2C1CLKSOURCE__))

/** @brief Macro to get the I2C1 clock source.
* @retval The clock source can be one of the following values:
* @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock
* @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock
*/
#define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC- & gt; CFGR3, RCC_CFGR3_I2C1SW)))
/**
* @}
*/

/** @defgroup RCC_PLL_Configuration PLL Configuration
* @{
*/

/** @brief Macro to enable the main PLL.
* @note After enabling the main PLL, the application software should wait on
* PLLRDY flag to be set indicating that PLL clock is stable and can
* be used as system clock source.
* @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
*/
#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC- & gt; CR, RCC_CR_PLLON)

/** @brief Macro to disable the main PLL.
* @note The main PLL can not be disabled if it is used as system clock source
*/
#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC- & gt; CR, RCC_CR_PLLON)

/** @brief Macro to configure the PLL clock source, multiplication and division factors.
* @note This function must be used only when the main PLL is disabled.
*
* @param __RCC_PLLSOURCE__ specifies the PLL entry clock source.
* This parameter can be one of the following values:
* @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry
* @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
* @param __PLLMUL__ specifies the multiplication factor for PLL VCO output clock
* This parameter can be one of the following values:
* This parameter must be a number between RCC_PLL_MUL2 and RCC_PLL_MUL16.
* @param __PREDIV__ specifies the predivider factor for PLL VCO input clock
* This parameter must be a number between RCC_PREDIV_DIV1 and RCC_PREDIV_DIV16.
*
*/
#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__ , __PREDIV__, __PLLMUL__) \
do { \
MODIFY_REG(RCC- & gt; CFGR2, RCC_CFGR2_PREDIV, (__PREDIV__)); \
MODIFY_REG(RCC- & gt; CFGR, RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)|(__RCC_PLLSOURCE__))); \
} while(0U)


/** @brief Get oscillator clock selected as PLL input clock
* @retval The clock source used for PLL entry. The returned value can be one
* of the following:
* @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock
*/
#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC- & gt; CFGR, RCC_CFGR_PLLSRC)))

/**
* @}
*/

/** @defgroup RCC_Get_Clock_source Get Clock source
* @{
*/

/**
* @brief Macro to configure the system clock source.
* @param __SYSCLKSOURCE__ specifies the system clock source.
* This parameter can be one of the following values:
* @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source.
* @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source.
* @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source.
*/
#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
MODIFY_REG(RCC- & gt; CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))

/** @brief Macro to get the clock source used as system clock.
* @retval The clock source used as system clock. The returned value can be one
* of the following:
* @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock
* @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock
* @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock
*/
#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC- & gt; CFGR & RCC_CFGR_SWS))

/**
* @}
*/

/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
* @{
*/

#if defined(RCC_CFGR_MCOPRE)
/** @brief Macro to configure the MCO clock.
* @param __MCOCLKSOURCE__ specifies the MCO clock source.
* This parameter can be one of the following values:
* @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
* @arg @ref RCC_MCO1SOURCE_SYSCLK System Clock selected as MCO clock
* @arg @ref RCC_MCO1SOURCE_HSI HSI oscillator clock selected as MCO clock
* @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock
* @arg @ref RCC_MCO1SOURCE_LSI LSI selected as MCO clock
* @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock
* @arg @ref RCC_MCO1SOURCE_HSI14 HSI14 selected as MCO clock
@if STM32F042x6
* @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock
* @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
@elseif STM32F048xx
* @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock
* @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
@elseif STM32F071xB
* @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock
* @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
@elseif STM32F072xB
* @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock
* @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
@elseif STM32F078xx
* @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock
* @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
@elseif STM32F091xC
* @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock
* @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
@elseif STM32F098xx
* @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock
* @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
@elseif STM32F030x6
* @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
@elseif STM32F030xC
* @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
@elseif STM32F031x6
* @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
@elseif STM32F038xx
* @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
@elseif STM32F070x6
* @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
@elseif STM32F070xB
* @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
@endif
* @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock
* @param __MCODIV__ specifies the MCO clock prescaler.
* This parameter can be one of the following values:
* @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1
* @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2
* @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4
* @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8
* @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16
* @arg @ref RCC_MCODIV_32 MCO clock source is divided by 32
* @arg @ref RCC_MCODIV_64 MCO clock source is divided by 64
* @arg @ref RCC_MCODIV_128 MCO clock source is divided by 128
*/
#else
/** @brief Macro to configure the MCO clock.
* @param __MCOCLKSOURCE__ specifies the MCO clock source.
* This parameter can be one of the following values:
* @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
* @arg @ref RCC_MCO1SOURCE_SYSCLK System Clock selected as MCO clock
* @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock
* @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock
* @arg @ref RCC_MCO1SOURCE_LSI LSI selected as MCO clock
* @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock
* @arg @ref RCC_MCO1SOURCE_HSI14 HSI14 selected as MCO clock
* @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock
* @param __MCODIV__ specifies the MCO clock prescaler.
* This parameter can be one of the following values:
* @arg @ref RCC_MCODIV_1 No division applied on MCO clock source
*/
#endif
#if defined(RCC_CFGR_MCOPRE)
#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
MODIFY_REG(RCC- & gt; CFGR, (RCC_CFGR_MCO | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
#else

#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
MODIFY_REG(RCC- & gt; CFGR, RCC_CFGR_MCO, (__MCOCLKSOURCE__))

#endif

/**
* @}
*/

/** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
* @{
*/

/** @brief Macro to configure the RTC clock (RTCCLK).
* @note As the RTC clock configuration bits are in the Backup domain and write
* access is denied to this domain after reset, you have to enable write
* access using the Power Backup Access macro before to configure
* the RTC clock source (to be done once after reset).
* @note Once the RTC clock is configured it cannot be changed unless the
* Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by
* a Power On Reset (POR).
*
* @param __RTC_CLKSOURCE__ specifies the RTC clock source.
* This parameter can be one of the following values:
* @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
* @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
* @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
* @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32
* @note If the LSE or LSI is used as RTC clock source, the RTC continues to
* work in STOP and STANDBY modes, and can be used as wakeup source.
* However, when the LSI clock and HSE clock divided by 32 is used as RTC clock source,
* the RTC cannot be used in STOP and STANDBY modes.
* @note The system must always be configured so as to get a PCLK frequency greater than or
* equal to the RTCCLK frequency for a proper operation of the RTC.
*/
#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC- & gt; BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))

/** @brief Macro to get the RTC clock source.
* @retval The clock source can be one of the following values:
* @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
* @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
* @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
* @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32
*/
#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC- & gt; BDCR, RCC_BDCR_RTCSEL))

/** @brief Macro to enable the the RTC clock.
* @note These macros must be used only after the RTC clock source was selected.
*/
#define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC- & gt; BDCR, RCC_BDCR_RTCEN)

/** @brief Macro to disable the the RTC clock.
* @note These macros must be used only after the RTC clock source was selected.
*/
#define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC- & gt; BDCR, RCC_BDCR_RTCEN)

/** @brief Macro to force the Backup domain reset.
* @note This function resets the RTC peripheral (including the backup registers)
* and the RTC clock source selection in RCC_BDCR register.
*/
#define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC- & gt; BDCR, RCC_BDCR_BDRST)

/** @brief Macros to release the Backup domain reset.
*/
#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC- & gt; BDCR, RCC_BDCR_BDRST)

/**
* @}
*/

/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
* @brief macros to manage the specified RCC Flags and interrupts.
* @{
*/

/** @brief Enable RCC interrupt.
* @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled.
* This parameter can be any combination of the following values:
* @arg @ref RCC_IT_LSIRDY LSI ready interrupt
* @arg @ref RCC_IT_LSERDY LSE ready interrupt
* @arg @ref RCC_IT_HSIRDY HSI ready interrupt
* @arg @ref RCC_IT_HSERDY HSE ready interrupt
* @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
* @arg @ref RCC_IT_HSI14RDY HSI14 ready interrupt
@if STM32F042x6
* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
@elseif STM32F048xx
* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
@elseif STM32F071xB
* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
@elseif STM32F072xB
* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
@elseif STM32F078xx
* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
@elseif STM32F091xC
* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
@elseif STM32F098xx
* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
@endif
*/
#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))

/** @brief Disable RCC interrupt.
* @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled.
* This parameter can be any combination of the following values:
* @arg @ref RCC_IT_LSIRDY LSI ready interrupt
* @arg @ref RCC_IT_LSERDY LSE ready interrupt
* @arg @ref RCC_IT_HSIRDY HSI ready interrupt
* @arg @ref RCC_IT_HSERDY HSE ready interrupt
* @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
* @arg @ref RCC_IT_HSI14RDY HSI14 ready interrupt
@if STM32F042x6
* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
@elseif STM32F048xx
* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
@elseif STM32F071xB
* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
@elseif STM32F072xB
* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
@elseif STM32F078xx
* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
@elseif STM32F091xC
* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
@elseif STM32F098xx
* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
@endif
*/
#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS & = (uint8_t)(~(__INTERRUPT__)))

/** @brief Clear the RCC's interrupt pending bits.
* @param __INTERRUPT__ specifies the interrupt pending bit to clear.
* This parameter can be any combination of the following values:
* @arg @ref RCC_IT_LSIRDY LSI ready interrupt.
* @arg @ref RCC_IT_LSERDY LSE ready interrupt.
* @arg @ref RCC_IT_HSIRDY HSI ready interrupt.
* @arg @ref RCC_IT_HSERDY HSE ready interrupt.
* @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.
* @arg @ref RCC_IT_CSS Clock Security System interrupt
* @arg @ref RCC_IT_HSI14RDY HSI14 ready interrupt
@if STM32F042x6
* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
@elseif STM32F048xx
* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
@elseif STM32F071xB
* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
@elseif STM32F072xB
* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
@elseif STM32F078xx
* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
@elseif STM32F091xC
* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
@elseif STM32F098xx
* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
@endif
*/
#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))

/** @brief Check the RCC's interrupt has occurred or not.
* @param __INTERRUPT__ specifies the RCC interrupt source to check.
* This parameter can be one of the following values:
* @arg @ref RCC_IT_LSIRDY LSI ready interrupt.
* @arg @ref RCC_IT_LSERDY LSE ready interrupt.
* @arg @ref RCC_IT_HSIRDY HSI ready interrupt.
* @arg @ref RCC_IT_HSERDY HSE ready interrupt.
* @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.
* @arg @ref RCC_IT_CSS Clock Security System interrupt
* @arg @ref RCC_IT_HSI14RDY HSI14 ready interrupt enable
@if STM32F042x6
* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
@elseif STM32F048xx
* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
@elseif STM32F071xB
* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
@elseif STM32F072xB
* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
@elseif STM32F078xx
* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
@elseif STM32F091xC
* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
@elseif STM32F098xx
* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt
@endif
* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
*/
#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC- & gt; CIR & (__INTERRUPT__)) == (__INTERRUPT__))

/** @brief Set RMVF bit to clear the reset flags.
* The reset flags are RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
* RCC_FLAG_OBLRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
*/
#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC- & gt; CSR |= RCC_CSR_RMVF)

/** @brief Check RCC flag is set or not.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready.
* @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready.
* @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready.
* @arg @ref RCC_FLAG_HSI14RDY HSI14 oscillator clock ready
@if STM32F038xx
* @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
@elseif STM32F042x6
* @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready
@elseif STM32F048xx
* @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready
* @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
@elseif STM32F058xx
* @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
@elseif STM32F071xB
* @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready
@elseif STM32F072xB
* @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready
@elseif STM32F078xx
* @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready
* @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
@elseif STM32F091xC
* @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready
@elseif STM32F098xx
* @arg @ref RCC_FLAG_HSI48RDY HSI48 oscillator clock ready
* @arg @ref RCC_FLAG_V18PWRRST Reset flag of the 1.8 V domain
@endif
* @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready.
* @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready.
* @arg @ref RCC_FLAG_OBLRST Option Byte Load reset
* @arg @ref RCC_FLAG_PINRST Pin reset.
* @arg @ref RCC_FLAG_PORRST POR/PDR reset.
* @arg @ref RCC_FLAG_SFTRST Software reset.
* @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset.
* @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset.
* @arg @ref RCC_FLAG_LPWRRST Low Power reset.
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) & gt; & gt; 5U) == CR_REG_INDEX)? RCC- & gt; CR : \
(((__FLAG__) & gt; & gt; 5U) == CR2_REG_INDEX)? RCC- & gt; CR2 : \
(((__FLAG__) & gt; & gt; 5U) == BDCR_REG_INDEX) ? RCC- & gt; BDCR : \
RCC- & gt; CSR) & (1U & lt; & lt; ((__FLAG__) & RCC_FLAG_MASK)))

/**
* @}
*/

/**
* @}
*/

/* Include RCC HAL Extension module */
#include " stm32f0xx_hal_rcc_ex.h "

/* Exported functions --------------------------------------------------------*/
/** @addtogroup RCC_Exported_Functions
* @{
*/

/** @addtogroup RCC_Exported_Functions_Group1
* @{
*/

/* Initialization and de-initialization functions ******************************/
HAL_StatusTypeDef HAL_RCC_DeInit(void);
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);

/**
* @}
*/

/** @addtogroup RCC_Exported_Functions_Group2
* @{
*/

/* Peripheral Control functions ************************************************/
void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
void HAL_RCC_EnableCSS(void);
/* CSS NMI IRQ handler */
void HAL_RCC_NMI_IRQHandler(void);
/* User Callbacks in non blocking mode (IT mode) */
void HAL_RCC_CSSCallback(void);
void HAL_RCC_DisableCSS(void);
uint32_t HAL_RCC_GetSysClockFreq(void);
uint32_t HAL_RCC_GetHCLKFreq(void);
uint32_t HAL_RCC_GetPCLK1Freq(void);
void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);

/**
* @}
*/

/**
* @}
*/

/**
* @}
*/

/**
* @}
*/

#ifdef __cplusplus
}
#endif

#endif /* __STM32F0xx_HAL_RCC_H */

/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

ssr_test.zip > stm32f0xx_hal_dma_ex.h

/**
******************************************************************************
* @file stm32f0xx_hal_dma_ex.h
* @author MCD Application Team
* @brief Header file of DMA HAL Extension module.
******************************************************************************
* @attention
*
* & lt; h2 & gt; & lt; center & gt; & copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved. & lt; /center & gt; & lt; /h2 & gt;
*
* This software component is licensed by ST under BSD 3-Clause license,
* the " License " ; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/

/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F0xx_HAL_DMA_EX_H
#define __STM32F0xx_HAL_DMA_EX_H

#ifdef __cplusplus
extern " C " {
#endif

/* Includes ------------------------------------------------------------------*/
#include " stm32f0xx_hal_def.h "

/** @addtogroup STM32F0xx_HAL_Driver
* @{
*/

/** @defgroup DMAEx DMAEx
* @brief DMA HAL module driver
* @{
*/

/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
/** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants
* @{
*/
#define DMA1_CHANNEL1_RMP 0x00000000 /*! & lt; Internal define for remaping on STM32F09x/30xC */
#define DMA1_CHANNEL2_RMP 0x10000000 /*! & lt; Internal define for remaping on STM32F09x/30xC */
#define DMA1_CHANNEL3_RMP 0x20000000 /*! & lt; Internal define for remaping on STM32F09x/30xC */
#define DMA1_CHANNEL4_RMP 0x30000000 /*! & lt; Internal define for remaping on STM32F09x/30xC */
#define DMA1_CHANNEL5_RMP 0x40000000 /*! & lt; Internal define for remaping on STM32F09x/30xC */
#if !defined(STM32F030xC)
#define DMA1_CHANNEL6_RMP 0x50000000 /*! & lt; Internal define for remaping on STM32F09x/30xC */
#define DMA1_CHANNEL7_RMP 0x60000000 /*! & lt; Internal define for remaping on STM32F09x/30xC */
#define DMA2_CHANNEL1_RMP 0x00000000 /*! & lt; Internal define for remaping on STM32F09x/30xC */
#define DMA2_CHANNEL2_RMP 0x10000000 /*! & lt; Internal define for remaping on STM32F09x/30xC */
#define DMA2_CHANNEL3_RMP 0x20000000 /*! & lt; Internal define for remaping on STM32F09x/30xC */
#define DMA2_CHANNEL4_RMP 0x30000000 /*! & lt; Internal define for remaping on STM32F09x/30xC */
#define DMA2_CHANNEL5_RMP 0x40000000 /*! & lt; Internal define for remaping on STM32F09x/30xC */
#endif /* !defined(STM32F030xC) */

/****************** DMA1 remap bit field definition********************/
/* DMA1 - Channel 1 */
#define HAL_DMA1_CH1_DEFAULT (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_DEFAULT) /*! & lt; Default remap position for DMA1 */
#define HAL_DMA1_CH1_ADC (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_ADC) /*! & lt; Remap ADC on DMA1 Channel 1*/
#define HAL_DMA1_CH1_TIM17_CH1 (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_TIM17_CH1) /*! & lt; Remap TIM17 channel 1 on DMA1 channel 1 */
#define HAL_DMA1_CH1_TIM17_UP (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_TIM17_UP) /*! & lt; Remap TIM17 up on DMA1 channel 1 */
#define HAL_DMA1_CH1_USART1_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART1_RX) /*! & lt; Remap USART1 Rx on DMA1 channel 1 */
#define HAL_DMA1_CH1_USART2_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART2_RX) /*! & lt; Remap USART2 Rx on DMA1 channel 1 */
#define HAL_DMA1_CH1_USART3_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART3_RX) /*! & lt; Remap USART3 Rx on DMA1 channel 1 */
#define HAL_DMA1_CH1_USART4_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART4_RX) /*! & lt; Remap USART4 Rx on DMA1 channel 1 */
#define HAL_DMA1_CH1_USART5_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART5_RX) /*! & lt; Remap USART5 Rx on DMA1 channel 1 */
#define HAL_DMA1_CH1_USART6_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART6_RX) /*! & lt; Remap USART6 Rx on DMA1 channel 1 */
#if !defined(STM32F030xC)
#define HAL_DMA1_CH1_USART7_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART7_RX) /*! & lt; Remap USART7 Rx on DMA1 channel 1 */
#define HAL_DMA1_CH1_USART8_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART8_RX) /*! & lt; Remap USART8 Rx on DMA1 channel 1 */
#endif /* !defined(STM32F030xC) */

/* DMA1 - Channel 2 */
#define HAL_DMA1_CH2_DEFAULT (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_DEFAULT) /*! & lt; Default remap position for DMA1 */
#define HAL_DMA1_CH2_ADC (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_ADC) /*! & lt; Remap ADC on DMA1 channel 2 */
#define HAL_DMA1_CH2_I2C1_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_I2C1_TX) /*! & lt; Remap I2C1 Tx on DMA1 channel 2 */
#define HAL_DMA1_CH2_SPI1_RX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_SPI1_RX) /*! & lt; Remap SPI1 Rx on DMA1 channel 2 */
#define HAL_DMA1_CH2_TIM1_CH1 (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_TIM1_CH1) /*! & lt; Remap TIM1 channel 1 on DMA1 channel 2 */
#define HAL_DMA1_CH2_TIM17_CH1 (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_TIM17_CH1) /*! & lt; Remap TIM17 channel 1 on DMA1 channel 2 */
#define HAL_DMA1_CH2_TIM17_UP (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_TIM17_UP) /*! & lt; Remap TIM17 up on DMA1 channel 2 */
#define HAL_DMA1_CH2_USART1_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART1_TX) /*! & lt; Remap USART1 Tx on DMA1 channel 2 */
#define HAL_DMA1_CH2_USART2_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART2_TX) /*! & lt; Remap USART2 Tx on DMA1 channel 2 */
#define HAL_DMA1_CH2_USART3_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART3_TX) /*! & lt; Remap USART3 Tx on DMA1 channel 2 */
#define HAL_DMA1_CH2_USART4_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART4_TX) /*! & lt; Remap USART4 Tx on DMA1 channel 2 */
#define HAL_DMA1_CH2_USART5_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART5_TX) /*! & lt; Remap USART5 Tx on DMA1 channel 2 */
#define HAL_DMA1_CH2_USART6_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART6_TX) /*! & lt; Remap USART6 Tx on DMA1 channel 2 */
#if !defined(STM32F030xC)
#define HAL_DMA1_CH2_USART7_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART7_TX) /*! & lt; Remap USART7 Tx on DMA1 channel 2 */
#define HAL_DMA1_CH2_USART8_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART8_TX) /*! & lt; Remap USART8 Tx on DMA1 channel 2 */
#endif /* !defined(STM32F030xC) */

/* DMA1 - Channel 3 */
#define HAL_DMA1_CH3_DEFAULT (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_DEFAULT) /*! & lt; Default remap position for DMA1 */
#define HAL_DMA1_CH3_TIM6_UP (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM6_UP) /*! & lt; Remap TIM6 up on DMA1 channel 3 */
#if !defined(STM32F030xC)
#define HAL_DMA1_CH3_DAC_CH1 (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_DAC_CH1) /*! & lt; Remap DAC Channel 1on DMA1 channel 3 */
#endif /* !defined(STM32F030xC) */
#define HAL_DMA1_CH3_I2C1_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_I2C1_RX) /*! & lt; Remap I2C1 Rx on DMA1 channel 3 */
#define HAL_DMA1_CH3_SPI1_TX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_SPI1_TX) /*! & lt; Remap SPI1 Tx on DMA1 channel 3 */
#define HAL_DMA1_CH3_TIM1_CH2 (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM1_CH2) /*! & lt; Remap TIM1 channel 2 on DMA1 channel 3 */
#if !defined(STM32F030xC)
#define HAL_DMA1_CH3_TIM2_CH2 (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM2_CH2) /*! & lt; Remap TIM2 channel 2 on DMA1 channel 3 */
#endif /* !defined(STM32F030xC) */
#define HAL_DMA1_CH3_TIM16_CH1 (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM16_CH1) /*! & lt; Remap TIM16 channel 1 on DMA1 channel 3 */
#define HAL_DMA1_CH3_TIM16_UP (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM16_UP) /*! & lt; Remap TIM16 up on DMA1 channel 3 */
#define HAL_DMA1_CH3_USART1_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART1_RX) /*! & lt; Remap USART1 Rx on DMA1 channel 3 */
#define HAL_DMA1_CH3_USART2_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART2_RX) /*! & lt; Remap USART2 Rx on DMA1 channel 3 */
#define HAL_DMA1_CH3_USART3_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART3_RX) /*! & lt; Remap USART3 Rx on DMA1 channel 3 */
#define HAL_DMA1_CH3_USART4_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART4_RX) /*! & lt; Remap USART4 Rx on DMA1 channel 3 */
#define HAL_DMA1_CH3_USART5_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART5_RX) /*! & lt; Remap USART5 Rx on DMA1 channel 3 */
#define HAL_DMA1_CH3_USART6_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART6_RX) /*! & lt; Remap USART6 Rx on DMA1 channel 3 */
#if !defined(STM32F030xC)
#define HAL_DMA1_CH3_USART7_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART7_RX) /*! & lt; Remap USART7 Rx on DMA1 channel 3 */
#define HAL_DMA1_CH3_USART8_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART8_RX) /*! & lt; Remap USART8 Rx on DMA1 channel 3 */
#endif /* !defined(STM32F030xC) */

/* DMA1 - Channel 4 */
#define HAL_DMA1_CH4_DEFAULT (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_DEFAULT) /*! & lt; Default remap position for DMA1 */
#define HAL_DMA1_CH4_TIM7_UP (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM7_UP) /*! & lt; Remap TIM7 up on DMA1 channel 4 */
#if !defined(STM32F030xC)
#define HAL_DMA1_CH4_DAC_CH2 (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_DAC_CH2) /*! & lt; Remap DAC Channel 2 on DMA1 channel 4 */
#endif /* !defined(STM32F030xC) */
#define HAL_DMA1_CH4_I2C2_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_I2C2_TX) /*! & lt; Remap I2C2 Tx on DMA1 channel 4 */
#define HAL_DMA1_CH4_SPI2_RX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_SPI2_RX) /*! & lt; Remap SPI2 Rx on DMA1 channel 4 */
#if !defined(STM32F030xC)
#define HAL_DMA1_CH4_TIM2_CH4 (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM2_CH4) /*! & lt; Remap TIM2 channel 4 on DMA1 channel 4 */
#endif /* !defined(STM32F030xC) */
#define HAL_DMA1_CH4_TIM3_CH1 (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM3_CH1) /*! & lt; Remap TIM3 channel 1 on DMA1 channel 4 */
#define HAL_DMA1_CH4_TIM3_TRIG (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM3_TRIG) /*! & lt; Remap TIM3 Trig on DMA1 channel 4 */
#define HAL_DMA1_CH4_TIM16_CH1 (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM16_CH1) /*! & lt; Remap TIM16 channel 1 on DMA1 channel 4 */
#define HAL_DMA1_CH4_TIM16_UP (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM16_UP) /*! & lt; Remap TIM16 up on DMA1 channel 4 */
#define HAL_DMA1_CH4_USART1_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART1_TX) /*! & lt; Remap USART1 Tx on DMA1 channel 4 */
#define HAL_DMA1_CH4_USART2_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART2_TX) /*! & lt; Remap USART2 Tx on DMA1 channel 4 */
#define HAL_DMA1_CH4_USART3_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART3_TX) /*! & lt; Remap USART3 Tx on DMA1 channel 4 */
#define HAL_DMA1_CH4_USART4_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART4_TX) /*! & lt; Remap USART4 Tx on DMA1 channel 4 */
#define HAL_DMA1_CH4_USART5_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART5_TX) /*! & lt; Remap USART5 Tx on DMA1 channel 4 */
#define HAL_DMA1_CH4_USART6_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART6_TX) /*! & lt; Remap USART6 Tx on DMA1 channel 4 */
#if !defined(STM32F030xC)
#define HAL_DMA1_CH4_USART7_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART7_TX) /*! & lt; Remap USART7 Tx on DMA1 channel 4 */
#define HAL_DMA1_CH4_USART8_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART8_TX) /*! & lt; Remap USART8 Tx on DMA1 channel 4 */
#endif /* !defined(STM32F030xC) */

/* DMA1 - Channel 5 */
#define HAL_DMA1_CH5_DEFAULT (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_DEFAULT) /*! & lt; Default remap position for DMA1 */
#define HAL_DMA1_CH5_I2C2_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_I2C2_RX) /*! & lt; Remap I2C2 Rx on DMA1 channel 5 */
#define HAL_DMA1_CH5_SPI2_TX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_SPI2_TX) /*! & lt; Remap SPI1 Tx on DMA1 channel 5 */
#define HAL_DMA1_CH5_TIM1_CH3 (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_TIM1_CH3) /*! & lt; Remap TIM1 channel 3 on DMA1 channel 5 */
#define HAL_DMA1_CH5_USART1_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART1_RX) /*! & lt; Remap USART1 Rx on DMA1 channel 5 */
#define HAL_DMA1_CH5_USART2_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART2_RX) /*! & lt; Remap USART2 Rx on DMA1 channel 5 */
#define HAL_DMA1_CH5_USART3_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART3_RX) /*! & lt; Remap USART3 Rx on DMA1 channel 5 */
#define HAL_DMA1_CH5_USART4_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART4_RX) /*! & lt; Remap USART4 Rx on DMA1 channel 5 */
#define HAL_DMA1_CH5_USART5_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART5_RX) /*! & lt; Remap USART5 Rx on DMA1 channel 5 */
#define HAL_DMA1_CH5_USART6_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART6_RX) /*! & lt; Remap USART6 Rx on DMA1 channel 5 */
#if !defined(STM32F030xC)
#define HAL_DMA1_CH5_USART7_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART7_RX) /*! & lt; Remap USART7 Rx on DMA1 channel 5 */
#define HAL_DMA1_CH5_USART8_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART8_RX) /*! & lt; Remap USART8 Rx on DMA1 channel 5 */
#endif /* !defined(STM32F030xC) */

#if !defined(STM32F030xC)
/* DMA1 - Channel 6 */
#define HAL_DMA1_CH6_DEFAULT (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_DEFAULT) /*! & lt; Default remap position for DMA1 */
#define HAL_DMA1_CH6_I2C1_TX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_I2C1_TX) /*! & lt; Remap I2C1 Tx on DMA1 channel 6 */
#define HAL_DMA1_CH6_SPI2_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_SPI2_RX) /*! & lt; Remap SPI2 Rx on DMA1 channel 6 */
#define HAL_DMA1_CH6_TIM1_CH1 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM1_CH1) /*! & lt; Remap TIM1 channel 1 on DMA1 channel 6 */
#define HAL_DMA1_CH6_TIM1_CH2 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM1_CH2) /*! & lt; Remap TIM1 channel 2 on DMA1 channel 6 */
#define HAL_DMA1_CH6_TIM1_CH3 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM1_CH3) /*! & lt; Remap TIM1 channel 3 on DMA1 channel 6 */
#define HAL_DMA1_CH6_TIM3_CH1 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM3_CH1) /*! & lt; Remap TIM3 channel 1 on DMA1 channel 6 */
#define HAL_DMA1_CH6_TIM3_TRIG (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM3_TRIG) /*! & lt; Remap TIM3 Trig on DMA1 channel 6 */
#define HAL_DMA1_CH6_TIM16_CH1 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM16_CH1) /*! & lt; Remap TIM16 channel 1 on DMA1 channel 6 */
#define HAL_DMA1_CH6_TIM16_UP (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM16_UP) /*! & lt; Remap TIM16 up on DMA1 channel 6 */
#define HAL_DMA1_CH6_USART1_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART1_RX) /*! & lt; Remap USART1 Rx on DMA1 channel 6 */
#define HAL_DMA1_CH6_USART2_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART2_RX) /*! & lt; Remap USART2 Rx on DMA1 channel 6 */
#define HAL_DMA1_CH6_USART3_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART3_RX) /*! & lt; Remap USART3 Rx on DMA1 channel 6 */
#define HAL_DMA1_CH6_USART4_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART4_RX) /*! & lt; Remap USART4 Rx on DMA1 channel 6 */
#define HAL_DMA1_CH6_USART5_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART5_RX) /*! & lt; Remap USART5 Rx on DMA1 channel 6 */
#define HAL_DMA1_CH6_USART6_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART6_RX) /*! & lt; Remap USART6 Rx on DMA1 channel 6 */
#define HAL_DMA1_CH6_USART7_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART7_RX) /*! & lt; Remap USART7 Rx on DMA1 channel 6 */
#define HAL_DMA1_CH6_USART8_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART8_RX) /*! & lt; Remap USART8 Rx on DMA1 channel 6 */
/* DMA1 - Channel 7 */
#define HAL_DMA1_CH7_DEFAULT (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_DEFAULT) /*! & lt; Default remap position for DMA1 */
#define HAL_DMA1_CH7_I2C1_RX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_I2C1_RX) /*! & lt; Remap I2C1 Rx on DMA1 channel 7 */
#define HAL_DMA1_CH7_SPI2_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_SPI2_TX) /*! & lt; Remap SPI2 Tx on DMA1 channel 7 */
#define HAL_DMA1_CH7_TIM2_CH2 (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM2_CH2) /*! & lt; Remap TIM2 channel 2 on DMA1 channel 7 */
#define HAL_DMA1_CH7_TIM2_CH4 (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM2_CH4) /*! & lt; Remap TIM2 channel 4 on DMA1 channel 7 */
#define HAL_DMA1_CH7_TIM17_CH1 (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM17_CH1) /*! & lt; Remap TIM17 channel 1 on DMA1 channel 7 */
#define HAL_DMA1_CH7_TIM17_UP (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM17_UP) /*! & lt; Remap TIM17 up on DMA1 channel 7 */
#define HAL_DMA1_CH7_USART1_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART1_TX) /*! & lt; Remap USART1 Tx on DMA1 channel 7 */
#define HAL_DMA1_CH7_USART2_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART2_TX) /*! & lt; Remap USART2 Tx on DMA1 channel 7 */
#define HAL_DMA1_CH7_USART3_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART3_TX) /*! & lt; Remap USART3 Tx on DMA1 channel 7 */
#define HAL_DMA1_CH7_USART4_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART4_TX) /*! & lt; Remap USART4 Tx on DMA1 channel 7 */
#define HAL_DMA1_CH7_USART5_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART5_TX) /*! & lt; Remap USART5 Tx on DMA1 channel 7 */
#define HAL_DMA1_CH7_USART6_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART6_TX) /*! & lt; Remap USART6 Tx on DMA1 channel 7 */
#define HAL_DMA1_CH7_USART7_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART7_TX) /*! & lt; Remap USART7 Tx on DMA1 channel 7 */
#define HAL_DMA1_CH7_USART8_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART8_TX) /*! & lt; Remap USART8 Tx on DMA1 channel 7 */

/****************** DMA2 remap bit field definition********************/
/* DMA2 - Channel 1 */
#define HAL_DMA2_CH1_DEFAULT (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_DEFAULT) /*! & lt; Default remap position for DMA2 */
#define HAL_DMA2_CH1_I2C2_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_I2C2_TX) /*! & lt; Remap I2C2 TX on DMA2 channel 1 */
#define HAL_DMA2_CH1_USART1_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART1_TX) /*! & lt; Remap USART1 Tx on DMA2 channel 1 */
#define HAL_DMA2_CH1_USART2_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART2_TX) /*! & lt; Remap USART2 Tx on DMA2 channel 1 */
#define HAL_DMA2_CH1_USART3_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART3_TX) /*! & lt; Remap USART3 Tx on DMA2 channel 1 */
#define HAL_DMA2_CH1_USART4_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART4_TX) /*! & lt; Remap USART4 Tx on DMA2 channel 1 */
#define HAL_DMA2_CH1_USART5_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART5_TX) /*! & lt; Remap USART5 Tx on DMA2 channel 1 */
#define HAL_DMA2_CH1_USART6_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART6_TX) /*! & lt; Remap USART6 Tx on DMA2 channel 1 */
#define HAL_DMA2_CH1_USART7_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART7_TX) /*! & lt; Remap USART7 Tx on DMA2 channel 1 */
#define HAL_DMA2_CH1_USART8_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART8_TX) /*! & lt; Remap USART8 Tx on DMA2 channel 1 */
/* DMA2 - Channel 2 */
#define HAL_DMA2_CH2_DEFAULT (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_DEFAULT) /*! & lt; Default remap position for DMA2 */
#define HAL_DMA2_CH2_I2C2_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_I2C2_RX) /*! & lt; Remap I2C2 Rx on DMA2 channel 2 */
#define HAL_DMA2_CH2_USART1_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART1_RX) /*! & lt; Remap USART1 Rx on DMA2 channel 2 */
#define HAL_DMA2_CH2_USART2_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART2_RX) /*! & lt; Remap USART2 Rx on DMA2 channel 2 */
#define HAL_DMA2_CH2_USART3_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART3_RX) /*! & lt; Remap USART3 Rx on DMA2 channel 2 */
#define HAL_DMA2_CH2_USART4_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART4_RX) /*! & lt; Remap USART4 Rx on DMA2 channel 2 */
#define HAL_DMA2_CH2_USART5_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART5_RX) /*! & lt; Remap USART5 Rx on DMA2 channel 2 */
#define HAL_DMA2_CH2_USART6_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART6_RX) /*! & lt; Remap USART6 Rx on DMA2 channel 2 */
#define HAL_DMA2_CH2_USART7_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART7_RX) /*! & lt; Remap USART7 Rx on DMA2 channel 2 */
#define HAL_DMA2_CH2_USART8_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART8_RX) /*! & lt; Remap USART8 Rx on DMA2 channel 2 */
/* DMA2 - Channel 3 */
#define HAL_DMA2_CH3_DEFAULT (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_DEFAULT) /*! & lt; Default remap position for DMA2 */
#define HAL_DMA2_CH3_TIM6_UP (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_TIM6_UP) /*! & lt; Remap TIM6 up on DMA2 channel 3 */
#define HAL_DMA2_CH3_DAC_CH1 (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_DAC_CH1) /*! & lt; Remap DAC channel 1 on DMA2 channel 3 */
#define HAL_DMA2_CH3_SPI1_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_SPI1_RX) /*! & lt; Remap SPI1 Rx on DMA2 channel 3 */
#define HAL_DMA2_CH3_USART1_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART1_RX) /*! & lt; Remap USART1 Rx on DMA2 channel 3 */
#define HAL_DMA2_CH3_USART2_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART2_RX) /*! & lt; Remap USART2 Rx on DMA2 channel 3 */
#define HAL_DMA2_CH3_USART3_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART3_RX) /*! & lt; Remap USART3 Rx on DMA2 channel 3 */
#define HAL_DMA2_CH3_USART4_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART4_RX) /*! & lt; Remap USART4 Rx on DMA2 channel 3 */
#define HAL_DMA2_CH3_USART5_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART5_RX) /*! & lt; Remap USART5 Rx on DMA2 channel 3 */
#define HAL_DMA2_CH3_USART6_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART6_RX) /*! & lt; Remap USART6 Rx on DMA2 channel 3 */
#define HAL_DMA2_CH3_USART7_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART7_RX) /*! & lt; Remap USART7 Rx on DMA2 channel 3 */
#define HAL_DMA2_CH3_USART8_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART8_RX) /*! & lt; Remap USART8 Rx on DMA2 channel 3 */
/* DMA2 - Channel 4 */
#define HAL_DMA2_CH4_DEFAULT (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_DEFAULT) /*! & lt; Default remap position for DMA2 */
#define HAL_DMA2_CH4_TIM7_UP (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_TIM7_UP) /*! & lt; Remap TIM7 up on DMA2 channel 4 */
#define HAL_DMA2_CH4_DAC_CH2 (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_DAC_CH2) /*! & lt; Remap DAC channel 2 on DMA2 channel 4 */
#define HAL_DMA2_CH4_SPI1_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_SPI1_TX) /*! & lt; Remap SPI1 Tx on DMA2 channel 4 */
#define HAL_DMA2_CH4_USART1_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART1_TX) /*! & lt; Remap USART1 Tx on DMA2 channel 4 */
#define HAL_DMA2_CH4_USART2_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART2_TX) /*! & lt; Remap USART2 Tx on DMA2 channel 4 */
#define HAL_DMA2_CH4_USART3_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART3_TX) /*! & lt; Remap USART3 Tx on DMA2 channel 4 */
#define HAL_DMA2_CH4_USART4_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART4_TX) /*! & lt; Remap USART4 Tx on DMA2 channel 4 */
#define HAL_DMA2_CH4_USART5_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART5_TX) /*! & lt; Remap USART5 Tx on DMA2 channel 4 */
#define HAL_DMA2_CH4_USART6_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART6_TX) /*! & lt; Remap USART6 Tx on DMA2 channel 4 */
#define HAL_DMA2_CH4_USART7_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART7_TX) /*! & lt; Remap USART7 Tx on DMA2 channel 4 */
#define HAL_DMA2_CH4_USART8_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART8_TX) /*! & lt; Remap USART8 Tx on DMA2 channel 4 */
/* DMA2 - Channel 5 */
#define HAL_DMA2_CH5_DEFAULT (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_DEFAULT) /*! & lt; Default remap position for DMA2 */
#define HAL_DMA2_CH5_ADC (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_ADC) /*! & lt; Remap ADC on DMA2 channel 5 */
#define HAL_DMA2_CH5_USART1_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART1_TX) /*! & lt; Remap USART1 Tx on DMA2 channel 5 */
#define HAL_DMA2_CH5_USART2_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART2_TX) /*! & lt; Remap USART2 Tx on DMA2 channel 5 */
#define HAL_DMA2_CH5_USART3_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART3_TX) /*! & lt; Remap USART3 Tx on DMA2 channel 5 */
#define HAL_DMA2_CH5_USART4_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART4_TX) /*! & lt; Remap USART4 Tx on DMA2 channel 5 */
#define HAL_DMA2_CH5_USART5_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART5_TX) /*! & lt; Remap USART5 Tx on DMA2 channel 5 */
#define HAL_DMA2_CH5_USART6_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART6_TX) /*! & lt; Remap USART6 Tx on DMA2 channel 5 */
#define HAL_DMA2_CH5_USART7_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART7_TX) /*! & lt; Remap USART7 Tx on DMA2 channel 5 */
#define HAL_DMA2_CH5_USART8_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART8_TX) /*! & lt; Remap USART8 Tx on DMA2 channel 5 */
#endif /* !defined(STM32F030xC) */

#if defined(STM32F091xC) || defined(STM32F098xx)
#define IS_HAL_DMA1_REMAP(REQUEST) (((REQUEST) == HAL_DMA1_CH1_DEFAULT) ||\
((REQUEST) == HAL_DMA1_CH1_ADC) ||\
((REQUEST) == HAL_DMA1_CH1_TIM17_CH1) ||\
((REQUEST) == HAL_DMA1_CH1_TIM17_UP) ||\
((REQUEST) == HAL_DMA1_CH1_USART1_RX) ||\
((REQUEST) == HAL_DMA1_CH1_USART2_RX) ||\
((REQUEST) == HAL_DMA1_CH1_USART3_RX) ||\
((REQUEST) == HAL_DMA1_CH1_USART4_RX) ||\
((REQUEST) == HAL_DMA1_CH1_USART5_RX) ||\
((REQUEST) == HAL_DMA1_CH1_USART6_RX) ||\
((REQUEST) == HAL_DMA1_CH1_USART7_RX) ||\
((REQUEST) == HAL_DMA1_CH1_USART8_RX) ||\
((REQUEST) == HAL_DMA1_CH2_DEFAULT) ||\
((REQUEST) == HAL_DMA1_CH2_ADC) ||\
((REQUEST) == HAL_DMA1_CH2_I2C1_TX) ||\
((REQUEST) == HAL_DMA1_CH2_SPI1_RX) ||\
((REQUEST) == HAL_DMA1_CH2_TIM1_CH1) ||\
((REQUEST) == HAL_DMA1_CH2_I2C1_TX) ||\
((REQUEST) == HAL_DMA1_CH2_TIM17_CH1) ||\
((REQUEST) == HAL_DMA1_CH2_TIM17_UP) ||\
((REQUEST) == HAL_DMA1_CH2_USART1_TX) ||\
((REQUEST) == HAL_DMA1_CH2_USART2_TX) ||\
((REQUEST) == HAL_DMA1_CH2_USART3_TX) ||\
((REQUEST) == HAL_DMA1_CH2_USART4_TX) ||\
((REQUEST) == HAL_DMA1_CH2_USART5_TX) ||\
((REQUEST) == HAL_DMA1_CH2_USART6_TX) ||\
((REQUEST) == HAL_DMA1_CH2_USART7_TX) ||\
((REQUEST) == HAL_DMA1_CH2_USART8_TX) ||\
((REQUEST) == HAL_DMA1_CH3_DEFAULT) ||\
((REQUEST) == HAL_DMA1_CH3_TIM6_UP) ||\
((REQUEST) == HAL_DMA1_CH3_DAC_CH1) ||\
((REQUEST) == HAL_DMA1_CH3_I2C1_RX) ||\
((REQUEST) == HAL_DMA1_CH3_SPI1_TX) ||\
((REQUEST) == HAL_DMA1_CH3_TIM1_CH2) ||\
((REQUEST) == HAL_DMA1_CH3_TIM2_CH2) ||\
((REQUEST) == HAL_DMA1_CH3_TIM16_CH1) ||\
((REQUEST) == HAL_DMA1_CH3_TIM16_UP) ||\
((REQUEST) == HAL_DMA1_CH3_USART1_RX) ||\
((REQUEST) == HAL_DMA1_CH3_USART2_RX) ||\
((REQUEST) == HAL_DMA1_CH3_USART3_RX) ||\
((REQUEST) == HAL_DMA1_CH3_USART4_RX) ||\
((REQUEST) == HAL_DMA1_CH3_USART5_RX) ||\
((REQUEST) == HAL_DMA1_CH3_USART6_RX) ||\
((REQUEST) == HAL_DMA1_CH3_USART7_RX) ||\
((REQUEST) == HAL_DMA1_CH3_USART8_RX) ||\
((REQUEST) == HAL_DMA1_CH4_DEFAULT) ||\
((REQUEST) == HAL_DMA1_CH4_TIM7_UP) ||\
((REQUEST) == HAL_DMA1_CH4_DAC_CH2) ||\
((REQUEST) == HAL_DMA1_CH4_I2C2_TX) ||\
((REQUEST) == HAL_DMA1_CH4_SPI2_RX) ||\
((REQUEST) == HAL_DMA1_CH4_TIM2_CH4) ||\
((REQUEST) == HAL_DMA1_CH4_TIM3_CH1) ||\
((REQUEST) == HAL_DMA1_CH4_TIM3_TRIG) ||\
((REQUEST) == HAL_DMA1_CH4_TIM16_CH1) ||\
((REQUEST) == HAL_DMA1_CH4_TIM16_UP) ||\
((REQUEST) == HAL_DMA1_CH4_USART1_TX) ||\
((REQUEST) == HAL_DMA1_CH4_USART2_TX) ||\
((REQUEST) == HAL_DMA1_CH4_USART3_TX) ||\
((REQUEST) == HAL_DMA1_CH4_USART4_TX) ||\
((REQUEST) == HAL_DMA1_CH4_USART5_TX) ||\
((REQUEST) == HAL_DMA1_CH4_USART6_TX) ||\
((REQUEST) == HAL_DMA1_CH4_USART7_TX) ||\
((REQUEST) == HAL_DMA1_CH4_USART8_TX) ||\
((REQUEST) == HAL_DMA1_CH5_DEFAULT) ||\
((REQUEST) == HAL_DMA1_CH5_I2C2_RX) ||\
((REQUEST) == HAL_DMA1_CH5_SPI2_TX) ||\
((REQUEST) == HAL_DMA1_CH5_TIM1_CH3) ||\
((REQUEST) == HAL_DMA1_CH5_USART1_RX) ||\
((REQUEST) == HAL_DMA1_CH5_USART2_RX) ||\
((REQUEST) == HAL_DMA1_CH5_USART3_RX) ||\
((REQUEST) == HAL_DMA1_CH5_USART4_RX) ||\
((REQUEST) == HAL_DMA1_CH5_USART5_RX) ||\
((REQUEST) == HAL_DMA1_CH5_USART6_RX) ||\
((REQUEST) == HAL_DMA1_CH5_USART7_RX) ||\
((REQUEST) == HAL_DMA1_CH5_USART8_RX) ||\
((REQUEST) == HAL_DMA1_CH6_DEFAULT) ||\
((REQUEST) == HAL_DMA1_CH6_I2C1_TX) ||\
((REQUEST) == HAL_DMA1_CH6_SPI2_RX) ||\
((REQUEST) == HAL_DMA1_CH6_TIM1_CH1) ||\
((REQUEST) == HAL_DMA1_CH6_TIM1_CH2) ||\
((REQUEST) == HAL_DMA1_CH6_TIM1_CH3) ||\
((REQUEST) == HAL_DMA1_CH6_TIM3_CH1) ||\
((REQUEST) == HAL_DMA1_CH6_TIM3_TRIG) ||\
((REQUEST) == HAL_DMA1_CH6_TIM16_CH1) ||\
((REQUEST) == HAL_DMA1_CH6_TIM16_UP) ||\
((REQUEST) == HAL_DMA1_CH6_USART1_RX) ||\
((REQUEST) == HAL_DMA1_CH6_USART2_RX) ||\
((REQUEST) == HAL_DMA1_CH6_USART3_RX) ||\
((REQUEST) == HAL_DMA1_CH6_USART4_RX) ||\
((REQUEST) == HAL_DMA1_CH6_USART5_RX) ||\
((REQUEST) == HAL_DMA1_CH6_USART6_RX) ||\
((REQUEST) == HAL_DMA1_CH6_USART7_RX) ||\
((REQUEST) == HAL_DMA1_CH6_USART8_RX) ||\
((REQUEST) == HAL_DMA1_CH7_DEFAULT) ||\
((REQUEST) == HAL_DMA1_CH7_I2C1_RX) ||\
((REQUEST) == HAL_DMA1_CH7_SPI2_TX) ||\
((REQUEST) == HAL_DMA1_CH7_TIM2_CH2) ||\
((REQUEST) == HAL_DMA1_CH7_TIM2_CH4) ||\
((REQUEST) == HAL_DMA1_CH7_TIM17_CH1) ||\
((REQUEST) == HAL_DMA1_CH7_TIM17_UP) ||\
((REQUEST) == HAL_DMA1_CH7_USART1_TX) ||\
((REQUEST) == HAL_DMA1_CH7_USART2_TX) ||\
((REQUEST) == HAL_DMA1_CH7_USART3_TX) ||\
((REQUEST) == HAL_DMA1_CH7_USART4_TX) ||\
((REQUEST) == HAL_DMA1_CH7_USART5_TX) ||\
((REQUEST) == HAL_DMA1_CH7_USART6_TX) ||\
((REQUEST) == HAL_DMA1_CH7_USART7_TX) ||\
((REQUEST) == HAL_DMA1_CH7_USART8_TX))

#define IS_HAL_DMA2_REMAP(REQUEST) (((REQUEST) == HAL_DMA2_CH1_DEFAULT) ||\
((REQUEST) == HAL_DMA2_CH1_I2C2_TX) ||\
((REQUEST) == HAL_DMA2_CH1_USART1_TX) ||\
((REQUEST) == HAL_DMA2_CH1_USART2_TX) ||\
((REQUEST) == HAL_DMA2_CH1_USART3_TX) ||\
((REQUEST) == HAL_DMA2_CH1_USART4_TX) ||\
((REQUEST) == HAL_DMA2_CH1_USART5_TX) ||\
((REQUEST) == HAL_DMA2_CH1_USART6_TX) ||\
((REQUEST) == HAL_DMA2_CH1_USART7_TX) ||\
((REQUEST) == HAL_DMA2_CH1_USART8_TX) ||\
((REQUEST) == HAL_DMA2_CH2_DEFAULT) ||\
((REQUEST) == HAL_DMA2_CH2_I2C2_RX) ||\
((REQUEST) == HAL_DMA2_CH2_USART1_RX) ||\
((REQUEST) == HAL_DMA2_CH2_USART2_RX) ||\
((REQUEST) == HAL_DMA2_CH2_USART3_RX) ||\
((REQUEST) == HAL_DMA2_CH2_USART4_RX) ||\
((REQUEST) == HAL_DMA2_CH2_USART5_RX) ||\
((REQUEST) == HAL_DMA2_CH2_USART6_RX) ||\
((REQUEST) == HAL_DMA2_CH2_USART7_RX) ||\
((REQUEST) == HAL_DMA2_CH2_USART8_RX) ||\
((REQUEST) == HAL_DMA2_CH3_DEFAULT) ||\
((REQUEST) == HAL_DMA2_CH3_TIM6_UP) ||\
((REQUEST) == HAL_DMA2_CH3_DAC_CH1) ||\
((REQUEST) == HAL_DMA2_CH3_SPI1_RX) ||\
((REQUEST) == HAL_DMA2_CH3_USART1_RX) ||\
((REQUEST) == HAL_DMA2_CH3_USART2_RX) ||\
((REQUEST) == HAL_DMA2_CH3_USART3_RX) ||\
((REQUEST) == HAL_DMA2_CH3_USART4_RX) ||\
((REQUEST) == HAL_DMA2_CH3_USART5_RX) ||\
((REQUEST) == HAL_DMA2_CH3_USART6_RX) ||\
((REQUEST) == HAL_DMA2_CH3_USART7_RX) ||\
((REQUEST) == HAL_DMA2_CH3_USART8_RX) ||\
((REQUEST) == HAL_DMA2_CH4_DEFAULT) ||\
((REQUEST) == HAL_DMA2_CH4_TIM7_UP) ||\
((REQUEST) == HAL_DMA2_CH4_DAC_CH2) ||\
((REQUEST) == HAL_DMA2_CH4_SPI1_TX) ||\
((REQUEST) == HAL_DMA2_CH4_USART1_TX) ||\
((REQUEST) == HAL_DMA2_CH4_USART2_TX) ||\
((REQUEST) == HAL_DMA2_CH4_USART3_TX) ||\
((REQUEST) == HAL_DMA2_CH4_USART4_TX) ||\
((REQUEST) == HAL_DMA2_CH4_USART5_TX) ||\
((REQUEST) == HAL_DMA2_CH4_USART6_TX) ||\
((REQUEST) == HAL_DMA2_CH4_USART7_TX) ||\
((REQUEST) == HAL_DMA2_CH4_USART8_TX) ||\
((REQUEST) == HAL_DMA2_CH5_DEFAULT) ||\
((REQUEST) == HAL_DMA2_CH5_ADC) ||\
((REQUEST) == HAL_DMA2_CH5_USART1_TX) ||\
((REQUEST) == HAL_DMA2_CH5_USART2_TX) ||\
((REQUEST) == HAL_DMA2_CH5_USART3_TX) ||\
((REQUEST) == HAL_DMA2_CH5_USART4_TX) ||\
((REQUEST) == HAL_DMA2_CH5_USART5_TX) ||\
((REQUEST) == HAL_DMA2_CH5_USART6_TX) ||\
((REQUEST) == HAL_DMA2_CH5_USART7_TX) ||\
((REQUEST) == HAL_DMA2_CH5_USART8_TX ))
#endif /* STM32F091xC || STM32F098xx */

#if defined(STM32F030xC)
#define IS_HAL_DMA1_REMAP(REQUEST) (((REQUEST) == HAL_DMA1_CH1_DEFAULT) ||\
((REQUEST) == HAL_DMA1_CH1_ADC) ||\
((REQUEST) == HAL_DMA1_CH1_TIM17_CH1) ||\
((REQUEST) == HAL_DMA1_CH1_TIM17_UP) ||\
((REQUEST) == HAL_DMA1_CH1_USART1_RX) ||\
((REQUEST) == HAL_DMA1_CH1_USART2_RX) ||\
((REQUEST) == HAL_DMA1_CH1_USART3_RX) ||\
((REQUEST) == HAL_DMA1_CH1_USART4_RX) ||\
((REQUEST) == HAL_DMA1_CH1_USART5_RX) ||\
((REQUEST) == HAL_DMA1_CH1_USART6_RX) ||\
((REQUEST) == HAL_DMA1_CH2_DEFAULT) ||\
((REQUEST) == HAL_DMA1_CH2_ADC) ||\
((REQUEST) == HAL_DMA1_CH2_I2C1_TX) ||\
((REQUEST) == HAL_DMA1_CH2_SPI1_RX) ||\
((REQUEST) == HAL_DMA1_CH2_TIM1_CH1) ||\
((REQUEST) == HAL_DMA1_CH2_I2C1_TX) ||\
((REQUEST) == HAL_DMA1_CH2_TIM17_CH1) ||\
((REQUEST) == HAL_DMA1_CH2_TIM17_UP) ||\
((REQUEST) == HAL_DMA1_CH2_USART1_TX) ||\
((REQUEST) == HAL_DMA1_CH2_USART2_TX) ||\
((REQUEST) == HAL_DMA1_CH2_USART3_TX) ||\
((REQUEST) == HAL_DMA1_CH2_USART4_TX) ||\
((REQUEST) == HAL_DMA1_CH2_USART5_TX) ||\
((REQUEST) == HAL_DMA1_CH2_USART6_TX) ||\
((REQUEST) == HAL_DMA1_CH3_DEFAULT) ||\
((REQUEST) == HAL_DMA1_CH3_TIM6_UP) ||\
((REQUEST) == HAL_DMA1_CH3_I2C1_RX) ||\
((REQUEST) == HAL_DMA1_CH3_SPI1_TX) ||\
((REQUEST) == HAL_DMA1_CH3_TIM1_CH2) ||\
((REQUEST) == HAL_DMA1_CH3_TIM16_CH1) ||\
((REQUEST) == HAL_DMA1_CH3_TIM16_UP) ||\
((REQUEST) == HAL_DMA1_CH3_USART1_RX) ||\
((REQUEST) == HAL_DMA1_CH3_USART2_RX) ||\
((REQUEST) == HAL_DMA1_CH3_USART3_RX) ||\
((REQUEST) == HAL_DMA1_CH3_USART4_RX) ||\
((REQUEST) == HAL_DMA1_CH3_USART5_RX) ||\
((REQUEST) == HAL_DMA1_CH3_USART6_RX) ||\
((REQUEST) == HAL_DMA1_CH4_DEFAULT) ||\
((REQUEST) == HAL_DMA1_CH4_TIM7_UP) ||\
((REQUEST) == HAL_DMA1_CH4_I2C2_TX) ||\
((REQUEST) == HAL_DMA1_CH4_SPI2_RX) ||\
((REQUEST) == HAL_DMA1_CH4_TIM3_CH1) ||\
((REQUEST) == HAL_DMA1_CH4_TIM3_TRIG) ||\
((REQUEST) == HAL_DMA1_CH4_TIM16_CH1) ||\
((REQUEST) == HAL_DMA1_CH4_TIM16_UP) ||\
((REQUEST) == HAL_DMA1_CH4_USART1_TX) ||\
((REQUEST) == HAL_DMA1_CH4_USART2_TX) ||\
((REQUEST) == HAL_DMA1_CH4_USART3_TX) ||\
((REQUEST) == HAL_DMA1_CH4_USART4_TX) ||\
((REQUEST) == HAL_DMA1_CH4_USART5_TX) ||\
((REQUEST) == HAL_DMA1_CH4_USART6_TX) ||\
((REQUEST) == HAL_DMA1_CH5_DEFAULT) ||\
((REQUEST) == HAL_DMA1_CH5_I2C2_RX) ||\
((REQUEST) == HAL_DMA1_CH5_SPI2_TX) ||\
((REQUEST) == HAL_DMA1_CH5_TIM1_CH3) ||\
((REQUEST) == HAL_DMA1_CH5_USART1_RX) ||\
((REQUEST) == HAL_DMA1_CH5_USART2_RX) ||\
((REQUEST) == HAL_DMA1_CH5_USART3_RX) ||\
((REQUEST) == HAL_DMA1_CH5_USART4_RX) ||\
((REQUEST) == HAL_DMA1_CH5_USART5_RX) ||\
((REQUEST) == HAL_DMA1_CH5_USART6_RX))
#endif /* STM32F030xC */

/**
* @}
*/
#endif /* STM32F091xC || STM32F098xx || STM32F030xC */

/* Exported macros -----------------------------------------------------------*/

/** @defgroup DMAEx_Exported_Macros DMAEx Exported Macros
* @{
*/
/* Interrupt & Flag management */

#if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
/**
* @brief Returns the current DMA Channel transfer complete flag.
* @param __HANDLE__ DMA handle
* @retval The specified transfer complete flag index.
*/
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
DMA_FLAG_TC7)

/**
* @brief Returns the current DMA Channel half transfer complete flag.
* @param __HANDLE__ DMA handle
* @retval The specified half transfer complete flag index.
*/
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
DMA_FLAG_HT7)

/**
* @brief Returns the current DMA Channel transfer error flag.
* @param __HANDLE__ DMA handle
* @retval The specified transfer error flag index.
*/
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
DMA_FLAG_TE7)

/**
* @brief Return the current DMA Channel Global interrupt flag.
* @param __HANDLE__ DMA handle
* @retval The specified transfer error flag index.
*/
#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\
((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\
((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\
((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\
((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\
((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\
DMA_FLAG_GL7)

/**
* @brief Get the DMA Channel pending flags.
* @param __HANDLE__ DMA handle
* @param __FLAG__ Get the specified flag.
* This parameter can be any combination of the following values:
* @arg DMA_FLAG_TCx: Transfer complete flag
* @arg DMA_FLAG_HTx: Half transfer complete flag
* @arg DMA_FLAG_TEx: Transfer error flag
* Where x can be 1_7 to select the DMA Channel flag.
* @retval The state of FLAG (SET or RESET).
*/

#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1- & gt; ISR & (__FLAG__))

/**
* @brief Clears the DMA Channel pending flags.
* @param __HANDLE__ DMA handle
* @param __FLAG__ specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg DMA_FLAG_TCx: Transfer complete flag
* @arg DMA_FLAG_HTx: Half transfer complete flag
* @arg DMA_FLAG_TEx: Transfer error flag
* Where x can be 1_7 to select the DMA Channel flag.
* @retval None
*/
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1- & gt; IFCR = (__FLAG__))

#elif defined(STM32F091xC) || defined(STM32F098xx)
/**
* @brief Returns the current DMA Channel transfer complete flag.
* @param __HANDLE__ DMA handle
* @retval The specified transfer complete flag index.
*/
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\
((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
DMA_FLAG_TC5)

/**
* @brief Returns the current DMA Channel half transfer complete flag.
* @param __HANDLE__ DMA handle
* @retval The specified half transfer complete flag index.
*/
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\
((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
DMA_FLAG_HT5)

/**
* @brief Returns the current DMA Channel transfer error flag.
* @param __HANDLE__ DMA handle
* @retval The specified transfer error flag index.
*/
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\
((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
DMA_FLAG_TE5)

/**
* @brief Return the current DMA Channel Global interrupt flag.
* @param __HANDLE__ DMA handle
* @retval The specified transfer error flag index.
*/
#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\
((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\
((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\
((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\
((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\
((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\
((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_GL7 :\
((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_GL1 :\
((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_GL2 :\
((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_GL3 :\
((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_GL4 :\
DMA_FLAG_GL5)

/**
* @brief Get the DMA Channel pending flags.
* @param __HANDLE__ DMA handle
* @param __FLAG__ Get the specified flag.
* This parameter can be any combination of the following values:
* @arg DMA_FLAG_TCx: Transfer complete flag
* @arg DMA_FLAG_HTx: Half transfer complete flag
* @arg DMA_FLAG_TEx: Transfer error flag
* Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag.
* @retval The state of FLAG (SET or RESET).
*/

#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
(((uint32_t)((__HANDLE__)- & gt; Instance) & gt; (uint32_t)DMA1_Channel7)? (DMA2- & gt; ISR & (__FLAG__)) :\
(DMA1- & gt; ISR & (__FLAG__)))

/**
* @brief Clears the DMA Channel pending flags.
* @param __HANDLE__ DMA handle
* @param __FLAG__ specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg DMA_FLAG_TCx: Transfer complete flag
* @arg DMA_FLAG_HTx: Half transfer complete flag
* @arg DMA_FLAG_TEx: Transfer error flag
* Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag.
* @retval None
*/
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
(((uint32_t)((__HANDLE__)- & gt; Instance) & gt; (uint32_t)DMA1_Channel7)? (DMA2- & gt; IFCR = (__FLAG__)) :\
(DMA1- & gt; IFCR = (__FLAG__)))

#else /* STM32F030x8_STM32F030xC_STM32F031x6_STM32F038xx_STM32F051x8_STM32F058xx_STM32F070x6_STM32F070xB Product devices */
/**
* @brief Returns the current DMA Channel transfer complete flag.
* @param __HANDLE__ DMA handle
* @retval The specified transfer complete flag index.
*/
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
DMA_FLAG_TC5)

/**
* @brief Returns the current DMA Channel half transfer complete flag.
* @param __HANDLE__ DMA handle
* @retval The specified half transfer complete flag index.
*/
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
DMA_FLAG_HT5)

/**
* @brief Returns the current DMA Channel transfer error flag.
* @param __HANDLE__ DMA handle
* @retval The specified transfer error flag index.
*/
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
DMA_FLAG_TE5)

/**
* @brief Return the current DMA Channel Global interrupt flag.
* @param __HANDLE__ DMA handle
* @retval The specified transfer error flag index.
*/
#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\
((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\
((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\
((uint32_t)((__HANDLE__)- & gt; Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\
DMA_FLAG_GL5)

/**
* @brief Get the DMA Channel pending flags.
* @param __HANDLE__ DMA handle
* @param __FLAG__ Get the specified flag.
* This parameter can be any combination of the following values:
* @arg DMA_FLAG_TCx: Transfer complete flag
* @arg DMA_FLAG_HTx: Half transfer complete flag
* @arg DMA_FLAG_TEx: Transfer error flag
* Where x can be 1_5 to select the DMA Channel flag.
* @retval The state of FLAG (SET or RESET).
*/

#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1- & gt; ISR & (__FLAG__))

/**
* @brief Clears the DMA Channel pending flags.
* @param __HANDLE__ DMA handle
* @param __FLAG__ specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg DMA_FLAG_TCx: Transfer complete flag
* @arg DMA_FLAG_HTx: Half transfer complete flag
* @arg DMA_FLAG_TEx: Transfer error flag
* Where x can be 1_5 to select the DMA Channel flag.
* @retval None
*/
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1- & gt; IFCR = (__FLAG__))

#endif


#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
#define __HAL_DMA1_REMAP(__REQUEST__) \
do { assert_param(IS_HAL_DMA1_REMAP(__REQUEST__)); \
DMA1- & gt; CSELR & = ~(0x0FU & lt; & lt; (uint32_t)(((__REQUEST__) & gt; & gt; 28U) * 4U)); \
DMA1- & gt; CSELR |= (uint32_t)((__REQUEST__) & 0x0FFFFFFFU); \
}while(0)

#if defined(STM32F091xC) || defined(STM32F098xx)
#define __HAL_DMA2_REMAP(__REQUEST__) \
do { assert_param(IS_HAL_DMA2_REMAP(__REQUEST__)); \
DMA2- & gt; CSELR & = ~(0x0FU & lt; & lt; (uint32_t)(((__REQUEST__) & gt; & gt; 28U) * 4U)); \
DMA2- & gt; CSELR |= (uint32_t)((__REQUEST__) & 0x0FFFFFFFU); \
}while(0)
#endif /* STM32F091xC || STM32F098xx */

#endif /* STM32F091xC || STM32F098xx || STM32F030xC */

/**
* @}
*/

/**
* @}
*/

/**
* @}
*/

#ifdef __cplusplus
}
#endif

#endif /* __STM32F0xx_HAL_DMA_EX_H */

/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

ssr_test.zip > stm32f0xx_hal_i2c.h

/**
******************************************************************************
* @file stm32f0xx_hal_i2c.h
* @author MCD Application Team
* @brief Header file of I2C HAL module.
******************************************************************************
* @attention
*
* & lt; h2 & gt; & lt; center & gt; & copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved. & lt; /center & gt; & lt; /h2 & gt;
*
* This software component is licensed by ST under BSD 3-Clause license,
* the " License " ; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/

/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F0xx_HAL_I2C_H
#define STM32F0xx_HAL_I2C_H

#ifdef __cplusplus
extern " C " {
#endif

/* Includes ------------------------------------------------------------------*/
#include " stm32f0xx_hal_def.h "

/** @addtogroup STM32F0xx_HAL_Driver
* @{
*/

/** @addtogroup I2C
* @{
*/

/* Exported types ------------------------------------------------------------*/
/** @defgroup I2C_Exported_Types I2C Exported Types
* @{
*/

/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
* @brief I2C Configuration Structure definition
* @{
*/
typedef struct
{
uint32_t Timing; /*! & lt; Specifies the I2C_TIMINGR_register value.
This parameter calculated by referring to I2C initialization
section in Reference manual */

uint32_t OwnAddress1; /*! & lt; Specifies the first device own address.
This parameter can be a 7-bit or 10-bit address. */

uint32_t AddressingMode; /*! & lt; Specifies if 7-bit or 10-bit addressing mode is selected.
This parameter can be a value of @ref I2C_ADDRESSING_MODE */

uint32_t DualAddressMode; /*! & lt; Specifies if dual addressing mode is selected.
This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */

uint32_t OwnAddress2; /*! & lt; Specifies the second device own address if dual addressing mode is selected
This parameter can be a 7-bit address. */

uint32_t OwnAddress2Masks; /*! & lt; Specifies the acknowledge mask address second device own address if dual addressing mode is selected
This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */

uint32_t GeneralCallMode; /*! & lt; Specifies if general call mode is selected.
This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */

uint32_t NoStretchMode; /*! & lt; Specifies if nostretch mode is selected.
This parameter can be a value of @ref I2C_NOSTRETCH_MODE */

} I2C_InitTypeDef;

/**
* @}
*/

/** @defgroup HAL_state_structure_definition HAL state structure definition
* @brief HAL State structure definition
* @note HAL I2C State value coding follow below described bitmap :\n
* b7-b6 Error information\n
* 00 : No Error\n
* 01 : Abort (Abort user request on going)\n
* 10 : Timeout\n
* 11 : Error\n
* b5 Peripheral initialization status\n
* 0 : Reset (peripheral not initialized)\n
* 1 : Init done (peripheral initialized and ready to use. HAL I2C Init function called)\n
* b4 (not used)\n
* x : Should be set to 0\n
* b3\n
* 0 : Ready or Busy (No Listen mode ongoing)\n
* 1 : Listen (peripheral in Address Listen Mode)\n
* b2 Intrinsic process state\n
* 0 : Ready\n
* 1 : Busy (peripheral busy with some configuration or internal operations)\n
* b1 Rx state\n
* 0 : Ready (no Rx operation ongoing)\n
* 1 : Busy (Rx operation ongoing)\n
* b0 Tx state\n
* 0 : Ready (no Tx operation ongoing)\n
* 1 : Busy (Tx operation ongoing)
* @{
*/
typedef enum
{
HAL_I2C_STATE_RESET = 0x00U, /*! & lt; Peripheral is not yet Initialized */
HAL_I2C_STATE_READY = 0x20U, /*! & lt; Peripheral Initialized and ready for use */
HAL_I2C_STATE_BUSY = 0x24U, /*! & lt; An internal process is ongoing */
HAL_I2C_STATE_BUSY_TX = 0x21U, /*! & lt; Data Transmission process is ongoing */
HAL_I2C_STATE_BUSY_RX = 0x22U, /*! & lt; Data Reception process is ongoing */
HAL_I2C_STATE_LISTEN = 0x28U, /*! & lt; Address Listen Mode is ongoing */
HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*! & lt; Address Listen Mode and Data Transmission
process is ongoing */
HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*! & lt; Address Listen Mode and Data Reception
process is ongoing */
HAL_I2C_STATE_ABORT = 0x60U, /*! & lt; Abort user request ongoing */
HAL_I2C_STATE_TIMEOUT = 0xA0U, /*! & lt; Timeout state */
HAL_I2C_STATE_ERROR = 0xE0U /*! & lt; Error */

} HAL_I2C_StateTypeDef;

/**
* @}
*/

/** @defgroup HAL_mode_structure_definition HAL mode structure definition
* @brief HAL Mode structure definition
* @note HAL I2C Mode value coding follow below described bitmap :\n
* b7 (not used)\n
* x : Should be set to 0\n
* b6\n
* 0 : None\n
* 1 : Memory (HAL I2C communication is in Memory Mode)\n
* b5\n
* 0 : None\n
* 1 : Slave (HAL I2C communication is in Slave Mode)\n
* b4\n
* 0 : None\n
* 1 : Master (HAL I2C communication is in Master Mode)\n
* b3-b2-b1-b0 (not used)\n
* xxxx : Should be set to 0000
* @{
*/
typedef enum
{
HAL_I2C_MODE_NONE = 0x00U, /*! & lt; No I2C communication on going */
HAL_I2C_MODE_MASTER = 0x10U, /*! & lt; I2C communication is in Master Mode */
HAL_I2C_MODE_SLAVE = 0x20U, /*! & lt; I2C communication is in Slave Mode */
HAL_I2C_MODE_MEM = 0x40U /*! & lt; I2C communication is in Memory Mode */

} HAL_I2C_ModeTypeDef;

/**
* @}
*/

/** @defgroup I2C_Error_Code_definition I2C Error Code definition
* @brief I2C Error Code definition
* @{
*/
#define HAL_I2C_ERROR_NONE (0x00000000U) /*! & lt; No error */
#define HAL_I2C_ERROR_BERR (0x00000001U) /*! & lt; BERR error */
#define HAL_I2C_ERROR_ARLO (0x00000002U) /*! & lt; ARLO error */
#define HAL_I2C_ERROR_AF (0x00000004U) /*! & lt; ACKF error */
#define HAL_I2C_ERROR_OVR (0x00000008U) /*! & lt; OVR error */
#define HAL_I2C_ERROR_DMA (0x00000010U) /*! & lt; DMA transfer error */
#define HAL_I2C_ERROR_TIMEOUT (0x00000020U) /*! & lt; Timeout error */
#define HAL_I2C_ERROR_SIZE (0x00000040U) /*! & lt; Size Management error */
#define HAL_I2C_ERROR_DMA_PARAM (0x00000080U) /*! & lt; DMA Parameter Error */
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
#define HAL_I2C_ERROR_INVALID_CALLBACK (0x00000100U) /*! & lt; Invalid Callback error */
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
#define HAL_I2C_ERROR_INVALID_PARAM (0x00000200U) /*! & lt; Invalid Parameters error */
/**
* @}
*/

/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
* @brief I2C handle Structure definition
* @{
*/
typedef struct __I2C_HandleTypeDef
{
I2C_TypeDef *Instance; /*! & lt; I2C registers base address */

I2C_InitTypeDef Init; /*! & lt; I2C communication parameters */

uint8_t *pBuffPtr; /*! & lt; Pointer to I2C transfer buffer */

uint16_t XferSize; /*! & lt; I2C transfer size */

__IO uint16_t XferCount; /*! & lt; I2C transfer counter */

__IO uint32_t XferOptions; /*! & lt; I2C sequantial transfer options, this parameter can
be a value of @ref I2C_XFEROPTIONS */

__IO uint32_t PreviousState; /*! & lt; I2C communication Previous state */

HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); /*! & lt; I2C transfer IRQ handler function pointer */

DMA_HandleTypeDef *hdmatx; /*! & lt; I2C Tx DMA handle parameters */

DMA_HandleTypeDef *hdmarx; /*! & lt; I2C Rx DMA handle parameters */

HAL_LockTypeDef Lock; /*! & lt; I2C locking object */

__IO HAL_I2C_StateTypeDef State; /*! & lt; I2C communication state */

__IO HAL_I2C_ModeTypeDef Mode; /*! & lt; I2C communication mode */

__IO uint32_t ErrorCode; /*! & lt; I2C Error code */

__IO uint32_t AddrEventCount; /*! & lt; I2C Address Event counter */

#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*! & lt; I2C Master Tx Transfer completed callback */
void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*! & lt; I2C Master Rx Transfer completed callback */
void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*! & lt; I2C Slave Tx Transfer completed callback */
void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*! & lt; I2C Slave Rx Transfer completed callback */
void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*! & lt; I2C Listen Complete callback */
void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*! & lt; I2C Memory Tx Transfer completed callback */
void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*! & lt; I2C Memory Rx Transfer completed callback */
void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c); /*! & lt; I2C Error callback */
void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c); /*! & lt; I2C Abort callback */

void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*! & lt; I2C Slave Address Match callback */

void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*! & lt; I2C Msp Init callback */
void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c); /*! & lt; I2C Msp DeInit callback */

#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
} I2C_HandleTypeDef;

#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
/**
* @brief HAL I2C Callback ID enumeration definition
*/
typedef enum
{
HAL_I2C_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*! & lt; I2C Master Tx Transfer completed callback ID */
HAL_I2C_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*! & lt; I2C Master Rx Transfer completed callback ID */
HAL_I2C_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*! & lt; I2C Slave Tx Transfer completed callback ID */
HAL_I2C_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*! & lt; I2C Slave Rx Transfer completed callback ID */
HAL_I2C_LISTEN_COMPLETE_CB_ID = 0x04U, /*! & lt; I2C Listen Complete callback ID */
HAL_I2C_MEM_TX_COMPLETE_CB_ID = 0x05U, /*! & lt; I2C Memory Tx Transfer callback ID */
HAL_I2C_MEM_RX_COMPLETE_CB_ID = 0x06U, /*! & lt; I2C Memory Rx Transfer completed callback ID */
HAL_I2C_ERROR_CB_ID = 0x07U, /*! & lt; I2C Error callback ID */
HAL_I2C_ABORT_CB_ID = 0x08U, /*! & lt; I2C Abort callback ID */

HAL_I2C_MSPINIT_CB_ID = 0x09U, /*! & lt; I2C Msp Init callback ID */
HAL_I2C_MSPDEINIT_CB_ID = 0x0AU /*! & lt; I2C Msp DeInit callback ID */

} HAL_I2C_CallbackIDTypeDef;

/**
* @brief HAL I2C Callback pointer definition
*/
typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c); /*! & lt; pointer to an I2C callback function */
typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*! & lt; pointer to an I2C Address Match callback function */

#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
/**
* @}
*/

/**
* @}
*/
/* Exported constants --------------------------------------------------------*/

/** @defgroup I2C_Exported_Constants I2C Exported Constants
* @{
*/

/** @defgroup I2C_XFEROPTIONS I2C Sequential Transfer Options
* @{
*/
#define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE)
#define I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
#define I2C_LAST_FRAME_NO_STOP ((uint32_t)I2C_SOFTEND_MODE)

/* List of XferOptions in usage of :
* 1- Restart condition in all use cases (direction change or not)
*/
#define I2C_OTHER_FRAME (0x000000AAU)
#define I2C_OTHER_AND_LAST_FRAME (0x0000AA00U)
/**
* @}
*/

/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode
* @{
*/
#define I2C_ADDRESSINGMODE_7BIT (0x00000001U)
#define I2C_ADDRESSINGMODE_10BIT (0x00000002U)
/**
* @}
*/

/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode
* @{
*/
#define I2C_DUALADDRESS_DISABLE (0x00000000U)
#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
/**
* @}
*/

/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks
* @{
*/
#define I2C_OA2_NOMASK ((uint8_t)0x00U)
#define I2C_OA2_MASK01 ((uint8_t)0x01U)
#define I2C_OA2_MASK02 ((uint8_t)0x02U)
#define I2C_OA2_MASK03 ((uint8_t)0x03U)
#define I2C_OA2_MASK04 ((uint8_t)0x04U)
#define I2C_OA2_MASK05 ((uint8_t)0x05U)
#define I2C_OA2_MASK06 ((uint8_t)0x06U)
#define I2C_OA2_MASK07 ((uint8_t)0x07U)
/**
* @}
*/

/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode
* @{
*/
#define I2C_GENERALCALL_DISABLE (0x00000000U)
#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN
/**
* @}
*/

/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode
* @{
*/
#define I2C_NOSTRETCH_DISABLE (0x00000000U)
#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
/**
* @}
*/

/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size
* @{
*/
#define I2C_MEMADD_SIZE_8BIT (0x00000001U)
#define I2C_MEMADD_SIZE_16BIT (0x00000002U)
/**
* @}
*/

/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View
* @{
*/
#define I2C_DIRECTION_TRANSMIT (0x00000000U)
#define I2C_DIRECTION_RECEIVE (0x00000001U)
/**
* @}
*/

/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode
* @{
*/
#define I2C_RELOAD_MODE I2C_CR2_RELOAD
#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND
#define I2C_SOFTEND_MODE (0x00000000U)
/**
* @}
*/

/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode
* @{
*/
#define I2C_NO_STARTSTOP (0x00000000U)
#define I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
#define I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
#define I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
/**
* @}
*/

/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
* @brief I2C Interrupt definition
* Elements values convention: 0xXXXXXXXX
* - XXXXXXXX : Interrupt control mask
* @{
*/
#define I2C_IT_ERRI I2C_CR1_ERRIE
#define I2C_IT_TCI I2C_CR1_TCIE
#define I2C_IT_STOPI I2C_CR1_STOPIE
#define I2C_IT_NACKI I2C_CR1_NACKIE
#define I2C_IT_ADDRI I2C_CR1_ADDRIE
#define I2C_IT_RXI I2C_CR1_RXIE
#define I2C_IT_TXI I2C_CR1_TXIE
/**
* @}
*/

/** @defgroup I2C_Flag_definition I2C Flag definition
* @{
*/
#define I2C_FLAG_TXE I2C_ISR_TXE
#define I2C_FLAG_TXIS I2C_ISR_TXIS
#define I2C_FLAG_RXNE I2C_ISR_RXNE
#define I2C_FLAG_ADDR I2C_ISR_ADDR
#define I2C_FLAG_AF I2C_ISR_NACKF
#define I2C_FLAG_STOPF I2C_ISR_STOPF
#define I2C_FLAG_TC I2C_ISR_TC
#define I2C_FLAG_TCR I2C_ISR_TCR
#define I2C_FLAG_BERR I2C_ISR_BERR
#define I2C_FLAG_ARLO I2C_ISR_ARLO
#define I2C_FLAG_OVR I2C_ISR_OVR
#define I2C_FLAG_PECERR I2C_ISR_PECERR
#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT
#define I2C_FLAG_ALERT I2C_ISR_ALERT
#define I2C_FLAG_BUSY I2C_ISR_BUSY
#define I2C_FLAG_DIR I2C_ISR_DIR
/**
* @}
*/

/**
* @}
*/

/* Exported macros -----------------------------------------------------------*/

/** @defgroup I2C_Exported_Macros I2C Exported Macros
* @{
*/

/** @brief Reset I2C handle state.
* @param __HANDLE__ specifies the I2C Handle.
* @retval None
*/
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)- & gt; State = HAL_I2C_STATE_RESET; \
(__HANDLE__)- & gt; MspInitCallback = NULL; \
(__HANDLE__)- & gt; MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)- & gt; State = HAL_I2C_STATE_RESET)
#endif

/** @brief Enable the specified I2C interrupt.
* @param __HANDLE__ specifies the I2C Handle.
* @param __INTERRUPT__ specifies the interrupt source to enable.
* This parameter can be one of the following values:
* @arg @ref I2C_IT_ERRI Errors interrupt enable
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable
* @arg @ref I2C_IT_NACKI NACK received interrupt enable
* @arg @ref I2C_IT_ADDRI Address match interrupt enable
* @arg @ref I2C_IT_RXI RX interrupt enable
* @arg @ref I2C_IT_TXI TX interrupt enable
*
* @retval None
*/
#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)- & gt; Instance- & gt; CR1 |= (__INTERRUPT__))

/** @brief Disable the specified I2C interrupt.
* @param __HANDLE__ specifies the I2C Handle.
* @param __INTERRUPT__ specifies the interrupt source to disable.
* This parameter can be one of the following values:
* @arg @ref I2C_IT_ERRI Errors interrupt enable
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable
* @arg @ref I2C_IT_NACKI NACK received interrupt enable
* @arg @ref I2C_IT_ADDRI Address match interrupt enable
* @arg @ref I2C_IT_RXI RX interrupt enable
* @arg @ref I2C_IT_TXI TX interrupt enable
*
* @retval None
*/
#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)- & gt; Instance- & gt; CR1 & = (~(__INTERRUPT__)))

/** @brief Check whether the specified I2C interrupt source is enabled or not.
* @param __HANDLE__ specifies the I2C Handle.
* @param __INTERRUPT__ specifies the I2C interrupt source to check.
* This parameter can be one of the following values:
* @arg @ref I2C_IT_ERRI Errors interrupt enable
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable
* @arg @ref I2C_IT_NACKI NACK received interrupt enable
* @arg @ref I2C_IT_ADDRI Address match interrupt enable
* @arg @ref I2C_IT_RXI RX interrupt enable
* @arg @ref I2C_IT_TXI TX interrupt enable
*
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)- & gt; Instance- & gt; CR1 & \
(__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

/** @brief Check whether the specified I2C flag is set or not.
* @param __HANDLE__ specifies the I2C Handle.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg @ref I2C_FLAG_TXE Transmit data register empty
* @arg @ref I2C_FLAG_TXIS Transmit interrupt status
* @arg @ref I2C_FLAG_RXNE Receive data register not empty
* @arg @ref I2C_FLAG_ADDR Address matched (slave mode)
* @arg @ref I2C_FLAG_AF Acknowledge failure received flag
* @arg @ref I2C_FLAG_STOPF STOP detection flag
* @arg @ref I2C_FLAG_TC Transfer complete (master mode)
* @arg @ref I2C_FLAG_TCR Transfer complete reload
* @arg @ref I2C_FLAG_BERR Bus error
* @arg @ref I2C_FLAG_ARLO Arbitration lost
* @arg @ref I2C_FLAG_OVR Overrun/Underrun
* @arg @ref I2C_FLAG_PECERR PEC error in reception
* @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
* @arg @ref I2C_FLAG_ALERT SMBus alert
* @arg @ref I2C_FLAG_BUSY Bus busy
* @arg @ref I2C_FLAG_DIR Transfer direction (slave mode)
*
* @retval The new state of __FLAG__ (SET or RESET).
*/
#define I2C_FLAG_MASK (0x0001FFFFU)
#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)- & gt; Instance- & gt; ISR) & \
(__FLAG__)) == (__FLAG__)) ? SET : RESET)

/** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
* @param __HANDLE__ specifies the I2C Handle.
* @param __FLAG__ specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg @ref I2C_FLAG_TXE Transmit data register empty
* @arg @ref I2C_FLAG_ADDR Address matched (slave mode)
* @arg @ref I2C_FLAG_AF Acknowledge failure received flag
* @arg @ref I2C_FLAG_STOPF STOP detection flag
* @arg @ref I2C_FLAG_BERR Bus error
* @arg @ref I2C_FLAG_ARLO Arbitration lost
* @arg @ref I2C_FLAG_OVR Overrun/Underrun
* @arg @ref I2C_FLAG_PECERR PEC error in reception
* @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
* @arg @ref I2C_FLAG_ALERT SMBus alert
*
* @retval None
*/
#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)- & gt; Instance- & gt; ISR |= (__FLAG__)) \
: ((__HANDLE__)- & gt; Instance- & gt; ICR = (__FLAG__)))

/** @brief Enable the specified I2C peripheral.
* @param __HANDLE__ specifies the I2C Handle.
* @retval None
*/
#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)- & gt; Instance- & gt; CR1, I2C_CR1_PE))

/** @brief Disable the specified I2C peripheral.
* @param __HANDLE__ specifies the I2C Handle.
* @retval None
*/
#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)- & gt; Instance- & gt; CR1, I2C_CR1_PE))

/** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode.
* @param __HANDLE__ specifies the I2C Handle.
* @retval None
*/
#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)- & gt; Instance- & gt; CR2, I2C_CR2_NACK))
/**
* @}
*/

/* Include I2C HAL Extended module */
#include " stm32f0xx_hal_i2c_ex.h "

/* Exported functions --------------------------------------------------------*/
/** @addtogroup I2C_Exported_Functions
* @{
*/

/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization and de-initialization functions******************************/
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);

/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID,
pI2C_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID);

HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c);
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
/**
* @}
*/

/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions
* @{
*/
/* IO operation functions ****************************************************/
/******* Blocking mode: Polling */
HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size,
uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size,
uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials,
uint32_t Timeout);

/******* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);

HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);

/******* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);

HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
uint32_t XferOptions);
/**
* @}
*/

/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
* @{
*/
/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
/**
* @}
*/

/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
* @{
*/
/* Peripheral State, Mode and Error functions *********************************/
HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);

/**
* @}
*/

/**
* @}
*/

/* Private constants ---------------------------------------------------------*/
/** @defgroup I2C_Private_Constants I2C Private Constants
* @{
*/

/**
* @}
*/

/* Private macros ------------------------------------------------------------*/
/** @defgroup I2C_Private_Macro I2C Private Macros
* @{
*/

#define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \
((MODE) == I2C_ADDRESSINGMODE_10BIT))

#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
((ADDRESS) == I2C_DUALADDRESS_ENABLE))

#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \
((MASK) == I2C_OA2_MASK01) || \
((MASK) == I2C_OA2_MASK02) || \
((MASK) == I2C_OA2_MASK03) || \
((MASK) == I2C_OA2_MASK04) || \
((MASK) == I2C_OA2_MASK05) || \
((MASK) == I2C_OA2_MASK06) || \
((MASK) == I2C_OA2_MASK07))

#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \
((CALL) == I2C_GENERALCALL_ENABLE))

#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
((STRETCH) == I2C_NOSTRETCH_ENABLE))

#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
((SIZE) == I2C_MEMADD_SIZE_16BIT))

#define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \
((MODE) == I2C_AUTOEND_MODE) || \
((MODE) == I2C_SOFTEND_MODE))

#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \
((REQUEST) == I2C_GENERATE_START_READ) || \
((REQUEST) == I2C_GENERATE_START_WRITE) || \
((REQUEST) == I2C_NO_STARTSTOP))

#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \
((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \
((REQUEST) == I2C_NEXT_FRAME) || \
((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
((REQUEST) == I2C_LAST_FRAME) || \
((REQUEST) == I2C_LAST_FRAME_NO_STOP) || \
IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))

#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME) || \
((REQUEST) == I2C_OTHER_AND_LAST_FRAME))

#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)- & gt; Instance- & gt; CR2 & = \
(uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))

#define I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)- & gt; Instance- & gt; ISR & I2C_ISR_ADDCODE) & gt; & gt; 16U))
#define I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)- & gt; Instance- & gt; ISR & I2C_ISR_DIR) & gt; & gt; 16U))
#define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)- & gt; Instance- & gt; CR2 & I2C_CR2_AUTOEND)
#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)- & gt; Instance- & gt; OAR1 & I2C_OAR1_OA1))
#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)- & gt; Instance- & gt; OAR2 & I2C_OAR2_OA2))

#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) & lt; = 0x000003FFU)
#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) & lt; = (uint16_t)0x00FFU)

#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & \
(uint16_t)(0xFF00U))) & gt; & gt; 8U)))
#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))

#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))

#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \
((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
/**
* @}
*/

/* Private Functions ---------------------------------------------------------*/
/** @defgroup I2C_Private_Functions I2C Private Functions
* @{
*/
/* Private functions are defined in stm32f0xx_hal_i2c.c file */
/**
* @}
*/

/**
* @}
*/

/**
* @}
*/

#ifdef __cplusplus
}
#endif


#endif /* STM32F0xx_HAL_I2C_H */

/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

ssr_test.zip > stm32f0xx_hal.h

/**
******************************************************************************
* @file stm32f0xx_hal.h
* @author MCD Application Team
* @brief This file contains all the functions prototypes for the HAL
* module driver.
******************************************************************************
* @attention
*
* & lt; h2 & gt; & lt; center & gt; & copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved. & lt; /center & gt; & lt; /h2 & gt;
*
* This software component is licensed by ST under BSD 3-Clause license,
* the " License " ; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/

/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F0xx_HAL_H
#define __STM32F0xx_HAL_H

#ifdef __cplusplus
extern " C " {
#endif

/* Includes ------------------------------------------------------------------*/
#include " stm32f0xx_hal_conf.h "

/** @addtogroup STM32F0xx_HAL_Driver
* @{
*/

/** @addtogroup HAL
* @{
*/

/* Private macros ------------------------------------------------------------*/
/** @addtogroup HAL_Private_Macros
* @{
*/
#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F042x6) || defined(STM32F048xx) || \
defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || \
defined(STM32F070xB) || defined(STM32F030x6)
#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PA9) == SYSCFG_FASTMODEPLUS_PA9) || \
(((__PIN__) & SYSCFG_FASTMODEPLUS_PA10) == SYSCFG_FASTMODEPLUS_PA10) || \
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
#else
#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
#endif
#if defined(SYSCFG_CFGR1_PA11_PA12_RMP)
#define IS_HAL_REMAP_PIN(RMP) ((RMP) == HAL_REMAP_PA11_PA12)
#endif /* SYSCFG_CFGR1_PA11_PA12_RMP */
#if defined(STM32F091xC) || defined(STM32F098xx)
#define IS_HAL_SYSCFG_IRDA_ENV_SEL(SEL) (((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_TIM16) || \
((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART1) || \
((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART4))
#endif /* STM32F091xC || STM32F098xx */
/**
* @}
*/

/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup HAL_Exported_Constants HAL Exported Constants
* @{
*/

/** @defgroup HAL_TICK_FREQ Tick Frequency
* @{
*/
typedef enum
{
HAL_TICK_FREQ_10HZ = 100U,
HAL_TICK_FREQ_100HZ = 10U,
HAL_TICK_FREQ_1KHZ = 1U,
HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ
} HAL_TickFreqTypeDef;

/**
* @}
*/

#if defined(SYSCFG_CFGR1_PA11_PA12_RMP)
/** @defgroup HAL_Pin_remapping HAL Pin remapping
* @{
*/
#define HAL_REMAP_PA11_PA12 (SYSCFG_CFGR1_PA11_PA12_RMP) /*! & lt; PA11 and PA12 remapping bit for small packages (28 and 20 pins).
0: No remap (pin pair PA9/10 mapped on the pins)
1: Remap (pin pair PA11/12 mapped instead of PA9/10) */

/**
* @}
*/
#endif /* SYSCFG_CFGR1_PA11_PA12_RMP */

#if defined(STM32F091xC) || defined(STM32F098xx)
/** @defgroup HAL_IRDA_ENV_SEL HAL IRDA Enveloppe Selection
* @note Applicable on STM32F09x
* @{
*/
#define HAL_SYSCFG_IRDA_ENV_SEL_TIM16 (SYSCFG_CFGR1_IRDA_ENV_SEL_0 & SYSCFG_CFGR1_IRDA_ENV_SEL_1) /* 00: Timer16 is selected as IRDA Modulation enveloppe source */
#define HAL_SYSCFG_IRDA_ENV_SEL_USART1 (SYSCFG_CFGR1_IRDA_ENV_SEL_0) /* 01: USART1 is selected as IRDA Modulation enveloppe source */
#define HAL_SYSCFG_IRDA_ENV_SEL_USART4 (SYSCFG_CFGR1_IRDA_ENV_SEL_1) /* 10: USART4 is selected as IRDA Modulation enveloppe source */

/**
* @}
*/
#endif /* STM32F091xC || STM32F098xx */


/** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO
* @{
*/

/** @brief Fast-mode Plus driving capability on a specific GPIO
*/
#if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F042x6) || defined(STM32F048xx) || \
defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || \
defined(STM32F070xB) || defined(STM32F030x6)
#define SYSCFG_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_FMP_PA9 /*! & lt; Enable Fast-mode Plus on PA9 */
#define SYSCFG_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_FMP_PA10 /*! & lt; Enable Fast-mode Plus on PA10 */
#endif
#define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_FMP_PB6 /*! & lt; Enable Fast-mode Plus on PB6 */
#define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_FMP_PB7 /*! & lt; Enable Fast-mode Plus on PB7 */
#define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_FMP_PB8 /*! & lt; Enable Fast-mode Plus on PB8 */
#define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_FMP_PB9 /*! & lt; Enable Fast-mode Plus on PB9 */

/**
* @}
*/


#if defined(STM32F091xC) || defined (STM32F098xx)
/** @defgroup HAL_ISR_Wrapper HAL ISR Wrapper
* @brief ISR Wrapper
* @note applicable on STM32F09x
* @{
*/
#define HAL_SYSCFG_ITLINE0 ( 0x00000000U) /*! & lt; Internal define for macro handling */
#define HAL_SYSCFG_ITLINE1 ( 0x00000001U) /*! & lt; Internal define for macro handling */
#define HAL_SYSCFG_ITLINE2 ( 0x00000002U) /*! & lt; Internal define for macro handling */
#define HAL_SYSCFG_ITLINE3 ( 0x00000003U) /*! & lt; Internal define for macro handling */
#define HAL_SYSCFG_ITLINE4 ( 0x00000004U) /*! & lt; Internal define for macro handling */
#define HAL_SYSCFG_ITLINE5 ( 0x00000005U) /*! & lt; Internal define for macro handling */
#define HAL_SYSCFG_ITLINE6 ( 0x00000006U) /*! & lt; Internal define for macro handling */
#define HAL_SYSCFG_ITLINE7 ( 0x00000007U) /*! & lt; Internal define for macro handling */
#define HAL_SYSCFG_ITLINE8 ( 0x00000008U) /*! & lt; Internal define for macro handling */
#define HAL_SYSCFG_ITLINE9 ( 0x00000009U) /*! & lt; Internal define for macro handling */
#define HAL_SYSCFG_ITLINE10 ( 0x0000000AU) /*! & lt; Internal define for macro handling */
#define HAL_SYSCFG_ITLINE11 ( 0x0000000BU) /*! & lt; Internal define for macro handling */
#define HAL_SYSCFG_ITLINE12 ( 0x0000000CU) /*! & lt; Internal define for macro handling */
#define HAL_SYSCFG_ITLINE13 ( 0x0000000DU) /*! & lt; Internal define for macro handling */
#define HAL_SYSCFG_ITLINE14 ( 0x0000000EU) /*! & lt; Internal define for macro handling */
#define HAL_SYSCFG_ITLINE15 ( 0x0000000FU) /*! & lt; Internal define for macro handling */
#define HAL_SYSCFG_ITLINE16 ( 0x00000010U) /*! & lt; Internal define for macro handling */
#define HAL_SYSCFG_ITLINE17 ( 0x00000011U) /*! & lt; Internal define for macro handling */
#define HAL_SYSCFG_ITLINE18 ( 0x00000012U) /*! & lt; Internal define for macro handling */
#define HAL_SYSCFG_ITLINE19 ( 0x00000013U) /*! & lt; Internal define for macro handling */
#define HAL_SYSCFG_ITLINE20 ( 0x00000014U) /*! & lt; Internal define for macro handling */
#define HAL_SYSCFG_ITLINE21 ( 0x00000015U) /*! & lt; Internal define for macro handling */
#define HAL_SYSCFG_ITLINE22 ( 0x00000016U) /*! & lt; Internal define for macro handling */
#define HAL_SYSCFG_ITLINE23 ( 0x00000017U) /*! & lt; Internal define for macro handling */
#define HAL_SYSCFG_ITLINE24 ( 0x00000018U) /*! & lt; Internal define for macro handling */
#define HAL_SYSCFG_ITLINE25 ( 0x00000019U) /*! & lt; Internal define for macro handling */
#define HAL_SYSCFG_ITLINE26 ( 0x0000001AU) /*! & lt; Internal define for macro handling */
#define HAL_SYSCFG_ITLINE27 ( 0x0000001BU) /*! & lt; Internal define for macro handling */
#define HAL_SYSCFG_ITLINE28 ( 0x0000001CU) /*! & lt; Internal define for macro handling */
#define HAL_SYSCFG_ITLINE29 ( 0x0000001DU) /*! & lt; Internal define for macro handling */
#define HAL_SYSCFG_ITLINE30 ( 0x0000001EU) /*! & lt; Internal define for macro handling */
#define HAL_SYSCFG_ITLINE31 ( 0x0000001FU) /*! & lt; Internal define for macro handling */

#define HAL_ITLINE_EWDG ((uint32_t) ((HAL_SYSCFG_ITLINE0 & lt; & lt; 0x18U) | SYSCFG_ITLINE0_SR_EWDG)) /*! & lt; EWDG has expired .... */
#if defined(STM32F091xC)
#define HAL_ITLINE_PVDOUT ((uint32_t) ((HAL_SYSCFG_ITLINE1 & lt; & lt; 0x18U) | SYSCFG_ITLINE1_SR_PVDOUT)) /*! & lt; Power voltage detection Interrupt .... */
#endif
#define HAL_ITLINE_VDDIO2 ((uint32_t) ((HAL_SYSCFG_ITLINE1 & lt; & lt; 0x18U) | SYSCFG_ITLINE1_SR_VDDIO2)) /*! & lt; VDDIO2 Interrupt .... */
#define HAL_ITLINE_RTC_WAKEUP ((uint32_t) ((HAL_SYSCFG_ITLINE2 & lt; & lt; 0x18U) | SYSCFG_ITLINE2_SR_RTC_WAKEUP)) /*! & lt; RTC WAKEUP - & gt; exti[20] Interrupt */
#define HAL_ITLINE_RTC_TSTAMP ((uint32_t) ((HAL_SYSCFG_ITLINE2 & lt; & lt; 0x18U) | SYSCFG_ITLINE2_SR_RTC_TSTAMP)) /*! & lt; RTC Time Stamp - & gt; exti[19] interrupt */
#define HAL_ITLINE_RTC_ALRA ((uint32_t) ((HAL_SYSCFG_ITLINE2 & lt; & lt; 0x18U) | SYSCFG_ITLINE2_SR_RTC_ALRA)) /*! & lt; RTC Alarm - & gt; exti[17] interrupt .... */
#define HAL_ITLINE_FLASH_ITF ((uint32_t) ((HAL_SYSCFG_ITLINE3 & lt; & lt; 0x18U) | SYSCFG_ITLINE3_SR_FLASH_ITF)) /*! & lt; Flash ITF Interrupt */
#define HAL_ITLINE_CRS ((uint32_t) ((HAL_SYSCFG_ITLINE4 & lt; & lt; 0x18U) | SYSCFG_ITLINE4_SR_CRS)) /*! & lt; CRS Interrupt */
#define HAL_ITLINE_CLK_CTRL ((uint32_t) ((HAL_SYSCFG_ITLINE4 & lt; & lt; 0x18U) | SYSCFG_ITLINE4_SR_CLK_CTRL)) /*! & lt; CLK Control Interrupt */
#define HAL_ITLINE_EXTI0 ((uint32_t) ((HAL_SYSCFG_ITLINE5 & lt; & lt; 0x18U) | SYSCFG_ITLINE5_SR_EXTI0)) /*! & lt; External Interrupt 0 */
#define HAL_ITLINE_EXTI1 ((uint32_t) ((HAL_SYSCFG_ITLINE5 & lt; & lt; 0x18U) | SYSCFG_ITLINE5_SR_EXTI1)) /*! & lt; External Interrupt 1 */
#define HAL_ITLINE_EXTI2 ((uint32_t) ((HAL_SYSCFG_ITLINE6 & lt; & lt; 0x18U) | SYSCFG_ITLINE6_SR_EXTI2)) /*! & lt; External Interrupt 2 */
#define HAL_ITLINE_EXTI3 ((uint32_t) ((HAL_SYSCFG_ITLINE6 & lt; & lt; 0x18U) | SYSCFG_ITLINE6_SR_EXTI3)) /*! & lt; External Interrupt 3 */
#define HAL_ITLINE_EXTI4 ((uint32_t) ((HAL_SYSCFG_ITLINE7 & lt; & lt; 0x18U) | SYSCFG_ITLINE7_SR_EXTI4)) /*! & lt; EXTI4 Interrupt */
#define HAL_ITLINE_EXTI5 ((uint32_t) ((HAL_SYSCFG_ITLINE7 & lt; & lt; 0x18U) | SYSCFG_ITLINE7_SR_EXTI5)) /*! & lt; EXTI5 Interrupt */
#define HAL_ITLINE_EXTI6 ((uint32_t) ((HAL_SYSCFG_ITLINE7 & lt; & lt; 0x18U) | SYSCFG_ITLINE7_SR_EXTI6)) /*! & lt; EXTI6 Interrupt */
#define HAL_ITLINE_EXTI7 ((uint32_t) ((HAL_SYSCFG_ITLINE7 & lt; & lt; 0x18U) | SYSCFG_ITLINE7_SR_EXTI7)) /*! & lt; EXTI7 Interrupt */
#define HAL_ITLINE_EXTI8 ((uint32_t) ((HAL_SYSCFG_ITLINE7 & lt; & lt; 0x18U) | SYSCFG_ITLINE7_SR_EXTI8)) /*! & lt; EXTI8 Interrupt */
#define HAL_ITLINE_EXTI9 ((uint32_t) ((HAL_SYSCFG_ITLINE7 & lt; & lt; 0x18U) | SYSCFG_ITLINE7_SR_EXTI9)) /*! & lt; EXTI9 Interrupt */
#define HAL_ITLINE_EXTI10 ((uint32_t) ((HAL_SYSCFG_ITLINE7 & lt; & lt; 0x18U) | SYSCFG_ITLINE7_SR_EXTI10)) /*! & lt; EXTI10 Interrupt */
#define HAL_ITLINE_EXTI11 ((uint32_t) ((HAL_SYSCFG_ITLINE7 & lt; & lt; 0x18U) | SYSCFG_ITLINE7_SR_EXTI11)) /*! & lt; EXTI11 Interrupt */
#define HAL_ITLINE_EXTI12 ((uint32_t) ((HAL_SYSCFG_ITLINE7 & lt; & lt; 0x18U) | SYSCFG_ITLINE7_SR_EXTI12)) /*! & lt; EXTI12 Interrupt */
#define HAL_ITLINE_EXTI13 ((uint32_t) ((HAL_SYSCFG_ITLINE7 & lt; & lt; 0x18U) | SYSCFG_ITLINE7_SR_EXTI13)) /*! & lt; EXTI13 Interrupt */
#define HAL_ITLINE_EXTI14 ((uint32_t) ((HAL_SYSCFG_ITLINE7 & lt; & lt; 0x18U) | SYSCFG_ITLINE7_SR_EXTI14)) /*! & lt; EXTI14 Interrupt */
#define HAL_ITLINE_EXTI15 ((uint32_t) ((HAL_SYSCFG_ITLINE7 & lt; & lt; 0x18U) | SYSCFG_ITLINE7_SR_EXTI15)) /*! & lt; EXTI15 Interrupt */
#define HAL_ITLINE_TSC_EOA ((uint32_t) ((HAL_SYSCFG_ITLINE8 & lt; & lt; 0x18U) | SYSCFG_ITLINE8_SR_TSC_EOA)) /*! & lt; Touch control EOA Interrupt */
#define HAL_ITLINE_TSC_MCE ((uint32_t) ((HAL_SYSCFG_ITLINE8 & lt; & lt; 0x18U) | SYSCFG_ITLINE8_SR_TSC_MCE)) /*! & lt; Touch control MCE Interrupt */
#define HAL_ITLINE_DMA1_CH1 ((uint32_t) ((HAL_SYSCFG_ITLINE9 & lt; & lt; 0x18U) | SYSCFG_ITLINE9_SR_DMA1_CH1)) /*! & lt; DMA1 Channel 1 Interrupt */
#define HAL_ITLINE_DMA1_CH2 ((uint32_t) ((HAL_SYSCFG_ITLINE10 & lt; & lt; 0x18U) | SYSCFG_ITLINE10_SR_DMA1_CH2)) /*! & lt; DMA1 Channel 2 Interrupt */
#define HAL_ITLINE_DMA1_CH3 ((uint32_t) ((HAL_SYSCFG_ITLINE10 & lt; & lt; 0x18U) | SYSCFG_ITLINE10_SR_DMA1_CH3)) /*! & lt; DMA1 Channel 3 Interrupt */
#define HAL_ITLINE_DMA2_CH1 ((uint32_t) ((HAL_SYSCFG_ITLINE10 & lt; & lt; 0x18U) | SYSCFG_ITLINE10_SR_DMA2_CH1)) /*! & lt; DMA2 Channel 1 Interrupt */
#define HAL_ITLINE_DMA2_CH2 ((uint32_t) ((HAL_SYSCFG_ITLINE10 & lt; & lt; 0x18U) | SYSCFG_ITLINE10_SR_DMA2_CH2)) /*! & lt; DMA2 Channel 2 Interrupt */
#define HAL_ITLINE_DMA1_CH4 ((uint32_t) ((HAL_SYSCFG_ITLINE11 & lt; & lt; 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH4)) /*! & lt; DMA1 Channel 4 Interrupt */
#define HAL_ITLINE_DMA1_CH5 ((uint32_t) ((HAL_SYSCFG_ITLINE11 & lt; & lt; 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH5)) /*! & lt; DMA1 Channel 5 Interrupt */
#define HAL_ITLINE_DMA1_CH6 ((uint32_t) ((HAL_SYSCFG_ITLINE11 & lt; & lt; 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH6)) /*! & lt; DMA1 Channel 6 Interrupt */
#define HAL_ITLINE_DMA1_CH7 ((uint32_t) ((HAL_SYSCFG_ITLINE11 & lt; & lt; 0x18U) | SYSCFG_ITLINE11_SR_DMA1_CH7)) /*! & lt; DMA1 Channel 7 Interrupt */
#define HAL_ITLINE_DMA2_CH3 ((uint32_t) ((HAL_SYSCFG_ITLINE11 & lt; & lt; 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH3)) /*! & lt; DMA2 Channel 3 Interrupt */
#define HAL_ITLINE_DMA2_CH4 ((uint32_t) ((HAL_SYSCFG_ITLINE11 & lt; & lt; 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH4)) /*! & lt; DMA2 Channel 4 Interrupt */
#define HAL_ITLINE_DMA2_CH5 ((uint32_t) ((HAL_SYSCFG_ITLINE11 & lt; & lt; 0x18U) | SYSCFG_ITLINE11_SR_DMA2_CH5)) /*! & lt; DMA2 Channel 5 Interrupt */
#define HAL_ITLINE_ADC ((uint32_t) ((HAL_SYSCFG_ITLINE12 & lt; & lt; 0x18U) | SYSCFG_ITLINE12_SR_ADC)) /*! & lt; ADC Interrupt */
#define HAL_ITLINE_COMP1 ((uint32_t) ((HAL_SYSCFG_ITLINE12 & lt; & lt; 0x18U) | SYSCFG_ITLINE12_SR_COMP1)) /*! & lt; COMP1 Interrupt - & gt; exti[21] */
#define HAL_ITLINE_COMP2 ((uint32_t) ((HAL_SYSCFG_ITLINE12 & lt; & lt; 0x18U) | SYSCFG_ITLINE12_SR_COMP2)) /*! & lt; COMP2 Interrupt - & gt; exti[21] */
#define HAL_ITLINE_TIM1_BRK ((uint32_t) ((HAL_SYSCFG_ITLINE13 & lt; & lt; 0x18U) | SYSCFG_ITLINE13_SR_TIM1_BRK)) /*! & lt; TIM1 BRK Interrupt */
#define HAL_ITLINE_TIM1_UPD ((uint32_t) ((HAL_SYSCFG_ITLINE13 & lt; & lt; 0x18U) | SYSCFG_ITLINE13_SR_TIM1_UPD)) /*! & lt; TIM1 UPD Interrupt */
#define HAL_ITLINE_TIM1_TRG ((uint32_t) ((HAL_SYSCFG_ITLINE13 & lt; & lt; 0x18U) | SYSCFG_ITLINE13_SR_TIM1_TRG)) /*! & lt; TIM1 TRG Interrupt */
#define HAL_ITLINE_TIM1_CCU ((uint32_t) ((HAL_SYSCFG_ITLINE13 & lt; & lt; 0x18U) | SYSCFG_ITLINE13_SR_TIM1_CCU)) /*! & lt; TIM1 CCU Interrupt */
#define HAL_ITLINE_TIM1_CC ((uint32_t) ((HAL_SYSCFG_ITLINE14 & lt; & lt; 0x18U) | SYSCFG_ITLINE14_SR_TIM1_CC)) /*! & lt; TIM1 CC Interrupt */
#define HAL_ITLINE_TIM2 ((uint32_t) ((HAL_SYSCFG_ITLINE15 & lt; & lt; 0x18U) | SYSCFG_ITLINE15_SR_TIM2_GLB)) /*! & lt; TIM2 Interrupt */
#define HAL_ITLINE_TIM3 ((uint32_t) ((HAL_SYSCFG_ITLINE16 & lt; & lt; 0x18U) | SYSCFG_ITLINE16_SR_TIM3_GLB)) /*! & lt; TIM3 Interrupt */
#define HAL_ITLINE_DAC ((uint32_t) ((HAL_SYSCFG_ITLINE17 & lt; & lt; 0x18U) | SYSCFG_ITLINE17_SR_DAC)) /*! & lt; DAC Interrupt */
#define HAL_ITLINE_TIM6 ((uint32_t) ((HAL_SYSCFG_ITLINE17 & lt; & lt; 0x18U) | SYSCFG_ITLINE17_SR_TIM6_GLB)) /*! & lt; TIM6 Interrupt */
#define HAL_ITLINE_TIM7 ((uint32_t) ((HAL_SYSCFG_ITLINE18 & lt; & lt; 0x18U) | SYSCFG_ITLINE18_SR_TIM7_GLB)) /*! & lt; TIM7 Interrupt */
#define HAL_ITLINE_TIM14 ((uint32_t) ((HAL_SYSCFG_ITLINE19 & lt; & lt; 0x18U) | SYSCFG_ITLINE19_SR_TIM14_GLB)) /*! & lt; TIM14 Interrupt */
#define HAL_ITLINE_TIM15 ((uint32_t) ((HAL_SYSCFG_ITLINE20 & lt; & lt; 0x18U) | SYSCFG_ITLINE20_SR_TIM15_GLB)) /*! & lt; TIM15 Interrupt */
#define HAL_ITLINE_TIM16 ((uint32_t) ((HAL_SYSCFG_ITLINE21 & lt; & lt; 0x18U) | SYSCFG_ITLINE21_SR_TIM16_GLB)) /*! & lt; TIM16 Interrupt */
#define HAL_ITLINE_TIM17 ((uint32_t) ((HAL_SYSCFG_ITLINE22 & lt; & lt; 0x18U) | SYSCFG_ITLINE22_SR_TIM17_GLB)) /*! & lt; TIM17 Interrupt */
#define HAL_ITLINE_I2C1 ((uint32_t) ((HAL_SYSCFG_ITLINE23 & lt; & lt; 0x18U) | SYSCFG_ITLINE23_SR_I2C1_GLB)) /*! & lt; I2C1 Interrupt - & gt; exti[23] */
#define HAL_ITLINE_I2C2 ((uint32_t) ((HAL_SYSCFG_ITLINE24 & lt; & lt; 0x18U) | SYSCFG_ITLINE24_SR_I2C2_GLB)) /*! & lt; I2C2 Interrupt */
#define HAL_ITLINE_SPI1 ((uint32_t) ((HAL_SYSCFG_ITLINE25 & lt; & lt; 0x18U) | SYSCFG_ITLINE25_SR_SPI1)) /*! & lt; I2C1 Interrupt - & gt; exti[23] */
#define HAL_ITLINE_SPI2 ((uint32_t) ((HAL_SYSCFG_ITLINE26 & lt; & lt; 0x18U) | SYSCFG_ITLINE26_SR_SPI2)) /*! & lt; SPI1 Interrupt */
#define HAL_ITLINE_USART1 ((uint32_t) ((HAL_SYSCFG_ITLINE27 & lt; & lt; 0x18U) | SYSCFG_ITLINE27_SR_USART1_GLB)) /*! & lt; USART1 GLB Interrupt - & gt; exti[25] */
#define HAL_ITLINE_USART2 ((uint32_t) ((HAL_SYSCFG_ITLINE28 & lt; & lt; 0x18U) | SYSCFG_ITLINE28_SR_USART2_GLB)) /*! & lt; USART2 GLB Interrupt - & gt; exti[26] */
#define HAL_ITLINE_USART3 ((uint32_t) ((HAL_SYSCFG_ITLINE29 & lt; & lt; 0x18U) | SYSCFG_ITLINE29_SR_USART3_GLB)) /*! & lt; USART3 Interrupt .... */
#define HAL_ITLINE_USART4 ((uint32_t) ((HAL_SYSCFG_ITLINE29 & lt; & lt; 0x18U) | SYSCFG_ITLINE29_SR_USART4_GLB)) /*! & lt; USART4 Interrupt .... */
#define HAL_ITLINE_USART5 ((uint32_t) ((HAL_SYSCFG_ITLINE29 & lt; & lt; 0x18U) | SYSCFG_ITLINE29_SR_USART5_GLB)) /*! & lt; USART5 Interrupt .... */
#define HAL_ITLINE_USART6 ((uint32_t) ((HAL_SYSCFG_ITLINE29 & lt; & lt; 0x18U) | SYSCFG_ITLINE29_SR_USART6_GLB)) /*! & lt; USART6 Interrupt .... */
#define HAL_ITLINE_USART7 ((uint32_t) ((HAL_SYSCFG_ITLINE29 & lt; & lt; 0x18U) | SYSCFG_ITLINE29_SR_USART7_GLB)) /*! & lt; USART7 Interrupt .... */
#define HAL_ITLINE_USART8 ((uint32_t) ((HAL_SYSCFG_ITLINE29 & lt; & lt; 0x18U) | SYSCFG_ITLINE29_SR_USART8_GLB)) /*! & lt; USART8 Interrupt .... */
#define HAL_ITLINE_CAN ((uint32_t) ((HAL_SYSCFG_ITLINE30 & lt; & lt; 0x18U) | SYSCFG_ITLINE30_SR_CAN)) /*! & lt; CAN Interrupt */
#define HAL_ITLINE_CEC ((uint32_t) ((HAL_SYSCFG_ITLINE30 & lt; & lt; 0x18U) | SYSCFG_ITLINE30_SR_CEC)) /*! & lt; CEC Interrupt - & gt; exti[27] */
/**
* @}
*/
#endif /* STM32F091xC || STM32F098xx */

/**
* @}
*/

/* Exported macros -----------------------------------------------------------*/
/** @defgroup HAL_Exported_Macros HAL Exported Macros
* @{
*/

/** @defgroup HAL_Freeze_Unfreeze_Peripherals HAL Freeze Unfreeze Peripherals
* @brief Freeze/Unfreeze Peripherals in Debug mode
* @{
*/

#if defined(DBGMCU_APB1_FZ_DBG_CAN_STOP)
#define __HAL_FREEZE_CAN_DBGMCU() (DBGMCU- & gt; APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN_STOP))
#define __HAL_UNFREEZE_CAN_DBGMCU() (DBGMCU- & gt; APB1FZ & = ~(DBGMCU_APB1_FZ_DBG_CAN_STOP))
#endif /* DBGMCU_APB1_FZ_DBG_CAN_STOP */

#if defined(DBGMCU_APB1_FZ_DBG_RTC_STOP)
#define __HAL_DBGMCU_FREEZE_RTC() (DBGMCU- & gt; APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP))
#define __HAL_DBGMCU_UNFREEZE_RTC() (DBGMCU- & gt; APB1FZ & = ~(DBGMCU_APB1_FZ_DBG_RTC_STOP))
#endif /* DBGMCU_APB1_FZ_DBG_RTC_STOP */

#if defined(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)
#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() (DBGMCU- & gt; APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() (DBGMCU- & gt; APB1FZ & = ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
#endif /* DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT */

#if defined(DBGMCU_APB1_FZ_DBG_IWDG_STOP)
#define __HAL_DBGMCU_FREEZE_IWDG() (DBGMCU- & gt; APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP))
#define __HAL_DBGMCU_UNFREEZE_IWDG() (DBGMCU- & gt; APB1FZ & = ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP))
#endif /* DBGMCU_APB1_FZ_DBG_IWDG_STOP */

#if defined(DBGMCU_APB1_FZ_DBG_WWDG_STOP)
#define __HAL_DBGMCU_FREEZE_WWDG() (DBGMCU- & gt; APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP))
#define __HAL_DBGMCU_UNFREEZE_WWDG() (DBGMCU- & gt; APB1FZ & = ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP))
#endif /* DBGMCU_APB1_FZ_DBG_WWDG_STOP */

#if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP)
#define __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU- & gt; APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))
#define __HAL_DBGMCU_UNFREEZE_TIM2() (DBGMCU- & gt; APB1FZ & = ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP))
#endif /* DBGMCU_APB1_FZ_DBG_TIM2_STOP */

#if defined(DBGMCU_APB1_FZ_DBG_TIM3_STOP)
#define __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU- & gt; APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP))
#define __HAL_DBGMCU_UNFREEZE_TIM3() (DBGMCU- & gt; APB1FZ & = ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP))
#endif /* DBGMCU_APB1_FZ_DBG_TIM3_STOP */

#if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP)
#define __HAL_DBGMCU_FREEZE_TIM6() (DBGMCU- & gt; APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP))
#define __HAL_DBGMCU_UNFREEZE_TIM6() (DBGMCU- & gt; APB1FZ & = ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP))
#endif /* DBGMCU_APB1_FZ_DBG_TIM6_STOP */

#if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP)
#define __HAL_DBGMCU_FREEZE_TIM7() (DBGMCU- & gt; APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP))
#define __HAL_DBGMCU_UNFREEZE_TIM7() (DBGMCU- & gt; APB1FZ & = ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP))
#endif /* DBGMCU_APB1_FZ_DBG_TIM7_STOP */

#if defined(DBGMCU_APB1_FZ_DBG_TIM14_STOP)
#define __HAL_DBGMCU_FREEZE_TIM14() (DBGMCU- & gt; APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP))
#define __HAL_DBGMCU_UNFREEZE_TIM14() (DBGMCU- & gt; APB1FZ & = ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP))
#endif /* DBGMCU_APB1_FZ_DBG_TIM14_STOP */

#if defined(DBGMCU_APB2_FZ_DBG_TIM1_STOP)
#define __HAL_DBGMCU_FREEZE_TIM1() (DBGMCU- & gt; APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP))
#define __HAL_DBGMCU_UNFREEZE_TIM1() (DBGMCU- & gt; APB2FZ & = ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP))
#endif /* DBGMCU_APB2_FZ_DBG_TIM1_STOP */

#if defined(DBGMCU_APB2_FZ_DBG_TIM15_STOP)
#define __HAL_DBGMCU_FREEZE_TIM15() (DBGMCU- & gt; APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM15_STOP))
#define __HAL_DBGMCU_UNFREEZE_TIM15() (DBGMCU- & gt; APB2FZ & = ~(DBGMCU_APB2_FZ_DBG_TIM15_STOP))
#endif /* DBGMCU_APB2_FZ_DBG_TIM15_STOP */

#if defined(DBGMCU_APB2_FZ_DBG_TIM16_STOP)
#define __HAL_DBGMCU_FREEZE_TIM16() (DBGMCU- & gt; APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM16_STOP))
#define __HAL_DBGMCU_UNFREEZE_TIM16() (DBGMCU- & gt; APB2FZ & = ~(DBGMCU_APB2_FZ_DBG_TIM16_STOP))
#endif /* DBGMCU_APB2_FZ_DBG_TIM16_STOP */

#if defined(DBGMCU_APB2_FZ_DBG_TIM17_STOP)
#define __HAL_DBGMCU_FREEZE_TIM17() (DBGMCU- & gt; APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM17_STOP))
#define __HAL_DBGMCU_UNFREEZE_TIM17() (DBGMCU- & gt; APB2FZ & = ~(DBGMCU_APB2_FZ_DBG_TIM17_STOP))
#endif /* DBGMCU_APB2_FZ_DBG_TIM17_STOP */

/**
* @}
*/

/** @defgroup Memory_Mapping_Selection Memory Mapping Selection
* @{
*/
#if defined(SYSCFG_CFGR1_MEM_MODE)
/** @brief Main Flash memory mapped at 0x00000000
*/
#define __HAL_SYSCFG_REMAPMEMORY_FLASH() (SYSCFG- & gt; CFGR1 & = ~(SYSCFG_CFGR1_MEM_MODE))
#endif /* SYSCFG_CFGR1_MEM_MODE */

#if defined(SYSCFG_CFGR1_MEM_MODE_0)
/** @brief System Flash memory mapped at 0x00000000
*/
#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() do {SYSCFG- & gt; CFGR1 & = ~(SYSCFG_CFGR1_MEM_MODE); \
SYSCFG- & gt; CFGR1 |= SYSCFG_CFGR1_MEM_MODE_0; \
}while(0)
#endif /* SYSCFG_CFGR1_MEM_MODE_0 */

#if defined(SYSCFG_CFGR1_MEM_MODE_0) & & defined(SYSCFG_CFGR1_MEM_MODE_1)
/** @brief Embedded SRAM mapped at 0x00000000
*/
#define __HAL_SYSCFG_REMAPMEMORY_SRAM() do {SYSCFG- & gt; CFGR1 & = ~(SYSCFG_CFGR1_MEM_MODE); \
SYSCFG- & gt; CFGR1 |= (SYSCFG_CFGR1_MEM_MODE_0 | SYSCFG_CFGR1_MEM_MODE_1); \
}while(0)
#endif /* SYSCFG_CFGR1_MEM_MODE_0 & & SYSCFG_CFGR1_MEM_MODE_1 */
/**
* @}
*/


#if defined(SYSCFG_CFGR1_PA11_PA12_RMP)
/** @defgroup HAL_Pin_remap HAL Pin remap
* @brief Pin remapping enable/disable macros
* @param __PIN_REMAP__ This parameter can be a value of @ref HAL_Pin_remapping
* @{
*/
#define __HAL_REMAP_PIN_ENABLE(__PIN_REMAP__) do {assert_param(IS_HAL_REMAP_PIN((__PIN_REMAP__))); \
SYSCFG- & gt; CFGR1 |= (__PIN_REMAP__); \
}while(0)
#define __HAL_REMAP_PIN_DISABLE(__PIN_REMAP__) do {assert_param(IS_HAL_REMAP_PIN((__PIN_REMAP__))); \
SYSCFG- & gt; CFGR1 & = ~(__PIN_REMAP__); \
}while(0)
/**
* @}
*/
#endif /* SYSCFG_CFGR1_PA11_PA12_RMP */

/** @brief Fast-mode Plus driving capability enable/disable macros
* @param __FASTMODEPLUS__ This parameter can be a value of @ref SYSCFG_FastModePlus_GPIO values.
* That you can find above these macros.
*/
#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
SET_BIT(SYSCFG- & gt; CFGR1, (__FASTMODEPLUS__));\
}while(0)

#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
CLEAR_BIT(SYSCFG- & gt; CFGR1, (__FASTMODEPLUS__));\
}while(0)
#if defined(SYSCFG_CFGR2_LOCKUP_LOCK)
/** @defgroup Cortex_Lockup_Enable Cortex Lockup Enable
* @{
*/
/** @brief SYSCFG Break Lockup lock
* Enables and locks the connection of Cortex-M0 LOCKUP (Hardfault) output to TIM1/15/16/17 Break input
* @note The selected configuration is locked and can be unlocked by system reset
*/
#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() do {SYSCFG- & gt; CFGR2 & = ~(SYSCFG_CFGR2_LOCKUP_LOCK); \
SYSCFG- & gt; CFGR2 |= SYSCFG_CFGR2_LOCKUP_LOCK; \
}while(0)
/**
* @}
*/
#endif /* SYSCFG_CFGR2_LOCKUP_LOCK */

#if defined(SYSCFG_CFGR2_PVD_LOCK)
/** @defgroup PVD_Lock_Enable PVD Lock
* @{
*/
/** @brief SYSCFG Break PVD lock
* Enables and locks the PVD connection with Timer1/8/15/16/17 Break Input, , as well as the PVDE and PLS[2:0] in the PWR_CR register
* @note The selected configuration is locked and can be unlocked by system reset
*/
#define __HAL_SYSCFG_BREAK_PVD_LOCK() do {SYSCFG- & gt; CFGR2 & = ~(SYSCFG_CFGR2_PVD_LOCK); \
SYSCFG- & gt; CFGR2 |= SYSCFG_CFGR2_PVD_LOCK; \
}while(0)
/**
* @}
*/
#endif /* SYSCFG_CFGR2_PVD_LOCK */

#if defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK)
/** @defgroup SRAM_Parity_Lock SRAM Parity Lock
* @{
*/
/** @brief SYSCFG Break SRAM PARITY lock
* Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1/8/15/16/17
* @note The selected configuration is locked and can be unlocked by system reset
*/
#define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK() do {SYSCFG- & gt; CFGR2 & = ~(SYSCFG_CFGR2_SRAM_PARITY_LOCK); \
SYSCFG- & gt; CFGR2 |= SYSCFG_CFGR2_SRAM_PARITY_LOCK; \
}while(0)
/**
* @}
*/
#endif /* SYSCFG_CFGR2_SRAM_PARITY_LOCK */

#if defined(SYSCFG_CFGR2_SRAM_PEF)
/** @defgroup HAL_SYSCFG_Parity_check_on_RAM HAL SYSCFG Parity check on RAM
* @brief Parity check on RAM disable macro
* @note Disabling the parity check on RAM locks the configuration bit.
* To re-enable the parity check on RAM perform a system reset.
* @{
*/
#define __HAL_SYSCFG_RAM_PARITYCHECK_DISABLE() (SYSCFG- & gt; CFGR2 |= SYSCFG_CFGR2_SRAM_PEF)
/**
* @}
*/
#endif /* SYSCFG_CFGR2_SRAM_PEF */


#if defined(STM32F091xC) || defined (STM32F098xx)
/** @defgroup HAL_ISR_wrapper_check HAL ISR wrapper check
* @brief ISR wrapper check
* @note This feature is applicable on STM32F09x
* @note Allow to determine interrupt source per line.
* @{
*/
#define __HAL_GET_PENDING_IT(__SOURCE__) (SYSCFG- & gt; IT_LINE_SR[((__SOURCE__) & gt; & gt; 0x18U)] & ((__SOURCE__) & 0x00FFFFFF))
/**
* @}
*/
#endif /* (STM32F091xC) || defined (STM32F098xx)*/

#if defined(STM32F091xC) || defined (STM32F098xx)
/** @defgroup HAL_SYSCFG_IRDA_modulation_envelope_selection HAL SYSCFG IRDA modulation envelope selection
* @brief selection of the modulation envelope signal macro, using bits [7:6] of SYS_CTRL(CFGR1) register
* @note This feature is applicable on STM32F09x
* @param __SOURCE__ This parameter can be a value of @ref HAL_IRDA_ENV_SEL
* @{
*/
#define __HAL_SYSCFG_IRDA_ENV_SELECTION(__SOURCE__) do {assert_param(IS_HAL_SYSCFG_IRDA_ENV_SEL((__SOURCE__))); \
SYSCFG- & gt; CFGR1 & = ~(SYSCFG_CFGR1_IRDA_ENV_SEL); \
SYSCFG- & gt; CFGR1 |= (__SOURCE__); \
}while(0)

#define __HAL_SYSCFG_GET_IRDA_ENV_SELECTION() ((SYSCFG- & gt; CFGR1) & 0x000000C0)
/**
* @}
*/
#endif /* (STM32F091xC) || defined (STM32F098xx)*/

/**
* @}
*/

/** @defgroup HAL_Private_Macros HAL Private Macros
* @{
*/
#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \
((FREQ) == HAL_TICK_FREQ_100HZ) || \
((FREQ) == HAL_TICK_FREQ_1KHZ))
/**
* @}
*/

/* Exported functions --------------------------------------------------------*/

/** @addtogroup HAL_Exported_Functions
* @{
*/

/** @addtogroup HAL_Exported_Functions_Group1
* @{
*/
/* Initialization and de-initialization functions ******************************/
HAL_StatusTypeDef HAL_Init(void);
HAL_StatusTypeDef HAL_DeInit(void);
void HAL_MspInit(void);
void HAL_MspDeInit(void);
HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
/**
* @}
*/

/* Exported variables ---------------------------------------------------------*/
/** @addtogroup HAL_Exported_Variables
* @{
*/
extern __IO uint32_t uwTick;
extern uint32_t uwTickPrio;
extern HAL_TickFreqTypeDef uwTickFreq;
/**
* @}
*/

/** @addtogroup HAL_Exported_Functions_Group2
* @{
*/

/* Peripheral Control functions ************************************************/
void HAL_IncTick(void);
void HAL_Delay(uint32_t Delay);
uint32_t HAL_GetTick(void);
uint32_t HAL_GetTickPrio(void);
HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);
HAL_TickFreqTypeDef HAL_GetTickFreq(void);
void HAL_SuspendTick(void);
void HAL_ResumeTick(void);
uint32_t HAL_GetHalVersion(void);
uint32_t HAL_GetREVID(void);
uint32_t HAL_GetDEVID(void);
uint32_t HAL_GetUIDw0(void);
uint32_t HAL_GetUIDw1(void);
uint32_t HAL_GetUIDw2(void);
void HAL_DBGMCU_EnableDBGStopMode(void);
void HAL_DBGMCU_DisableDBGStopMode(void);
void HAL_DBGMCU_EnableDBGStandbyMode(void);
void HAL_DBGMCU_DisableDBGStandbyMode(void);
/**
* @}
*/

/**
* @}
*/

/**
* @}
*/

/**
* @}
*/

#ifdef __cplusplus
}
#endif

#endif /* __STM32F0xx_HAL_H */

/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

ssr_test.zip > stm32f0xx_hal_tim.h

/**
******************************************************************************
* @file stm32f0xx_hal_tim.h
* @author MCD Application Team
* @brief Header file of TIM HAL module.
******************************************************************************
* @attention
*
* & lt; h2 & gt; & lt; center & gt; & copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved. & lt; /center & gt; & lt; /h2 & gt;
*
* This software component is licensed by ST under BSD 3-Clause license,
* the " License " ; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/

/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F0xx_HAL_TIM_H
#define STM32F0xx_HAL_TIM_H

#ifdef __cplusplus
extern " C " {
#endif

/* Includes ------------------------------------------------------------------*/
#include " stm32f0xx_hal_def.h "

/** @addtogroup STM32F0xx_HAL_Driver
* @{
*/

/** @addtogroup TIM
* @{
*/

/* Exported types ------------------------------------------------------------*/
/** @defgroup TIM_Exported_Types TIM Exported Types
* @{
*/

/**
* @brief TIM Time base Configuration Structure definition
*/
typedef struct
{
uint32_t Prescaler; /*! & lt; Specifies the prescaler value used to divide the TIM clock.
This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */

uint32_t CounterMode; /*! & lt; Specifies the counter mode.
This parameter can be a value of @ref TIM_Counter_Mode */

uint32_t Period; /*! & lt; Specifies the period value to be loaded into the active
Auto-Reload Register at the next update event.
This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */

uint32_t ClockDivision; /*! & lt; Specifies the clock division.
This parameter can be a value of @ref TIM_ClockDivision */

uint32_t RepetitionCounter; /*! & lt; Specifies the repetition counter value. Each time the RCR downcounter
reaches zero, an update event is generated and counting restarts
from the RCR value (N).
This means in PWM mode that (N+1) corresponds to:
- the number of PWM periods in edge-aligned mode
- the number of half PWM period in center-aligned mode
GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */

uint32_t AutoReloadPreload; /*! & lt; Specifies the auto-reload preload.
This parameter can be a value of @ref TIM_AutoReloadPreload */
} TIM_Base_InitTypeDef;

/**
* @brief TIM Output Compare Configuration Structure definition
*/
typedef struct
{
uint32_t OCMode; /*! & lt; Specifies the TIM mode.
This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */

uint32_t Pulse; /*! & lt; Specifies the pulse value to be loaded into the Capture Compare Register.
This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */

uint32_t OCPolarity; /*! & lt; Specifies the output polarity.
This parameter can be a value of @ref TIM_Output_Compare_Polarity */

uint32_t OCNPolarity; /*! & lt; Specifies the complementary output polarity.
This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
@note This parameter is valid only for timer instances supporting break feature. */

uint32_t OCFastMode; /*! & lt; Specifies the Fast mode state.
This parameter can be a value of @ref TIM_Output_Fast_State
@note This parameter is valid only in PWM1 and PWM2 mode. */


uint32_t OCIdleState; /*! & lt; Specifies the TIM Output Compare pin state during Idle state.
This parameter can be a value of @ref TIM_Output_Compare_Idle_State
@note This parameter is valid only for timer instances supporting break feature. */

uint32_t OCNIdleState; /*! & lt; Specifies the TIM Output Compare pin state during Idle state.
This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
@note This parameter is valid only for timer instances supporting break feature. */
} TIM_OC_InitTypeDef;

/**
* @brief TIM One Pulse Mode Configuration Structure definition
*/
typedef struct
{
uint32_t OCMode; /*! & lt; Specifies the TIM mode.
This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */

uint32_t Pulse; /*! & lt; Specifies the pulse value to be loaded into the Capture Compare Register.
This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */

uint32_t OCPolarity; /*! & lt; Specifies the output polarity.
This parameter can be a value of @ref TIM_Output_Compare_Polarity */

uint32_t OCNPolarity; /*! & lt; Specifies the complementary output polarity.
This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
@note This parameter is valid only for timer instances supporting break feature. */

uint32_t OCIdleState; /*! & lt; Specifies the TIM Output Compare pin state during Idle state.
This parameter can be a value of @ref TIM_Output_Compare_Idle_State
@note This parameter is valid only for timer instances supporting break feature. */

uint32_t OCNIdleState; /*! & lt; Specifies the TIM Output Compare pin state during Idle state.
This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
@note This parameter is valid only for timer instances supporting break feature. */

uint32_t ICPolarity; /*! & lt; Specifies the active edge of the input signal.
This parameter can be a value of @ref TIM_Input_Capture_Polarity */

uint32_t ICSelection; /*! & lt; Specifies the input.
This parameter can be a value of @ref TIM_Input_Capture_Selection */

uint32_t ICFilter; /*! & lt; Specifies the input capture filter.
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
} TIM_OnePulse_InitTypeDef;

/**
* @brief TIM Input Capture Configuration Structure definition
*/
typedef struct
{
uint32_t ICPolarity; /*! & lt; Specifies the active edge of the input signal.
This parameter can be a value of @ref TIM_Input_Capture_Polarity */

uint32_t ICSelection; /*! & lt; Specifies the input.
This parameter can be a value of @ref TIM_Input_Capture_Selection */

uint32_t ICPrescaler; /*! & lt; Specifies the Input Capture Prescaler.
This parameter can be a value of @ref TIM_Input_Capture_Prescaler */

uint32_t ICFilter; /*! & lt; Specifies the input capture filter.
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
} TIM_IC_InitTypeDef;

/**
* @brief TIM Encoder Configuration Structure definition
*/
typedef struct
{
uint32_t EncoderMode; /*! & lt; Specifies the active edge of the input signal.
This parameter can be a value of @ref TIM_Encoder_Mode */

uint32_t IC1Polarity; /*! & lt; Specifies the active edge of the input signal.
This parameter can be a value of @ref TIM_Encoder_Input_Polarity */

uint32_t IC1Selection; /*! & lt; Specifies the input.
This parameter can be a value of @ref TIM_Input_Capture_Selection */

uint32_t IC1Prescaler; /*! & lt; Specifies the Input Capture Prescaler.
This parameter can be a value of @ref TIM_Input_Capture_Prescaler */

uint32_t IC1Filter; /*! & lt; Specifies the input capture filter.
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */

uint32_t IC2Polarity; /*! & lt; Specifies the active edge of the input signal.
This parameter can be a value of @ref TIM_Encoder_Input_Polarity */

uint32_t IC2Selection; /*! & lt; Specifies the input.
This parameter can be a value of @ref TIM_Input_Capture_Selection */

uint32_t IC2Prescaler; /*! & lt; Specifies the Input Capture Prescaler.
This parameter can be a value of @ref TIM_Input_Capture_Prescaler */

uint32_t IC2Filter; /*! & lt; Specifies the input capture filter.
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
} TIM_Encoder_InitTypeDef;

/**
* @brief Clock Configuration Handle Structure definition
*/
typedef struct
{
uint32_t ClockSource; /*! & lt; TIM clock sources
This parameter can be a value of @ref TIM_Clock_Source */
uint32_t ClockPolarity; /*! & lt; TIM clock polarity
This parameter can be a value of @ref TIM_Clock_Polarity */
uint32_t ClockPrescaler; /*! & lt; TIM clock prescaler
This parameter can be a value of @ref TIM_Clock_Prescaler */
uint32_t ClockFilter; /*! & lt; TIM clock filter
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
} TIM_ClockConfigTypeDef;

/**
* @brief TIM Clear Input Configuration Handle Structure definition
*/
typedef struct
{
uint32_t ClearInputState; /*! & lt; TIM clear Input state
This parameter can be ENABLE or DISABLE */
uint32_t ClearInputSource; /*! & lt; TIM clear Input sources
This parameter can be a value of @ref TIM_ClearInput_Source */
uint32_t ClearInputPolarity; /*! & lt; TIM Clear Input polarity
This parameter can be a value of @ref TIM_ClearInput_Polarity */
uint32_t ClearInputPrescaler; /*! & lt; TIM Clear Input prescaler
This parameter must be 0: When OCRef clear feature is used with ETR source, ETR prescaler must be off */
uint32_t ClearInputFilter; /*! & lt; TIM Clear Input filter
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
} TIM_ClearInputConfigTypeDef;

/**
* @brief TIM Master configuration Structure definition
*/
typedef struct
{
uint32_t MasterOutputTrigger; /*! & lt; Trigger output (TRGO) selection
This parameter can be a value of @ref TIM_Master_Mode_Selection */
uint32_t MasterSlaveMode; /*! & lt; Master/slave mode selection
This parameter can be a value of @ref TIM_Master_Slave_Mode
@note When the Master/slave mode is enabled, the effect of
an event on the trigger input (TRGI) is delayed to allow a
perfect synchronization between the current timer and its
slaves (through TRGO). It is not mandatory in case of timer
synchronization mode. */
} TIM_MasterConfigTypeDef;

/**
* @brief TIM Slave configuration Structure definition
*/
typedef struct
{
uint32_t SlaveMode; /*! & lt; Slave mode selection
This parameter can be a value of @ref TIM_Slave_Mode */
uint32_t InputTrigger; /*! & lt; Input Trigger source
This parameter can be a value of @ref TIM_Trigger_Selection */
uint32_t TriggerPolarity; /*! & lt; Input Trigger polarity
This parameter can be a value of @ref TIM_Trigger_Polarity */
uint32_t TriggerPrescaler; /*! & lt; Input trigger prescaler
This parameter can be a value of @ref TIM_Trigger_Prescaler */
uint32_t TriggerFilter; /*! & lt; Input trigger filter
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */

} TIM_SlaveConfigTypeDef;

/**
* @brief TIM Break input(s) and Dead time configuration Structure definition
* @note 2 break inputs can be configured (BKIN and BKIN2) with configurable
* filter and polarity.
*/
typedef struct
{
uint32_t OffStateRunMode; /*! & lt; TIM off state in run mode
This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
uint32_t OffStateIDLEMode; /*! & lt; TIM off state in IDLE mode
This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
uint32_t LockLevel; /*! & lt; TIM Lock level
This parameter can be a value of @ref TIM_Lock_level */
uint32_t DeadTime; /*! & lt; TIM dead Time
This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
uint32_t BreakState; /*! & lt; TIM Break State
This parameter can be a value of @ref TIM_Break_Input_enable_disable */
uint32_t BreakPolarity; /*! & lt; TIM Break input polarity
This parameter can be a value of @ref TIM_Break_Polarity */
uint32_t BreakFilter; /*! & lt; Specifies the break input filter.
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
uint32_t AutomaticOutput; /*! & lt; TIM Automatic Output Enable state
This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
} TIM_BreakDeadTimeConfigTypeDef;

/**
* @brief HAL State structures definition
*/
typedef enum
{
HAL_TIM_STATE_RESET = 0x00U, /*! & lt; Peripheral not yet initialized or disabled */
HAL_TIM_STATE_READY = 0x01U, /*! & lt; Peripheral Initialized and ready for use */
HAL_TIM_STATE_BUSY = 0x02U, /*! & lt; An internal process is ongoing */
HAL_TIM_STATE_TIMEOUT = 0x03U, /*! & lt; Timeout state */
HAL_TIM_STATE_ERROR = 0x04U /*! & lt; Reception process is ongoing */
} HAL_TIM_StateTypeDef;

/**
* @brief TIM Channel States definition
*/
typedef enum
{
HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /*! & lt; TIM Channel initial state */
HAL_TIM_CHANNEL_STATE_READY = 0x01U, /*! & lt; TIM Channel ready for use */
HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, /*! & lt; An internal process is ongoing on the TIM channel */
} HAL_TIM_ChannelStateTypeDef;

/**
* @brief DMA Burst States definition
*/
typedef enum
{
HAL_DMA_BURST_STATE_RESET = 0x00U, /*! & lt; DMA Burst initial state */
HAL_DMA_BURST_STATE_READY = 0x01U, /*! & lt; DMA Burst ready for use */
HAL_DMA_BURST_STATE_BUSY = 0x02U, /*! & lt; Ongoing DMA Burst */
} HAL_TIM_DMABurstStateTypeDef;

/**
* @brief HAL Active channel structures definition
*/
typedef enum
{
HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*! & lt; The active channel is 1 */
HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*! & lt; The active channel is 2 */
HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*! & lt; The active channel is 3 */
HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*! & lt; The active channel is 4 */
HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*! & lt; All active channels cleared */
} HAL_TIM_ActiveChannel;

/**
* @brief TIM Time Base Handle Structure definition
*/
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
typedef struct __TIM_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
{
TIM_TypeDef *Instance; /*! & lt; Register base address */
TIM_Base_InitTypeDef Init; /*! & lt; TIM Time Base required parameters */
HAL_TIM_ActiveChannel Channel; /*! & lt; Active channel */
DMA_HandleTypeDef *hdma[7]; /*! & lt; DMA Handlers array
This array is accessed by a @ref DMA_Handle_index */
HAL_LockTypeDef Lock; /*! & lt; Locking object */
__IO HAL_TIM_StateTypeDef State; /*! & lt; TIM operation state */
__IO HAL_TIM_ChannelStateTypeDef ChannelState[4]; /*! & lt; TIM channel operation state */
__IO HAL_TIM_ChannelStateTypeDef ChannelNState[4]; /*! & lt; TIM complementary channel operation state */
__IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /*! & lt; DMA burst operation state */

#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*! & lt; TIM Base Msp Init Callback */
void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*! & lt; TIM Base Msp DeInit Callback */
void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*! & lt; TIM IC Msp Init Callback */
void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*! & lt; TIM IC Msp DeInit Callback */
void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*! & lt; TIM OC Msp Init Callback */
void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*! & lt; TIM OC Msp DeInit Callback */
void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*! & lt; TIM PWM Msp Init Callback */
void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*! & lt; TIM PWM Msp DeInit Callback */
void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*! & lt; TIM One Pulse Msp Init Callback */
void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*! & lt; TIM One Pulse Msp DeInit Callback */
void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*! & lt; TIM Encoder Msp Init Callback */
void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*! & lt; TIM Encoder Msp DeInit Callback */
void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*! & lt; TIM Hall Sensor Msp Init Callback */
void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*! & lt; TIM Hall Sensor Msp DeInit Callback */
void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*! & lt; TIM Period Elapsed Callback */
void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*! & lt; TIM Period Elapsed half complete Callback */
void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*! & lt; TIM Trigger Callback */
void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*! & lt; TIM Trigger half complete Callback */
void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*! & lt; TIM Input Capture Callback */
void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*! & lt; TIM Input Capture half complete Callback */
void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*! & lt; TIM Output Compare Delay Elapsed Callback */
void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*! & lt; TIM PWM Pulse Finished Callback */
void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*! & lt; TIM PWM Pulse Finished half complete Callback */
void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*! & lt; TIM Error Callback */
void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim); /*! & lt; TIM Commutation Callback */
void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*! & lt; TIM Commutation half complete Callback */
void (* BreakCallback)(struct __TIM_HandleTypeDef *htim); /*! & lt; TIM Break Callback */
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
} TIM_HandleTypeDef;

#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
/**
* @brief HAL TIM Callback ID enumeration definition
*/
typedef enum
{
HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*! & lt; TIM Base MspInit Callback ID */
, HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*! & lt; TIM Base MspDeInit Callback ID */
, HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*! & lt; TIM IC MspInit Callback ID */
, HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*! & lt; TIM IC MspDeInit Callback ID */
, HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*! & lt; TIM OC MspInit Callback ID */
, HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*! & lt; TIM OC MspDeInit Callback ID */
, HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*! & lt; TIM PWM MspInit Callback ID */
, HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*! & lt; TIM PWM MspDeInit Callback ID */
, HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*! & lt; TIM One Pulse MspInit Callback ID */
, HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*! & lt; TIM One Pulse MspDeInit Callback ID */
, HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*! & lt; TIM Encoder MspInit Callback ID */
, HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*! & lt; TIM Encoder MspDeInit Callback ID */
, HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*! & lt; TIM Hall Sensor MspDeInit Callback ID */
, HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*! & lt; TIM Hall Sensor MspDeInit Callback ID */
, HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*! & lt; TIM Period Elapsed Callback ID */
, HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*! & lt; TIM Period Elapsed half complete Callback ID */
, HAL_TIM_TRIGGER_CB_ID = 0x10U /*! & lt; TIM Trigger Callback ID */
, HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*! & lt; TIM Trigger half complete Callback ID */

, HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*! & lt; TIM Input Capture Callback ID */
, HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*! & lt; TIM Input Capture half complete Callback ID */
, HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*! & lt; TIM Output Compare Delay Elapsed Callback ID */
, HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*! & lt; TIM PWM Pulse Finished Callback ID */
, HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*! & lt; TIM PWM Pulse Finished half complete Callback ID */
, HAL_TIM_ERROR_CB_ID = 0x17U /*! & lt; TIM Error Callback ID */
, HAL_TIM_COMMUTATION_CB_ID = 0x18U /*! & lt; TIM Commutation Callback ID */
, HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*! & lt; TIM Commutation half complete Callback ID */
, HAL_TIM_BREAK_CB_ID = 0x1AU /*! & lt; TIM Break Callback ID */
} HAL_TIM_CallbackIDTypeDef;

/**
* @brief HAL TIM Callback pointer definition
*/
typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*! & lt; pointer to the TIM callback function */

#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */

/**
* @}
*/
/* End of exported types -----------------------------------------------------*/

/* Exported constants --------------------------------------------------------*/
/** @defgroup TIM_Exported_Constants TIM Exported Constants
* @{
*/

/** @defgroup TIM_ClearInput_Source TIM Clear Input Source
* @{
*/
#define TIM_CLEARINPUTSOURCE_NONE 0x00000000U /*! & lt; OCREF_CLR is disabled */
#define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*! & lt; OCREF_CLR is connected to ETRF input */
#define TIM_CLEARINPUTSOURCE_OCREFCLR 0x00000002U /*! & lt; OCREF_CLR is connected to OCREF_CLR_INT */
/**
* @}
*/

/** @defgroup TIM_DMA_Base_address TIM DMA Base Address
* @{
*/
#define TIM_DMABASE_CR1 0x00000000U
#define TIM_DMABASE_CR2 0x00000001U
#define TIM_DMABASE_SMCR 0x00000002U
#define TIM_DMABASE_DIER 0x00000003U
#define TIM_DMABASE_SR 0x00000004U
#define TIM_DMABASE_EGR 0x00000005U
#define TIM_DMABASE_CCMR1 0x00000006U
#define TIM_DMABASE_CCMR2 0x00000007U
#define TIM_DMABASE_CCER 0x00000008U
#define TIM_DMABASE_CNT 0x00000009U
#define TIM_DMABASE_PSC 0x0000000AU
#define TIM_DMABASE_ARR 0x0000000BU
#define TIM_DMABASE_RCR 0x0000000CU
#define TIM_DMABASE_CCR1 0x0000000DU
#define TIM_DMABASE_CCR2 0x0000000EU
#define TIM_DMABASE_CCR3 0x0000000FU
#define TIM_DMABASE_CCR4 0x00000010U
#define TIM_DMABASE_BDTR 0x00000011U
#define TIM_DMABASE_DCR 0x00000012U
#define TIM_DMABASE_DMAR 0x00000013U
/**
* @}
*/

/** @defgroup TIM_Event_Source TIM Event Source
* @{
*/
#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*! & lt; Reinitialize the counter and generates an update of the registers */
#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*! & lt; A capture/compare event is generated on channel 1 */
#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*! & lt; A capture/compare event is generated on channel 2 */
#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*! & lt; A capture/compare event is generated on channel 3 */
#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*! & lt; A capture/compare event is generated on channel 4 */
#define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*! & lt; A commutation event is generated */
#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*! & lt; A trigger event is generated */
#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*! & lt; A break event is generated */
/**
* @}
*/

/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity
* @{
*/
#define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*! & lt; Polarity for TIx source */
#define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*! & lt; Polarity for TIx source */
#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*! & lt; Polarity for TIx source */
/**
* @}
*/

/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
* @{
*/
#define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*! & lt; Polarity for ETR source */
#define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*! & lt; Polarity for ETR source */
/**
* @}
*/

/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
* @{
*/
#define TIM_ETRPRESCALER_DIV1 0x00000000U /*! & lt; No prescaler is used */
#define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*! & lt; ETR input source is divided by 2 */
#define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*! & lt; ETR input source is divided by 4 */
#define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*! & lt; ETR input source is divided by 8 */
/**
* @}
*/

/** @defgroup TIM_Counter_Mode TIM Counter Mode
* @{
*/
#define TIM_COUNTERMODE_UP 0x00000000U /*! & lt; Counter used as up-counter */
#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*! & lt; Counter used as down-counter */
#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*! & lt; Center-aligned mode 1 */
#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*! & lt; Center-aligned mode 2 */
#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*! & lt; Center-aligned mode 3 */
/**
* @}
*/

/** @defgroup TIM_ClockDivision TIM Clock Division
* @{
*/
#define TIM_CLOCKDIVISION_DIV1 0x00000000U /*! & lt; Clock division: tDTS=tCK_INT */
#define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*! & lt; Clock division: tDTS=2*tCK_INT */
#define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*! & lt; Clock division: tDTS=4*tCK_INT */
/**
* @}
*/

/** @defgroup TIM_Output_Compare_State TIM Output Compare State
* @{
*/
#define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*! & lt; Capture/Compare 1 output disabled */
#define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*! & lt; Capture/Compare 1 output enabled */
/**
* @}
*/

/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload
* @{
*/
#define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*! & lt; TIMx_ARR register is not buffered */
#define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*! & lt; TIMx_ARR register is buffered */

/**
* @}
*/

/** @defgroup TIM_Output_Fast_State TIM Output Fast State
* @{
*/
#define TIM_OCFAST_DISABLE 0x00000000U /*! & lt; Output Compare fast disable */
#define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*! & lt; Output Compare fast enable */
/**
* @}
*/

/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
* @{
*/
#define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*! & lt; OCxN is disabled */
#define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*! & lt; OCxN is enabled */
/**
* @}
*/

/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
* @{
*/
#define TIM_OCPOLARITY_HIGH 0x00000000U /*! & lt; Capture/Compare output polarity */
#define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*! & lt; Capture/Compare output polarity */
/**
* @}
*/

/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
* @{
*/
#define TIM_OCNPOLARITY_HIGH 0x00000000U /*! & lt; Capture/Compare complementary output polarity */
#define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /*! & lt; Capture/Compare complementary output polarity */
/**
* @}
*/

/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
* @{
*/
#define TIM_OCIDLESTATE_SET TIM_CR2_OIS1 /*! & lt; Output Idle state: OCx=1 when MOE=0 */
#define TIM_OCIDLESTATE_RESET 0x00000000U /*! & lt; Output Idle state: OCx=0 when MOE=0 */
/**
* @}
*/

/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
* @{
*/
#define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N /*! & lt; Complementary output Idle state: OCxN=1 when MOE=0 */
#define TIM_OCNIDLESTATE_RESET 0x00000000U /*! & lt; Complementary output Idle state: OCxN=0 when MOE=0 */
/**
* @}
*/

/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
* @{
*/
#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*! & lt; Capture triggered by rising edge on timer input */
#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*! & lt; Capture triggered by falling edge on timer input */
#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*! & lt; Capture triggered by both rising and falling edges on timer input*/
/**
* @}
*/

/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity
* @{
*/
#define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*! & lt; Encoder input with rising edge polarity */
#define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*! & lt; Encoder input with falling edge polarity */
/**
* @}
*/

/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
* @{
*/
#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*! & lt; TIM Input 1, 2, 3 or 4 is selected to be
connected to IC1, IC2, IC3 or IC4, respectively */
#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*! & lt; TIM Input 1, 2, 3 or 4 is selected to be
connected to IC2, IC1, IC4 or IC3, respectively */
#define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*! & lt; TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
/**
* @}
*/

/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
* @{
*/
#define TIM_ICPSC_DIV1 0x00000000U /*! & lt; Capture performed each time an edge is detected on the capture input */
#define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*! & lt; Capture performed once every 2 events */
#define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*! & lt; Capture performed once every 4 events */
#define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*! & lt; Capture performed once every 8 events */
/**
* @}
*/

/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
* @{
*/
#define TIM_OPMODE_SINGLE TIM_CR1_OPM /*! & lt; Counter stops counting at the next update event */
#define TIM_OPMODE_REPETITIVE 0x00000000U /*! & lt; Counter is not stopped at update event */
/**
* @}
*/

/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
* @{
*/
#define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*! & lt; Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */
#define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*! & lt; Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */
#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*! & lt; Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */
/**
* @}
*/

/** @defgroup TIM_Interrupt_definition TIM interrupt Definition
* @{
*/
#define TIM_IT_UPDATE TIM_DIER_UIE /*! & lt; Update interrupt */
#define TIM_IT_CC1 TIM_DIER_CC1IE /*! & lt; Capture/Compare 1 interrupt */
#define TIM_IT_CC2 TIM_DIER_CC2IE /*! & lt; Capture/Compare 2 interrupt */
#define TIM_IT_CC3 TIM_DIER_CC3IE /*! & lt; Capture/Compare 3 interrupt */
#define TIM_IT_CC4 TIM_DIER_CC4IE /*! & lt; Capture/Compare 4 interrupt */
#define TIM_IT_COM TIM_DIER_COMIE /*! & lt; Commutation interrupt */
#define TIM_IT_TRIGGER TIM_DIER_TIE /*! & lt; Trigger interrupt */
#define TIM_IT_BREAK TIM_DIER_BIE /*! & lt; Break interrupt */
/**
* @}
*/

/** @defgroup TIM_Commutation_Source TIM Commutation Source
* @{
*/
#define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /*! & lt; When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */
#define TIM_COMMUTATION_SOFTWARE 0x00000000U /*! & lt; When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */
/**
* @}
*/

/** @defgroup TIM_DMA_sources TIM DMA Sources
* @{
*/
#define TIM_DMA_UPDATE TIM_DIER_UDE /*! & lt; DMA request is triggered by the update event */
#define TIM_DMA_CC1 TIM_DIER_CC1DE /*! & lt; DMA request is triggered by the capture/compare macth 1 event */
#define TIM_DMA_CC2 TIM_DIER_CC2DE /*! & lt; DMA request is triggered by the capture/compare macth 2 event event */
#define TIM_DMA_CC3 TIM_DIER_CC3DE /*! & lt; DMA request is triggered by the capture/compare macth 3 event event */
#define TIM_DMA_CC4 TIM_DIER_CC4DE /*! & lt; DMA request is triggered by the capture/compare macth 4 event event */
#define TIM_DMA_COM TIM_DIER_COMDE /*! & lt; DMA request is triggered by the commutation event */
#define TIM_DMA_TRIGGER TIM_DIER_TDE /*! & lt; DMA request is triggered by the trigger event */
/**
* @}
*/

/** @defgroup TIM_Flag_definition TIM Flag Definition
* @{
*/
#define TIM_FLAG_UPDATE TIM_SR_UIF /*! & lt; Update interrupt flag */
#define TIM_FLAG_CC1 TIM_SR_CC1IF /*! & lt; Capture/Compare 1 interrupt flag */
#define TIM_FLAG_CC2 TIM_SR_CC2IF /*! & lt; Capture/Compare 2 interrupt flag */
#define TIM_FLAG_CC3 TIM_SR_CC3IF /*! & lt; Capture/Compare 3 interrupt flag */
#define TIM_FLAG_CC4 TIM_SR_CC4IF /*! & lt; Capture/Compare 4 interrupt flag */
#define TIM_FLAG_COM TIM_SR_COMIF /*! & lt; Commutation interrupt flag */
#define TIM_FLAG_TRIGGER TIM_SR_TIF /*! & lt; Trigger interrupt flag */
#define TIM_FLAG_BREAK TIM_SR_BIF /*! & lt; Break interrupt flag */
#define TIM_FLAG_CC1OF TIM_SR_CC1OF /*! & lt; Capture 1 overcapture flag */
#define TIM_FLAG_CC2OF TIM_SR_CC2OF /*! & lt; Capture 2 overcapture flag */
#define TIM_FLAG_CC3OF TIM_SR_CC3OF /*! & lt; Capture 3 overcapture flag */
#define TIM_FLAG_CC4OF TIM_SR_CC4OF /*! & lt; Capture 4 overcapture flag */
/**
* @}
*/

/** @defgroup TIM_Channel TIM Channel
* @{
*/
#define TIM_CHANNEL_1 0x00000000U /*! & lt; Capture/compare channel 1 identifier */
#define TIM_CHANNEL_2 0x00000004U /*! & lt; Capture/compare channel 2 identifier */
#define TIM_CHANNEL_3 0x00000008U /*! & lt; Capture/compare channel 3 identifier */
#define TIM_CHANNEL_4 0x0000000CU /*! & lt; Capture/compare channel 4 identifier */
#define TIM_CHANNEL_ALL 0x0000003CU /*! & lt; Global Capture/compare channel identifier */
/**
* @}
*/

/** @defgroup TIM_Clock_Source TIM Clock Source
* @{
*/
#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*! & lt; External clock source mode 2 */
#define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*! & lt; Internal clock source */
#define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*! & lt; External clock source mode 1 (ITR0) */
#define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*! & lt; External clock source mode 1 (ITR1) */
#define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*! & lt; External clock source mode 1 (ITR2) */
#define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*! & lt; External clock source mode 1 (ITR3) */
#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*! & lt; External clock source mode 1 (TTI1FP1 + edge detect.) */
#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*! & lt; External clock source mode 1 (TTI1FP1) */
#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*! & lt; External clock source mode 1 (TTI2FP2) */
#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*! & lt; External clock source mode 1 (ETRF) */
/**
* @}
*/

/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
* @{
*/
#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*! & lt; Polarity for ETRx clock sources */
#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*! & lt; Polarity for ETRx clock sources */
#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*! & lt; Polarity for TIx clock sources */
#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*! & lt; Polarity for TIx clock sources */
#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*! & lt; Polarity for TIx clock sources */
/**
* @}
*/

/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
* @{
*/
#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*! & lt; No prescaler is used */
#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*! & lt; Prescaler for External ETR Clock: Capture performed once every 2 events. */
#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*! & lt; Prescaler for External ETR Clock: Capture performed once every 4 events. */
#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*! & lt; Prescaler for External ETR Clock: Capture performed once every 8 events. */
/**
* @}
*/

/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
* @{
*/
#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*! & lt; Polarity for ETRx pin */
#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*! & lt; Polarity for ETRx pin */
/**
* @}
*/

/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
* @{
*/
#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*! & lt; No prescaler is used */
#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*! & lt; Prescaler for External ETR pin: Capture performed once every 2 events. */
#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*! & lt; Prescaler for External ETR pin: Capture performed once every 4 events. */
#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*! & lt; Prescaler for External ETR pin: Capture performed once every 8 events. */
/**
* @}
*/

/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state
* @{
*/
#define TIM_OSSR_ENABLE TIM_BDTR_OSSR /*! & lt; When inactive, OC/OCN outputs are enabled (still controlled by the timer) */
#define TIM_OSSR_DISABLE 0x00000000U /*! & lt; When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */
/**
* @}
*/

/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state
* @{
*/
#define TIM_OSSI_ENABLE TIM_BDTR_OSSI /*! & lt; When inactive, OC/OCN outputs are enabled (still controlled by the timer) */
#define TIM_OSSI_DISABLE 0x00000000U /*! & lt; When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */
/**
* @}
*/
/** @defgroup TIM_Lock_level TIM Lock level
* @{
*/
#define TIM_LOCKLEVEL_OFF 0x00000000U /*! & lt; LOCK OFF */
#define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*! & lt; LOCK Level 1 */
#define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*! & lt; LOCK Level 2 */
#define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*! & lt; LOCK Level 3 */
/**
* @}
*/

/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable
* @{
*/
#define TIM_BREAK_ENABLE TIM_BDTR_BKE /*! & lt; Break input BRK is enabled */
#define TIM_BREAK_DISABLE 0x00000000U /*! & lt; Break input BRK is disabled */
/**
* @}
*/

/** @defgroup TIM_Break_Polarity TIM Break Input Polarity
* @{
*/
#define TIM_BREAKPOLARITY_LOW 0x00000000U /*! & lt; Break input BRK is active low */
#define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /*! & lt; Break input BRK is active high */
/**
* @}
*/

/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
* @{
*/
#define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*! & lt; MOE can be set only by software */
#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*! & lt; MOE can be set by software or automatically at the next update event
(if none of the break inputs BRK and BRK2 is active) */
/**
* @}
*/

/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
* @{
*/
#define TIM_TRGO_RESET 0x00000000U /*! & lt; TIMx_EGR.UG bit is used as trigger output (TRGO) */
#define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*! & lt; TIMx_CR1.CEN bit is used as trigger output (TRGO) */
#define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*! & lt; Update event is used as trigger output (TRGO) */
#define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*! & lt; Capture or a compare match 1 is used as trigger output (TRGO) */
#define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*! & lt; OC1REF signal is used as trigger output (TRGO) */
#define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*! & lt; OC2REF signal is used as trigger output(TRGO) */
#define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*! & lt; OC3REF signal is used as trigger output(TRGO) */
#define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*! & lt; OC4REF signal is used as trigger output(TRGO) */
/**
* @}
*/

/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode
* @{
*/
#define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*! & lt; No action */
#define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*! & lt; Master/slave mode is selected */
/**
* @}
*/

/** @defgroup TIM_Slave_Mode TIM Slave mode
* @{
*/
#define TIM_SLAVEMODE_DISABLE 0x00000000U /*! & lt; Slave mode disabled */
#define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*! & lt; Reset Mode */
#define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*! & lt; Gated Mode */
#define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*! & lt; Trigger Mode */
#define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*! & lt; External Clock Mode 1 */
/**
* @}
*/

/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes
* @{
*/
#define TIM_OCMODE_TIMING 0x00000000U /*! & lt; Frozen */
#define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*! & lt; Set channel to active level on match */
#define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*! & lt; Set channel to inactive level on match */
#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*! & lt; Toggle */
#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*! & lt; PWM mode 1 */
#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*! & lt; PWM mode 2 */
#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*! & lt; Force active level */
#define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*! & lt; Force inactive level */
/**
* @}
*/

/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
* @{
*/
#define TIM_TS_ITR0 0x00000000U /*! & lt; Internal Trigger 0 (ITR0) */
#define TIM_TS_ITR1 TIM_SMCR_TS_0 /*! & lt; Internal Trigger 1 (ITR1) */
#define TIM_TS_ITR2 TIM_SMCR_TS_1 /*! & lt; Internal Trigger 2 (ITR2) */
#define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*! & lt; Internal Trigger 3 (ITR3) */
#define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*! & lt; TI1 Edge Detector (TI1F_ED) */
#define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*! & lt; Filtered Timer Input 1 (TI1FP1) */
#define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*! & lt; Filtered Timer Input 2 (TI2FP2) */
#define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*! & lt; Filtered External Trigger input (ETRF) */
#define TIM_TS_NONE 0x0000FFFFU /*! & lt; No trigger selected */
/**
* @}
*/

/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
* @{
*/
#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*! & lt; Polarity for ETRx trigger sources */
#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*! & lt; Polarity for ETRx trigger sources */
#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*! & lt; Polarity for TIxFPx or TI1_ED trigger sources */
#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*! & lt; Polarity for TIxFPx or TI1_ED trigger sources */
#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*! & lt; Polarity for TIxFPx or TI1_ED trigger sources */
/**
* @}
*/

/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
* @{
*/
#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*! & lt; No prescaler is used */
#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*! & lt; Prescaler for External ETR Trigger: Capture performed once every 2 events. */
#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*! & lt; Prescaler for External ETR Trigger: Capture performed once every 4 events. */
#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*! & lt; Prescaler for External ETR Trigger: Capture performed once every 8 events. */
/**
* @}
*/

/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
* @{
*/
#define TIM_TI1SELECTION_CH1 0x00000000U /*! & lt; The TIMx_CH1 pin is connected to TI1 input */
#define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*! & lt; The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */
/**
* @}
*/

/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
* @{
*/
#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*! & lt; The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*! & lt; The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*! & lt; The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*! & lt; The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*! & lt; The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*! & lt; The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*! & lt; The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*! & lt; The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*! & lt; The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*! & lt; The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*! & lt; The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*! & lt; The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*! & lt; The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*! & lt; The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*! & lt; The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*! & lt; The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*! & lt; The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*! & lt; The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
/**
* @}
*/

/** @defgroup DMA_Handle_index TIM DMA Handle Index
* @{
*/
#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*! & lt; Index of the DMA handle used for Update DMA requests */
#define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*! & lt; Index of the DMA handle used for Capture/Compare 1 DMA requests */
#define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*! & lt; Index of the DMA handle used for Capture/Compare 2 DMA requests */
#define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /*! & lt; Index of the DMA handle used for Capture/Compare 3 DMA requests */
#define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /*! & lt; Index of the DMA handle used for Capture/Compare 4 DMA requests */
#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005) /*! & lt; Index of the DMA handle used for Commutation DMA requests */
#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /*! & lt; Index of the DMA handle used for Trigger DMA requests */
/**
* @}
*/

/** @defgroup Channel_CC_State TIM Capture/Compare Channel State
* @{
*/
#define TIM_CCx_ENABLE 0x00000001U /*! & lt; Input or output channel is enabled */
#define TIM_CCx_DISABLE 0x00000000U /*! & lt; Input or output channel is disabled */
#define TIM_CCxN_ENABLE 0x00000004U /*! & lt; Complementary output channel is enabled */
#define TIM_CCxN_DISABLE 0x00000000U /*! & lt; Complementary output channel is enabled */
/**
* @}
*/

/**
* @}
*/
/* End of exported constants -------------------------------------------------*/

/* Exported macros -----------------------------------------------------------*/
/** @defgroup TIM_Exported_Macros TIM Exported Macros
* @{
*/

/** @brief Reset TIM handle state.
* @param __HANDLE__ TIM handle.
* @retval None
*/
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
(__HANDLE__)- & gt; State = HAL_TIM_STATE_RESET; \
(__HANDLE__)- & gt; ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)- & gt; ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)- & gt; ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)- & gt; ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)- & gt; ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)- & gt; ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)- & gt; ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)- & gt; ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)- & gt; DMABurstState = HAL_DMA_BURST_STATE_RESET; \
(__HANDLE__)- & gt; Base_MspInitCallback = NULL; \
(__HANDLE__)- & gt; Base_MspDeInitCallback = NULL; \
(__HANDLE__)- & gt; IC_MspInitCallback = NULL; \
(__HANDLE__)- & gt; IC_MspDeInitCallback = NULL; \
(__HANDLE__)- & gt; OC_MspInitCallback = NULL; \
(__HANDLE__)- & gt; OC_MspDeInitCallback = NULL; \
(__HANDLE__)- & gt; PWM_MspInitCallback = NULL; \
(__HANDLE__)- & gt; PWM_MspDeInitCallback = NULL; \
(__HANDLE__)- & gt; OnePulse_MspInitCallback = NULL; \
(__HANDLE__)- & gt; OnePulse_MspDeInitCallback = NULL; \
(__HANDLE__)- & gt; Encoder_MspInitCallback = NULL; \
(__HANDLE__)- & gt; Encoder_MspDeInitCallback = NULL; \
(__HANDLE__)- & gt; HallSensor_MspInitCallback = NULL; \
(__HANDLE__)- & gt; HallSensor_MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
(__HANDLE__)- & gt; State = HAL_TIM_STATE_RESET; \
(__HANDLE__)- & gt; ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)- & gt; ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)- & gt; ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)- & gt; ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)- & gt; ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)- & gt; ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)- & gt; ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)- & gt; ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)- & gt; DMABurstState = HAL_DMA_BURST_STATE_RESET; \
} while(0)
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */

/**
* @brief Enable the TIM peripheral.
* @param __HANDLE__ TIM handle
* @retval None
*/
#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)- & gt; Instance- & gt; CR1|=(TIM_CR1_CEN))

/**
* @brief Enable the TIM main Output.
* @param __HANDLE__ TIM handle
* @retval None
*/
#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)- & gt; Instance- & gt; BDTR|=(TIM_BDTR_MOE))

/**
* @brief Disable the TIM peripheral.
* @param __HANDLE__ TIM handle
* @retval None
*/
#define __HAL_TIM_DISABLE(__HANDLE__) \
do { \
if (((__HANDLE__)- & gt; Instance- & gt; CCER & TIM_CCER_CCxE_MASK) == 0UL) \
{ \
if(((__HANDLE__)- & gt; Instance- & gt; CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
{ \
(__HANDLE__)- & gt; Instance- & gt; CR1 & = ~(TIM_CR1_CEN); \
} \
} \
} while(0)

/**
* @brief Disable the TIM main Output.
* @param __HANDLE__ TIM handle
* @retval None
* @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled
*/
#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
do { \
if (((__HANDLE__)- & gt; Instance- & gt; CCER & TIM_CCER_CCxE_MASK) == 0UL) \
{ \
if(((__HANDLE__)- & gt; Instance- & gt; CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
{ \
(__HANDLE__)- & gt; Instance- & gt; BDTR & = ~(TIM_BDTR_MOE); \
} \
} \
} while(0)

/**
* @brief Disable the TIM main Output.
* @param __HANDLE__ TIM handle
* @retval None
* @note The Main Output Enable of a timer instance is disabled unconditionally
*/
#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)- & gt; Instance- & gt; BDTR & = ~(TIM_BDTR_MOE)

/** @brief Enable the specified TIM interrupt.
* @param __HANDLE__ specifies the TIM Handle.
* @param __INTERRUPT__ specifies the TIM interrupt source to enable.
* This parameter can be one of the following values:
* @arg TIM_IT_UPDATE: Update interrupt
* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
* @arg TIM_IT_COM: Commutation interrupt
* @arg TIM_IT_TRIGGER: Trigger interrupt
* @arg TIM_IT_BREAK: Break interrupt
* @retval None
*/
#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)- & gt; Instance- & gt; DIER |= (__INTERRUPT__))

/** @brief Disable the specified TIM interrupt.
* @param __HANDLE__ specifies the TIM Handle.
* @param __INTERRUPT__ specifies the TIM interrupt source to disable.
* This parameter can be one of the following values:
* @arg TIM_IT_UPDATE: Update interrupt
* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
* @arg TIM_IT_COM: Commutation interrupt
* @arg TIM_IT_TRIGGER: Trigger interrupt
* @arg TIM_IT_BREAK: Break interrupt
* @retval None
*/
#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)- & gt; Instance- & gt; DIER & = ~(__INTERRUPT__))

/** @brief Enable the specified DMA request.
* @param __HANDLE__ specifies the TIM Handle.
* @param __DMA__ specifies the TIM DMA request to enable.
* This parameter can be one of the following values:
* @arg TIM_DMA_UPDATE: Update DMA request
* @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
* @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
* @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
* @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
* @arg TIM_DMA_COM: Commutation DMA request
* @arg TIM_DMA_TRIGGER: Trigger DMA request
* @retval None
*/
#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)- & gt; Instance- & gt; DIER |= (__DMA__))

/** @brief Disable the specified DMA request.
* @param __HANDLE__ specifies the TIM Handle.
* @param __DMA__ specifies the TIM DMA request to disable.
* This parameter can be one of the following values:
* @arg TIM_DMA_UPDATE: Update DMA request
* @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
* @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
* @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
* @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
* @arg TIM_DMA_COM: Commutation DMA request
* @arg TIM_DMA_TRIGGER: Trigger DMA request
* @retval None
*/
#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)- & gt; Instance- & gt; DIER & = ~(__DMA__))

/** @brief Check whether the specified TIM interrupt flag is set or not.
* @param __HANDLE__ specifies the TIM Handle.
* @param __FLAG__ specifies the TIM interrupt flag to check.
* This parameter can be one of the following values:
* @arg TIM_FLAG_UPDATE: Update interrupt flag
* @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
* @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
* @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
* @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
* @arg TIM_FLAG_COM: Commutation interrupt flag
* @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
* @arg TIM_FLAG_BREAK: Break interrupt flag
* @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
* @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
* @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
* @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)- & gt; Instance- & gt; SR & (__FLAG__)) == (__FLAG__))

/** @brief Clear the specified TIM interrupt flag.
* @param __HANDLE__ specifies the TIM Handle.
* @param __FLAG__ specifies the TIM interrupt flag to clear.
* This parameter can be one of the following values:
* @arg TIM_FLAG_UPDATE: Update interrupt flag
* @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
* @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
* @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
* @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
* @arg TIM_FLAG_COM: Commutation interrupt flag
* @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
* @arg TIM_FLAG_BREAK: Break interrupt flag
* @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
* @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
* @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
* @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)- & gt; Instance- & gt; SR = ~(__FLAG__))

/**
* @brief Check whether the specified TIM interrupt source is enabled or not.
* @param __HANDLE__ TIM handle
* @param __INTERRUPT__ specifies the TIM interrupt source to check.
* This parameter can be one of the following values:
* @arg TIM_IT_UPDATE: Update interrupt
* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
* @arg TIM_IT_COM: Commutation interrupt
* @arg TIM_IT_TRIGGER: Trigger interrupt
* @arg TIM_IT_BREAK: Break interrupt
* @retval The state of TIM_IT (SET or RESET).
*/
#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)- & gt; Instance- & gt; DIER & (__INTERRUPT__)) \
== (__INTERRUPT__)) ? SET : RESET)

/** @brief Clear the TIM interrupt pending bits.
* @param __HANDLE__ TIM handle
* @param __INTERRUPT__ specifies the interrupt pending bit to clear.
* This parameter can be one of the following values:
* @arg TIM_IT_UPDATE: Update interrupt
* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
* @arg TIM_IT_COM: Commutation interrupt
* @arg TIM_IT_TRIGGER: Trigger interrupt
* @arg TIM_IT_BREAK: Break interrupt
* @retval None
*/
#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)- & gt; Instance- & gt; SR = ~(__INTERRUPT__))

/**
* @brief Indicates whether or not the TIM Counter is used as downcounter.
* @param __HANDLE__ TIM handle.
* @retval False (Counter used as upcounter) or True (Counter used as downcounter)
* @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder
mode.
*/
#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)- & gt; Instance- & gt; CR1 & (TIM_CR1_DIR)) == (TIM_CR1_DIR))

/**
* @brief Set the TIM Prescaler on runtime.
* @param __HANDLE__ TIM handle.
* @param __PRESC__ specifies the Prescaler new value.
* @retval None
*/
#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)- & gt; Instance- & gt; PSC = (__PRESC__))

/**
* @brief Set the TIM Counter Register value on runtime.
* @param __HANDLE__ TIM handle.
* @param __COUNTER__ specifies the Counter register new value.
* @retval None
*/
#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)- & gt; Instance- & gt; CNT = (__COUNTER__))

/**
* @brief Get the TIM Counter Register value on runtime.
* @param __HANDLE__ TIM handle.
* @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
*/
#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)- & gt; Instance- & gt; CNT)

/**
* @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function.
* @param __HANDLE__ TIM handle.
* @param __AUTORELOAD__ specifies the Counter register new value.
* @retval None
*/
#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
do{ \
(__HANDLE__)- & gt; Instance- & gt; ARR = (__AUTORELOAD__); \
(__HANDLE__)- & gt; Init.Period = (__AUTORELOAD__); \
} while(0)

/**
* @brief Get the TIM Autoreload Register value on runtime.
* @param __HANDLE__ TIM handle.
* @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
*/
#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)- & gt; Instance- & gt; ARR)

/**
* @brief Set the TIM Clock Division value on runtime without calling another time any Init function.
* @param __HANDLE__ TIM handle.
* @param __CKD__ specifies the clock division value.
* This parameter can be one of the following value:
* @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
* @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
* @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
* @retval None
*/
#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
do{ \
(__HANDLE__)- & gt; Instance- & gt; CR1 & = (~TIM_CR1_CKD); \
(__HANDLE__)- & gt; Instance- & gt; CR1 |= (__CKD__); \
(__HANDLE__)- & gt; Init.ClockDivision = (__CKD__); \
} while(0)

/**
* @brief Get the TIM Clock Division value on runtime.
* @param __HANDLE__ TIM handle.
* @retval The clock division can be one of the following values:
* @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
* @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
* @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
*/
#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)- & gt; Instance- & gt; CR1 & TIM_CR1_CKD)

/**
* @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.
* @param __HANDLE__ TIM handle.
* @param __CHANNEL__ TIM Channels to be configured.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @param __ICPSC__ specifies the Input Capture4 prescaler new value.
* This parameter can be one of the following values:
* @arg TIM_ICPSC_DIV1: no prescaler
* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
* @retval None
*/
#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
do{ \
TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
} while(0)

/**
* @brief Get the TIM Input Capture prescaler on runtime.
* @param __HANDLE__ TIM handle.
* @param __CHANNEL__ TIM Channels to be configured.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: get input capture 1 prescaler value
* @arg TIM_CHANNEL_2: get input capture 2 prescaler value
* @arg TIM_CHANNEL_3: get input capture 3 prescaler value
* @arg TIM_CHANNEL_4: get input capture 4 prescaler value
* @retval The input capture prescaler can be one of the following values:
* @arg TIM_ICPSC_DIV1: no prescaler
* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
*/
#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)- & gt; Instance- & gt; CCMR1 & TIM_CCMR1_IC1PSC) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)- & gt; Instance- & gt; CCMR1 & TIM_CCMR1_IC2PSC) & gt; & gt; 8U) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)- & gt; Instance- & gt; CCMR2 & TIM_CCMR2_IC3PSC) :\
(((__HANDLE__)- & gt; Instance- & gt; CCMR2 & TIM_CCMR2_IC4PSC)) & gt; & gt; 8U)

/**
* @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
* @param __HANDLE__ TIM handle.
* @param __CHANNEL__ TIM Channels to be configured.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @param __COMPARE__ specifies the Capture Compare register new value.
* @retval None
*/
#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)- & gt; Instance- & gt; CCR1 = (__COMPARE__)) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)- & gt; Instance- & gt; CCR2 = (__COMPARE__)) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)- & gt; Instance- & gt; CCR3 = (__COMPARE__)) :\
((__HANDLE__)- & gt; Instance- & gt; CCR4 = (__COMPARE__)))

/**
* @brief Get the TIM Capture Compare Register value on runtime.
* @param __HANDLE__ TIM handle.
* @param __CHANNEL__ TIM Channel associated with the capture compare register
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: get capture/compare 1 register value
* @arg TIM_CHANNEL_2: get capture/compare 2 register value
* @arg TIM_CHANNEL_3: get capture/compare 3 register value
* @arg TIM_CHANNEL_4: get capture/compare 4 register value
* @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
*/
#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)- & gt; Instance- & gt; CCR1) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)- & gt; Instance- & gt; CCR2) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)- & gt; Instance- & gt; CCR3) :\
((__HANDLE__)- & gt; Instance- & gt; CCR4))

/**
* @brief Set the TIM Output compare preload.
* @param __HANDLE__ TIM handle.
* @param __CHANNEL__ TIM Channels to be configured.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval None
*/
#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)- & gt; Instance- & gt; CCMR1 |= TIM_CCMR1_OC1PE) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)- & gt; Instance- & gt; CCMR1 |= TIM_CCMR1_OC2PE) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)- & gt; Instance- & gt; CCMR2 |= TIM_CCMR2_OC3PE) :\
((__HANDLE__)- & gt; Instance- & gt; CCMR2 |= TIM_CCMR2_OC4PE))

/**
* @brief Reset the TIM Output compare preload.
* @param __HANDLE__ TIM handle.
* @param __CHANNEL__ TIM Channels to be configured.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval None
*/
#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)- & gt; Instance- & gt; CCMR1 & = ~TIM_CCMR1_OC1PE) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)- & gt; Instance- & gt; CCMR1 & = ~TIM_CCMR1_OC2PE) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)- & gt; Instance- & gt; CCMR2 & = ~TIM_CCMR2_OC3PE) :\
((__HANDLE__)- & gt; Instance- & gt; CCMR2 & = ~TIM_CCMR2_OC4PE))

/**
* @brief Enable fast mode for a given channel.
* @param __HANDLE__ TIM handle.
* @param __CHANNEL__ TIM Channels to be configured.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @note When fast mode is enabled an active edge on the trigger input acts
* like a compare match on CCx output. Delay to sample the trigger
* input and to activate CCx output is reduced to 3 clock cycles.
* @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode.
* @retval None
*/
#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)- & gt; Instance- & gt; CCMR1 |= TIM_CCMR1_OC1FE) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)- & gt; Instance- & gt; CCMR1 |= TIM_CCMR1_OC2FE) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)- & gt; Instance- & gt; CCMR2 |= TIM_CCMR2_OC3FE) :\
((__HANDLE__)- & gt; Instance- & gt; CCMR2 |= TIM_CCMR2_OC4FE))

/**
* @brief Disable fast mode for a given channel.
* @param __HANDLE__ TIM handle.
* @param __CHANNEL__ TIM Channels to be configured.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @note When fast mode is disabled CCx output behaves normally depending
* on counter and CCRx values even when the trigger is ON. The minimum
* delay to activate CCx output when an active edge occurs on the
* trigger input is 5 clock cycles.
* @retval None
*/
#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)- & gt; Instance- & gt; CCMR1 & = ~TIM_CCMR1_OC1FE) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)- & gt; Instance- & gt; CCMR1 & = ~TIM_CCMR1_OC2FE) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)- & gt; Instance- & gt; CCMR2 & = ~TIM_CCMR2_OC3FE) :\
((__HANDLE__)- & gt; Instance- & gt; CCMR2 & = ~TIM_CCMR2_OC4FE))

/**
* @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register.
* @param __HANDLE__ TIM handle.
* @note When the URS bit of the TIMx_CR1 register is set, only counter
* overflow/underflow generates an update interrupt or DMA request (if
* enabled)
* @retval None
*/
#define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)- & gt; Instance- & gt; CR1|= TIM_CR1_URS)

/**
* @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
* @param __HANDLE__ TIM handle.
* @note When the URS bit of the TIMx_CR1 register is reset, any of the
* following events generate an update interrupt or DMA request (if
* enabled):
* _ Counter overflow underflow
* _ Setting the UG bit
* _ Update generation through the slave mode controller
* @retval None
*/
#define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)- & gt; Instance- & gt; CR1 & =~TIM_CR1_URS)

/**
* @brief Set the TIM Capture x input polarity on runtime.
* @param __HANDLE__ TIM handle.
* @param __CHANNEL__ TIM Channels to be configured.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @param __POLARITY__ Polarity for TIx source
* @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
* @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
* @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
* @retval None
*/
#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
do{ \
TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
}while(0)

/**
* @}
*/
/* End of exported macros ----------------------------------------------------*/

/* Private constants ---------------------------------------------------------*/
/** @defgroup TIM_Private_Constants TIM Private Constants
* @{
*/
/* The counter of a timer instance is disabled only if all the CCx and CCxN
channels have been disabled */
#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
/**
* @}
*/
/* End of private constants --------------------------------------------------*/

/* Private macros ------------------------------------------------------------*/
/** @defgroup TIM_Private_Macros TIM Private Macros
* @{
*/
#define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) || \
((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) || \
((__MODE__) == TIM_CLEARINPUTSOURCE_OCREFCLR))

#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \
((__BASE__) == TIM_DMABASE_CR2) || \
((__BASE__) == TIM_DMABASE_SMCR) || \
((__BASE__) == TIM_DMABASE_DIER) || \
((__BASE__) == TIM_DMABASE_SR) || \
((__BASE__) == TIM_DMABASE_EGR) || \
((__BASE__) == TIM_DMABASE_CCMR1) || \
((__BASE__) == TIM_DMABASE_CCMR2) || \
((__BASE__) == TIM_DMABASE_CCER) || \
((__BASE__) == TIM_DMABASE_CNT) || \
((__BASE__) == TIM_DMABASE_PSC) || \
((__BASE__) == TIM_DMABASE_ARR) || \
((__BASE__) == TIM_DMABASE_RCR) || \
((__BASE__) == TIM_DMABASE_CCR1) || \
((__BASE__) == TIM_DMABASE_CCR2) || \
((__BASE__) == TIM_DMABASE_CCR3) || \
((__BASE__) == TIM_DMABASE_CCR4) || \
((__BASE__) == TIM_DMABASE_BDTR))

#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFF00U) == 0x00000000U) & & ((__SOURCE__) != 0x00000000U))

#define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \
((__MODE__) == TIM_COUNTERMODE_DOWN) || \
((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \
((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \
((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))

#define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
((__DIV__) == TIM_CLOCKDIVISION_DIV4))

#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))

#define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \
((__STATE__) == TIM_OCFAST_ENABLE))

#define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \
((__POLARITY__) == TIM_OCPOLARITY_LOW))

#define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \
((__POLARITY__) == TIM_OCNPOLARITY_LOW))

#define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \
((__STATE__) == TIM_OCIDLESTATE_RESET))

#define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \
((__STATE__) == TIM_OCNIDLESTATE_RESET))

#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \
((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING))

#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \
((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \
((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))

#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \
((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \
((__SELECTION__) == TIM_ICSELECTION_TRC))

#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \
((__PRESCALER__) == TIM_ICPSC_DIV2) || \
((__PRESCALER__) == TIM_ICPSC_DIV4) || \
((__PRESCALER__) == TIM_ICPSC_DIV8))

#define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \
((__MODE__) == TIM_OPMODE_REPETITIVE))

#define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \
((__MODE__) == TIM_ENCODERMODE_TI2) || \
((__MODE__) == TIM_ENCODERMODE_TI12))

#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) & & ((__SOURCE__) != 0x00000000U))

#define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
((__CHANNEL__) == TIM_CHANNEL_2) || \
((__CHANNEL__) == TIM_CHANNEL_3) || \
((__CHANNEL__) == TIM_CHANNEL_4) || \
((__CHANNEL__) == TIM_CHANNEL_ALL))

#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
((__CHANNEL__) == TIM_CHANNEL_2))

#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
((__CHANNEL__) == TIM_CHANNEL_2) || \
((__CHANNEL__) == TIM_CHANNEL_3))

#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))

#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \
((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \
((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \
((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))

#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \
((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \
((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \
((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))

#define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) & lt; = 0xFU)

#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))

#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \
((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \
((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \
((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))

#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) & lt; = 0xFU)

#define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \
((__STATE__) == TIM_OSSR_DISABLE))

#define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \
((__STATE__) == TIM_OSSI_DISABLE))

#define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \
((__LEVEL__) == TIM_LOCKLEVEL_1) || \
((__LEVEL__) == TIM_LOCKLEVEL_2) || \
((__LEVEL__) == TIM_LOCKLEVEL_3))

#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) & lt; = 0xFUL)


#define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \
((__STATE__) == TIM_BREAK_DISABLE))

#define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \
((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))

#define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \
((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))

#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \
((__SOURCE__) == TIM_TRGO_ENABLE) || \
((__SOURCE__) == TIM_TRGO_UPDATE) || \
((__SOURCE__) == TIM_TRGO_OC1) || \
((__SOURCE__) == TIM_TRGO_OC1REF) || \
((__SOURCE__) == TIM_TRGO_OC2REF) || \
((__SOURCE__) == TIM_TRGO_OC3REF) || \
((__SOURCE__) == TIM_TRGO_OC4REF))

#define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \
((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))

#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \
((__MODE__) == TIM_SLAVEMODE_RESET) || \
((__MODE__) == TIM_SLAVEMODE_GATED) || \
((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \
((__MODE__) == TIM_SLAVEMODE_EXTERNAL1))

#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \
((__MODE__) == TIM_OCMODE_PWM2))

#define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \
((__MODE__) == TIM_OCMODE_ACTIVE) || \
((__MODE__) == TIM_OCMODE_INACTIVE) || \
((__MODE__) == TIM_OCMODE_TOGGLE) || \
((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \
((__MODE__) == TIM_OCMODE_FORCED_INACTIVE))

#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
((__SELECTION__) == TIM_TS_ITR1) || \
((__SELECTION__) == TIM_TS_ITR2) || \
((__SELECTION__) == TIM_TS_ITR3) || \
((__SELECTION__) == TIM_TS_TI1F_ED) || \
((__SELECTION__) == TIM_TS_TI1FP1) || \
((__SELECTION__) == TIM_TS_TI2FP2) || \
((__SELECTION__) == TIM_TS_ETRF))

#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
((__SELECTION__) == TIM_TS_ITR1) || \
((__SELECTION__) == TIM_TS_ITR2) || \
((__SELECTION__) == TIM_TS_ITR3) || \
((__SELECTION__) == TIM_TS_NONE))

#define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \
((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \
((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \
((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE ))

#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \
((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \
((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \
((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))

#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) & lt; = 0xFU)

#define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))

#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))

#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) & gt; = 0x1U) & & ((LENGTH) & lt; 0x10000U))

#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) & lt; = 0xFU)

#define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) & lt; = 0xFFU)

#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) ((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER)

#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)- & gt; Instance- & gt; CCMR1 |= (__ICPSC__)) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)- & gt; Instance- & gt; CCMR1 |= ((__ICPSC__) & lt; & lt; 8U)) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)- & gt; Instance- & gt; CCMR2 |= (__ICPSC__)) :\
((__HANDLE__)- & gt; Instance- & gt; CCMR2 |= ((__ICPSC__) & lt; & lt; 8U)))

#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)- & gt; Instance- & gt; CCMR1 & = ~TIM_CCMR1_IC1PSC) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)- & gt; Instance- & gt; CCMR1 & = ~TIM_CCMR1_IC2PSC) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)- & gt; Instance- & gt; CCMR2 & = ~TIM_CCMR2_IC3PSC) :\
((__HANDLE__)- & gt; Instance- & gt; CCMR2 & = ~TIM_CCMR2_IC4PSC))

#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)- & gt; Instance- & gt; CCER |= (__POLARITY__)) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)- & gt; Instance- & gt; CCER |= ((__POLARITY__) & lt; & lt; 4U)) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)- & gt; Instance- & gt; CCER |= ((__POLARITY__) & lt; & lt; 8U)) :\
((__HANDLE__)- & gt; Instance- & gt; CCER |= (((__POLARITY__) & lt; & lt; 12U))))

#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)- & gt; Instance- & gt; CCER & = ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)- & gt; Instance- & gt; CCER & = ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)- & gt; Instance- & gt; CCER & = ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
((__HANDLE__)- & gt; Instance- & gt; CCER & = ~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))

#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\
(((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)- & gt; ChannelState[0] :\
((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)- & gt; ChannelState[1] :\
((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)- & gt; ChannelState[2] :\
(__HANDLE__)- & gt; ChannelState[3])

#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)- & gt; ChannelState[0] = (__CHANNEL_STATE__)) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)- & gt; ChannelState[1] = (__CHANNEL_STATE__)) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)- & gt; ChannelState[2] = (__CHANNEL_STATE__)) :\
((__HANDLE__)- & gt; ChannelState[3] = (__CHANNEL_STATE__)))

#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \
(__HANDLE__)- & gt; ChannelState[0] = (__CHANNEL_STATE__); \
(__HANDLE__)- & gt; ChannelState[1] = (__CHANNEL_STATE__); \
(__HANDLE__)- & gt; ChannelState[2] = (__CHANNEL_STATE__); \
(__HANDLE__)- & gt; ChannelState[3] = (__CHANNEL_STATE__); \
} while(0)

#define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\
(((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)- & gt; ChannelNState[0] :\
((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)- & gt; ChannelNState[1] :\
((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)- & gt; ChannelNState[2] :\
(__HANDLE__)- & gt; ChannelNState[3])

#define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)- & gt; ChannelNState[0] = (__CHANNEL_STATE__)) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)- & gt; ChannelNState[1] = (__CHANNEL_STATE__)) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)- & gt; ChannelNState[2] = (__CHANNEL_STATE__)) :\
((__HANDLE__)- & gt; ChannelNState[3] = (__CHANNEL_STATE__)))

#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \
(__HANDLE__)- & gt; ChannelNState[0] = (__CHANNEL_STATE__); \
(__HANDLE__)- & gt; ChannelNState[1] = (__CHANNEL_STATE__); \
(__HANDLE__)- & gt; ChannelNState[2] = (__CHANNEL_STATE__); \
(__HANDLE__)- & gt; ChannelNState[3] = (__CHANNEL_STATE__); \
} while(0)

/**
* @}
*/
/* End of private macros -----------------------------------------------------*/

/* Include TIM HAL Extended module */
#include " stm32f0xx_hal_tim_ex.h "

/* Exported functions --------------------------------------------------------*/
/** @addtogroup TIM_Exported_Functions TIM Exported Functions
* @{
*/

/** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions
* @brief Time Base functions
* @{
*/
/* Time Base functions ********************************************************/
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
/**
* @}
*/

/** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions
* @brief TIM Output Compare functions
* @{
*/
/* Timer Output Compare functions *********************************************/
HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
/**
* @}
*/

/** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions
* @brief TIM PWM functions
* @{
*/
/* Timer PWM functions ********************************************************/
HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
/**
* @}
*/

/** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions
* @brief TIM Input Capture functions
* @{
*/
/* Timer Input Capture functions **********************************************/
HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
/**
* @}
*/

/** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions
* @brief TIM One Pulse functions
* @{
*/
/* Timer One Pulse functions **************************************************/
HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
/**
* @}
*/

/** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions
* @brief TIM Encoder functions
* @{
*/
/* Timer Encoder functions ****************************************************/
HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig);
HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
uint32_t *pData2, uint16_t Length);
HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
/**
* @}
*/

/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management
* @brief IRQ handler management
* @{
*/
/* Interrupt Handler functions ***********************************************/
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
/**
* @}
*/

/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
* @brief Peripheral Control functions
* @{
*/
/* Control functions *********************************************************/
HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
uint32_t OutputChannel, uint32_t InputChannel);
HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig,
uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig);
HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength,
uint32_t DataLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength,
uint32_t DataLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
/**
* @}
*/

/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
* @brief TIM Callbacks functions
* @{
*/
/* Callback in non blocking modes (Interrupt and DMA) *************************/
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim);
void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim);
void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim);
void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim);
void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);

/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
pTIM_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */

/**
* @}
*/

/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
* @brief Peripheral State functions
* @{
*/
/* Peripheral State functions ************************************************/
HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);

/* Peripheral Channel state functions ************************************************/
HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim);
HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim);
/**
* @}
*/

/**
* @}
*/
/* End of exported functions -------------------------------------------------*/

/* Private functions----------------------------------------------------------*/
/** @defgroup TIM_Private_Functions TIM Private Functions
* @{
*/
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);

void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);
void TIM_DMAError(DMA_HandleTypeDef *hdma);
void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma);
void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState);

#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
void TIM_ResetCallback(TIM_HandleTypeDef *htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */

/**
* @}
*/
/* End of private functions --------------------------------------------------*/

/**
* @}
*/

/**
* @}
*/

#ifdef __cplusplus
}
#endif

#endif /* STM32F0xx_HAL_TIM_H */

/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

ssr_test.zip > stm32f0xx_hal_def.h

/**
******************************************************************************
* @file stm32f0xx_hal_def.h
* @author MCD Application Team
* @brief This file contains HAL common defines, enumeration, macros and
* structures definitions.
******************************************************************************
* @attention
*
* & lt; h2 & gt; & lt; center & gt; & copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved. & lt; /center & gt; & lt; /h2 & gt;
*
* This software component is licensed by ST under BSD 3-Clause license,
* the " License " ; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/

/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F0xx_HAL_DEF
#define __STM32F0xx_HAL_DEF

#ifdef __cplusplus
extern " C " {
#endif

/* Includes ------------------------------------------------------------------*/
#include " stm32f0xx.h "
#include " Legacy/stm32_hal_legacy.h "
#include & lt; stddef.h & gt;

/* Exported types ------------------------------------------------------------*/

/**
* @brief HAL Status structures definition
*/
typedef enum
{
HAL_OK = 0x00U,
HAL_ERROR = 0x01U,
HAL_BUSY = 0x02U,
HAL_TIMEOUT = 0x03U
} HAL_StatusTypeDef;

/**
* @brief HAL Lock structures definition
*/
typedef enum
{
HAL_UNLOCKED = 0x00U,
HAL_LOCKED = 0x01U
} HAL_LockTypeDef;

/* Exported macro ------------------------------------------------------------*/

#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */

#define HAL_MAX_DELAY 0xFFFFFFFFU

#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT))
#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U)

#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \
do{ \
(__HANDLE__)- & gt; __PPP_DMA_FIELD__ = & (__DMA_HANDLE__); \
(__DMA_HANDLE__).Parent = (__HANDLE__); \
} while(0U)

/** @brief Reset the Handle's State field.
* @param __HANDLE__ specifies the Peripheral Handle.
* @note This macro can be used for the following purpose:
* - When the Handle is declared as local variable; before passing it as parameter
* to HAL_PPP_Init() for the first time, it is mandatory to use this macro
* to set to 0 the Handle's " State " field.
* Otherwise, " State " field may have any random value and the first time the function
* HAL_PPP_Init() is called, the low level hardware initialization will be missed
* (i.e. HAL_PPP_MspInit() will not be executed).
* - When there is a need to reconfigure the low level hardware: instead of calling
* HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
* In this later function, when the Handle's " State " field is set to 0, it will execute the function
* HAL_PPP_MspInit() which will reconfigure the low level hardware.
* @retval None
*/
#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)- & gt; State = 0U)

#if (USE_RTOS == 1U)
/* Reserved for future use */
#error " USE_RTOS should be 0 in the current HAL release "
#else
#define __HAL_LOCK(__HANDLE__) \
do{ \
if((__HANDLE__)- & gt; Lock == HAL_LOCKED) \
{ \
return HAL_BUSY; \
} \
else \
{ \
(__HANDLE__)- & gt; Lock = HAL_LOCKED; \
} \
}while (0U)

#define __HAL_UNLOCK(__HANDLE__) \
do{ \
(__HANDLE__)- & gt; Lock = HAL_UNLOCKED; \
}while (0U)
#endif /* USE_RTOS */

#if defined (__ARMCC_VERSION) & & (__ARMCC_VERSION & gt; = 6010050) /* ARM Compiler V6 */
#ifndef __weak
#define __weak __attribute__((weak))
#endif
#ifndef __packed
#define __packed __attribute__((packed))
#endif
#elif defined ( __GNUC__ ) & & !defined (__CC_ARM) /* GNU Compiler */
#ifndef __weak
#define __weak __attribute__((weak))
#endif /* __weak */
#ifndef __packed
#define __packed __attribute__((__packed__))
#endif /* __packed */
#endif /* __GNUC__ */


/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive " #pragma data_alignment=4 " must be used instead */
#if defined (__ARMCC_VERSION) & & (__ARMCC_VERSION & gt; = 6010050) /* ARM Compiler V6 */
#ifndef __ALIGN_BEGIN
#define __ALIGN_BEGIN
#endif
#ifndef __ALIGN_END
#define __ALIGN_END __attribute__ ((aligned (4)))
#endif
#elif defined ( __GNUC__ ) & & !defined (__CC_ARM) /* GNU Compiler */
#ifndef __ALIGN_END
#define __ALIGN_END __attribute__ ((aligned (4)))
#endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN
#define __ALIGN_BEGIN
#endif /* __ALIGN_BEGIN */
#else
#ifndef __ALIGN_END
#define __ALIGN_END
#endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN
#if defined (__CC_ARM) /* ARM Compiler V5*/
#define __ALIGN_BEGIN __align(4)
#elif defined (__ICCARM__) /* IAR Compiler */
#define __ALIGN_BEGIN
#endif /* __CC_ARM */
#endif /* __ALIGN_BEGIN */
#endif /* __GNUC__ */

/**
* @brief __NOINLINE definition
*/
#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) & & (__ARMCC_VERSION & gt; = 6010050)) || defined ( __GNUC__ )
/* ARM V4/V5 and V6 & GNU Compiler
-------------------------------
*/
#define __NOINLINE __attribute__ ( (noinline) )

#elif defined ( __ICCARM__ )
/* ICCARM Compiler
---------------
*/
#define __NOINLINE _Pragma( " optimize = no_inline " )

#endif

#ifdef __cplusplus
}
#endif

#endif /* ___STM32F0xx_HAL_DEF */

/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

ssr_test.zip > stm32f0xx_hal_cortex.h

/**
******************************************************************************
* @file stm32f0xx_hal_cortex.h
* @author MCD Application Team
* @brief Header file of CORTEX HAL module.
******************************************************************************
* @attention
*
* & lt; h2 & gt; & lt; center & gt; & copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved. & lt; /center & gt; & lt; /h2 & gt;
*
* This software component is licensed by ST under BSD 3-Clause license,
* the " License " ; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/

/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F0xx_HAL_CORTEX_H
#define __STM32F0xx_HAL_CORTEX_H

#ifdef __cplusplus
extern " C " {
#endif

/* Includes ------------------------------------------------------------------*/
#include " stm32f0xx_hal_def.h "

/** @addtogroup STM32F0xx_HAL_Driver
* @{
*/

/** @addtogroup CORTEX CORTEX
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/

/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
* @{
*/

/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source
* @{
*/
#define SYSTICK_CLKSOURCE_HCLK_DIV8 (0x00000000U)
#define SYSTICK_CLKSOURCE_HCLK (0x00000004U)

/**
* @}
*/

/**
* @}
*/

/* Exported Macros -----------------------------------------------------------*/

/* Exported functions --------------------------------------------------------*/
/** @addtogroup CORTEX_Exported_Functions CORTEX Exported Functions
* @{
*/
/** @addtogroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
* @{
*/
/* Initialization and de-initialization functions *******************************/
void HAL_NVIC_SetPriority(IRQn_Type IRQn,uint32_t PreemptPriority, uint32_t SubPriority);
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
void HAL_NVIC_SystemReset(void);
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
/**
* @}
*/

/** @addtogroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
* @brief Cortex control functions
* @{
*/

/* Peripheral Control functions *************************************************/
uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn);
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
void HAL_SYSTICK_IRQHandler(void);
void HAL_SYSTICK_Callback(void);
/**
* @}
*/

/**
* @}
*/

/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
* @{
*/
#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) & lt; 0x4)

#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) & gt; = 0x00)

#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
/**
* @}
*/

/**
* @}
*/

/**
* @}
*/

#ifdef __cplusplus
}
#endif

#endif /* __STM32F0xx_HAL_CORTEX_H */


/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/