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BK2461
BK2461
Datasheet
FLIP51 MCU+RF
Beken Corporation
Building 41, 1387 Zhangdong Road, Zhangjiang High-Tech Park, Pudong New District,
Shanghai, China
Tel： (86)21 51086811
Fax： (86)21 60871089
This document contains information that may be proprietary to, and/or secrets of, Beken Corporation. The
contents of this document should not be disclosed outside the companies without specific written permission.
Disclaimer: Descriptions of specific implementations are for illustrative purpose only, actual hardware
implementation may differ.
© 2015 Beken Corporation
Proprietary and Confidential
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BK2461
Revision History
Version
0.1
0.2
Date
Nov. 20,2014
Mar. 20,2015
© 2015 Beken Corporation
Author(s)
Lizhen
Lizhen
Description
Initial flash version
Update version
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BK2461
Table of Contents
1
2
3
4
Introduction ................................................................................................................. 9
Feature......................................................................................................................... 9
Block Diagram .......................................................................................................... 10
PIN information ........................................................................................................ 11
4.1 BK2461_QFN24 ................................................................................................. 11
4.2 BK2461_SOP16 .................................................................................................. 13
5
FLIP51 Micro-Controller .......................................................................................... 14
5.1 Instruction Set ..................................................................................................... 14
5.2 MCU diagram ..................................................................................................... 15
6
FLIP8051 address space ........................................................................................... 17
6.1 Overview ............................................................................................................. 17
6.2 Program Memory (CODE space)........................................................................ 17
6.3 External Data Memory (XDATA space) ............................................................ 17
6.4 Internal Data Memory (IDATA space) ............................................................... 18
6.4.1 Internal Data memory organization ............................................................ 18
6.4.2 Internal ram: lower 128 byes....................................................................... 19
6.4.3 Internal Ram: Upper 128 Bytes ................................................................... 19
6.4.4 The Stack and the stack pointer ................................................................... 19
6.4.5 Special Function Registers........................................................................... 20
6.4.6 SFR table for MCU part............................................................................... 24
7
Power management ................................................................................................... 26
7.1 Power Control Register ....................................................................................... 26
7.2 Work State .......................................................................................................... 27
7.2.1 IDLE MODE................................................................................................ 27
7.2.2 SLEEP MODE ............................................................................................. 27
7.2.3 DEEP SLEEP MODE .................................................................................. 27
7.2.4 Wake Up ...................................................................................................... 28
8
Clock system ............................................................................................................. 28
8.1 System clock topology ........................................................................................ 28
8.2 Peripherals clock management ........................................................................... 29
9
Reset system.............................................................................................................. 30
10 Interrupt system ........................................................................................................ 31
10.1 7.1 Introduction ................................................................................................... 31
10.1.1 Interrupt source ............................................................................................ 31
10.1.2 Int0_n and int1_n ......................................................................................... 32
10.1.3 Intnmi interrupt ............................................................................................ 33
10.1.4 Additional interrupts .................................................................................... 33
10.1.5 Timer Interrupts ........................................................................................... 34
10.1.6 Serial Port Interrupt...................................................................................... 34
10.1.7 TRAP interrupt............................................................................................. 34
10.2 Interrupt enable ................................................................................................... 34
10.3 Interrupt priority.................................................................................................. 35
10.4 Interrupt blocking conditions .............................................................................. 37
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BK2461
11
Peripheral module ..................................................................................................... 38
11.1 OVERVIEW ....................................................................................................... 38
11.2 UART .................................................................................................................. 38
11.2.1 Serial port overview ..................................................................................... 38
11.2.2 Operation mode ............................................................................................ 38
11.2.3 Programming the Baud Rate ........................................................................ 40
11.2.4 Serial port registers ...................................................................................... 41
11.1 ADC .................................................................................................................... 43
11.1.1 introduction .................................................................................................. 43
11.1.2 Register explain ........................................................................................... 43
11.1.3 Sample rate: ................................................................................................. 44
11.1.4 ADC usage ................................................................................................... 44
11.2 PWM ................................................................................................................... 45
11.2.1 OVERVIEW ................................................................................................ 45
11.2.2 FUNCTIONAL DESCRIPTION ................................................................. 45
11.2.3 Frequency of PWM ...................................................................................... 46
11.3 I2C master ........................................................................................................... 47
11.3.1 Overview ...................................................................................................... 47
11.3.2 List of I2CM register ................................................................................... 47
11.3.3 I2C frame data format .................................................................................. 51
11.3.4 Acknowledge ............................................................................................... 52
11.3.5 Clock synchronization and wait state .......................................................... 53
11.3.6 Master mode: Transmission ......................................................................... 54
11.3.7 Master mode: Reception .............................................................................. 58
11.3.8 Stop and Repeated Start ............................................................................... 58
11.3.9 Reception FSM ............................................................................................ 60
11.3.10 Data Handling .............................................................................................. 60
11.3.11 Software Reset ............................................................................................. 61
11.4 Ext_timer............................................................................................................. 62
11.5 WDT ................................................................................................................... 63
12 BK2461 RF transceiver............................................................................................. 64
12.1 General Description ............................................................................................ 64
12.2 Abbreviations ...................................................................................................... 66
12.3 State Control ....................................................................................................... 67
12.3.1 State Control Diagram ................................................................................. 67
12.3.2 Power Down Mode ...................................................................................... 68
12.3.3 Standby-I Mode ........................................................................................... 68
12.3.4 Standby-II Mode .......................................................................................... 68
12.3.5 TX Mode ...................................................................................................... 68
12.3.6 RX Mode ...................................................................................................... 69
12.4 Packet Processing................................................................................................ 70
12.4.1 Packet Format .............................................................................................. 70
12.4.2 Packet Handling ........................................................................................... 72
12.5 Data and Control Interface .................................................................................. 73
12.5.1 TX/RX FIFO ................................................................................................ 73
12.5.2 Interrupt........................................................................................................ 74
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BK2461
12.6 RF Command ...................................................................................................... 75
12.7 Register Map ....................................................................................................... 77
12.7.1 Digital Register ............................................................................................ 77
12.7.2 Analog Register ........................................................................................... 84
12.7.3 TX power control setting ............................................................................. 85
13 Typical Application Schematic ................................................................................. 88
14 Package Information ................................................................................................. 89
15 Solder Reflow Profile ............................................................................................... 93
16 Order Information ..................................................................................................... 94
17 Solder Reflow Profile ............................................................................................... 94
18 Contact Information .................................................................................................. 95
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BK2461
v0.3
List of Figures
FIGURE 1BK2461 BLOCK DIAGRAM .............................................................................................................. 10
FIGURE 2 BK2461-QFN ................................................................................................................................. 11
FIGURE 3 BK2461-SOP .................................................................................................................................. 13
FIGURE 4 FLIP51 ARCHITECTURE .................................................................................................................. 15
FIGURE 5 FLIP51 SPACE ................................................................................................................................ 17
FIGURE 6 INTERNAL DATA MEMORY ........................................................................................................... 19
FIGURE 7 INTERNAL RAM LOWER 128 BYTES .............................................................................................. 19
FIGURE 8 WAKE UP PROCESS ....................................................................................................................... 28
FIGURE 9 CLOCK TOPOLOGY......................................................................................................................... 29
FIGURE 10 SERIAL TRANSMIT MODE 1 ........................................................................................................ 39
FIGURE 11 SERIAL RECEIVE MODE 1 ............................................................................................................ 39
FIGURE 12 SERIAL TRANSMIT MODE 2 ........................................................................................................ 40
FIGURE 13 SERIAL RECEIVE MODE 2 ............................................................................................................ 40
FIGURE 14 ADC ............................................................................................................................................. 43
FIGURE 15 PWM PARAMETER ..................................................................................................................... 46
FIGURE 16 COMPLETE DATA TRANSFER ....................................................................................................... 51
FIGURE 17 " NOT ACKNOWLEDGE " BY SLAVE .............................................................................................. 52
FIGURE 18 " NOT ACKNOWLEDGE " BY MASTER (END OF TRANSMISSION) ................................................ 53
FIGURE 19 CLOCK SYNCHRONIZATION AS HANDSHAKE ............................................................................. 53
FIGURE 20 CLOCK SYNCHRONIZATION ........................................................................................................ 54
FIGURE 21 TYPICAL TRANSMISSION ............................................................................................................ 54
FIGURE 22 REPEATED START OR STOP CONDITION AFTER LAST BYTE ....................................................... 55
FIGURE 23 TRANSMISSION FSM .................................................................................................................. 57
FIGURE 24 TYPICAL RECEPTION ................................................................................................................... 58
FIGURE 25 REPEATED START OR STOP CONDITION AFTER LAST BYTE ....................................................... 59
FIGURE 26 RECEPTION FSM ......................................................................................................................... 60
FIGURE 27 BK2461 RF BLOCK DIAGRAM ...................................................................................................... 65
FIGURE 28 PTX (PRIM_RX=0) STATE CONTROL DIAGRAM ........................................................................... 67
FIGURE 29 PRX (PRIM_RX=1) STATE CONTROL DIAGRAM ........................................................................... 68
FIGURE 30 PACKET FORMAT......................................................................................................................... 70
FIGURE 31 CLASSIFICATION REFLOW PROFILE ............................................................................................. 93
BK2461
List of tables
TABLE 1 PIN DEFINITION .............................................................................................................................. 12
TABLE 2 PIN DEFINITION .............................................................................................................................. 14
TABLE 3 SPECIAL FUNCTION REGISTERS MEMORY MAP ............................................................................ 24
TABLE 4 CORE SFRS ...................................................................................................................................... 24
TABLE 5 ADDITIONAL INTERRUPT SFRS ....................................................................................................... 24
TABLE 6 I/O PORTS SFRS .............................................................................................................................. 25
TABLE 7 SERIAL PORT SFRS .......................................................................................................................... 25
TABLE 8 TIMERS SFRS ................................................................................................................................... 26
TABLE 9 BIRD SFRS ....................................................................................................................................... 26
TABLE 10 POWER MANAGEMENT REGISTER................................................................................................ 26
TABLE 11 CLOCK ENABLE REGISTER.............................................................................................................. 29
TABLE 12 INTERRUPT SOURCES ................................................................................................................... 32
TABLE 13 TIMER/COUNTER CONTROL REGISTER (TCON LOW)................................................................... 33
TABLE 14 ADDITIONAL INTERRUPT REGISTERS ........................................................................................... 33
TABLE 15 ADDITIONAL INTERRUPT FLAG REGISTER (AIF) ........................................................................... 34
TABLE 16 INTERRUPT ENABLE 0 REGISTER (IE0) ......................................................................................... 35
TABLE 17 ADDITIONAL INTERRUPT ENABLE REGISTER (AIE) ...................................................................... 35
TABLE 18 INTERRUPT PRIORITY LEVELS AND VECTOR ADDRESSES ............................................................ 36
TABLE 19 INTERRUPT PRIORITY WITHIN A SAME PRIORITY LEVEL (0 OR 1) .............................................. 37
TABLE 20 INTERRUPT PRIORITY REGISTER (IP)............................................................................................ 37
TABLE 21 ADDITIONAL INTERRUPT PRIORITY REGISTER (AIP) ................................................................... 37
TABLE 22 SERIAL PORT REGISTERS .............................................................................................................. 41
TABLE 23 SERIAL PORT CONTROL REGISTER (SCON) ................................................................................... 42
TABLE 26 ADC REGISTER .............................................................................................................................. 43
TABLE 27 ADC REGISTER ............................................................................................................................... 44
TABLE 28 ADC 的 SFR ................................................................................................................................... 44
TABLE 29 ADC REGISTER ............................................................................................................................... 44
TABLE 30 ADC REGISTER ............................................................................................................................... 44
TABLE 31 ADC ANALOG REGISTER ................................................................................................................ 45
TABLE 24 PWM REGISTER ADDRESS ............................................................................................................ 45
TABLE 25 I2CM REGISTER............................................................................................................................. 47
TABLE 26 I2CM CONTROL REGISTER (MCON) .............................................................................................. 48
TABLE 27 I2CM RECEIVE REGISTER (MRXBUF) ............................................................................................ 48
TABLE 28 I2CM TRANSMIT BUFFER (MTXBUF)............................................................................................ 48
TABLE 29 I2CM MPRESC REGISTER ............................................................................................................. 48
TABLE 30 I2CM STATUS REGISTER 0 (MSTAT0) ........................................................................................... 49
TABLE 31 I2CM STATUS REGISTER 1 (MSTAT1) ........................................................................................... 49
TABLE 32 I2CM INTERRUPT ENABLE REGISTER 0 (MIEN0) .......................................................................... 50
TABLE 33 I2CM INTERRUPT ENABLE REGISTER 1 (MIEN1) .......................................................................... 50
TABLE 34 I2CM CALL ADDRESS REGISTER (MCADDR) ................................................................................ 51
TABLE 35 RESERVED ADDRESSES FOR I2CANSACTIONS ............................................................................. 52
TABLE 36 RTC REGISTER ............................................................................................................................... 62
TABLE 20 WATCH DOG REGISTER ................................................................................................................. 63
TABLE 21 THE PRESCALE OF WATCH DOG CLOCK ........................................................................................ 63
TABLE 37 RF COMMAND .............................................................................................................................. 76
TABLE 38 DIGITAL REGISTER ......................................................................................................................... 84
TABLE 39 REGISTER BANK 1 .......................................................................................................................... 85
TABLE 40 TX POWER SETTING ...................................................................................................................... 85
TABLE 41 SOLDER REFLOW PROFILE............................................................................................................. 93
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BK2461
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BK2461
1
Introduction
The BK2461 is a RF SOC chip, which embedded the newest FLIP51 processor.
2 Feature
1.9 V to 3.6 V power supply
FLIP51 MCU compatible with 8051
A 4-stage pipeline architecture that enables to execute most of the instructions in a single
clock cycle.
8k bytes OTP for program
256 Bytes IRAM and 512k Bytes SRAM
Embedded three Timer/Counter
Support UART I2C interface
low power consumption, embedded with 32k RC oscillator
Total 9/18 GPIO available
The most 5 PWM available
The embedded BIRD (Built-In Real-time Debugger) system for online debug
8+1 channel ADC embedded
Integrated 2.4G RF transceiver
The max output power can be 12DBm
low power consumption, embedded with 32k RC oscillator
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BK2461
3
Block Diagram
Timer
RF-Tranceiver
BIRD
PWM
RAM
(8K)
OTP
(8k)
WDT
FLIP51
XRAM(512)
ADC
Uart
I2C
IRAM(256)
RTC
Power Managerment
16M
32K
BOR
Interrupt
Control
GPIO
24 I/0 Crossbar/Configuration
Figure 1BK2461 Block Diagram
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BK2461
4 PIN information
XTALN
XTALP
CDVDD
P26
P27
P25
23
22
21
20
19
BK2461_QFN24
24
4.1
VCC3
1
18
P24
RF
2
17
P23
VCCPA
3
16
P22
P37
4
15
P21
P36
5
14
P30
P35
6
13
P20
10
11
12
P11
P31
9
P33
P32
8
P34
VPP
7
2461
QFN
4x4
Figure 2 BK2461-QFN
Num.
1
2
3
4
5
6
Name
Pin Function
Description
VCC3
RF
VCCPA
Power supply
Antenna input/output
Analog output
3v supply
P3.7
P3.6
P3.5
VPP
Digital I/O
Digital I/O
Digital I/O
Power supply
P3.4
P3.3
Digital I/O
Digital I/O
7
8
9
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PA power output, connected with
decoupling CAP
General I/O，ADC input
General I/O，ADC input
General I/O，ADC input
Mode select and 6.5V power supply
for OTP burning, or P12
output(PWM)
General I/O，ADC input
General I/O，ADC input
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BK2461
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
P3.2
P1.1
P3.1
P2.0
P3.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.7
P2.6
CDVDD
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Analog output
XTALP
XTALN
Analog output
Analog input
General I/O，ADC input
General I/O， external interrupt
General I/O，ADC input
General I/O，or input for UART
General I/O，ADC input
General I/O，or output for UART
General I/O，or I2C SCL
General I/O，or I2C SDA
General I/O，or PWM, or JTAG
General I/O，or PWM, or JTAG
General I/O，or PWM, or JTAG
General I/O，or PWM, or JTAG
power output, connected with
decoupling CAP
Oscillator output
Oscillator input
Table 1 PIN definition
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BK2461
4.2 BK2461_SOP16
P27 1
16 P21
P26 2
15 P20
CDVDD 3
14 P34
VSS 4
BK2461
SOP16
XTALP 5
13 VPP
12 P35
XTALN 6
11 P36
VCC3 7
10 P37
RF 8
9 VCCPA
Figure 3 BK2461-SOP
NO.
Name
Pin Function
Description
1
2
3
P2.7
P2.6
CDVDD
Digital I/O
Digital I/O
Analog output
General I/O，or PWM
General I/O，or PWM
power output, connected with
decoupling CAP
4
5
6
7
8
9
VSS
XTALP
XTALN
VCC3
RF
VCCPA
ground
Analog output
Analog input
Power supply
Antenna input/output
Analog output
10
P3.7
Digital I/O
11
P3.6
Digital I/O
12
P3.5
Digital I/O
13
VPP
Power supply
14
P3.4
Digital I/O
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Oscillator output
Oscillator input
3v supply
PA power output, connected with
decoupling CAP
General I/O，ADC input ,OTP
download
General I/O，ADC input ,OTP
download
General I/O，ADC input ,OTP
download
Mode select and 6.5V power supply
for OTP burning, or P12 output
General I/O，ADC input ,OTP
download
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BK2461
15
16
P2.0
P2.1
Digital I/O
Digital I/O
General I/O，or input for UART
General I/O，or output for UART
Table 2 PIN definition
5 FLIP51 Micro-Controller
5.1 Instruction Set
The FLIP8051 is an improved option of the 80c51 microcontroller. It is 100% binary
code upward compatible with the legacy 80c51.
Its pipeline architecture provides an increase of processing speed an average nine
times, when running at the same clock frequency as a standard 80c51 real component.
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BK2461
5.2 MCU diagram
Figure 4 FlIP51 architecture
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BK2461
6 Development and download
The BK2461 have some different development and download methods. The working
mode is decided by the VPP voltage when power up. The next table describes the
different working mode.
VPP
voltage
mode
description
Note
6.5+-0.5
OTP burning
mode
GPIO mapping to OTP download
mode.
3+-0.5
DEBUG mode
GPIO mapping to BIRD interface
used to debug on chip. At this
mode, the program can be loaded
to the chip from JTAG interface.
P3.4=spi_mosi
P3.5=spi_miso
P3.6=spi_clk
P3.7=spi_cs
P2.4=TDO
P2.5=TDI
P2.6=TMS
P2.7=TCK
1.2+-0.5
FLASH
download mode
At this mode, BK2461 load
program from the outside FLASH
firstly, then run the loaded
program
P3.4=boot_si
P3.5= boot_s0
P3.6= boot_sck
P3.7= boot_csn
0+-0.5
Normal mode
At this mode, BK2461 run the
program from the OTP directly.
(product mode)
Table 3 work mode selection
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BK2461
7 FLIP8051 address space
7.1 Overview
The memory organization of the Flip8051 is similar to that of standard 80C51. There
are three separate memory spaces: CODE space (program memory), the XDATA space
(external data memory) and the IDATA space (internal data memory).
These memory spaces shared the same address space but are accessed with different
instruction types.
There are organized as follow for BK2461:
CODE space: up to 8K Bytes of addressing range
XDATA space: up to 512 Bytes of addressing range
IDATA space: up to 256 Bytes.
0X1FFF
PWM RTC ADC
0x918
OTP
8k bytes
0x880
RF part register
128 byte
0x200
External RAM
512 bytes
0x0000
0x00
Internal RAM
256 bytes
0x00
Figure 5 FLIP51 SPACE
7.2 Program Memory (CODE space)
The Flip8051 has a 64K Bytes CODE space (8K for BK2461). Program memory is
normally assumed to be read only and can be accessed only by MOVC instruction (or of
course by the instruction fetch)
Two addressing modes are available for MOVC instructions:
16-bit data pointer (@A+DPTR).
The MOVC instructions use these indirect modes to access the current 64 K page of
the code memory.
16-bit program counter (@A+PC).
The MOVC instruction uses this indirect mode to access the 64 K page of the code
memory.
7.3 External Data Memory (XDATA space)
The External Data memory shares address bus with program memory. This data
space can be up to 64K Bytes (512 for BK2461).
The external data memory can be accessed only by the standard MOVX instructions
(plus some new instructions of the WHIRL instruction set)
Two addressing modes are available for MOVX instructions:
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BK2461
Byte register (@Ri, i = 0,1).
Registers R0 and R1 indirectly address external data memory locations 00h-FFh. When
MOVX instructions use this indirect mode, the MSB of the 16-bit address is filled with
the content of MPAGE SFR (0A1h). Then, it allows MOVX @Ri instruction to access to
64K Bytes of external data memory. Usually, in 80C51 application, the Port 2 is used to
this address extension. In order to keep software compatibility with existing 80C51
program, the register MPAGE is also updated by any value written at P2 register.
16-bit data pointer (@DPTR).
The MOVX instructions use these indirect modes to access the page of the external data
RAM pointed by the extended data pointer (DPX).
7.4 Internal Data Memory (IDATA space)
The Internal data memory is composed by 256 bytes of internal RAM and by a
number of SFRs.
The main difference between these IDATA and XDATA spaces is the kind of
instructions that enable to access to these memories. Most of the “data transfer”
instructions are dedicated to access internal data memory (IDATA) since there are only
four instructions (MOVX) dedicated to access external data memory. Moreover, only
indirect addressing mode is available for XDATA whilst IDATA can be addressed by
register, direct, register-indirect or immediate addressing mode. This provides a higher
flexibility to access data. In addition, the Flip8051 memory interface with IDATA space
is optimized and then access time to this space is faster than the access time of XDATA
for both read/write operations.
7.4.1 Internal Data memory organization
The internal data memory is divided into 3 spaces, which are referred to as the Lower 128,
Upper 128 and SFR space. Either direct or indirect addressing may be used to access the
lower 128 bytes of internal data memory. The upper 128 bytes of internal data memory are
accessible by indirect addressing only while direct addressing to region above 0x7F will
access SFR space.
In the Flip8051, the SFRs are implemented internally to the model using Flip-Flops.
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BK2461
Figure 6 Internal Data memory
7.4.2 Internal ram: lower 128 byes
Figure 7 Internal Ram lower 128 bytes
The lower 128 bytes of Internal Data Memory is organized in three distinct areas:
0x00-0x1F: The Register Banks are at the lowest 32 bytes of the internal data memory. Only
one Register Bank is used at a time when an instruction uses R0 to R7. 2 bits in Processor
Status Word (PSW), called RS1 and RS0, control the selection of the Register Bank. Bank 0
is selected upon reset. Indirect addressing mode used R0 and R1 as index registers
0x20-0x2F: This memory space contains a general-purpose memory, which is bit addressable
as well as byte addressable. The bit address ranged from 0 to 0x7F. When bit addressing is
used in an instruction, the bit access in this region will occur. In this memory range, when bit
addressing is used, bit address 0x00 is the bit 0 of address 0x20 while bit 7 of of the byte
0x20 has bit address 0x07. Bit address 0x7F is the bit 7 of address 0x2F. A bit access is
different than a byte access by the type of instruction used.
0x30-0x7F: A general-purpose byte-addressable memory is located above address 0x30. It
can be accessed both by direct or indirect addressing mode.
7.4.3 Internal Ram: Upper 128 Bytes
The usage of the addresses between 0x80 and 0xFF is up to the user. This memory can be
used for any purpose providing that indirect addressing mode is used when accessing this
memory space, otherwise the Special Function Register memory will be accessed.
7.4.4 The Stack and the stack pointer
The stack refers to an area of internal RAM that is used in conjunction with certain
instructions (PUSH, POP) to store and retrieve data quickly. The Stack pointer register (SP,
0x81) is used to hold an internal RAM address that is called the “top of the stack”. The data
held in the SP register is the address in internal RAM where the last byte of data was stored
by a stack operation. The reset value of Stack pointer register is 0x07 and can be changed to
any internal RAM address by the programmer. Usually, the stack is located high in the RAM
to avoid conflict with the work register, bit and byte area in internal RAM.
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BK2461
7.4.5 Special Function Registers
The direct-access data memory locations from 0x80 to 0xFF constitute the special function
registers (SFRs). All the special function registers of the original 80C51 are present in the
Flip8051. SFRs with addresses ending in 0x0 or 0x8 (e.g. P0, TCON, P1, SCON, IE, etc.) are
bit-addressable as well as byte-addressable. All other SFRs are byte-addressable only.
The special function registers (SFRs) reside in their associated peripherals or in the core.
The following tables shows the SFR address space with the SFR mnemonics and reset values.
Unoccupied locations in the SFR space are unimplemented, i.e. no register exists. If an
instruction attempts to write to an unimplemented SFR location, the instruction executes, but
nothing is actually written. If an unimplemented SFR location is read, it returns an
unspecified value.
SFR
Name
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
addr
0x80
SP
-
-
-
-
-
-
-
-
0x81
DPL
-
-
-
-
-
-
-
-
0x82
DPH
-
-
-
-
-
-
-
-
0x83
CKCON
CKDIV1
CKDIV0
smod0
x
x
x
x
x
0x84
CLK_EN
CFG
PCON2
adc_en
timer_en
uart_en
pwm_en
spi_en
i2c_en
aes_mud_
en
wdt_en
0x85
SMOD
EUSB
CMD_RS
T
Latch_en
deep_sleep
OSC32k
RC32k
IDLE
0x86
0x87
TCON
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
0x88
TMOD
GATE
C/T
M1
M0
GATE
C/T
M1
M0
0x89
TL0
-
-
-
-
-
-
-
-
0x8A
TL1
-
-
-
-
-
-
-
-
0x8B
TH0
-
-
-
-
-
-
-
-
0x8C
TH1
-
-
-
-
-
-
-
-
0x8D
CCMCON
-
-
-
-
-
-
-
-
0x8E
CCMVAL
-
-
-
-
-
-
-
-
0x8F
P1
-
-
-
-
-
-
-
-
0x90
0x91
DPSEL
x
x
x
x
x
x
x
DPSEL0
0x92
P1IN_EN
-
-
-
-
-
-
-
-
0x93
P2IN_EN
-
-
-
-
-
-
-
-
0x94
P3IN_EN
-
-
-
-
-
-
-
-
0x95
0x96
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BK2461
-
-
-
-
-
-
-
-
0x97
SCON0
SM0
SM1
SM2
REN
TB8
RB8
TI
RI
0x98
SBUF0
-
-
-
-
-
-
-
-
0x99
MMS
0x9A
PAGE_A
（NA）
PAGE_B
（NA）
PAGE_C
（NA）
P1OUT_N
x
x
x
x
x
x
x
x
0x9B
x
x
x
x
x
x
x
x
0x9C
x
x
x
x
x
x
x
x
0x9D
-
-
-
-
-
-
-
-
0x9E
P2OUT_N
-
-
-
-
-
-
-
-
0x9F
P2
-
-
-
-
-
-
-
-
0xA0
MPAGE
-
-
-
-
-
-
-
-
0xA1
0xA2
0xA3
0xA4
P3OUT_N
-
-
-
-
-
-
-
-
0xA5
WDT
x
x
x
state
x
ps2
ps1
ps0
0xA6
EA
x
ET2
ES
ET1
EX1
ET0
EX0
0xA8
0xA7
IE
0xA9
P1_PU
-
-
-
-
-
-
-
-
0xAA
P2_PU
-
-
-
-
-
-
-
-
0xAB
P3_PU
-
-
-
-
-
-
-
-
0xAC
0xAD
0xAE
P1_PD
-
-
-
-
-
-
-
-
0xAF
P3
-
-
-
-
-
-
-
-
0xB0
0xB1
0xB2
0xB3
P2_PD
-
-
-
-
-
-
-
-
0xB4
P3_PD
-
-
-
-
-
-
-
-
0xB5
0xB6
0xB7
IP
-
-
-
-
-
-
-
-
0xB8
0XB9
0xBA
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BK2461
0xBB
0xBC
0xBD
0xBE
0xBF
AIF
-
-
-
-
-
-
-
-
0xC0
0xC1
0xC2
0xC3
0xC4
0xC5
0xC6
0xC7
T2CON
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
CT2
CPRL2
0xC8
0xC9
RCAP2L
-
-
-
-
-
-
-
-
0xCA
RCAP2H
-
-
-
-
-
-
-
-
0xCB
TL2
-
-
-
-
-
-
-
-
0xCC
TH2
-
-
-
-
-
-
-
-
0xCD
0xCE
0xCF
PSW
-
-
-
-
-
-
-
-
0xD0
0xD1
I2CM
DATA_IE
x
x
ETBE
x
ETBF
ERBE
x
ERBF
0xD2
0xD3
I2CM
CALLADD
R0
RWN
CADDR[6]
CADDR[
5]
CADDR[4]
CADDR[3]
CADDR[
2]
CADDR[1]
CADDR[
0]
0xD4
0xD5
0xD6
0xD7
0xD8
P1_OPDR
-
-
-
-
-
-
-
-
0xD9
P2_OPDR
-
-
-
-
-
-
-
-
0xDa
P3_OPDR
-
-
-
-
-
-
-
-
0xDb
0xDc
0xDd
0xDe
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0xDf
ACC
-
-
-
-
-
-
-
-
0xE0
I2CM
CTRL
I2CM
RXDATA
I2CM
TXDATA
I2CM
PRESC
I2CM
TXRX_ST
S
I2CM
DATA_ST
S
I2CM
TXRX_IE
AIE
x
x
WAIT
x
STOP
SRST
STA
BUSY
0xE1
-
-
-
-
-
-
-
-
0xE2
-
-
-
-
-
-
-
-
0xE3
-
-
-
-
-
-
-
-
0xE4
x
x
DNA
SANA
UNF
OVF
NEND
0XE5
x
x
TBE
x
TBF
RBE
x
RBF
0XE6
x
x
x
EDNA
ESANA
EUNF
EOVF
ENEND
0xE7
-
-
-
-
-
-
-
-
0xE8
PALT0
x
x
T2_IN_EN
T1_IN_EN
x
x
x
x
T0_IN_E
N
x
EX1_IN_E
N
exsleep2
EX0_IN_
EN
ex_sleep
1
0xE9
EXSLEEP
T2_EX_
EN
x
0xEA
0xEB
P1_WUEN
-
-
-
-
-
-
-
-
0xEC
P2_WUEN
-
-
-
-
-
-
-
-
0xED
P3_WUEN
-
-
-
-
-
-
-
-
0xEE
0xEF
0xF0
B
0xF1
0xF2
0xF3
0xF4
0xF5
0xF6
UART0
_IO
SPI_IO
I2C_IO
0xF7
-
-
-
-
0xF8
-
-
-
-
-
0xFA
-
-
-
-
-
-
0xFB
-
-
-
-
-
-
0xFC
PALT1
(W only)
AIP
PWM4_I
O_EN
PWM3_I
O_EN
PWM2_I
O_EN
-
-
-
-
P1_WUM
OD
P2_WUM
OD
P3_WUM
OD
-
-
-
-
-
-
-
PWM1_I
O_EN
PWM0_I
O_EN
0xF9
0xFD
0xFE
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BK2461
0xFF
Table 4 Special Function Registers Memory Map
7.4.6 SFR table for MCU part
Register
Address
0xE0
ACC
0xF0
B
0x83
DPH
0x82
DPL
0x92
DPSEL
0xA8
IE
0xB8
IP
0xA1
MPAGE
0x86
PCON2
0xD0
PSW
0x81
SP
0xE0
ACC
0xF0
B
0x83
DPH
0x82
DPL
0x92
DPSEL
0xA8
IE
0xB8
IP
0xA1
MPAGE
0x87
PCON
0xD0
PSW
0x81
SP
Register
AIE
AIF
AIP
Register
P0
P0IN_EN_
P0OUT_N_
P0_PU
P0_PD
P0_OPDR
P0_WUEN
P0_WKMOD
Description
Accumulator
B Register
Data Pointer high byte
Data Pointer low byte
Data Pointer selection
Interrupt Enable Control
Interrupt Priority Control
Memory page register
Power Control
Program Status Word
Stack Pointer
Accumulator
B Register
Data Pointer high byte
Data Pointer low byte
Data Pointer selection
Interrupt Enable Control
Interrupt Priority Control
Memory page register
Power Control
Program Status Word
Stack Pointer
Table 5 Core SFRs
Reset value
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
07h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
07h
Address
Description
0xE8
Additional interrupt enable
0xC0
Additional interrupt flag
0xF8
Additional interrupt priority
Table 6 Additional interrupt SFRs
Address
Description
0x80
Port0 value
0x91
Port input enable, active high
0x9A
Port output enable, active low
0xA9
Port pull-up selection
0xAE
Port pull-down selection
0xD8
Open drain selection
0xEB
Port wake up enable
0xF9
Port wake up mode selection
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Reset value
00h
00h
00h
RST value
0xFF
0xFF
0xFF
0xFF
0x00
0x00
0x00
0x00
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BK2461
P1
P1IN_EN_
P1OUT_N_
P1_PU
P1_PD
P1_OPDR
P1_WUEN
P1_WKMOD
P2
P2IN_EN_
P2OUT_N_
P2_PU
P2_PD
P2_OPDR
P2_WUEN
P2_WKMOD
P3
P3IN_EN_
P3OUT_N_
P3_PU
P3_PD
P3_OPDR
P3_WUEN
P3_WKMOD
P4
P4IN_EN_
P4OUT_N_
P4_PU
P4_PD
P4_OPDR
P4_WUEN
P4_WKMOD
0x80
0x93
0x9E
0xAA
0xAF
0xD9
0xEC
0xFA
0xA0
0x94
0x9F
0xAB
0XB4
0xDA
0xED
0xFB
0xB0
0x95
0Xa5
0xAC
0xB5
0xDB
0xEE
0xFC
0xB7
0x96
0xa7
0xAD
0xB6
0xDC
0xEF
0xFD
Port0 value
0xFF
Port input enable, active high
0xFF
0xFF
Port output enable, active low
0xFF
Port pull-up selection
0x00
Port pull-down selection
0x00
Open drain selection
0x00
Port wake up enable
0x00
Port wake up mode selection
Port0 value
0xFF
Port input enable, active high
0xFF
0xFF
Port output enable, active low
0xFF
Port pull-up selection
0x00
Port pull-down selection
0x00
Open drain selection
0x00
Port wake up enable
0x00
Port wake up mode selection
Port0 value
0xFF
Port input enable, active high
0xFF
0xFF
Port output enable, active low
0xFF
Port pull-up selection
0x00
Port pull-down selection
0x00
Open drain selection
0x00
Port wake up enable
0x00
Port wake up mode selection
Port0 value
0xFF
Port input enable, active high
0xFF
0xFF
Port output enable, active low
0xFF
Port pull-up selection
0x00
Port pull-down selection
0x00
Open drain selection
0x00
Port wake up enable
0x00
Port wake up mode selection
Table 7 I/O ports SFRs
NOTE: some ports are not available in BK2461, please refer to the package information.
Register
SBUF
SCON
Address
0x99
0x98
Register
T2CON
TCON
Description
Serial Buffer
Serial Control
Table 8 Serial Port SFRs
Address
Description
0xC8
Timer/Counter 2 control
0x88
Timer/Counter 0 and 1 control
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Reset value
00h
00h
RST value
00h
00h
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BK2461
TH0
TH1
TH2
TL0
TL1
TL2
TMOD
RCAP2H
RCAP2L
WDTRST
0x8C
0x8D
0xCD
0x8A
0x8B
0xCC
0x89
0xCB
0xCA
0xA6
Timer/Counter 0 high byte
Timer/Counter 1 high byte
Timer/Counter 2 high byte
Timer/Counter 0 low byte
Timer/Counter 1 low byte
Timer/Counter 2 low byte
Timer/Counter 0 and 1 mode control
Timer 2 Reload/Capture high byte
Timer 2 Reload/Capture low byte
WDT enable register
Table 9 Timers SFRs
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
Register
CCMCON
CCMVAL
MMS
Address
0x8E
0x8F
0x97
Description
BIRD Communication Control
BIRD Communication Value
Reserved for emulation purpose
Table 10 BIRD SFRs
RST value
00h
00h
07h
8 Power management
For applications where power consumption is critical, the BK2461 provides all kinds of
power saving modes.
8.1 Power Control Register
PCON2
0x87
7
SMOD
6
EUSB
5
CMD_R
ST
4
Latch_
en
3
Deep_s
leep
2
OSC32
K _sel
1
RC32k_
sel
0
IDLE
Table 11 power management register
SMOD: – Serial Port 0 baud rate doublers enable. When SMOD0=1, the baud rate
for Serial Port 0 is doubled.
EUSB: R/W by software only. USB enable, the 48MHz clock will exist when
EUSB=1.
CMD_RST: Write 1 to reset MCU (not include RF part).
Latch_en: this register used for deep sleep mode. In deep sleep mode, the power
supply to digital part will be shut down, but the GPIO setting must be hold use this
register.
Deep_sleep: System will enter deep sleep mode when setting this register. The lowest
current consumption can be got by setting this register.
RC32k_sel: System will select RC32k clock when write 1 to this position. Interrupts
and software can clear it.. In this state, the system clock changed to 32K RC clock, so the
power consumption is very low.
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OSC32k_sel: System will select OSC32k (divided by OSC16M) clock when write 1
to this position. Interrupts and software can clear it. In this state, the system clock
changed to 32K OSC clock, so the power consumption will decrease evidently.
Please note that OSC32k clock is more accurate than RC 32k clock, but need more
power consumption.
IDLE: When set by software, system enter stop mode, and it can only be wake up by
enabled interrupt.(Clear it to 0 by hardware). In this state, the most of clocks are shut
down for power saving.
Note: set RC32k_sel and IDLE bit simultaneously can get the lowest power
consumption, and in this state, all the register settings are retained.
8.2 Work State
8.2.1 IDLE MODE
An instruction that sets the IDLE bit (PCON2.0) causes the FLIP51 to enter idle
mode when that instruction completes. In idle mode, CPU processing is suspended,
internal registers maintain their current data. However, unlike the standard 8051, the
clock is not disabled internally.
Activation of any enabled interrupt causes the hardware to clear the IDLE bit and
terminate idle mode.
In idle mode, the power consumption is decreased evidently.
8.2.2 SLEEP MODE
An instruction that sets the IDLE bit (PCON2.0) causes the FLIP51 to enter idle
mode when that instruction completes. Also, you can decrease the power consumption to
a lower level thanks for the register PCON2.1. When setting the register, the system
clock changed from 16MHz to RC32KHz. We define this state as sleep mode.
After reset, the system will enter normal mode running at 16MHz immediately.
Note: You should always clear PCON2.6 to 0 to save current when USB module
doesn’t need work at any time.
As showed above, the IDLE bit decide CPU run or not, the PCON2.1 bit decide the
system clock source. (16MHz or RC32KHz)
8.2.3 DEEP SLEEP MODE
If you want to get the lowest power consumption, you can let BK2461 enter deep
sleep mode. Firstly, you should set all the GPIO to certain setting , then, set latch_en
(PCON2 [4]) to latch all the register setting, lastly, set deep sleep bit (PCON2 [3]) to
enter deep sleep status. In this state, the power supplied to digital will be shut down.
Note: after wake up from this state, the instruction will run from the address zero.
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8.2.4 Wake Up
8.2.4.1
Wake Up from sleep mode
When the MCU entered IDLE/SLEEP mode, all the enabled GPIO ports and interrupt
sources can be used to wake up the MCU separately. Configure the corresponding SFR
bit can enable or disenable the wake up function.
PX_WKEN: port x wake up enable or disable 0: disable; 1: enable
PX_WKMOD: wake up mode setting. 0: low level trigger; 1: edge trigger
You can get the detail GPIO register address from SFR table part.
The process wake up from sleep mode is showed in next figure.
80us
400us
Wake up
RC 16M
XOSC 16M
clock
Figure 8 wake up process
After wake up, RC 16M clock will spend 80us to wake up, and after 400us, the
clock source will switch to XOSC 16M automatically. RC 16M clock is not very accurate,
so, during this period, you can only run ordinary MCU instruction, but cannot send or
receive RF package.
Please note that: The RF part will also resume 120us for PLL locking after power up
RF part. So, if you want to send/receive package through RF, you should wait 600us
after wake up from sleep mode.
8.2.4.2
Wake up from deep sleep mode
All the ports can be set to wake up MCU from deep sleep status; also, you can enable
or disable them separately. After wake up from deep sleep, a POR will be generated to
reset the whole digital system.
9 Clock system
9.1 System clock topology
The BK2461 clock topology is showed as below. There are two clock sources, one is
16M, and the other is RC32k. You can select them by setting register according.
If the wake up time is a critical parameter for some application, a RC16M clock can be
used before the OSC16M oscillating. To do this, the register XXX must be set as xxx.
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The clock source of ext timer is always fixed to 32k. In working mode, the OSC32K is
used for counter, and in idle mode, the RC32k can be automatically selected. The ext
timer is very suitable used for the application which has periodic behavior, such as mouse.
CKCON[2:1]
16M
8M
4M
2M
OSC16M
/RC16M
PCON2[1]
select
32K
Pcon2[2]
clk_gate
gated_clk
RC_32K
Extimer
Samp_pad
PCON2[1]
Figure 9 clock topology
9.2 Peripherals clock management
The peripherals clock source can be enabled or disenabled, to do this, you can refer to the
next register. Evidently, the clock must be enabled when you want to use some peripheral
equipment.
CLK_EN_CFG
7
6
5
4
3
2
1
0
adc
timer
uart
pwm
i2c
WDT
0x85
_en
_en
_en
_en
_en
_en
Table 12 clock enable register
CLK_EN_CFG: this register can use to power on or off all the peripheral equipment
clocks for saving power.
adc_en : ADC clock enable or not ( 1 enable )
timer_en : TIMER 0 /1 /2 clock enable or not ( 1 enable )
uart_en : UART clock enable or not ( 1 enable )
pwm_en : PWM clock enable or not ( 1 enable )
i2c_en : I2C clock enable or not ( 1 enable )
WDT_en : MDU clock enable or not ( 1 enable )
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10 Reset system
There are three active low reset source in BK2461, they are power on reset, reset pin,
watch dog reset. After reset, the MCU will re-start from address 0.
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11 Interrupt system
The Flip8051 has the same interrupt sources as the original 80C51. These are handled the
same as on the original 80C51, however the Flip8051 has a shorter interrupt latency period,
and can distinguish shorter external interrupt pulses. The interrupt sources are sampled every
clock cycle (clock rising edge), and the decision of whether an interrupt will be accepted
takes place at the last clock cycle of each instruction execution, or every clock cycle during
idle mode.
11.1 7.1 Introduction
When an enabled interrupt occurs, this operation branches to a subroutine and performs
some service in response to the interrupt. When the subroutine completes, execution resumes
at the point where the interrupt occurred. Interrupts may occur as a result of internal activity
(e.g. timer0 overflow) or at the initiation of an external device (external interrupt pin). In any
case, interrupt operation is programmed by the system designer, who determines the priority
of interrupt service, compare to relative normal code execution or other interrupt service
routines. All the interrupts may be enabled / disabled dynamically by the system designer
except the TRAP (software) and the NMI that are non-maskable.
A typical interrupt process occurs as follow:
An interrupt event on the signal, connected to an input pin and sampled by the Flip8051, is
registered into a flag buffer.
The priority of the flag is compared to the priority of the other interrupt by the interrupt
controller. A higher priority causes the controller to set an interrupt flag.
The setting of the interrupt flag indicates to the control unit to execute a context switch.
This context switch breaks the current instruction execution flow1. The control unit
completes the current instruction execution prior to saving the two bytes of the program
counter (PC) and reloads the PC with the interrupt vector address, which is the start address
of a software service routine.
The software service routine performs the assigned tasks and executes a RETI instruction
as a final instruction. This instruction signals the completion of the interrupt, resets the
interrupt-in-progress priority. The RETI instruction reloads the two bytes of the program
counter and uses them as the 16-bit return address. Program execution then continues from
the original point of interruption.
11.1.1 Interrupt source
The Flip8051 has one software interrupt, the TRAP instruction (always enabled) and up to
fifteen interrupt sources controlled by hardware. Fourteen of these hardware interrupt are
maskable interrupt sources and one is non-maskable (intnmi input, always enabled). The
maskable sources include two external interrupts (int0_n and int1_n), three timer interrupts
(timers 0, 1, and 2), and one serial port (UART) interrupt. Depending on configuration, eight
additional external interrupt (intextra_n[7:0]) are available and maskable.
Each interrupt (except TRAP and intnmi) has an interrupt request flag, which can be set by
software as well as by hardware. For some interrupts, hardware clears the request flag when
it grants an interrupt. Software can clear any request flag to cancel an impending interrupt.
For BK2461, the available interrupts are showed in the next table:
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Interrupt
Number
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Interrupt
Flag
EX0
ET0
EX1
ET1
UART
TF2+EXF2
TRAP
Intnmi
EX2
EX3
EX4
EX5
EX6
EX7
EX8
EX9
Interrupt
Source
NA
Flip8051 Timer0 Interrupt
GPIO P1.1 Input
Flip8051 Timer1 Interrupt
RI+TI
Flip8051 Timer2 Interrupt
NA
NA
I2CM Interrupt
NA
BK2401 Transceiver Interrupt
External Timer Interrupt
NA
ADC Interrupt
NA
Table 13 interrupt sources
Interrupt Routine
Code Address
0x0013
0x000B
0x001B
0x0023
0x002B
0x0033
0x004B
0x005B
0x0063
0x0073
11.1.2 Int0_n and int1_n
External interrupt int0_n (not available for BK2461) and int1_n may be each
programmed to be level-activated or transition-activated, depending on bits IT0 and IT1 in
TCON register. External interrupts are enabled with bits EX0 and EX1 in IE register. Events
on int0_n or int1_n set respectively the interrupt request flag IE0 or IE1 in TCON register. If
the interrupt is transition-activated, the hardware jump to the service routine clears the
request flag. Otherwise, if the interrupt is level activated, then the interrupt must be deasserted before the end of the ISR.
External interrupt pins must be de-asserted for at least two clock cycles prior to a request.
External interrupt inputs are sampled at each clock cycle. A level-triggered interrupt pin held
low or high for any two clock cycles time period guarantees detection. Edge-triggered
external interrupts must hold the request pin low for at least two clock cycles. This ensures
edge recognition and sets interrupt request bit IEx. The CPU clears IEx automatically during
service routine fetch cycles for edge-triggered interrupts.
External interrupt inputs int0_n and int1_n provide both the capability to exit from idle
mode on low-level signal. GPIO description
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Table 14 Timer/counter control register (TCON low)
11.1.3 Intnmi interrupt
Intnmi input is the non-maskable interrupt input. Since intnmi is high level-triggered input,
Not available for BK2461
11.1.4 Additional interrupts
This configuration requires the use of three new SFRs: Additional interrupt Flag register
(AIF), Additional Interrupt Enable Register (AIE) and Additional Interrupt Priority Register
(AIP).
Register Address
Description
Reset value
AIE
0xE8
Additional interrupt enable
00h
AIF
0xC0
Additional interrupt flag
00h
AIP
0xF8
Additional interrupt priority
00h
Table 15 Additional interrupt registers
The additional external sources are level-activated for intextra_n[5:0] and transitionactivated for intextra_n [7:6].
The flags that actually generate these interrupts are bits AIFj in Special Function Register
AIF. When an external interrupt is generated, the flag that generated it is NOT cleared by
hardware when the service routine is vectored to. This has to be done in the user's
software.
All of the bits that generate interrupt (AIFj) can be set by software, with the same result
as though it had been set by hardware. That is, interrupts can be generated in software.
Each of the additional external interrupt sources can be individually enabled or disabled by
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setting or clearing bit AIEj in Special Function Register AIE.
The interrupt global disable bit EA in IE register also disables the additional interrupts.
Like int0_n and int0_n inputs, intextra_n inputs are synchronized once on clock rising edge
before internal use.
Table 16 Additional interrupt flag register (AIF)
11.1.5 Timer Interrupts
Two timer-interrupt request bits (TF0 and TF1 in TCON register) are set by timer overflow
(except Timer 0 in Mode 3). When a timer interrupt is generated, the bit is cleared by a
hardware jump to an interrupt service routine. Timer interrupts are enabled by bits ET0, ET1,
and ET2 in the IE register.
Timer 2 interrupts are generated by a logical OR of bits TF2 and EXF2 in register T2CON.
Neither flag is cleared by a hardware jump to a service routine. In fact, the interrupt service
routine must determine if TF2 or EXF2 generated the interrupt, and then clear the bit. Timer
2 interrupt is enabled by ET2 in register IE0.
NOTE: EXF2 is not available for P03(T2EX) is not exist.
11.1.6 Serial Port Interrupt
Serial port interrupts are generated by the logical OR of bits RI and TI in the SCON
register. Neither flag is cleared by a hardware jump to the interrupt service routine. The
service routine resolves RI or TI interrupt generation and clears the serial port request flag.
The serial port interrupt is enabled by bit ES in the IE register.
11.1.7 TRAP interrupt
The function of TRAP instruction is like a software breakpoint, which is useful in software
debug. The coding of this instruction is [0xA5]. By execution of the TRAP instruction, the
Flip8051 generates an interrupt and executes the interrupt service routine at address 0x0033.
It acts like the highest priority non-interruptible interrupt.
11.2 Interrupt enable
Each interrupt source (with the exception of TRAP) may be individually enabled or
disabled by the appropriate interrupt enable bit in the IE register (or in the AIE register for
additional interrupt sources). Note IE also contains a global disable bit (EA) that applies to all
interrupts (except TRAP and intnmi that is not maskable). If EA is set, interrupts are
individually enabled or disabled by bits in IE. If EA is clear, all interrupts are disabled.
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Table 17 Interrupt Enable 0 register (IE0)
Table 18 Additional Interrupt Enable register (AIE)
11.3 Interrupt priority
Each of the hardware interrupt sources may be individually programmed to high or low
priority levels (except the NMI input and the TRAP, which have a higher priority level). This
is accomplished by clearing/setting the corresponding bit in the Interrupt Priority registers (IP
or AIP)
The TRAP instruction is the highest priority level interrupt. A TRAP cannot be
interrupted by any other interrupt source including the TRAP. A low-priority interrupt can be
itself interrupted by a higher priority level interrupt, but not by another lower or equal
priority interrupts. Higher priority level interrupts are serviced before lower priority
interrupts.
NOTE: some interrupts are not available for BK2461, please refer to the interrupt source
for detail.
Interrupt
Interrupt Priority
Vector
Cleared by hardware
source
flag
level
Addresses (H) or by software (S)
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-
3
(highest - not
interruptible)
0x0033
-
Intnmi
int0_n
Timer 0
int1_n
Timer 1
UART
Timer2
Intextra_n[0]
IE0
TF0
IE1
TF1
RI+TI
TF2+EXF2
AIF0
2
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0x003B
0x0003
0x000B
0x0013
0x001B
0x0023
0x002B
0x0043
-
Intextra_n[1]
AIF1
0 or 1
0x004B
S
Intextra_n[2]
AIF2
0 or 1
0x0053
S
Intextra_n[3]
AIF3
0 or 1
0x005B
S
Intextra_n[4]
AIF4
0 or 1
0x0063
S
Intextra_n[5]
AIF5
0 or 1
0x006B
S
TRAP
H if edge
H
H if edge
H
S
S
S
Intextra_n[6]
Intextra_n[7]
AIF6
0 or 1
0x0073
S
AIF7
0 or 1
0x007B
S
Table 19 Interrupt priority levels and vector addresses
If two interrupt requests with the same priority level (0 or 1) are received simultaneously,
an internal polling sequence determines which request is serviced, according to the table
below:
Interrupt source
Interrupt flag
Servicing priority order
int0_n
Timer 0
int1_n
Timer 1
UART
Timer2
Intextra_n[0]
IE0
TF0
IE1
TF1
RI+TI
TF2+EXF2
AIF0
1 (highest)
2
3
4
5
6
7
Intextra_n[1]
AIF1
8
Intextra_n[2]
AIF2
9
Intextra_n[3]
AIF3
10
Intextra_n[4]
AIF4
11
Intextra_n[5]
AIF5
12
Intextra_n[6]
AIF6
13
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Intextra_n[7]
AIF7
14 (lowest)
Table 20 Interrupt priority within a same priority level (0 or 1)
Table 21 Interrupt Priority Register (IP)
Table 22 Additional Interrupt Priority Register (AIP)
11.4 Interrupt blocking conditions
If all enable and priority requirements have been met, a single prioritized interrupt request
at a time branches to an interrupt service routine. There are 3 causes of blocking conditions
with hardware-generated interrupt request:
1. An interrupt of equal or higher priority level is already in progress (defined as any point
after the flag has been set and the RETI of the ISR has not executed).
2. The current polling cycle is not the final cycle of the instruction in progress.
3. The instruction in progress is RETI or any write to the IE, IP, AIE or AIP registers.
Any of these conditions blocks calls to interrupt service routines. Condition 2 ensures the
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instruction in progress completes before the system vectors to the ISR. Condition 3 ensures at
least one more instruction executes before the system vectors to interrupts if the instruction in
progress is a RETI or any write to an interrupt control registers.
: If the interrupt flag for a level-triggered external interrupt is set but denied for
one of the above conditions and is clear when the blocking condition is removed, then the
denied interrupt is ignored. In other words, blocked interrupt requests are not buffered for
retention.
12 Peripheral module
12.1 OVERVIEW
12.2 UART
12.2.1 Serial port overview
The Flip8051 provides a standard serial communication interface (UART). The Serial
Port uses the signals Serial In and Serial Out to receive and transmit serial data. The modes of
operation and baud rate generation are the same as the original 80C51. The serial interface in
the Flip8051 supports all operation modes, as in standard 80C51.
12.2.2 Operation mode
12.2.2.1 Mode 0 (synchronous mode, half duplex)
Not supported for BK2461
12.2.2.2 Mode 1 (asynchronous mode, full duplex)
In Mode 1, data is transmitted through serial out signal and received through serial in
signal. The data is composed of 10 bits: starting with a start bit “0”, then followed by 8 data
bits (LSB first, MSB last), and then the stop bit “1”. The Baud Rate in Mode 1 is controlled
by Timer1 or Timer2 and is programmable. Please refer to Programming the Baud Rate, in
later part of this chapter for details. To select the mode 1, clear SCON.SM0 and set
SCON.SM1.
12.2.2.2.1
Transmission
To send out data, clear the SCON.REN bit and write the data into the SBUF special
function register. The data will then be shifted out (LSB first, MSB last), at the serial out pin.
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Figure 10 Serial Transmit Mode 1
12.2.2.2.2
Reception
To receive data, set the SCON.REN bit and clear the SCON.RI, this will enable the
receive function. When received the data value can be read from the SBUF special function
register.
Figure 11 Serial receive Mode 1
12.2.2.3 Mode 2 (asynchronous mode, full duplex)
In Mode 1, data is transmitted through serial out signal and received through serial in
signal. The data is composed of 11 bits: 1 start bit, 8 data bits, 1 TB8 bit (in SCON) and the
stop bit. The extra TB8 bit is for use in a multiprocessor communication environment. When
multiprocessor communication support is not needed, this bit can also be used as a parity bit.
The data transfer rate in Mode 2 is fixed as clock/32 or clock/64. Timer 1 and Timer 2 are
independent of the Baud Rate generation and can be used for other purposes. To select the
mode 2, set SCON.SM0 and clear SCON.SM1.
12.2.2.3.1
Transmission
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To send out data, clear the SCON.REN bit and write the data into the SBUF special
function register. The data will then be shifted out (LSB first, MSB last), at the serial out pin.
Figure 12 Serial Transmit Mode 2
12.2.2.3.2
Reception
To receive data, set the SCON.REN bit and clear the SCON.RI, this will enable the
receive function. When received the data value can be read from the SBUF special function
register.
Figure 13 Serial receive Mode 2
12.2.2.4 Mode 3 (asynchronous mode, full duplex)
The operation of Mode 3 is same as Mode 2. The only difference is that Timer1 (or Timer
2) controls the Baud Rate. Serial Mode 3 has the same timing diagram as Mode 2 (above),
but the source of the shift pulse is different. To select the mode 1, set SCON.SM0 and
SCON.SM1.
12.2.3 Programming the Baud Rate
12.2.3.1 Mode 0
Not available for BK2461.
12.2.3.2 Modes 1 & 3 - Timer1 generating Baud Rate
Timer 1 generates the Receive Clock when T2CON.RCLK=0 and the Transmit Clock
when T2CON.TCLK=0, (or always in the Flip8051 without the Timer2). Timer1 should be
set up in timer auto-reload mode.
Baud Rate = ((PCON2.SMOD+1)*clock)/( 32*12*(256-TH1))
Given a baud rate, the reload value for TH1 is
TH1 = (256 - (PCON2.SMOD+1)*clock)/( 384*Baud Rate)
If TH1 is not an integer value then either the Baud Rate or clock frequency must be changed.
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12.2.3.3 Modes 1 & 3 - Timer2 generating Baud Rate
Timer 2 can generate the Receive Clock in the Flip8051, when T2CON.RCLK=1 and the
Transmit Clock when T2CON.TCLK=1. If Timer2 is being clocked internally,
Baud Rate = clock /(32*(65536-(RCAP2H,RCAP2L)))
The reload value for RCAP2H, RCAP2L is given by
RCAP2H, RCAP2L = 65536 - clock /(32*Baud Rate)
Otherwise if Timer2 is being clocked by the Timer2 signal, Baud Rate = Timer2 Overflow
rate/16.
12.2.3.4 Mode 2
In serial mode 2 the Baud Rate is fixed to (PCON2.SMOD +1)/64.
12.2.4 Serial port registers
The serial port uses two SFR registers.
Register
Address
Description
0x98
Serial Control
SCON
0x99
Serial Buffer
SBUF
Table 23 Serial Port registers
Bit
Number
7:6
Bit
Mnemonic
SM0, SM1
Reset value
00h
00h
Function
Serial port mode bit
SM0
SM1
0
0
Mode
0
Description
Shift register
Baud rate
Clk/12
0
1
SM2
4
REN
3
TB8
2
RB8
1
TI
1
2
8 bit UART
9 bit UART
Variable
Clk/32 or Clk/64
1
5
1
0
1
3
9 bit UART
Variable
Serial port mode bit 2
If set in serial modes 2 or 3, RI is only activated if the 9th received data bit
(RB8)
is 1. If set in serial mode 1, then RI is only activated if a valid stop bit is
received.
Receiver Enable Bit
Set for reception, clear for transmission
Transmit bit 8
In serial modes 2 and 3, the 9th data bit transmitted
Receiver bit 8
In serial modes 2 and 3, the 9th data bit received.
Transmit interrupt flag
Set at the beginning of the stop bit, or at the end of the 8th bit time in mode 0.
Cleared by software.
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0
RI
Receive interrupt flag
Set halfway through the stop bit, or at the end of the 8th bit time in mode 0.
Cleared by software.
Table 24 Serial Port control register (SCON)
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12.1 ADC
12.1.1 introduction
PORT0
PORT1
PORT2
PORT3
PORT4
PORT5
PORT6
PORT7
ADC
INPUT
MUX
DC_COMP
Vref_sel
1/4 D & lt; 11:0 & gt;
10Bit
ADC
ADC
OUTPUT
D & lt; 9:0 & gt;
S & lt; 2:0 & gt;
Figure 14 ADC
A 10bits/12bits SAR ADC is integrated in BK2535. Total 8 channels can be selected
used for ADC transfer. The ADC supports continue mode and single transfer mode, and
the sample rate can be 1kHz to 32kHz. In single transfer mode, it will generate interrupt
every time after transform. The input of ADC is share with P3 general I/O port.
In single transfer mode, the time used to convert is very little.
Convert time & lt; 30us(single mode) Convert Done),
The ADC register located at the XRAM space, the basic address is 0X920.
12.1.2 Register explain
ADDR bit7
bit6
0x0922
adc_mode
bit5
bit4
adc_chnn
bit3
bit2
bit1
bit0
intr_en adc_ch ready
_en
adc_mode:=00, power down mode
adc_mode:=01, single mode
adc_mode:=10, soft mode
adc_mode:=10, continue mode; 12bitsmode(filt_mode=1) is only effective for
this mode.
adc_chnn：eight channel corresponding to GPIO3.0- GPIO3.7
intr_en: generate interrupt or not to MCU
adc_ch_en: ADC channel enable. If no GPIO port used to ADC transfer, this
bit should be set to 0.
ready： when the transfer is done, the bit will be set to zero. After read, it
will be set to 1 automatically.
Table 25 ADC register
ADDR
adc_dataL[7:0]
0x0920
adc_data low 8 bits
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Table 26 ADC register
ADDR [7]
[6:4]
[3:0]
0x0921 adc_setting
pre_divid[2:0]
adc_dataH
adc_setting: the setting time for ADC after power on，1：40us。 0：20us
pre_divid[2:0]: clock divider (the number should be set as 0x01)
adc_dataH：the higher 4 bits for adc_dat.
high resolution mode:{adc_dataH[3:0],adc_dataL[7:0]},
normal mode:
{adc_dataH[1:0],adc_dataL[7:0]}.
Table 27 ADC的SFR
ADDR
adc_rate
0x0923
adc_rate low 8 bits
Table 28 ADC register
ADDR [7]
[6:5]
[4]
[3:0]
0x0924 High_res_mode adc_dly[1：0]
vdd_chnn
adc_rate[11:8]
High_res_mode: 12 bits mode or 10 bits mode
adc_dly: the valid sample for the first conversion. Please set as 2 or 3 for this
register.
vdd_chnn: 1: set VDD as the input of ADC; 0: GPIO3 will be the input of ADC
adc_rate： the high 4 bits for adc_rate
Table 29 ADC register
12.1.3 Sample rate:
Given a ADC sample rate, you can calculate the adc_rate value as below:
ADC sample = system_clk/(( pre_divid+1)*( adc_rate+1))
ADC sample = system_clk/(( pre_divid+1)*( adc_rate+1))/4 High_res_mode
adc_rate = system_clk/(( pre_divid+1)*( ADC sample))-1
= system_clk/(2*( ADC sample)) -1
Note1: the sample rate should be not greater than 85k for 10bits mode.
Note2: the sample rate will decrease 4 times for high resolution mode.
Note3: the pre_divid should be set as 1.
Note4: In continue mode, the sample rate is fixed in spite of read or not by MCU. In
software mode, ADC will enter waiting state until the result is read by MCU
12.1.4 ADC usage
The reference voltage can be set as 1.2V or Vdd/2 for different application. Also, you
can decide whether add DC compensation for improving the negative input voltage.
BANK1
Reg07[26]
Select the reference voltage. 0: 1.2V; 1: VDD/2
Reg07[25]
Compensate the DC or not. 0: not compensate; 1: yes
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Table 30 ADC analog register
12.2 PWM
12.2.1 OVERVIEW
The PWM peripheral is an additional peripheral. The PWM is connected to the
Flip8051 through the external RAM interface.The Pulse Width Modulation can be used
in several kinds of applications. Typically, the PWM can be used to drive DC motors in
automotive applications, to generate DTMF in telecom applications or to generate AM
radio quality equivalent audio signals.
12.2.2 FUNCTIONAL DESCRIPTION
The PWM generates pulses of programmable length and period. To set up the duty
cycle, four registers are needed (depending on the resolution mode): one control register
PWMC, one register for the resolution, one register for the duty cycle PWMDCLSB and
in the case of high resolution, one other register for the duty cycle PWMDCMSB. The
PWM can operate in two modes:
• High-resolution mode (10 bits): registers PWMDCLSB and PWMDCMSB are used.
• Standard-resolution mode (8 bits): the register PWMDCMSB is not used.
When operating in the standard-resolution mode, only the PWMDCLSB is taken into
account.
When the resolution for the application is decided, it’s advised not to change it again.
The PWM address is show as below; the basic address is 0XA00 in external RAM
space.
ADDRESS
PWM_CTRL
PWM_DCLSB
PWM_DCMSB PWM_RESOLUTION
PWM0
0XA00
0XA01
0XA02
0XA03
PWM1
0XA04
0XA05
0XA06
0XA07
PWM2
0XA08
0XA09
0XA0A
0XA0B
PWM3
0XA0C
0XA0D
0XA0E
0XA0F
PWM4
0XA10
0XA11
0XA12
0XA13
Table 31 PWM register address
All the five PWM have the same operation. Next, we will describe the detail usage of
PWM0.
register[bit]
控制信号名
[7]
pwm0_dcresol
[6]
[5:0]
[7:0]
en_pwm0
ADDR
pwm0_prescaler
pwm0_dclsb
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Operation
R/W
0XA00
0XA00
0XA00
0XA01
R/W
R/W
R/W
Function
PWM0 Duty Cycle Resolution
1'b0 = & gt; standard resolution
1'b1 = & gt; high resolution
Enable PWM0
PWM0 prescaler
PWM0 Duty Cycle LSB
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[7:0]
[7:0]
pwm0_dcmsb
pwm0_resol
0XA02
0XA03
R/W
R/W
PWM0 Duty Cycle MSB
PWM0 resolution
pwm0_dcresol: Duty Cycle Resolution.
This bit is used to select the duty cycle resolution. It is advised to set the resolution
only once, at the beginning of the application and not to change it after.
0 = the 8-bit resolution mode is selected (Standard resolution).
1 = the 10-bit resolution mode is selected (High resolution).
ENPWM: Enable Pulse Width Modulation.
This bit controls the pulse width modulation output. While this bit is low, the output is
disabled.
0 = The PWM output is disabled.
1 = The PWM output is enabled.
When the bit ENPWM is cleared, the user can change the prescaler, and then the period
of the pulse width modulation output is modified. The period can be changed at each
cycle of clock.
The way to configure the output period is:
Disable the bit ENPWM
Write the value of the prescaler (bits 5 downto 0 of the register PWMCTRL)
Enable the bit ENPWM (bit 6 of the register PWMCTRL).
PWMPESCALER: Pulse Width Modulation Prescaler.
This field is used to set the repetition rate of the square wave available at output PWM.
The frequency of this square wave is given by the following formula:
PWM_resoluation: the 8 bit register decide the stop counter of the PWM. It can be used
to adjust the resolution of PWM.
PWMDCLSB and PWMDCMSB registers are used to set the duty cycle of the square
wave generated. These registers are constantly compared to an internal counter. The size
of this counter is function of the resolution (8 or 10 bits). This gives a pulse width
modulation in the range of 0/(1~255) to 255/(1~255) for the standard-resolution and
0/(769~1023) to 1023/(769~1023)for the high-resolution.
The PWMDC value indicates the duration of the high level:
If PWMDC=all zeros, PWMOUT stays low.
If PWMDC=all ones, PWMOUT stays high.
resoluation
duty
Figure 15 PWM parameter
12.2.3 Frequency of PWM
The frequency of PWM can be calculated by the next formula.
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NOTE: the default value of pwm_resol is 255, it cannot be set as zero. The value is
preferred be set more than127.
NOTE: PWMPESCALER cannot be set as zero, or overflow will be happened.
NOTE: The duty cycle is set dynamically. During a period, it is possible to change the
duty cycle.
12.3 I2C master
12.3.1 Overview
The Inter-Integrated Circuit (I2C) master controller is a simple bi-directional 2-wire
bus, which provides an interface between BK2461 and an I2C bus.
The I2C mater handles all functions necessary to establish and maintain data link:
Fast and standard transfer rates.
7-bit addressing on I2C.
Simple master operations.
Clock Stretching and Wait State generation.
Operates from a wide range of input frequencies.
Interrupt generation.
Fully synthesizable, static synchronous design.
Received and Transmit Data are stored respectively in Receive Buffer and Transmit
Buffer. Only one byte at a time can be stored in each buffer. During an I2C transaction,
the CPU needs to read regularly the Receive Buffer and to write regularly the Transmit
Buffer.
NOTE: Arbitration for multi-master use is not supported by BK2461.
12.3.2 List of I2CM register
Mnemonic
MCON
MRXBUF
MTXBUF
MPRESC
MSTAT0
MSTAT1
MIEN0
MIEN1
MCADDR
Name
I2CM Control register
I2CM Reception buffer
I2CM Transmission Buffer
I2CM Pre-scalar clock register
I2CM Status register 0
I2CM Status register 1
I2CM Interrupt Enable register 0
I2CM Interrupt Enable register 1
I2CM Call Address register
Table 32 I2CM register
Addre
S:0E1
S:0E2
S:0E3
S:0E4
S:0E5
S:0E6
S:0E7
S:0D2
S:0D4
MCON (S:E1h) I2CM Control Register
BIT
FIELD
7
--
6
--
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5
WAIT
4
--
3
STOP
2
SRST
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STA
0
BUSY
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RESET
0000 0000b
Bit
Number
7
Bit
Mnemonic
--
Function
Reserved
The value read from this bit is indeterminate.
Reserved
The value read from this bit is indeterminate.
Wait state mode
‘1’: Generate wait state on SCL line when RX overflows.
‘0’: Send “Not Acknowledge” to stop the transmission when
RX
Reserved
The value read from this bit is 0.
Generate Stop condition
When this bit is set, the current byte ends normally and a STOP
condition is generated just after the acknowledge cycle.
This bit is automatically cleared by the controller when the
STOP
Software reset
This bit is automatically cleared once IDLE state is reached.
Generate Start condition
This bit is automatically cleared by the controller when the
transmission has begun or if an error is detected.
BUSY flag
This bit is set to ‘1’ when an I2C frame transfer is in progress on I2C bus.
6
5
WAIT
4
--
3
STOP
2
SRST
1
STA
0
BUSY
Table 33 I2CM Control Register (MCON)
MRXBUF (S:E2h) Read only I2CM Receive Buffer
Bit
Number
7:0
Bit
Mnemonic
RXBUF
Function
Data received by I2CM
Table 34 I2CM Receive Register (MRXBUF)
MTXBUF (S:E3h) Write only I2CM Transmit Buffer
Bit
Number
7:0
Bit
Mnemonic
TXBUF
Function
Data transmitted by I2CM
Table 35 I2CM Transmit Buffer (MTXBUF)
MPRESC (S:E4h) I2CM Clock Prescalar Register
MPRESC register enables to generate OSCL output from a large range of CLK frequency.
Bit
Number
7:0
Bit
Mnemonic
PRESC
Function
Clock pre scalar register
Fscl = Fclk/10*(1+PRESC)
Default value
‘h00
Table 36 I2CM MPRESC Register
Note: This register should not be written during a transmission.
MSTAT0 (S:E5h) I2CM Status Register 0
Bit
Number
7
Bit
Mnemonic
--
6
--
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Function
Reserved
The value read from this bit is indeterminate.
Reserved
The value read from this bit is indeterminate.
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5
--
4
DNA
3
SANA
2
UNF
1
OVF
0
NEND
Reserved
The value read from this bit is indeterminate.
Data byte not acknowledged
Data byte not acknowledged during transmission. Stop condition sent.
Slave Address Not Acknowledged
Slave Address not acknowledged. Stop condition sent.
Under Flow
Transmit Data Byte not ready (Transmit Buffer is empty) while a new data
byte needs to be sent. A STOP condition is sent.
Receive Overflow
Received Data Byte could not be written (Receive Buffer is full) while a
new byte was received.
A Not Acknowledge and a STOP condition are sent.
Normal End (End of access with no error)
Set when a stop is sent at the end of a successful access.
Clear automatically when a new I2C access starts.
Table 37 I2CM Status Register 0 (MSTAT0)
These interrupt sources are automatically cleared after a read access to this register.
When DNA, SANA, UNF or OVF flags have been set, reception and transmission processes are disabled until the
CPU has read MSTAT0 register. This read operation automatically resets MSTAT0 register and MCON.STA bit, if one
of these error bits is set. If this read operation is performed while no error bit is set, MCON.STA bit is not cleared.
These interrupt sources can all be individually enabled/disabled by MIEN0 register.
MSTAT1 (S:E6h) Read only I2CM Status Register 1
Bit
Number
7
Bit
Mnemonic
--
6
--
5
TBE
4
--
3
TBF
2
RBE
1
--
0
RBF
Function
Reserved
The value read from this bit is indeterminate.
Reserved
The value read from this bit is indeterminate.
Transmission buffer is empty
'1': Transmit Buffer empty.
This flag is cleared when the CPU performs a write access to TXDATA
register.
'0': At least one Transmit Data Byte is available.
Reserved
The value read from this bit is 0.
Transmission buffer is full
'1': Transmit Buffer full.
No more write operation into transmit buffer or memory is performed
(CPU write request to TXDATA not taken in account).
This flag is cleared when a new Data Byte is requested by the TXRX
controller.
'0': Transmit Buffer is empty
Reception buffer is empty
'1': Receive Buffer empty.
No more write operation into receive buffer or memory is performed (CPU
read request to RXDATA not taken in account). This flag is cleared when
a new Data Byte is received by the TXRX controller.
'0': At least one received Data Byte is available.
Reserved
The value read from this bit is indeterminate.
Reception buffer is full
'1': Receive Buffer full.
This flag is cleared when the CPU performs a read operation to RXDATA
register.
'0': Receive Buffer is empty
Table 38 I2CM Status Register 1 (MSTAT1)
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These interrupt sources can all be individually enabled/disabled by MIEN1 register.
MIEN0 (S:E7h) I2CM Interrupt Enable Register 0
Bit
Number
7
Bit
Mnemonic
--
6
--
5
--
4
EDNA
3
ESANA
2
EUNF
1
EOVF
0
ENEND
Function
Reserved
The value read from this bit is indeterminate.
Reserved
The value read from this bit is indeterminate.
Reserved
The value read from this bit is indeterminate.
Data byte Not Acknowledged Interrupt enable bit
Clear to disable MSTAT0.DNA bit to generate an interrupt request
Set to enable MSTAT0.DNA bit to generate an interrupt request
Slave Address Not Acknowledged Interrupt enable bit
Clear to disable MSTAT0.SANA bit to generate an interrupt request
Set to enable MSTAT0.SANA bit to generate an interrupt request
Underflow Interrupt enable bit
Clear to disable MSTAT0.UNF bit to generate an interrupt request
Set to enable MSTAT0.UNF bit to generate an interrupt request
Overflow Interrupt enable bit
Clear to disable MSTAT0.OVF bit to generate an interrupt request
Set to enable MSTAT0.OVF bit to generate an interrupt request
Normal End Interrupt enable bit
Clear to disable MSTAT0.NEND bit to generate an interrupt request
Set to enable MSTAT0.NEND bit to generate an interrupt request
Table 39 I2CM Interrupt Enable register 0 (MIEN0)
MIEN1 (S:D2h) I2CM Interrupt Enable Register 1
Bit
Number
7
Bit
Mnemonic
--
6
--
5
ETBE
4
--
3
ETBF
2
ERBE
1
--
0
ERBF
Function
Reserved
The value read from this bit is indeterminate.
Reserved
The value read from this bit is indeterminate.
Transmission Buffer Empty Interrupt enable bit
Clear to disable MSTAT1.TBE bit to generate an interrupt request
Set to enable MSTAT1.TBE bit to generate an interrupt request
Reserved
The value read from this bit is indeterminate.
Transmission Buffer Full Interrupt enable bit
Clear to disable MSTAT1.TBF bit to generate an interrupt request
Set to enable MSTAT1.TBF bit to generate an interrupt request
Reception Buffer Empty Interrupt enable bit
Clear to disable MSTAT1.RBE bit to generate an interrupt request
Set to enable MSTAT1.RBE bit to generate an interrupt request
Reserved
The value read from this bit is indeterminate.
Reception Buffer Full Interrupt enable bit
Clear to disable MSTAT1.RBF bit to generate an interrupt request
Set to enable MSTAT1.RBF bit to generate an interrupt request
Table 40 I2CM Interrupt Enable register 1 (MIEN1)
MCADDR (S:D4h)I2CM Call Address Register
Bit
Number
Bit
Mnemonic
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Function
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7
RWN
6:0
CADDR
Read/write control bit for I2C transaction Set
to read data from addressed slave device Clear
to write data to the addressed slave device
7-bit Call Address
This register must be written before the beginning of an I2C transaction.
Table 41 I2CM Call address register (MCADDR)
12.3.3 I2C frame data format
This I2C master controller only support 7-bit format as shown on the figure below:
Figure 16 Complete data transfer
All words put on the SDA line are 8-bits long
Each byte is followed by an acknowledge bit set by receiver. Data is transferred with the
most significant bit (MSB) first.
After the Start condition (S), a slave address is sent. This address is 7 bits long. The eighth
bit determines the direction of the message (R/WN): a ‘0’ means that the master will write
data to a selected slave, a ‘1’ means that the master will read data from a selected slave.
A data transfer is always terminated by Stop condition (P). However, if the master still
wishes to communicate on the bus, it can generate a Repeated Start (Sr) that this to say to
generate another START without first generating a STOP. Various combinations of
read/write formats are then possible within such a transfer.
Note that two groups of eight addresses (0000XXX and 1111XXX) are reserved for
purposed shown in the following table.
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CALL
ADDRESS
0000 000
RWN
Bit
0
Description
General call address.
It is used to address every device connected to I2C-bus.
START byte(1)
CBUS address (2).
Reserved for different bus format.
Reserved for future purposes.
High Speed master code.
Reserved for future purposes.
10-bit slave addressing. Not yet supported.
0000 000
1
0000 001
X
0000 010
X
0000 011
X
0000 1XX
X
1111 1XX
X
1111 0XX
X
(1) : No device enables to acknowledge at the reception of the START byte.
(2) : The CBUS address has been reserved to enable the intermixing of CBUS compatible and the I2C-bus
compatible devices in the same system. I2C-bus compatible devices are not allowed to respond on
reception of this address.
Table 42 Reserved addresses for I2Cansactions
12.3.4 Acknowledge
Data transfer with acknowledge is mandatory. The clock pulse related to acknowledge is
generated by the master. The transmitter releases the SDA line (High) during the
acknowledge clock pulse. The receiver must pull down the SDA line during the acknowledge
pulse so that it remains stable Low during the High period of this clock pulse.
When a slave does not acknowledge the slave address or the data, the data line SDA must
be left high by the slave. Then the master can generate a Stop condition to abort the transfer.
Figure 17 " not acknowledge " by slave
If a master receiver is involved in a transfer it must signal the end of data to the slave
transmitter by not generating an acknowledgement after sending a byte. The slave will
release SDA line to allow the master to generate Stop or repeated condition.
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Figure 18 " not acknowledge " by master (end of transmission)
12.3.5 Clock synchronization and wait state
For this device the clock synchronization will be used to enable slaves to hold the SCL line
Low after reception and acknowledgement of a byte to force the master into a wait state. This
enables to slave devices to get more time to store a received byte or prepare another byte to
be transmitted.
Figure 19 Clock synchronization as handshake
Clock synchronization is performed using the “wired AND” connection of I2C interface
to the SCL line. This means that a High to Low transition on the SCL line will cause devices
concerned to start counting off their Low period. At the end of their own Low period, devices
will set their clocks High. However, SCL line will stay Low as long as one clock is still
within its Low period. The SCL line will therefore be held Low by the device with the
longest Low period. Devices with shorter Low periods enter a High wait state during this
time. When all devices concerned have counted off their Low period, SCL line will be
released and go High. There will then be no difference between device clocks and SCL line,
and all devices will start counting their High periods. The first device to complete its High
period will again pull the SCL line Low. In this way, a synchronized clock is generated.
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Figure 20 Clock synchronization
12.3.6 Master mode: Transmission
Figure 21 Typical transmission
12.3.6.1 Initialization
Before starting the transmission, the CPU has to write slave address into MCADDR
register. Note that for a write request the LSB of the slave address must be set to ‘0’.
The CPU will have to write a data byte regularly into the Transmit Buffer (MTXBUF register)
during the transaction (care must be taken to avoid underflow). TBF (Transmit Buffer Full)
or TBE (Transmit Buffer Empty) flags can be used to check the status of the Transmit Buffer.
12.3.6.2 Start
After initialization, CPU can start the transmission by setting the STA bit of the MCON
register. Then, the master controller generates the Start condition on the I2C-bus. The STA
bit is automatically cleared when the transmission has begun slave address transmission.
After that start has been sent, the slave address is loaded in the shift register to be
transmitted on the I2C-bus and the master controller requests the first data byte to the
Transmit. Once the slave address had been transmitted, the master controller waits for the
slave address Acknowledge from the slave controller.
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12.3.6.3 Data transmission
If the slave controller returns a slave address acknowledge, the master controller loads the
data byte in the shift register to be transmitted on the I2C-bus. If this data byte was not the
last one, the master sends a request to read the next data byte. Once data byte had been
transmitted, the master controller waits for the data acknowledge from slave controller. In
case of acknowledge and if data byte sent was not the last one, the controller sends another
data byte.
Detection of last data byte:
The data byte is the last data byte if STOP bit is set.
Note: Due to the size of the transmit buffer (1 byte), the first transmitted data byte is also
the last data byte.
12.3.6.4 Stop and Repeated Start
Once last data byte had been transmitted, the master controller waits for the data
acknowledge from slave controller. In case of acknowledge, if STA is set to ‘1’ by the CPU,
the controller will generate a Repeated Start in order to access to an other slave device or
change the direction of the transfer (Master Mode Reception) else a Stop condition is sent to
finish the communication. The STOP bit is automatically cleared once the Stop condition or
repeated Start has been sent.
In case of Repeated Start, the CPU must initialize the next transmission (write of Slave
address, length and data bytes) before the end of the current transmission.
Figure 22 Repeated Start or Stop condition after last byte
12.3.6.5 Transmission error
Not acknowledge from Slave Controller
If the slave address is not acknowledged by the slave controller, the master interrupts the
transmission by sending a Stop condition, and sets SANA flag.
If data is not acknowledged by the slave controller, the master interrupts the transmission by
sending a Stop condition, and sets DNA flag.
Transmit Underflow
If no data byte is valid from the Transmit Buffer when the controller needs to transmit a data
byte, the master interrupts the transmission by sending a Stop condition, and sets UNF flag.
Such underflow occurs when the Transmit Buffer is empty (the CPU did not fill in time the
Transmit Buffer).
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End of error
When an error is detected, OTXRXINT output is set if the corresponding interrupt source is
enabled. The Controller is blocked until MSTAT0 register is read by the CPU. This read
operation resets MSTAT0 register and STA bit to disable potential Repeated Start. To pursue
the transmission, the CPU must set STA only. To restart the same transmission from the
beginning, the CPU must set software reset, refill MTXBUF and then set STA.
12.3.6.6 Transmission FSM
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Figure 23 Transmission FSM
Note: If an error occurs during the transmission, FSM will stay into “SEND STOP” state
until MSTAT0 register had been read by the CPU. This read operation will clear the STA bit
of MCON register and MSTAT0 register. Since MSTAT0 register and MCON register had
been reinitialized, the FSM is released into “IDLE” state.
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12.3.7 Master mode: Reception
Figure 24 Typical reception
12.3.7.1 Initialization
Before starting the reception, the CPU has to write Slave address into the MCADDR register.
Note that for a read request the LSB of the slave address must be set to ‘1’.
The CPU will have to read the received data bytes in the Receive Buffer (MRXBUF register)
regularly during the transaction (care must be taken to avoid overflow).
12.3.7.2 Start
After initialization, the CPU can start the reception by setting the STA bit of the MCON
register. Then, the master controller generates the Start condition on the I2C-bus. The STA
bit is automatically cleared when the transmission has begun.
Now the slave address is loaded in the shift register to be transmitted on the I2C-bus. Once
the slave address had been transmitted, the master controller waits for the slave address
acknowledge from the slave controller. If the slave controller returns a slave address
acknowledgement, the master controller is waiting for first received data byte.
12.3.7.3 Reception
Once a data byte had been received, it is stored by the master controller in the Receive.
More over, if received data byte is not the last one, the master controller sends an
acknowledgement on the I2C-bus. Otherwise a “Not Acknowledge” is sent to indicate that it
was the last read request and that slave controller must release the I2C bus to allow
generating stop condition.
After the data acknowledge transmission, a new data reception can be done and the CPU can
read the stored data using MRXBUF register.
Detection of last data byte:
The data byte is the last data byte if STOP bit is set.
Note: Due to the size of the receive buffer (1 byte), the first received data byte is also the
last data byte.
12.3.8 Stop and Repeated Start
After the “data not acknowledge” transmission, if STA is set to ‘1’ by the CPU, the controller
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will generate a Repeated Start in order to access to another slave device or change the
direction of the transfer (Master mode Transmission) else a Stop condition is sent to finish
the communication. The STOP bit is automatically cleared once the Stop condition or
repeated Start has been sent.
In case of Repeated Start, the CPU must initialize the next transmission (write of Slave
address, length and data bytes) before the end of the current reception.
Figure 25 Repeated Start or Stop condition after last byte
12.3.8.1 Reception error
Not acknowledge from Slave Controller
If the slave address is not acknowledged by the slave controller, the master interrupts the
transmission by sending a Stop condition, and sets SANA flag.
Receive Overflow
When a data byte is received, the TXRX controller checks that the previous data byte has
been handled. If it is not the case (RXBUF overflow), the master interrupts the reception by
sending “not acknowledge “ and a Stop condition, and sets OVF flag.
End of error
When an error is detected, OTXRXINT output is set if the corresponding interrupt source
is enabled. The controller is blocked until MSTAT0 register is read by the CPU. This read
operation resets MSTAT0 register and STA bit to disable a potential Repeated Start. If the
CPU wants to discard previous received data byte, it must set software reset. To restart the
same transmission, the CPU just has to set STA.
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12.3.9 Reception FSM
Figure 26 Reception FSM
Note: If an error occurs during the reception, FSM will stay into “SEND STOP” state until
MSTAT0 register had been read by the CPU. This read operation will clear the STA bit of
MCON register and MSTAT0 register. Since MSTAT0 register and MCON register had been
reinitialized, the FSM is released into “IDLE” state.
12.3.10
Data Handling
The Data Bytes exchanged on the I2C line are available in MRXBUF (received data) and
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MTXBUF (transmitted data) registers.
It is up to the user of the FlipI2CM to read/write data byte exchanged on the I2C line when
they are available. This can be handled by software routine thanks to the status flags.
12.3.11
Software Reset
The software reset is activated by CPU setting bit SRST of control register (MCON). The
software reset is used to stop current access on I2C bus.
Software reset initializes MCON, MSTAT0 registers and also TXRX controller.
If a software reset occurs during an I2C access, the master controller finishes the transmit or
reception of current data byte, it send a Stop condition (in case of reception, send a ”not
acknowledge " first) and next, MCON and MSTAT0 registers and TXRX controller are
cleared.
At the end of software reset process, the master controller is ready to restart a new or the
same access. For same access, the CPU must refill TXBUF (for transmission only) and set
STA (MCADDR register is not affected by software reset).
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12.4 Ext_timer
A simple timer is integrated in BK2535 for fixed time interrupt for some special
application, such as mouse. (8ms wake up)
This timer selects 32k clock always for avoiding the effect brought by clock switch.
The period can be set precisely through the register descript below:
ADDR
[7:3]
[2]
[1:0] timer_div
0X918
reserved
RTC enable
RTC clock divider
[7:0] timer_count
0X919
RTC counter high byte
Counter[15:0]=
[0X919,0X91A]
0X91A
RTC counter low byte
Table 43 RTC Register
RTC period = 1/32e3 *（2+ timer_div） * ( 1+timer_count)
For example, if you want to get 8ms period wakeup, you can set timer_div=2 and
timer_count=63.
Note: to enable the RTC interrupt, you should set EA= 1 and EX6 = 1.
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12.5 WDT
There is a watch dog timer in BK2535. When overflow happened, the WDT will
trigger the CPU into reset status and rerun from the beginning location. The
software need feed the dog timely to avoid the overflow happen.
Note: the reset does not affect the RF part.
There are two methods to enable the WDT.
One is writing 0Xa5 on SFR address 0XA6(WDCON) and this operation will
clear the WDT counter also (feed dog). Once the WDT enabled by this method, you
can disable the WDT through writing 0XDE and 0XAD consecutively during eight
clock periods. When the WDT enabled by this method, you can also set whether
running in IDLE state. To do this, you can enable it by writing 0XD1 on SFR
address 0XA6 or disable it by writing 0XDE and 0XDA consecutively during eight
clock periods.
The other method is writing 0XFF on SFR address 0XA6. You cannot close it
once you enable the WDT with this method except any reset happened. In this status,
the WDT will run always even in IDLE state.
WDCON
0XA6
7
/
6
/
5
/
4
state
3
/
2
ps2
1
ps1
0
ps0
Table 44 Watch Dog Register
State: read only 1: the WDT in active status 0: the WDT in inactive status
Ps2, ps1, ps0: the prescale of watch dog clock.
Note: when write the prescale value, the bit7 must be set as 0.
PS2
PS1
PS0
PRE_scale
0
0
0
2
0
0
1
4
0
1
0
8
0
1
1
16
1
0
0
32
1
0
1
64
1
1
0
128
1
1
1
256
Table 45 the Prescale of Watch Dog clock
The overflow time of watch dog：
PRE _ scale × 32768
WatchdogOverflowTime =
system clock
When overflow occur, the whole system will be reset.
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13 BK2461 RF transceiver
13.1 General Description
A RF transceiver (BK-RF) is embedded
in BK2461, and the BK-RF is a high
performance IP of Beken corporation.
BK-RF is a GFSK transceiver operating
in the world wide ISM frequency band at
2400-2483.5 MHz
Burst mode
transmission and up to 2Mbps air data
rate make them suitable for applications
requiring ultra low power consumption.
The embedded packet processing
engines enable their full operation with a
very simple MCU as a radio system.
Auto
re-transmission
and
auto
acknowledge give reliable link without
any MCU interference.
The BK-RF operates in TDD mode,
either as a transmitter or as a receiver.
The RF channel frequency determines
the center of the channel used by BK-RF.
The frequency is set by the RF_CH
register in register bank 0 according to
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the following formula: F0= 2400 +
RF_CH (MHz). The resolution of the RF
channel frequency is 1MHz.
A transmitter and a receiver must be
programmed with the same RF channel
frequency to be able to communicate
with each other.
The output power of BK-RF is set by the
RF_PWR bits in the RF_SETUP register.
Demodulation is done with embedded
data slicer and bit recovery logic. The air
data rate can be programmed to 1Mbps
or 2Mbps by RF_DR register. A
transmitter and a receiver must be
programmed with the same setting.
In the following chapters, all registers
are in register bank 0 except with
explicit claim.
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FM
Demodulator
Integrated
TDD RF
Transceiver
Packet
Processing &
State Control
Power
Management
Gaussian
shaping
Tx FIFO
MCU
IRQ
CE
Register
banks
FM Modulator
XTALP
Rx FIFO
Data Slicer
MCU
Interface
RFP
RFN
XTALN
Figure 27 BK2461 RF Block Diagram
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13.2 Abbreviations
ACK
ARC
ARD
CD
CE
CRC
CSN
DPL
FIFO
GFSK
GHz
LNA
IRQ
ISM
LSB
MAX_RT
Mbps
MCU
MHz
MISO
MOSI
MSB
PA
PID
PLD
PRX
PTX
PWD_DWN
PWD_UP
RF_CH
RSSI
RX
RX_DR
SCK
SPI
TDD
TX
TX_DS
XTAL
Acknowledgement
Auto Retransmission Count
Auto Retransmission Delay
Carrier Detection
Chip Enable
Cyclic Redundancy Check
Chip Select Not
Dynamic Payload Length
First-In-First-Out
Gaussian Frequency Shift Keying
Gigahertz
Low Noise Amplifier
Interrupt Request
Industrial-Scientific-Medical
Least Significant Bit
Maximum Retransmit
Megabit per second
Microcontroller Unit
Megahertz
Master In Slave Out
Master Out Slave In
Most Significant Bit
Power Amplifier
Packet Identity Bits
Payload
Primary RX
Primary TX
Power Down
Power Up
Radio Frequency Channel
Received Signal Strength Indicator
Receive
Receive Data Ready
SPI Clock
Serial Peripheral Interface
Time Division Duplex
Transmit
Transmit Data Sent
Crystal
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13.3 State Control
13.3.1 State Control Diagram
Internal signal: POR,VDD
SPI register: CE, PWR_UP,
PRIM_RX, EN_AA, NO_ACK,
ARC, ARD
System information: Time out, ACK
received, ARD elapsed, ARC_CNT,
TX FIFO empty, ACK packet
transmitted, Packet received
BK-RF has built-in state machines that
control the state transition between
different modes.
When auto acknowledge feature is
disabled, state transition will be fully
controlled by MCU.
VDD & gt; =1.9 V
Power Down
PWR_UP=1
PWR_UP=0
Standby-I
CE=1
ARD elapsed and ARC_CNT & lt; ARC
Time out or ACK received
CE=0
CE=0
TX FIFO empty
RX
Standby-II
TX
TX FIFO
Data Ready
EN_AA=1
NO_ACK=0
Figure 28 PTX (PRIM_RX=0) state control diagram
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VDD & gt; =1.9 V
Power Down
PWR_UP=1
PWR_UP=0
Standby-I
CE=1
CE=0
CE=0
ACK packet transmitted
RX
TX
Packet received
EN_AA=1
NO_ACK=0
Figure 29 PRX (PRIM_RX=1) state control diagram
BK-RF returns to from TX or RX mode
when CE is set low.
13.3.2 Power Down Mode
In power down mode the BK-RF is in
sleep mode with minimal current
consumption. SPI interface is still active
in this mode, and all register values are
available by SPI. Power down mode is
entered by setting the PWR_UP bit in
the CONFIG register to low.
13.3.3 Standby-I Mode
By setting the PWR_UP bit in the
CONFIG register to 1 and de-asserting
CE to 0, the device enters standby-I
mode. Standby-I mode is used to
minimize average current consumption
while maintaining short start-up time. In
this mode, part of the crystal oscillator is
active. This is also the mode which the
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13.3.4 Standby-II Mode
In standby-II mode more clock buffers
are active than in standby-I mode and
much more current is used. Standby-II
occurs when CE is held high on a PTX
device with empty TX FIFO. If a new
packet is uploaded to the TX FIFO in
this mode, the device will automatically
enter TX mode and the packet is
transmitted.
13.3.5 TX Mode
PTX device (PRIM_RX=0)
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The TX mode is an active mode where
the PTX device transmits a packet. To
enter this mode from power down mode,
the PTX device must have the PWR_UP
bit set high, PRIM_RX bit set low, a
payload in the TX FIFO, and a high
pulse on the CE for more than 10µs.
The PTX device stays in TX mode until
it finishes transmitting the current packet.
If CE = 0 it returns to standby-I mode. If
CE = 1, the next action is determined by
the status of the TX FIFO. If the TX
FIFO is not empty the PTX device
remains in TX mode, transmitting the
next packet. If the TX FIFO is empty the
PTX device goes into standby-II mode.
If the auto retransmit is enabled
(EN_AA=1) and auto acknowledge is
required (NO_ACK=0), the PTX device
will enter TX mode from standby-I
mode when ARD elapsed and number of
retried is less than ARC.
PRX device (PRIM_RX=1)
The PRX device will enter TX mode
from RX mode only when EN_AA=1
and NO_ACK=0 in received packet to
transmit acknowledge packet with
pending payload in TX FIFO.
standby-I mode, the PRX device must
have the PWR_UP bit set high,
PRIM_RX bit set high and the CE pin
set high. Or PRX device can enter this
mode from TX mode after transmitting
an acknowledge packet when EN_AA=1
and NO_ACK=0 in received packet.
In this mode the receiver demodulates
the signals from the RF channel,
constantly presenting the demodulated
data to the packet processing engine.
The
packet
processing
engine
continuously searches for a valid packet.
If a valid packet is found (by a matching
address and a valid CRC) the payload of
the packet is presented in a vacant slot in
the RX FIFO. If the RX FIFO is full, the
received packet is discarded.
The PRX device remains in RX mode
until the MCU configures it to standby-I
mode or power down mode.
In RX mode a carrier detection (CD)
signal is available. The CD is set to high
when a RF signal is detected inside the
receiving frequency channel. The
internal CD signal is filtered before
presented to CD register. The RF signal
must be present for at least 128 µs
before the CD is set high.
13.3.6 RX Mode
The PTX device will enter RX mode
from TX mode only when EN_AA=1
and NO_ACK=0 to receive
acknowledge packet.
PRX device (PRIM_RX=1)
The RX mode is an active mode where
the BK-RF radio is configured to be a
receiver. To enter this mode from
© 2015 Beken Corporation
PTX device (PRIM_RX=0)
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13.4 Packet Processing
13.4.1 Packet Format
The packet format has a preamble, address, packet control, payload and CRC field.
Preamble 1 byte
Address 3~5 byte
Packet Control 9/0 bit
Payload Length 6 bit
Payload 0~32 byte
PID 2 bit
CRC 2/1 byte
NO_ACK 1 bit
Figure 30 Packet Format
Preamble
EN_RXADDR register. By default only
data pipe 0 and 1 are enabled.
The preamble is a bit sequence used to
detect 0 and 1 levels in the receiver. The
preamble is one byte long and is either
01010101 or 10101010. If the first bit in
the address is 1 the preamble is
automatically set to 10101010 and if the
first bit is 0 the preamble is
automatically set to 01010101. This is
done to ensure there are enough
transitions in the preamble to stabilize
the receiver.
Address
This is the address for the receiver. An
address ensures that the packet is
detected by the target receiver. The
address field can be configured to be 3, 4,
or 5 bytes long by the AW register.
The PRX device can open up to six data
pipes to support up to six PTX devices
with unique addresses. All six PTX
device
addresses
are
searched
simultaneously. In PRX side, the data
pipes are enabled with the bits in the
© 2015 Beken Corporation
Each data pipe address is configured in
the RX_ADDR_PX registers.
Each pipe can have up to 5 bytes
configurable address. Data pipe 0 has a
unique 5 byte address. Data pipes 1-5
share the 4 most significant address
bytes. The LSB byte must be unique for
all 6 pipes.
To ensure that the ACK packet from the
PRX is transmitted to the correct PTX,
the PRX takes the data pipe address
where it received the packet and uses it
as the TX address when transmitting the
ACK packet.
On the PRX the RX_ADDR_Pn, defined
as the pipe address, must be unique. On
the PTX the TX_ADDR must be the
same as the RX_ADDR_P0 on the PTX,
and as the pipe address for the
designated pipe on the PRX.
No other data pipe can receive data until
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a complete packet is received by a data
pipe that has detected its address. When
multiple PTX devices are transmitting to
a PRX, the ARD can be used to skew the
auto retransmission so that they only
block each other once.
Packet Control
When Dynamic Payload Length function
is enabled, the packet control field
contains a 6 bit payload length field, a 2
bit PID (Packet Identity) field and, a 1
bit NO_ACK flag.
Payload length
The payload length field is only used if
the Dynamic Payload Length function is
enabled.
PID
The 2 bit PID field is used to detect
whether the received packet is new or
retransmitted. PID prevents the PRX
device from presenting the same payload
more than once to the MCU. The PID
field is incremented at the TX side for
each new packet received through the
SPI. The PID and CRC fields are used
by the PRX device to determine whether
a packet is old or new. When several
data packets are lost on the link, the PID
fields may become equal to the last
received PID. If a packet has the same
PID as the previous packet, BK-RF
compares the CRC sums from both
packets. If the CRC sums are also equal,
the last received packet is considered a
copy of the previously received packet
and discarded.
NO_ACK
The NO_ACK flag is only used when
the auto acknowledgement feature is
© 2015 Beken Corporation
used. Setting the flag high, tells the
receiver that the packet is not to be auto
acknowledged.
The PTX can set the NO_ACK flag bit
in the Packet Control Field with the
command:
W_TX_PAYLOAD_NOACK.However,
the function must first be enabled in the
FEATURE register by setting the
EN_DYN_ACK bit. When you use this
option, the PTX goes directly to
standby-I mode after transmitting the
packet and the PRX does not transmit an
ACK packet when it receives the packet.
Payload
The payload is the user defined content
of the packet. It can be 0 to 32 bytes
wide, and it is transmitted on-air as it is
uploaded (unmodified) to the device.
The BK-RF provides two alternatives for
handling payload lengths, static and
dynamic payload length. The static
payload length of each of six data pipes
can be individually set.
The default alternative is static payload
length. With static payload length all
packets between a transmitter and a
receiver have the same length. Static
payload length is set by the RX_PW_Px
registers. The payload length on the
transmitter side is set by the number of
bytes clocked into the TX_FIFO and
must equal the value in the RX_PW_Px
register on the receiver side. Each pipe
has its own payload length.
Dynamic Payload Length (DPL) is an
alternative to static payload length. DPL
enables the transmitter to send packets
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with variable payload length to the
receiver. This means for a system with
different payload lengths it is not
necessary to scale the packet length to
the longest payload.
The transmitter fetches payload from TX
FIFO, automatically assembles it into
packet and transmits the packet in a very
short burst period with 1Mbps or 2Mbps
air data rate.
With DPL feature the BK-RF can
decode the payload length of the
received packet automatically instead of
using the RX_PW_Px registers. The
MCU can read the length of the received
payload by using the command:
R_RX_PL_WID.
After transmission, if the PTX packet
has the NO_ACK flag set, BK-RF sets
TX_DS and gives an active low interrupt
IRQ to MCU. If the PTX is ACK packet,
the PTX needs receive ACK from the
PRX and then asserts the TX_DS IRQ.
In order to enable DPL the EN_DPL bit
in the FEATURE register must be set. In
RX mode the DYNPD register has to be
set. A PTX that transmits to a PRX with
DPL enabled must have the DPL_P0 bit
in DYNPD set.
The receiver automatically validates and
disassembles received packet, if there is
a valid packet within the new payload, it
will write the payload into RX FIFO, set
RX_DR and give an active low interrupt
IRQ to MCU.
CRC
The CRC is the error detection
mechanism in the packet. The number of
bytes in the CRC is set by the CRCO bit
in the CONFIG register. It may be either
1 or 2 bytes and is calculated over the
address, Packet Control Field, and
Payload.
The polynomial for 1 byte CRC is X8 +
X2 + X + 1. Initial value is 0xFF.
The polynomial for 2 byte CRC is X16 +
X12 + X5 + 1. Initial value is 0xFFFF.
No packet is accepted by receiver side if
the CRC fails.
13.4.2 Packet Handling
BK-RF uses burst mode for payload
transmission and receive.
© 2015 Beken Corporation
When auto acknowledge is enabled
(EN_AA=1), the PTX device will
automatically wait for acknowledge
packet after transmission, and retransmit original packet with the delay of
ARD until an acknowledge packet is
received or the number of retransmission exceeds a threshold ARC.
If the later one happens, BK-RF will set
MAX_RT and give an active low
interrupt IRQ to MCU. Two packet loss
counters (ARC_CNT and PLOS_CNT)
are incremented each time a packet is
lost. The ARC_CNT counts the number
of retransmissions for the current
transaction. The PLOS_CNT counts the
total number of retransmissions since the
last channel change. ARC_CNT is reset
by initiating a new transaction.
PLOS_CNT is reset by writing to the
RF_CH register. It is possible to use the
information in the OBSERVE_TX
register to make an overall assessment of
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the channel quality.
The PTX device will retransmit if its RX
FIFO is full but received ACK frame has
payload.
As an alternative for PTX device to auto
retransmit it is possible to manually set
the BK-RF to retransmit a packet a
number of times. This is done by the
REUSE_TX_PL command.
When auto acknowledge is enabled, the
PRX device will automatically check the
NO_ACK field in received packet, and if
NO_ACK=0, it will automatically send
an acknowledge packet to PTX device.
If EN_ACK_PAY is set, and the
acknowledge packet can also include
pending payload in TX FIFO.
13.5 Data and Control
Interface
commands. A TX FIFO in PRX can
store payload for ACK packets to three
different PTX devices. If the TX FIFO
contains more than one payload to a pipe,
payloads are handled using the first in
first out principle. The TX FIFO in a
PRX is blocked if all pending payloads
are addressed to pipes where the link to
the PTX is lost. In this case, the MCU
can flush the TX FIFO by using the
FLUSH_TX command.
The RX FIFO in PRX may contain
payload from up to three different PTX
devices.
.
A TX FIFO in PTX can have up to three
payloads stored.
The TX FIFO can be written to by three
commands, W_TX_PAYLOAD and
W_TX_PAYLOAD_NO_ACK in PTX
mode and W_ACK_PAYLOAD in PRX
mode. All three commands give access
to the TX_PLD register.
13.5.1 TX/RX FIFO
The data FIFOs are used to store payload
that is to be transmitted (TX FIFO) or
payload that is received and ready to be
clocked out (RX FIFO). The FIFO is
accessible in both PTX mode and PRX
mode.
There are three levels 32 bytes FIFO for
both TX and RX, supporting both
acknowledge mode or no acknowledge
mode with up to six pipes.
TX three levels, 32 byte FIFO
RX three levels, 32 byte FIFO
Both FIFOs have a controller and are
accessible by using dedicated SPI
© 2015 Beken Corporation
The RX FIFO can be read by the
command R_RX_PAYLOAD in both
PTX and PRX mode. This command
gives access to the RX_PLD register.
The payload in TX FIFO in a PTX is
NOT removed if the MAX_RT IRQ is
asserted.
In the FIFO_STATUS register it is
possible to read if the TX and RX FIFO
are full or empty. The TX_REUSE bit is
also available in the FIFO_STATUS
register. TX_REUSE is set by the
command REUSE_TX_PL, and is reset
by the command: W_TX_PAYLOAD or
FLUSH TX.
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13.5.2 Interrupt
In BK2461-RF there is an active low
interrupt (IRQ), which is activated when
TX_DS IRQ, RX_DR IRQ or MAX_RT
IRQ are set high by the state machine in
the STATUS register. The IRQ resets
when MCU writes '1' to the IRQ source
bit in the STATUS register. The IRQ
mask in the CONFIG register is used to
select the IRQ sources that are allowed
to assert the IRQ. By setting one of the
MASK bits high, the corresponding IRQ
source is disabled. By default all IRQ
sources are enabled.
The 3 bit pipe information in the
STATUS register is updated during the
IRQ high to low transition. If the
STATUS register is read during an IRQ
high to low transition, the pipe
information is unreliable.
© 2015 Beken Corporation
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13.6
RF Command
The RF commands are shown in the table:
Command name
Command word (binary)
R_REGISTER
Write directly
W_ANALOG_REG
Operation
Read directly
W_REGISTER
# Data
bytes
Write through
register0X8B8-0X8BC
R_RX_PAYLOAD
8'b01000000
1 to 32
LSB byte
first
W_TX_PAYLOAD
8'b01100000
1 to 32
LSB byte
first
FLUSH_TX
8'b10100000
0
FLUSH_RX
8'b10000000
0
REUSE_TX_PL
8'b00010000
0
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Read RX-payload: 1 – 32
bytes. A read operation
always starts at byte 0.
Payload is deleted from FIFO
after it is read. Used in RX
mode.
Write TX-payload: 1 – 32
bytes. A write operation
always starts at byte 0 used in
TX payload. This command
used for ENABLE_ACK
payload
Flush TX FIFO, used in TX
mode
Flush RX FIFO, used in RX
mode
Should not be executed during
transmission of acknowledge,
that is, acknowledge package
will not be completed.
Used for a PTX device
Reuse last transmitted
payload. Packets are
repeatedly retransmitted as
long as CE is high.
TX payload reuse is active
until
W_TX_PAYLOAD or
FLUSH TX is executed. TX
payload reuse must not be
activated or deactivated
during package transmission
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Read RX-payload width for
the top R_RX_PAYLOAD in
the RX FIFO.
R_RX_PL_WID
Read register 0x8C4 directly
W_ACK_PAYLOAD
8'b01101ppp
1 to 32
LSB byte
first
W_TX_PAYLOAD_NO
ACK
8'b01101000
1 to 32
LSB byte
first
NOP
8'b00000000
0
Used in RX mode.
Write Payload to be
transmitted together with
ACK packet on PIPE PPP.
(PPP valid in the range from
000 to 101). Maximum three
ACK packet payloads can be
pending. Payloads with same
PPP are handled using first in
- first out principle. Write
payload: 1– 32 bytes. A write
operation always starts at byte
0.
Used in TX mode. Disables
AUTOACK on this specific
packet.
No Operation.
Table 46 RF command
© 2015 Beken Corporation
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13.7 Register Map
There are two register groups in BK2461 that is digital register and analog register.
13.7.1 Digital Register
Address
(Hex)
0x0880
Mnemonic
Bit
Reset
Value
Type
7
0
R/W
MASK_RX_DR
6
0
R/W
MASK_TX_DS
5
0
R/W
MASK_MAX_RT
4
0
R/W
EN_CRC
3
1
R/W
CRCO
2
0
R/W
PWR_UP
PRIM_RX
0x0881
CONFIG
Reserved
1
0
0
0
R/W
R/W
EN_AA
Reserved
7:6
00
R/W
ENAA_P5
5
1
R/W
ENAA_P4
4
1
R/W
ENAA_P3
3
1
R/W
ENAA_P2
2
1
R/W
ENAA_P1
1
1
R/W
ENAA_P0
0
1
R/W
© 2015 Beken Corporation
Description
Configuration Register
Only '0' allowed
Mask interrupt caused by RX_DR
1: Interrupt not reflected on the IRQ
pin
0: Reflect RX_DR as active low
interrupt on the IRQ pin
Mask interrupt caused by TX_DS
1: Interrupt not reflected on the IRQ
pin
0: Reflect TX_DS as active low
interrupt on the IRQ pin
Mask interrupt caused by MAX_RT
1: Interrupt not reflected on the IRQ
pin
0: Reflect MAX_RT as active low
interrupt on the IRQ pin
Enable CRC. Forced high if one of
the bits in the EN_AA is high
CRC encoding scheme
'0' - 1 byte
'1' - 2 bytes
1: POWER UP, 0:POWER DOWN
RX/TX control,
1: PRX, 0: PTX
Enable ‘Auto Acknowledgment’
Function (only used by RX part)
Need match with TX part
Only '00' allowed
Enable auto acknowledgement data
pipe 5
Enable auto acknowledgement data
pipe 4
Enable auto acknowledgement data
pipe 3
Enable auto acknowledgement data
pipe 2
Enable auto acknowledgement data
pipe 1
Enable auto acknowledgement data
pipe 0
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0x0882
0x0883
EN_RXADDR
Reserved
ERX_P5
ERX_P4
ERX_P3
ERX_P2
ERX_P1
ERX_P0
7:6
5
4
3
2
1
0
00
0
0
0
0
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SETUP_AW
Reserved
000000
R/W
AW
0x0884
7:2
1:0
11
R/W
SETUP_RETR
ARD
R/W
3:0
0011
R/W
RF_CH
Reserved
RF_CH
7
6:0
0
0000010
R/W
R/W
7
6
5
4
0
0
0
0
R/W
R/W
R/W
RF_DR
3
1
R/W
RF_PWR[1:0]
0 x0886
0000
ARC
0x0885
7:4
2:1
11
R/W
RF_SETUP
Reserved
En_250k_rate
© 2015 Beken Corporation
Enabled RX Addresses
Only '00' allowed
Enable data pipe 5.
Enable data pipe 4.
Enable data pipe 3.
Enable data pipe 2.
Enable data pipe 1.
Enable data pipe 0.
Setup of Address Widths
(common for all data pipes)
Only '000000' allowed
RX/TX Address field width
'00' - Illegal
'01' - 3 bytes
'10' - 4 bytes
'11' - 5 bytes
LSB bytes are used if address width
is below 5 bytes
Setup of Automatic Retransmission
Auto Retransmission Delay
‘0000’ – Wait 250 us
‘0001’ – Wait 500 us
‘0010’ – Wait 750 us
……..
‘1111’ – Wait 4000 us
(Delay defined from end of
transmission to start of next
transmission)
Auto Retransmission Count
‘0000’ –Re-Transmit disabled
‘0001’ – Up to 1 Re-Transmission
on fail
of AA
……
‘1111’ – Up to 15 Re-Transmission
on fail of AA
RF Channel
Only '0' allowed
Sets the frequency channel
RF Setup Register
Reserved
Reserved
Set RF datarate to 250k
Reserved,pls don’t change it
Air Data Rate ,decide by 0x886 bit
{[5],[3]}
‘00’ – 1Mbps
‘01’ – 2Mbps
‘10’ – 250kbps
‘11’ – reserved
Set RF output power in TX mode
RF_PWR[1:0]
'00' – -10 dBm
'01' – -5 dBm
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LNA_HCURR
1
R/W
39:0
0xE7E7E
7E7E7
R/W
RX_ADDR_P1
39:0
0xC2C2C
2C2C2
R/W
RX_ADDR_P2
7:0
0xC3
R/W
RX_ADDR_P3
7:0
0xC4
R/W
RX_ADDR_P4
7:0
0xC5
R/W
0 x0894
RX_ADDR_P5
7:0
0xC6
R/W
0 x0895
0 x0896
0 x0897
0 x0898
0 x0899
TX_ADDR
39:0
0xE7E7E
7E7E7
R/W
RX_PW_P0
Reserved
7:6
00
R/W
RX_PW_P0
5:0
000000
R/W
RX_PW_P1
Reserved
7:6
00
R/W
RX_PW_P1
5:0
000000
R/W
7:6
00
R/W
5:0
000000
0 x0887
0 x0888
0 x0889
0 x088A
0 x088B
0 x088C
0 x088D
0 x088E
0 x088F
0 x0890
0 x0891
0 x0892
0 x0893
0 x089A
0 x089B
0 x089C
0
RX_ADDR_P0
RX_PW_P2
Reserved
RX_PW_P2
© 2015 Beken Corporation
R/W
'10' – 0 dBm
'11' – 5 dBm
Setup LNA gain
0:Low gain(20dB down)
1:High gain
Receive address data pipe 0. 5
Bytes maximum length. Write the
number of bytes defined by
SETUP_AW)
{X88B,X88A,X889,X888,X887}
Receive address data pipe 1. 5
Bytes maximum length. Write the
number of bytes defined by
SETUP_AW)
Receive address data pipe 2. Only
LSB. MSB bytes is equal to
RX_ADDR_P1[39:8]
Receive address data pipe 3. Only
LSB. MSB bytes is equal to
RX_ADDR_P1[39:8]
Receive address data pipe 4. Only
LSB. MSB bytes is equal to
RX_ADDR_P1[39:8]
Receive address data pipe 5. Only
LSB. MSB bytes is equal to
RX_ADDR_P1[39:8]
Transmit address. Used for a PTX
device only.
(LSB byte is written first)
Set RX_ADDR_P0 equal to this
address to handle automatic
acknowledge if this is a PTX device
Only '00' allowed
Number of bytes in RX payload in
data pipe 0 (1 to 32 bytes).
0: not used
1 = 1 byte
…
32 = 32 bytes
Only '00' allowed
Number of bytes in RX payload in
data pipe 1 (1 to 32 bytes).
0: not used
1 = 1 byte
…
32 = 32 bytes
Only '00' allowed
Number of bytes in RX payload in
data pipe 2 (1 to 32 bytes).
0: not used
1 = 1 byte
…
32 = 32 bytes
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0 x089D
RX_PW_P3
Reserved
7:6
00
5:0
000000
R/W
RX_PW_P3
0 x089E
R/W
7:6
00
R/W
RX_PW_P4
0 x089F
RX_PW_P4
Reserved
5:0
000000
R/W
RX_PW_P5
Reserved
7:6
00
R/W
RX_PW_P5
000000
5:0
0 x08A0
R/W
7:6
0
R/W
DPL_P5
5
0
R/W
DPL_P4
4
0
R/W
DPL_P3
3
0
R/W
DPL_P2
2
0
R/W
DPL_P1
1
0
R/W
DPL_P0
0
0
R/W
FEATURE
Reserved
EN_DPL
EN_ACK_PAY
7:3
2
1
0
0
0
R/W
R/W
R/W
R/W
EN_DYN_ACK
0 x08A1
DYNPD
Reserved
0
0
R/W
© 2015 Beken Corporation
Only '00' allowed
Number of bytes in RX payload in
data pipe 3 (1 to 32 bytes).
0: not used
1 = 1 byte
…
32 = 32 bytes
Only '00' allowed
Number of bytes in RX payload in
data pipe 4 (1 to 32 bytes).
0: not used
1 = 1 byte
…
32 = 32 bytes
Only '00' allowed
Number of bytes in RX payload in
data pipe 5 (1 to 32 bytes).
0: not used
1 = 1 byte
…
32 = 32 bytes
Enable dynamic payload length
Only ‘00’ allowed
Enable dynamic payload length data
pipe 5.
(Requires EN_DPL and
ENAA_P5)
Enable dynamic payload length data
pipe 4.
(Requires EN_DPL and
ENAA_P4)
Enable dynamic payload length data
pipe 3.
(Requires EN_DPL and
ENAA_P3)
Enable dynamic payload length data
pipe 2.
(Requires EN_DPL and
ENAA_P2)
Enable dynamic payload length data
pipe 1.
(Requires EN_DPL and
ENAA_P1)
Enable dynamic payload length data
pipe 0.
(Requires EN_DPL and ENAA_P0)
Feature Register
Only ‘00000’ allowed
Enables Dynamic Payload Length
Enables Payload with ACK
Enables the
W_TX_PAYLOAD_NOACK
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command
0 x08A5
0 x08A4
0 x08A3
0 x08A2
0 x08A9
0 x08A8
0 x08A7
0 x08A6
0 x08B4
0 x08B3
0 x08B2
0 x08B1
0 x08B0
0 x08AF
0 x08AE
0 x08AD
0 x08AC
0 x08AB
0 x08AA
0 x08B5
(cfg0c0--3)
NEW_FEATURE
(cfg0d0--3)
31:0
31:0
0
0
RAMP
(2402table_0
--2401table_A)
87:0
NA
Please initialize with 0x00731200
Please initialize with 0x0080B436
W
Ramp curve
Please write with
0xFFFFFEF7CF208104082041
BK-RF_ce
7:1
0
0 x08B6
BK-RF_cmd
0 x08B7
BK-RF_FIFO
0 x08B8
0 x08B9
0 x08BA
0 x08BB
BK-RF_sdata_0
BK-RF_sdata_1
BK-RF_sdata_2
BK-RF_sdata_3
0 x08BC
BK-RF_sctrl
0 x08C0
BK-RF_status
R/W
RX_DR
6
0
R/W
TX_DS
5
0
R/W
MAX_RT
4
0
R/W
© 2015 Beken Corporation
reserved
ce
8'b10000000 : Flush RX
8'b10100000 : Flush TX
8'b00010000 : Reusle TX PL
8'b01000000 : Read RX Payload
8'b01100000 : Write TX Payload
8'b01101ppp :
W_ACK_PAYLOAD
8'b01101000 :
W_TX_PAYLAOD_NOACK
8'b00000000 : NOP
TX MODE: TX data payload
register 1 - 32 bytes.
RX MODE: RX data payload
register 1 - 32 bytes.
Analog register0[7:0]
Analog register1[15:8]
Analog register2[23:16]
Analog register3[31:24]
Write address of Analog rgister
(only can be writen)
Status, read only
Data Ready RX FIFO interrupt
Asserted when new data arrives RX
FIFO
Write 1 to clear bit.
Data Sent TX FIFO interrupt
Asserted when packet transmitted
on TX. If AUTO_ACK is activated,
this bit is set high only when ACK
is received.
Write 1 to clear bit.
Maximum number of TX
retransmits interrupt
Write 1 to clear bit. If MAX_RT is
asserted it must be cleared to enable
further communication.
Proprietary and Confidential
Page 81 of 95
RX_P_NO
TX_FULL
0 x08C1
3:1
0
111
R
0
R
BK-RF_observetx
Status, read only
PLOS_CNT
7:4
0000
R
ARC_CNT
0 x08C2
3:0
0000
R
7:1
0
000000
0
R
R
BK-RF_cdstatus
Reserved
CD
0 x08C3
BK-RF_fifostatus
Reserved
7
0
TX_REUSE
6
R/W
0
R
TX_FULL
5
0
R
TX_EMPTY
4
1
R
Reserved
3:2
00
R/W
RX_FULL
1
0
R
RX_EMPTY
0 x08 C4
Data pipe number for the payload
available for reading from
RX_FIFO
000-101: Data Pipe Number
110: Not used
111: RX FIFO Empty
TX FIFO full flag.
1: TX FIFO full
0: Available locations in TX FIFO
0
1
R
BK-RF_rpl_width
Count lost packets. The counter is
overflow protected to 15, and
discontinues at max until reset. The
counter is reset by writing to
RF_CH.
Count retransmitted packets. The
counter is reset when transmission
of a new packet starts.
Status, read only
Carrier Detect
Status, read only
Only '0' allowed
Reuse last transmitted data packet if
set high.
The packet is repeatedly
retransmitted as long as CE is high.
TX_REUSE is set by the SPI
command REUSE_TX_PL, and is
reset by the SPI command
W_TX_PAYLOAD or FLUSH TX
TX FIFO full flag
1: TX FIFO full; 0: Available
locations in TX FIFO
TX FIFO empty flag.
1: TX FIFO empty
0: Data in TX FIFO
Only '00' allowed
RX FIFO full flag
1: RX FIFO full
0: Available locations in RX FIFO
RX FIFO empty flag
1: RX FIFO empty
0: Data in RX FIFO
Status, read only
The width of the payload
0X8C5
0X8C6~0X8C7
BK-RF_mbist_st
reseved
Done
Pass
Fail
Chip_id
Status, read only
R
5'b0
2
R
test_done
1
R
test_pass
0
R
test_fail
R
R
© 2015 Beken Corporation
Chip_id [7:0]
Proprietary and Confidential
Page 82 of 95
R
Chip_id [15:8]
0X8C8~0X8CB
BK-RF_bit_cnt
R
0X8CC~0X8CF
BK-RF_err_cnt
R
0X8D0~0X8D3
Tx_freq_offset
Rx_freq_offset
RW
Status, read only
Total number of bits received
register
Status, read only
Error counter register
RF MOD/DEMOD config
RW
RW
RW
RF MOD/DEMOD config
RF MOD/DEMOD config
RF MOD/DEMOD config
0X8D4~0X8D7
0X8D8[7:4]
0X8D8[3:0]
Mod_sdm_dly
Mod_dac_dly
0xd9[7]
clksel_cfg
R/W
0xd9[6]
sdm3bit_cfg
R/W
0xd9[5]
0xd9[4]
pn25ena_cfg
open_loop_en
R/W
R/W
0xd9[3]
rx_if_select
R/W
0xd9[2]
tbfalcon_reset
R/W
0xd9[1]
0xd9[0]
0xda[0]
0xdb[7:0]
bp_kmod
vco_cal_en
R/W
R/W
fm_gain
R/W
0xda[1]
rx_if_select
R/W
0xda[2]
rf_test_en
R/W
0xdc[0]
0xdd[7:0]
fm_kmod_set
R/W
mod_coefficient
R/W
pwdRSSI
PAD_DR
R/W
R/W
R/W
R/W
R/W
0xe0[0]
boost_mode
R/W
0xe1[7]
0xe1[6:5]]
0xe1[4:0]]
0xe2[7:3]
0xe2[2:0]
0xe3[7]
lnag
R/W
R/W
R/W
R/W
R/W
R/W
0xde[7:0]
0xdf[7:0]
0xe0[7]
0xe0[6:4]
0xe0[3]
0xe0[2]
0xe0[1]
dsplpctrl
p11_pusel
p10_pusel
HQ
gPA
lbd_thre
lbd_hys
pwdlbd
© 2015 Beken Corporation
pll sdm output latch edge
1: posedge 0:negedge
sdm 2nd/3nd selection
1:3nd 0:2nd
PN25 enable
1: FracN = 0
lo direction select
0:+500k 1: -500k
sdm reset
1: reset
bypass kmod calibration
vco calibriation enable
vco after calibriation value is
set in this register
tx mod direction select
0:+500k 1: -500k
rf test enable
if it is 1,
then gpio3 and gpio4 output
testsignal
if bp_kmod is 1
auto channel compensation
is stopped, this register value
is the default value
tx N value compensation
powerdown RSSI
analog control
analog control
analog control
analog control
boost mode select
0: auto boost
1: digital control
analog control
analog control
analog control
analog control
analog control
analog control
Proprietary and Confidential
Page 83 of 95
0xe3[6]
0xe3[5]
0xe3[0]
0xf9[7:3]
0xf9[2]
0xf9[1]
0xf9[0]
0xfa[7:0]
0xfb[7:0]
0xfc[7:0]
0xfd[7:0]
0xfe[7:0]
0xff[7:0]
R/W
R/W
R/W
R
R
R
R
lbd_intset
TXCWEN
samp_pad_c
fltcal
pll48_fast
pll48_slow
vco_amp_ind
chip_id
R
device_id
analog control
analog control
analog control
analog indicator
analog indicator
analog indicator
analog indicator
R
chip id/2461
device id
Note: Don’t write reserved registers and registers at other addresses in register
bank 0
Table 47 Digital Register
Note:
1. ARD-auto retransmission delay. If the ACK payload is more than 15 byte in 2Mbps
mode the ARD must be 500μS or more, if the ACK payload is more than 5byte in
1Mbps mode the ARD must be 500μS or more. In 250kbps mode (even when the
payload is not in ACK) the ARD must be 500μS or more.
2. The RX_DR IRQ is asserted by a new packet arrival event. The procedure for
handling this interrupt should be: 1) read payload from FIFO, 2) clear RX_DR IRQ, 3)
read FIFO_STATUS to check if thereare more payloads available in RX FIFO, 4) if
there are more data in RX FIFO, repeat from step 1).
3. Register 0x881 EN_AA only used for RX part now. For TX part, the command
W_TX_PAYLOAD used for auto-ack payload, the command
W_TX_PAYLOAD_NOACK used for disable-ack payload.
13.7.2 Analog Register
The analog registers can be written through writing 0X8B8 to 0X8BC.
Analog register data [31:0] = {0X8BB, 0X8Ba, 0X8B9, 0X8B8}
Analog register address [7:0] = {0X8BC}
Writing corresponding data and address into these serial registers can update the analog
register value.
Address
(Hex)
Mnemonic
Bit
Reset
Value
Type
00
01
02
03
04
31:0
31:0
31:0
31:0
31:0
25
05
31:0
Description
W
W
W
W
W
W
W
© 2015 Beken Corporation
Proprietary and Confidential
Page 84 of 95
29:26
11
31:0
31:0
06
07
08
09
0A
0B
W
W
W
W
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Note: Don’t write reserved registers and no definition registers in register bank 1
Table 48 Register Bank 1
Please contact BEKEN FAE for the default setting used by the analog register.
13.7.3 TX power control setting
The transmit power can be set from -51dBm to 5dBm, to do this, please refer to the next
table.
PALDO & lt; 1:0 & gt;
PCsel
HQ & lt; 1:0 & gt;
gPA & lt; 4:0 & gt;
TX
RF
Ana.Reg3 & lt; 23:22 & gt; Ana.Reg4 & lt; 16 & gt; Dig.61h & lt; 6:5 & gt; dig.61h & lt; 4:0 & gt; Power
Current
Hex
(dBm)
(mA)
Table 49 TX power setting
14 Electrical Specifications
RF part
Name
VDD
Parameter (Condition)
Operating Condition
Voltage
© 2015 Beken Corporation
Min
2.2
Typical
Max
3.6
Proprietary and Confidential
Unit
Comment
V
Page 85 of 95
PSR
TEMP
VIH
VIL
VOH
VOL
IVDD
IVDD
IVDD
FOP
FXTAL
RFSK
PRF
PBW
PBW
PBW
PRF1
PRF2
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
Max
Input
RXSENS
RXSENS
RXSENS
C/ICO
C/I1ST
Temperature
Digital input Pin
High level
Low level
Digital output Pin
High level (IOH=-0.25mA)
Low level(IOL=0.25mA)
Normal condition
Dsleep current
Idle 16M current
Idle 32K current
Normal RF condition
Operating frequency
Crystal frequency
Air data rate
Transmitter
Output power
Modulation 20 dB
bandwidth(2Mbps)
Modulation 20 dB bandwidth
(1Mbps)
Modulation 20 dB bandwidth
(250Kbps)
Out of band emission 2 MHz
Out of band emission 4 MHz
Current at -36 dBm output
power
Current at -30 dBm output
power
Current at -22 dBm output
power
Current at -18 dBm output
power
Current at -12 dBm output
power
Current at -9 dBm output power
Current at -6 dBm output power
Current at -3dBm output power
Current at 0 dBm output power
Current at 3 dBm output power
Current at 12 dBm output
power
Receiver
Current (2Mbps)
Current (1Mbps)
Current (250Kbps)
1 E-3 BER
1 E-3 BER sensitivity (2Mbps)
1 E-3 BER sensitivity (1Mbps)
1 E-3 BER sensitivity
(250Kbps)
Co-channel C/I (2Mbps)
ACS C/I 2MHz (2Mbps)
© 2015 Beken Corporation
-20
85
ºC
VDD-0.3
VDD
0.3VDD
V
V
VDD
0.3
V
V
VSS
VDD- 0.3
0
3
1.3
6.5
2400
0.25
uA
mA
uA
2527
16
1
2
Total current
Total current
Total current
MHz
MHz
Mbps
12
2.5
dBm
MHz
2
MHz
1.6
MHz
dBm
dBm
mA
1MHz,RBW=100K
TXPOWER=5dBm
Maxhold
Include MCU part
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
25
24
23.5
10
-87
-90
-95
mA
mA
mA
dBm
dBm
dBm
dBm
dB
dB
Proprietary and Confidential
Page 86 of 95
C/I2ND
C/I3RD
C/ICO
C/I1ST
C/I2ND
C/I3RD
ACS C/I 4MHz (2Mbps)
ACS C/I 6MHz (2Mbps)
Co-channel C/I (1Mbps)
ACS C/I 1MHz (1Mbps)
ACS C/I 2MHz (1Mbps)
ACS C/I 3MHz (1Mbps)
dB
dB
dB
dB
dB
dB
6
6
-17
-32
MCU part
Name
Parameter (Condition)
Min
Typical
（3V）
Max
Unit
Comment
Core functions
Sleep mode
Deep sleep mode
Idle mode at 16M
Idle mode at 8M
Idle mode at 4M
Idle mode at XOSC32k(16M
running)
Active mode (16M)
Active mode (8M)
Active mode (4M)
Active mode (2M)
Active mode (32k)
Active mode (RC32k)
6
2.6 @3V
1.6@2.1V
0.8
0.44
0.26
95
uA
mA
mA
mA
uA
2.9
1.5
0.84
0.49
0.16
61
mA
3.87MA
ADC (8k byte rates)
RC32K
uA
uA
mA
mA
mA
mA
uA
ADC SINAD (fin=1khz, fs=8khz)
DB
LBD (always on)
uA
GPIO
Drive ability
© 2015 Beken Corporation
4
Proprietary and Confidential
8
mA
Page 87 of 95
15 Typical Application Schematic
Please refer to the separate documents for detail.
© 2015 Beken Corporation
Proprietary and Confidential
Page 88 of 95
16 Package Information
24pin 4X4
16pin SOP
© 2015 Beken Corporation
Proprietary and Confidential
Page 89 of 95
参数
A
A1
A2
A3
b
b1
c
c1
D
E
E1
e
L
L1
最小
1.35
0.10
1.25
0.55
0.36
0.35
0.17
0.17
9.80
5.80
3.80
0.45
典型
1.60
0.15
1.45
0.65
0.40
0.20
9.90
6.00
3.90
1.27 BSC
0.60
1.04 REF
© 2015 Beken Corporation
最大
1.75
0.25
1.65
0.75
0.51
0.45
0.25
0.23
10.00
6.20
4.00
0.80
单位
mm
mm
mm
mm
mm
mm
mm
mm
mm
mm
mm
mm
mm
mm
Proprietary and Confidential
Page 90 of 95
L2
R
R1
h
θ
θ1
θ2
θ3
θ4
0.07
0.07
0.30
0
6
6
5
5
0.25 BSC
0.40
8
8
7
7
0.50
8
10
10
9
9
mm
mm
mm
mm
°
°
°
°
°
QFN32-4X4
© 2015 Beken Corporation
Proprietary and Confidential
Page 91 of 95
© 2015 Beken Corporation
Proprietary and Confidential
Page 92 of 95
17 Solder Reflow Profile
Figure 31 Classification Reflow Profile
Table 50 Solder Reflow Profile
Profile Feature
Average Ramp-Up Rate (tsmax to tp)
Temperature Min (Tsmin)
Pre_heat
Temperature Max (Tsmax)
Time (ts)
Time Maintained
Temperature (TL)
above
Time (tL)
Peak/Classification Temperature (Tp)
Time within 5°C of Actual Peak Temperature (tp)
Ramp-Down Rate 6
Time 25°C to Peak Temperature 8
© 2015 Beken Corporation
Specification
3°C/second max.
150°C
200°C
60-180 seconds
217°C
60-150 seconds
260°C
20-40 seconds
6°C/second max.
8 minutes max.
Proprietary and Confidential
Page 93 of 95
18 Order Information
19 Solder Reflow Profile
© 2015 Beken Corporation
Proprietary and Confidential
Page 94 of 95
20 Contact Information
Beken Corporation Technical Support Center
Shanghai office
Building 41, 1387 Zhangdong Road, Zhangjiang High-Tech Park, Pudong New District,
Shanghai, China
Phone:
86-21-51086811
Fax:
86-21-60871089
Postal Code: 201203
Email:
info@bekencorp.com
Website:
www.bekencorp.com
© 2015 Beken Corporation
Proprietary and Confidential
Page 95 of 95
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