uboot_tools.zip

Jak przywrócić oprogramowanie w rejestratorze BCS-CVR0401E-IV po nieudanej aktualizacji z FTP?

No i najważniejsze - skąd wiedzieć który plik pod jaki adres ma zostać wgrany? Tabela informacji o konfiguracji partycji, z bazy wiedzy „Planowanie partycji Flash” Edytując plik .bin "BIOS_V3.218.0000001.2.R.170808.bin" w edytorze HxD zmieniasz początkowe HEX 44 48 na 50 4B i zapisujesz plik. Otwierasz go w programie 7zip i masz wgląd do plików: https://obrazki.elektroda.pl/2666739400_1605485590_thumb.jpg Edytując plik Install.lua w edytorze tekstu np: Notepad ++ masz wgląd to informacji które mogą ci pomóc. Zmodyfikowany plik .bin możesz spróbować wgrać tym ruskim programem może ruszy po modyfikacji. Dodano po 5 : Nie wiem tak do końca czy dysponuję dobrym firmware HCVR5104C-S3 No chyba nie to co trzeba. https://obrazki.elektroda.pl/8905800500_1605486230_thumb.jpg To są potrzebne pliki. W załączniku masz plik u boot pobierz go oraz program do wgrywania nie wiem jaki masz chipset bo masz na nim radiator ale może program zadziała. PRZYKŁAD... https://obrazki.elektroda.pl/4686980700_1605487425_thumb.jpg Po wgraniu uruchom rejestrator i hisilicon # print I sprawdź czy przez ruski program wgra ci BIOS_V3.218.0000001.2.R.170808.bin

Download file - link to post

• uboot_tools.zip
  • FastBoot3.1_BVT.exe
  • uboot-Hi3520D-bvt_No1_660_330_660_ddr_innerFEPHY.xls
  • uboot-Hi3515A-bvt_No1_600_300_600_ddr_outPHY.xls
  • mkboot.sh
  • reg_info_Hi3515A-bvt_No1_600_300_600_ddr_innerFEPHY.bin
  • mkboot-hi3520d.sh
  • reg_info_Hi3520A_930_310_620_ddr.bin
  • uboot-Hi3515A-bvt_No1_600_300_600_ddr_innerFEPHY.xls
  • uboot-Hi3520A-bvt_No1_930_310_620_ddr_NO1.xls
  • reg_info_Hi3515A-bvt_No1_600_300_600_ddr_outPHY.bin
  • uboot-Hi3520D-bvt_No1_660_330_660_ddr_outPHY.xls
  • reg_info_Hi3520D-bvt_No1_660_330_660_ddr_innerFEPHY.bin
  • UserConfig.ini
  • reg_info_930_310_620_ddr0_slow.bin
  • reg_info_Hi3520D-bvt_No1_660_330_660_ddr_outPHY.bin
  • uboot-Hi3521-bvt_No1_930_310_620_ddr0_slow.xls

uboot_tools.zip > uboot-Hi3515A-bvt_No1_600_300_600_ddr_outPHY.xls

,,,,
, " Boot V1.0 " ,,
, " Hisilicon Technologies Co., Ltd. All rights reserved. @2012 " ,,
,,,,,,,,
" Basic Project Information " ,,,,
,,,,
" Project Name " , " xxx " ,, " Project Version " , " 1.0 "
" Project Start Time " , " 40543 " ,, " Development " , " xxx "
" Product Line " , " Media " ,, " Department " , " Media "
" Project Description " , " Project description " ,,,
 " Module Name " , " slow "
" Base Address " , " 0x20050000 "
" Priority " , " 1 "
" Execution Required for Standby Wakeup " , " N "
" Execution Required for Normal Boot " , " Y "
" Register " , " Offset Address " , " Value Written to or Read from Register " , " delay " , " Read or Write " , " Bits to Be Read or Written " , " Start Bit to Be Read or Written " , " Register Attribute "
" SC_CTRL " , " 0 " , " 0x2 " , " 0 " , " write " , " 2 " , " 0 " , " "
" SC_CTRL " , " 0 " , " 0x2 " , " 0 " , " read " , " 3 " , " 3 " , " "
,,,,,,,
,,,,,,,
,,,,,,,
 " Module Name " , " pll "
" Base Address " , " 0x20030000 "
" Priority " , " 2 "
" Execution Required for Standby Wakeup " , " N "
" Execution Required for Normal Boot " , " Y " ,,,,,,
" Register " , " Offset Address " , " Value Written to or Read from Register " , " delay " , " Read or Write " , " Bits to Be Read or Written " , " Start Bit to Be Read or Written " , " Register Attribute "
" PERI_CRG0 " , " 0x0 " , " 0x11000000 " , " 0 " , " write " , " 31 " , " 0 " , " "
" PERI_CRG1 " , " 0x4 " , " " , " 0 " , " write " , " 31 " , " 0 " , " "
" PERI_CRG2 " , " 0x8 " , " 0x22000000 " , " 0 " , " write " , " 31 " , " 0 " , " "
" PERI_CRG3 " , " 0xc " , " 0x007c2063 " , " 0 " , " write " , " 31 " , " 0 " , " "
" PERI_CRG10 " , " 0x28 " , " 0x0 " , " 0 " , " write " , " 1 " , " 2 " , " "
" PERI_CRG58 " , " 0xe8 " , " 0x7 " , " 0 " , " read " , " 2 " , " 0 " , " "
" " , " " , " " , " " , " write " , " " , " " , " " , " "
" " , " " , " " , " " , " none " , " " , " " , " "
" " , " " , " " , " " , " write " , " " , " " , " "
,,,,,,,
,,,,,,,
 " Module Name " , " normal "
" Base Address " , " 0x20050000 "
" Priority " , " 3 "
" Execution Required for Standby Wakeup " , " N "
" Execution Required for Normal Boot " , " Y "
" Register " , " Offset Address " , " Value Written to or Read from Register " , " delay " , " Read or Write " , " Bits to Be Read or Written " , " Start Bit to Be Read or Written " , " Register Attribute "
" SC_PLLCTRL " , " 0x14 " , " 0x0fff8000 " , " 0 " , " write " , " 31 " , " 0 " , " "
" SC_CTRL " , " 0 " , " 0x4 " , " 0 " , " write " , " 2 " , " 0 " , " "
" SC_CTRL " , " 0 " , " 0x4 " , " 0 " , " read " , " 3 " , " 3 " , " "
" SC_CTRL_SWDQS_TRAINING " , " 0xa0 " , "  & lt;
=B
70x0 7
DDRC_PHY_270xa0470x1f7031
DDRC_PHY_370xac070x557
DDRC_PHY_570x80470x4b7PERIPHCTRL2870xa47?07PERIPHCTRL2970xa873172
$NB\?gM`n?ÿ
[6:4]SFC :4ma 010;
[2:0]PAD_SPI_SDO:4ma 010
72ÛVB\?gM`n?ÿ
[6:4]SFC :8ma 110;
[2:0]PAD_SPI_SDO:8ma 1107Ü
$NB\?gM`n?ÿ
[30:28]spi_sclk:8ma 110;
[26:24]aio_ws_tx:4ma 010;
[22:20]aio_bclk_tx:11ma 111;
[18:16]aio_ws_rx:4ma 010;
[14:12]aio_bclk_rx:11ma 111;
[10:8]aio_mclk:11ma 111;
[6:4]vga_hs/vga_vs:8ma 010;
[2:0]vi_adc_clk:11ma 111
7
0x627277277
0x000000227ÞÛVB\?gM`n?ÿ
[30:28]spi_sclk:11ma 111;
[26:24]aio_ws_tx:4ma 010;
[22:20]aio_bclk_tx:11ma 111;
[18:16]aio_ws_rx:4ma 010;
[14:12]aio_bclk_rx:11ma 111;
[10:8]aio_mclk:11ma 111;
[6:4]vga_hs/vga_vs:12ma 100;
[2:0]vi_adc_clk:11ma 1117
DDRC_PHY_170x8307?07
DDRC_PHY_470x81870x4070x87?07317
DDRC_PHY_REG870x8e070x237?07317DDRC_PHY_REG1170x92070x227
DDRC_PHY_REG670x8d470xc7
DDRC_PHY_REG970x91470xd7
0x00000015·
0x181D0000·0x0000000FD7
0x0000100D7
0x0015000070x0000000FD7
0x000000157
0x181D00007
0x0000000570x070x0000000FD7
0x0000000D7
0x0000200D70x0000000FD7
0x000500007
0x0000005570x07
0x100500007
0x180500007
0x000D00007
0x0000000D70x917
PERI_CRG51 70xcc7
0x0000000f7?073170x0000000FD7
...QèŸCRG
7NULL71000070x07
0x0000000a7
muxctrl_reg380x9870x17
0x000000157RMII7
muxctrl_reg390x9c7
muxctrl_reg400xa07
muxctrl_reg410xa47
muxctrl_reg420xa87
muxctrl_reg430xac7
muxctrl_reg440xb07
muxctrl_reg450xb47
muxctrl_reg4970xc47MDIO7
muxctrl_reg5070xc87PERIPHCTRL2470x947?87
0x007c30967
0x6355100B7
0xFF637A317
0x3350E0007
0xFFDFF6f370x937`À Î0kÏPkÏpkÏ kÏÀkÏðkÏ lÏPlϟlÏÐlÏmÏ0mÏpmϟmÏÀmÏnÏ@nÏpnϟnÏðnÏ0oÏ`oϟoÏÀoÏðoÏ pÏPpÏ?pÏ pÏÀpÏðpÏ qÏPqÏ?qÏ qÏÀqÏðqÏ rÏPrÏ?rÏ°rÏàrÏsÏ0sÏ`sÏ?sÏ°sÏÐsÏðsÏtÏ0tÏPtÏptϟtÏÀtÏàtÏuÏ0uÏPuÏ?uÏ uÏÀuÏàuÏvÏ0vÏPvÏpvÏ vÏÐvÏwÏ0wÏPwÏ?wÏ°wÏàwÏxÏ@xÏpxϟxÏ°xÏÐxÏyÏ@yÏpyÏ yÏÐyÏzÏ0zÏ`zϟzÏÀzÏ{Ï@{Ï?{ÏÀ{Ï|Ï@|Ï?|ÏÀ|Ï}Ï@}Ï`}Ï?}Ï }ÏÀ}Ïà}Ï~Ï ~Ï@~Ï`~Ï?~Ï ~ÏÀ~Ïà~Ï?Ï ?Ï@?Ïp?ϟ?ÏÀ?Ïð?Ï ?Ï@?Ï`?Ï??Ï ?ÏÀ?Ïð?Ï ŸÏPŸÏ?ŸÏ°ŸÏàŸÏ'Ï@'Ïp'Ï 'ÏÐ'Ïð'Ï?Ï0?ÏP?Ï??Ï°?Ïð?Ï0''Ï`''ϟ''ÏÐ''Ï...Ï@...Ï?...ÏÀ...Ïð...Ï ?Ï@?Ïp?ϟ?ÏÀ?Ïð?Ï ?ÏP?Ïp?Ï ?ÏÐ?Ï?Ï0?Ï`?ϟ?ÏÀ?Ïð?Ï o/ooÏPo/ooÏ?o/ooÏ o/ooÏÀo/ooÏào/ooÏ?Ï0?ÏP?Ïp?Ï ?ÏÀ?Ïð?Ï " " Ï@ " " Ïp " " Ï  " " ÏÐ " " Ï?Ï ?Ï@?Ï`?Ï??Ï ?ÏÐ?Ïð?ÏŸÏ0ŸÏPŸÏpŸÏŸŸÏ°ŸÏПÏðŸÏ ?Ï@?Ï`?ϟ?Ï°?ÏÐ?ÏŸÏ ŸÏ@ŸÏpŸÏŸŸÏÀŸÏàŸÏŸÏ0ŸÏPŸÏ?ŸÏ ŸÏПÏðŸÏ `Ï@`Ï``ϟ`Ï°`Ïà`Ï'Ï0'ÏP'Ï?'Ï 'ÏÀ'Ïà'Ï``Ï0``Ï```Ï?``Ï°``ÏÐ``Ïð``Ï ''Ï@''Ï`''ϟ''Ï°''ÏÐ''Ïð''Ï*Ï0*Ï`*ϟ*Ï°*Ïà*Ï-Ï@-Ïp-Ï -Ïà-Ï - ÏP - Ï? - ÏÀ - Ïà - Ï?ÏP?ϟ?ÏÀ?Ïà?ÏtmÏ tmÏPtmÏptmϟtmÏ°tmÏàtmÏ?Ï0?ÏP?Ïp?Ï ?ÏÀ?Ïà?Ï " " ÏP " " Ïp " " Ï  " " ÏÐ " " Ïð " " Ï ?Ï@?Ï??Ï°?ÏÐ?ϟÏ0ŸÏPŸÏ?ŸÏ ŸÏàŸÏ?Ï0?Ï`?ϟ?Ï°?ÏÐ?Ï?Ï ?Ï@?Ï??Ï°?ÏÐ?Ï Ï0 ÏP Ï? Ï  ÏÀ Ïð Ï¡Ï@¡Ï`¡ÏŸ¡Ï°¡Ïà¡Ï¢Ï0¢ÏP¢Ï?¢Ï ¢ÏТÏð¢Ï £Ï@£Ïp£ÏŸ£ÏÀ£Ïà£Ï¤Ï0¤Ï`¤Ï?¤Ï°¤ÏÐ¤Ï¥Ï ¥Ï@¥Ïp¥ÏŸ¥ÏÀ¥Ïà¥Ï¦Ï0¦ÏP¦Ï?¦Ï ¦ÏÀ¦Ïà¦Ï§Ï §Ï@§Ïp§ÏŸ§ÏÀ§Ïà§Ï¨Ï ¨Ï@¨Ï`¨Ï?¨Ï°¨ÏШÏð¨Ï ©Ï@©Ï`©Ï?©Ï ©ÏЩÏð©ÏªÏ0ªÏPªÏpªÏ ªÏЪÏðªÏ«Ï0«ÏP«Ï?«Ï «ÏÀ«Ïà«Ï¬Ï ¬Ï@¬Ï`¬Ï?¬Ï ¬ÏÀ¬Ïà¬ÏÏ Ï@Ï`Ï?Ï°ÏÐÏ®Ï ®Ï!cp1252xt1¸?ã''Ð?¸?ã''Ð?g slew rate 1000

 
 ! " " #$% & '()*+,-./0123456789:; & lt; = & gt; ?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~?¬  '''...???o/oo? " " ?}   " "   Ü " " !a " " ?~? ¡¢£¤¥¦§¨©ª«¬®¯°±²³´µ¶·¸¹º»¼½¾¿ÀÁÂÃÄÅÆÇÈÉÊËÌÍÎÏÐÑÒÓÔÕÖ×ØÙÚÛÜÝÞßàáâãäåæçèéêëìíîïðñòóôõö÷øùúûüýþÿ!xxxxt!1.01Boot V1.0ŸÄ!Y1Module Name1Äÿÿÿÿÿÿÿÿ1Base AddressÄÿÿÿÿ1Priorityeã''Ð?ÑÃAExecution Required for Standby WakeupAExecution Required for Normal Bootu1Register!Ã1Offset AddressñÂAValue Written to or Read from Register!delaybã''Ð?1Read or WriteaÂA Bits to Be Read or Writtenm RegisteAStart Bit to Be Read or Writtengiste1Register Attribute±Á!writeaHisilicon Technologies Co., Ltd. All rights reserved. @20121ÁABasic Project Informationitteegiste1Project NameÁÀ1Project Start Time`À1Product LineaÀ1Project Description1À1Project VersionÀ1DevelopmentÑ¿1Department¡¿!Media!Media1Project description1¿1nand flash¿1spi flashѾ1emmc flash¡¾!name!ID1chip size1¾1erase size¾1page sizeѽ1oob size¡½1ecc typeq½1jedec_idA½!ext_id1block_sizeñ¼1chip_sizeÁ¼!clk1chip selectq¼!SC_CTRL!0!0x2!2!0x2!3!slow10x20050000a»!N1PERI_CRG0»!0x0!311PERI_CRG1¡º!0x4!0x14!pll10x20030000º!N!N!normal10x20050000Ÿ¹1SC_PLLCTRLQ¹10x0fff8000!¹10x20110000ñ¸!Y1DDRC_SREFCTRL¡¸10x80000000q¸1DDRC_ODTCFGA¸1DDRC_INITCTRL¸1standby_pin_ctrlá·10x200f0000±·!0!read!noneAMT29F16G08CBABx-4K-24bit1Ktteegiste1NAND01GW3B2CN6á¶1K9F1G0bU0C±¶1K9F2G08U0BŸ¶1HY27UF082G2BQ¶1K9F4G08U0B!¶1HY27UF084G2Bñµ129F4G08ABADAÁµ129F1G08ABADA`µ1HY27UF081G2AaµA0x2C 0x48 0x04 0x46 0x85 0x00 0x00 0x00A0x20 0xF1 0x00 0x1D 0x20 0xF1 0x00 0x1DA0xEC 0xF1 0x00 0x95 0x40 0x00 0xEC 0xF1A0xEC 0xDA 0x10 0x95 0x44 0xEC 0xEC 0xDAA0xAD 0xDA 0x10 0x95 0x44 0xAD 0xDA 0x10A0xEC 0xDC 0x10 0x95 0x54 0xEC 0xEC 0xDCA0xAD 0xDC 0x10 0x95 0x54 0xAD 0xDC 0x10A0x2C 0xDC 0x90 0x95 0x56 0x00 0x00 0x00A0x2C 0xF1 0x80 0x95 0x02 0x00 0x00 0x00A0xAD 0xF1 0x80 0x1D 0xAD 0xF1 0x80 0x1D!2GB!128MB!256MB!512MB!1MB!128KB!128KB!4KB!2KB!2KB!2KB!2KB!224B!64B!64B!64B1mx25l1655d±°!w25x161s25sl032aa°1s25sl064a1°1s25sl12800°!m25px16!m25px32!m25px64!m25p32!m25p12810xc2 0x26 0x151¯10xef 0x30 0x15¯10x01 0x02 0x15Ñ®10x01 0x02 0x16¡®10x01 0x20 0x18q®10x20 0x71 0x15A®10x20 0x71 0x16®10x20 0x71 0x17á10x20 0x20 0x16±10x20 0x20 0x18Ÿ10x03 0x00Q!0x0!0x0!0x40100!0x601001Module Name¡¬1Priorityq¬AExecution Required for Standby WakeupAExecution Required for Normal Bootu11RegisterÁ«1Offset Address`«AValue Written to or Read from Register1Read or Write!«AStart Bit to Be Read or WrittengisteA Bits to Be Read or WrittenteegisteA Bits to Be Read or Writtenteegiste1Register Attribute1ª1PERI_CRG2ª!0x81PERI_CRG3±©!0xc1ddrc_inita©10x110000001©10x22000000©10x007c2063Ѩ!311DDRC_PHYCTRLŸ¨1muxctrl_reg27Q¨1muxctrl_reg29!¨1muxctrl_reg30ñ§1muxctrl_reg31Á§1muxctrl_reg32`§1muxctrl_reg33a§1muxctrl_reg341§1muxctrl_reg35§1muxctrl_reg36Ѧ1muxctrl_reg37¡¦!0x1!0!1!0x01muxctrl_reg19ñ¥!0x4c!UART11muxctrl_reg20Ÿ¥!0x501muxctrl_reg211¥!0x541muxctrl_reg22á¤1muxctrl_reg23±¤1muxctrl_reg24Ÿ¤1TEMPER_DQQ¤1PERI_CRG10!¤!0x28!0x0!0!1!21PERI_CRG58Q£!0xe8!0x7!31!NULL!1000!0x0!10000!0x408!0x01DDRC_PHYSTATUS¢!0x404!0x11DDRC_EMRS01`¡!0x14!0x61b601DDRC_EMRS23!¡!0x18!0x101DDRC_CONFIG0± !0x1c10x8000C600a !write1DDRC_CONFIG1 !0x20!0x7851DDRC_TIMING2¡?!0x581DDRC_CTRLQ?!0x11DDRC_RNKCFG?!0x2c!0x1321DDRC_TIMING0`?!0x501DDRC_TIMING1A?!0x541DDRC_TIMING3ñŸ!0x5c1DDRC_BASEADDR¡Ÿ!0x40!31!0xf41DDRC_DTRCTRLŸ!0xac10x3000301Á?!0x41DDRC_STATUSq?!0x8!31DDRC_PHY_REG4A?!0x838!0xA01DDRC_PHY_REG2` " " !0x808!200000!10!0x1B!0x31ether_sysctrlÁ?1DDRC_PHY_REG61`?!0xBE81Module NameA?1ddr_common?1Base Addressátm10x20110000±tm1PriorityŸtmAExecution Required for Standby WakeupAExecution Required for Normal Bootu1RegisterÑ?1Offset Address¡?AValue Written to or Read from Register!delay1Read or Write?A Bits to Be Read or Writtenm RegisteAStart Bit to Be Read or Writtengiste1Register Attributea - !NULL!0!100001DDRC_PHY_REG12Ñ-!0x840!0xcc!311CMD0???01100=46?A-1DDRC_PHY_REG14-!0x848!0x0!11DDRC_PHY_REG13Ÿ*!0x844!0xffACMD0 rising/falling slew rate 1111te1DDRC_PHY_REG16Ñ''!0x8541CMD1???01100=46?Ÿ''1DDRC_PHY_REG18Q''!0x85c1DDRC_PHY_REG17?!0x858ACMD1 rising/falling slew rate 1111te1DDRC_PHY_REG22q``!0x8701CK???01100=46?!``1DDRC_PHY_REG24ñ'!0x8781DDRC_PHY_REG23¡'!0x874ACK rising/falling slew rate 1111ste1DDRC_PHY_REG25'!0x8801DQ???01100=46?Á`1DDRC_PHY_REG28``!0x88c!41DDRC_PHY_REG26!`!0x884!0x88ADQ rising/falling slew rate 1000ste1DDRC_PHY_REG27qŸ!0x8881ODT?1011=120!Ÿ1DDRC_PHY_REG28ñŸ!0x31DDRC_PHY_REG30¡Ÿ!0xac4!0x01DDRC_PHY_REG311Ÿ!0xac81DDRC_PHY_REG32á?!0xacc1DDRC_PHY_REG33`?!0xad01DDRC_PHY_REG34A?!0xad41DDRC_PHY_REG35ñŸ!0xad81DDRC_PHY_REG36¡Ÿ!0xadc1DDRC_PHY_REG37QŸ!0xae01DDRC_PHY_REG38?!0xae41DDRC_PHY_REG39±?!0xae81DDRC_PHY_REG41a?!0xaf01DDRC_PHY_REG42?!0xaf41DDRC_PHY_REG43Á " " !0xaf81DDRC_PHY_REG53q " " !0xb201DDRC_PHY_REG40! " " !0xaec!0x91DDRC_PHY_REG54±?!0xb241DDRC_PHY_REG55a?!0xb281DDRC_PHY_TXDQSKEW?!0xafc!0xb001DDRC_PHY_TXDQSKEW¡o/oo!0xb04!0xb08!0xb0c!0xb10!0xb14!0xb181DDRC_PHY_REG52±?!0xb1c1DDRC_PHY_RXDQSKEWa?!0xb2c!0xb30!0xb34!0xb38!0xb3c!0xb401DDRC_PHY_RXDQSKEWq?!0xb44!0xb481DDRC_PHY_REG5E?!0xb4c!0x2!0!11SKT???PWMQ?!0x58!0x0!0x5C!UART2!0x601??PHY?????GPIO??Ÿ...1muxctrl_reg26Q...!0x68!0x1!USB0!0x6c1muxctrl_reg28¡''!0x70!USB1!0x74!0x78!0x1!0!HDMI!0x7c!0x80!0x84!0x88!SATA!0x8c!0x90!ETH!0x941muxctrl_reg48q'!0xc01SC_CTRL_SWDQS_TRAINING!'!0xa0q??DQStraining??_sQÿbit[0]ÿ
0ÿ
N?Oý?o?öNDQStrainingÿÅN?O(ulxöNtrainingÿ
1`Ÿ: & lt;
=B
70x0 7
DDRC_PHY_270xa0470x1f7031
DDRC_PHY_370xac070x557
DDRC_PHY_570x80470x4b7PERIPHCTRL2870xa47?07PERIPHCTRL2970xa873172
$NB\?gM`n?ÿ
[6:4]SFC :4ma 010;
[2:0]PAD_SPI_SDO:4ma 010
72ÛVB\?gM`n?ÿ
[6:4]SFC :8ma 110;
[2:0]PAD_SPI_SDO:8ma 1107Ü
$NB\?gM`n?ÿ
[30:28]spi_sclk:8ma 110;
[26:24]aio_ws_tx:4ma 010;
[22:20]aio_bclk_tx:11ma 111;
[18:16]aio_ws_rx:4ma 010;
[14:12]aio_bclk_rx:11ma 111;
[10:8]aio_mclk:11ma 111;
[6:4]vga_hs/vga_vs:8ma 010;
[2:0]vi_adc_clk:11ma 111
7
0x627277277
0x000000227ÞÛVB\?gM`n?ÿ
[30:28]spi_sclk:11ma 111;
[26:24]aio_ws_tx:4ma 010;
[22:20]aio_bclk_tx:11ma 111;
[18:16]aio_ws_rx:4ma 010;
[14:12]aio_bclk_rx:11ma 111;
[10:8]aio_mclk:11ma 111;
[6:4]vga_hs/vga_vs:12ma 100;
[2:0]vi_adc_clk:11ma 1117
DDRC_PHY_170x8307?07
DDRC_PHY_470x81870x4070x87?07317
DDRC_PHY_REG870x8e070x237?07317DDRC_PHY_REG1170x92070x227
DDRC_PHY_REG670x8d470xc7
DDRC_PHY_REG970x91470xd7
0x00000015·
0x181D0000·0x0000000FD7
0x0000100D7
0x0015000070x0000000FD7
0x000000157
0x181D00007
0x0000000570x070x0000000FD7
0x0000000D7
0x0000200D70x0000000FD7
0x000500007
0x0000005570x07
0x100500007
0x180500007
0x000D00007
0x0000000D70x917
PERI_CRG51 70xcc7
0x0000000f7?073170x0000000FD7
...Qè?CRG
7NULL71000070x07
0x0000000a7
muxctrl_reg380x9870x17
0x000000157RMII7
muxctrl_reg390x9c7
muxctrl_reg400xa07
muxctrl_reg410xa47
muxctrl_reg420xa87
muxctrl_reg430xac7
muxctrl_reg440xb07
muxctrl_reg450xb47
muxctrl_reg4970xc47MDIO7
muxctrl_reg5070xc87PERIPHCTRL2470x947?87
0x007c30967
0x6355100B7
0xFF637A317
0x3350E0007
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 " Module Name " , " ddr_common "
" Base Address " , " 0x20110000 "
" Priority " , " 4 "
" Execution Required for Standby Wakeup " , " N "
" Execution Required for Normal Boot " , " Y "
" Register " , " Offset Address " , " Value Written to or Read from Register " , " delay " , " Read or Write " , " Bits to Be Read or Written " , " Start Bit to Be Read or Written " , " Register Attribute "
" NULL " , " 0 " , " 0 " , " 10000 " , " none " , " 0 " , " 0 " , " "
" " , " " , " " , " " , " write " , " " , " " , " " ,
" " , " " , " " , " " , " write " , " " , " " , " " ,
" " , " " , " " , " " , " write " , " " , " " , " " ,
" " , " " , " " , " " , " write " , " " , " " , " " ,
" " , " " , " " , " " , " write " , " " , " " , " " ,
" DDRC_PHY_REG12 " , " 0x840 " , " 0xcc " , " 0 " , " write " , " 31 " , " 0 " , " " , " CMD0???01100=46? "
" DDRC_PHY_REG14 " , " 0x848 " , " 0x0 " , " 0 " , " write " , " 1 " , " 0 " , " " ,
" DDRC_PHY_REG13 " , " 0x844 " , " 0xff " , " 0 " , " write " , " 31 " , " 0 " , " " , " CMD0 rising/falling slew rate 1111 "
" DDRC_PHY_REG16 " , " 0x854 " , " 0xcc " , " 0 " , " write " , " 31 " , " 0 " , " " , " CMD1???01100=46? "
" DDRC_PHY_REG18 " , " 0x85c " , " 0x0 " , " 0 " , " write " , " 1 " , " 0 " , " " ,
" DDRC_PHY_REG17 " , " 0x858 " , " 0xff " , " 0 " , " write " , " 31 " , " 0 " , " " , " CMD1 rising/falling slew rate 1111 "
" DDRC_PHY_REG22 " , " 0x870 " , " 0xcc " , " 0 " , " write " , " 31 " , " 0 " , " " , " CK???01100=46? "
" DDRC_PHY_REG24 " , " 0x878 " , " 0x0 " , " 0 " , " write " , " 1 " , " 0 " , " " ,
" DDRC_PHY_REG23 " , " 0x874 " , " 0xff " , " 0 " , " write " , " 31 " , " 0 " , " " , " CK rising/falling slew rate 1111 "
" DDRC_PHY_REG25 " , " 0x880 " , " 0xcc " , " 0 " , " write " , " 31 " , " 0 " , " " , " DQ???01100=46? "
" DDRC_PHY_REG28 " , " 0x88c " , " 0x0 " , " 0 " , " write " , " 1 " , " 4 " , " " ,
" DDRC_PHY_REG26 " , " 0x884 " , " 0x88 " , " 0 " , " write " , " 31 " , " 0 " , " " , " DQ rising/falling slew rate 1000 "
" DDRC_PHY_REG27 " , " 0x888 " , " 0x1B " , " 0 " , " write " , " 31 " , " 0 " , " " , " ODT?1011=120 "
" DDRC_PHY_REG28 " , " 0x88c " , " 0x3 " , " 0 " , " write " , " 1 " , " 0 " , " " ,
" DDRC_PHY_REG30 " , " 0xac4 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG31 " , " 0xac8 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG32 " , " 0xacc " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG33 " , " 0xad0 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG34 " , " 0xad4 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG35 " , " 0xad8 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG36 " , " 0xadc " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG37 " , " 0xae0 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG38 " , " 0xae4 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG39 " , " 0xae8 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG41 " , " 0xaf0 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG42 " , " 0xaf4 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG43 " , " 0xaf8 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG53 " , " 0xb20 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG40 " , " 0xaec " , " 0x9 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG54 " , " 0xb24 " , " 0x9 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG55 " , " 0xb28 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_TXDQSKEW " , " 0xafc " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_TXDQSKEW " , " 0xb00 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_TXDQSKEW " , " 0xb04 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_TXDQSKEW " , " 0xb08 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_TXDQSKEW " , " 0xb0c " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_TXDQSKEW " , " 0xb10 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_TXDQSKEW " , " 0xb14 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_TXDQSKEW " , " 0xb18 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG52 " , " 0xb1c " , " " , " " , " write " , " " , " " , " "
" DDRC_PHY_RXDQSKEW " , " 0xb2c " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_RXDQSKEW " , " 0xb30 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_RXDQSKEW " , " 0xb34 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_RXDQSKEW " , " 0xb38 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_RXDQSKEW " , " 0xb3c " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_RXDQSKEW " , " 0xb40 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_RXDQSKEW " , " 0xb44 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_RXDQSKEW " , " 0xb48 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG5E " , " 0xb4c " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" " , " " , " " , " " , " write " , " " , " " , " "
" " , " " , " " , " " , " write " , " " , " " , " "
" " , " " , " " , " " , " write " , " " , " " , " "
" " , " " , " " , " " , " write " , " " , " " , " "
 " Module Name " , " ddrc_init "
" Base Address " , " 0x20110000 "
" Priority " , " 5 "
" Execution Required for Standby Wakeup " , " N "
" Execution Required for Normal Boot " , " Y "
" Register " , " Offset Address " , " Value Written to or Read from Register " , " delay " , " Read or Write " , " Bits to Be Read or Written " , " Start Bit to Be Read or Written " , " Register Attribute "
" NULL " , " 0 " , " 0 " , " 10000 " , " none " , " 0 " , " 0 " , " "
" DDRC_PHYCTRL " , " 0x408 " , " 0x0 " , " 1000 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHYSTATUS " , " 0x404 " , " 0x1 " , " 0 " , " read " , " 0 " , " 0 " , " "
" DDRC_EMRS01 " , " 0x14 " , " 0x61b60 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_EMRS23 " , " 0x18 " , " 0x10 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_CONFIG0 " , " 0x1c " , " 0x8000C600 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_CONFIG1 " , " 0x20 " , " 0x785 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_TIMING2 " , " 0x58 " , " 0x0 " , " 0 " , " write " , " 10 " , " 0 " , " "
" DDRC_CTRL " , " 0x10 " , " 0x1 " , " 0 " , " write " , " 31 " , " 0 " , " "
" NULL " , " 0 " , " 0 " , " 200000 " , " none " , " 0 " , " 0 " , " "
" DDRC_RNKCFG " , " 0x2c " , " 0x132 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_TIMING0 " , " 0x50 " , " " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_TIMING1 " , " 0x54 " , " " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_TIMING2 " , " 0x58 " , " " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_TIMING3 " , " 0x5c " , " " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_BASEADDR " , " 0x40 " , " 0x80000000 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_ODTCFG " , " 0xf4 " , " 0x1 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_DTRCTRL " , " 0xac " , " 0x3000301 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_SREFCTRL " , " 0x4 " , " 0 " , " 1000 " , " write " , " 31 " , " 0 " , " "
" DDRC_STATUS " , " 0x0 " , " 0x0 " , " 0 " , " read " , " 0 " , " 2 " , " "
" DDRC_INITCTRL " , " 0x8 " , " 0x1 " , " 1000 " , " write " , " 0 " , " 0 " , " "
" DDRC_STATUS " , " 0x0 " , " 0x0 " , " 0 " , " read " , " 0 " , " 3 " , " "
" DDRC_PHY_REG4A " , " 0x838 " , " 0xA0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG2 " , " 0x808 " , " 0x1 " , " 1000 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG61 " , " 0xBE8 " , " 0x3 " , " 0 " , " read " , " 1 " , " 0 " , " "
" DDRC_PHY_REG2 " , " 0x808 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_TIMING2 " , " 0x58 " , " " , " 0 " , " write " , " 10 " , " 0 " , " "
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 " Module Name " , " standby_pin_ctrl "
" Base Address " , " 0x200f0000 "
" Priority " , " 6 "
" Execution Required for Standby Wakeup " , " N "
" Execution Required for Normal Boot " , " Y "
" Register " , " Offset Address " , " Value Written to or Read from Register " , " delay " , " Read or Write " , " Bits to Be Read or Written " , " Start Bit to Be Read or Written " , " Register Attribute "
" muxctrl_reg19 " , " 0x4c " , " 0x0 " , " 0 " , " write " , " 0 " , " 0 " , " " , " UART1 "
" muxctrl_reg20 " , " 0x50 " , " 0x0 " , " 0 " , " write " , " 0 " , " 0 " , " " ,
" muxctrl_reg21 " , " 0x54 " , " 0x2 " , " 0 " , " write " , " 1 " , " 0 " , " " ,, " SKT???PWM "
" muxctrl_reg22 " , " 0x58 " , " 0x0 " , " 0 " , " write " , " 0 " , " 0 " , " " ,
" muxctrl_reg23 " , " 0x5C " , " 0x0 " , " 0 " , " write " , " 0 " , " 0 " , " " , " UART2 "
" muxctrl_reg24 " , " 0x60 " , " 0x0 " , " 0 " , " write " , " 0 " , " 0 " , " " ,, " ??PHY?????GPIO?? "
" muxctrl_reg26 " , " 0x68 " , " 0x1 " , " 0 " , " write " , " 0 " , " 0 " , " " , " USB0 "
" muxctrl_reg27 " , " 0x6c " , " 0x1 " , " 0 " , " write " , " 0 " , " 0 " , " " ,
" muxctrl_reg28 " , " 0x70 " , " 0x1 " , " 0 " , " write " , " 0 " , " 0 " , " " , " USB1 "
" muxctrl_reg29 " , " 0x74 " , " 0x1 " , " 0 " , " write " , " 0 " , " 0 " , " " ,
" muxctrl_reg30 " , " 0x78 " , " 0x1 " , " 0 " , " write " , " 0 " , " 0 " , " " , " HDMI "
" muxctrl_reg31 " , " 0x7c " , " 0x1 " , " 0 " , " write " , " 0 " , " 0 " , " " ,
" muxctrl_reg32 " , " 0x80 " , " 0x1 " , " 0 " , " write " , " 0 " , " 0 " , " " ,
" muxctrl_reg33 " , " 0x84 " , " 0x1 " , " 0 " , " write " , " 0 " , " 0 " , " " ,
" muxctrl_reg34 " , " 0x88 " , " 0x1 " , " 0 " , " write " , " 0 " , " 0 " , " " , " SATA "
" muxctrl_reg35 " , " 0x8c " , " 0x1 " , " 0 " , " write " , " 0 " , " 0 " , " " ,
" muxctrl_reg36 " , " 0x90 " , " 0x1 " , " 0 " , " write " , " 0 " , " 0 " , " " , " ETH "
" muxctrl_reg37 " , " 0x94 " , " 0x1 " , " 0 " , " write " , " 0 " , " 0 " , " " ,
" muxctrl_reg48 " , " 0xc0 " , " 0x1 " , " 0 " , " write " , " 0 " , " 0 " , " " , " TEMPER_DQ "
" " , " " , " " , " " , " write " , " " , " " , " " , " "
" " , " " , " " , " " , " write " , " " , " " , " " ,
" " , " " , " " , " " , " write " , " " , " " , " " ,
" " , " " , " " , " " , " write " , " " , " " , " " ,
" " , " " , " " , " " , " write " , " " , " " , " " ,
" " , " " , " " , " " , " write " , " " , " " , " " ,
" " , " " , " " , " " , " write " , " " , " " , " " ,
" " , " " , " " , " " , " write " , " " , " " , " " ,
" " , " " , " " , " " , " write " , " " , " " , " " , " "
" " , " " , " " , " " , " write " , " " , " " , " " ,
 " Module Name " , " ether_sysctrl "
" Base Address " , " 0x20050000 "
" Priority " , " 7 "
" Execution Required for Standby Wakeup " , " N "
" Execution Required for Normal Boot " , " Y "
" Register " , " Offset Address " , " Value Written to or Read from Register " , " delay " , " Read or Write " , " Bits to Be Read or Written " , " Start Bit to Be Read or Written " , " Register Attribute "
" " , " " , " 0x1 " , " 0 " , " write " , " 0 " , " " , " "
" " , " " , " " , " 0 " , " write " , " 31 " , " 0 " , " " , " " , " "
" " , " " , " " , " " , " write " , " " , " " , " " , " " , " "
,,,,,,,
,,,,,,,
,,,,,,,
 " nand flash " ,,,,,,,, " spi flash " ,,,,,,,, " emmc flash " ,,,,,,
" name " , " ID " , " chip size " , " erase size " , " page size " , " oob size " , " ecc type " ,, " name " , " jedec_id " , " ext_id " , " block_size " , " chip_size " , " clk " , " chip select "
" MT29F16G08CBABx-4K-24bit1K " , " 0x2C 0x48 0x04 0x46 0x85 0x00 0x00 0x00 " , " 2GB " , " 1MB " , " 4KB " , " 224B " , " 4 " ,, " mx25l1655d " , " 0xc2 0x26 0x15 " , " 0x0 " , " 65536 " , " 2097152 " , " 0x40100 " , " 1 "
" NAND01GW3B2CN6 " , " 0x20 0xF1 0x00 0x1D 0x20 0xF1 0x00 0x1D " , " 128MB " , " 128KB " , " 2KB " , " 64B " , " 1 " ,, " w25x16 " , " 0xef 0x30 0x15 " , " 0x0 " , " 65536 " , " 2097152 " , " 0x40100 " , " 1 "
" K9F1G0bU0C " , " 0xEC 0xF1 0x00 0x95 0x40 0x00 0xEC 0xF1 " , " 128MB " , " 128KB " , " 2KB " , " 64B " , " 1 " ,, " s25sl032a " , " 0x01 0x02 0x15 " , " 0x0 " , " 65536 " , " 4194304 " , " 0x40100 " , " 1 "
" K9F2G08U0B " , " 0xEC 0xDA 0x10 0x95 0x44 0xEC 0xEC 0xDA " , " 256MB " , " 128KB " , " 2KB " , " 64B " , " 1 " ,, " s25sl064a " , " 0x01 0x02 0x16 " , " 0x0 " , " 65536 " , " 8388608 " , " 0x40100 " , " 1 "
" HY27UF082G2B " , " 0xAD 0xDA 0x10 0x95 0x44 0xAD 0xDA 0x10 " , " 256MB " , " 128KB " , " 2KB " , " 64B " , " 1 " ,, " s25sl12800 " , " 0x01 0x20 0x18 " , " 0x03 0x00 " , " 262144 " , " 16777216 " , " 0x60100 " , " 1 "
" K9F4G08U0B " , " 0xEC 0xDC 0x10 0x95 0x54 0xEC 0xEC 0xDC " , " 512MB " , " 128KB " , " 2KB " , " 64B " , " 1 " ,, " m25px16 " , " 0x20 0x71 0x15 " , " 0x0 " , " 65536 " , " 2097152 " , " 0x40100 " , " 1 "
" HY27UF084G2B " , " 0xAD 0xDC 0x10 0x95 0x54 0xAD 0xDC 0x10 " , " 512MB " , " 128KB " , " 2KB " , " 64B " , " 1 " ,, " m25px32 " , " 0x20 0x71 0x16 " , " 0x0 " , " 65536 " , " 4194304 " , " 0x40100 " , " 1 "
" 29F4G08ABADA " , " 0x2C 0xDC 0x90 0x95 0x56 0x00 0x00 0x00 " , " 512MB " , " 128KB " , " 2KB " , " 64B " , " 1 " ,, " m25px64 " , " 0x20 0x71 0x17 " , " 0x0 " , " 65536 " , " 8388608 " , " 0x40100 " , " 1 "
" 29F1G08ABADA " , " 0x2C 0xF1 0x80 0x95 0x02 0x00 0x00 0x00 " , " 128MB " , " 128KB " , " 2KB " , " 64B " , " 1 " ,, " m25p32 " , " 0x20 0x20 0x16 " , " 0x0 " , " 65536 " , " 4194304 " , " 0x40100 " , " 1 "
" HY27UF081G2A " , " 0xAD 0xF1 0x80 0x1D 0xAD 0xF1 0x80 0x1D " , " 128MB " , " 128KB " , " 2KB " , " 64B " , " 1 " ,, " m25p128 " , " 0x20 0x20 0x18 " , " 0x0 " , " 262144 " , " 16777216 " , " 0x40100 " , " 1 "


uboot_tools.zip > uboot-Hi3515A-bvt_No1_600_300_600_ddr_innerFEPHY.xls

,,,,
, " Boot V1.0 " ,,
, " Hisilicon Technologies Co., Ltd. All rights reserved. @2012 " ,,
,,,,,,,,
" Basic Project Information " ,,,,
,,,,
" Project Name " , " xxx " ,, " Project Version " , " 1.0 "
" Project Start Time " , " 40543 " ,, " Development " , " xxx "
" Product Line " , " Media " ,, " Department " , " Media "
" Project Description " , " Project description " ,,,
 " Module Name " , " slow "
" Base Address " , " 0x20050000 "
" Priority " , " 1 "
" Execution Required for Standby Wakeup " , " N "
" Execution Required for Normal Boot " , " Y "
" Register " , " Offset Address " , " Value Written to or Read from Register " , " delay " , " Read or Write " , " Bits to Be Read or Written " , " Start Bit to Be Read or Written " , " Register Attribute "
" SC_CTRL " , " 0 " , " 0x2 " , " 0 " , " write " , " 2 " , " 0 " , " "
" SC_CTRL " , " 0 " , " 0x2 " , " 0 " , " read " , " 3 " , " 3 " , " "
,,,,,,,
,,,,,,,
,,,,,,,
 " Module Name " , " pll "
" Base Address " , " 0x20030000 "
" Priority " , " 2 "
" Execution Required for Standby Wakeup " , " N "
" Execution Required for Normal Boot " , " Y " ,,,,,,
" Register " , " Offset Address " , " Value Written to or Read from Register " , " delay " , " Read or Write " , " Bits to Be Read or Written " , " Start Bit to Be Read or Written " , " Register Attribute "
" PERI_CRG0 " , " 0x0 " , " 0x11000000 " , " 0 " , " write " , " 31 " , " 0 " , " "
" PERI_CRG1 " , " 0x4 " , " " , " 0 " , " write " , " 31 " , " 0 " , " "
" PERI_CRG2 " , " 0x8 " , " 0x22000000 " , " 0 " , " write " , " 31 " , " 0 " , " "
" PERI_CRG3 " , " 0xc " , " 0x007c2063 " , " 0 " , " write " , " 31 " , " 0 " , " "
" PERI_CRG10 " , " 0x28 " , " 0x0 " , " 0 " , " write " , " 1 " , " 2 " , " "
" PERI_CRG58 " , " 0xe8 " , " 0x7 " , " 0 " , " read " , " 2 " , " 0 " , " "
,,,,,,,
,,,,,,,
,,,,,,,
,,,,,,,
,,,,,,,
 " Module Name " , " normal "
" Base Address " , " 0x20050000 "
" Priority " , " 3 "
" Execution Required for Standby Wakeup " , " N "
" Execution Required for Normal Boot " , " Y "
" Register " , " Offset Address " , " Value Written to or Read from Register " , " delay " , " Read or Write " , " Bits to Be Read or Written " , " Start Bit to Be Read or Written " , " Register Attribute "
" SC_PLLCTRL " , " 0x14 " , " 0x0fff8000 " , " 0 " , " write " , " 31 " , " 0 " , " "
" SC_CTRL " , " 0 " , " 0x4 " , " 0 " , " write " , " 2 " , " 0 " , " "
" SC_CTRL " , " 0 " , " 0x4 " , " 0 " , " read " , " 3 " , " 3 " , " "
" SC_CTRL_SWDQS_TRAINING " , " 0xa0 " , "  & lt;
=B
70x0 7
DDRC_PHY_270xa0470x1f7031
DDRC_PHY_370xac070x557
DDRC_PHY_570x80470x4b7PERIPHCTRL2870xa47?07Ü
$NB\?gM`n?ÿ
[30:28]spi_sclk:8ma 110;
[26:24]aio_ws_tx:4ma 010;
[22:20]aio_bclk_tx:11ma 111;
[18:16]aio_ws_rx:4ma 010;
[14:12]aio_bclk_rx:11ma 111;
[10:8]aio_mclk:11ma 111;
[6:4]vga_hs/vga_vs:8ma 010;
[2:0]vi_adc_clk:11ma 111
7PERIPHCTRL2970xa873172
$NB\?gM`n?ÿ
[6:4]SFC :4ma 010;
[2:0]PAD_SPI_SDO:4ma 010
72ÛVB\?gM`n?ÿ
[6:4]SFC :8ma 110;
[2:0]PAD_SPI_SDO:8ma 1107ÞÛVB\?gM`n?ÿ
[30:28]spi_sclk:11ma 111;
[26:24]aio_ws_tx:4ma 010;
[22:20]aio_bclk_tx:11ma 111;
[18:16]aio_ws_rx:4ma 010;
[14:12]aio_bclk_rx:11ma 111;
[10:8]aio_mclk:11ma 111;
[6:4]vga_hs/vga_vs:12ma 100;
[2:0]vi_adc_clk:11ma 1117
DDRC_PHY_REG870x8e070x2370x8d470xd70x91470xd7
DDRC_PHY_REG67
DDRC_PHY_REG97
0x007c30967
0x6355100B7
0xFF637A317
0x3350E0007
0xFFDFF6f370x937
0x000000227
0x627277277PERIPHCTRL2470x9470x07?07127
DDRC_PHY_170x8307?07
DDRC_PHY_470x81870x407
DDRC_PHY_REG870x8e070x237317DDRC_PHY_REG1170x92070x227
DDRC_PHY_REG670x8d470xc7
DDRC_PHY_REG970x91470xd7
0x00000015·
0x181D0000·0x0000000FD7
0x0000100D7
0x0015000070x0000000FD7
0x000000157
0x181D00007
0x0000000570x070x0000000FD7
0x0000000D7
0x0000200D7
0x000500007
0x0000005570x07
0x100500007
0x180500007
0x000D00007
0x0000000D7
0x000040057
0x0000600570x917áÀPÉ  - ÊÀ - Êà - Ê?Ê0?Ê`?ʟ?ÊÀ?ÊtmÊ@tmÊptmÊ tmÊàtmÊ?Ê0?Êp?Ê°?Êà?Ê " " Ê` " " Ê  " " ÊÐ " " Ê?Ê0?Ê`?ʟ?ÊÀ?Êð?ÊŸÊ0ŸÊ`ŸÊŸŸÊÀŸÊðŸÊ?Ê0?Ê`?ʟ?ÊÀ?Êð?Ê ?ÊP?Êp?Ê ?ÊÐ?Êð?Ê  Ê@ Ê` Ê? Ê  ÊÀ Êà Ê¡Ê0¡ÊP¡Ê?¡Ê ¡ÊÀ¡Êð¡Ê¢Ê0¢ÊP¢Ê?¢Ê ¢ÊÀ¢Êà¢Ê£Ê@£Êp£Ê £ÊÀ£Êð£Ê ¤ÊP¤Ê?¤Ê°¤Êà¤Ê¥Ê ¥Ê@¥Ê?¥Ê°¥Êà¥Ê¦Ê@¦Êp¦Ê ¦ÊЦʧÊ0§Êp§Ê°§Êð§Ê0¨Êp¨Ê°¨Êð¨Ê0©Êp©Ê°©ÊЩÊð©ÊªÊ0ªÊPªÊpªÊŸªÊ°ªÊЪÊðªÊ«Ê0«ÊP«Êp«ÊŸ«Ê°«Êà«Ê¬Ê0¬Ê`¬ÊŸ¬Ê°¬ÊЬÊð¬ÊÊ0Ê`ʟÊÀÊðÊ ®ÊP®Ê?®Ê°®Êà®Ê¯Ê@¯Ê`¯Ê?¯Ê ¯ÊÀ¯Êð¯Ê °Ê`°Ê °ÊаʱÊ@±Êp±Ê°±Êð±Ê0²Ê`²ÊŸ²Ê°²Êà²Ê³Ê0³Ê`³ÊŸ³ÊÀ³Êà³Ê´Ê@´Êp´Ê ´ÊдʵÊ0µÊ`µÊŸµÊÀµÊðµÊ ¶Ê@¶Ê`¶Ê?¶Ê ¶ÊÀ¶Êà¶Ê·Ê0·ÊP·Êp·Ê ·ÊÀ·Êð·Ê¸Ê@¸Êp¸Ê ¸ÊÐ¸Ê¹Ê ¹Ê@¹Ê`¹Ê?¹Ê ¹ÊйÊð¹ÊºÊ0ºÊPºÊpºÊŸºÊ°ºÊкÊðºÊ »Ê@»Ê`»ÊŸ»Ê°»ÊÐ»Ê¼Ê ¼Ê@¼Êp¼ÊŸ¼ÊÀ¼Êà¼Ê½Ê0½ÊP½Ê?½Ê ½ÊнÊð½Ê ¾Ê@¾Ê`¾ÊŸ¾Ê°¾Êà¾Ê¿Ê0¿ÊP¿Ê?¿Ê ¿ÊÀ¿Êà¿ÊÀÊ0ÀÊ`ÀÊ?ÀÊ°ÀÊÐÀÊðÀÊ ÁÊ@ÁÊ`ÁʟÁÊ°ÁÊÐÁÊðÁÊÂÊ0ÂÊ`ÂʟÂÊ°ÂÊàÂÊÃÊ@ÃÊpÃÊ ÃÊàÃÊ ÄÊPÄÊ?ÄÊÀÄÊàÄÊÅÊPÅʟÅÊÀÅÊàÅÊÆÊ ÆÊPÆÊpÆʟÆÊ°ÆÊàÆÊÇÊ0ÇÊPÇÊpÇÊ ÇÊÀÇÊàÇÊ ÈÊPÈÊpÈÊ ÈÊÐÈÊðÈÊ ÉÊ@ÉÊ?ÉÊ°ÉÊÐÉÊÊÊ0ÊÊPÊÊ?ÊÊ ÊÊàÊÊËÊ0ËÊ`ËʟËÊ°ËÊÐËÊÌÊ ÌÊ@ÌÊ?ÌÊ°ÌÊÐÌÊÍÊ0ÍÊPÍÊ?ÍÊ ÍÊÀÍÊðÍÊÎÊ@ÎÊ`ÎʟÎÊ°ÎÊàÎÊÏÊ0ÏÊPÏÊ?ÏÊ ÏÊÐÏÊðÏÊ ÐÊ@ÐÊpÐʟÐÊÀÐÊàÐÊÑÊ0ÑÊ`ÑÊ?ÑÊ°ÑÊÐÑÊÒÊ ÒÊ@ÒÊpÒʟÒÊÀÒÊàÒÊÓÊ0ÓÊPÓÊ?ÓÊ ÓÊÀÓÊàÓÊÔÊ ÔÊ@ÔÊpÔʟÔÊÀÔÊàÔÊÕÊ ÕÊ@ÕÊ`ÕÊ?ÕÊ°ÕÊÐÕÊðÕÊ ÖÊ@ÖÊ`ÖÊ?ÖÊ ÖÊÐÖÊðÖÊ×Ê0×ÊP×Êp×Ê ×ÊÐ×Êð×ÊØÊ0ØÊPØÊ?ØÊ ØÊÀØÊàØÊÙÊ ÙÊ@ÙÊ`ÙÊ?ÙÊ ÙÊÀÙÊàÙÊÚÊ ÚÊ@ÚÊ`ÚÊ?ÚÊ°ÚÊÐÚÊÛÊ ÛÊ!cp1252xt1¸?§»¢?¸?§»¢?g slew rate 1000

 
 ! " " #$% & '()*+,-./0123456789:; & lt; = & gt; ?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~?¬  '''...???o/oo? " " ?}   " "   Ü " " !a " " ?~? ¡¢£¤¥¦§¨©ª«¬®¯°±²³´µ¶·¸¹º»¼½¾¿ÀÁÂÃÄÅÆÇÈÉÊËÌÍÎÏÐÑÒÓÔÕÖ×ØÙÚÛÜÝÞßàáâãäåæçèéêëìíîïðñòóôõö÷øùúûüýþÿ!xxxxt!1.01Boot V1.0È!Y1Module NameÁÇÿÿÿÿÿÿÿÿ1Base Address`Çÿÿÿÿ1Priorityu§»¢?aÇAExecution Required for Standby WakeupAExecution Required for Normal Bootu1Register±Æ1Offset AddressŸÆAValue Written to or Read from Register!delayr§»¢?1Read or WriteñÅA Bits to Be Read or Writtenm RegisteAStart Bit to Be Read or Writtengiste1Register AttributeAÅ!writeaHisilicon Technologies Co., Ltd. All rights reserved. @2012ÁÄABasic Project Informationitteegiste1Project NameQÄ1Project Start Time!Ä1Product LineñÃ1Project DescriptionÁÃ1Project Version`Ã1DevelopmentaÃ1Department1Ã!Media!Media1Project descriptionÁÂ1nand flash`Â1spi flashaÂ1emmc flash1Â!name!ID1chip sizeÁÁ1erase size`Á1page sizeaÁ1oob size1Á1ecc typeÁ1jedec_idÑÀ!ext_id1block_sizeŸÀ1chip_sizeQÀ!clk1chip selectÀ!SC_CTRL!0!0x2!2!0x2!3!slow10x20050000ñ¾!N1PERI_CRG0¡¾!0x0!311PERI_CRG11¾!0x4!0x14!pll10x20030000¡½!N!N!normal10x20050000½1SC_PLLCTRLá¼10x0fff8000±¼10x20110000Ÿ¼!Y1DDRC_SREFCTRL1¼10x80000000¼1DDRC_ODTCFGÑ»1DDRC_INITCTRL¡»1standby_pin_ctrlq»10x200f0000A»!0!read!noneAMT29F16G08CBABx-4K-24bit1Ktteegiste1NAND01GW3B2CN6qº1K9F1G0bU0CAº1K9F2G08U0Bº1HY27UF082G2Bá¹1K9F4G08U0B±¹1HY27UF084G2BŸ¹129F4G08ABADAQ¹129F1G08ABADA!¹1HY27UF081G2Añ¸A0x2C 0x48 0x04 0x46 0x85 0x00 0x00 0x00A0x20 0xF1 0x00 0x1D 0x20 0xF1 0x00 0x1DA0xEC 0xF1 0x00 0x95 0x40 0x00 0xEC 0xF1A0xEC 0xDA 0x10 0x95 0x44 0xEC 0xEC 0xDAA0xAD 0xDA 0x10 0x95 0x44 0xAD 0xDA 0x10A0xEC 0xDC 0x10 0x95 0x54 0xEC 0xEC 0xDCA0xAD 0xDC 0x10 0x95 0x54 0xAD 0xDC 0x10A0x2C 0xDC 0x90 0x95 0x56 0x00 0x00 0x00A0x2C 0xF1 0x80 0x95 0x02 0x00 0x00 0x00A0xAD 0xF1 0x80 0x1D 0xAD 0xF1 0x80 0x1D!2GB!128MB!256MB!512MB!1MB!128KB!128KB!4KB!2KB!2KB!2KB!2KB!224B!64B!64B!64B1mx25l1655dA´!w25x161s25sl032añ³1s25sl064aÁ³1s25sl12800`³!m25px16!m25px32!m25px64!m25p32!m25p12810xc2 0x26 0x15Á²10xef 0x30 0x15`²10x01 0x02 0x15a²10x01 0x02 0x161²10x01 0x20 0x18²10x20 0x71 0x15ѱ10x20 0x71 0x16¡±10x20 0x71 0x17q±10x20 0x20 0x16A±10x20 0x20 0x18±10x03 0x00á°!0x0!0x0!0x40100!0x601001Module Name1°1Priority°AExecution Required for Standby WakeupAExecution Required for Normal Bootu11RegisterQ¯1Offset Address!¯AValue Written to or Read from Register1Read or Write±®AStart Bit to Be Read or WrittengisteA Bits to Be Read or WrittenteegisteA Bits to Be Read or Writtenteegiste1Register AttributeÁ1PERI_CRG2`!0x81PERI_CRG3A!0xc1ddrc_initñ¬10x11000000Á¬10x22000000`¬10x007c2063a¬!311DDRC_PHYCTRL¬1muxctrl_reg27á«1muxctrl_reg29±«1muxctrl_reg30Ÿ«1muxctrl_reg31Q«1muxctrl_reg32!«1muxctrl_reg33ñª1muxctrl_reg34Áª1muxctrl_reg35`ª1muxctrl_reg36aª1muxctrl_reg371ª1PERIPHCTRL24ª!0x94!8!0x0!0x1!0!1!0x01muxctrl_reg19ñ¨!0x4c!UART11muxctrl_reg20Ÿ¨!0x501muxctrl_reg211¨!0x541muxctrl_reg22á§1muxctrl_reg23±§1muxctrl_reg24Ÿ§1TEMPER_DQQ§1PERI_CRG10!§!0x28!0x0!0!1!21PERI_CRG58Q¦!0xe8!0x7!31!NULL!1000!0x0!10000!0x408!0x01DDRC_PHYSTATUS¥!0x404!0x11DDRC_EMRS01`¤!0x14!0x61b601DDRC_EMRS23!¤!0x18!0x101DDRC_CONFIG0±£!0x1c10x8000C600a£!write1DDRC_CONFIG1£!0x20!0x7851DDRC_TIMING2¡¢!0x581DDRC_CTRLQ¢!0x11DDRC_RNKCFG¢!0x2c!0x1321DDRC_TIMING0`¡!0x501DDRC_TIMING1A¡!0x541DDRC_TIMING3ñ !0x5c1DDRC_BASEADDR¡ !0x40!31!0xf41DDRC_DTRCTRL !0xac10x3000301Á?!0x41DDRC_STATUSq?!0x8!31DDRC_PHY_REG4A?!0x838!0xA01DDRC_PHY_REG2`?!0x808!200000!10!0x1B!0x31ether_sysctrlÁŸ1DDRC_PHY_REG61`Ÿ!0xBE81Module NameAŸ1ddr_commonŸ1Base Addressá?10x20110000±?1PriorityŸ?AExecution Required for Standby WakeupAExecution Required for Normal Bootu1RegisterÑ " " 1Offset Address¡ " " AValue Written to or Read from Register!delay1Read or Write " " A Bits to Be Read or Writtenm RegisteAStart Bit to Be Read or Writtengiste1Register Attributea?!NULL!0!100001DDRC_PHY_REG12Ñtm!0x840!0xcc!311CMD0???01100=46?Atm1DDRC_PHY_REG14tm!0x848!0x0!11DDRC_PHY_REG13Ÿ?!0x844!0xffACMD0 rising/falling slew rate 1111te1DDRC_PHY_REG16Ñ - !0x8541CMD1???01100=46?Ÿ - 1DDRC_PHY_REG18Q - !0x85c1DDRC_PHY_REG17?!0x858ACMD1 rising/falling slew rate 1111te1DDRC_PHY_REG22q-!0x8701CK???01100=46?!-1DDRC_PHY_REG24ñ*!0x8781DDRC_PHY_REG23¡*!0x874ACK rising/falling slew rate 1111ste1DDRC_PHY_REG25*!0x8801DQ???01100=46?Á''1DDRC_PHY_REG28`''!0x88c!41DDRC_PHY_REG26!''!0x884!0x88ADQ rising/falling slew rate 1000ste1DDRC_PHY_REG27q``!0x8881ODT?1011=120!``1DDRC_PHY_REG28ñ'!0x31DDRC_PHY_REG30¡'!0xac4!0x01DDRC_PHY_REG311'!0xac81DDRC_PHY_REG32á`!0xacc1DDRC_PHY_REG33``!0xad01DDRC_PHY_REG34A`!0xad41DDRC_PHY_REG35ñŸ!0xad81DDRC_PHY_REG36¡Ÿ!0xadc1DDRC_PHY_REG37QŸ!0xae01DDRC_PHY_REG38?!0xae41DDRC_PHY_REG39±Ÿ!0xae81DDRC_PHY_REG41aŸ!0xaf01DDRC_PHY_REG42Ÿ!0xaf41DDRC_PHY_REG43Á?!0xaf81DDRC_PHY_REG53q?!0xb201DDRC_PHY_REG40!?!0xaec!0x91DDRC_PHY_REG54±Ÿ!0xb241DDRC_PHY_REG55aŸ!0xb281DDRC_PHY_TXDQSKEWŸ!0xafc!0xb001DDRC_PHY_TXDQSKEW¡?!0xb04!0xb08!0xb0c!0xb10!0xb14!0xb181DDRC_PHY_REG52± " " !0xb1c1DDRC_PHY_RXDQSKEWa " " !0xb2c!0xb30!0xb34!0xb38!0xb3c!0xb401DDRC_PHY_RXDQSKEWq?!0xb44!0xb481DDRC_PHY_REG5E?!0xb4c!0x2!0!11SKT???PWMQo/oo!0x58!0x0!0x5C!UART2!0x601??PHY?????GPIO??Ÿ?1muxctrl_reg26Q?!0x68!0x1!USB0!0x6c1muxctrl_reg28¡?!0x70!USB1!0x74!0x78!0x1!0!HDMI!0x7c!0x80!0x84!0x88!SATA!0x8c!0x90!ETH!0x941muxctrl_reg48q...!0xc01SC_CTRL_SWDQS_TRAINING!...!0xa0q??DQStraining??_sQÿbit[0]ÿ
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N?Oý?o?öNDQStrainingÿÅN?O(ulxöNtrainingÿ
1`'': & lt;
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70x0 7
DDRC_PHY_270xa0470x1f7031
DDRC_PHY_370xac070x557
DDRC_PHY_570x80470x4b7PERIPHCTRL2870xa47?07Ü
$NB\?gM`n?ÿ
[30:28]spi_sclk:8ma 110;
[26:24]aio_ws_tx:4ma 010;
[22:20]aio_bclk_tx:11ma 111;
[18:16]aio_ws_rx:4ma 010;
[14:12]aio_bclk_rx:11ma 111;
[10:8]aio_mclk:11ma 111;
[6:4]vga_hs/vga_vs:8ma 010;
[2:0]vi_adc_clk:11ma 111
7PERIPHCTRL2970xa873172
$NB\?gM`n?ÿ
[6:4]SFC :4ma 010;
[2:0]PAD_SPI_SDO:4ma 010
72ÛVB\?gM`n?ÿ
[6:4]SFC :8ma 110;
[2:0]PAD_SPI_SDO:8ma 1107ÞÛVB\?gM`n?ÿ
[30:28]spi_sclk:11ma 111;
[26:24]aio_ws_tx:4ma 010;
[22:20]aio_bclk_tx:11ma 111;
[18:16]aio_ws_rx:4ma 010;
[14:12]aio_bclk_rx:11ma 111;
[10:8]aio_mclk:11ma 111;
[6:4]vga_hs/vga_vs:12ma 100;
[2:0]vi_adc_clk:11ma 1117
DDRC_PHY_REG870x8e070x2370x8d470xd70x91470xd7
DDRC_PHY_REG67
DDRC_PHY_REG97
0x007c30967
0x6355100B7
0xFF637A317
0x3350E0007
0xFFDFF6f370x937
0x000000227
0x627277277PERIPHCTRL2470x9470x07?07127
DDRC_PHY_170x8307?07
DDRC_PHY_470x81870x407
DDRC_PHY_REG870x8e070x237317DDRC_PHY_REG1170x92070x227
DDRC_PHY_REG670x8d470xc7
DDRC_PHY_REG970x91470xd7
0x00000015·
0x181D0000·0x0000000FD7
0x0000100D7
0x0015000070x0000000FD7
0x000000157
0x181D00007
0x0000000570x070x0000000FD7
0x0000000D7
0x0000200D7
0x000500007
0x0000005570x07
0x100500007
0x180500007
0x000D00007
0x0000000D7
0x000040057
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 " Module Name " , " ddr_common "
" Base Address " , " 0x20110000 "
" Priority " , " 4 "
" Execution Required for Standby Wakeup " , " N "
" Execution Required for Normal Boot " , " Y "
" Register " , " Offset Address " , " Value Written to or Read from Register " , " delay " , " Read or Write " , " Bits to Be Read or Written " , " Start Bit to Be Read or Written " , " Register Attribute "
" NULL " , " 0 " , " 0 " , " 10000 " , " none " , " 0 " , " 0 " , " "
" " , " " , " " , " " , " write " , " " , " " , " " ,
" " , " " , " " , " " , " write " , " " , " " , " " ,
" " , " " , " " , " " , " write " , " " , " " , " " ,
" " , " " , " " , " " , " write " , " " , " " , " " ,
" " , " " , " " , " " , " write " , " " , " " , " " ,
" DDRC_PHY_REG12 " , " 0x840 " , " 0xcc " , " 0 " , " write " , " 31 " , " 0 " , " " , " CMD0???01100=46? "
" DDRC_PHY_REG14 " , " 0x848 " , " 0x0 " , " 0 " , " write " , " 1 " , " 0 " , " " ,
" DDRC_PHY_REG13 " , " 0x844 " , " 0xff " , " 0 " , " write " , " 31 " , " 0 " , " " , " CMD0 rising/falling slew rate 1111 "
" DDRC_PHY_REG16 " , " 0x854 " , " 0xcc " , " 0 " , " write " , " 31 " , " 0 " , " " , " CMD1???01100=46? "
" DDRC_PHY_REG18 " , " 0x85c " , " 0x0 " , " 0 " , " write " , " 1 " , " 0 " , " " ,
" DDRC_PHY_REG17 " , " 0x858 " , " 0xff " , " 0 " , " write " , " 31 " , " 0 " , " " , " CMD1 rising/falling slew rate 1111 "
" DDRC_PHY_REG22 " , " 0x870 " , " 0xcc " , " 0 " , " write " , " 31 " , " 0 " , " " , " CK???01100=46? "
" DDRC_PHY_REG24 " , " 0x878 " , " 0x0 " , " 0 " , " write " , " 1 " , " 0 " , " " ,
" DDRC_PHY_REG23 " , " 0x874 " , " 0xff " , " 0 " , " write " , " 31 " , " 0 " , " " , " CK rising/falling slew rate 1111 "
" DDRC_PHY_REG25 " , " 0x880 " , " 0xcc " , " 0 " , " write " , " 31 " , " 0 " , " " , " DQ???01100=46? "
" DDRC_PHY_REG28 " , " 0x88c " , " 0x0 " , " 0 " , " write " , " 1 " , " 4 " , " " ,
" DDRC_PHY_REG26 " , " 0x884 " , " 0x88 " , " 0 " , " write " , " 31 " , " 0 " , " " , " DQ rising/falling slew rate 1000 "
" DDRC_PHY_REG27 " , " 0x888 " , " 0x1B " , " 0 " , " write " , " 31 " , " 0 " , " " , " ODT?1011=120 "
" DDRC_PHY_REG28 " , " 0x88c " , " 0x3 " , " 0 " , " write " , " 1 " , " 0 " , " " ,
" DDRC_PHY_REG30 " , " 0xac4 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG31 " , " 0xac8 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG32 " , " 0xacc " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG33 " , " 0xad0 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG34 " , " 0xad4 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG35 " , " 0xad8 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG36 " , " 0xadc " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG37 " , " 0xae0 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG38 " , " 0xae4 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG39 " , " 0xae8 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG41 " , " 0xaf0 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG42 " , " 0xaf4 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG43 " , " 0xaf8 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG53 " , " 0xb20 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG40 " , " 0xaec " , " 0x9 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG54 " , " 0xb24 " , " 0x9 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG55 " , " 0xb28 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_TXDQSKEW " , " 0xafc " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_TXDQSKEW " , " 0xb00 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_TXDQSKEW " , " 0xb04 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_TXDQSKEW " , " 0xb08 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_TXDQSKEW " , " 0xb0c " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_TXDQSKEW " , " 0xb10 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_TXDQSKEW " , " 0xb14 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_TXDQSKEW " , " 0xb18 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG52 " , " 0xb1c " , " 0x8 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_RXDQSKEW " , " 0xb2c " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_RXDQSKEW " , " 0xb30 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_RXDQSKEW " , " 0xb34 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_RXDQSKEW " , " 0xb38 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_RXDQSKEW " , " 0xb3c " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_RXDQSKEW " , " 0xb40 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_RXDQSKEW " , " 0xb44 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_RXDQSKEW " , " 0xb48 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG5E " , " 0xb4c " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" " , " " , " " , " 0 " , " write " , " 31 " , " 0 " , " "
" " , " " , " " , " 0 " , " write " , " 31 " , " 0 " , " "
" " , " " , " " , " 0 " , " write " , " 31 " , " 0 " , " "
" " , " " , " " , " " , " write " , " " , " " , " "
" " , " " , " " , " " , " write " , " " , " " , " "
" " , " " , " " , " " , " write " , " " , " " , " "
" " , " " , " " , " " , " write " , " " , " " , " "
 " Module Name " , " ddrc_init "
" Base Address " , " 0x20110000 "
" Priority " , " 5 "
" Execution Required for Standby Wakeup " , " N "
" Execution Required for Normal Boot " , " Y "
" Register " , " Offset Address " , " Value Written to or Read from Register " , " delay " , " Read or Write " , " Bits to Be Read or Written " , " Start Bit to Be Read or Written " , " Register Attribute "
" NULL " , " 0 " , " 0 " , " 10000 " , " none " , " 0 " , " 0 " , " "
" DDRC_PHYCTRL " , " 0x408 " , " 0x0 " , " 1000 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHYSTATUS " , " 0x404 " , " 0x1 " , " 0 " , " read " , " 0 " , " 0 " , " "
" DDRC_EMRS01 " , " 0x14 " , " 0x61b60 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_EMRS23 " , " 0x18 " , " 0x10 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_CONFIG0 " , " 0x1c " , " 0x8000C600 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_CONFIG1 " , " 0x20 " , " 0x785 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_TIMING2 " , " 0x58 " , " 0x0 " , " 0 " , " write " , " 10 " , " 0 " , " "
" DDRC_CTRL " , " 0x10 " , " 0x1 " , " 0 " , " write " , " 31 " , " 0 " , " "
" NULL " , " 0 " , " 0 " , " 200000 " , " none " , " 0 " , " 0 " , " "
" DDRC_RNKCFG " , " 0x2c " , " 0x132 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_TIMING0 " , " 0x50 " , " " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_TIMING1 " , " 0x54 " , " " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_TIMING2 " , " 0x58 " , " " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_TIMING3 " , " 0x5c " , " " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_BASEADDR " , " 0x40 " , " 0x80000000 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_ODTCFG " , " 0xf4 " , " 0x1 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_DTRCTRL " , " 0xac " , " 0x3000301 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_SREFCTRL " , " 0x4 " , " 0 " , " 1000 " , " write " , " 31 " , " 0 " , " "
" DDRC_STATUS " , " 0x0 " , " 0x0 " , " 0 " , " read " , " 0 " , " 2 " , " "
" DDRC_INITCTRL " , " 0x8 " , " 0x1 " , " 1000 " , " write " , " 0 " , " 0 " , " "
" DDRC_STATUS " , " 0x0 " , " 0x0 " , " 0 " , " read " , " 0 " , " 3 " , " "
" DDRC_PHY_REG4A " , " 0x838 " , " 0xA0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG2 " , " 0x808 " , " 0x1 " , " 1000 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG61 " , " 0xBE8 " , " 0x3 " , " 0 " , " read " , " 1 " , " 0 " , " "
" DDRC_PHY_REG2 " , " 0x808 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_TIMING2 " , " 0x58 " , " " , " 0 " , " write " , " 10 " , " 0 " , " "
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 " Module Name " , " standby_pin_ctrl "
" Base Address " , " 0x200f0000 "
" Priority " , " 6 "
" Execution Required for Standby Wakeup " , " N "
" Execution Required for Normal Boot " , " Y "
" Register " , " Offset Address " , " Value Written to or Read from Register " , " delay " , " Read or Write " , " Bits to Be Read or Written " , " Start Bit to Be Read or Written " , " Register Attribute "
" muxctrl_reg19 " , " 0x4c " , " 0x0 " , " 0 " , " write " , " 0 " , " 0 " , " " , " UART1 "
" muxctrl_reg20 " , " 0x50 " , " 0x0 " , " 0 " , " write " , " 0 " , " 0 " , " " ,
" muxctrl_reg21 " , " 0x54 " , " 0x2 " , " 0 " , " write " , " 1 " , " 0 " , " " ,, " SKT???PWM "
" muxctrl_reg22 " , " 0x58 " , " 0x0 " , " 0 " , " write " , " 0 " , " 0 " , " " ,
" muxctrl_reg23 " , " 0x5C " , " 0x0 " , " 0 " , " write " , " 0 " , " 0 " , " " , " UART2 "
" muxctrl_reg24 " , " 0x60 " , " 0x0 " , " 0 " , " write " , " 0 " , " 0 " , " " ,, " ??PHY?????GPIO?? "
" muxctrl_reg26 " , " 0x68 " , " 0x1 " , " 0 " , " write " , " 0 " , " 0 " , " " , " USB0 "
" muxctrl_reg27 " , " 0x6c " , " 0x1 " , " 0 " , " write " , " 0 " , " 0 " , " " ,
" muxctrl_reg28 " , " 0x70 " , " 0x1 " , " 0 " , " write " , " 0 " , " 0 " , " " , " USB1 "
" muxctrl_reg29 " , " 0x74 " , " 0x1 " , " 0 " , " write " , " 0 " , " 0 " , " " ,
" muxctrl_reg30 " , " 0x78 " , " 0x1 " , " 0 " , " write " , " 0 " , " 0 " , " " , " HDMI "
" muxctrl_reg31 " , " 0x7c " , " 0x1 " , " 0 " , " write " , " 0 " , " 0 " , " " ,
" muxctrl_reg32 " , " 0x80 " , " 0x1 " , " 0 " , " write " , " 0 " , " 0 " , " " ,
" muxctrl_reg33 " , " 0x84 " , " 0x1 " , " 0 " , " write " , " 0 " , " 0 " , " " ,
" muxctrl_reg34 " , " 0x88 " , " 0x1 " , " 0 " , " write " , " 0 " , " 0 " , " " , " SATA "
" muxctrl_reg35 " , " 0x8c " , " 0x1 " , " 0 " , " write " , " 0 " , " 0 " , " " ,
" muxctrl_reg36 " , " 0x90 " , " 0x1 " , " 0 " , " write " , " 0 " , " 0 " , " " , " ETH "
" muxctrl_reg37 " , " 0x94 " , " 0x1 " , " 0 " , " write " , " 0 " , " 0 " , " " ,
" muxctrl_reg48 " , " 0xc0 " , " 0x1 " , " 0 " , " write " , " 0 " , " 0 " , " " , " TEMPER_DQ "
 " Module Name " , " ether_sysctrl "
" Base Address " , " 0x20050000 "
" Priority " , " 7 "
" Execution Required for Standby Wakeup " , " N "
" Execution Required for Normal Boot " , " Y "
" Register " , " Offset Address " , " Value Written to or Read from Register " , " delay " , " Read or Write " , " Bits to Be Read or Written " , " Start Bit to Be Read or Written " , " Register Attribute "
" PERIPHCTRL24 " , " 0x94 " , " 0x0 " , " 0 " , " write " , " 0 " , " 8 " , " "
" " , " " , " " , " " , " write " , " " , " " , " "
" " , " " , " " , " 0 " , " write " , " 31 " , " 0 " , " " , " " , " "
" " , " " , " " , " " , " write " , " " , " " , " " , " " , " "
,,,,,,,
,,,,,,,
,,,,,,,
 " nand flash " ,,,,,,,, " spi flash " ,,,,,,,, " emmc flash " ,,,,,,
" name " , " ID " , " chip size " , " erase size " , " page size " , " oob size " , " ecc type " ,, " name " , " jedec_id " , " ext_id " , " block_size " , " chip_size " , " clk " , " chip select "
" MT29F16G08CBABx-4K-24bit1K " , " 0x2C 0x48 0x04 0x46 0x85 0x00 0x00 0x00 " , " 2GB " , " 1MB " , " 4KB " , " 224B " , " 4 " ,, " mx25l1655d " , " 0xc2 0x26 0x15 " , " 0x0 " , " 65536 " , " 2097152 " , " 0x40100 " , " 1 "
" NAND01GW3B2CN6 " , " 0x20 0xF1 0x00 0x1D 0x20 0xF1 0x00 0x1D " , " 128MB " , " 128KB " , " 2KB " , " 64B " , " 1 " ,, " w25x16 " , " 0xef 0x30 0x15 " , " 0x0 " , " 65536 " , " 2097152 " , " 0x40100 " , " 1 "
" K9F1G0bU0C " , " 0xEC 0xF1 0x00 0x95 0x40 0x00 0xEC 0xF1 " , " 128MB " , " 128KB " , " 2KB " , " 64B " , " 1 " ,, " s25sl032a " , " 0x01 0x02 0x15 " , " 0x0 " , " 65536 " , " 4194304 " , " 0x40100 " , " 1 "
" K9F2G08U0B " , " 0xEC 0xDA 0x10 0x95 0x44 0xEC 0xEC 0xDA " , " 256MB " , " 128KB " , " 2KB " , " 64B " , " 1 " ,, " s25sl064a " , " 0x01 0x02 0x16 " , " 0x0 " , " 65536 " , " 8388608 " , " 0x40100 " , " 1 "
" HY27UF082G2B " , " 0xAD 0xDA 0x10 0x95 0x44 0xAD 0xDA 0x10 " , " 256MB " , " 128KB " , " 2KB " , " 64B " , " 1 " ,, " s25sl12800 " , " 0x01 0x20 0x18 " , " 0x03 0x00 " , " 262144 " , " 16777216 " , " 0x60100 " , " 1 "
" K9F4G08U0B " , " 0xEC 0xDC 0x10 0x95 0x54 0xEC 0xEC 0xDC " , " 512MB " , " 128KB " , " 2KB " , " 64B " , " 1 " ,, " m25px16 " , " 0x20 0x71 0x15 " , " 0x0 " , " 65536 " , " 2097152 " , " 0x40100 " , " 1 "
" HY27UF084G2B " , " 0xAD 0xDC 0x10 0x95 0x54 0xAD 0xDC 0x10 " , " 512MB " , " 128KB " , " 2KB " , " 64B " , " 1 " ,, " m25px32 " , " 0x20 0x71 0x16 " , " 0x0 " , " 65536 " , " 4194304 " , " 0x40100 " , " 1 "
" 29F4G08ABADA " , " 0x2C 0xDC 0x90 0x95 0x56 0x00 0x00 0x00 " , " 512MB " , " 128KB " , " 2KB " , " 64B " , " 1 " ,, " m25px64 " , " 0x20 0x71 0x17 " , " 0x0 " , " 65536 " , " 8388608 " , " 0x40100 " , " 1 "
" 29F1G08ABADA " , " 0x2C 0xF1 0x80 0x95 0x02 0x00 0x00 0x00 " , " 128MB " , " 128KB " , " 2KB " , " 64B " , " 1 " ,, " m25p32 " , " 0x20 0x20 0x16 " , " 0x0 " , " 65536 " , " 4194304 " , " 0x40100 " , " 1 "
" HY27UF081G2A " , " 0xAD 0xF1 0x80 0x1D 0xAD 0xF1 0x80 0x1D " , " 128MB " , " 128KB " , " 2KB " , " 64B " , " 1 " ,, " m25p128 " , " 0x20 0x20 0x18 " , " 0x0 " , " 262144 " , " 16777216 " , " 0x40100 " , " 1 "


uboot_tools.zip > uboot-Hi3520D-bvt_No1_660_330_660_ddr_innerFEPHY.xls

,,,,
, " Boot V1.0 " ,,
, " Hisilicon Technologies Co., Ltd. All rights reserved. @2012 " ,,
,,,,,,,,
" Basic Project Information " ,,,,
,,,,
" Project Name " , " xxx " ,, " Project Version " , " 1.0 "
" Project Start Time " , " 40543 " ,, " Development " , " xxx "
" Product Line " , " Media " ,, " Department " , " Media "
" Project Description " , " Project description " ,,,
 " Module Name " , " slow "
" Base Address " , " 0x20050000 "
" Priority " , " 1 "
" Execution Required for Standby Wakeup " , " N "
" Execution Required for Normal Boot " , " Y "
" Register " , " Offset Address " , " Value Written to or Read from Register " , " delay " , " Read or Write " , " Bits to Be Read or Written " , " Start Bit to Be Read or Written " , " Register Attribute "
" SC_CTRL " , " 0 " , " 0x2 " , " 0 " , " write " , " 2 " , " 0 " , " "
" SC_CTRL " , " 0 " , " 0x2 " , " 0 " , " read " , " 3 " , " 3 " , " "
,,,,,,,
,,,,,,,
,,,,,,,
 " Module Name " , " pll "
" Base Address " , " 0x20030000 "
" Priority " , " 2 "
" Execution Required for Standby Wakeup " , " N "
" Execution Required for Normal Boot " , " Y " ,,,,,,
" Register " , " Offset Address " , " Value Written to or Read from Register " , " delay " , " Read or Write " , " Bits to Be Read or Written " , " Start Bit to Be Read or Written " , " Register Attribute "
" PERI_CRG0 " , " 0x0 " , " 0x11000000 " , " 0 " , " write " , " 31 " , " 0 " , " "
" PERI_CRG1 " , " 0x4 " , " 0x007c30a5 " , " 0 " , " write " , " 31 " , " 0 " , " "
" PERI_CRG2 " , " 0x8 " , " 0x22000000 " , " 0 " , " write " , " 31 " , " 0 " , " "
" PERI_CRG3 " , " 0xc " , " 0x007c2063 " , " 0 " , " write " , " 31 " , " 0 " , " "
" PERI_CRG10 " , " 0x28 " , " 0x0 " , " 0 " , " write " , " 1 " , " 2 " , " "
" PERI_CRG58 " , " 0xe8 " , " 0x7 " , " 0 " , " read " , " 2 " , " 0 " , " "
,,,,,,,
,,,,,,,
,,,,,,,
,,,,,,,
,,,,,,,
 " Module Name " , " normal "
" Base Address " , " 0x20050000 "
" Priority " , " 3 "
" Execution Required for Standby Wakeup " , " N "
" Execution Required for Normal Boot " , " Y "
" Register " , " Offset Address " , " Value Written to or Read from Register " , " delay " , " Read or Write " , " Bits to Be Read or Written " , " Start Bit to Be Read or Written " , " Register Attribute "
" SC_PLLCTRL " , " 0x14 " , " 0x0fff8000 " , " 0 " , " write " , " 31 " , " 0 " , " "
" SC_CTRL " , " 0 " , " 0x4 " , " 0 " , " write " , " 2 " , " 0 " , " "
" SC_CTRL " , " 0 " , " 0x4 " , " 0 " , " read " , " 3 " , " 3 " , " "
" SC_CTRL_SWDQS_TRAINING " , " 0xa0 " , "  & lt;
=B
70x0 7
DDRC_PHY_270xa0470x1f7031
DDRC_PHY_370xac070x557
DDRC_PHY_570x80470x4b7PERIPHCTRL2870xa47?07PERIPHCTRL2970xa873172
$NB\?gM`n?ÿ
[6:4]SFC :4ma 010;
[2:0]PAD_SPI_SDO:4ma 010
72ÛVB\?gM`n?ÿ
[6:4]SFC :8ma 110;
[2:0]PAD_SPI_SDO:8ma 1107Ü
$NB\?gM`n?ÿ
[30:28]spi_sclk:8ma 110;
[26:24]aio_ws_tx:4ma 010;
[22:20]aio_bclk_tx:11ma 111;
[18:16]aio_ws_rx:4ma 010;
[14:12]aio_bclk_rx:11ma 111;
[10:8]aio_mclk:11ma 111;
[6:4]vga_hs/vga_vs:8ma 010;
[2:0]vi_adc_clk:11ma 111
7
0x627277277
0x0000002270x947127ÞÛVB\?gM`n?ÿ
[30:28]spi_sclk:11ma 111;
[26:24]aio_ws_tx:4ma 010;
[22:20]aio_bclk_tx:11ma 111;
[18:16]aio_ws_rx:4ma 010;
[14:12]aio_bclk_rx:11ma 111;
[10:8]aio_mclk:11ma 111;
[6:4]vga_hs/vga_vs:12ma 100;
[2:0]vi_adc_clk:11ma 1117
DDRC_PHY_170x8307?07
DDRC_PHY_470x81870x4070x87?07317
DDRC_PHY_REG870x8e070x237?07317DDRC_PHY_REG1170x92070x227
DDRC_PHY_REG670x8d470xc7
DDRC_PHY_REG970x91470xd7
0x00000015·
0x181D0000·0x0000000FD7
0x0000100D7
0x0015000070x0000000FD7
0x000000157
0x181D00007
0x0000000570x070x0000000FD7
0x0000000D7
0x0000200D70x0000000FD7
0x000500007
0x0000005570x07
0x100500007
0x180500007
0x000D00007
0x0000000D7
0x000040057
0x0000600570x917¡À ¦ðf§g§0g§`g§?g§°g§àg§h§Ph§Ÿh§Àh§ðh§0i§Pi§?i§Ài§j§0j§Pj§°j§ðj§ k§Pk§?k§°k§àk§l§@l§`l§?l§°l§àl§m§@m§`m§?m§°m§àm§n§@n§pn§ n§Àn§ðn§ o§@o§po§Ÿo§°o§Ðo§ðo§p§0p§Pp§?p§ p§Ðp§ðp§q§@q§`q§?q§ q§Ðq§ðq§r§0r§`r§Ÿr§Àr§ðr§s§@s§ps§ s§Ðs§t§0t§Pt§pt§Ÿt§Ðt§u§0u§`u§Ÿu§Àu§ðu§ v§Pv§?v§Àv§w§@w§?w§Àw§x§@x§?x§Àx§y§ y§@y§`y§?y§ y§Ày§ày§z§ z§@z§`z§?z§ z§Àz§àz§{§0{§P{§?{§°{§à{§|§ |§@|§`|§?|§°|§à|§}§@}§p}§ }§Ð}§~§0~§`~§Ÿ~§°~§Ð~§ð~§?§@?§p?§°?§ð?§ ?§P?§Ÿ?§À?§Ÿ§@Ÿ§?Ÿ§°Ÿ§àŸ§'§0'§P'§?'§°'§à'§?§0?§`?§Ÿ?§À?§ð?§ ''§P''§?''§°''§à''§...§@...§p...§ ...§À...§à...§?§0?§`?§Ÿ?§À?§à?§?§ ?§@?§p?§Ÿ?§°?§à?§?§0?§P?§??§°?§à?§o/oo§@o/oo§`o/oo§?o/oo§ o/oo§Ào/oo§ào/oo§?§0?§P?§p?§Ÿ?§°?§Ð?§ð?§ " " §0 " " §` " " §? " " §  " " §Ð " " §ð " " §?§@?§`?§??§°?§Ð?§Ÿ§ Ÿ§PŸ§pŸ§ŸŸ§ÀŸ§àŸ§?§0?§`?§??§ ?§Ð?§ð?§ Ÿ§@Ÿ§pŸ§ŸŸ§ÀŸ§àŸ§Ÿ§ Ÿ§PŸ§pŸ§ Ÿ§ÀŸ§ðŸ§`§0`§``§?`§ `§Ð`§ð`§'§0'§P'§p'§Ÿ'§À'§ð'§``§@``§p``§ ``§Ð``§''§@''§?''§°''§à''§ *§@*§p*§°*§ð*§ -§@-§`-§?-§°-§Ð-§ð-§ - §@ - §p - §Ÿ - §° - §Ð - §?§ ?§@?§??§°?§Ð?§tm§0tm§Ptm§?tm§ tm§àtm§?§0?§`?§Ÿ?§°?§à?§ " " §@ " " §p " " §Ÿ " " §À " " §ð " " §?§0?§`?§??§ ?§à?§Ÿ§0Ÿ§`Ÿ§ŸŸ§°Ÿ§àŸ§?§ ?§P?§p?§ ?§À?§ð?§?§@?§`?§Ÿ?§°?§à?§ §0 §P §? §  §Ð §ð § ¡§@¡§p¡§Ÿ¡§À¡§à¡§¢§0¢§`¢§?¢§ ¢§Ð¢§ð¢§ £§@£§p£§Ÿ£§°£§à£§¤§ ¤§@¤§`¤§?¤§ ¤§Ð¤§ð¤§ ¥§@¥§`¥§?¥§ ¥§À¥§à¥§¦§0¦§P¦§?¦§ ¦§À¦§à¦§§§0§§P§§p§§Ÿ§§°§§Ð§§¨§0¨§P¨§p¨§Ÿ¨§°¨§à¨§©§ ©§@©§`©§?©§ ©§À©§à©§ª§ ª§@ª§`ª§?ª§ ª§Àª§àª§«§0«§`«§?«§!cp1252xt1¸Nchû?¸Nchû?g slew rate 1000

 
 ! " " #$% & '()*+,-./0123456789:; & lt; = & gt; ?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~?¬  '''...???o/oo? " " ?}   " "   Ü " " !a " " ?~? ¡¢£¤¥¦§¨©ª«¬®¯°±²³´µ¶·¸¹º»¼½¾¿ÀÁÂÃÄÅÆÇÈÉÊËÌÍÎÏÐÑÒÓÔÕÖ×ØÙÚÛÜÝÞßàáâãäåæçèéêëìíîïðñòóôõö÷øùúûüýþÿ!xxxxt!1.01Boot V1.0ÁÈ!Y1Module NameqÈÿÿÿÿÿÿÿÿ1Base AddressAÈÿÿÿÿ1Priority%chû?ÈAExecution Required for Standby WakeupAExecution Required for Normal Bootu1RegisteraÇ1Offset Address1ÇAValue Written to or Read from Register!delay " " chû?1Read or Write¡ÆA Bits to Be Read or Writtenm RegisteAStart Bit to Be Read or Writtengiste1Register AttributeñÅ!writeaHisilicon Technologies Co., Ltd. All rights reserved. @2012qÅABasic Project Informationitteegiste1Project NameÅ1Project Start TimeÑÄ1Product Line¡Ä1Project DescriptionqÄ1Project VersionAÄ1DevelopmentÄ1DepartmentáÃ!Media!Media1Project descriptionqÃ1nand flashAÃ1spi flashÃ1emmc flasháÂ!name!ID1chip sizeqÂ1erase sizeAÂ1page sizeÂ1oob sizeáÁ1ecc type±Á1jedec_idŸÁ!ext_id1block_size1Á1chip_sizeÁ!clk1chip select±À!SC_CTRL!0!0x2!2!0x2!3!slow10x20050000¡¿!N1PERI_CRG0Q¿!0x0!311PERI_CRG1á¾!0x4!0x14!pll10x20030000Q¾!N!N!normal10x20050000Á½1SC_PLLCTRL`½10x0fff8000a½10x201100001½!Y1DDRC_SREFCTRLá¼10x80000000±¼1DDRC_ODTCFGŸ¼1DDRC_INITCTRLQ¼1standby_pin_ctrl!¼10x200f0000ñ»!0!read!noneAMT29F16G08CBABx-4K-24bit1Ktteegiste1NAND01GW3B2CN6!»1K9F1G0bU0Cñº1K9F2G08U0BÁº1HY27UF082G2B`º1K9F4G08U0Baº1HY27UF084G2B1º129F4G08ABADAº129F1G08ABADAѹ1HY27UF081G2A¡¹A0x2C 0x48 0x04 0x46 0x85 0x00 0x00 0x00A0x20 0xF1 0x00 0x1D 0x20 0xF1 0x00 0x1DA0xEC 0xF1 0x00 0x95 0x40 0x00 0xEC 0xF1A0xEC 0xDA 0x10 0x95 0x44 0xEC 0xEC 0xDAA0xAD 0xDA 0x10 0x95 0x44 0xAD 0xDA 0x10A0xEC 0xDC 0x10 0x95 0x54 0xEC 0xEC 0xDCA0xAD 0xDC 0x10 0x95 0x54 0xAD 0xDC 0x10A0x2C 0xDC 0x90 0x95 0x56 0x00 0x00 0x00A0x2C 0xF1 0x80 0x95 0x02 0x00 0x00 0x00A0xAD 0xF1 0x80 0x1D 0xAD 0xF1 0x80 0x1D!2GB!128MB!256MB!512MB!1MB!128KB!128KB!4KB!2KB!2KB!2KB!2KB!224B!64B!64B!64B1mx25l1655dñ´!w25x161s25sl032a¡´1s25sl064aq´1s25sl12800A´!m25px16!m25px32!m25px64!m25p32!m25p12810xc2 0x26 0x15q³10xef 0x30 0x15A³10x01 0x02 0x15³10x01 0x02 0x16á²10x01 0x20 0x18±²10x20 0x71 0x15Ÿ²10x20 0x71 0x16Q²10x20 0x71 0x17!²10x20 0x20 0x16ñ±10x20 0x20 0x18Á±10x03 0x00`±!0x0!0x0!0x40100!0x601001Module Nameá°1Priority±°AExecution Required for Standby WakeupAExecution Required for Normal Bootu11Register°1Offset AddressѯAValue Written to or Read from Register1Read or Writea¯AStart Bit to Be Read or WrittengisteA Bits to Be Read or WrittenteegisteA Bits to Be Read or Writtenteegiste1Register Attributeq®1PERI_CRG2A®!0x81PERI_CRG3ñ!0xc1ddrc_init¡10x11000000q10x22000000A10x007c2063!311DDRC_PHYCTRLÁ¬10xffdff6f3`¬1muxctrl_reg27a¬1muxctrl_reg291¬1muxctrl_reg30¬1muxctrl_reg31Ñ«1muxctrl_reg32¡«1muxctrl_reg33q«1muxctrl_reg34A«1muxctrl_reg35«1muxctrl_reg36áª1muxctrl_reg37±ª1PERIPHCTRL24Ÿª!0x94!8!0x010x007c30a5ñ©10x4350f000Á©10x6355110C`©10xFF637A35a©!0x1!0!1!0x01muxctrl_reg19±¨!0x4c!UART11muxctrl_reg20A¨!0x501muxctrl_reg21ñ§!0x541muxctrl_reg22¡§1muxctrl_reg23q§1muxctrl_reg24A§1TEMPER_DQ§1PERI_CRG10á¦!0x28!0x0!0!1!21PERI_CRG58¦!0xe8!0x7!31!NULL!1000!0x0!10000!0x408!0x01DDRC_PHYSTATUSÁ¤!0x404!0x11DDRC_EMRS01Q¤!0x14!0x61b601DDRC_EMRS23á£!0x18!0x101DDRC_CONFIG0q£!0x1c10x8000C600!£!write1DDRC_CONFIG1Ñ¢!0x20!0x7851DDRC_TIMING2a¢!0x581DDRC_CTRL¢!0x11DDRC_RNKCFGÁ¡!0x2c!0x1321DDRC_TIMING0Q¡!0x501DDRC_TIMING1¡!0x541DDRC_TIMING3± !0x5c1DDRC_BASEADDRa !0x40!31!0xf41DDRC_DTRCTRLÑ?!0xac10x3000301Ÿ?!0x41DDRC_STATUS1?!0x8!31DDRC_PHY_REG4AÁ?!0x838!0xA01DDRC_PHY_REG2Q?!0x808!200000!10!0xA1!0x1B!0x31ether_sysctrlaŸ1DDRC_PHY_REG611Ÿ!0xBE81Module Nameá?1ddr_common±?1Base AddressŸ?10x20110000Q?1Priority!?AExecution Required for Standby WakeupAExecution Required for Normal Bootu1Registerq " " 1Offset AddressA " " AValue Written to or Read from Register!delay1Read or Write±?A Bits to Be Read or Writtenm RegisteAStart Bit to Be Read or Writtengiste1Register Attribute?!NULL!0!100001DDRC_PHY_REG12qtm!0x840!0xcc!311CMD0???01100=46?á?1DDRC_PHY_REG14±?!0x848!0x0!11DDRC_PHY_REG13!?!0x844!0xffACMD0 rising/falling slew rate 1111te1DDRC_PHY_REG16q - !0x8541CMD1???01100=46?! - 1DDRC_PHY_REG18ñ-!0x85c1DDRC_PHY_REG17¡-!0x858ACMD1 rising/falling slew rate 1111te1DDRC_PHY_REG22-!0x8701CK???01100=46?Á*1DDRC_PHY_REG24`*!0x8781DDRC_PHY_REG23A*!0x874ACK rising/falling slew rate 1111ste1DDRC_PHY_REG25±''!0x8801DQ???01100=46?a''1DDRC_PHY_REG281''!0x88c!41DDRC_PHY_REG26Á``!0x884!0x88ADQ rising/falling slew rate 1000ste1DDRC_PHY_REG27``!0x8881ODT?1011=120Á'1DDRC_PHY_REG28`'!0x31DDRC_PHY_REG30A'!0xac4!0x01DDRC_PHY_REG31Ñ`!0xac81DDRC_PHY_REG32Ÿ`!0xacc1DDRC_PHY_REG331`!0xad01DDRC_PHY_REG34áŸ!0xad41DDRC_PHY_REG35`Ÿ!0xad81DDRC_PHY_REG36AŸ!0xadc1DDRC_PHY_REG37ñŸ!0xae01DDRC_PHY_REG38¡Ÿ!0xae41DDRC_PHY_REG39QŸ!0xae81DDRC_PHY_REG41?!0xaf01DDRC_PHY_REG42±?!0xaf41DDRC_PHY_REG43a?!0xaf81DDRC_PHY_REG53?!0xb201DDRC_PHY_REG40ÁŸ!0xaec!0x91DDRC_PHY_REG54QŸ!0xb241DDRC_PHY_REG55?!0xb281DDRC_PHY_TXDQSKEW±?!0xafc!0xb001DDRC_PHY_TXDQSKEWA?!0xb04!0xb08!0xb0c!0xb10!0xb14!0xb181DDRC_PHY_REG52Q " " !0xb1c1DDRC_PHY_RXDQSKEW?!0xb2c!0xb30!0xb34!0xb38!0xb3c!0xb401DDRC_PHY_RXDQSKEW?!0xb44!0xb481DDRC_PHY_REG5E¡o/oo!0xb4c!0x2!0!11SKT???PWMñ?!0x58!0x0!0x5C!UART2!0x601??PHY?????GPIO??!?1muxctrl_reg26ñ?!0x68!0x1!USB0!0x6c1muxctrl_reg28A?!0x70!USB1!0x74!0x78!0x1!0!HDMI!0x7c!0x80!0x84!0x88!SATA!0x8c!0x90!ETH!0x941muxctrl_reg48...!0xc01SC_CTRL_SWDQS_TRAININGÁ''!0xa0q??DQStraining??_sQÿbit[0]ÿ
0ÿ
N?Oý?o?öNDQStrainingÿÅN?O(ulxöNtrainingÿ
11'': & lt;
=B
70x0 7
DDRC_PHY_270xa0470x1f7031
DDRC_PHY_370xac070x557
DDRC_PHY_570x80470x4b7PERIPHCTRL2870xa47?07PERIPHCTRL2970xa873172
$NB\?gM`n?ÿ
[6:4]SFC :4ma 010;
[2:0]PAD_SPI_SDO:4ma 010
72ÛVB\?gM`n?ÿ
[6:4]SFC :8ma 110;
[2:0]PAD_SPI_SDO:8ma 1107Ü
$NB\?gM`n?ÿ
[30:28]spi_sclk:8ma 110;
[26:24]aio_ws_tx:4ma 010;
[22:20]aio_bclk_tx:11ma 111;
[18:16]aio_ws_rx:4ma 010;
[14:12]aio_bclk_rx:11ma 111;
[10:8]aio_mclk:11ma 111;
[6:4]vga_hs/vga_vs:8ma 010;
[2:0]vi_adc_clk:11ma 111
7
0x627277277
0x0000002270x947127ÞÛVB\?gM`n?ÿ
[30:28]spi_sclk:11ma 111;
[26:24]aio_ws_tx:4ma 010;
[22:20]aio_bclk_tx:11ma 111;
[18:16]aio_ws_rx:4ma 010;
[14:12]aio_bclk_rx:11ma 111;
[10:8]aio_mclk:11ma 111;
[6:4]vga_hs/vga_vs:12ma 100;
[2:0]vi_adc_clk:11ma 1117
DDRC_PHY_170x8307?07
DDRC_PHY_470x81870x4070x87?07317
DDRC_PHY_REG870x8e070x237?07317DDRC_PHY_REG1170x92070x227
DDRC_PHY_REG670x8d470xc7
DDRC_PHY_REG970x91470xd7
0x00000015·
0x181D0000·0x0000000FD7
0x0000100D7
0x0015000070x0000000FD7
0x000000157
0x181D00007
0x0000000570x070x0000000FD7
0x0000000D7
0x0000200D70x0000000FD7
0x000500007
0x0000005570x07
0x100500007
0x180500007
0x000D00007
0x0000000D7
0x000040057
0x0000600570x917¡À ¦ðf§g§0g§`g§?g§°g§àg§h§Ph§?h§Àh§ðh§0i§Pi§?i§Ài§j§0j§Pj§°j§ðj§ k§Pk§?k§°k§àk§l§@l§`l§?l§°l§àl§m§@m§`m§?m§°m§àm§n§@n§pn§ n§Àn§ðn§ o§@o§po§?o§°o§Ðo§ðo§p§0p§Pp§?p§ p§Ðp§ðp§q§@q§`q§?q§ q§Ðq§ðq§r§0r§`r§?r§Àr§ðr§s§@s§ps§ s§Ðs§t§0t§Pt§pt§?t§Ðt§u§0u§`u§?u§Àu§ðu§ v§Pv§?v§Àv§w§@w§?w§Àw§x§@x§?x§Àx§y§ y§@y§`y§?y§ y§Ày§ày§z§ z§@z§`z§?z§ z§Àz§àz§{§0{§P{§?{§°{§à{§|§ |§@|§`|§?|§°|§à|§}§@}§p}§ }§Ð}§~§0~§`~§?~§°~§Ð~§ð~§?§@?§p?§°?§ð?§ ?§P?§??§À?§?§@?§??§°?§à?§'§0'§P'§?'§°'§à'§?§0?§`?§??§À?§ð?§ ''§P''§?''§°''§à''§...§@...§p...§ ...§À...§à...§?§0?§`?§??§À?§à?§?§ ?§@?§p?§??§°?§à?§?§0?§P?§??§°?§à?§o/oo§@o/oo§`o/oo§?o/oo§ o/oo§Ào/oo§ào/oo§?§0?§P?§p?§??§°?§Ð?§ð?§ " " §0 " " §` " " §? " " §  " " §Ð " " §ð " " §?§@?§`?§??§°?§Ð?§?§ ?§P?§p?§??§À?§à?§?§0?§`?§??§ ?§Ð?§ð?§ ?§@?§p?§??§À?§à?§?§ ?§P?§p?§ ?§À?§ð?§`§0`§``§?`§ `§Ð`§ð`§'§0'§P'§p'§?'§À'§ð'§``§@``§p``§ ``§Ð``§''§@''§?''§°''§à''§ *§@*§p*§°*§ð*§ -§@-§`-§?-§°-§Ð-§ð-§ - §@ - §p - §? - §° - §Ð - §?§ ?§@?§??§°?§Ð?§tm§0tm§Ptm§?tm§ tm§àtm§?§0?§`?§??§°?§à?§ " " §@ " " §p " " §? " " §À " " §ð " " §?§0?§`?§??§ ?§à?§?§0?§`?§??§°?§à?§?§ ?§P?§p?§ ?§À?§ð?§?§@?§`?§??§°?§à?§ §0 §P §? §  §Ð §ð § ¡§@¡§p¡§?¡§À¡§à¡§¢§0¢§`¢§?¢§ ¢§Ð¢§ð¢§ £§@£§p£§?£§°£§à£§¤§ ¤§@¤§`¤§?¤§ ¤§Ð¤§ð¤§ ¥§@¥§`¥§?¥§ ¥§À¥§à¥§¦§0¦§P¦§?¦§ ¦§À¦§à¦§§§0§§P§§p§§?§§°§§Ð§§¨§0¨§P¨§p¨§?¨§°¨§à¨§©§ ©§@©§`©§?©§ ©§À©§à©§ª§ ª§@ª§`ª§?ª§ ª§Àª§àª§«§0«§`«§?«§!cp1252xt1¸Nchû?¸Nchû?g slew rate 1000

 
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 " Module Name " , " ddr_common "
" Base Address " , " 0x20110000 "
" Priority " , " 4 "
" Execution Required for Standby Wakeup " , " N "
" Execution Required for Normal Boot " , " Y "
" Register " , " Offset Address " , " Value Written to or Read from Register " , " delay " , " Read or Write " , " Bits to Be Read or Written " , " Start Bit to Be Read or Written " , " Register Attribute "
" NULL " , " 0 " , " 0 " , " 10000 " , " none " , " 0 " , " 0 " , " "
" " , " " , " " , " " , " write " , " " , " " , " " ,
" " , " " , " " , " " , " write " , " " , " " , " " ,
" " , " " , " " , " " , " write " , " " , " " , " " ,
" " , " " , " " , " " , " write " , " " , " " , " " ,
" " , " " , " " , " " , " write " , " " , " " , " " ,
" DDRC_PHY_REG12 " , " 0x840 " , " 0xcc " , " 0 " , " write " , " 31 " , " 0 " , " " , " CMD0???01100=46? "
" DDRC_PHY_REG14 " , " 0x848 " , " 0x0 " , " 0 " , " write " , " 1 " , " 0 " , " " ,
" DDRC_PHY_REG13 " , " 0x844 " , " 0xff " , " 0 " , " write " , " 31 " , " 0 " , " " , " CMD0 rising/falling slew rate 1111 "
" DDRC_PHY_REG16 " , " 0x854 " , " 0xcc " , " 0 " , " write " , " 31 " , " 0 " , " " , " CMD1???01100=46? "
" DDRC_PHY_REG18 " , " 0x85c " , " 0x0 " , " 0 " , " write " , " 1 " , " 0 " , " " ,
" DDRC_PHY_REG17 " , " 0x858 " , " 0xff " , " 0 " , " write " , " 31 " , " 0 " , " " , " CMD1 rising/falling slew rate 1111 "
" DDRC_PHY_REG22 " , " 0x870 " , " 0xcc " , " 0 " , " write " , " 31 " , " 0 " , " " , " CK???01100=46? "
" DDRC_PHY_REG24 " , " 0x878 " , " 0x0 " , " 0 " , " write " , " 1 " , " 0 " , " " ,
" DDRC_PHY_REG23 " , " 0x874 " , " 0xff " , " 0 " , " write " , " 31 " , " 0 " , " " , " CK rising/falling slew rate 1111 "
" DDRC_PHY_REG25 " , " 0x880 " , " 0xcc " , " 0 " , " write " , " 31 " , " 0 " , " " , " DQ???01100=46? "
" DDRC_PHY_REG28 " , " 0x88c " , " 0x0 " , " 0 " , " write " , " 1 " , " 4 " , " " ,
" DDRC_PHY_REG26 " , " 0x884 " , " 0x88 " , " 0 " , " write " , " 31 " , " 0 " , " " , " DQ rising/falling slew rate 1000 "
" DDRC_PHY_REG27 " , " 0x888 " , " 0x1B " , " 0 " , " write " , " 31 " , " 0 " , " " , " ODT?1011=120 "
" DDRC_PHY_REG28 " , " 0x88c " , " 0x3 " , " 0 " , " write " , " 1 " , " 0 " , " " ,
" DDRC_PHY_REG30 " , " 0xac4 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG31 " , " 0xac8 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG32 " , " 0xacc " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG33 " , " 0xad0 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG34 " , " 0xad4 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG35 " , " 0xad8 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG36 " , " 0xadc " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG37 " , " 0xae0 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG38 " , " 0xae4 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG39 " , " 0xae8 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG41 " , " 0xaf0 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG42 " , " 0xaf4 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG43 " , " 0xaf8 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG53 " , " 0xb20 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG40 " , " 0xaec " , " 0x9 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG54 " , " 0xb24 " , " 0x9 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG55 " , " 0xb28 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_TXDQSKEW " , " 0xafc " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_TXDQSKEW " , " 0xb00 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_TXDQSKEW " , " 0xb04 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_TXDQSKEW " , " 0xb08 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_TXDQSKEW " , " 0xb0c " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_TXDQSKEW " , " 0xb10 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_TXDQSKEW " , " 0xb14 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_TXDQSKEW " , " 0xb18 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG52 " , " 0xb1c " , " " , " " , " write " , " " , " " , " "
" DDRC_PHY_RXDQSKEW " , " 0xb2c " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_RXDQSKEW " , " 0xb30 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_RXDQSKEW " , " 0xb34 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_RXDQSKEW " , " 0xb38 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_RXDQSKEW " , " 0xb3c " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_RXDQSKEW " , " 0xb40 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_RXDQSKEW " , " 0xb44 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_RXDQSKEW " , " 0xb48 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG5E " , " 0xb4c " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" " , " " , " " , " " , " write " , " " , " " , " "
" " , " " , " " , " " , " write " , " " , " " , " "
" " , " " , " " , " " , " write " , " " , " " , " "
" " , " " , " " , " " , " write " , " " , " " , " "
 " Module Name " , " ddrc_init "
" Base Address " , " 0x20110000 "
" Priority " , " 5 "
" Execution Required for Standby Wakeup " , " N "
" Execution Required for Normal Boot " , " Y "
" Register " , " Offset Address " , " Value Written to or Read from Register " , " delay " , " Read or Write " , " Bits to Be Read or Written " , " Start Bit to Be Read or Written " , " Register Attribute "
" NULL " , " 0 " , " 0 " , " 10000 " , " none " , " 0 " , " 0 " , " "
" DDRC_PHYCTRL " , " 0x408 " , " 0x0 " , " 1000 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHYSTATUS " , " 0x404 " , " 0x1 " , " 0 " , " read " , " 0 " , " 0 " , " "
" DDRC_EMRS01 " , " 0x14 " , " 0x61b60 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_EMRS23 " , " 0x18 " , " 0x10 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_CONFIG0 " , " 0x1c " , " 0x8000C600 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_CONFIG1 " , " 0x20 " , " 0x785 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_TIMING2 " , " 0x58 " , " 0x0 " , " 0 " , " write " , " 10 " , " 0 " , " "
" DDRC_CTRL " , " 0x10 " , " 0x1 " , " 0 " , " write " , " 31 " , " 0 " , " "
" NULL " , " 0 " , " 0 " , " 200000 " , " none " , " 0 " , " 0 " , " "
" DDRC_RNKCFG " , " 0x2c " , " 0x132 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_TIMING0 " , " 0x50 " , " 0x6355110C " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_TIMING1 " , " 0x54 " , " 0xFF637A35 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_TIMING2 " , " 0x58 " , " 0x4350f000 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_TIMING3 " , " 0x5c " , " 0xffdff6f3 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_BASEADDR " , " 0x40 " , " 0x80000000 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_ODTCFG " , " 0xf4 " , " 0x1 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_DTRCTRL " , " 0xac " , " 0x3000301 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_SREFCTRL " , " 0x4 " , " 0 " , " 1000 " , " write " , " 31 " , " 0 " , " "
" DDRC_STATUS " , " 0x0 " , " 0x0 " , " 0 " , " read " , " 0 " , " 2 " , " "
" DDRC_INITCTRL " , " 0x8 " , " 0x1 " , " 1000 " , " write " , " 0 " , " 0 " , " "
" DDRC_STATUS " , " 0x0 " , " 0x0 " , " 0 " , " read " , " 0 " , " 3 " , " "
" DDRC_PHY_REG4A " , " 0x838 " , " 0xA0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG2 " , " 0x808 " , " 0x1 " , " 1000 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG61 " , " 0xBE8 " , " 0x3 " , " 0 " , " read " , " 1 " , " 0 " , " "
" DDRC_PHY_REG2 " , " 0x808 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_TIMING2 " , " 0x58 " , " 0xA1 " , " 0 " , " write " , " 10 " , " 0 " , " "
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 " Module Name " , " standby_pin_ctrl "
" Base Address " , " 0x200f0000 "
" Priority " , " 6 "
" Execution Required for Standby Wakeup " , " N "
" Execution Required for Normal Boot " , " Y "
" Register " , " Offset Address " , " Value Written to or Read from Register " , " delay " , " Read or Write " , " Bits to Be Read or Written " , " Start Bit to Be Read or Written " , " Register Attribute "
" muxctrl_reg19 " , " 0x4c " , " 0x0 " , " 0 " , " write " , " 0 " , " 0 " , " " , " UART1 "
" muxctrl_reg20 " , " 0x50 " , " 0x0 " , " 0 " , " write " , " 0 " , " 0 " , " " ,
" muxctrl_reg21 " , " 0x54 " , " 0x2 " , " 0 " , " write " , " 1 " , " 0 " , " " ,, " SKT???PWM "
" muxctrl_reg22 " , " 0x58 " , " 0x0 " , " 0 " , " write " , " 0 " , " 0 " , " " ,
" muxctrl_reg23 " , " 0x5C " , " 0x0 " , " 0 " , " write " , " 0 " , " 0 " , " " , " UART2 "
" muxctrl_reg24 " , " 0x60 " , " 0x0 " , " 0 " , " write " , " 0 " , " 0 " , " " ,, " ??PHY?????GPIO?? "
" muxctrl_reg26 " , " 0x68 " , " 0x1 " , " 0 " , " write " , " 0 " , " 0 " , " " , " USB0 "
" muxctrl_reg27 " , " 0x6c " , " 0x1 " , " 0 " , " write " , " 0 " , " 0 " , " " ,
" muxctrl_reg28 " , " 0x70 " , " 0x1 " , " 0 " , " write " , " 0 " , " 0 " , " " , " USB1 "
" muxctrl_reg29 " , " 0x74 " , " 0x1 " , " 0 " , " write " , " 0 " , " 0 " , " " ,
" muxctrl_reg30 " , " 0x78 " , " 0x1 " , " 0 " , " write " , " 0 " , " 0 " , " " , " HDMI "
" muxctrl_reg31 " , " 0x7c " , " 0x1 " , " 0 " , " write " , " 0 " , " 0 " , " " ,
" muxctrl_reg32 " , " 0x80 " , " 0x1 " , " 0 " , " write " , " 0 " , " 0 " , " " ,
" muxctrl_reg33 " , " 0x84 " , " 0x1 " , " 0 " , " write " , " 0 " , " 0 " , " " ,
" muxctrl_reg34 " , " 0x88 " , " 0x1 " , " 0 " , " write " , " 0 " , " 0 " , " " , " SATA "
" muxctrl_reg35 " , " 0x8c " , " 0x1 " , " 0 " , " write " , " 0 " , " 0 " , " " ,
" muxctrl_reg36 " , " 0x90 " , " 0x1 " , " 0 " , " write " , " 0 " , " 0 " , " " , " ETH "
" muxctrl_reg37 " , " 0x94 " , " 0x1 " , " 0 " , " write " , " 0 " , " 0 " , " " ,
" muxctrl_reg48 " , " 0xc0 " , " 0x1 " , " 0 " , " write " , " 0 " , " 0 " , " " , " TEMPER_DQ "
 " Module Name " , " ether_sysctrl "
" Base Address " , " 0x20050000 "
" Priority " , " 7 "
" Execution Required for Standby Wakeup " , " N "
" Execution Required for Normal Boot " , " Y "
" Register " , " Offset Address " , " Value Written to or Read from Register " , " delay " , " Read or Write " , " Bits to Be Read or Written " , " Start Bit to Be Read or Written " , " Register Attribute "
" PERIPHCTRL24 " , " 0x94 " , " 0x0 " , " 0 " , " write " , " 0 " , " 8 " , " "
" PERIPHCTRL24 " , " " , " 0x0 " , " 0 " , " write " , " 0 " , " " , " "
" " , " " , " " , " 0 " , " write " , " 31 " , " 0 " , " " , " " , " "
" " , " " , " " , " " , " write " , " " , " " , " " , " " , " "
,,,,,,,
,,,,,,,
,,,,,,,
 " nand flash " ,,,,,,,, " spi flash " ,,,,,,,, " emmc flash " ,,,,,,
" name " , " ID " , " chip size " , " erase size " , " page size " , " oob size " , " ecc type " ,, " name " , " jedec_id " , " ext_id " , " block_size " , " chip_size " , " clk " , " chip select "
" MT29F16G08CBABx-4K-24bit1K " , " 0x2C 0x48 0x04 0x46 0x85 0x00 0x00 0x00 " , " 2GB " , " 1MB " , " 4KB " , " 224B " , " 4 " ,, " mx25l1655d " , " 0xc2 0x26 0x15 " , " 0x0 " , " 65536 " , " 2097152 " , " 0x40100 " , " 1 "
" NAND01GW3B2CN6 " , " 0x20 0xF1 0x00 0x1D 0x20 0xF1 0x00 0x1D " , " 128MB " , " 128KB " , " 2KB " , " 64B " , " 1 " ,, " w25x16 " , " 0xef 0x30 0x15 " , " 0x0 " , " 65536 " , " 2097152 " , " 0x40100 " , " 1 "
" K9F1G0bU0C " , " 0xEC 0xF1 0x00 0x95 0x40 0x00 0xEC 0xF1 " , " 128MB " , " 128KB " , " 2KB " , " 64B " , " 1 " ,, " s25sl032a " , " 0x01 0x02 0x15 " , " 0x0 " , " 65536 " , " 4194304 " , " 0x40100 " , " 1 "
" K9F2G08U0B " , " 0xEC 0xDA 0x10 0x95 0x44 0xEC 0xEC 0xDA " , " 256MB " , " 128KB " , " 2KB " , " 64B " , " 1 " ,, " s25sl064a " , " 0x01 0x02 0x16 " , " 0x0 " , " 65536 " , " 8388608 " , " 0x40100 " , " 1 "
" HY27UF082G2B " , " 0xAD 0xDA 0x10 0x95 0x44 0xAD 0xDA 0x10 " , " 256MB " , " 128KB " , " 2KB " , " 64B " , " 1 " ,, " s25sl12800 " , " 0x01 0x20 0x18 " , " 0x03 0x00 " , " 262144 " , " 16777216 " , " 0x60100 " , " 1 "
" K9F4G08U0B " , " 0xEC 0xDC 0x10 0x95 0x54 0xEC 0xEC 0xDC " , " 512MB " , " 128KB " , " 2KB " , " 64B " , " 1 " ,, " m25px16 " , " 0x20 0x71 0x15 " , " 0x0 " , " 65536 " , " 2097152 " , " 0x40100 " , " 1 "
" HY27UF084G2B " , " 0xAD 0xDC 0x10 0x95 0x54 0xAD 0xDC 0x10 " , " 512MB " , " 128KB " , " 2KB " , " 64B " , " 1 " ,, " m25px32 " , " 0x20 0x71 0x16 " , " 0x0 " , " 65536 " , " 4194304 " , " 0x40100 " , " 1 "
" 29F4G08ABADA " , " 0x2C 0xDC 0x90 0x95 0x56 0x00 0x00 0x00 " , " 512MB " , " 128KB " , " 2KB " , " 64B " , " 1 " ,, " m25px64 " , " 0x20 0x71 0x17 " , " 0x0 " , " 65536 " , " 8388608 " , " 0x40100 " , " 1 "
" 29F1G08ABADA " , " 0x2C 0xF1 0x80 0x95 0x02 0x00 0x00 0x00 " , " 128MB " , " 128KB " , " 2KB " , " 64B " , " 1 " ,, " m25p32 " , " 0x20 0x20 0x16 " , " 0x0 " , " 65536 " , " 4194304 " , " 0x40100 " , " 1 "
" HY27UF081G2A " , " 0xAD 0xF1 0x80 0x1D 0xAD 0xF1 0x80 0x1D " , " 128MB " , " 128KB " , " 2KB " , " 64B " , " 1 " ,, " m25p128 " , " 0x20 0x20 0x18 " , " 0x0 " , " 262144 " , " 16777216 " , " 0x40100 " , " 1 "


uboot_tools.zip > uboot-Hi3520D-bvt_No1_660_330_660_ddr_outPHY.xls

,,,,
, " Boot V1.0 " ,,
, " Hisilicon Technologies Co., Ltd. All rights reserved. @2012 " ,,
,,,,,,,,
" Basic Project Information " ,,,,
,,,,
" Project Name " , " xxx " ,, " Project Version " , " 1.0 "
" Project Start Time " , " 40543 " ,, " Development " , " xxx "
" Product Line " , " Media " ,, " Department " , " Media "
" Project Description " , " Project description " ,,,
 " Module Name " , " slow "
" Base Address " , " 0x20050000 "
" Priority " , " 1 "
" Execution Required for Standby Wakeup " , " N "
" Execution Required for Normal Boot " , " Y "
" Register " , " Offset Address " , " Value Written to or Read from Register " , " delay " , " Read or Write " , " Bits to Be Read or Written " , " Start Bit to Be Read or Written " , " Register Attribute "
" SC_CTRL " , " 0 " , " 0x2 " , " 0 " , " write " , " 2 " , " 0 " , " "
" SC_CTRL " , " 0 " , " 0x2 " , " 0 " , " read " , " 3 " , " 3 " , " "
,,,,,,,
,,,,,,,
,,,,,,,
 " Module Name " , " pll "
" Base Address " , " 0x20030000 "
" Priority " , " 2 "
" Execution Required for Standby Wakeup " , " N "
" Execution Required for Normal Boot " , " Y " ,,,,,,
" Register " , " Offset Address " , " Value Written to or Read from Register " , " delay " , " Read or Write " , " Bits to Be Read or Written " , " Start Bit to Be Read or Written " , " Register Attribute "
" PERI_CRG0 " , " 0x0 " , " 0x11000000 " , " 0 " , " write " , " 31 " , " 0 " , " "
" PERI_CRG1 " , " 0x4 " , " 0x007c30a5 " , " 0 " , " write " , " 31 " , " 0 " , " "
" PERI_CRG2 " , " 0x8 " , " 0x22000000 " , " 0 " , " write " , " 31 " , " 0 " , " "
" PERI_CRG3 " , " 0xc " , " 0x007c2063 " , " 0 " , " write " , " 31 " , " 0 " , " "
" PERI_CRG10 " , " 0x28 " , " 0x0 " , " 0 " , " write " , " 1 " , " 2 " , " "
" PERI_CRG58 " , " 0xe8 " , " 0x7 " , " 0 " , " read " , " 2 " , " 0 " , " "
" " , " " , " " , " " , " write " , " " , " " , " " , " "
" " , " " , " " , " " , " none " , " " , " " , " "
" " , " " , " " , " " , " write " , " " , " " , " "
,,,,,,,
,,,,,,,
 " Module Name " , " normal "
" Base Address " , " 0x20050000 "
" Priority " , " 3 "
" Execution Required for Standby Wakeup " , " N "
" Execution Required for Normal Boot " , " Y "
" Register " , " Offset Address " , " Value Written to or Read from Register " , " delay " , " Read or Write " , " Bits to Be Read or Written " , " Start Bit to Be Read or Written " , " Register Attribute "
" SC_PLLCTRL " , " 0x14 " , " 0x0fff8000 " , " 0 " , " write " , " 31 " , " 0 " , " "
" SC_CTRL " , " 0 " , " 0x4 " , " 0 " , " write " , " 2 " , " 0 " , " "
" SC_CTRL " , " 0 " , " 0x4 " , " 0 " , " read " , " 3 " , " 3 " , " "
" SC_CTRL_SWDQS_TRAINING " , " 0xa0 " , "  & lt;
=B
70x0 7
DDRC_PHY_270xa0470x1f7031
DDRC_PHY_370xac070x557
DDRC_PHY_570x80470x4b7PERIPHCTRL2870xa47?07PERIPHCTRL2970xa873172
$NB\?gM`n?ÿ
[6:4]SFC :4ma 010;
[2:0]PAD_SPI_SDO:4ma 010
72ÛVB\?gM`n?ÿ
[6:4]SFC :8ma 110;
[2:0]PAD_SPI_SDO:8ma 1107Ü
$NB\?gM`n?ÿ
[30:28]spi_sclk:8ma 110;
[26:24]aio_ws_tx:4ma 010;
[22:20]aio_bclk_tx:11ma 111;
[18:16]aio_ws_rx:4ma 010;
[14:12]aio_bclk_rx:11ma 111;
[10:8]aio_mclk:11ma 111;
[6:4]vga_hs/vga_vs:8ma 010;
[2:0]vi_adc_clk:11ma 111
7
0x627277277
0x000000227ÞÛVB\?gM`n?ÿ
[30:28]spi_sclk:11ma 111;
[26:24]aio_ws_tx:4ma 010;
[22:20]aio_bclk_tx:11ma 111;
[18:16]aio_ws_rx:4ma 010;
[14:12]aio_bclk_rx:11ma 111;
[10:8]aio_mclk:11ma 111;
[6:4]vga_hs/vga_vs:12ma 100;
[2:0]vi_adc_clk:11ma 1117
DDRC_PHY_170x8307?07
DDRC_PHY_470x81870x4070x87?07317
DDRC_PHY_REG870x8e070x237?07317DDRC_PHY_REG1170x92070x227
DDRC_PHY_REG670x8d470xc7
DDRC_PHY_REG970x91470xd7
0x00000015·
0x181D0000·0x0000000FD7
0x0000100D7
0x0015000070x0000000FD7
0x000000157
0x181D00007
0x0000000570x070x0000000FD7
0x0000000D7
0x0000200D70x0000000FD7
0x000500007
0x0000005570x07
0x100500007
0x180500007
0x000D00007
0x0000000D70x917
PERI_CRG51 7ÿ0xcc7ÿ
0x0000000f7ÿ?07ÿ317ÿ0x0000000FD7ÿ
...QèŸCRG
7ÿNULL7ÿ100007ÿ0x07ÿ
0x0000000a7ÿ
muxctrl_reg380x987ÿ0x17ÿ
0x000000157ÿRMII7ÿ
muxctrl_reg390x9c7ÿ
muxctrl_reg400xa07ÿ
muxctrl_reg410xa47ÿ
muxctrl_reg420xa87ÿ
muxctrl_reg430xac7ÿ
muxctrl_reg440xb07ÿ
muxctrl_reg450xb47ÿ
muxctrl_reg497ÿ0xc47ÿMDIO7ÿ
muxctrl_reg507ÿ0xc87ÿPERIPHCTRL2470x947?87`Àà`à*``+`` +``P+``p+`` +``Ð+``,``@,``?,``°,``à,`` -``@-``p-``°-``ð-`` .``@.`` .``à.``/``@/``p/`` /``Ð/``0``00``P0``p0`` 0``Ð0``1``01``P1``p1`` 1``Ð1``2``02```2``Ÿ2``°2``à2``3``03```3``?3`` 3``À3``à3``4`` 4``@4``p4``Ÿ4``À4``à4``5``05``P5``p5``Ÿ5``À5``à5``6`` 6``P6``?6``°6``à6``7``07```7``Ÿ7``À7``ð7`` 8``@8```8``?8``À8``ð8`` 9``P9``?9``°9``à9``:``@:``p:``°:``ð:``0;``p;``°;``ð;``0 & lt; ``p & lt; ``° & lt; ``ð & lt; ``=``0=``P=``p=``Ÿ=``°=``Ð=``ð=`` & gt; ``0 & gt; ``P & gt; ``p & gt; ``Ÿ & gt; ``° & gt; ``Ð & gt; ``ð & gt; `` ?``@?``p?`` ?``Ð?``ð?``@``0@``P@``p@`` @``Ð@``A``0A```A``ŸA``ÀA``ðA`` B``PB``?B`` B``ÀB``àB``C``0C```C`` C``àC``D``@D``?D``°D``ðD``0E``pE`` E``ÐE``ðE`` F``@F``pF`` F``ÐF``G`` G``PG``?G``°G``àG``H``@H``pH`` H``ÐH``I``0I```I``ŸI``ÀI``ðI`` J``@J```J``?J`` J``ÐJ``ðJ``K``@K```K``ŸK``°K``àK``L``@L``pL`` L``ÀL``àL``M`` M``@M``pM``ŸM``°M``ÐM``ðM``N``0N``PN``pN``ŸN``ÀN``àN``O``0O``PO``pO`` O``ÀO``àO``P``0P```P``?P``°P``ÐP``ðP`` Q``@Q``pQ``ŸQ``ÀQ``àQ``R``0R``PR``?R`` R``ÐR``ðR`` S``@S```S``?S``°S``ÐS``T`` T``PT``pT``ŸT``ÀT``àT``U``0U``PU``pU``ŸU``°U``ÐU``ðU`` V``PV``pV`` V``ÐV``W``0W```W`` W``àW``X``@X``?X`` X``ÐX``Y``PY``?Y`` Y``ÀY``àY``Z``0Z``PZ``pZ`` Z``ÐZ``ðZ``[``0[```[``?[`` [``à[``\``0\```\``Ÿ\``°\``à\``]``@]``p]``Ÿ]``À]``ð]``^``@^```^`` ^``Ð^``ð^`` _``P_``p_``Ÿ_``À_``à_`````@```p```Ÿ```À```ð```a``@a```a``?a``°a``Ða``b`` b``Pb``pb`` b``Àb``ðb``c``@c```c``Ÿc``°c``àc``d``0d``Pd``?d`` d``Ðd``ðd`` e``@e``pe``Ÿe``Àe``àe``f``0f``Pf``?f`` f``Ðf``ðf``g``@g```g``?g`` g``Àg``àg``h``0h``Ph``?h`` h``Àh``àh``i`` i``@i``pi``Ÿi``°i``ài``j`` j``@j```j``Ÿj``°j``Ðj``ðj``k``0k```k``Ÿk``°k``Ðk``ðk``l``@l```l``?l`` l``Àl``àl``m`` m``@m```m``?m`` m``Àm``àm``n`` n``@n``pn``Ÿn``Àn``àn``!cp1252xt1¸ Èè?¸ Èè?g slew rate 1000

 
 ! " " #$% & '()*+,-./0123456789:; & lt; = & gt; ?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~?¬  '''...???o/oo? " " ?}   " "   Ü " " !a " " ?~? ¡¢£¤¥¦§¨©ª«¬®¯°±²³´µ¶·¸¹º»¼½¾¿ÀÁÂÃÄÅÆÇÈÉÊËÌÍÎÏÐÑÒÓÔÕÖ×ØÙÚÛÜÝÞßàáâãäåæçèéêëìíîïðñòóôõö÷øùúûüýþÿ!xxxxt!1.01Boot V1.0ÑÄ!Y1Module NameŸÄÿÿÿÿÿÿÿÿ1Base AddressQÄÿÿÿÿ1PriorityåÈè?!ÄAExecution Required for Standby WakeupAExecution Required for Normal Bootu1RegisterqÃ1Offset AddressAÃAValue Written to or Read from Register!delayâÈè?1Read or Write±ÂA Bits to Be Read or Writtenm RegisteAStart Bit to Be Read or Writtengiste1Register AttributeÂ!writeaHisilicon Technologies Co., Ltd. All rights reserved. @2012ŸÁABasic Project Informationitteegiste1Project NameÁ1Project Start TimeáÀ1Product Line±À1Project DescriptionŸÀ1Project VersionQÀ1Development!À1Departmentñ¿!Media!Media1Project descriptionŸ¿1nand flashQ¿1spi flash!¿1emmc flashñ¾!name!ID1chip sizeŸ¾1erase sizeQ¾1page size!¾1oob sizeñ½1ecc typeÁ½1jedec_id`½!ext_id1block_sizeA½1chip_size½!clk1chip selectÁ¼!SC_CTRL!0!0x2!2!0x2!3!slow10x20050000±»!N1PERI_CRG0a»!0x0!311PERI_CRG1ñº!0x4!0x14!pll10x20030000aº!N!N!normal10x20050000ѹ1SC_PLLCTRL¡¹10x0fff8000q¹10x20110000A¹!Y1DDRC_SREFCTRLñ¸10x80000000Á¸1DDRC_ODTCFG`¸1DDRC_INITCTRLa¸1standby_pin_ctrl1¸10x200f0000¸!0!read!noneAMT29F16G08CBABx-4K-24bit1Ktteegiste1NAND01GW3B2CN61·1K9F1G0bU0C·1K9F2G08U0BѶ1HY27UF082G2B¡¶1K9F4G08U0Bq¶1HY27UF084G2BA¶129F4G08ABADA¶129F1G08ABADAáµ1HY27UF081G2A±µA0x2C 0x48 0x04 0x46 0x85 0x00 0x00 0x00A0x20 0xF1 0x00 0x1D 0x20 0xF1 0x00 0x1DA0xEC 0xF1 0x00 0x95 0x40 0x00 0xEC 0xF1A0xEC 0xDA 0x10 0x95 0x44 0xEC 0xEC 0xDAA0xAD 0xDA 0x10 0x95 0x44 0xAD 0xDA 0x10A0xEC 0xDC 0x10 0x95 0x54 0xEC 0xEC 0xDCA0xAD 0xDC 0x10 0x95 0x54 0xAD 0xDC 0x10A0x2C 0xDC 0x90 0x95 0x56 0x00 0x00 0x00A0x2C 0xF1 0x80 0x95 0x02 0x00 0x00 0x00A0xAD 0xF1 0x80 0x1D 0xAD 0xF1 0x80 0x1D!2GB!128MB!256MB!512MB!1MB!128KB!128KB!4KB!2KB!2KB!2KB!2KB!224B!64B!64B!64B1mx25l1655d±!w25x161s25sl032a±°1s25sl064aŸ°1s25sl12800Q°!m25px16!m25px32!m25px64!m25p32!m25p12810xc2 0x26 0x15Ÿ¯10xef 0x30 0x15Q¯10x01 0x02 0x15!¯10x01 0x02 0x16ñ®10x01 0x20 0x18Á®10x20 0x71 0x15`®10x20 0x71 0x16a®10x20 0x71 0x171®10x20 0x20 0x16®10x20 0x20 0x18Ñ10x03 0x00¡!0x0!0x0!0x40100!0x601001Module Nameñ¬1PriorityÁ¬AExecution Required for Standby WakeupAExecution Required for Normal Bootu11Register¬1Offset Addressá«AValue Written to or Read from Register1Read or Writeq«AStart Bit to Be Read or WrittengisteA Bits to Be Read or WrittenteegisteA Bits to Be Read or Writtenteegiste1Register AttributeŸª1PERI_CRG2Qª!0x81PERI_CRG3ª!0xc1ddrc_init±©10x11000000Ÿ©10x22000000Q©10x007c2063!©!311DDRC_PHYCTRLѨ10xffdff6f3¡¨1muxctrl_reg27q¨1muxctrl_reg29A¨1muxctrl_reg30¨1muxctrl_reg31á§1muxctrl_reg32±§1muxctrl_reg33Ÿ§1muxctrl_reg34Q§1muxctrl_reg35!§1muxctrl_reg36ñ¦1muxctrl_reg37Á¦10x007c30a5`¦10x4350f000a¦10x6355110C1¦10xFF637A35¦!0x1!0!1!0x01muxctrl_reg19Q¥!0x4c!UART11muxctrl_reg20á¤!0x501muxctrl_reg21`¤!0x541muxctrl_reg22A¤1muxctrl_reg23¤1muxctrl_reg24á£1TEMPER_DQ±£1PERI_CRG10Ÿ£!0x28!0x0!0!1!21PERI_CRG58±¢!0xe8!0x7!31!NULL!1000!0x0!10000!0x408!0x01DDRC_PHYSTATUSa¡!0x404!0x11DDRC_EMRS01ñ !0x14!0x61b601DDRC_EMRS23Ÿ !0x18!0x101DDRC_CONFIG0 !0x1c10x8000C600Á?!write1DDRC_CONFIG1q?!0x20!0x7851DDRC_TIMING2?!0x581DDRC_CTRL±?!0x11DDRC_RNKCFGa?!0x2c!0x1321DDRC_TIMING0ñŸ!0x501DDRC_TIMING1¡Ÿ!0x541DDRC_TIMING3QŸ!0x5c1DDRC_BASEADDR?!0x40!31!0xf41DDRC_DTRCTRLq?!0xac10x3000301!?!0x41DDRC_STATUSÑ " " !0x8!31DDRC_PHY_REG4Aa " " !0x838!0xA01DDRC_PHY_REG2ñ?!0x808!200000!10!0xA1!0x1B!0x31ether_sysctrl?1DDRC_PHY_REG61Ñtm!0xBE81Module NameŸtm1ddr_commonQtm1Base Address!tm10x20110000ñ?1PriorityÁ?AExecution Required for Standby WakeupAExecution Required for Normal Bootu1Register?1Offset Addressá - AValue Written to or Read from Register!delay1Read or WriteQ - A Bits to Be Read or Writtenm RegisteAStart Bit to Be Read or Writtengiste1Register Attribute¡-!NULL!0!100001DDRC_PHY_REG12-!0x840!0xcc!311CMD0???01100=46?Ÿ*1DDRC_PHY_REG14Q*!0x848!0x0!11DDRC_PHY_REG13Á''!0x844!0xffACMD0 rising/falling slew rate 1111te1DDRC_PHY_REG16''!0x8541CMD1???01100=46?Á``1DDRC_PHY_REG18```!0x85c1DDRC_PHY_REG17A``!0x858ACMD1 rising/falling slew rate 1111te1DDRC_PHY_REG22±'!0x8701CK???01100=46?a'1DDRC_PHY_REG241'!0x8781DDRC_PHY_REG23á`!0x874ACK rising/falling slew rate 1111ste1DDRC_PHY_REG25Q`!0x8801DQ???01100=46??1DDRC_PHY_REG28џ!0x88c!41DDRC_PHY_REG26aŸ!0x884!0x88ADQ rising/falling slew rate 1000ste1DDRC_PHY_REG27±Ÿ!0x8881ODT?1011=120aŸ1DDRC_PHY_REG281Ÿ!0x31DDRC_PHY_REG30á?!0xac4!0x01DDRC_PHY_REG31q?!0xac81DDRC_PHY_REG32!?!0xacc1DDRC_PHY_REG33џ!0xad01DDRC_PHY_REG34ŸŸ!0xad41DDRC_PHY_REG351Ÿ!0xad81DDRC_PHY_REG36á?!0xadc1DDRC_PHY_REG37`?!0xae01DDRC_PHY_REG38A?!0xae41DDRC_PHY_REG39ñ " " !0xae81DDRC_PHY_REG41¡ " " !0xaf01DDRC_PHY_REG42Q " " !0xaf41DDRC_PHY_REG43?!0xaf81DDRC_PHY_REG53±?!0xb201DDRC_PHY_REG40a?!0xaec!0x91DDRC_PHY_REG54ño/oo!0xb241DDRC_PHY_REG55¡o/oo!0xb281DDRC_PHY_TXDQSKEWQo/oo!0xafc!0xb001DDRC_PHY_TXDQSKEWá?!0xb04!0xb08!0xb0c!0xb10!0xb14!0xb181DDRC_PHY_REG52ñ?!0xb1c1DDRC_PHY_RXDQSKEW¡?!0xb2c!0xb30!0xb34!0xb38!0xb3c!0xb401DDRC_PHY_RXDQSKEW±?!0xb44!0xb481DDRC_PHY_REG5EA?!0xb4c!0x2!0!11SKT???PWM`...!0x58!0x0!0x5C!UART2!0x601??PHY?????GPIO??Á''1muxctrl_reg26`''!0x68!0x1!USB0!0x6c1muxctrl_reg28á?!0x70!USB1!0x74!0x78!0x1!0!HDMI!0x7c!0x80!0x84!0x88!SATA!0x8c!0x90!ETH!0x941muxctrl_reg48±Ÿ!0xc01SC_CTRL_SWDQS_TRAININGaŸ!0xa0q??DQStraining??_sQÿbit[0]ÿ
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70x0 7
DDRC_PHY_270xa0470x1f7031
DDRC_PHY_370xac070x557
DDRC_PHY_570x80470x4b7PERIPHCTRL2870xa47?07PERIPHCTRL2970xa873172
$NB\?gM`n?ÿ
[6:4]SFC :4ma 010;
[2:0]PAD_SPI_SDO:4ma 010
72ÛVB\?gM`n?ÿ
[6:4]SFC :8ma 110;
[2:0]PAD_SPI_SDO:8ma 1107Ü
$NB\?gM`n?ÿ
[30:28]spi_sclk:8ma 110;
[26:24]aio_ws_tx:4ma 010;
[22:20]aio_bclk_tx:11ma 111;
[18:16]aio_ws_rx:4ma 010;
[14:12]aio_bclk_rx:11ma 111;
[10:8]aio_mclk:11ma 111;
[6:4]vga_hs/vga_vs:8ma 010;
[2:0]vi_adc_clk:11ma 111
7
0x627277277
0x000000227ÞÛVB\?gM`n?ÿ
[30:28]spi_sclk:11ma 111;
[26:24]aio_ws_tx:4ma 010;
[22:20]aio_bclk_tx:11ma 111;
[18:16]aio_ws_rx:4ma 010;
[14:12]aio_bclk_rx:11ma 111;
[10:8]aio_mclk:11ma 111;
[6:4]vga_hs/vga_vs:12ma 100;
[2:0]vi_adc_clk:11ma 1117
DDRC_PHY_170x8307?07
DDRC_PHY_470x81870x4070x87?07317
DDRC_PHY_REG870x8e070x237?07317DDRC_PHY_REG1170x92070x227
DDRC_PHY_REG670x8d470xc7
DDRC_PHY_REG970x91470xd7
0x00000015·
0x181D0000·0x0000000FD7
0x0000100D7
0x0015000070x0000000FD7
0x000000157
0x181D00007
0x0000000570x070x0000000FD7
0x0000000D7
0x0000200D70x0000000FD7
0x000500007
0x0000005570x07
0x100500007
0x180500007
0x000D00007
0x0000000D70x917
PERI_CRG51 7ÿ0xcc7ÿ
0x0000000f7ÿ?07ÿ317ÿ0x0000000FD7ÿ
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0x0000000a7ÿ
muxctrl_reg380x987ÿ0x17ÿ
0x000000157ÿRMII7ÿ
muxctrl_reg390x9c7ÿ
muxctrl_reg400xa07ÿ
muxctrl_reg410xa47ÿ
muxctrl_reg420xa87ÿ
muxctrl_reg430xac7ÿ
muxctrl_reg440xb07ÿ
muxctrl_reg450xb47ÿ
muxctrl_reg497ÿ0xc47ÿMDIO7ÿ
muxctrl_reg507ÿ0xc87ÿPERIPHCTRL2470x947?87`Àà`à*``+`` +``P+``p+`` +``Ð+``,``@,``?,``°,``à,`` -``@-``p-``°-``ð-`` .``@.`` .``à.``/``@/``p/`` /``Ð/``0``00``P0``p0`` 0``Ð0``1``01``P1``p1`` 1``Ð1``2``02```2``?2``°2``à2``3``03```3``?3`` 3``À3``à3``4`` 4``@4``p4``?4``À4``à4``5``05``P5``p5``?5``À5``à5``6`` 6``P6``?6``°6``à6``7``07```7``?7``À7``ð7`` 8``@8```8``?8``À8``ð8`` 9``P9``?9``°9``à9``:``@:``p:``°:``ð:``0;``p;``°;``ð;``0 & lt; ``p & lt; ``° & lt; ``ð & lt; ``=``0=``P=``p=``?=``°=``Ð=``ð=`` & gt; ``0 & gt; ``P & gt; ``p & gt; ``? & gt; ``° & gt; ``Ð & gt; ``ð & gt; `` ?``@?``p?`` ?``Ð?``ð?``@``0@``P@``p@`` @``Ð@``A``0A```A``?A``ÀA``ðA`` B``PB``?B`` B``ÀB``àB``C``0C```C`` C``àC``D``@D``?D``°D``ðD``0E``pE`` E``ÐE``ðE`` F``@F``pF`` F``ÐF``G`` G``PG``?G``°G``àG``H``@H``pH`` H``ÐH``I``0I```I``?I``ÀI``ðI`` J``@J```J``?J`` J``ÐJ``ðJ``K``@K```K``?K``°K``àK``L``@L``pL`` L``ÀL``àL``M`` M``@M``pM``?M``°M``ÐM``ðM``N``0N``PN``pN``?N``ÀN``àN``O``0O``PO``pO`` O``ÀO``àO``P``0P```P``?P``°P``ÐP``ðP`` Q``@Q``pQ``?Q``ÀQ``àQ``R``0R``PR``?R`` R``ÐR``ðR`` S``@S```S``?S``°S``ÐS``T`` T``PT``pT``?T``ÀT``àT``U``0U``PU``pU``?U``°U``ÐU``ðU`` V``PV``pV`` V``ÐV``W``0W```W`` W``àW``X``@X``?X`` X``ÐX``Y``PY``?Y`` Y``ÀY``àY``Z``0Z``PZ``pZ`` Z``ÐZ``ðZ``[``0[```[``?[`` [``à[``\``0\```\``?\``°\``à\``]``@]``p]``?]``À]``ð]``^``@^```^`` ^``Ð^``ð^`` _``P_``p_``?_``À_``à_`````@```p```?```À```ð```a``@a```a``?a``°a``Ða``b`` b``Pb``pb`` b``Àb``ðb``c``@c```c``?c``°c``àc``d``0d``Pd``?d`` d``Ðd``ðd`` e``@e``pe``?e``Àe``àe``f``0f``Pf``?f`` f``Ðf``ðf``g``@g```g``?g`` g``Àg``àg``h``0h``Ph``?h`` h``Àh``àh``i`` i``@i``pi``?i``°i``ài``j`` j``@j```j``?j``°j``Ðj``ðj``k``0k```k``?k``°k``Ðk``ðk``l``@l```l``?l`` l``Àl``àl``m`` m``@m```m``?m`` m``Àm``àm``n`` n``@n``pn``?n``Àn``àn``!cp1252xt1¸ Èè?¸ Èè?g slew rate 1000

 
 ! " " #$% & '()*+,-./0123456789:; & lt; = & gt; ?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~?¬  '''...???o/oo? " " ?}   " "   Ü " " !a " " ?~? ¡¢£¤¥¦§¨©ª«¬®¯°±²³´µ¶·¸¹º»¼½¾¿ÀÁÂÃÄÅÆÇÈÉÊËÌÍÎÏÐÑÒÓÔÕÖ×ØÙÚÛÜÝÞßàáâãäåæçèéêëìíîïðñòóôõö÷øùúûüýþÿ!xxxxt!1.01Boot V1.0ÑÄ!Y1Module Name?Äÿÿÿÿÿÿÿÿ1Base AddressQÄÿÿÿÿ1PriorityåÈè?!ÄAExecution Required for Standby WakeupAExecution Required for Normal Bootu1RegisterqÃ1Offset AddressAÃAValue Written to or Read from Register!delayâÈè?1Read or Write±ÂA Bits to Be Read or Writtenm RegisteAStart Bit to Be Read or Writtengiste1Register AttributeÂ!writeaHisilicon Technologies Co., Ltd. All rights reserved. @2012?ÁABasic Project Informationitteegiste1Project NameÁ1Project Start TimeáÀ1Product Line±À1Project Description?À1Project VersionQÀ1Development!À1Departmentñ¿!Media!Media1Project description?¿1nand flashQ¿1spi flash!¿1emmc flashñ¾!name!ID1chip size?¾1erase sizeQ¾1page size!¾1oob sizeñ½1ecc typeÁ½1jedec_id`½!ext_id1block_sizeA½1chip_size½!clk1chip selectÁ¼!SC_CTRL!0!0x2!2!0x2!3!slow10x20050000±»!N1PERI_CRG0a»!0x0!311PERI_CRG1ñº!0x4!0x14!pll10x20030000aº!N!N!normal10x20050000ѹ1SC_PLLCTRL¡¹10x0fff8000q¹10x20110000A¹!Y1DDRC_SREFCTRLñ¸10x80000000Á¸1DDRC_ODTCFG`¸1DDRC_INITCTRLa¸1standby_pin_ctrl1¸10x200f0000¸!0!read!noneAMT29F16G08CBABx-4K-24bit1Ktteegiste1NAND01GW3B2CN61·1K9F1G0bU0C·1K9F2G08U0BѶ1HY27UF082G2B¡¶1K9F4G08U0Bq¶1HY27UF084G2BA¶129F4G08ABADA¶129F1G08ABADAáµ1HY27UF081G2A±µA0x2C 0x48 0x04 0x46 0x85 0x00 0x00 0x00A0x20 0xF1 0x00 0x1D 0x20 0xF1 0x00 0x1DA0xEC 0xF1 0x00 0x95 0x40 0x00 0xEC 0xF1A0xEC 0xDA 0x10 0x95 0x44 0xEC 0xEC 0xDAA0xAD 0xDA 0x10 0x95 0x44 0xAD 0xDA 0x10A0xEC 0xDC 0x10 0x95 0x54 0xEC 0xEC 0xDCA0xAD 0xDC 0x10 0x95 0x54 0xAD 0xDC 0x10A0x2C 0xDC 0x90 0x95 0x56 0x00 0x00 0x00A0x2C 0xF1 0x80 0x95 0x02 0x00 0x00 0x00A0xAD 0xF1 0x80 0x1D 0xAD 0xF1 0x80 0x1D!2GB!128MB!256MB!512MB!1MB!128KB!128KB!4KB!2KB!2KB!2KB!2KB!224B!64B!64B!64B1mx25l1655d±!w25x161s25sl032a±°1s25sl064a?°1s25sl12800Q°!m25px16!m25px32!m25px64!m25p32!m25p12810xc2 0x26 0x15?¯10xef 0x30 0x15Q¯10x01 0x02 0x15!¯10x01 0x02 0x16ñ®10x01 0x20 0x18Á®10x20 0x71 0x15`®10x20 0x71 0x16a®10x20 0x71 0x171®10x20 0x20 0x16®10x20 0x20 0x18Ñ10x03 0x00¡!0x0!0x0!0x40100!0x601001Module Nameñ¬1PriorityÁ¬AExecution Required for Standby WakeupAExecution Required for Normal Bootu11Register¬1Offset Addressá«AValue Written to or Read from Register1Read or Writeq«AStart Bit to Be Read or WrittengisteA Bits to Be Read or WrittenteegisteA Bits to Be Read or Writtenteegiste1Register Attribute?ª1PERI_C " , " 0 " , " write " , " 0 " , " 0 " , " " , " ??DQStraining??_sQÿbit[0]ÿ
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 " Module Name " , " ddr_common "
" Base Address " , " 0x20110000 "
" Priority " , " 4 "
" Execution Required for Standby Wakeup " , " N "
" Execution Required for Normal Boot " , " Y "
" Register " , " Offset Address " , " Value Written to or Read from Register " , " delay " , " Read or Write " , " Bits to Be Read or Written " , " Start Bit to Be Read or Written " , " Register Attribute "
" NULL " , " 0 " , " 0 " , " 10000 " , " none " , " 0 " , " 0 " , " "
" " , " " , " " , " " , " write " , " " , " " , " " ,
" " , " " , " " , " " , " write " , " " , " " , " " ,
" " , " " , " " , " " , " write " , " " , " " , " " ,
" " , " " , " " , " " , " write " , " " , " " , " " ,
" " , " " , " " , " " , " write " , " " , " " , " " ,
" DDRC_PHY_REG12 " , " 0x840 " , " 0xcc " , " 0 " , " write " , " 31 " , " 0 " , " " , " CMD0???01100=46? "
" DDRC_PHY_REG14 " , " 0x848 " , " 0x0 " , " 0 " , " write " , " 1 " , " 0 " , " " ,
" DDRC_PHY_REG13 " , " 0x844 " , " 0xff " , " 0 " , " write " , " 31 " , " 0 " , " " , " CMD0 rising/falling slew rate 1111 "
" DDRC_PHY_REG16 " , " 0x854 " , " 0xcc " , " 0 " , " write " , " 31 " , " 0 " , " " , " CMD1???01100=46? "
" DDRC_PHY_REG18 " , " 0x85c " , " 0x0 " , " 0 " , " write " , " 1 " , " 0 " , " " ,
" DDRC_PHY_REG17 " , " 0x858 " , " 0xff " , " 0 " , " write " , " 31 " , " 0 " , " " , " CMD1 rising/falling slew rate 1111 "
" DDRC_PHY_REG22 " , " 0x870 " , " 0xcc " , " 0 " , " write " , " 31 " , " 0 " , " " , " CK???01100=46? "
" DDRC_PHY_REG24 " , " 0x878 " , " 0x0 " , " 0 " , " write " , " 1 " , " 0 " , " " ,
" DDRC_PHY_REG23 " , " 0x874 " , " 0xff " , " 0 " , " write " , " 31 " , " 0 " , " " , " CK rising/falling slew rate 1111 "
" DDRC_PHY_REG25 " , " 0x880 " , " 0xcc " , " 0 " , " write " , " 31 " , " 0 " , " " , " DQ???01100=46? "
" DDRC_PHY_REG28 " , " 0x88c " , " 0x0 " , " 0 " , " write " , " 1 " , " 4 " , " " ,
" DDRC_PHY_REG26 " , " 0x884 " , " 0x88 " , " 0 " , " write " , " 31 " , " 0 " , " " , " DQ rising/falling slew rate 1000 "
" DDRC_PHY_REG27 " , " 0x888 " , " 0x1B " , " 0 " , " write " , " 31 " , " 0 " , " " , " ODT?1011=120 "
" DDRC_PHY_REG28 " , " 0x88c " , " 0x3 " , " 0 " , " write " , " 1 " , " 0 " , " " ,
" DDRC_PHY_REG30 " , " 0xac4 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG31 " , " 0xac8 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG32 " , " 0xacc " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG33 " , " 0xad0 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG34 " , " 0xad4 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG35 " , " 0xad8 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG36 " , " 0xadc " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG37 " , " 0xae0 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG38 " , " 0xae4 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG39 " , " 0xae8 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG41 " , " 0xaf0 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG42 " , " 0xaf4 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG43 " , " 0xaf8 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG53 " , " 0xb20 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG40 " , " 0xaec " , " 0x9 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG54 " , " 0xb24 " , " 0x9 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG55 " , " 0xb28 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_TXDQSKEW " , " 0xafc " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_TXDQSKEW " , " 0xb00 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_TXDQSKEW " , " 0xb04 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_TXDQSKEW " , " 0xb08 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_TXDQSKEW " , " 0xb0c " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_TXDQSKEW " , " 0xb10 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_TXDQSKEW " , " 0xb14 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_TXDQSKEW " , " 0xb18 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG52 " , " 0xb1c " , " " , " " , " write " , " " , " " , " "
" DDRC_PHY_RXDQSKEW " , " 0xb2c " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_RXDQSKEW " , " 0xb30 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_RXDQSKEW " , " 0xb34 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_RXDQSKEW " , " 0xb38 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_RXDQSKEW " , " 0xb3c " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_RXDQSKEW " , " 0xb40 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_RXDQSKEW " , " 0xb44 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_RXDQSKEW " , " 0xb48 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG5E " , " 0xb4c " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" " , " " , " " , " " , " write " , " " , " " , " "
" " , " " , " " , " " , " write " , " " , " " , " "
" " , " " , " " , " " , " write " , " " , " " , " "
" " , " " , " " , " " , " write " , " " , " " , " "
 " Module Name " , " ddrc_init "
" Base Address " , " 0x20110000 "
" Priority " , " 5 "
" Execution Required for Standby Wakeup " , " N "
" Execution Required for Normal Boot " , " Y "
" Register " , " Offset Address " , " Value Written to or Read from Register " , " delay " , " Read or Write " , " Bits to Be Read or Written " , " Start Bit to Be Read or Written " , " Register Attribute "
" NULL " , " 0 " , " 0 " , " 10000 " , " none " , " 0 " , " 0 " , " "
" DDRC_PHYCTRL " , " 0x408 " , " 0x0 " , " 1000 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHYSTATUS " , " 0x404 " , " 0x1 " , " 0 " , " read " , " 0 " , " 0 " , " "
" DDRC_EMRS01 " , " 0x14 " , " 0x61b60 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_EMRS23 " , " 0x18 " , " 0x10 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_CONFIG0 " , " 0x1c " , " 0x8000C600 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_CONFIG1 " , " 0x20 " , " 0x785 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_TIMING2 " , " 0x58 " , " 0x0 " , " 0 " , " write " , " 10 " , " 0 " , " "
" DDRC_CTRL " , " 0x10 " , " 0x1 " , " 0 " , " write " , " 31 " , " 0 " , " "
" NULL " , " 0 " , " 0 " , " 200000 " , " none " , " 0 " , " 0 " , " "
" DDRC_RNKCFG " , " 0x2c " , " 0x132 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_TIMING0 " , " 0x50 " , " 0x6355110C " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_TIMING1 " , " 0x54 " , " 0xFF637A35 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_TIMING2 " , " 0x58 " , " 0x4350f000 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_TIMING3 " , " 0x5c " , " 0xffdff6f3 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_BASEADDR " , " 0x40 " , " 0x80000000 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_ODTCFG " , " 0xf4 " , " 0x1 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_DTRCTRL " , " 0xac " , " 0x3000301 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_SREFCTRL " , " 0x4 " , " 0 " , " 1000 " , " write " , " 31 " , " 0 " , " "
" DDRC_STATUS " , " 0x0 " , " 0x0 " , " 0 " , " read " , " 0 " , " 2 " , " "
" DDRC_INITCTRL " , " 0x8 " , " 0x1 " , " 1000 " , " write " , " 0 " , " 0 " , " "
" DDRC_STATUS " , " 0x0 " , " 0x0 " , " 0 " , " read " , " 0 " , " 3 " , " "
" DDRC_PHY_REG4A " , " 0x838 " , " 0xA0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG2 " , " 0x808 " , " 0x1 " , " 1000 " , " write " , " 31 " , " 0 " , " "
" DDRC_PHY_REG61 " , " 0xBE8 " , " 0x3 " , " 0 " , " read " , " 1 " , " 0 " , " "
" DDRC_PHY_REG2 " , " 0x808 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " "
" DDRC_TIMING2 " , " 0x58 " , " 0xA1 " , " 0 " , " write " , " 10 " , " 0 " , " "
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 " Module Name " , " standby_pin_ctrl "
" Base Address " , " 0x200f0000 "
" Priority " , " 6 "
" Execution Required for Standby Wakeup " , " N "
" Execution Required for Normal Boot " , " Y "
" Register " , " Offset Address " , " Value Written to or Read from Register " , " delay " , " Read or Write " , " Bits to Be Read or Written " , " Start Bit to Be Read or Written " , " Register Attribute "
" muxctrl_reg19 " , " 0x4c " , " 0x0 " , " 0 " , " write " , " 0 " , " 0 " , " " , " UART1 "
" muxctrl_reg20 " , " 0x50 " , " 0x0 " , " 0 " , " write " , " 0 " , " 0 " , " " ,
" muxctrl_reg21 " , " 0x54 " , " 0x2 " , " 0 " , " write " , " 1 " , " 0 " , " " ,, " SKT???PWM "
" muxctrl_reg22 " , " 0x58 " , " 0x0 " , " 0 " , " write " , " 0 " , " 0 " , " " ,
" muxctrl_reg23 " , " 0x5C " , " 0x0 " , " 0 " , " write " , " 0 " , " 0 " , " " , " UART2 "
" muxctrl_reg24 " , " 0x60 " , " 0x0 " , " 0 " , " write " , " 0 " , " 0 " , " " ,, " ??PHY?????GPIO?? "
" muxctrl_reg26 " , " 0x68 " , " 0x1 " , " 0 " , " write " , " 0 " , " 0 " , " " , " USB0 "
" muxctrl_reg27 " , " 0x6c " , " 0x1 " , " 0 " , " write " , " 0 " , " 0 " , " " ,
" muxctrl_reg28 " , " 0x70 " , " 0x1 " , " 0 " , " write " , " 0 " , " 0 " , " " , " USB1 "
" muxctrl_reg29 " , " 0x74 " , " 0x1 " , " 0 " , " write " , " 0 " , " 0 " , " " ,
" muxctrl_reg30 " , " 0x78 " , " 0x1 " , " 0 " , " write " , " 0 " , " 0 " , " " , " HDMI "
" muxctrl_reg31 " , " 0x7c " , " 0x1 " , " 0 " , " write " , " 0 " , " 0 " , " " ,
" muxctrl_reg32 " , " 0x80 " , " 0x1 " , " 0 " , " write " , " 0 " , " 0 " , " " ,
" muxctrl_reg33 " , " 0x84 " , " 0x1 " , " 0 " , " write " , " 0 " , " 0 " , " " ,
" muxctrl_reg34 " , " 0x88 " , " 0x1 " , " 0 " , " write " , " 0 " , " 0 " , " " , " SATA "
" muxctrl_reg35 " , " 0x8c " , " 0x1 " , " 0 " , " write " , " 0 " , " 0 " , " " ,
" muxctrl_reg36 " , " 0x90 " , " 0x1 " , " 0 " , " write " , " 0 " , " 0 " , " " , " ETH "
" muxctrl_reg37 " , " 0x94 " , " 0x1 " , " 0 " , " write " , " 0 " , " 0 " , " " ,
" muxctrl_reg48 " , " 0xc0 " , " 0x1 " , " 0 " , " write " , " 0 " , " 0 " , " " , " TEMPER_DQ "
" " , " " , " " , " " , " write " , " " , " " , " " , " "
" " , " " , " " , " " , " write " , " " , " " , " " ,
" " , " " , " " , " " , " write " , " " , " " , " " ,
" " , " " , " " , " " , " write " , " " , " " , " " ,
" " , " " , " " , " " , " write " , " " , " " , " " ,
" " , " " , " " , " " , " write " , " " , " " , " " ,
" " , " " , " " , " " , " write " , " " , " " , " " ,
" " , " " , " " , " " , " write " , " " , " " , " " ,
" " , " " , " " , " " , " write " , " " , " " , " " , " "
" " , " " , " " , " " , " write " , " " , " " , " " ,
 " Module Name " , " ether_sysctrl "
" Base Address " , " 0x20050000 "
" Priority " , " 7 "
" Execution Required for Standby Wakeup " , " N "
" Execution Required for Normal Boot " , " Y "
" Register " , " Offset Address " , " Value Written to or Read from Register " , " delay " , " Read or Write " , " Bits to Be Read or Written " , " Start Bit to Be Read or Written " , " Register Attribute "
" " , " " , " 0x1 " , " 0 " , " write " , " 0 " , " " , " "
" " , " " , " " , " 0 " , " write " , " 31 " , " 0 " , " " , " " , " "
" " , " " , " " , " " , " write " , " " , " " , " " , " " , " "
,,,,,,,
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,,,,,,,
 " nand flash " ,,,,,,,, " spi flash " ,,,,,,,, " emmc flash " ,,,,,,
" name " , " ID " , " chip size " , " erase size " , " page size " , " oob size " , " ecc type " ,, " name " , " jedec_id " , " ext_id " , " block_size " , " chip_size " , " clk " , " chip select "
" MT29F16G08CBABx-4K-24bit1K " , " 0x2C 0x48 0x04 0x46 0x85 0x00 0x00 0x00 " , " 2GB " , " 1MB " , " 4KB " , " 224B " , " 4 " ,, " mx25l1655d " , " 0xc2 0x26 0x15 " , " 0x0 " , " 65536 " , " 2097152 " , " 0x40100 " , " 1 "
" NAND01GW3B2CN6 " , " 0x20 0xF1 0x00 0x1D 0x20 0xF1 0x00 0x1D " , " 128MB " , " 128KB " , " 2KB " , " 64B " , " 1 " ,, " w25x16 " , " 0xef 0x30 0x15 " , " 0x0 " , " 65536 " , " 2097152 " , " 0x40100 " , " 1 "
" K9F1G0bU0C " , " 0xEC 0xF1 0x00 0x95 0x40 0x00 0xEC 0xF1 " , " 128MB " , " 128KB " , " 2KB " , " 64B " , " 1 " ,, " s25sl032a " , " 0x01 0x02 0x15 " , " 0x0 " , " 65536 " , " 4194304 " , " 0x40100 " , " 1 "
" K9F2G08U0B " , " 0xEC 0xDA 0x10 0x95 0x44 0xEC 0xEC 0xDA " , " 256MB " , " 128KB " , " 2KB " , " 64B " , " 1 " ,, " s25sl064a " , " 0x01 0x02 0x16 " , " 0x0 " , " 65536 " , " 8388608 " , " 0x40100 " , " 1 "
" HY27UF082G2B " , " 0xAD 0xDA 0x10 0x95 0x44 0xAD 0xDA 0x10 " , " 256MB " , " 128KB " , " 2KB " , " 64B " , " 1 " ,, " s25sl12800 " , " 0x01 0x20 0x18 " , " 0x03 0x00 " , " 262144 " , " 16777216 " , " 0x60100 " , " 1 "
" K9F4G08U0B " , " 0xEC 0xDC 0x10 0x95 0x54 0xEC 0xEC 0xDC " , " 512MB " , " 128KB " , " 2KB " , " 64B " , " 1 " ,, " m25px16 " , " 0x20 0x71 0x15 " , " 0x0 " , " 65536 " , " 2097152 " , " 0x40100 " , " 1 "
" HY27UF084G2B " , " 0xAD 0xDC 0x10 0x95 0x54 0xAD 0xDC 0x10 " , " 512MB " , " 128KB " , " 2KB " , " 64B " , " 1 " ,, " m25px32 " , " 0x20 0x71 0x16 " , " 0x0 " , " 65536 " , " 4194304 " , " 0x40100 " , " 1 "
" 29F4G08ABADA " , " 0x2C 0xDC 0x90 0x95 0x56 0x00 0x00 0x00 " , " 512MB " , " 128KB " , " 2KB " , " 64B " , " 1 " ,, " m25px64 " , " 0x20 0x71 0x17 " , " 0x0 " , " 65536 " , " 8388608 " , " 0x40100 " , " 1 "
" 29F1G08ABADA " , " 0x2C 0xF1 0x80 0x95 0x02 0x00 0x00 0x00 " , " 128MB " , " 128KB " , " 2KB " , " 64B " , " 1 " ,, " m25p32 " , " 0x20 0x20 0x16 " , " 0x0 " , " 65536 " , " 4194304 " , " 0x40100 " , " 1 "
" HY27UF081G2A " , " 0xAD 0xF1 0x80 0x1D 0xAD 0xF1 0x80 0x1D " , " 128MB " , " 128KB " , " 2KB " , " 64B " , " 1 " ,, " m25p128 " , " 0x20 0x20 0x18 " , " 0x0 " , " 262144 " , " 16777216 " , " 0x40100 " , " 1 "


uboot_tools.zip > uboot-Hi3521-bvt_No1_930_310_620_ddr0_slow.xls

,,,,
, " Boot V1.0 " ,,
, " Hisilicon Technologies Co., Ltd. All rights reserved. @2012 " ,,
,,,,,,,,
" Basic Project Information " ,,,,
,,,,
" Project Name " , " xxx " ,, " Project Version " , " 1.0 "
" Project Start Time " , " 40543 " ,, " Development " , " xxx "
" Product Line " , " Media " ,, " Department " , " Media "
" Project Description " , " Project description " ,,,
 " Module Name " , " slow "
" Base Address " , " 0x20050000 "
" Priority " , " 1 "
" Execution Required for Standby Wakeup " , " N "
" Execution Required for Normal Boot " , " Y "
" Register " , " Offset Address " , " Value Written to or Read from Register " , " delay " , " Read or Write " , " Bits to Be Read or Written " , " Start Bit to Be Read or Written " , " Register Attribute "
" SC_CTRL " , " 0 " , " 0x2 " , " 0 " , " write " , " 2 " , " 0 " , " 0x00000015 "
" SC_CTRL " , " 0 " , " 0x2 " , " 0 " , " read " , " 3 " , " 3 " , " 0x181D0000 "
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,,,,,,,
,,,,,,,
 " Module Name " , " pll "
" Base Address " , " 0x20030000 "
" Priority " , " 2 "
" Execution Required for Standby Wakeup " , " N "
" Execution Required for Normal Boot " , " Y " ,,,,,,
" Register " , " Offset Address " , " Value Written to or Read from Register " , " delay " , " Read or Write " , " Bits to Be Read or Written " , " Start Bit to Be Read or Written " , " Register Attribute "
" PERI_CRG0 " , " 0x0 " , " 0x09000000 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" PERI_CRG1 " , " 0x4 " , " 0x006c209b " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" PERI_CRG2 " , " 0x8 " , " 0x24000000 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" PERI_CRG3 " , " 0xc " , " 0x006c2063 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" PERI_CRG58 " , " 0xe8 " , " 0xf " , " 0 " , " read " , " 3 " , " 0 " , " 0x001D0000 "
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 " Module Name " , " nand_timing "
" Base Address " , " 0x10000000 "
" Priority " , " 3 "
" Execution Required for Standby Wakeup " , " N "
" Execution Required for Normal Boot " , " Y "
" Register " , " Offset Address " , " Value Written to or Read from Register " , " delay " , " Read or Write " , " Bits to Be Read or Written " , " Start Bit to Be Read or Written " , " Register Attribute "
" NFC_PWIDTH " , " 0x4 " , " 0xaaa " , " 0 " , " write " , " 11 " , " 0 " , " 0x0000005D "
,,,,,,,
 " Module Name " , " normal "
" Base Address " , " 0x20050000 "
" Priority " , " 4 "
" Execution Required for Standby Wakeup " , " N "
" Execution Required for Normal Boot " , " Y "
" Register " , " Offset Address " , " Value Written to or Read from Register " , " delay " , " Read or Write " , " Bits to Be Read or Written " , " Start Bit to Be Read or Written " , " Register Attribute "
" SC_PLLCTRL " , " 0x14 " , " 0x0fff8000 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" SC_CTRL " , " 0 " , " 0x4 " , " 0 " , " write " , " 2 " , " 0 " , " 0x00000015 "
" SC_CTRL " , " 0 " , " 0x4 " , " 0 " , " read " , " 3 " , " 3 " , " 0x181D0000 "
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 " Module Name " , " ddrc_init "
" Base Address " , " 0x20110000 "
" Priority " , " 5 "
" Execution Required for Standby Wakeup " , " N "
" Execution Required for Normal Boot " , " Y "
" Register " , " Offset Address " , " Value Written to or Read from Register " , " delay " , " Read or Write " , " Bits to Be Read or Written " , " Start Bit to Be Read or Written " , " Register Attribute "
" NULL " , " 0 " , " 0 " , " 10000 " , " none " , " 0 " , " 0 " , " 0x0 "
" DDRC_IOCFG " , " 0x570 " , " 0x4e7 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_IOCFG " , " 0x574 " , " 0x4e7 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_PHYSRST " , " 0x4f0 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_CDLLCFG " , " 0x430 " , " 0x52 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_CDLLCFG " , " 0x434 " , " 0x52 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_QDLLCFG " , " 0x440 " , " 0x52 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_QDLLCFG " , " 0x444 " , " 0x52 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_QDLLCFG " , " 0x448 " , " 0x52 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_QDLLCFG " , " 0x44c " , " 0x52 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_QDLLCFG " , " 0x450 " , " 0x52 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_QDLLCFG " , " 0x454 " , " 0x52 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_QDLLCFG " , " 0x458 " , " 0x52 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_QDLLCFG " , " 0x45c " , " 0x52 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_QDLLCFG " , " 0x460 " , " 0x52 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_QDLLCFG " , " 0x464 " , " 0x52 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" NULL " , " 0x0 " , " 0 " , " 10000 " , " none " , " 0 " , " 0 " , " 0x0 "
" DDRC_CDLLCFG " , " 0x430 " , " 0x53 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_CDLLCFG " , " 0x434 " , " 0x53 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_QDLLCFG " , " 0x440 " , " 0x53 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_QDLLCFG " , " 0x444 " , " 0x53 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_QDLLCFG " , " 0x448 " , " 0x53 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_QDLLCFG " , " 0x44c " , " 0x53 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_QDLLCFG " , " 0x450 " , " 0x53 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_QDLLCFG " , " 0x454 " , " 0x53 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_QDLLCFG " , " 0x458 " , " 0x53 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_QDLLCFG " , " 0x45c " , " 0x53 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_QDLLCFG " , " 0x460 " , " 0x53 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_QDLLCFG " , " 0x464 " , " 0x53 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_PHYSRST " , " 0x4f0 " , " 0x1 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" NULL " , " 0x0 " , " 0 " , " 10000 " , " none " , " 0 " , " 0 " , " 0x0 "
" DDRC_TIMING2 " , " 0x58 " , " 0x83510000 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_CTRL " , " 0x10 " , " 0x1 " , " 0 " , " write " , " 0 " , " 0 " , " 0x00000005 "
" NULL " , " 0 " , " 0 " , " 10000 " , " none " , " 0 " , " 0 " , " 0x0 "
" DDRC_SREFCTRL " , " 0x4 " , " 0 " , " 1000 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_STATUS " , " 0x0 " , " 0x0 " , " 0 " , " read " , " 0 " , " 2 " , " 0x10050000 "
" DDRC_EMRS01 " , " 0x14 " , " 0x61b50 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_EMRS23 " , " 0x18 " , " 0x10 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_CONFIG0 " , " 0x1c " , " 0x80000610 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_CONFIG1 " , " 0x20 " , " 0x785 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_RNKCFG " , " 0x2c " , " 0x132 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_BASEADDR " , " 0x40 " , " 0x80000000 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_TIMING0 " , " 0x50 " , " 0xc455120c " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_TIMING1 " , " 0x54 " , " 0xff527932 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_TIMING2 " , " 0x58 " , " 0x83510096 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_TIMING3 " , " 0x5c " , " 0xffdff6f4 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_DTRCTRL " , " 0xac " , " 0xf000703 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_ODTCFG " , " 0xf4 " , " 0x1 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_PHYCFG " , " 0x400 " , " 0x2 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_INITCTRL " , " 0x8 " , " 0x1 " , " 1000 " , " write " , " 0 " , " 0 " , " 0x00000005 "
" DDRC_INITCTRL " , " 0x8 " , " 0x0 " , " 0 " , " read " , " 0 " , " 0 " , " 0x00050000 "
" DDRC_DTRSTATUS " , " 0xd4 " , " 0xf00 " , " 0 " , " read " , " 11 " , " 0 " , " 0x005D0000 "
,,,,,,,
,,,,,,,
,,,,,,,
 " Module Name " , " standby_pin_ctrl "
" Base Address " , " 0x200f0000 "
" Priority " , " 6 "
" Execution Required for Standby Wakeup " , " N "
" Execution Required for Normal Boot " , " Y "
" Register " , " Offset Address " , " Value Written to or Read from Register " , " delay " , " Read or Write " , " Bits to Be Read or Written " , " Start Bit to Be Read or Written " , " Register Attribute "
" muxctrl_reg57 " , " 0xe4 " , " 0x3 " , " 0 " , " write " , " 1 " , " 0 " , " 0x0000000D "
" muxctrl_reg58 " , " 0xe8 " , " 0x3 " , " 0 " , " write " , " 1 " , " 0 " , " 0x0000000D "
" muxctrl_reg59 " , " 0xec " , " 0x3 " , " 0 " , " write " , " 1 " , " 0 " , " 0x0000000D "
" muxctrl_reg60 " , " 0xf0 " , " 0x3 " , " 0 " , " write " , " 1 " , " 0 " , " 0x0000000D "
" muxctrl_reg61 " , " 0xf4 " , " 0x3 " , " 0 " , " write " , " 1 " , " 0 " , " 0x0000000D "
" muxctrl_reg62 " , " 0xf8 " , " 0x3 " , " 0 " , " write " , " 1 " , " 0 " , " 0x0000000D "
" muxctrl_reg63 " , " 0xfc " , " 0x3 " , " 0 " , " write " , " 1 " , " 0 " , " 0x0000000D "
" muxctrl_reg64 " , " 0x100 " , " 0x3 " , " 0 " , " write " , " 1 " , " 0 " , " 0x0000000D "
" muxctrl_reg65 " , " 0x104 " , " 0x3 " , " 0 " , " write " , " 1 " , " 0 " , " 0x0000000D "
" muxctrl_reg88 " , " 0x160 " , " 0x1 " , " 0 " , " write " , " 1 " , " 0 " , " 0x0000000D "
" muxctrl_reg89 " , " 0x164 " , " 0x0 " , " 0 " , " write " , " 1 " , " 0 " , " 0x0000000D "
" muxctrl_reg90 " , " 0x168 " , " 0x1 " , " 0 " , " write " , " 1 " , " 0 " , " 0x0000000D "
" muxctrl_reg91 " , " 0x16c " , " 0x1 " , " 0 " , " write " , " 1 " , " 0 " , " 0x0000000D "
" muxctrl_reg107 " , " 0x1ac " , " 0x1 " , " 0 " , " write " , " 0 " , " 0 " , " 0x00000005 "
" muxctrl_reg108 " , " 0x1b0 " , " 0x1 " , " 0 " , " write " , " 0 " , " 0 " , " 0x00000005 "
" muxctrl_reg109 " , " 0x1b4 " , " 0x1 " , " 0 " , " write " , " 0 " , " 0 " , " 0x00000005 "
" muxctrl_reg110 " , " 0x1b8 " , " 0x1 " , " 0 " , " write " , " 0 " , " 0 " , " 0x00000005 "
" muxctrl_reg113 " , " 0x1c4 " , " 0x1 " , " 0 " , " write " , " 0 " , " 0 " , " 0x00000005 "
" muxctrl_reg114 " , " 0x1c8 " , " 0x1 " , " 0 " , " write " , " 0 " , " 0 " , " 0x00000005 "
" muxctrl_reg115 " , " 0x1cc " , " 0x1 " , " 0 " , " write " , " 0 " , " 0 " , " 0x00000005 "
" muxctrl_reg116 " , " 0x1d0 " , " 0x1 " , " 0 " , " write " , " 0 " , " 0 " , " 0x00000005 "
" muxctrl_reg117 " , " 0x1d4 " , " 0x1 " , " 0 " , " write " , " 0 " , " 0 " , " 0x00000005 "
" muxctrl_reg118 " , " 0x1d8 " , " 0x1 " , " 0 " , " write " , " 0 " , " 0 " , " 0x00000005 "
,,,,,,,
,,,,,,,
,,,,,,,
,,,,,,,
,,,,,,,
,,,,,,,
 " Module Name " , " eth_phy_reset "
" Base Address " , " 0x20050000 "
" Priority " , " 7 "
" Execution Required for Standby Wakeup " , " N "
" Execution Required for Normal Boot " , " Y "
" Register " , " Offset Address " , " Value Written to or Read from Register " , " delay " , " Read or Write " , " Bits to Be Read or Written " , " Start Bit to Be Read or Written " , " Register Attribute "
" periphctrl51 " , " 0x100 " , " 0xcfcfcfcf " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" periphctrl52 " , " 0x104 " , " 0xcfcf " , " 0 " , " write " , " 15 " , " 0 " , " 0x0000007D "
,,,,,,,
,,,,,,,
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,,,,,,,
 " nand flash " ,,,,,,,, " spi flash " ,,,,,,,, " emmc flash " ,,,,,,
" name " , " ID " , " chip size " , " erase size " , " page size " , " oob size " , " ecc type " ,, " name " , " jedec_id " , " ext_id " , " block_size " , " chip_size " , " clk " , " chip select "
" MT29F16G08CBABx-4K-24bit1K " , " 0x2C 0x48 0x04 0x46 0x85 0x00 0x00 0x00 " , " 2GB " , " 1MB " , " 4KB " , " 224B " , " 4 " ,, " mx25l1655d " , " 0xc2 0x26 0x15 " , " 0x0 " , " 65536 " , " 2097152 " , " 0x40100 " , " 1 "
" NAND01GW3B2CN6 " , " 0x20 0xF1 0x00 0x1D 0x20 0xF1 0x00 0x1D " , " 128MB " , " 128KB " , " 2KB " , " 64B " , " 1 " ,, " w25x16 " , " 0xef 0x30 0x15 " , " 0x0 " , " 65536 " , " 2097152 " , " 0x40100 " , " 1 "
" K9F1G0bU0C " , " 0xEC 0xF1 0x00 0x95 0x40 0x00 0xEC 0xF1 " , " 128MB " , " 128KB " , " 2KB " , " 64B " , " 1 " ,, " s25sl032a " , " 0x01 0x02 0x15 " , " 0x0 " , " 65536 " , " 4194304 " , " 0x40100 " , " 1 "
" K9F2G08U0B " , " 0xEC 0xDA 0x10 0x95 0x44 0xEC 0xEC 0xDA " , " 256MB " , " 128KB " , " 2KB " , " 64B " , " 1 " ,, " s25sl064a " , " 0x01 0x02 0x16 " , " 0x0 " , " 65536 " , " 8388608 " , " 0x40100 " , " 1 "
" HY27UF082G2B " , " 0xAD 0xDA 0x10 0x95 0x44 0xAD 0xDA 0x10 " , " 256MB " , " 128KB " , " 2KB " , " 64B " , " 1 " ,, " s25sl12800 " , " 0x01 0x20 0x18 " , " 0x03 0x00 " , " 262144 " , " 16777216 " , " 0x60100 " , " 1 "
" K9F4G08U0B " , " 0xEC 0xDC 0x10 0x95 0x54 0xEC 0xEC 0xDC " , " 512MB " , " 128KB " , " 2KB " , " 64B " , " 1 " ,, " m25px16 " , " 0x20 0x71 0x15 " , " 0x0 " , " 65536 " , " 2097152 " , " 0x40100 " , " 1 "
" HY27UF084G2B " , " 0xAD 0xDC 0x10 0x95 0x54 0xAD 0xDC 0x10 " , " 512MB " , " 128KB " , " 2KB " , " 64B " , " 1 " ,, " m25px32 " , " 0x20 0x71 0x16 " , " 0x0 " , " 65536 " , " 4194304 " , " 0x40100 " , " 1 "
" 29F4G08ABADA " , " 0x2C 0xDC 0x90 0x95 0x56 0x00 0x00 0x00 " , " 512MB " , " 128KB " , " 2KB " , " 64B " , " 1 " ,, " m25px64 " , " 0x20 0x71 0x17 " , " 0x0 " , " 65536 " , " 8388608 " , " 0x40100 " , " 1 "
" 29F1G08ABADA " , " 0x2C 0xF1 0x80 0x95 0x02 0x00 0x00 0x00 " , " 128MB " , " 128KB " , " 2KB " , " 64B " , " 1 " ,, " m25p32 " , " 0x20 0x20 0x16 " , " 0x0 " , " 65536 " , " 4194304 " , " 0x40100 " , " 1 "
" HY27UF081G2A " , " 0xAD 0xF1 0x80 0x1D 0xAD 0xF1 0x80 0x1D " , " 128MB " , " 128KB " , " 2KB " , " 64B " , " 1 " ,, " m25p128 " , " 0x20 0x20 0x18 " , " 0x0 " , " 262144 " , " 16777216 " , " 0x40100 " , " 1 "


uboot_tools.zip > uboot-Hi3520A-bvt_No1_930_310_620_ddr_NO1.xls

,,,,
, " Boot V1.0 " ,,
, " Hisilicon Technologies Co., Ltd. All rights reserved. @2012 " ,,
,,,,,,,,
" Basic Project Information " ,,,,
,,,,
" Project Name " , " xxx " ,, " Project Version " , " 1.0 "
" Project Start Time " , " 40543 " ,, " Development " , " xxx "
" Product Line " , " Media " ,, " Department " , " Media "
" Project Description " , " Project description " ,,,
 " Module Name " , " slow "
" Base Address " , " 0x20050000 "
" Priority " , " 1 "
" Execution Required for Standby Wakeup " , " N "
" Execution Required for Normal Boot " , " Y "
" Register " , " Offset Address " , " Value Written to or Read from Register " , " delay " , " Read or Write " , " Bits to Be Read or Written " , " Start Bit to Be Read or Written " , " Register Attribute "
" SC_CTRL " , " 0 " , " 0x2 " , " 0 " , " write " , " 2 " , " 0 " , " 0x00000015 "
" SC_CTRL " , " 0 " , " 0x2 " , " 0 " , " read " , " 3 " , " 3 " , " 0x181D0000 "
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,,,,,,,
,,,,,,,
 " Module Name " , " pll "
" Base Address " , " 0x20030000 "
" Priority " , " 2 "
" Execution Required for Standby Wakeup " , " N "
" Execution Required for Normal Boot " , " Y " ,,,,,,
" Register " , " Offset Address " , " Value Written to or Read from Register " , " delay " , " Read or Write " , " Bits to Be Read or Written " , " Start Bit to Be Read or Written " , " Register Attribute "
" PERI_CRG0 " , " 0x0 " , " 0x09000000 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" PERI_CRG1 " , " 0x4 " , " 0x006c209b " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" PERI_CRG2 " , " 0x8 " , " 0x24000000 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" PERI_CRG3 " , " 0xc " , " 0x006c2063 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" PERI_CRG58 " , " 0xe8 " , " 0xf " , " 0 " , " read " , " 3 " , " 0 " , " 0x001D0000 "
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,,,,,,,
,,,,,,,
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 " Module Name " , " nand_timing "
" Base Address " , " 0x10000000 "
" Priority " , " 3 "
" Execution Required for Standby Wakeup " , " N "
" Execution Required for Normal Boot " , " Y "
" Register " , " Offset Address " , " Value Written to or Read from Register " , " delay " , " Read or Write " , " Bits to Be Read or Written " , " Start Bit to Be Read or Written " , " Register Attribute "
" NFC_PWIDTH " , " 0x4 " , " 0xaaa " , " 0 " , " write " , " 11 " , " 0 " , " 0x0000005D "
,,,,,,,
 " Module Name " , " normal "
" Base Address " , " 0x20050000 "
" Priority " , " 4 "
" Execution Required for Standby Wakeup " , " N "
" Execution Required for Normal Boot " , " Y "
" Register " , " Offset Address " , " Value Written to or Read from Register " , " delay " , " Read or Write " , " Bits to Be Read or Written " , " Start Bit to Be Read or Written " , " Register Attribute "
" SC_PLLCTRL " , " 0x14 " , " 0x0fff8000 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" SC_CTRL " , " 0 " , " 0x4 " , " 0 " , " write " , " 2 " , " 0 " , " 0x00000015 "
" SC_CTRL " , " 0 " , " 0x4 " , " 0 " , " read " , " 3 " , " 3 " , " 0x181D0000 "
,,,,,,,
,,,,,,,
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 " Module Name " , " ddrc_init "
" Base Address " , " 0x20110000 "
" Priority " , " 5 "
" Execution Required for Standby Wakeup " , " N "
" Execution Required for Normal Boot " , " Y "
" Register " , " Offset Address " , " Value Written to or Read from Register " , " delay " , " Read or Write " , " Bits to Be Read or Written " , " Start Bit to Be Read or Written " , " Register Attribute "
" NULL " , " 0 " , " 0 " , " 10000 " , " none " , " 0 " , " 0 " , " 0x0 "
" DDRC_IOCFG " , " 0x570 " , " 0x467 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_IOCFG " , " 0x574 " , " 0x467 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_PHYSRST " , " 0x4f0 " , " 0x0 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_CDLLCFG " , " 0x430 " , " 0x1052 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_CDLLCFG " , " 0x434 " , " 0x1052 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_QDLLCFG " , " 0x440 " , " 0x1052 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_QDLLCFG " , " 0x444 " , " 0x1052 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_QDLLCFG " , " 0x448 " , " 0x1052 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_QDLLCFG " , " 0x44c " , " 0x1052 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_QDLLCFG " , " 0x450 " , " 0x1052 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_QDLLCFG " , " 0x454 " , " 0x1052 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_QDLLCFG " , " 0x458 " , " 0x1052 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_QDLLCFG " , " 0x45c " , " 0x1052 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_QDLLCFG " , " 0x460 " , " 0x1052 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_QDLLCFG " , " 0x464 " , " 0x1052 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" NULL " , " 0x0 " , " 0 " , " 10000 " , " none " , " 0 " , " 0 " , " 0x0 "
" DDRC_CDLLCFG " , " 0x430 " , " 0x1053 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_CDLLCFG " , " 0x434 " , " 0x1053 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_QDLLCFG " , " 0x440 " , " 0x1053 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_QDLLCFG " , " 0x444 " , " 0x1053 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_QDLLCFG " , " 0x448 " , " 0x1053 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_QDLLCFG " , " 0x44c " , " 0x1053 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_QDLLCFG " , " 0x450 " , " 0x1053 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_QDLLCFG " , " 0x454 " , " 0x1053 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_QDLLCFG " , " 0x458 " , " 0x1053 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_QDLLCFG " , " 0x45c " , " 0x1053 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_QDLLCFG " , " 0x460 " , " 0x1053 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_QDLLCFG " , " 0x464 " , " 0x1053 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_PHYSRST " , " 0x4f0 " , " 0x1 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" NULL " , " 0x0 " , " 0 " , " 10000 " , " none " , " 0 " , " 0 " , " 0x0 "
" DDRC_TIMING2 " , " 0x58 " , " 0x83510000 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_CTRL " , " 0x10 " , " 0x1 " , " 0 " , " write " , " 0 " , " 0 " , " 0x00000005 "
" NULL " , " 0 " , " 0 " , " 10000 " , " none " , " 0 " , " 0 " , " 0x0 "
" DDRC_SREFCTRL " , " 0x4 " , " 0 " , " 1000 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_STATUS " , " 0x0 " , " 0x0 " , " 0 " , " read " , " 0 " , " 2 " , " 0x10050000 "
" DDRC_EMRS01 " , " 0x14 " , " 0x61b50 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_EMRS23 " , " 0x18 " , " 0x10 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_CONFIG0 " , " 0x1c " , " 0x80000600 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_CONFIG1 " , " 0x20 " , " 0x785 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_RNKCFG " , " 0x2c " , " 0x132 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_BASEADDR " , " 0x40 " , " 0x80000000 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_TIMING0 " , " 0x50 " , " 0xc455120c " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_TIMING1 " , " 0x54 " , " 0xff527932 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_TIMING2 " , " 0x58 " , " 0x83510096 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_TIMING3 " , " 0x5c " , " 0xffdff6f4 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_DTRCTRL " , " 0xac " , " 0x3000703 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_ODTCFG " , " 0xf4 " , " 0x1 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_PHYCFG " , " 0x400 " , " 0x2 " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" DDRC_INITCTRL " , " 0x8 " , " 0x1 " , " 1000 " , " write " , " 0 " , " 0 " , " 0x00000005 "
" DDRC_INITCTRL " , " 0x8 " , " 0x0 " , " 0 " , " read " , " 0 " , " 0 " , " 0x00050000 "
" DDRC_DTRSTATUS " , " 0xd4 " , " 0x300 " , " 0 " , " read " , " 11 " , " 0 " , " 0x005D0000 "
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 " Module Name " , " standby_pin_ctrl "
" Base Address " , " 0x200f0000 "
" Priority " , " 6 "
" Execution Required for Standby Wakeup " , " N "
" Execution Required for Normal Boot " , " Y "
" Register " , " Offset Address " , " Value Written to or Read from Register " , " delay " , " Read or Write " , " Bits to Be Read or Written " , " Start Bit to Be Read or Written " , " Register Attribute "
" muxctrl_reg57 " , " 0xe4 " , " 0x3 " , " 0 " , " write " , " 1 " , " 0 " , " 0x0000000D "
" muxctrl_reg58 " , " 0xe8 " , " 0x3 " , " 0 " , " write " , " 1 " , " 0 " , " 0x0000000D "
" muxctrl_reg59 " , " 0xec " , " 0x3 " , " 0 " , " write " , " 1 " , " 0 " , " 0x0000000D "
" muxctrl_reg60 " , " 0xf0 " , " 0x3 " , " 0 " , " write " , " 1 " , " 0 " , " 0x0000000D "
" muxctrl_reg61 " , " 0xf4 " , " 0x3 " , " 0 " , " write " , " 1 " , " 0 " , " 0x0000000D "
" muxctrl_reg62 " , " 0xf8 " , " 0x3 " , " 0 " , " write " , " 1 " , " 0 " , " 0x0000000D "
" muxctrl_reg63 " , " 0xfc " , " 0x3 " , " 0 " , " write " , " 1 " , " 0 " , " 0x0000000D "
" muxctrl_reg64 " , " 0x100 " , " 0x3 " , " 0 " , " write " , " 1 " , " 0 " , " 0x0000000D "
" muxctrl_reg65 " , " 0x104 " , " 0x3 " , " 0 " , " write " , " 1 " , " 0 " , " 0x0000000D "
" muxctrl_reg88 " , " 0x160 " , " 0x1 " , " 0 " , " write " , " 1 " , " 0 " , " 0x0000000D "
" muxctrl_reg89 " , " 0x164 " , " 0x0 " , " 0 " , " write " , " 1 " , " 0 " , " 0x0000000D "
" muxctrl_reg90 " , " 0x168 " , " 0x1 " , " 0 " , " write " , " 1 " , " 0 " , " 0x0000000D "
" muxctrl_reg91 " , " 0x16c " , " 0x1 " , " 0 " , " write " , " 1 " , " 0 " , " 0x0000000D "
" muxctrl_reg107 " , " 0x1ac " , " 0x1 " , " 0 " , " write " , " 0 " , " 0 " , " 0x00000005 "
" muxctrl_reg108 " , " 0x1b0 " , " 0x1 " , " 0 " , " write " , " 0 " , " 0 " , " 0x00000005 "
" muxctrl_reg109 " , " 0x1b4 " , " 0x1 " , " 0 " , " write " , " 0 " , " 0 " , " 0x00000005 "
" muxctrl_reg110 " , " 0x1b8 " , " 0x1 " , " 0 " , " write " , " 0 " , " 0 " , " 0x00000005 "
" muxctrl_reg113 " , " 0x1c4 " , " 0x1 " , " 0 " , " write " , " 0 " , " 0 " , " 0x00000005 "
" muxctrl_reg114 " , " 0x1c8 " , " 0x1 " , " 0 " , " write " , " 0 " , " 0 " , " 0x00000005 "
" muxctrl_reg115 " , " 0x1cc " , " 0x1 " , " 0 " , " write " , " 0 " , " 0 " , " 0x00000005 "
" muxctrl_reg116 " , " 0x1d0 " , " 0x1 " , " 0 " , " write " , " 0 " , " 0 " , " 0x00000005 "
" muxctrl_reg117 " , " 0x1d4 " , " 0x1 " , " 0 " , " write " , " 0 " , " 0 " , " 0x00000005 "
" muxctrl_reg118 " , " 0x1d8 " , " 0x1 " , " 0 " , " write " , " 0 " , " 0 " , " 0x00000005 "
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 " Module Name " , " eth_phy_reset "
" Base Address " , " 0x20050000 "
" Priority " , " 7 "
" Execution Required for Standby Wakeup " , " N "
" Execution Required for Normal Boot " , " Y "
" Register " , " Offset Address " , " Value Written to or Read from Register " , " delay " , " Read or Write " , " Bits to Be Read or Written " , " Start Bit to Be Read or Written " , " Register Attribute "
" periphctrl51 " , " 0x100 " , " 0xcfcfcfcf " , " 0 " , " write " , " 31 " , " 0 " , " 0x0000000FD "
" periphctrl52 " , " 0x104 " , " 0xcfcf " , " 0 " , " write " , " 15 " , " 0 " , " 0x0000007D "
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 " nand flash " ,,,,,,,, " spi flash " ,,,,,,,, " emmc flash " ,,,,,,
" name " , " ID " , " chip size " , " erase size " , " page size " , " oob size " , " ecc type " ,, " name " , " jedec_id " , " ext_id " , " block_size " , " chip_size " , " clk " , " chip select "
" MT29F16G08CBABx-4K-24bit1K " , " 0x2C 0x48 0x04 0x46 0x85 0x00 0x00 0x00 " , " 2GB " , " 1MB " , " 4KB " , " 224B " , " 4 " ,, " mx25l1655d " , " 0xc2 0x26 0x15 " , " 0x0 " , " 65536 " , " 2097152 " , " 0x40100 " , " 1 "
" NAND01GW3B2CN6 " , " 0x20 0xF1 0x00 0x1D 0x20 0xF1 0x00 0x1D " , " 128MB " , " 128KB " , " 2KB " , " 64B " , " 1 " ,, " w25x16 " , " 0xef 0x30 0x15 " , " 0x0 " , " 65536 " , " 2097152 " , " 0x40100 " , " 1 "
" K9F1G0bU0C " , " 0xEC 0xF1 0x00 0x95 0x40 0x00 0xEC 0xF1 " , " 128MB " , " 128KB " , " 2KB " , " 64B " , " 1 " ,, " s25sl032a " , " 0x01 0x02 0x15 " , " 0x0 " , " 65536 " , " 4194304 " , " 0x40100 " , " 1 "
" K9F2G08U0B " , " 0xEC 0xDA 0x10 0x95 0x44 0xEC 0xEC 0xDA " , " 256MB " , " 128KB " , " 2KB " , " 64B " , " 1 " ,, " s25sl064a " , " 0x01 0x02 0x16 " , " 0x0 " , " 65536 " , " 8388608 " , " 0x40100 " , " 1 "
" HY27UF082G2B " , " 0xAD 0xDA 0x10 0x95 0x44 0xAD 0xDA 0x10 " , " 256MB " , " 128KB " , " 2KB " , " 64B " , " 1 " ,, " s25sl12800 " , " 0x01 0x20 0x18 " , " 0x03 0x00 " , " 262144 " , " 16777216 " , " 0x60100 " , " 1 "
" K9F4G08U0B " , " 0xEC 0xDC 0x10 0x95 0x54 0xEC 0xEC 0xDC " , " 512MB " , " 128KB " , " 2KB " , " 64B " , " 1 " ,, " m25px16 " , " 0x20 0x71 0x15 " , " 0x0 " , " 65536 " , " 2097152 " , " 0x40100 " , " 1 "
" HY27UF084G2B " , " 0xAD 0xDC 0x10 0x95 0x54 0xAD 0xDC 0x10 " , " 512MB " , " 128KB " , " 2KB " , " 64B " , " 1 " ,, " m25px32 " , " 0x20 0x71 0x16 " , " 0x0 " , " 65536 " , " 4194304 " , " 0x40100 " , " 1 "
" 29F4G08ABADA " , " 0x2C 0xDC 0x90 0x95 0x56 0x00 0x00 0x00 " , " 512MB " , " 128KB " , " 2KB " , " 64B " , " 1 " ,, " m25px64 " , " 0x20 0x71 0x17 " , " 0x0 " , " 65536 " , " 8388608 " , " 0x40100 " , " 1 "
" 29F1G08ABADA " , " 0x2C 0xF1 0x80 0x95 0x02 0x00 0x00 0x00 " , " 128MB " , " 128KB " , " 2KB " , " 64B " , " 1 " ,, " m25p32 " , " 0x20 0x20 0x16 " , " 0x0 " , " 65536 " , " 4194304 " , " 0x40100 " , " 1 "
" HY27UF081G2A " , " 0xAD 0xF1 0x80 0x1D 0xAD 0xF1 0x80 0x1D " , " 128MB " , " 128KB " , " 2KB " , " 64B " , " 1 " ,, " m25p128 " , " 0x20 0x20 0x18 " , " 0x0 " , " 262144 " , " 16777216 " , " 0x40100 " , " 1 "