Telewizor United LED32BH55. Uszkodzony zasilacz w wyniku burzy. Sterownikiem tranzystora kluczującego zasilacza jest nietypowy układ Pxt 30R AP, który jest uszkodzony. Po rozrysowaniu pinów stwierdziłem, że układ ma taką samą "pinologię" jak układ AP3105. Tu jest schemat jego przeróbki na układ NCP1207. https://www.elektroda.pl/rtvforum/topic3658883.html#18461184 Oczywiście do sprawdzenia jeszcze wszystkie elementy koło układu scalonego, tranzystora kluczującego, transoptora i układu TL431. Kolega "tenap" Przysłał mi takie pliki, dodaje je do posta. T30R=LD5530R (bardzo dziękuję)
LD5530R
10/8/2013
Green-Mode PWM Controller with Frequency Swapping
and Integrated Protections
Rev. 01
General Description
Features
The LD5530R is built-in with several functions, protection
and EMI-improved solution in a tiny package. It takes less
High-Voltage CMOS Process with Excellent ESD
protection
components counts or circuit space, especially ideal for
Very Low Startup Current ( & lt; 1A)
those total solutions of low cost.
Current Mode Control
Green Mode Control
UVLO (Under Voltage Lockout)
LEB (Leading-Edge Blanking) on CS Pin
Internal Frequency Swapping
Internal Slope Compensation
OVP (Over Voltage Protection) on Vcc Pin
Adjustment OVP(Over Voltage Protection) on CS Pin
Adjustment OCP(Over Current Protection) on CS Pin
OTP (Over Temperature Protection) through a NTC
OLP (Over Load Protection)
250/-500mA Driving Capability
The implemented functions include low startup current,
green-mode
power-saving
operation,
leading-edge
blanking of the current sensing and internal slope
compensation.
It also features more protections like
OLP (Over Load Protection) and OVP (Over Voltage
Protection) to prevent circuit damage occurred under
abnormal conditions.
Furthermore, the Frequency Swapping function is to
reduce the noise level and thus helps the power circuit
designers to easily deal with the EMI filter design by
spending minimum amount of component cost and
Applications
developing time.
Switching AC/DC Adaptor and Battery Charger
Open Frame Switching Power Supply
Typical Application
AC
input
DC
Output
EMI
Filter
VCC
OUT
OTP
LD5530R
CS/OVP
COMP
GND
1
Leadtrend Technology Corporation
LD5530R-DS-01
Oct. 2013
www.leadtrend.com.tw
photocoupler
LD5530R
Pin Configuration
SOT-26 (TOP VIEW)
GND
COMP
NC
OTP
DIP-8 (TOP VIEW)
8
7
6
5
OUT
VCC CS/OVP
6
5
4
30R
YWt pp
1
2
3
TOP MARK
YYWWPP
CS/OVP
NC
VCC
2
3
YYWWPP4
OUT
1
GND COMP OTP
YY, Y : Year code (D: 2004, E: 2005…..)
WW, W : Week code
PP
: Production code
t30R : LD5530R
Ordering Information
Part number
Package
Top Mark
Shipping
LD5530R GL
SOT-26
YWt/30R
3000 /tape & reel
LD5530R GN
DIP-8
LD5530R GN
3600 /tube /Carton
The LD5530R is ROHS compliant / Green Packaged
Protection Mode
Switching Freq.
OLP
VCC OVP
CS OVP
OTP Pin
65kHz
Auto recovery
Auto recovery
Auto recovery
Latch
Pin Descriptions
SOT-26
DIP-8
NAME
1
8
GND
2
7
COMP
FUNCTION
Ground
Voltage feedback pin (same as the COMP pin in UC384X). Connect a
photo-coupler to close the control loop and achieve the regulation.
Pull this pin below 0.95V to shut down the controller into latch mode until the
3
5
OTP
AC resumes power-on. Connecting this pin to ground with NTC will achieve
OTP protection. Let this pin float or connect a 100k resistor to disable the
latch protection.
Current sense pin, connect it to sense the MOSFET current. This pin is also
4
4
CS/OVP
connected to an auxiliary winding of the PWM transformer through a resistor
and a diode for output over-voltage protection.
5
2
VCC
Supply voltage pin
6
1
OUT
Gate drive output to drive the external MOSFET
2
Leadtrend Technology Corporation
LD5530R-DS-01
Oct. 2013
LD5530R
Block Diagram
VCC
Latch
UVLO
Comparator
All
Blocks
internal bias
& Vref
16.0V/
7.5V
Latch
VCC OK
VCC OVP
Comparator
VCC OVP
PG
Latch
Vref OK
Int.OSC
28.5V
Protection
VCC OVP
Driver
Stage
OUT
GreenMode
Control
Vbias
S
Q
PWM
Comparator
COMP
VF
R
2R
R
+
+
Leading
Edge
Blanking
0.85V
Slope
Compensation
VBIAS
Duty
OCP
Comparator
OUT
CS
OLP
Comparator
OLP
Protection
OLP Delay
Counter
4.5V
S
PG
Q
R
Sample
Vbias
GND
100 uA
Delay
CS OVP
0.2V
OTP Latch
Comparator
OTP
OUT
OTP
1.05V/
0.95V
CS OVP
OTP
S
PG
3
Leadtrend Technology Corporation
LD5530R-DS-01
Oct. 2013
R
Q
Protection/
Latch
LD5530R
Absolute Maximum Ratings
Supply Voltage VCC
-0.3V ~30V
COMP, OTP, CS
-0.3V ~6V
OUT
-0.3V ~Vcc+0.3V
Maximum Junction Temperature
150C
Storage Temperature Range
-65C to 150C
Package Thermal Resistance (SOT-26, JA)
200C/W
Package Thermal Resistance (DIP-8, JA)
100C/W
Power Dissipation (SOT-26, at Ambient Temperature = 85C)
200mW
Power Dissipation (DIP-8, at Ambient Temperature = 85C)
400mW
Lead temperature (Soldering, 10sec)
260C
ESD Voltage Protection, Human Body Model
2.5 KV
ESD Voltage Protection, Machine Model
250 V
Caution:
Stress exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stress above Recommended Operating Conditions may affect
device reliability
Recommended Operating Conditions
Item
Min.
Max.
Unit
Operating Ambient Temperature
-40
85
C
Operating Junction Temperature
-40
125
C
Supply VCC Voltage
8.0
26.5
V
VCC Capacitor
3.3
10
F
400K
2M
Comp Pin Capacitor
1
10
nF
CS Pin Capacitor Value
47
390
pF
Start-up resistor Value (AC Side, Half Wave)
Note:
1.
It’s essential to connect VCC pin with a SMD ceramic capacitor (0.1F~0.47F) to
filter out the undesired switching noise for stable operation. This capacitor should be
placed close to IC pin as possible
2.
Connecting a capacitor to COMP pin is also essential to filter out the undesired
switching noise for stable operation.
3.
The small signal components should be placed close to IC pin as possible.
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Leadtrend Technology Corporation
LD5530R-DS-01
Oct. 2013
LD5530R
Electrical Characteristics
(TA = +25C unless otherwise stated, VCC=15.0V)
PARAMETER
CONDITIONS
SYM.
MIN
TYP
MAX
UNITS
VCC & lt; UVLO (ON)
ICC-ST
---
0.6
1
A
VCOMP=3V
ICC-OP1
1.7
1.85
2.1
mA
VCOMP=0V
ICC-OP2
0.53
0.65
0.77
mA
ICC-OPA
0.48
0.52
0.64
ICC-OPL1
0.70
0.83
0.98
mA
Vcc-PDR
3.7
4.3
5.1
V
ICC-OPL2
360
450
540
A
ICC-OPL3
20
25
29
A
VCC-OFF
7.0
7.5
8.0
V
UVLO (on)
VCC-ON
15
16
17
V
VCC OVP Level
VCC-OVP
27.5
28.5
29.5
V
Supply Voltage (Vcc Pin)
Startup Current
Operating Current
(with 1nF load on OUT pin)
OLP/OVP Tripped / Auto,
OTP=3V
OTP Pin Tripped / Latch
Latch-Off Release Voltage
VCC=10V (Latched)
Holding Current
VCC=Latch-Off Release
Voltage+0.2V
UVLO (off)
OUT OFF
mA
mA
VCC OVP De-bounce time
*
TD-VCCOVP
---
8
---
cycle
VCC OSCP
COMP & gt; 4.6V
VCC-OSCP
---
9
---
V
TD-OSCP
---
15
---
ms
ICOMP
0.10
0.125
0.15
mA
VCOMP-OPEN
4.75
5
5.25
V
VG
---
2.1
---
V
Zero Duty Threshold VCOMP
VZDC
1.5
1.6
1.7
V
Zero Duty Hysteresis
VZDCH
70
100
130
mV
VCS-MAX
0.837
0.85
0.863
V
IOCP
234
240
246
A
TLEB
250
300
400
ns
VSLP-L
---
300
---
mV
VCC OSCP De-bounce Time
Voltage Feedback (Comp Pin)
Short Circuit Current
VCOMP=0V
Open Loop Voltage
COMP pin open
Green Mode Threshold VCOMP
*
Current Sensing (CS/OVP pin)
Maximum Input Voltage, VCS_OFF
Max.
OCP
Compensation
Current, IOCP
Leading Edge Blanking Time,
LEB
Internal Slope Compensation
*0% to DMAX. (Linearly
increase)
Input impedance
*
ZCS
1
---
---
M
Delay to Output
*
TPD
---
100
---
ns
Soft Start Duration
*
TSS
---
6.5
---
ms
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Leadtrend Technology Corporation
LD5530R-DS-01
Oct. 2013
LD5530R
PARAMETER
CONDITIONS
SYM.
MIN
TYP
MAX
UNITS
VCSOVP
0.186
0.2
0.214
V
TD-CSOVP
---
8
---
Cycle
FSW
63
65
67
kHz
FSW-GREEN
21.5
25
28
FSW-MOD
---
5.0
---
kHz
Over Voltage Protection (CS/OVP pin)
OVP Trip Current Level
De-bounce Cycle
*
Oscillator for Switching Frequency
Frequency, FREQ
Green
Mode
Frequency,
FREQG
kHz
Frequency Swapping
VCOMP & gt; 3V
Temp. Stability
(-20C ~85C)*
FSW-TS
0
5
---
%
Voltage Stability
(VCC=11V-25V)*
FSW-VS
0
1
---
%
Gate Drive Output (OUT Pin)
Output Low Level
VCC=15V, Io=20mA
VOL
---
---
1
V
Output High Level
VCC=15V, Io=20mA
VOH
8
---
15
V
Output High Clamp Level
VCC=20V
VO-CLAMP
13
15
17
V
Tr
---
150
250
ns
Tf
---
50
75
ns
MXD
71
75
79
%
VOLP
4.3
4.5
4.7
V
TD-OLPSS
---
71.5
---
ms
TD-OLP
60
65
70
ms
OTP Pin Source Current
IOTP
93
100
107
A
OTP Turn-On Trip Level
VOTP-ON
1.00
1.05
1.10
V
OTP Turn-Off Trip Level
VOTP-OFF
0.9
0.95
1.0
V
Load
Rising Time
Capacitance=1000pF*
Load
Falling Time
Capacitance=1000pF*
Max. Duty
OLP (Over Load Protection)
OLP Trip Level
OLP Delay Time at start-up
OLP + Soft start*
OLP Delay Time after start-up
OTP Pin Latch Protection (OTP Pin)
OTP Turn-Off Trip Resistance
=VOTP-OFF/IOTP*
ROTP
8.75
9.5
10.25
OTP pin de-bounce time
VCOMP & gt; 3V
TD-OTP
400
500
600
s
OTP Tripped Level
*
TINOTP
---
140
---
C
OTP Hysteresis
*
TINOTP-HYS
---
30
---
C
Internal OTP Latch Protection
*: Guaranteed by design.
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Leadtrend Technology Corporation
LD5530R-DS-01
Oct. 2013
LD5530R
Typical Performance Characteristics
8.0
UVLO (off) (V)
8.5
17.2
UVLO (on) (V)
18.0
16.4
15.6
6.0
-40
40
0
Fig. 1
80
120 125
Fig. 2
80
120
125
120
125
UVLO (off ) vs. Temperature
29
Green Mode Frequency (KHz)
Frequency (KHz)
40
Temperature (C)
68
66
64
62
27
25
23
21
19
0
-40
40
80
120
125
-40
Fig. 4
80
Green Mode Frequency vs. Temperature
28
Green Mode Frequency (KHz)
70
68
66
64
62
60
11
40
0
Temperature (C)
Temperature (C)
Fig. 3 Frequency vs. Temperature
Frequency (KHz)
0
-40
Temperature (C)
UVLO (on) vs. Temperature
70
60
7.0
6.5
14.8
14.0
7.5
12
14
16
18
20
22
24
26
24
22
20
18
11
25
12
14
Vcc (V)
Fig. 6
7
LD5530R-DS-01
Oct. 2013
18
20
22
Vcc (V)
Fig. 5 Frequency vs. Vcc
Leadtrend Technology Corporation
16
Green Mode Frequency vs. Vcc
24
25
LD5530R
0.90
85
18
0.88
15
15
VCS (off) (V)
75
12
12
Y Axis Title
Y Axis Title
Max Duty (%)
80 18
70
0.86
0.84
99
65
0.82
66
60 3 3
-40
0
40
80
0.80
-40
120 125
0
40
Temperature (C)
0
-40
0
-20
-40
0
-20 Fig. 7
0
20
40
60
80
100
20
40
60
80
Max Axis Title Temperature
X Duty vs.
120
100
120
Fig. 8
80
120
125
Temperature (C)
VCS (off) vs. Temperature
X Axis Title
1.8
35
1.5
30
VCC OVP (V)
Istartup (A)
1.2
1
0.8
25
20
15
0.6
0.4
-40
10
0
40
80
120 125
-40
0
40
Temperature (C)
Fig. 9
Fig. 10
Startup Current (Istartup) vs. Temperature
120
125
6.0
5.0
5.5
VCC OVP vs. Temperature
6.0
4.5
OLP (V)
6.5
VCOMP (V)
80
Temperature (C)
5.0
4.5
4.0
4.0
3.5
-40
0
40
80
3.0
120 125
-40
0
Temperature (C)
Fig. 11
VCOMP open loop voltage vs. Temperature
Fig. 12
8
Leadtrend Technology Corporation
LD5530R-DS-01
Oct. 2013
40
80
Temperature (C)
OLP-Trip Level vs. Temperature
120
125
LD5530R
Application Information
Operation Overview
controller will help to increase the value of R1 and then
The LD5530R meets the green-power requirement and is
reduce the power consumption on R1. By using CMOS
intended for the use in those modern switching power
process and the special circuit design, the maximum
suppliers and adaptors which demand higher power
startup current for LD5530R is only 1A.
efficiency and power-saving. It integrated more functions
If a higher resistance value of the R1 is chosen, it will
to reduce the external components counts and the size.
usually take more time to start up. To carefully select the
Its major features are described as below.
value of R1 and C1 will optimize the power consumption
and startup time.
Under Voltage Lockout (UVLO)
AC
input
An UVLO comparator is implemented in it to detect the
EMI
Filter
voltage on the VCC pin. It would assure the supply
Cbulk
voltage enough to turn on the LD5530R PWM controller
and further to drive the power MOSFET.
As shown in Fig.
D1
R1
C1
13, a hysteresis is built in to prevent the shutdown from
the voltage dip during startup.
VCC
OUT
Vcc
LD5530R
UVLO(on)
CS/OVP
UVLO(off)
GND
Fig. 14
t
I(Vcc)
operating current
(~ mA)
Current
Sensing
and
Leading-edge
Blanking
startup current
(~uA)
The typical current mode of PWM controller feedbacks
t
both current signal and voltage signal to close the control
loop and achieve regulation. As shown in Fig. 15, the
Fig. 13
LD5530R detects the primary MOSFET current from the
Startup Current and Startup Circuit
CS pin, which is not only for the peak current mode
The typical startup circuit to generate VCC of the LD5530R
control but also for the pulse-by-pulse current limit. The
is shown in Fig. 14.
During the startup transient, the VCC
maximum voltage threshold of the current sensing pin is
is below UVLO threshold. Before it has sufficient voltage
set at 0.85V. From above, the MOSFET peak current can
to develop OUT pulse to drive the power MOSFET, R1 will
be obtained from below.
provide the startup current to charge the capacitor C1.
IPEAK (MAX)
Once VCC obtain enough voltage to turn on the LD5530R
and further to deliver the gate drive signal, it will enable
the auxiliary winding of the transformer to provide supply
current.
Lower startup current requirement on the PWM
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Leadtrend Technology Corporation
LD5530R-DS-01
Oct. 2013
0.85V
RS
LD5530R
Oscillator and Switching Frequency
The LD5530R is implemented with Frequency Swapping
function which helps the power supply designers to both
AC
Line
optimize EMI performance and lower system cost. The
switching frequency substantially centers at 65KHz, and
VCC
swap between a range of ±5KHz.
LEB time
OUT
Green-Mode Operation
LD5530R
By using the green-mode control, the switching frequency
can be reduced under the light load condition. This feature
CS/OVP
helps to improve the efficiency in light load conditions.
GND
RS
The green-mode control is Leadtrend Technology’s own
property. Fig. 16 shows the characteristics of the
Fig. 15
switching frequency vs. the comp pin voltage (VCOMP)
A leading-edge blanking (LEB) time is included in the
On/Off Control
input of CS pin to prevent the false-trigger from the current
The LD5530R can be turned off by pulling COMP pin
spike.
lower than 1.6V. The gate output pin of the LD5530R will
be disabled immediately under such condition. The
Output Stage and Maximum Duty-Cycle
off-mode can be released when the pull-low signal is
An output stage of a CMOS buffer, with typical
removed.
250/-500mA driving capability, is incorporated to drive a
power MOSFET directly.
Fs
And the maximum duty-cycle
65kHz
of LD5530R is limited to 75% to avoid the transformer
saturation.
Voltage Feedback Loop
25kHz
The voltage feedback signal is provided from the TL431 at
the secondary side through the photo-coupler to the
COMP pin of the LD5530R.
Similar to UC3842, the
1.6
LD5530R would carry a diode voltage offset at the stage
2.1
2.4 VCOMP(V)
Fig. 16
to feed the voltage divider at the ratio of RA and RB, that
is,
Internal Slope Compensation
R
( VCOMP VF )
R 2R
A pull-high resistor is embedded internally and can be
V(PWM COMPARATOR )
In the conventional applications, the problem of the
stability is a critical issue for current mode controlling,
when it operates over 50% duty-cycle. As UC384X, It
eliminated externally.
takes slope compensation from injecting the ramp signal
of the RT/CT pin through a coupling capacitor. It therefore
requires no extra design for the LD5530R since it has
integrated it already.
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Leadtrend Technology Corporation
LD5530R-DS-01
Oct. 2013
LD5530R
Adjustable
Over Current
over voltage protection. This delay time is used to ignore
Compensation
the voltage ringing from leakage inductance of PWM
(CS/OVP Pin)
transformer. The sampling voltage level is compared with
In general, the power converter can deliver more current
internal threshold voltage 0.2V. If the sampling voltage
at high input voltage than at low input voltage. To
exceeds the OVP trip level, an internal counter starts
compensate this, an offset voltage is added to the CS
counting subsequent OVP events. The counter has been
signal by an internal current source (IOCP) and an external
resistor (ROCP) in series between the sense resistor (Rs)
added to prevent incorrect OVP detection which might
and the CS/OVP pin, as shown in Fig. 17. By selecting a
occur during ESD or lightning events. However, when
proper value of the resistor in series with the CS pin, the
typically 8 cycles of subsequent OVP events are detected,
amount of compensation can be adjusted. The value of
the OVP circuit switches the power MOSFET off. As the
IOCP depends on the duty cycle of OUT pin. The equation
protection is auto recovery, the converter restarts after the
of IOCP is decreased as:
VCC is lower than UVLO OFF level and then recharge to
(0.625 Duty) 480uA(0.125 Duty 0.625)
IOCP 0uA
(Duty 0.625)
(Duty 0.125 )
240uA
UVLO ON.
Delay
Sample
AUX
In light load conditions, the offset should be removed
OVP
since it is in same order of magnitude as the current
OUT
sense signal. Therefore the compensation current is only
Debouce
8 cycle
CS
0.2V
ROCP
RS
fully added when the COMP voltage is higher than 2.9V.
ROCP:470~1.2k; COCP:47pF~390pF
Fig. 18
Out
0.85V
V BIAS
OCP
Comparator
IOCP
Duty/VCOMP
AUX Winding
OUT
CS/OVP
ROCP
LEB
COCP
RS
Sample
Delay
Fig. 17
CS/OVP
Output Over Voltage Protection (CS/OVP
Pin) - Auto Recovery
An output overvoltage protection is implemented in the
Fig. 19
LD5530R, as shown in Fig. 18 and 19. It senses the
auxiliary voltage via the divided resistors. The auxiliary
winding voltage is reflected from secondary winding and
therefore the flat voltage on the CS/OVP pin is
proportional to the output voltage. LD5530R can sample
this flat voltage level after a delay time to perform output
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Leadtrend Technology Corporation
LD5530R-DS-01
Oct. 2013
LD5530R
Over Load Protection (OLP) –
shutdown simultaneous to turn off the power MOSFET.
Fig. 21 shows its operation.
Auto Recovery
To protect the circuit from damage in over-load condition
VCC
and short or open-loop condition, the LD5530R is
OVP
Level
implemented with smart OLP function. It also features
UVLO (on)
auto recovery function; see Fig. 20 for the waveform. In
UVLO (off)
case of fault condition, the feedback system will force the
OVP
voltage loop toward the saturation and then pull the
voltage high on COMP pin (VCOMP).
UVLO(off)
OVP Reset
t
When the VCOMP
ramps up to the OLP threshold of 4.5V and continues over
OUT
OLP delay time, the protection will be activated and then
turn off the gate output to stop the switching of power
Switching
circuit.
Non- Switching
Switching
With the protection mechanism, the average input power
t
will be minimized to remain the component temperature
Fig. 21
and stress within the safe operating area.
OTP Pin --- Latched Mode Protection
VCC
The OTP circuit is implemented to sense whether there is
any hot-spot of power circuit like power MOSFET or
UVLO(on)
output rectifier. Once an over-temperature condition is
UVLO(off)
OLP
UVLO(off)
OLP Reset
detected, the OTP is enabled to shut down the controller
t
to protect the controller. Typically, a NTC is recommended
COMP
to connect with OTP pin.
OLP delay time
The NTC resistance will
decrease as the device or ambient in high temperature.
OLP
The relationship is as below.
OLP trip Level
VOTP 100μA RNTC
t
OUT
When the VOTP is below the defined voltage threshold (typ.
0.95V), LD5530R will shutdown the gate output and latch
Switching
Non-Switching
off the power supply.
Switching
There are 2 conditions required to
restart it successfully. First, cool down the circuit so that
t
NTC resistance will increase and raise VOTP up above
Fig. 20
1.05V. Then, remove the AC power cord and re-plug AC
power.
Over Voltage Protection (OVP) on Vcc Auto Recovery
The Vcc OVP function of LD5530R is in auto recovery
mode. As soon as the voltage of the Vcc pin rises above
OVP threshold, the output gate drive circuit will be
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Leadtrend Technology Corporation
LD5530R-DS-01
Oct. 2013
LD5530R
MOSFET Characteristic
Output Short Circuit Protection (OSCP) –
The MOSFET is divided into three operation regions,
Auto Recovery
ohmic region, saturation region, and the cut-off region,
The OSCP function is to prevent the damage from output
shown as Fig. 22.
short circuit. Once the output is shorted, Vo and VCC drop
For switching power supply applications, it shall operate in
immediately. And according to the close loop control,
ohmic and cut-off region. Never reach the region of
COMP voltage will pull high in the meanwhile. If the
saturation; it would cause damage for acting beyond the
VCOMP pulls high to over 4.5 V for over 15 ms and Vcc
maximum safety operating area. It’s necessary to check
drops below 9 V. At this time, the OSCP protection will be
the characteristic of MOSFET.
triggered and turn off the gate driving.
ID
VGS5 & gt; VGS4 & gt; VGS3 & gt; VGS2 & gt; VGS1
Ohmic Region
Saturation Region
VGS5
VGS4
VGS3
VGS2
VGS1
Cut-off region
VDS
Fig. 22
13
Leadtrend Technology Corporation
LD5530R-DS-01
Oct. 2013
LD5530R
Package Information
SOT-26
Symbol
Dimension in Millimeters
Dimensions in Inches
Min
Max
Min
Max
A
2.692
3.099
0.106
0.122
B
1.397
1.803
0.055
0.071
C
-------
1.450
-------
0.057
D
0.300
0.500
0.012
0.020
F
0.95 TYP
0.037 TYP
H
0.080
0.254
0.003
0.010
I
0.050
0.150
0.002
0.006
J
2.600
3.000
0.102
0.118
M
0.300
0.600
0.012
0.024
θ
0°
10°
0°
10°
14
Leadtrend Technology Corporation
LD5530R-DS-01
Oct. 2013
LD5530R
Package Information
DIP-8
Symbol
Dimension in Millimeters
Dimensions in Inches
Min
Max
Min
Max
A
9.017
10.160
0.355
0.400
B
6.096
7.112
0.240
0.280
C
-----
5.334
------
0.210
D
0.356
0.584
0.014
0.023
E
1.143
1.778
0.045
0.070
F
2.337
2.743
0.092
0.108
I
2.921
3.556
0.115
0.140
J
7.366
8.255
0.29
0.325
L
0.381
------
0.015
--------
Important Notice
Leadtrend Technology Corp. reserves the right to make changes or corrections to its products at any time without notice. Customers
should verify the datasheets are current and complete before placing order.
15
Leadtrend Technology Corporation
LD5530R-DS-01
Oct. 2013
LD5530R
Revision History
Rev.
Date
Change Notice
00
6/6/2013
Original Specification.
01
10/8/2013
Revision: Operating Current (OTP Pin Tripped / Latch), ICC-OPL1=0.7~0.98 mA
New: Symbols data for the parameters
Holding Current (Vcc=10V), ICC-OPL2=360~540 A
(VCC=Latch-Off Release Voltage+0.2V), ICC-OPL3 = 20~29 A
Internal OTP Latch Protection,
OTP Level=140C, OTP Hysteresis=30C (Guaranteed by design)
OTP Trip Resistance (Guaranteed by design)
16
Leadtrend Technology Corporation
LD5530R-DS-01
Oct. 2013