To uszkodzenie z rodzaju albo się wie i robi szybko albo się szuka - może nawet długo. Ja niestety takiego zachowania tego radia nie spotkałem. Jeśli radio nie pamiętałoby też stacji sprawa prosta - RAM procesora - np. brak napięcia podtrzymującego. W przypadku tylko problemów z kodem jest więcej możliwości do analizy. Pamięć 2444 jest specyficzna. W swojej strukturze ma RAM i EEPROM. Dane są przepisywane pomiędzy pamięciami. Wg producenta trwałość danych w pamięci nieulotnej to 100 lat i 1000000 cykli zapisu. I teraz pytanie - w którym RAM-ie jest przechowywana informacja o prawidłowym wprowadzeniu kodu? Jako pomoc zamieszczam swoje notatki z okresu, gdy to radio rozpracowywałem (jakieś 25 lat do tyłu) i pdf-a pamięci. Może ktoś się podejmie naprawy.
APPLICATION NOTES
A V A I L A B L E
AN3 • AN7 • AN8 • AN15 • AN16 • AN25 • AN29
• AN30 • AN35 • AN36 • AN39 • AN56 • AN69
X24C44
X24C44
256 Bit
16 x 16 Bit
Serial Nonvolatile Static RAM
FEATURES
DESCRIPTION
•
•
•
•
The Xicor X24C44 is a serial 256 bit NOVRAM featuring
a static RAM configured 16 x 16, overlaid bit-by-bit with
a nonvolatile E2PROM array. The X24C44 is fabricated
with Xicor’s Advanced CMOS Floating Gate technology.
•
•
•
•
•
•
Advanced CMOS Version of Xicor’s X2444
16 x 16 Organization
Single 5 Volt Supply
Ideal for use with Single Chip Microcomputers
—Static Timing
—Minimum I/O Interface
—Serial Port Compatible (COPS™, 8051)
—Easily Interfaced to Microcontroller Ports
Software and Hardware Control of Nonvolatile
Functions
Auto Recall on Power-Up
TTL and CMOS Compatible
Low Power Dissipation
—Active Current: 10mA Maximum
—Standby Current: 50µA Maximum
8-Lead PDIP, Cerdip, and 8-Lead SOIC Packages
High Reliability
—Store Cycles: 1,000,000
—Data Retention: 100 Years
The Xicor NOVRAM design allows data to be transferred
between the two memory arrays by means of software
commands or external hardware inputs. A store operation (RAM data to E2PROM) is completed in 5ms or less
and a recall operation (E2PROM data to RAM) is completed in 2µs or less.
Xicor NOVRAMs are designed for unlimited write operations to RAM, either from the host or recalls from
E2PROM and a minimum 1,000,000 store operations.
Inherent data retention is specified to be greater than
100 years.
FUNCTIONAL DIAGRAM
CE (1)
DI (3)
SK (2)
INSTRUCTION
REGISTER
INSTRUCTION
DECODE
COLUMN
DECODE
EC
R
STATIC
RAM
256-BIT
ROW
DECODE
AL
L
ST
O
R
E
NONVOLATILE
2
E PROM
CONTROL
LOGIC
RECALL (6)
STORE (7)
DO (4)
4-BIT
COUNTER
3832 FHD F01
COPS is a trademark of National Semiconductor Corp.
© Xicor, Inc. 1991, 1995, 1996 Patents Pending
3832-1.5 6/19/96 T2/C1/D1 NS
1
Characteristics subject to change without notice
X24C44
PIN DESCRIPTIONS
PIN CONFIGURATION
Chip Enable (CE)
The Chip Enable input must be HIGH to enable all read/
write operations. CE must remain HIGH following a
Read or Write command until the data transfer is complete. CE LOW places the X24C44 in the low power
standby mode and resets the instruction register. Therefore, CE must be brought LOW after the completion of an
operation in order to reset the instruction register in
preparation for the next command.
PDIP/CERDIP/SOIC
CE
1
8
SK
2
7
VCC
STORE
DI
3
6
RECALL
DO
4
5
VSS
X24C44
3832 FHD F02.2
Serial Clock (SK)
The Serial Clock input is used to clock all data into and
out of the device.
Data In (DI)
PIN NAMES
Data In is the serial data input.
Symbol
CE
SK
DI
DO
RECALL
STORE
VCC
VSS
Data Out (DO)
Data Out is the serial data output. It is in the high
impedance state except during data output cycles in
response to a READ instruction.
STORE
STORE LOW will initiate an internal transfer of data from
RAM to the E2PROM array.
RECALL
Description
Chip Enable
Serial Clock
Serial Data In
Serial Data Out
Recall Input
Store Input
+5V
Ground
3832 PGM T01
RECALL LOW will initiate an internal transfer of data
from E2PROM to the RAM array.
2
X24C44
operations to the E2PROM. The WREN instruction sets
the latch and the WRDS instruction resets the latch,
disabling both RAM writes and E2PROM stores, effectively protecting the nonvolatile data from corruption. The
write enable latch is automatically reset on power-up.
DEVICE OPERATION
The X24C44 contains an 8-bit instruction register. It is
accessed via the DI input, with data being clocked in on
the rising edge of SK. CE must be HIGH during the entire
data transfer operation.
STO and STORE
Table 1. contains a list of the instructions and their
operation codes. The most significant bit (MSB) of all
instructions is a logic one (HIGH), bits 6 through 3 are
either RAM address bits (A) or don’t cares (X) and bits
2 through 0 are the operation codes. The X24C44
requires the instruction to be shifted in with the MSB first.
Either the software STO instruction or a LOW on the
STORE input will initiate a transfer of data from RAM to
E2PROM. In order to safeguard against unwanted store
operations, the following conditions must be true:
• STO instruction issued or STORE input is LOW.
• The internal “write enable” latch must be set
(WREN instruction issued).
• The “previous recall” latch must be set (either a
software or hardware recall operation).
After CE is HIGH, the X24C44 will not begin to interpret
the data stream until a logic “1” has been shifted in on DI.
Therefore, CE may be brought HIGH with SK running
and DI LOW. DI must then go HIGH to indicate the start
condition of an instruction before the X24C44 will begin
any action.
In addition, the SK clock is totally static. The user can
completely stop the clock and data shifting will be stopped.
Restarting the clock will resume shifting of data.
Once the store cycle is initiated, all other device functions are inhibited. Upon completion of the store cycle,
the write enable latch is reset. Refer to Figure 4 for a
state diagram description of enabling/disabling conditions for store operations.
RCL and RECALL
WRITE
Either a software RCL instruction or a LOW on the
RECALL input will initiate a transfer of E2PROM data
into RAM. This software or hardware recall operation
sets an internal “previous recall” latch. This latch is reset
upon power-up and must be intentionally set by the user
to enable any write or store operations. Although a recall
operation is performed upon power-up, the previous
recall latch is not set by this operation.
The WRITE instruction contains the 4-bit address of the
word to be written. The write instruction is immediately
followed by the 16-bit word to be written. CE must remain
HIGH during the entire operation. CE must go LOW
before the next rising edge of SK. If CE is brought LOW
prematurely (after the instruction but before 16 bits of data
are transferred), the instruction register will be reset and
the data that was shifted-in will be written to RAM.
WRDS and WREN
If CE is kept HIGH for more than 24 SK clock cycles (8-bit
instruction plus 16-bit data), the data already shifted-in will
be overwritten.
Internally the X24C44 contains a “write enable” latch. This
latch must be set for either writes to the RAM or store
Table 1. Instruction Set
Instruction
Format, I2 I1 I0
Operation
WRDS (Figure 3)
STO (Figure 3)
Reserved
WRITE (Figure 2)
WREN (Figure 3)
RCL (Figure 3)
READ (Figure 1)
1XXXX000
1XXXX001
1XXXX010
1AAAA011
1XXXX100
1XXXX101
1AAAA11X
Reset Write Enable Latch (Disables Writes and Stores)
Store RAM Data in E2PROM
N/A
Write Data into RAM Address AAAA
Set Write Enable Latch (Enables Writes and Stores)
Recall E2PROM Data into RAM
Read Data from RAM Address AAAA
3832 PGM T13
X = Don't Care
A = Address
3
X24C44
READ
SYSTEM CONSIDERATIONS
The READ instruction contains the 4-bit address of the
word to be accessed. Unlike the other six instructions, I0
of the instruction word is a “don’t care”. This provides two
advantages. In a design that ties both DI and DO
together, the absence of an eighth bit in the instruction
allows the host time to convert an I/O line from an output
to an input. Secondly, it allows for valid data output
during the ninth SK clock cycle.
Power-Up Recall
The X24C44 performs a power-up recall that transfers
the E2PROM contents to the RAM array. Although the
data may be read from the RAM array, this recall does
not set the “previous recall” latch. During this power-up
recall operation, all commands are ignored. Therefore,
the host should delay any operations with the X24C44 a
minimum of tPUR after VCC is stable.
D0, the first bit output during a read operation, is truncated. That is, it is internally clocked by the falling edge
of the eighth SK clock; whereas, all succeeding bits are
clocked by the rising edge of SK (refer to Read Cycle
Diagram).
Power-Down Data Protection
Because the X24C44 is a 5V only nonvolatile memory
device it may be susceptible to inadvertent stores to the
E2PROM array during power-down cycles. Power-up
cycles are not a problem because the “previous recall”
latch and “write enable” latch are reset, preventing any
possible corruption of E2PROM data.
LOW POWER MODE
When CE is LOW, non-critical internal devices are
powered-down, placing the device in the standby power
mode, thereby minimizing power consumption.
Software Power-Down Protection
The X24C44 provides two software write protection
mechanisms to prevent inadvertent stores of unknown
data.
If the STORE and RECALL pins are tied to VCC through
a pull-up resistor and only software operations are
performed to initiate stores, there is little likelihood of an
inadvertent store. However, if these two lines are under
microprocessor control, positive action should be employed to negate the possibility of these control lines
bouncing and generating an unwanted store. The safest
method is to issue the WRDS command after a write
sequence and also following store operations. Note: an
internal store may take up to 5ms; therefore, the host
microprocessor should delay 5ms after initiating the
store prior to issuing the WRDS command.
Power-Up Condition
Hardware Power-Down Protection
Upon power-up the “write enable” latch is in the reset
state, disabling any store operation.
(when the “write enable” latch and “previous recall” latch
are not in the reset state):
Unknown Data Store
Holding either RECALL LOW, CE LOW or STORE
HIGH during power-down will prevent an inadvertent
store.
SLEEP
Because the X24C44 is a low power CMOS device, the
SLEEP instruction implemented on the first generation
NMOS device has been deleted. For systems converting from the X2444 to the X24C44 the software need not
be changed; the instruction will be ignored.
WRITE PROTECTION
The “previous recall” latch must be set after power-up.
It may be set only by performing a software or hardware
recall operation, which assures that data in all RAM
locations is valid.
4
X24C44
Figure 1. RAM Read
CE
SK
1
2
3
4
5
6
7
8
DI
1
A
A
A
A
1
1
9
10
11
12
22
23
24
X*
HIGH Z
DO
D0
D1
D2
D3
D13
D14
D15
D0
*Bit 8 of Read Instructions is Don’t Care
3832 FHD F07.1
Figure 2. RAM Write
CE
SK
1
2
3
4
5
6
7
8
9
10
11
21
22
23
24
DI
1
A
A
A
A
0
1
1
D0
D1
D2
D12
D13
D14
D15
3832 FHD F08.1
Figure 3. Non-Data Operations
CE
SK
1
2
3
4
5
6
7
8
DI
1
X
X
X
X
I2
I1
I0
3832 FHD F09.1
5
X24C44
Figure 4. X24C44 State Diagram
POWER
ON
POWER-UP
RECALL
RAM
READ
ENABLED
RAM READ
RCL COMMAND
OR RECALL
RAM
READ
ENABLED
RAM READ
WREN
COMMAND
STO OR
WRDS CMD
OR STORE
RAM
READ &
WRITE
RAM READ
OR WRITE
STORE
ENABLED
3832 FHD F10.1
6
X24C44
ABSOLUTE MAXIMUM RATINGS*
Temperature under Bias .................. –65°C to +135°C
Storage Temperature ....................... –65°C to +150°C
Voltage on any Pin with
Respect to VSS ............................................ –1V to +7V
D.C. Output Current ............................................. 5mA
Lead Temperature
(Soldering, 10 seconds) .............................. 300°C
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Temperature
Min.
Max.
Supply Voltage
Limits
Commercial
Industrial
Military
0°C
–40°C
–55°C
+70°C
+85°C
+125°C
X24C44
5V ±10%
3832 PGM T03.1
3832 PGM T02.1
D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.)
Limits
Symbol
lCC
ISB1
ISB2
ILI
ILO
VlL(1)
VIH(1)
VOL
VOH
Parameter
Min.
VCC Supply Current
(TTL Inputs)
VCC Standby Current
(TTL Inputs)
VCC Standby Current
(CMOS Inputs)
Input Load Current
Output Leakage Current
Input LOW Voltage
Input HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
Units
10
mA
1
mA
50
–1
2
Max.
µA
10
10
0.8
VCC + 1
0.4
µA
µA
V
V
V
V
2.4
Test Conditions
SK = 0.4V/2.4V Levels @ 1MHz,
DO = Open, All Other Inputs = VIH
DO = Open, CE = VIL,
All Other Inputs = VIH
DO = Open, CE = VSS
All Other Inputs = VCC – 0.3V
VIN = VSS to VCC
VOUT = VSS to VCC
IOL = 4.2mA
IOH = –2mA
3832 PGM T04.3
ENDURANCE AND DATA RETENTION
Parameter
Min.
Units
Endurance
Store Cycles
Data Retention
100,000
1,000,000
100
Data Changes Per Bit
Store Cycles
Years
3832 PGM T05
CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V
Symbol
COUT(2)
CIN(2)
Parameter
Max.
Test Conditions
8
6
Output Capacitance
Input Capacitance
Units
pF
pF
VOUT = 0V
VIN = 0V
3832 PGM T06.1
Notes: (1) VIL min. and VIH max. are for reference only and are not tested.
(2) This parameter is periodically sampled and not 100% tested.
7
X24C44
EQUIVALENT A.C. LOAD CIRCUIT
A.C. CONDITIONS OF TEST
Input Pulse Levels
5V
0V to 3V
Input Rise and
Fall Times
Input and Output
Timing Levels
919Ω
10ns
1.5V
OUTPUT
3832 PGM T07.1
497Ω
100pF
3832 FHD F11
A.C. CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Read and Write Cycle Limits
Symbol
FSK(3)
tSKH
tSKL
tDS
tDH
tPD1
tPD
tZ
tCES
tCEH
tCDS
Parameter
Min.
SK Frequency
SK Positive Pulse Width
SK Negative Pulse Width
Data Setup Time
Data Hold Time
SK to Data Bit 0 Valid
SK to Data Valid
Chip Enable to Output High Z
Chip Enable Setup
Chip Enable Hold
Chip Deselect
Max.
Units
1
MHz
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
400
400
400
80
375
375
1
800
350
800
3832 PGM T08.1
POWER-UP TIMING
Symbol
Parameter
Max.
Units
tPUR(4)
tPUW(4)
Power-up to Read Operation
Power-up to Write or Store Operation
200
5
µs
ms
3832 PGM T09
Notes: (3) SK rise and fall times must be less than 50ns.
(4) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. These parameters
are periodically sampled and not 100% tested.
8
X24C44
Write Cycle
1/FSK
SK CYCLE #
tSKH
SK
tSKL
x
1
2
n
tCEH
tCES
tCDS
CE
tDS
tDH
DI
3832 FHD F03
Read Cycle
SK CYCLE #
6
7
8
9
10
n
SK
VIH
CE
tPD
DI
I2
I1
DON’T CARE
tPD1
DO
tZ
HIGH Z
D0
D1
Dn
HIGH Z
3832 FHD F04
9
X24C44
NONVOLATILE OPERATIONS
STORE
Hardware Recall
Software Recall
Hardware Store
Software Store
RECALL
1
1
0
1
Operation
Software
Instruction
0
1
1
1
NOP(5)
RCL
NOP(5)
STO
Write Enable
Latch State
Previous
Recall Latch
State
X
X
SET
SET
X
X
SET
SET
3832 PGM T10
ARRAY RECALL LIMITS
Symbol
Parameter
Min.
tRCC
tRCP
tRCZ
Recall Cycle Time
Recall Pulse Width(6)
Recall to Output in High Z
Max.
Units
2
500
500
µs
ns
ns
3832 PGM T11
Recall Timing
tRCC
tRCP
RECALL
tRCZ
HIGH Z
DO
3832 FHD F05
Notes: (5) NOP designates when the X24C44 is not currently executing an instruction.
(6) Recall rise time must be & lt; 10µs.
10
X24C44
STORE CYCLE LIMITS
Symbol
tST
tSTP
tZ
VCC
Min.
Store Time
Store Pulse Width
CE to Output in High Z
Store Inhibit
Typ.(7)
Max.
Units
2
Parameter
5
ms
ns
µs
V
200
1
3
3832 PGM T12
Store Timing
CE
tST
tSTP
STORE
tZ
HIGH Z
DO
3832 FHD F06
Note:
(7) Typical values are for TA = 25°C and nominal supply voltage.
SYMBOL TABLE
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A
Changing:
State Not
Known
Center Line
is High
Impedance
11
X24C44
PACKAGING INFORMATION
8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P
0.430 (10.92)
0.360 (9.14)
0.092 (2.34)
DIA. NOM.
0.255 (6.47)
0.245 (6.22)
PIN 1 INDEX
PIN 1
0.300
(7.62) REF.
HALF SHOULDER WIDTH ON
ALL END PINS OPTIONAL
0.140 (3.56)
0.130 (3.30)
SEATING
PLANE
0.020 (0.51)
0.015 (0.38)
0.062 (1.57)
0.058 (1.47)
0.150 (3.81)
0.125 (3.18)
0.020 (0.51)
0.016 (0.41)
0.110 (2.79)
0.090 (2.29)
0.015 (0.38)
MAX.
0.060 (1.52)
0.020 (0.51)
0.325 (8.25)
0.300 (7.62)
0°
15°
TYP. 0.010 (0.25)
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F01
12
X24C44
PACKAGING INFORMATION
8-LEAD HERMETIC DUAL IN-LINE PACKAGE TYPE D
0.405 (10.29)
––
0.310 (7.87)
0.220 (5.59)
PIN 1
0.005 (0.13) MIN.
0.300 (7.62)
REF.
0.200 (5.08)
0.140 (3.56)
SEATING
PLANE
0.150 (3.81) MIN.
0.055 (1.40) MAX.
0.060 (1.52)
0.015 (0.38)
0.200 (5.08)
0.125 (3.18)
0.065 (1.65)
0.038 (0.97)
TYP. 0.060 (1.52)
0.110 (2.79)
0.090 (2.29)
TYP. 0.100 (2.54)
0.023 (0.58)
0.014 (0.36)
TYP. 0.017 (0.43)
0.320 (8.13)
0.290 (7.37)
TYP. 0.311 (7.90)
0°
15°
0.015 (0.38)
0.008 (0.20)
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F05
13
X24C44
PACKAGING INFORMATION
8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
0.150 (3.80)
0.158 (4.00)
0.228 (5.80)
0.244 (6.20)
PIN 1 INDEX
PIN 1
0.014 (0.35)
0.019 (0.49)
0.188 (4.78)
0.197 (5.00)
(4X) 7°
0.053 (1.35)
0.069 (1.75)
0.004 (0.19)
0.010 (0.25)
0.050 (1.27)
0.010 (0.25)
X 45°
0.020 (0.50)
0.050 " TYPICAL
0.050 "
TYPICAL
0° – 8°
0.0075 (0.19)
0.010 (0.25)
0.250 "
0.016 (0.410)
0.037 (0.937)
0.030 "
TYPICAL
8 PLACES
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F22.1
14
X24C44
ORDERING INFORMATION
X24C44
P
T
-V
VCC Limits
Blank = 5V ±10%
Device
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
M = Military = –55°C to +125°C
Package
P = 8-Lead Plastic DIP
D = 8-Lead Ceramic DIP
S = 8-Lead SOIC
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes
no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described
devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness tor any purpose. Xicor, Inc. reserves the right to
discontinue production and change specifications and prices at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents,
licenses are implied.
US. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481;
4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967;
4,883,976. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with
appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence.
Xicor’s products are not authorized for use as critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life,
and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected
to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure
of the life support device or system, or to affect its satety or effectiveness.
15
X24C44
U.S. SALES OFFICES
Corporate Office
Xicor Inc.
1511 Buckeye Drive
Milpitas, CA 95035
Phone: 408/432-8888
Fax: 408/432-0640
E-mail: info@smtpgate.xicor.com
Mid-Atlantic Region
Xicor Inc.
50 North Street
Danbury, CT 06810
Phone: 203/743-1701
Fax: 203/794-9501
E-mail: xicor-ma@smtpgate.xicor.com
Northeast Region
Xicor Inc.
1344 Main Street
Waltham, MA 02154
Phone: 617/899-5510
Fax: 617/899-6808
E-mail: xicor-ne@smtpgate.xicor.com
North Central Region
Xicor Inc.
810 South Bartlett Road
Suite 103
Streamwood, IL 60107
Phone: 708/372-3200
Fax: 708/372-3210
E-mail: xicor-nc@smtpgate.xicor.com
Southeast Region
Xicor Inc.
100 E. Sybelia Ave.
Suite 355
Maitland, FL 32751
Phone: 407/740-8282
Fax: 407/740-8602
E-mail: xicor-se@smtpgate.xicor.com
South Central Region
Xicor Inc.
11884 Greenville Ave.
Suite 102
Dallas, TX 75243
Phone: 214/669-2022
Fax: 214/644-5835
E-mail: xicor-sc@smtpgate.xicor.com
Southwest Region
Xicor Inc.
4100 Newport Place Drive
Suite 710
Newport Beach, CA 92660
Phone: 714/752-8700
Fax: 714/752-8634
E-mail: xicor-sw@smtpgate.xicor.com
Northwest Region
Xicor Inc.
2700 Augustine Drive
Suite 219
Santa Clara, CA 95054
Phone: 408/292-2011
Fax: 408/980-9478
E-mail: xicor-nw@smtpgate.xicor.com
INTERNATIONAL SALES OFFICES
EUROPE
Northern Europe
Xicor Ltd.
Grant Thornton House
Witan Way
Witney
Oxford OX8 6FE
UK
Phone: (44) 1933.700544
Fax: (44) 1933.700533
E-mail: xicor-uk@smtpgate.xicor.com
Central Europe
Xicor GmbH
Technopark Neukeferloh
Bretonischer Ring 15
85630 Grasbrunn bei Muenchen
Germany
Phone: (49) 8946.10080
Fax: (49) 8946.05472
E-mail: xicor-gm@smtpgate.xicor.com
ASIA/PACIFIC
Japan
Xicor Japan K.K.
Suzuki Building, 4th Floor
1-6-8 Shinjuku, Shinjuku-ku
Tokyo 160, Japan
Phone: (81) 3322.52004
Fax: (81) 3322.52319
E-mail: xicor-jp@smtpgate.xicor.com
Mainland China
Taiwan/Hong Kong
Xicor Inc.
4100 Newport Place Drive
Suite 710
Newport Beach, CA 92660
Phone: 714/752-8700
Fax: 714/752-8634
E-mail: xicor-sw@smtpgate.xicor.com
Singapore/Malaysia/India
Xicor Inc.
2700 Augustine Drive
Suite 219
Santa Clara, CA 95054
Phone: 408/292-2011
Fax: 408/980-9478
E-mail: xicor-nw@smtpgate.xicor.com
Korea
Xicor Korea
27th Fl., Korea World Trade Ctr.
159, Samsung-dong
Kangnam Ku
Seoul 135-729
Korea
Phone: (82) 2551.2750
Fax: (82) 2551.2710
E-mail: xicor-ka@smtpgate.xicor.com
( ) = Country Code
Xicor product information is available at:
http://www.xicor.com
Xicor, Inc., Marketing Dept. 1511 Buckeye Drive, Milpitas, California 95035-7493 TEL 408/432-8888 FAX 408/432-0640 Rev. 4 3/96 Stock# 99-A-0028
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