Sprawdź diodę dołączoną do n. 13 tego układu. Podstaw na próbę inne klucze przetwornicy która nie pracuje. Ogólnie ciężka sprawa bo nie ma ani schematu tej karty ani szczegółowej noty katalogowej OZ8138LN. W załączniku zamieszczam schemat w którym występuje taki układ i wzorując się częściowo na nim można co nieco pomierzyć (strona 33).
A
5
4
3
Title
Date:
Size
A
2
Thursday, February 26, 2009
Project Name
Q10
Power Block
CZC Technology
1
Sheet
2
of
Li.wang
Blank
Rev
B
48
A
B
B
1
C
2
C
3
D
4
D
5
A
B
C
D
H_ADSTB#0
H_A#[31:3]
[6]
[12]
[12]
[12]
[12]
[12]
[12]
[12]
[6]
H_A#[31:3]
[6]
TP4
R7
1K
ns
1K,1% H_A#32
R6
1K
ns
+V1.05S
1K,1% H_A#35
R25
R27
R31
1K
ns
+V1.05S
1K,1% H_A#34
R21
H_AP1
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_AP0
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
D6
G6
H6
K4
K5
M15
L16
U18
T16
J4
R16
T15
R15
U17
C19
F19
E21
A16
D19
C14
C18
C20
E20
D20
B18
C15
B16
B17
C16
A17
B14
B15
A14
B19
M18
P21
H20
N20
R20
J19
N19
G20
M19
H21
L20
M20
K19
J20
L21
K20
D17
N21
J21
G19
P20
R19
ATOM N270
NC1
NC2
NC3
NC4
NC5
NC6
NC7
A20M#
FERR#
IGNNE#
STPCLK#
LINT0
LINT1
SMI#
A[17]#
A[18]#
A[19]#
A[20]#
A[21]#
A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
A[32]#
A[33]#
A[34]#
A[35]#
ADSTB[1]#
AP1
A[3]#
A[4]#
A[5]#
A[6]#
A[7]#
A[8]#
A[9]#
A[10]#
A[11]#
A[12]#
A[13]#
A[14]#
A[15]#
A[16]#
ADSTB[0]#
AP0
REQ[0]#
REQ[1]#
REQ[2]#
REQ[3]#
REQ[4]#
U1A
5
H_NMI
R32
1K
ns
+V1.05S
H_SMI#
R33
1K
ns
+V1.05S
H_INTR
Reference Board Reservation only
1K,1% H_A#33
R19
+V1.05S
H_A20M#
H_FERR#
H_IGNNE#
H_STPCLK#
H_INTR
H_NMI
H_SMI#
H_ADSTB#1
TP1
H_REQ#[4:0]
Layout: Place near CPU
H_REQ#[4:0]
[6]
[6]
CONTROL
BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
PRDY#
PREQ#
TCK
TDI
TDO
TMS
TRST#
BR1#
HIT#
HITM#
RESET#
RS[0]#
RS[1]#
RS[2]#
TRDY#
LOCK#
IERR#
INIT#
BR0#
DEFER#
DRDY#
DBSY#
ADS#
BNR#
BPRI#
R20
R18
C21
C1
A3
V11
V12
H17
G17
E4
E5
K17
J18
H15
J15
K18
J16
M17
N16
M16
L17
K16
V15
AA17
V20
D15
W18
Y17
U20
W19
W20
F16
V16
T20
T21
T19
Y18
V19
Y19
U21
56
R34
1K
ns
+V1.05S
4
H_STPCLK#
56
R28
56
56
56
1K,1%
R8
[6]
[6]
0
R3
330
3
[12]
H_PROCHOT# [26,36]
H_INIT#
R23
2K,1%
R15
1K,1%
C1
0.1uF/16V,X7R
H_GTLREF
to IMVP6 IC
+V1.05S
R5
75
+V1.05S
R2
56
+V1.05S
R37
1K
ns
+V1.05S
3
CPU_PWRGD
Layout note: Zo=55 ohm,
0.5 " max for GTLREF
H_DPRSTP#
R36
1K
ns
+V1.05S
CLK_CPU_BCLK [17]
CLK_CPU_BCLK# [17]
PM_THRMTRIP# [5,7,12]
H_THERMDA [5]
H_THERMDC [5]
H_HIT#
H_HITM#
H_TRDY# [6]
H_LOCK# [6]
H_CPURST# [6,38]
H_RS#[2:0] [6]
R1
H_BREQ#0 [6]
H_DPSLP#
R35
1K
ns
+V1.05S
[6,38]
[6]
[6]
H_DEFER# [6]
H_DRDY# [6]
H_DBSY# [6]
H_ADS#
H_BNR#
H_BPRI#
+V1.05S
XDP_TMS
XDP_TRST#
XDP_BPM#5
XDP_TCK
XDP_TDI
H_RS#0
H_RS#1
H_RS#2
IERR#
4
XDP_TRST# R29
XDP_TCK
XDP_BPM#5 R22
XDP_TDI
XDP_TMS
RSVD3
RSVD2
RSVD1
BCLK[0]
BCLK[1]
THERMTRIP#
PROCHOT#
THRMDA
THRMDC
XDP/ITP SIGNALS
THERM
THERM
5
ADDR GROUP 1
H CLK
H CLK
R10
R12
H_DP#1
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
TP2
C2
1uF/10V,X5R
H_DPWR#
C3
0.1uF/16V,X7R
CPU_CMREF
ATOM N270
GTLREF
ACLKPH
DCLKPH
BINIT#
MISC
EDM
EXTBGREF
FORCEPR#
HFPLL
MCERR#
RSP#
BSEL[0]
BSEL[1]
BSEL[2]
D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#
DP#1
D[0]#
D[1]#
D[2]#
D[3]#
D[4]#
D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#
DP#0
U1B
R38
1K
ns
R30
1K
ns
+V1.05S
2
Layout note: Zo=55 ohm,
0.5 " max for CMREF
R26
2K,1%
R17
1K,1%
+V1.05S
A7
U5
V5
T17
R6
M6
N15
N6
P17
T6
J6
H5
G5
AA5
Y8
W3
U1
W7
W6
Y7
AA6
Y3
W2
V3
U2
T3
AA8
V2
W4
Y4
Y5
Y6
R4
Y11
W10
Y12
AA14
AA11
W12
AA16
Y10
Y9
Y13
W15
AA13
Y16
W13
AA9
W9
Y14
Y15
W16
H_DP#0 V9
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_GTLREF
ACLKPH
DCLKPH
TP7
H_BINIT#
TP8
EDM
EXTBGREF
TP9
FORCEPR#
TP10
H_HFPLL
TP11
H_MCERR#
TP12
H_RSP#
TP38
TP47
TP48
TP5
EXTBGREF
1K,1%
1K,1%
Layout note: Zo=55 ohm,
0.5 " max for EXTGBREF
R24
2K,1%
R16
1K,1%
ns
ns
H_DSTBN#1
H_DSTBP#1
H_DINV#1
H_D#[63:0]
H_DSTBN#0
H_DSTBP#0
H_DINV#0
H_D#[63:0]
+V1.05S
[6]
[6]
[6]
[6]
[6]
[6]
[6]
[6]
2
+V1.05S
DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#
CORE_DET
CMREF[1]
COMP[0]
COMP[1]
COMP[2]
COMP[3]
D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#
DSTBN[3]#
DSTBP[3]#
DINV[3]#
DP#3
D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#
DSTBN[2]#
DSTBP[2]#
DINV[2]#
DP#2
DATA GRP 2
DATA GRP 2
DATA GRP 3
DATA GRP 3
ADDR
GROUP
0
DATA GRP 1
NC
DATA GRP 0
R9
R11
R13
R14
H_DP#3
Date:
Size
A3
Q10
1
Sheet
3
Zo=27.4 ohm,make
than 0.5''
Zo=55 ohm,make
than 0.5''
Diamondville Bus/MISC
Thursday, February 26, 2009
Project Name
[6]
[6]
of
H_DPRSTP# [12,38]
H_DPSLP# [12,38]
H_DPWR# [6]
CPU_PWRGD [12,38]
H_CPUSLP# [6,38]
Layout note:
Comp0,2 connect with
trace length shorter
Comp1,3 connect with
trace length shorter
TP13
TP6
27.4,1%
54.9,1%
27.4,1%
54.9,1%
H_DSTBN#3 [6]
H_DSTBP#3 [6]
H_DINV#3 [6]
H_D#[63:0]
H_DSTBN#2 [6]
H_DSTBP#2 [6]
H_DINV#2 [6]
H_D#[63:0]
[4,5,6,8,9,12,15,17,26,33,35,38]
CZC Technology
CORE_DET
CPU_CMREF
R18
R17
U4
V17
N18
A13
B7
Title
TP3
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DP#2
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
T1
T2
F20
F21
C2
G2
F1
D3
B4
E1
A5
C3
A6
F2
C6
B6
B3
C4
C7
D2
E2
F3
C5
D4
R3
R2
P1
N1
M2
P2
J3
N3
G3
H2
N2
L2
M3
J2
H1
J1
K2
K3
L1
M4
+V1.05S
1
Rev
B
48
A
B
C
D
A
5
ATOM N270
4
C15
C15
1uF/10V,X5R
C31
C31
10uF/6.3V,X5R
C14
1uF/10V,X5R
1uF/10V,X5R
C30
10uF/6.3V,X5R
10uF/6.3V,X5R
ns
A10
A11
A12
B10
B11
B12
C10
C11
C12
D10
D11
D12
E10
E11
E12
F10
F11
F12
G10
G11
G12
H10
H11
H12
J10
J11
J12
K10
K11
K12
L10
L11
L12
M10
M11
M12
N10
N11
N12
P10
P11
P12
R10
R11
R12
ATOM N270
VCCP1
VCCP2
VCCP3
VCCP4
VCCP5
VCCP6
VCCP7
VCCP8
VCCP9
VCCP10
VCCP11
VCCP12
VCCP13
VCCP14
VCCP15
VCCP16
VCCP17
VCCP18
VCCP19
VCCP20
VCCP21
VCCP22
VCCP23
VCCP24
VCCP25
VCCP26
VCCP27
VCCP28
VCCP29
VCCP30
VCCP31
VCCP32
VCCP33
VCCP34
VCCP35
VCCP36
VCCP37
VCCP38
VCCP39
VCCP40
VCCP41
VCCP42
VCCP43
VCCP44
VCCP45
VCCQ1
VCCQ2
VCCF
Place In Cavity
+VCC_CORE
C4
0.1uF/16V,X7R
A9
B9
V10
C18
1uF/10V,X5R
VSSSENSE
VCCSENSE
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
VCCA
VCCPC64
VCCPC63
VCCPC62
VCCPC61
VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9
VTT10
VTT11
VTT12
VTT13
VTT14
VTT15
VTT16
VTT17
VTT18
VTT19
VTT20
VTT21
VTT22
VTT23
VTT24
VTT25
VTT26
VTT27
VTT28
VTT29
VTT30
VTT31
VTT32
3
Place in corridor and close to CPU
C34
C34
10uF/6.3V,X5R
+VCC_CORE
C16
1uF/10V,X5R
C32
10uF/6.3V,X5R
+V1.05S
C17
1uF/10V,X5R
1uF/10V,X5R
C33
10uF/6.3V,X5R
U1C
C19
1uF/10V,X5R
C35
10uF/6.3V,X5R
B
N5
N7
N9
N13
N17
P3
P4
P5
P6
P7
P9
P13
P15
P16
P18
P19
R1
R5
R7
R9
R13
R21
T4
T5
T7
T9
T10
T11
T12
T13
T18
U3
U6
U7
U15
U16
U19
V1
V4
V6
V7
V8
V13
V14
V18
V21
W1
W5
W8
W11
W14
W17
W21
Y1
Y2
Y20
Y21
AA2
AA3
AA4
AA7
AA10
AA12
AA15
AA18
AA19
AA20
D13
C13
F15
D16
E18
G15
G16
E17
G18
D7
F14
F13
E14
E13
C9
D9
E9
F8
F9
G8
G14
H8
H14
J8
J14
K8
K14
L8
L14
M8
M14
N8
N14
P8
P14
R8
R14
T8
T14
U8
U9
U10
U11
U12
U13
U14
C21
1uF/10V,X5R
C
VSS162
VSS161
VSS160
VSS159
VSS158
VSS157
VSS156
VSS155
VSS154
VSS153
VSS152
VSS151
VSS149
VSS148
VSS147
VSS146
VSS145
VSS144
VSS143
VSS142
VSS141
VSS140
VSS139
VSS138
VSS137
VSS136
VSS135
VSS134
VSS133
VSS132
VSS131
VSS130
VSS129
VSS128
VSS127
VSS126
VSS125
VSS124
VSS123
VSS122
VSS121
VSS120
VSS119
VSS118
VSS117
VSS116
VSS115
VSS114
VSS113
VSS112
VSS111
VSS110
VSS109
VSS108
VSS107
VSS106
VSS105
VSS104
VSS103
VSS102
VSS101
VSS100
VSS99
VSS98
VSS97
VSS96
VSS95
C20
C20
1uF/10V,X5R
C36
10uF/6.3V,X5R
10uF/6.3V,X5R
VSS1
VSS2
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS41
VSS42
VSS45
VSS46
VSS48
VSS49
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
C37
C37
10uF/6.3V,X5R
D
A2
A4
A8
A15
A18
A19
A20
B1
B2
B5
B8
B13
B20
B21
C8
C17
D1
D5
D8
D14
D18
D21
E3
E6
E7
E8
E15
E16
E19
F4
F5
F6
F7
F17
F18
G1
G4
G7
G9
G13
G21
H3
H4
H7
H9
H13
H16
H18
H19
J5
J7
J9
J13
J17
K1
K6
K7
K9
K13
K15
K21
L3
L4
L5
L6
L7
L9
L13
L15
L18
L19
M1
M5
M7
M9
M13
M21
N4
C22
C22
1uF/10V,X5R
C38
10uF/6.3V,X5R
10uF/6.3V,X5R
ns
C5
C5
0.1uF/16V,X7R
CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6
2
+V1.5S
+VCC_CORE
+V1.05S
+V1.05S
[36]
[36]
[36]
[36]
[36]
[36]
[36]
2
C9
1uF/10V,X5R
[3,5,6,8,9,12,15,17,26,33,35,38]
+V1.05S
+V1.5S
Date:
Size
A3
Title
R40
100,1%
R39
100,1%
+VCC_CORE
Q10
Diamondville Power
1
Thursday, February 26, 2009
Project Name
Sheet
CPU place
1
CZC Technology
VSS_SENSE [36]
VCC_SENSE [36]
close to
CT16
22uF/6.3V,TAN
+V1.05S
[7,8,9,13,15,20,33,35,38]
+VCC_CORE [36,38]
[3,5,6,8,9,12,15,17,26,33,35,38]
+V1.05S
C13
10uF/6.3V,X5R
+V1.5S
C12
0.1uF/16V,X7R
Place IN CAVITY
C6
1uF/10V,X5R
C41
10uF/6.3V,X5R
3
C23
1uF/10V,X5R
C39
C39
10uF/6.3V,X5R
C7
1uF/10V,X5R
C25
1uF/10V,X5R
U1D
4
C24
1uF/10V,X5R
C40
10uF/6.3V,X5R
C8
1uF/10V,X5R
C26
1uF/10V,X5R
1uF/10V,X5R
5
C27
C27
1uF/10V,X5R
C10
10uF/6.3V,X5R
C28
1uF/10V,X5R
C11
10uF/6.3V,X5R
C29
1uF/10V,X5R
1uF/10V,X5R
4
of
Rev
B
48
A
B
C
D
A
B
C
H_THERMDA
3450
3000
3900
THERM_ALERT#
50
55
R50
R48
ns
1K
10K
5
60
65
80
70
75
85
57.5 62.5 67.5 72.5 77.5 82.5
90
95
100
SMBCLK
R51
100K
R49
100K
ns
(Degree)
4
2200pF/25V,X7R
C46
1
ThermalALertON#
Q2
MMDT3904
SC70_6
ns
Q3
2N7002K
SOT23
2
R44
4.7K
R43
4.7K
+V3.3S
PWR_SHDN#
G781_PULLHIGH
R47
10K
ns
+V3.3S
C45
1000pF/50V,X7R
ns
5
4
6
7
8
THERM_ALERT#
100
C42
0.1uF/16V,X7R
DXN
SMBDATA
G781
ADM1032AR
ALERT#
LM86CIM
MAX6657MSA
THERM#
SOIC-8
DXP
aSC7511T3
3
2
CPU Temperature
Need to Proved
[26] ThermalAlertON
0
4350
Full on
FAN Speed
(RPM)
[3]
C43
2200pF/25V,X7R
THERMDC
pair to pair 8:8:8
shielding GND Line
H_THERMDC
[3]
U2
1
VCC
THERMDA
GND
5
R41
3
4
D
CPU Thermal
6
1
3
2
[26,27]
3
[3,4,6,8,9,12,15,17,26,33,35,38]
R45
470
C44
0.1uF/16V,X7R
5
R42
4.7K
+V1.05S
PWR_SHDN#
ThermalALertON#
2
Q1
MMDT3904
SC70_6
1
2
pair to pair 8:8:8
shielding GND Line
SMBCLK
Date:
Size
Custom
Title
4
6
7
8
+V3.3AUX
BAT_DATA
BAT_CLK
100
[26,30]
[26,30]
Q10
1
Sheet
CPU THERMAL SENSOR
Thursday, February 26, 2009
Project Name
CZC Technology
DXN
SMBDATA
G781
ADM1032AR
ALERT#
LM86CIM
MAX6657MSA
THERM#
SOIC-8
DXP
aSC7511T3
ns
3
2
U4
C550
0.1uF/16V,X7R
ns
R718 ns
5
of
R720
4.7K
ns
Rev
B
be placed near the area of the highest temp
C551
2200pF/25V,X7R
ns
1
Note: Need
System Thermal
[3,7,12] PM_THRMTRIP#
R46
10K
[7,8,9,11,12,13,14,15,17,18,20,22,23,25,26,27,28,34,35,36,38]
2
+V3.3AUX [12,13,14,15,18,20,25,26,27,29,30,31,34,38]
+V1.05S
+V3.3S
Q55
MMBT3904-F
ns
SMB_DAT1
PWR_SHDN# [29,35]
[26,27]
SMB_CLK1
+V3.3AUX
+V1.05S
+V3.3S
3
1
VCC
4
3
3
4
5
GND
5
2
6
1
48
R719
4.7K
ns
A
B
C
D
A
B
C
D
H_YRCOMP
C50
0.1uF/16V,X7R
H_YSWING
10 mil wide with 20 mil spacing
H_YSCOMP
R62
24.9,1%
5
10 mil wide with 20 mil spacing
R61
100,1%
R60
221,1%
+V1.05S
R58
54.9,1%
+V1.05S
R56
100,1%
C47
0.1uF/16V,X7R
10 mil wide with 20 mil spacing
H_XSWING
R55
221,1%
+V1.05S
H_XSCOMP
R54
54.9,1%
+V1.05S
R53
24.9,1%
10 mil wide with 20 mil spacing
H_XRCOMP
5
[3]
H_D#[63:0]
4
4
C4
F6
H9
H6
F7
E3
C2
C3
K9
F5
J7
K7
H8
E5
K8
J8
J2
J3
N1
M5
K5
J5
H3
J4
N3
M4
M3
N8
N6
K3
N9
M1
V8
V9
R6
T8
R2
N5
N2
R5
U7
R8
T4
T7
R3
T5
V6
V3
W2
W1
V2
W4
W7
W5
V5
AB4
AB8
W8
AA9
AA8
AB1
AB7
AA2
AB5
A10
A6
C15
J1
K1
H1
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_XRCOMP
H_XSCOMP
H_XSWING
H_YRCOMP
H_YSCOMP
H_YSWING
HXRCOMP
HXSCOMP
HXSWING
HYRCOMP
HYSCOMP
HYSWING
HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#
HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#
U3A
945GSE
HOST
3
HHIT#
HHITM#
HLOCK#
HREQ0#
HREQ1#
HREQ2#
HREQ3#
HREQ4#
HRS0#
HRS1#
HRS2#
HCPUSLP#
HTRDY#
HCLKN
HCLKP
HDBSY#
HDEFER#
HDINV0#
HDINV1#
HDINV2#
HDINV3#
HDPWR#
HDRDY#
HDSTBN0#
HDSTBN1#
HDSTBN2#
HDSTBN3#
HDSTBP0#
HDSTBP1#
HDSTBP2#
HDSTBP3#
HADS#
HADSTB0#
HADSTB1#
H_AVREF
HBNR#
HBPRI#
HBREQ0#
HCPURST#
HDVREF
HA3#
HA4#
HA5#
HA6#
HA7#
HA8#
HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#
3
C8
B4
C5
G9
E9
G12
B8
F12
A5
B6
G10
E8
E10
AA6
AA5
C10
C6
H5
J6
T9
U6
G7
E6
F3
M8
T1
AA3
F4
M7
T2
AB3
F10
C12
H16
E2
B9
C7
G8
B10
E1
F8
D12
C13
A8
E13
E12
J12
B13
A13
G13
A12
D14
F14
J13
E17
H15
G15
G14
A15
B18
B15
E14
H13
C14
A17
E15
H17
D17
G17
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#0
H_RS#1
H_RS#2
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
[3]
H_CPUSLP# [3,38]
H_TRDY# [3]
H_RS#[2:0]
H_HIT#
[3]
H_HITM# [3]
H_LOCK# [3]
H_REQ#[4:0] [3]
CLK_MCH_BCLK# [17]
CLK_MCH_BCLK [17]
H_DBSY# [3]
H_DEFER# [3]
H_DINV#0 [3]
H_DINV#1 [3]
H_DINV#2 [3]
H_DINV#3 [3]
H_DPWR# [3]
H_DRDY# [3]
H_DSTBN#0 [3]
H_DSTBN#1 [3]
H_DSTBN#2 [3]
H_DSTBN#3 [3]
H_DSTBP#0 [3]
H_DSTBP#1 [3]
H_DSTBP#2 [3]
H_DSTBP#3 [3]
H_BNR#
[3]
H_BPRI# [3]
H_BREQ#0 [3]
H_CPURST# [3,38]
H_ADS#
[3,38]
H_ADSTB#0 [3]
H_ADSTB#1 [3]
H_DVREF
R59
200,1%
2
C49
0.1uF/16V,X7R
ns
100 mils or less from GMCH pin
H_A#[31:3] [3]
2
Date:
Size
A3
Title
Note:H_CPURST#
has T topology
C48
0.1uF/16V,X7R
R57
100,1%
+V1.05S
+V1.05S
Q10
945GSE FSB
1
Thursday, February 26, 2009
Project Name
Sheet
6
[3,4,5,8,9,12,15,17,26,33,35,38]
CZC Technology
+V1.05S
1
of
Rev
B
48
A
B
C
D
A
B
C
[11] M_ODT0
[11] M_ODT1
[11] M_CS#0
[11] M_CS#1
[11] M_CKE0
[11] M_CKE1
[11] M_CLK_DDR0#
[11] M_CLK_DDR1#
[11] M_CLK_DDR0
[11] M_CLK_DDR1
DMI_RXN0
DMI_RXN1
DMI_RXP0
DMI_RXP1
[13]
[13]
[13]
[13]
5
R86
80.6,1%
R79
80.6,1%
+V1.8
R78
10K,1%
M_VREF_MCH
R77
10K,1%
+V1.8
DMI_TXN0
DMI_TXN1
DMI_TXP0
DMI_TXP1
[13]
[13]
[13]
[13]
Y29
Y32
Y28
Y31
M_RCOMP#
M_RCOMP
DMI_RXN0
DMI_RXN1
DMI_RXP0
DMI_RXP1
M_RCOMP
AN12
AN14
AA33
AE1
AE12
AF14
AJ14
AJ12
AJ21
AF11
AG14
AF12
AK14
AH12
AN21
AN22
AF26
AF25
AK1
AN30
AG33
AF1
AJ1
AM30
AF33
AG1
V28
V31
V29
V32
DMI_TXN0
DMI_TXN1
DMI_TXP0
DMI_TXP1
M_RCOMP#
C52
0.1uF/16V,X7R
D
C51
C51
1uF/10V,X5R
4
MCH_RSVD1
MCH_RSVD2
MCH_RSVD7
MCH_RSVD8
MCH_RSVD9
CFG0
CFG1
CFG2
CFG3
CFG5
CFG6
+V3.3S
4
10K
10K
ns
10K
R80
DREF_CLKN
DREF_CLKP
DREF_SSCLKN
DREF_SSCLKP
CLKREQB
ICHSYNC#
BM_BUSY#
EXT_TS0#
EXT_TS1#/DPRSLPVR
THRMTRIP#
PWROK
RSTIN#
945GSE
SMRCOMPN
SMRCOMPP
SMVREF0
SMVREF1
SM_ODT0
SM_ODT1
SM_ODT2
SM_ODT3
SMOCDCOMP0
SMOCDCOMP1
SM_CS0#
SM_CS1#
SM_CS2#
SM_CS3#
SM_CKE0
SM_CKE1
SM_CKE2
SM_CKE3
SM_CK2#
SM_CK3#
SM_CK0#
SM_CK1#
SM_CK2
SM_CK3
SM_CK0
SM_CK1
DMI_TXN0
DMI_TXN1
DMI_TXP0
DMI_TXP1
DMI_RXN0
DMI_RXN1
DMI_RXP0
DMI_RXP1
U3B
DMI
DDR2 MUXING
R82
R84
R65
2.2K
ns
GMS_CFG5
R63
2.2K
A27
A26
J33
H33
J22
MCH_CLKREQ#
PM_EXTTS#1
R_PM_EXTTS#0
E31
G21
F26 R_PM_EXTTS#0R74
H26 PM_EXTTS#1 R75
J15
AB29
W27 RST_IN#_MCH R76
K32
K31
C17
F18
A3
C18
E18
G20
G18
J20
J18
+V3.3S
1.5K,1%
R87
R85
R83
R81
3
10K
10K
10K
10K
L_DDC_DATA
L_DDC_CLK
L_CTLA_DATA
R72
R70
R71
[18] LA_DATAP0
[18] LA_DATAP1
[18] LA_DATAP2
[18] LA_DATAN0
[18] LA_DATAN1
[18] LA_DATAN2
[18] LA_CLKN
[18] LA_CLKP
[18] L_DDC_CLK
[18] L_DDC_DATA
[18] L_VDDEN
[18] L_BKLTCTL
[18] L_BKLTEN
249,1%
33
33
[23] CRT_RED
[23] CRT_GREEN
[23] CRT_DDC_CLK
[23] CRT_DDC_DATA
[23] CRT_BLUE
[17] CLK_PCIE_3GPLL#
[17] CLK_PCIE_3GPLL
L_CTLA_CLK
MCH_ICH_SYNC# [13]
PM_BMBUSY# [14]
PM_EXTTS#0 [11]
PM_DPRSLPVR [14,36]
PM_THRMTRIP# [3,5,12]
IMVP_PWROK [14,26,36,38]
PLTRST# [13,14,20,25,26,38]
DREFCLK# [17]
DREFCLK [17]
DREFSSCLK# [17]
DREFSSCLK [17]
MCH_CLKREQ# [17]
100
0
0
R73
[23] CRT_VSYNC
[23] CRT_HSYNC
Low=DMIx2 Defalt
High=DMIx4
MCH_CFG_5
R66
2.2K
ns
Reserve
MCH_CFG_6
MCH_BSEL0 [17]
MCH_BSEL1 [17]
MCH_BSEL2 [17]
Reserve
MCH_CFG_3
3
2
E33
D32
F29
F33
D33
F30
H31
G32
C31
G31
F32
D31
D30
C30
A30
A29
H30
G29
L_CTLA_CLK F28
L_CTLA_DATA E28
L_DDC_CLK G28
L_DDC_DATA H28
K30
K27
J29
J30
K29
VSYNC
HSYNC
CRTREFSET
H20
H22
A24
A23
E25
F25
C25
D25
F27
D27
H25
H27
J27
Y26
AA26
2
150,1%
150,1%
150,1%
R67
LBDATAP0
LBDATAP1
LBDATAP2
LBDATAN0
LBDATAN1
LBDATAN2
LADATAP0
LADATAP1
LADATAP2
LADATAN0
LADATAN1
LADATAN2
LACLKN
LACLKP
LBCLKN
LBCLKP
LBKLT_CTRL
LBKLT_EN
LCTLA_CLK
LCTLB_CLK
LDDC_CLK
LDDC_DATA
LVDD_EN
LIBG
LVBG
LVREFH
LVREFL
DDCCLK
DDCDATA
BLUE
BLUE#
GREEN
GREEN#
RED
RED#
VSYNC
HSYNC
REFSET
SDVOCTRL_DATA
SDVOCTRL_CLK
GCLKN
GCLKP
U3F
MISC
VGA
R68
R69
CRT_RED
G26
J26
A21
C20
E20
G23
B21
C21
D21
N28
M32
P33
R32
P28
N32
P32
T32
M30
P30
T30
N30
R30
T29
Date:
1
Q10
1
Sheet
7
945GSE DMI/MISC/VGA/LVDS
Thursday, February 26, 2009
Project Name
CZC Technology
+V1.5S
24.9,1%
+V1.5S_PCIE
of
Rev
B
48
A
B
C
D
+V1.5S_PCIE [9]
+V1.5S
[4,8,9,13,15,20,33,35,38]
+V3.3S
[5,8,9,11,12,13,14,15,17,18,20,22,23,25,26,27,28,34,35,36,38]
+V1.8
[9,11,32]
R28 PEG_COMP R64
M28
Size
A3
Title
CRT_GREEN
CRT_BLUE
TV_DCONSEL0
TV_DCONSEL1
TVDAC_A
TVDAC_B
TVDAC_C
TV_REFSET
TV_IRTNA
TV_IRTNB
TV_IRTNC
SDVOB_RED
SDVOB_GREEN
SDVOB_BLUE
SDVOB_CLKP
SDVOB_RED#
SDVOB_GREEN#
SDVOB_BLUE#
SDVOB_CLKN
SDVO_TVCLKIN
SDVO_INT
SDVO_FLDSTALL
SDV0_TVCLKIN#
SDVO_INT#
SDVO_FLDSTALL#
EXP_COMPI
EXP_ICOMPO
+V1.5S_PCIE
+V1.5S
+V3.3S
+V1.8
945GSE
LVDS
5
C53
0.1uF/16V,X7R
CFG/RSVD
PM
PM
CLK
CLK
SDVO
SDVO
TV
A
B
C
D
5
[11] M_A_DQ[63:0]
5
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
AG19
AG21
AG20
AC31
AB28
AE33
AF32
AC33
AB32
AB31
AE31
AH31
AK31
AL28
AK27
AH30
AL32
AJ28
AJ27
AH32
AF31
AH27
AF28
AJ32
AG31
AG28
AG27
AN27
AM26
AJ26
AJ25
AL27
AN26
AH25
AG26
AM12
AL11
AH9
AK9
AM11
AK11
AM8
AK8
AG9
AF9
AF8
AK6
AF7
AG11
AJ6
AH6
AN6
AM6
AK3
AL2
AM5
AL5
AJ3
AJ2
AG2
AF3
AE7
AF6
AH5
AG3
AG5
AF5
U3C
SB_CAS#
SB_RAS#
SB_WE#
SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63
945GSE
DDR2 SYSTEM MEMORY
DDR2 SYSTEM MEMORY
4
SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_BS_0
SB_BS_1
SB_BS_2
SA_CAS#
SA_RAS#
SA_RCVENINB
SA_RCVENOUTB
SA_WEB
SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_DQS0#
SA_DQS1#
SA_DQS2#
SA_DQS3#
SA_DQS4#
SA_DQS5#
SA_DQS6#
SA_DQS7#
SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7
SA_DM0
SA_DM1
SA_DM2
SA_DM3
SA_DM4
SA_DM5
SA_DM6
SA_DM7
SA_BS_0
SA_BS_1
SA_BS_2
4
M_A_A[13:0] [11]
M_A_DQS#[7:0] [11]
M_A_DQS[7:0] [11]
M_A_BS0
[11]
M_A_BS1
[11]
M_A_BS2
[11]
M_A_DM[7:0] [11]
AN20
AL21
AK21
AK22
AL22
AH22
AG22
AF21
AM21
AE21
AL20
AE22
AE26
AE20
AH21
AJ20
AE27
AJ17
M_A_CAS# [11]
AK18
M_A_RAS# [11]
TP14ns
AN28 TP_SA_RCVENIN#
TP15ns
AM28 TP_SA_RCVENOUT#
AH17
M_A_WE#
[11]
AJ15 M_A_A0
AM17 M_A_A1
AM15 M_A_A2
AH15 M_A_A3
AK15 M_A_A4
AN15 M_A_A5
AJ18 M_A_A6
AF19 M_A_A7
AN17 M_A_A8
AL17 M_A_A9
AG16 M_A_A10
AL18 M_A_A11
AG18 M_A_A12
AL14 M_A_A13
AC29 M_A_DQS#0
AK30 M_A_DQS#1
AJ33 M_A_DQS#2
AM25 M_A_DQS#3
AN8 M_A_DQS#4
AJ8 M_A_DQS#5
AM3 M_A_DQS#6
AE2 M_A_DQS#7
AC28 M_A_DQS0
AJ30 M_A_DQS1
AK33 M_A_DQS2
AL25 M_A_DQS3
AN9 M_A_DQS4
AH8 M_A_DQS5
AM2 M_A_DQS6
AE3 M_A_DQS7
AB30 M_A_DM0
AL31 M_A_DM1
AF30 M_A_DM2
AK26 M_A_DM3
AL9 M_A_DM4
AG7 M_A_DM5
AK5 M_A_DM6
AH3 M_A_DM7
AK12
AH11
AG17
+V1.05S
3
+V1.05S
3
M10
A18
AB10
AA10
T10
R10
P10
N10
L10
D1
T25
R25
P25
N25
M25
P24
N24
M24
Y22
W22
V22
U22
T22
R22
P22
N22
M22
Y21
W21
V21
U21
T21
R21
P21
N21
M21
Y20
W20
V20
U20
T20
R20
P20
N20
M20
Y19
P19
N19
M19
Y18
P18
N18
M18
Y17
P17
N17
M17
Y16
P16
N16
M16
Y15
P15
N15
M15
Y14
W14
V14
U14
T14
R14
P14
N14
M14
MCH_RSVD3
MCH_RSVD4
MCH_RSVD5
MCH_RSVD6
VTT_NCTF1
VTT_NCTF2
VTT_NCTF3
VTT_NCTF4
VTT_NCTF5
VTT_NCTF6
VCC_NCTF1
VCC_NCTF2
VCC_NCTF3
VCC_NCTF4
VCC_NCTF5
VCC_NCTF6
VCC_NCTF7
VCC_NCTF8
VCC_NCTF9
VCC_NCTF10
VCC_NCTF11
VCC_NCTF12
VCC_NCTF13
VCC_NCTF14
VCC_NCTF15
VCC_NCTF16
VCC_NCTF17
VCC_NCTF18
VCC_NCTF19
VCC_NCTF20
VCC_NCTF21
VCC_NCTF22
VCC_NCTF23
VCC_NCTF24
VCC_NCTF25
VCC_NCTF26
VCC_NCTF27
VCC_NCTF28
VCC_NCTF29
VCC_NCTF30
VCC_NCTF31
VCC_NCTF32
VCC_NCTF33
VCC_NCTF34
VCC_NCTF35
VCC_NCTF36
VCC_NCTF37
VCC_NCTF38
VCC_NCTF39
VCC_NCTF40
VCC_NCTF41
VCC_NCTF42
VCC_NCTF43
VCC_NCTF44
VCC_NCTF45
VCC_NCTF46
VCC_NCTF47
VCC_NCTF48
VCC_NCTF49
VCC_NCTF50
VCC_NCTF51
VCC_NCTF52
VCC_NCTF53
VCC_NCTF54
VCC_NCTF55
VCC_NCTF56
VCC_NCTF57
VCC_NCTF58
VCC_NCTF59
VCC_NCTF60
VCC_NCTF61
VCC_NCTF62
VCC_NCTF63
VCC_NCTF64
U3H
945GSE
NCTF
2
MCH_RSVD10
MCH_RSVD11
MCH_RSVD12
MCH_RSVD13
MCH_RSVD14
MCH_RSVD15
MCH_RSVD16
MCH_RSVD17
MCH_RSVD18
MCH_RSVD19
MCH_RSVD20
MCH_RSVD21
MCH_RSVD22
MCH_RSVD23
MCH_RSVD24
MCH_RSVD25
CFG19
VCCAUX_NCTF1
VCCAUX_NCTF2
VCCAUX_NCTF3
VCCAUX_NCTF4
VCCAUX_NCTF5
VCCAUX_NCTF6
VCCAUX_NCTF7
VCCAUX_NCTF8
VCCAUX_NCTF9
VCCAUX_NCTF10
VCCAUX_NCTF11
VCCAUX_NCTF12
VCCAUX_NCTF13
VCCAUX_NCTF14
VCCAUX_NCTF15
VCCAUX_NCTF16
VCCAUX_NCTF17
VCCAUX_NCTF18
VCCAUX_NCTF19
VCCAUX_NCTF20
VCCAUX_NCTF21
VCCAUX_NCTF22
VCCAUX_NCTF23
VCCAUX_NCTF24
VCCAUX_NCTF25
VCCAUX_NCTF26
VCCAUX_NCTF27
VCCAUX_NCTF28
VCCAUX_NCTF29
VCCAUX_NCTF30
VCCAUX_NCTF31
VCCAUX_NCTF32
VCCAUX_NCTF33
VCCAUX_NCTF34
VCCAUX_NCTF35
VCCAUX_NCTF36
VCCAUX_NCTF37
VCCAUX_NCTF38
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
VSS_NCTF8
VSS_NCTF9
VSS_NCTF10
VSS_NCTF11
VSS_NCTF12
VSS_NCTF13
VSS_NCTF14
VSS_NCTF15
VSS_NCTF16
VSS_NCTF17
VSS_NCTF18
VSS_NCTF19
2
K25
K26
R24
T24
K21
K19
K20
K24
K22
J17
K23
K17
K12
K13
K16
K15
K28
AD25
AC25
AB25
AD24
AC24
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
K14
AD13
Y13
W13
V13
U13
T13
R13
P13
N13
M13
AD12
Y12
W12
V12
U12
T12
R12
P12
N12
M12
AD11
AD10
K10
AN33
AA25
V25
U25
AA22
AA21
AA20
AA19
AA18
AA17
AA16
AA15
AA14
AA13
A4
A33
B2
AN1
C1
+V1.05S
+V1.5S
+V3.3S
Date:
Size
A3
Title
MCH_CFG_19
(DMI LANE REVSERSAL)
R88
1K
ns
+V3.3S
+V1.5S
GMS_CFG19
+V1.05S
+V1.5S
+V3.3S
Q10
945GSE DDRII
1
Thursday, February 26, 2009
Project Name
CZC Technology
LOW=NORMAL
HIGH=LANES REVERSED
Sheet
8
of
Rev
B
48
[3,4,5,6,9,12,15,17,26,33,35,38]
[4,7,9,13,15,20,33,35,38]
[5,7,9,11,12,13,14,15,17,18,20,22,23,25,26,27,28,34,35,36,38]
1
A
B
C
D
A
B
C
10uH/60mA
FB1
+V2.5S
+V1.5S
10
C98
10uF/6.3V,X5R
10uF/6.3V,X5R
FB3
5
120ohm/100MHz,1A
R89
1.0uH/1A
L4
82nH/950mA
L3
Place close to
MCH
120ohm/100MHz,1A
FB2
ns
10uH/60mA
LQM21FN100M70
10uH/100mA
L2
LQM21FN100M70
10uH/100mA
L1
120ohm/100MHz,1A
+V1.5S
CT5
22uF/6.3V,TAN
CT6
22uF/6.3V,TAN
CT7
22uF/6.3V,TAN
CT8
22uF/6.3V,TAN
+V1.5S_DPLLA
+V1.5S_DPLLB
+V1.5S_HPLL
+V2.5S_CRTDAC
D2
BAT54C
+V1.05S
+V1.5S_3GPLL
+V1.5S_PCIE
+V1.5S_MPLL
ns
C56
4.7uF/10V,X5R
+V1.05S
4
C82
4.7uF/10V,X5R
C81
4.7uF/10V,X5R
C58
C58
0.1uF/16V,X7R
0.1uF/16V,X7R
C57
C57
4.7uF/10V,X5R
Place in cavity
A14
D10
P9
L9
D9
P8
L8
D8
P7
L7
D7
A7
P6
L6
G6
D6
U5
P5
L5
G5
D5
Y4
U4
P4
L4
G4
D4
Y3
U3
P3
L3
G3
D3
Y2
U2
P2
L2
G2
D2
AA1
F1
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AC27
AD26
AC26
AB26
AE19
AE18
AF17
AE17
AF16
AE16
AF15
AE15
J14
J10
H10
AE9
AD9
U9
AD8
AD7
AD6
VTT0
VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9
VTT10
VTT11
VTT12
VTT13
VTT14
VTT15
VTT16
VTT17
VTT18
VTT19
VTT20
VTT21
VTT22
VTT23
VTT24
VTT25
VTT26
VTT27
VTT28
VTT29
VTT30
VTT31
VTT32
VTT33
VTT34
VTT36
VTT35
VTT37
VTT38
VTT39
VTT40
3
VCC_AUX1
VCC_AUX2
VCC_AUX3
VCC_AUX4
VCC_AUX5
VCC_AUX6
VCC_AUX7
VCC_AUX8
VCC_AUX9
VCC_AUX10
VCC_AUX11
VCC_AUX12
VCC_AUX13
VCC_AUX14
VCC_AUX15
VCC_AUX16
VCC_AUX17
VCC_AUX18
VCC_AUX19
VCC_AUX20
VCC_AUX21
VCC_AUX22
VCC_AUX23
VCC_AUX24
VCC_AUX25
VCC_AUX26
VCC_AUX27
VCC_AUX28
POWER
POWER
945GSE
VTT41
VTT42
VTT43
VTT44
VTT45
VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1
VCCA_TVBG
VSSA_TVBG
VCCD_TVDAC
VCCDQ_TVDAC
VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2
VCCHV0
VCCHV1
VCCHV2
VCCSM0
VCCSM1
VCCSM2
VCCSM3
VCCSM4
VCCSM5
VCCSM6
VCCSM7
VCCSM8
VCCSM9
VCCSM10
VCCSM11
VCCSM12
VCCSM13
VCCSM14
VCCSM15
VCCSM16
VCCSM17
VCCSM18
VCCSM19
VCCSM20
VCCSM21
VCCSM22
VCCSM23
VCCSM24
VCCSM25
VCCSM26
VCCSM27
VCCSM28
VCCSM29
VCCSM30
VCCSM31
VCCSM32
VCCSM33
VCCSM34
VCCSM35
VCCSM36
VCCSM37
VCCSM38
VCCSM39
VCCSM40
VCCSM41
VCCSM42
VCCSM43
VCCSM44
VCCSM45
VCCSM46
VCCSM47
VCCSM48
VCCSM49
VCCSM50
VCCSM51
VCCA_MPLL
VCCA_HPLL
VCCA_DPLLA
VCCA_DPLLB
VCCD_HMPLL1
VCCD_HMPLL2
VCCTX_LVDS0
VCCTX_LVDS1
VCC3G0
VCC3G1
VCCA_3GPLL
VCCA_3GBG
VSSA_3GBG
VCC_SYNC
VCCA_CRTDAC0
VCCA_CRTDAC1
VSSA_CRTDAC
VCCA_LVDS
VSSALVDS
P1
L1
G1
U1
Y1
B20
A20
B22
A22
D22
C22
D23
E23
F20
F22
C28
B28
A28
E26
D26
C26
AB33
AM32
AN29
AM29
AL29
AK29
AJ29
AH29
AG29
AF29
AE29
AN24
AM24
AL24
AK24
AJ24
AH24
AG24
AF24
AE24
AN18
AN16
AM16
AL16
AK16
AJ16
AN13
AM13
AL13
AK13
AJ13
AH13
AG13
AF13
AE13
AN4
AM10
AL10
AK10
AH1
AH10
AG10
AF10
AE10
AN7
AM7
AL7
AK7
AJ7
AH7
AN10
AJ10
AD1
AD2
B26
J32
AE5
AD5
D29
C29
U33
T33
V26
N33
M33
J23
C24
B24
B25
B31
B32
Disable TV
+VCC_CRTDAC
VSSCRTDAC
+VCCA_LVDS
VSSA_LVDS
+VCC_3GPLL
+VCCA_3GB
VSSA_3GB
+VCC_SYNC
+V1.5S_PCIE
+VCC_LVDS
+V1.5S_MPLL
+V1.5S_HPLL
+V1.5S_DPLLA
+V1.5S_DPLLB
+V1.5S
+V1.5S
C64
1uF/10V,X5R
C84
1uF/10V,X5R
CT9
100uF/10V,TAN
U3D
VCC0
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
+V1.05S
2
C62
0.1uF/16V,X7R
+V1.5S
C71
1uF/10V,X5R
C59
0.1uF/16V,X7R
0.1uF/16V,X7R
+V1.5S
T26
R26
P26
N26
M26
V19
U19
T19
W18
V18
T18
R18
W17
U17
R17
W16
V16
T16
R16
V15
U15
T15
2
C63
10uF/6.3V,X5R
VSSA_LVDS
1
+V2.5S
Date:
VSSA_3GB
+VCCA_3GB
+V2.5S
Q10
945GSE Power
1
Thursday, February 26, 2009
Project Name
Sheet
9
of
Rev
B
C95
C96
0.1uF/16V,X7R 0.01uF/25V,X7R
+V2.5S_CRTDAC
CZC Technology
Size
Custom
Title
+V2.5S
VSSCRTDAC
+VCC_CRTDAC
+VCC_LVDS
+V2.5S
+V2.5S
[34,38]
+V1.5S_PCIE [7]
+V1.5S
[4,7,8,13,15,20,33,35,38]
+V3.3S
[5,7,8,11,12,13,14,15,17,18,20,22,23,25,26,27,28,34,35,36,38]
+V1.8
[7,11,32]
+V1.05S [3,4,5,6,8,12,15,17,26,33,35,38]
+V1.5S_3GPLL
+VCCA_LVDS
+VCC_SYNC
+VCC_3GPLL
ns
+V1.8
+V3.3S
+V2.5S
+V1.5S_PCIE
+V1.5S
+V3.3S
+V1.8
+V1.05S
Place in cavity
C72
4.7uF/10V,X5R
D
CT10
CT10
100uF/10V,TAN
3
C65
1uF/10V,X5R
C85
1uF/10V,X5R
C77
1uF/10V,X5R
C60
0.1uF/16V,X7R
C70
0.1uF/16V,X7R
C104
0.47uF/16V,X7R
0.47uF/16V,X7R
C69
0.1uF/16V,X7R
C76
0.1uF/16V,X7R
C67
0.1uF/16V,X7R
C73
4.7uF/10V,X5R
+V1.05S
CT15
100uF/10V,TAN
C68
C68
10uF/6.3V,X5R
CT14
CT14
100uF/10V,TAN
C86
C86
0.1uF/16V,X7R
C93
C93
0.1uF/16V,X7R
C79
0.1uF/16V,X7R
C91
0.1uF/16V,X7R
C99
10uF/6.3V,X5R
3
C87
10uF/6.3V,X5R
10uF/6.3V,X5R
C94
10uF/6.3V,X5R
10uF/6.3V,X5R
C83
C83
0.47uF/16V,X7R
C92
C92
0.47uF/16V,X7R
C103
C103
0.47uF/16V,X7R
0.47uF/16V,X7R
C88
C88
0.1uF/16V,X7R
4
C100
0.1uF/16V,X7R
5
1
C105
10uF/6.3V,X5R
10uF/6.3V,X5R
C101
0.01uF/25V,X7R
C89
4.7uF/10V,X5R
4.7uF/10V,X5R
C102
0.1uF/16V,X7R
0.1uF/16V,X7R
C55
10uF/6.3V,X5R
2
48
A
B
C
D
A
B
C
D
5
5
AH33
Y33
V33
R33
G33
AK32
AG32
AE32
AC32
AA32
U32
H32
E32
C32
AM31
AJ31
AA31
U31
T31
R31
P31
N31
M31
J31
F31
AL30
AG30
AE30
AC30
AA30
Y30
V30
U30
G30
E30
B30
AA29
U29
R29
P29
N29
M29
H29
E29
B29
AK28
AH28
AE28
AA28
U28
T28
J28
D28
AM27
AF27
AB27
AA27
Y27
U27
T27
R27
P27
N27
M27
G27
E27
C27
B27
AL26
AH26
W26
U26
AN25
AK25
AG25
AE25
J25
G25
A25
H23
F23
B23
AM22
AJ22
AF22
G22
E22
J21
H21
F21
AM20
AK20
AH20
AF20
D20
W19
R19
AM18
AH18
AF18
U18
H18
D18
AK17
V17
T17
F17
B17
AH16
U16
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
U3E
VSS
VSS
945GSE
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
4
J16
AL15
AG15
W15
R15
F15
D15
AM14
AH14
AE14
H14
B14
F13
D13
AL12
AG12
H12
B12
AN11
AJ11
AE11
AM9
AJ9
AB9
W9
R9
M9
J9
F9
C9
A9
AL8
AG8
AE8
U8
AA7
V7
R7
N7
H7
E7
B7
AL6
AG6
AE6
AB6
W6
T6
M6
K6
AN5
AJ5
B5
AA4
V4
R4
N4
K4
H4
E4
AL3
AD3
W3
T3
B3
AK2
AH2
AF2
AB2
M2
K2
H2
F2
V1
R1
4
3
W33
AM33
AL33
C33
B33
AN32
A32
AN31
W28
V27
W29
J24
H24
W32
G24
F24
E24
D24
K33
A31
E21
C23
AN19
AM19
AL19
AK19
AJ19
AH19
AN3
Y9
J19
H19
G19
F19
E19
D19
C19
B19
A19
Y8
G16
F16
E16
D16
C16
B16
AN2
A16
Y7
AM4
AF4
AD4
AL4
AK4
W31
AJ4
AH4
AG4
AE4
AM1
3
U3G
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
NC17
NC18
NC19
NC20
NC21
NC22
NC23
NC24
NC25
NC26
NC27
NC28
NC29
NC30
NC31
NC32
NC33
NC34
NC35
NC36
NC37
NC38
NC39
NC40
NC41
NC42
NC43
NC44
NC45
NC46
NC47
NC48
NC49
NC50
NC51
NC52
NC53
NC54
NC55
NC56
NC57
NC58
NC59
NC60
945GSE
NC
NC
MCH_RSVD26
MCH_RSVD27
MCH_RSVD28
MCH_RSVD29
MCH_RSVD30
MCH_RSVD31
MCH_RSVD32
MCH_RSVD33
MCH_RSVD34
MCH_RSVD35
MCH_RSVD36
MCH_RSVD37
MCH_RSVD38
MCH_RSVD39
MCH_RSVD40
MCH_RSVD41
MCH_RSVD42
NC61
NC62
NC63
NC64
NC65
NC66
NC67
NC68
NC69
NC70
NC71
NC72
Y25
Y24
AB22
AB21
AB19
AB16
AB14
AA12
W24
AA24
AB24
AB20
AB18
AB15
AB13
AB12
AB17
W30
Y6
AL1
Y5
Y10
W10
W25
V24
U24
V10
U10
K18
2
2
Date:
Size
A3
Title
Q10
945GSE GND
1
Thursday, February 26, 2009
Project Name
CZC Technology
1
Sheet
10
of
Rev
B
48
A
B
C
D
A
B
C
D
M_VREF
5
C139
0.1uF/16V,X7R
+V3.3S
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
DIMM_SA0
DIMM_SA1
0 MBIAS_VREF
+V3.3S
[7] PM_EXTTS#0
R729
R92
R93
83
120
50
69
163
1
199
198
200
195
197
13
31
51
70
131
148
169
188
114
119
[7] M_ODT0
[7] M_ODT1
[8] M_A_DQS[7:0]
[7]
[7]
[7]
[7]
30
32
164
166
79
80
109
113
108
10
26
52
67
130
147
170
185
M_CLK_DDR0
M_CLK_DDR0#
M_CLK_DDR1
M_CLK_DDR1#
[7] M_CKE0
[7] M_CKE1
[8] M_A_WE#
[8] M_A_CAS#
[8] M_A_RAS#
[14,17,20] ICH7M_SMB_DATA
[14,17,20] ICH7M_SMB_CLK
[32]
M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7
110
115
[7] M_CS#0
[7] M_CS#1
[8] M_A_DM[7:0]
102
101
100
99
98
97
94
92
93
91
105
90
89
116
86
84
85
107
106
10K
10K
T2
T1
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
ns
ns
[8] M_A_BS0
[8] M_A_BS1
[8] M_A_BS2
[8] M_A_A[13:0]
+V1.8
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
A16_BA2
NC1
NC2
NC3
NC4
NCTEST
VREF1
VDDSPD
SA0
SA1
SDA
SCL
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
ODT0
ODT1
CK0
CK0
CK1
CK1
CKE0
CKE1
WE
CAS
RAS
DQM0
DQM1
DQM2
DQM3
DQM4
DQM5
DQM6
DQM7
CS0
CS1
BA0
BA1
4
Address: 1010 000x=A0H
CLOCK 0,1
CKE 0,1
DIM1
DDR2_STD_4.0
DDR2S200H40_STD
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
D41
D42
D43
D44
D45
D46
D47
D48
D49
D50
D51
D52
D53
D54
D55
D56
D57
D58
D59
D60
D61
D62
D63
DQS#0
DQS#1
DQS#2
DQS#3
DQS#4
DQS#5
DQS#6
DQS#7
112
111
117
96
95
118
81
82
87
103
88
104
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
4
MBIAS_VREF
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
R95
10K,1%
ns
R94
10K,1%
ns
3
+V1.8
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
11
29
49
68
129
146
167
186
3
5
7
17
19
4
6
14
16
23
25
35
37
20
22
36
38
43
45
55
57
44
46
56
58
61
63
73
75
62
64
74
76
123
125
135
137
124
126
134
136
141
143
151
153
140
142
152
154
157
159
173
175
158
160
174
176
179
181
189
191
180
182
192
194
C128
1uF/10V,X5R
Close to DDRII pin
C135
0.1uF/16V,X7R
47
133
183
77
12
48
184
78
71
72
121
122
196
193
8
18
24
41
53
42
54
59
65
60
66
127
139
128
145
165
171
172
177
5
187
178
190
9
21
33
155
34
132
144
156
168
2
3
15
27
39
149
161
28
40
138
150
162
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
GND0
GND1
201
202
56 x4
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
8
56 x4
2
4
6
8
56
+V0.9S
56
RN6
R91
56 x4
2
4
6
8
RN5
56 x4
RN4
RN3
56 x4
RN2
56 x4
RN1
R90
1
3
5
7
1
3
5
7
1
3
5
7
1
3
5
7
1
3
5
7
1
3
5
7
M_A_DQS#[7:0] [8]
+V0.9S
M_A_DQ[63:0] [8]
2
2
C129
0.1uF/16V,X7R
C121
0.1uF/16V,X7R
M_A_WE#
M_A_A8
M_A_A13
M_ODT0
M_A_RAS#
M_CS#0
M_A_CAS#
M_CS#1
M_ODT1
M_A_BS0
M_A_A5
M_A_A3
M_A_A1
M_A_A10
M_A_BS2
M_A_A9
M_A_A12
M_CKE0
M_A_BS1
M_A_A0
M_A_A4
M_A_A2
M_A_A6
M_A_A7
M_A_A11
M_CKE1
+V3.3S
+V0.9S
+V1.8
C130
0.1uF/16V,X7R
C122
0.1uF/16V,X7R
Date:
C133
0.1uF/16V,X7R
Q10
DDR2 SODIMM
1
Thursday, February 26, 2009
Project Name
Sheet
C134
0.1uF/16V,X7R
C126
0.1uF/16V,X7R
C119
0.1uF/16V,X7R
C114
1uF/10V,X5R
CZC Technology
C132
0.1uF/16V,X7R
Size
A3
Title
C131
0.1uF/16V,X7R
C125
0.1uF/16V,X7R
C118
0.1uF/16V,X7R
C113
1uF/10V,X5R
C110
1uF/10V,X5R
11
of
Rev
B
48
C127
0.1uF/16V,X7R
C120
0.1uF/16V,X7R
C115
1uF/10V,X5R
C106
1uF/10V,X5R
DDR slot VDD PIN
C109
1uF/10V,X5R
C124
0.1uF/16V,X7R
C117
0.1uF/16V,X7R
C112
1uF/10V,X5R
C123
0.1uF/16V,X7R
C116
0.1uF/16V,X7R
+V1.8
C111
1uF/10V,X5R
+V1.8
C108
1uF/10V,X5R
Layout note:
[5,7,8,9,12,13,14,15,17,18,20,22,23,25,26,27,28,34,35,36,38]
[32,38]
[7,9,32]
CT17
100uF/10V,TAN
ns
+V1.8
+V3.3S
+V0.9S
+V1.8
1
A
B
C
D
A
B
C
D
SATA_RXN1
SATA_RXP1
SATA_TXN1
SATA_TXP1
[19]
[19]
[19]
[19]
+V1.05S
56
56
56
56
1K
1K
R110 ns
R112 ns
R114
R117
R122 ns
R121 ns
5
Short pins AH10 and
AG10 at the package.
Place R within 500mils of ICH7 ball
[17] CLK_PCIE_SATA#
[17] CLK_PCIE_SATA
SATA_RXN0
SATA_RXP0
SATA_TXN0
SATA_TXP0
[19]
[19]
[19]
[19]
[27] SATA_LED#
[22] HDA_SDATAOUT
[22] HDA_SDATAIN0
[22] HDA_RST#
[22] HDA_BITCLK
[22] HDA_SYNC
R108
C233
C234
C142
C143
SATA_RXP1
SATA_RXN1
PM_THRMTRIP#
H_FERR#
H_DPSLP#
33
33
IDEREQ
IORDY
SATA_RBIAS_PN
SATA_TXN1_C
SATA_TXP1_C
SATA_TXN0_C
SATA_TXP0_C
SATA_LED#_R
ACZ_SDATAOUT_R
ACZ_RST#_R
ACZ_BITCLK_R
ACZ_SYNC_R
SM_INTRUDER#
ICH_INTVRMEN
AF15
AH15
AF16
AH16
AG16
AE15
AH10
AG10
AF1
AE1
AF7
AE7
AG6
AH6
AF3
AE3
AG2
AH2
AF18
T4
T2
T3
T1
R5
U1
R6
U7
V6
V7
U5
V4
T5
U3
V3
W1
Y1
Y2
W3
Y5
W4
AA3
RTC_RST#
H_DPRSTP# should be routed as
" Daisy chain " CMOS topology,
routed from ICH to IMVP to CPU
in this order exactly
24.9,1%
3900pF/50V,X7R
3900pF/50V,X7R
3900pF/50V,X7R
3900pF/50V,X7R
33
R103
R105
33
R101
R102
10pF/50V,NPO
ns
H_DPRSTP#
C410
AB1
AB2
RTC_X1
RTC_X2
U5A
4
1K ACZ_SDATAOUT_R
ns
1K FWH_INIT#
ns
10K LDRQ0#
10K LDRQ1#
4.7K IORDY
10K IDEREQ
R119
10K CPU_A20GATE-
R118
10K H_RCIN#
DCS1#
DCS3#
DA0
DA1
DA2
DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9
DD10
DD11
DD12
DD13
DD14
DD15
THERMTRIP#
STPCLK#
NMI
SMI#
RCIN#
IGNNE#
INIT3_3V#
INIT#
INTR
GPIO49/CPUPWRGD
FERR#
TP1/DPRSTP#
TP2/DPSLP#
CPUSLP#
A20GATE
A20M#
LFRAME#
LDRQ0#
LDRQ1#/GPIO23
LAD0
LAD1
LAD2
LAD3
R115
R113
IDE
+V3.3S
NH82801GBM
DIOR#
DIOW#
DDACK#
IDEIRQ
IORDY
DDREQ
SATARBIASN
SATARBIASP
SATA_CLKN
SATA_CLKP
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATALED#
ACZ_SDOUT
ACZ_SDIN0
ACZ_SDIN1
ACZ_SDIN2
ACZ_RST#
ACZ_BIT_CLK
ACZ_SYNC
LAN_TXD0
LAN_TXD1
LAN_TXD2
LAN_RXD0
LAN_RXD1
LAN_RXD2
LAN_RSTSYNC
LAN_CLK
EE_CS
EE_SHCLK
EE_DOUT
EE_DIN
INTRUDER#
INTVRMEN
RTCRST#
RTCX1
RTCX2
RTC
LPC
LPC
LAN
CPU
CPU
AC-97/AZALIA
SATA
4
R416
R417
R562
R430
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
FWH_INIT#
H_FERR#
AE16
AD16
AH17
AE17
AF17
24.9,1%
3
[3]
[3]
[3]
[3]
[26]
[3,38]
2
2
1
R97
1M
20K,1%
3
1
2
C145 15pF/50V,NPO
+
2
Date:
Size
A3
Title
1
RTCBAT1
RTC Battery with Cable
Disable
Enable(default)
STUFF
RTCSPNG1
RTC Battery Sponge
UNSTUFF
STUFF
Q10
1
Sheet
12
ICH7M IDE/SATA/LPC/RTC/AUDIO
Thursday, February 26, 2009
Project Name
CZC Technology
0
1
UNSTUFF
ACES
85204-02X01
Y1
32.768kHz,10ppm,12.5pF
X4S67X15
INTVRMEN
R100
1K
RTCCN1
W-B-2P-R
HWS2_1P25R
1
+V3.3AUX
D3
BAT54C
SOT23
C144 15pF/50V,NPO
CLRCMOS:
Shunt
Open
1
2
C140
1uF/10V,X5R
2
ICH7 intel VccSus1.05 enable strap
RTC_X2
R107
10M
CMOS Settings
Clear CMOS
Keep CMOS
RTC_X1
CLRCMOS
JOPEN
RESISTOR_1
ns
RTC_RST#
SM_INTRUDER#
R96
C141
1uF/10V,X5R
+V3.3A_RTC
+V1.05S
[3,4,5,6,8,9,15,17,26,33,35,38]
+V3.3S
[5,7,8,9,11,13,14,15,17,18,20,22,23,25,26,27,28,34,35,36,38]
+V3.3A_RTC [15]
+V3.3AUX [5,13,14,15,18,20,25,26,27,29,30,31,34,38]
RTC_RST#
ICH_INTVRMEN
R111
332K,1%
+V3.3A_RTC
PM_THRMTRIP# [3,5,7]
H_STPCLK# [3]
H_NMI
H_SMI#
H_RCIN#
H_INIT#
H_INTR
H_IGNNE# [3]
CPU_PWRGD
H_FERR# [3]
H_DPRSTP# [3,38]
H_DPSLP# [3,38]
CPU_A20GATE- [26]
H_A20M# [3]
R106 need to place within 2 " of ICH7
R104 must be placed within 2 " of R129 W/O stub
R106
0
0
0
[26,27,38]
[26,27,38]
[26,27,38]
[26,27,38]
+V1.05S
+V3.3S
+V3.3A_RTC
+V3.3AUX
LPC_FRAME# [26,27,38]
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
R118 strap functionality based on ICH_TP3 strap:
XOR chain entrance(ICH_TP3 pulled low)
PCIE port config bit 1(ICH_TP3 not pulled low)
AB15
AE14
AG13
AF13
AD14
AC13
AD12
AC12
AE12
AF12
AB13
AC14
AF14
AH13
AH14
AC15
AF26
H_THRMTRIP_R
AH24
AF23
AH22
H_SMI#_R
AG23
R104
H_DPRSTP#_R R98
H_DPSLP#_R R99
H_RCIN#
AG22
AG21
AF22
AF25
AG24
AG26
AF24
AH25
AG27
AE22
AH28
CPU_A20GATE-
AC3
AA5
AB3
LDRQ0#
LDRQ1#
AA6
AB5
AC4
Y6
3
1
4
5
2
3
3
3
4
4
of
Rev
B
48
A
B
C
D
A
B
C
D
USB_OC1#
USB_OC2#
USB_OC3#
01
SPI
5
10
11
STRAP
STUFF
UNSTUFF
UNSTUFF
GNT5#
INT_PIRQA#
INT_PIRQB#
INT_PIRQC#
INT_PIRQD#
UNSTUFF
STUFF
UNSTUFF
GNT4#
USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
USB_OC4#
USB_OC5#
USB_OC6#
USB_OC7#
C147 0.1uF/16V,X7R
C149 0.1uF/16V,X7R
C146 0.1uF/16V,X7R
C148 0.1uF/16V,X7R
ICH7 Boot BIOS select
PCI
LPC(Default)
PCIE_RXN2_SLOT
PCIE_RXP2_SLOT
PCIE_TXN2_SLOT
PCIE_TXP2_SLOT
[20]
[20]
[20]
[20]
[23]
[23]
[23]
PCIE_RXN1_LAN
PCIE_RXP1_LAN
PCIE_TXN1_LAN
PCIE_TXP1_LAN
[25]
[25]
[25]
[25]
Layout Note: PCIE AC coupling caps need
to be within 250 mils of the driver
AE5
AD5
AG4
AH4
AD9
A3
B4
C5
B5
E18
C18
A16
F18
E16
A18
E17
A17
A15
C14
E14
D14
B12
C13
G15
G13
E12
C11
D11
A11
A10
F11
F10
E9
D9
B9
A8
A6
C7
B6
E6
D6
D3
C4
D5
D4
E5
C3
A2
B3
P5
P2
R2
P6
P1
T25
T24
R28
R27
P26
P25
N28
N27
M26
M25
L28
L27
K26
K25
J28
J27
H26
H25
G28
G27
F26
F25
E28
E27
PCI
PLTRST#
PCICLK
PME#
IRDY#
PAR
PCIRST#
DEVSEL#
PERR#
PLOCK#
SERR#
STOP#
TRDY#
FRAME#
C/BE0#
C/BE1#
C/BE2#
C/BE3#
REQ0#
GNT0#
REQ1#
GNT1#
REQ2#
GNT2#
REQ3#
GNT3#
REQ4#/GPIO22
GNT4#/GPIO48
REQ5#/GPIO1
GNT5#/GPIO17
4
GPIO2/PIRQE#
GPIO3/PIRQF#
GPIO4/PIRQG#
GPIO5/PIRQH#
RSVD[6]
RSVD[7]
RSVD[8]
TP3
MCH_SYNC#
MISC
NH82801GBM
RSVD[1]
RSVD[2]
RSVD[3]
RSVD[4]
RSVD[5]
PIRQA#
PIRQB#
PIRQC#
PIRQD#
D2
D1
F1
F2
G4
G3
H1
H2
J4
J3
K1
K2
L4
L5
M1
M2
N4
N3
C25
D25
AE28
AE27
AD25
AD24
AC28
AC27
AB26
AB25
AA28
AA27
Y26
Y25
W28
W27
V26
V25
U28
U27
22.6,1%
USB_PN0
USB_PP0
USB_PN1
USB_PP1
USB_PN2
USB_PP2
USB_PN3
USB_PP3
USB_PN4
USB_PP4
USB_PN5
USB_PP5
USB_PN6
USB_PP6
USB_PN7
USB_PP7
USB_RBIAS_PN R131
DMI_IRCOMP_R
AE9
AG8
AH8
F21
AH20
G8
F7
F8
G7
C26
A9
B19
A7
E10
B18
A12
C9
E11
B10
F15
F14
F16
B15
C12
D12
C15
D7
E7
C16
D16
C17
D17
E13
F13
A13
A14
C8
D8
INT_PIRQE#
INT_PIRQF#
INT_PIRQG#
INT_PIRQH#
PLT_RST#
PCI_DEVSEL#
PCI_PERR#
PCI_LOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#
PCI_IRDY#
PCI_REQ#3
PCI_GNT#3
PCI_REQ#4
PCI_GNT#4
PCI_REQ#5
PCI_GNT#5
PCI_REQ#2
PCI_REQ#1
PCI_REQ#0
[7]
[7]
[7]
[7]
[7]
[7]
[7]
[7]
3
USB Port
Port0
Port1
Port2
Port3
Port4
Port5
Port6
Port7
[7]
[17]
ICH_TP3
MCH_ICH_SYNC#
CLK_PCIF_ICH
[23]
[23]
[23]
[23]
[23]
[23]
[20]
[20]
[24]
[24]
[23]
[23]
[18]
[18]
[21]
[21]
CLK_PCIE_ICH# [17]
CLK_PCIE_ICH [17]
DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1
DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0
3
Place within 500 mils of ICH, avoid routing
next to clock/high speed signals
USBRBIAS#
USBRBIAS
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
DMI_ZCOMP
DMI_IRCOMP
DMI_CLKN
DMI_CLKP
DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP
DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP
DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP
DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP
Interrupt I/F
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
U5B
NH82801GBM
OC0#
OC1#
OC2#
OC3#
OC4#
OC5#/GPIO29
OC6#/GPIO30
OC7#/GPIO31
SPI_MOSI
SPI_MISO
SPI_CLK
SPI_CS#
SPI_ARB
PERn6
PERp6
PETn6
PETp6
PERn5
PERp5
PETn5
PETp5
PERn4
PERp4
PETn4
PETp4
PERn3
PERp3
PETn3
PETp3
PERn2
PERp2
PETn2
PETp2
PERn1
PERp1
PETn1
PETp1
U5D
PCI-Express
PCI-Express
SPI
SPI
4
Direct Media Interface
Direct Media Interface
USB
5
Position
Main board Mini PCI-E
Main board USB PORT
Main board USB PORT
Main board USB PORT
USB Cardreader
No Connect
Power board PC Camera
No Connect
R109
1K
ns
2
R124
R120
USB_OC6#
PLT_RST#
PLTRST#
2
Stuff R109 foe XOR chain testing
ICH_TP3
[27]
[7,14,20,25,26,38]
1
24.9,1%
10K
10K
10K
10K
10K
4
R130
100K
+V1.5S
+V3.3AUX
+V3.3S
Date:
Size
A3
Title
GND
VCC
R698
R695
R696
R697
R701
R700
R699
R702
PCI_PERR#
PCI_SERR#
PCI_LOCK#
INT_PIRQE#
INT_PIRQF#
PCI_IRDY#
PCI_REQ#0
PCI_REQ#5
R132
R133
R694
R691
R692
R693
INT_PIRQA#
INT_PIRQB#
INT_PIRQC#
INT_PIRQD#
R136 ns
R137 ns
R138 ns
PCI_GNT#4
PCI_GNT#5
PCI_GNT#4
PCI_GNT#5
PCI_GNT#3
PLT_RST#
C150
0.1uF/16V,X7R
R134
R135
INT_PIRQG#
INT_PIRQH#
R690
R687
R688
R689
PCI_DEVSEL#
PCI_REQ#3
PCI_TRDY#
PCI_STOP#
1K
1K
1K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
Q10
1
Sheet
ICH7M PCI-E/PCI/DMI/USB
Thursday, February 26, 2009
Project Name
CZC Technology
U6
SOT23_5
SN74AHC1G08DBV
2
1
R683
R684
R685
R686
PCI_FRAME#
PCI_REQ#2
PCI_REQ#1
PCI_REQ#4
+V1.5S
[4,7,8,9,15,20,33,35,38]
+V3.3S
[5,7,8,9,11,12,14,15,17,18,20,22,23,25,26,27,28,34,35,36,38]
+V3.3AUX [5,12,14,15,18,20,25,26,27,29,30,31,34,38]
Place within 500 mils of ICH
DMI_IRCOMP_R R129
R128
R126
USB_OC5#
USB_OC7#
R125
USB_OC4#
USB_OC0#
+V1.5S
+V3.3S
+V3.3AUX
5
3
13
of
+V3.3S
Rev
B
48
A
B
C
D
A
B
C
D
[26] PM_CLKRUN#
5
[36] VR_PWRGD_CLKEN#
R276
R243
10K
+V3.3S
VR_PWRGD_CLKEN_R
2
1
0
0
+V3.3S
GND
VCC
1K
U27
SN74AHC1G08DBV
SOT23_5
[26] KBCSCI[26] KBCSMI-
[26,35,38] MAIN_PWROK
R147
R149
SPKR
PM_SUS_STAT#
[26] EC_PCIPME[26,27] SERIRQ
[26] PM_THRM#
[17] PM_STPPCI#
[17,38] PM_STPCPU#
[7] PM_BMBUSY#
[22] SPKR
[18,26] PM_SUS_STAT#
4
C22
B22
A26
B25
A25
SYS_RST#
1
Q5
2N7002K
ns
4
SMB
SMB
0
SMB_DATA_A
SMB_CLK_A
PWROK
SLP_S3#
SLP_S4#
SLP_S5#
SUSCLK
CLK14
CLK48
GPIO21/SATA0GP
GPIO19/SATA1GP
GPIO36/SATA2GP
GPIO37/SATA3GP
R160
2.2K
+V3.3AUX
R161
2.2K
ICH_PWROK
GPIO9
GPIO10
GPIO12
GPIO13
GPIO14
GPIO15
GPIO24
GPIO25
GPIO35
GPIO38
GPIO39
RSMRST#
LAN_RST#
PWRBTN#
TP0/BATLOW#
GPIO16/DPRSLPVR
VR_PWRGD_CLKEN
[38] ICH_PWROK
[17]
GPIO
VR_PWRGD_CLKEN
VR_PWRGD_CLKEN_R
R278
NH82801GBM
GPIO6
GPIO7
GPIO8
VRMPWRGD
WAKE#
SERIRQ
THRM#
GPIO33/AZ_DOCK_EN#
GPIO34/AZ_DOCK_RST#
GPIO32/CLKRUN#
GPIO27
GPIO28
GPIO26
GPIO18/STPPCI#
GPIO20/STPCPU#
GPIO11/SMBALERT#
GPIO0/BM_BUSY#
SPKR
SUS_STAT#
SYS_RST#
RI#
SMBCLK
SMBDATA
LINKALERT#
SMLINK0
SMLINK1
U5C
VR_PWRGD_CLKEN
R158
10K
+V3.3S
4
AC21
AC18
E21
AD22
F20
AH21
AF20
AC19
U2
AG18
B21
E23
A21
AC20
AF21
B23
C204
0.1uF/16V,X7R
VR_PWRGD_CLKEN
PM_STPPCI_ICH#
PM_STPCPU_ICH#
SMB_ALERT#
A19
A27
A22
PM_RI#
AB18
A28
SMB_CLK_A
SMB_DATA_A
SMB_LINK_ALERT#
SMLINK0
SMLINK1
+V3.3S
[5,7,8,9,11,12,13,15,17,18,20,22,23,25,26,27,28,34,35,36,38]
+V3.3AUX [5,12,13,15,18,20,25,26,27,29,30,31,34,38]
5
3
SATA
GPIO
Clocks
SYS
GPIO
Power MGT
Power MGT
+V3.3S
+V3.3AUX
3
2
0
8.2K
8.2K
8.2K
8.2K
+V3.3S
3
GND
VCC
+V3.3S
2
3
3
Q6
2N7002K
C202
0.1uF/16V,X7R
2
R162
2.2K
+V3.3S
U13
SOT23_5
SN74AHC1G08DBV
2
1
EC_WAKE_SCI#
PM_RSMRST#_ICH R153
PLTRST#_R
Q4
2N7002K
4
E20
A20
F19
E19
R4
E22
R3
D20
AD21
AD20
AE20
Y4
C19
C23
100
0
R152
AC22
PM_BATLOW#
R148
PM_DPRSLPVR_R
C21
0
R386 ns
TP16
ns
R139
R140
R142
R143
ICH_PWROK
TP_SUSCLK
SATA0_R3
SATA0_R0
AA4
B24
D23
F22
C20
AC1
B2
AF19
AH18
AH19
AE19
3
5
3
1
5
1
PM_RSMRST# [26,31,35,38]
PLTRST# [7,13,20,25,26,38]
PM_PWRBTN# [26,38]
PM_BATLOW# [26]
PM_DPRSLPVR [7,36]
PM_ICH_PWROK [26]
PM_SLP_S3# [26,27,32,33,34,35,38]
PM_SLP_S4# [26,32,38]
PM_SLP_S5# [26]
CLK_REF_ICH [17]
CLK_USB48 [17]
R163
2.2K
2
ICH7M_SMB_DATA [11,17,20]
ICH7M_SMB_CLK [11,17,20]
IMVP_PWROK [7,26,36,38]
MAIN_PWROK [26,35,38]
+V3.3S
2
1K
10K
10K
R141 ns
R144
R145 ns
R154
R151
R150
R159 10K
R157 10K
SERIRQ
8.2K
8.2K
8.2K
PM_SLP_S5#
PM_SLP_S3#
PM_SLP_S4#
Date:
Size
A3
Title
SYS_RST#
R171 10K
EC_WAKE_SCI#
+V3.3AUX
+V3.3S
Q10
1
Sheet
14
ICH7M GPIO/SMBUS/Power MGT
Thursday, February 26, 2009
Project Name
CZC Technology
R234 10K
R174
R173
R172
R170 10K
SMB_ALERT#
R169
8.2K
R168 10K
SMLINK1
PM_BATLOW#
R167 10K
SMLINK0
PM_RI#
R166 10K
R165 10K
EC_PCIPME-
SMB_LINK_ALERT#
R164 1K
KBCSMI-
R156 10K
8.2K
8.2K
KBCSCI-
R155
PM_THRM#
100K
10K
PM_STPCPU#
PM_STPPCI#
SPKR
of
SPKR
" 0 " Reboot mode(default)
" 1 " No Reboot mode
PM_CLKRUN#
ICH7 Pullups
PM_RSMRST#
ICH_PWROK
+V3.3S
1
Rev
B
48
A
B
C
D
A
B
C
3
1
2
C151
1uF/10V,X5R
1.0uH/1A
L1210
L5
5
Placed within 100 mils of ICH
on the bottom or 140 mils on
the top AG9
Placed within 100 mils of ICH
on the bottom or 140 mils on
the top
+V1.5S_PCIE_ICH
C156 need be placed within 100
mils of pinF6 of ICH7 on the
bottomside or 140mils on the top
10mA
D6
BAT54C
GPLL_R_L
+V1.5S
+V1.5S
+V3.3AUX
+V1.5S
+V1.5S
50mA
V5REF_SUS
VCC5REF
G10
10mA
nsTP20
nsTP20
nsTP21
nsTP21
4
TP_VCCSUSLAN1 AA2
TP_VCCSUSLAN2 Y7
C1
E3
AB10
AB9
AC10
AD10
AE10
AF10
AF9
AG9
AH9
VCC1_5_A Total 1.01A
52mA
AH11
AD2
AB7
AC6
AC7
AD6
AE6
AF5
AF6
AG5
AH5
AG28
B27
AA22
AA23
AB22
AB23
AC23
AC24
AC25
AC26
AD26
AD27
AD28
D26
D27
D28
E24
E25
E26
F23
F24
G22
G23
H22
H23
J22
J23
K22
K23
L22
L23
M22
M23
N22
N23
P22
P23
R22
R23
R24
R25
R26
T22
T23
T26
T27
T28
U22
U23
V22
V23
W22
W23
Y22
Y23
F6
AD17
VCC3_3 Total 0.33A
50mA
VCC1_5_A Total 1.01A
Placed within 100 mils of ICH
on the bottom side or 140 mils
on the top
+V3.3S
Placed above caps within 100
mils of on the bottom side or 140
mils on the top near D28 T28 AD28
CT12
100uF/10V,TAN
Placed within 100 mils of ICH
on the bottom or 140 mils on
the top
+V3.3S
6mA
+V3.3AUX
VCC1_5_B Total 0.77A
2
Placed within 100 mils of ICH
on the bottom side or 140 mils
on the top near pin AG5
0
R0603
100ohm/100MHz,2A
FB6
R177
+V1.5S
+V1.5S
Layout note:C151 need be placed within
100 mils of pinAD17 of ICH7 on the
bottomside or 140mils on the top
R176
10
3
C187
1uF/10V,X5R
D
+V5AUX
1
C156
C156
0.1uF/16V,X7R
C172
C172
10uF/6.3V,X5R
D5
BAT54C
C158
0.1uF/16V,X7R
C173
0.01uF/25V,X7R
0.01uF/25V,X7R
C182
0.1uF/16V,X7R
C185
0.1uF/16V,X7R
R175
100
C186
0.1uF/16V,X7R
C160
C160
0.1uF/16V,X7R
VccSus1_05[1]
Vcc1_5_A[24]
Vcc1_5_A[25]
Vcc1_5_A[21]
Vcc1_5_A[22]
Vcc1_5_A[23]
Vcc1_5_A[19]
Vcc1_5_A[20]
VccSus3_3[7]
VccSus3_3[8]
VccSus3_3[9]
VccSus3_3[10]
VccSus3_3[11]
VccSus3_3[12]
VccSus3_3[13]
VccSus3_3[14]
VccSus3_3[15]
VccSus3_3[16]
VccSus3_3[17]
VccSus3_3[18]
VccSus3_3[2]
VccSus3_3[3]
VccSus3_3[4]
VccSus3_3[5]
VccSus3_3[6]
VccSus3_3[1]
VccRTC
Vcc3_3[12]
Vcc3_3[13]
Vcc3_3[14]
Vcc3_3[15]
Vcc3_3[16]
Vcc3_3[17]
Vcc3_3[18]
Vcc3_3[19]
Vcc3_3[20]
Vcc3_3[21]
Vcc3_3[3]
Vcc3_3[4]
Vcc3_3[5]
Vcc3_3[6]
Vcc3_3[7]
Vcc3_3[8]
Vcc3_3[9]
Vcc3_3[10]
Vcc3_3[11]
V_CPU_IO[1]
V_CPU_IO[2]
V_CPU_IO[3]
VccSus3_3/VccSusHDA
Vcc3_3/VccHDA
VccSus3_3/VccLAN3_3[1]
VccSus3_3/VccLAN3_3[2]
VccSus3_3/VccLAN3_3[3]
VccSus3_3/VccLAN3_3[4]
Vcc1_05[1]
Vcc1_05[2]
Vcc1_05[3]
Vcc1_05[4]
Vcc1_05[5]
Vcc1_05[6]
Vcc1_05[7]
Vcc1_05[8]
Vcc1_05[9]
Vcc1_05[10]
Vcc1_05[11]
Vcc1_05[12]
Vcc1_05[13]
Vcc1_05[14]
Vcc1_05[15]
Vcc1_05[16]
Vcc1_05[17]
Vcc1_05[18]
Vcc1_05[19]
VCC PAUX Vcc1_05[20]
NH82801GBM
0.86A
+V3.3AUX
VCC3_3 Total 0.33A
+V3.3S
14mA
+V3.3S
C152
0.1uF/16V,X7R
0.1uF/16V,X7R
6uA
+V3.3S
A1
H6
H7
J6
J7
3
+V1.5S
TP18ns
TP19ns
K7
C28 TP_ICHVCCSUS2
G20 TP_ICHVCCSUS3
AB8
AC8
T7
F17
G17
AB17
AC17
TP17ns
+V1.5S
TP_ICHVCCSUS1
K3
K4
K5
K6
L1
L2
L3
L6
L7
M6
M7
N7
+V3.3AUX
P7
A24
C24
D19
D22
G19
VCCSus3_3 Total 52mA
W5
A5
B13
B16
B7
C10
D15
F9
G11
G12
G16
AA7
AB12
AB20
AC16
AD13
AD18
AG12
AG15
AG19
AE23
AE26
AH26
R7
U6
V5
V1
W2
W7
L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18
Placed within 100 mils of ICH
on the bottom or 140 mils on
the top
VccSus1_05[2]
VccSus1_05[3]
VccSus1_05/VccLAN1_05[1]
VccSus1_05/VccLAN1_05[2]Vcc1_5_A[26]
Vcc1_5_A[27]
Vcc1_5_A[28]
Vcc1_5_A[29]
Vcc1_5_A[30]
VccUSBPLL
VccSus3_3[19]
Vcc1_5_A[10]
Vcc1_5_A[11]
Vcc1_5_A[12]
Vcc1_5_A[13]
Vcc1_5_A[14]
Vcc1_5_A[15]
Vcc1_5_A[16]
Vcc1_5_A[17]
Vcc1_5_A[18]
Vcc3_3[2]
VccSATAPLL
Vcc1_5_A[1]
Vcc1_5_A[2]
Vcc1_5_A[3]
Vcc1_5_A[4]
Vcc1_5_A[5]
Vcc1_5_A[6]
Vcc1_5_A[7]
Vcc1_5_A[8]
Vcc1_5_A[9]
VccDMIPLL
Vcc3_3[1]
Vcc1_5_B[1]
Vcc1_5_B[2]
Vcc1_5_B[3]
Vcc1_5_B[4]
Vcc1_5_B[5]
Vcc1_5_B[6]
Vcc1_5_B[7]
Vcc1_5_B[8]
Vcc1_5_B[9]
Vcc1_5_B[10]
Vcc1_5_B[11]
Vcc1_5_B[12]
Vcc1_5_B[13]
Vcc1_5_B[14]
Vcc1_5_B[15]
Vcc1_5_B[16]
Vcc1_5_B[17]
Vcc1_5_B[18]
Vcc1_5_B[19]
Vcc1_5_B[20]
Vcc1_5_B[21]
Vcc1_5_B[22]
Vcc1_5_B[23]
Vcc1_5_B[24]
Vcc1_5_B[25]
Vcc1_5_B[26]
Vcc1_5_B[27]
Vcc1_5_B[28]
Vcc1_5_B[29]
Vcc1_5_B[30]
Vcc1_5_B[31]
Vcc1_5_B[32]
Vcc1_5_B[33]
Vcc1_5_B[34]
Vcc1_5_B[35]
Vcc1_5_B[36]
Vcc1_5_B[37]
Vcc1_5_B[38]
Vcc1_5_B[39]
Vcc1_5_B[40]
Vcc1_5_B[41]
Vcc1_5_B[42]
Vcc1_5_B[43]
Vcc1_5_B[44]
Vcc1_5_B[45]
Vcc1_5_B[46]
Vcc1_5_B[47]
Vcc1_5_B[48]
Vcc1_5_B[49]
Vcc1_5_B[50]
Vcc1_5_B[51]
Vcc1_5_B[52]
Vcc1_5_B[53]
V5REF_Sus
V5REF[2]
V5REF[1]
U5F
3
C161
0.1uF/16V,X7R
0.1uF/16V,X7R
+V3.3S
C188
0.01uF/25V,X7R
C174
0.1uF/16V,X7R
CORE
CORE
IDE
IDE
PCI
PCI
C159
0.1uF/16V,X7R
C190
0.1uF/16V,X7R
C168
0.1uF/16V,X7R
C175
0.1uF/16V,X7R
C183
0.1uF/16V,X7R
+V1.5S
+V3.3S
CT13
100uF/10V,TAN
+V1.05S
+V1.5S
+V3.3A_RTC
Placed within 100 mils of ICH
on the bottom or 140 mils on
the top
C165
C165
0.1uF/16V,X7R
+V5S
USB
USB CORE
C162
0.1uF/16V,X7R
C153
0.1uF/16V,X7R
C163
0.1uF/16V,X7R
C170
0.1uF/16V,X7R
C177
0.1uF/16V,X7R
C164
0.1uF/16V,X7R
C178
0.1uF/16V,X7R
0.1uF/16V,X7R
C180
0.1uF/16V,X7R
0.1uF/16V,X7R
+V3.3AUX
C179
0.1uF/16V,X7R
+V1.5S
C181
0.1uF/16V,X7R
C169
0.1uF/16V,X7R
0.1uF/16V,X7R
C176
0.1uF/16V,X7R
0.1uF/16V,X7R
C184
C184
0.1uF/16V,X7R
C154
1uF/10V,X5R
C171
0.1uF/16V,X7R
2
2
+V1.05S
C166
0.1uF/16V,X7R
0.1uF/16V,X7R
4
C167
4.7uF/10V,X5R
5
ATX
C191
0.1uF/16V,X7R
0.1uF/16V,X7R
ARX
C189
0.1uF/16V,X7R
VCCA3GP
[3,4,5,6,8,9,12,17,26,33,35,38]
[18,19,22,23,24,28,34,35,36,38]
[18,23,26,31,32,33,34,35,38]
Date:
Q10
ICH7M Power
1
Thursday, February 26, 2009
Project Name
CZC Technology
[4,7,8,9,13,20,33,35,38]
Sheet
15
of
Rev
B
48
[5,7,8,9,11,12,13,14,17,18,20,22,23,25,26,27,28,34,35,36,38]
[3,4,5,6,8,9,12,17,26,33,35,38]
Size
Custom
Title
+V1.5S
+V1.05S
+V3.3S
+V3.3AUX [5,12,13,14,18,20,25,26,27,29,30,31,34,38]
+V5S
+V5AUX
+V3.3A_RTC [12]
+V1.05S
Placed within 100 mils of ICH
on the bottom or 140 mils on
the top
+V1.5S
+V1.05S
+V3.3S
+V3.3AUX
+V5S
+V5AUX
+V3.3A_RTC
+V1.05S
1
A
B
C
D
A
B
C
D
5
5
A4
A23
B1
B8
B11
B14
B17
B20
B26
B28
C2
C6
C27
D10
D13
D18
D21
D24
E1
E2
E4
E8
E15
F3
F4
F5
F12
F27
F28
G1
G2
G5
G6
G9
G14
G18
G21
G24
G25
G26
H3
H4
H5
H24
H27
H28
J1
J2
J5
J24
J25
J26
K24
K27
K28
L13
L15
L24
L25
L26
M3
M4
M5
M12
M13
M14
M15
M16
M17
M24
M27
M28
N1
N2
N5
N6
N11
N12
N13
N14
N15
N16
N17
N18
N24
N25
N26
P3
P4
P12
P13
P14
P15
P16
P17
P24
P27
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
NH82801GBM
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
U5E
P28
R1
R11
R12
R13
R14
R15
R16
R17
R18
T6
T12
T13
T14
T15
T16
T17
U4
U12
U13
U14
U15
U16
U17
U24
U25
U26
V2
V13
V15
V24
V27
V28
W6
W24
W25
W26
Y3
Y24
Y27
Y28
AA1
AA24
AA25
AA26
AB4
AB6
AB11
AB14
AB16
AB19
AB21
AB24
AB27
AB28
AC2
AC5
AC9
AC11
AD1
AD3
AD4
AD7
AD8
AD11
AD15
AD19
AD23
AE2
AE4
AE8
AE11
AE13
AE18
AE21
AE24
AE25
AF2
AF4
AF8
AF11
AF27
AF28
AG1
AG3
AG7
AG11
AG14
AG17
AG20
AG25
AH1
AH3
AH7
AH12
AH23
AH27
4
4
3
3
2
2
Date:
Size
A3
Title
Q10
ICH7M GND
1
Thursday, February 26, 2009
Project Name
CZC Technology
1
Sheet
16
of
Rev
B
48
A
B
C
D
A
B
C
D
400
0
0
1
1
0
0
1
1
0
0
0
1
1
1
1
0
1
5
333
0
0
0
Reserved
266
200
166
133
100
1
R190
4.7K
Host Clock
frequency MHz
0
R189
4.7K
ns
PCIF5_ITP_EN
PCI2_TME
1
1
X2S60X35
Y2
14.318MHz,18pf
1
2
VerB: Modify
R191
4.7K
PCI4_SRC5_EN
4
[14] CLK_REF_ICH
[14] CLK_USB48
33
33
33
33
R195
R178
R182
C206
0.1uF/16V,X7R
C200
0.1uF/16V,X7R
R181
C205
0.1uF/16V,X7R
C193
0.1uF/16V,X7R
PCI2_TME
C207
0.1uF/16V,X7R
C201
0.1uF/16V,X7R
3
3
3
1
12
20
26
36
45
49
39
55
2
9
16
61
8
11
15
19
52
23
29
42
58
62
33
R186
FSC
4.7K
R185
10
CLK_BSEL2
FSA
57
4.7K
33
59
XTAL_OUT
R184
R183
60
XTAL_IN
7
6
PCI4_SRC5_EN
PCIF5_ITP_EN
5
PCI3
4
CLK_BSEL0
CLK_BSEL1
C198
0.1uF/16V,X7R
C192
0.1uF/16V,X7R
4
[13] CLK_PCIF_ICH
[38] PCICLK_LPC
[27] PCICLK_TCM
C212
27pF/50V,NPO
VerB: Add
C199
0.1uF/16V,X7R
C195
0.1uF/16V,X7R
[26] PCICLK_KBC
C203
0.1uF/16V,X7R
C194
10uF/6.3V,X5R
R187
4.7K
FSA
BSEL0
FSA
BSEL1
C196
0.1uF/16V,X7R
C197
10uF/6.3V,X5R
R188
4.7K
ns
+V3.3S_CLK
C315
10uF/6.3V,X5R
+V3.3S_CLK
C211
27pF/50V,NPO
FB40
100ohm/100MHz,2A
FSC
BSEL2
+V3.3S
5
SDA
SCLK
NC
R201
0
R192
1K
ns
+V1.05S
56
13
14
17
18
21
22
24
25
27
28
41
40
44
43
30
31
33
32
35
34
47
46
51
50
54
53
38
37
63
64
48
R202
0
R193
1K
ns
CKPWRGD/PWRDWN#
SRC0/DOT96
SRC0#/DOT96#
SRC1/SE1
SRC1#/SE2
SRC2/SATA
SRC#2/SATA#
SRC3/CR#_C
SRC3#/CR#_D
SRC4
SRC4#
SRC6
SRC6#
SRC7/CR#_F
SRC7#/CR#_E
SRC9
SRC9#
SRC11/CR#_H
SRC11#/CR#_G
SRC10#
SRC10
SRC8/ITP
SRC8#/ITP#
CPU1
CPU1#
CPU0
CPU0#
PCI_STOP#SRC5
CPU_STOP#SRC5#
VerB: Modify Net
VSS_PCI
VSS_48
VSS_IO
VSS_PLL3
VSS_CPU
VSS_SRC1
VSS_SRC2
VSS_SRC3
VSS_REF
REF/FSC/TESTSEL
FSB/TESTMODE
USB/FSA
XTAL_OUT
XTAL_IN
PCIF/ITP_EN
PCI4/SRC5_EN
PCI3
PCI2/TME
PCI1/CR#B
PCI0/CR#A
VDD_IO
VDD_PLL3_IO
VDD_SRC_IO_1
VDD_SRC_IO_2
VDD_SRC_IO_3
VDD_CPU_IO
VDD_SRC
VDD_CPU
VDD_PCI
VDD_48
VDD_PLL3
VDD_REF
U7
ICS9LPRS365xGLFT
TSSOP64_P5_6P1
DREFCLK
DREFCLK#
2
CLK_BSEL2
CLK_BSEL1
CLK_BSEL0
R214
4.7K
ns
R200
R198
R196
R381
[7]
[7]
DREFSSCLK [7]
DREFSSCLK# [7]
0
CLK_PCIE_SATA [12]
CLK_PCIE_SATA# [12]
+V3.3S_CLK
R203
1K
ns
R414
CLK_PCIE_ICH [13]
CLK_PCIE_ICH# [13]
CLK_SRC8-EN#_R
1K
1K
1K
CLK_PCIE_MINICARD [20]
CLK_PCIE_MINICARD# [20]
R179
R180
CLK_PCIE_LAN# [25]
CLK_PCIE_LAN [25]
CLK_PCIE_3GPLL [7]
CLK_PCIE_3GPLL# [7]
CLK_MCH_BCLK [6]
CLK_MCH_BCLK# [6]
CLK_CPU_BCLK [3]
CLK_CPU_BCLK# [3]
PM_STPPCI# [14]
PM_STPCPU# [14,38]
1
VR_PWRGD_CLKEN
Date:
Size
A3
Title
Q10
CK505
1
Thursday, February 26, 2009
Project Name
CZC Technology
MCH_BSEL2 [7]
MCH_BSEL1 [7]
[14]
MCH_CLKREQ# [7]
LAN_CLKREQ# [25]
MINICARD_CLKREQ#
[20]
Sheet
17
[5,7,8,9,11,12,13,14,15,18,20,22,23,25,26,27,28,34,35,36,38]
[3,4,5,6,8,9,12,15,26,33,35,38]
MCH_BSEL0 [7]
+V1.05S
+V3.3S
R215
100K
470
470
470
ICH7M_SMB_DATA [11,14,20]
CLK_SRC10-EN#_R
CLK_SRC9-EN#_R
R194
56
+V1.05S
+V3.3S
ICH7M_SMB_CLK [11,14,20]
2
of
Rev
B
48
A
B
C
D
A
B
C
[7]
TTL_ADJ
2
3
*
0
R227
12.1 inch CCFL Panel
6
7
5
BOE HT101WSA-100
*
BOE HT101WSB-100 [1024x600]
AUO B101AW01 V3
CPT CLAA101NA0ACN V0.0
CPT CLAA101NA0ACG V0.0
HSD101PFW1-A00
L_BKLTEN
7-21V
7-21V
5V
6-21V
6-21V
5-21V
VLED
ns
Q9
AO3407
3
1N4148WS
4
10
9
8
Need
12
Need
Need
11
Need
Need
Need
1N4148WS
D14
D15
1N4148WS
D13
C243
0.1uF/16V,X7R
LA_DATAP2
LA_DATAN2
LA_DATAP1
LA_DATAN1
LA_DATAP0
LA_DATAN0
[7]
[7]
[7]
[7]
[7]
[7]
FB17
120ohm/100MHz,1A
Hannstar HSD100IFW1-A**
CPT CLAA102NA0ACW
5V
5V
3
VLED
1000pF/50V,X7R
C232
BKLT_ON
LED_EN(3V)
1
R225
100K
No
No
R222
Q12
2N7002K
SOT23
R221
1M
+V5S
LCD0+
LCD0-
LCD1+
LCD1-
LCD2+
LCD2-
LED_EN(3V)
PN:620904000002???
ACES: 88742-4001
VerB: Modify PN
LA_CLKN
LA_CLKP
[7]
[7]
LCDCLK1LCDCLK1+
10UF/6.3V,X5R
C0805
C237
3
[7] L_DDC_CLK
[7] L_DDC_DATA
L20
100ohm/100MHz,2A
10.2 1024x600 Panel Type
LIGHT_ON
R224
4.7K
+V3.3S
+V5S
10UF/6.3V,X5R
C0805
C226
LCDVDD
0.1uF/16V,X7R
C225
1000pF/50V,X7R
C228
BKLT_PWM
LED_EN(3V)
R223
100K
500mA
L21
100ohm/100MHz,2A
LCDVDD rising
time is 470uS
2
High : Enable
Low : Disable
R220
100K
ns
0
0
0
R226
10.1 1024x576 Panel Type
[26] HW_OFF_BKLT#
5
4
ns
R713
8.2K [7]
+V3.3AUX
*
1
*
R418
R219
100K
C224
0.01uF/25V,X7R
Q10
2N7002K
SOT23
3.3v level
1
[14,26] PM_SUS_STAT#
[26,27]
*
[7]
R218
100K
LIDSW#
L_BKLTCTL
[26]
L_VDDEN
R217
R216
1M
+V3.3S
3
2
1
4
3
2
100K
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
ACES 88242-40xx
ACES 88242-40xx
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
C229
0.01uF/25V,X7R
41
D
5
2
2
2
3
0
R728
Q11
AO3407
+VDC
+V5AUX
+V5S
+V3.3S
[15,23,26,31,32,33,34,35,38]
C231
+V3.3AUX
L8
100ohm/100MHz,2A
ns
L6
100ohm/100MHz,2A
500mA
Date:
Size
A3
Title
Q10
1
Thursday, February 26, 2009
Project Name
LVDS Panel
CZC Technology
10UF/6.3V,X5R
C0805
C250
LEDVDD
C227
10UF/6.3V,X5R
C0805
0.1uF/25V,X7R
C230
0.1uF/25V,X7R
C295
USBCAM_VCC
+V5AUX
10uF/25V,X5R
C1210
0.1uF/25V,X7R
Sheet
18
of
Rev
B
6-21V
+V3.3AUX
L19
100ohm/100MHz,2A
C288
[29,31,32,33,36,38]
+VDC
[5,7,8,9,11,12,13,14,15,17,20,22,23,25,26,27,28,34,35,36,38]
[15,19,22,23,24,28,34,35,36,38]
L22
100ohm/100MHz,2A
+V3.3S
ns
LEDVDD
LCDVDD
USB_PN6 [13]
USB_PP6 [13]
BKLT_PWM
BKLT_ON
1
+V3.3AUX [5,12,13,14,15,20,25,26,27,29,30,31,34,38]
LCDCON1
Panel CON. 2x20Pin
LCDS2X20H39_1P0R
0
+VDC
+V5AUX
+V5S
+V3.3S
+V3.3AUX
R727
1
48
A
B
C
D
A
B
C
D
FB19
C238
4.7uF/10V,X5R
100ohm/100MHz,2A
+V5S
FB29
5
C372
4.7uF/10V,X5R
100ohm/100MHz,2A
C373
0.1uF/16V,X7R
V5S_ODD
Average 1A,Peak 1.5A
C239
0.1uF/16V,X7R
V5S_HDD
Average 1A,Peak 1.5A
SATA ODD
+V5S
SATA HDD
5
C371
0.1uF/16V,X7R
C240
0.1uF/16V,X7R
4
C420
4.7uF/10V,X5R
C415
4.7uF/10V,X5R
4
[12] SATA_TXN1
[12] SATA_TXP1
[12] SATA_RXP1
[12] SATA_RXN1
[12] SATA_TXN0
[12] SATA_TXP0
[12] SATA_RXP0
[12] SATA_RXN0
+V3.3AUX
VIN
ECVCC
+V5S
+V3.3S
[26,28]
[15,18,22,23,24,28,34,35,36,38]
[5,7,8,9,11,12,13,14,15,17,18,20,22,23,25,26,27,28,34,35,36,38]
VIN
C370 3900pF/50V,X7R
C369 3900pF/50V,X7R
C368 3900pF/50V,X7R
C352 3900pF/50V,X7R
3
SATA_TXN1
SATA_TXP1
SATA_RXP1_C
SATA_RXN1_C#
V5S_ODD
SATA_TXN0
SATA_TXP0
SATA_RXP0_C
SATA_RXN0_C#
V5S_HDD
10
9
8
7
6
5
4
3
2
1
10
9
8
7
6
5
4
3
2
1
11
12
11
12
10
9
8
7
6
5
4
3
2
1
11
12
11
12
ODDCN1
FPC10 1.0mm
FPC10_1p0rt
10
9
8
7
6
5
4
3
2
1
HDDCN1
FPC10 1.0mm
FPC10_1p0rt
+V3.3AUX [5,12,13,14,15,18,20,25,26,27,29,30,31,34,38]
[27,29,37,38]
ECVCC
+V5S
+V3.3S
3
2
2
S2
S3
P13
P14
P15
P7
P8
P9
P11
VCC12_0
VCC12_1
VCC12_2
VCC5_0
VCC5_1
VCC5_2
RESVE
VCC3_0
VCC3_1
VCC3_2
RX#
RX
TX
TX#
NC0
NC1
GND6
GND7
GND3
GND4
GND5
GND0
GND1
GND2
1
2
P10
P12
P4
P5
P6
S1
S4
S7
GND_SATA
10
9
8
7
6
5
4
3
2
1
10
9
8
7
6
5
4
3
2
1
11
12
GND_SATA
11
12
Date:
Size
A3
Title
FFC Cable
CN2
Q10
SATA\MISC
1
Thursday, February 26, 2009
Project Name
Sheet
GND_SATA
CZC Technology
CN1.Pin1 Connector to CN2.Pin1
CN1
SATACBL1
SATA 10P 1mmPitch FFC cable XXXmmL
SATA_TXN0_Brd
SATA_TXP0_Brd
SATA_RXP0_Brd
SATA_RXN0_Brd
V5S_SATAHDD
HDDCN2
FPC10 1.0mm
FPC10_1p0rt
Alltop C16614-122A4-Y
V5S_SATAHDD
SATA_RXN0_Brd
SATA_RXP0_Brd
P1
P2
P3
S5
S6
SATA_TXP0_Brd
SATA_TXN0_Brd
SATA1
SATACN
SATAS22
620402220002
SATA Board
1
19
of
Rev
B
48
A
B
C
D
A
B
C
D
+V3.3S
+V3.3S
+V3.3Aux
VerB:Add
C247
4.7uF/10V,X5R
+V1.5S
C245
4.7uF/10V,X5R
FB46
+V3.3S_WLAN
100ohm/100MHz,2A
FB45
100ohm/100MHz,2A
ns
[21] USB_PN7_3G
[21] USB_PP7_3G
C249
0.1uF/16V,X7R
C244
0.1uF/16V,X7R
0.1uF/16V,X7R
0.1uF/16V,X7R
VerB: Add
SIM_VCC
SIM_DAT0
SIM_CLK
SIM_RESET
+V3.3S_WLAN
C241
C242
36
38
5
C294
4.7uF/10V,X5R
+V1.5S
C251
0.1uF/16V,X7R
VerB:Add
C287
0.1uF/16V,X7R
4
SIM_VCC
SIM_DAT0
SIM_CLK
SIM_RESET
+V3.3S_3G
8
10
12
14
16
17
19
37
39
41
43
45
47
49
51
23
25
VerB:Add
C377
0.1uF/16V,X7R
31
33
FB41
+V3.3S_3G
100ohm/100MHz,2A
C374
10uF/6.3V,X5R
UIM_PWR
UIM_DATA
UIM_CLK
UIM_RESET
UIM_VPP
RESERVED0/UIM_C8
RESERVED1/UIM_C4
GND15
+3.3VAux2
+3.3VAux3
GND16
RESERVED0
RESERVED1
RESERVED2
RESERVED3
PERN0
PERP0
PETN0
PETP0
REFCLKREFCLK+
USB_DUSB_D+
+V3.3S_WLAN
+V1.5S
+V1.5S
UIM_PWR
UIM_DATA
UIM_CLK
UIM_RESET
UIM_VPP
3
3
V1.2
W_DISABLE#
COEX2
COEX1
SMB_DATA
SMB_CLK
PERST#
WAKE#
CLKREQ#
LED_WPAN#
LED_WLAN#
LED_WWAN#
VerB:Add
W_DISABLE#
COEX2
COEX1
SMB_DATA
SMB_CLK
PERST#
WAKE#
CLKREQ#
LED_WPAN#
LED_WLAN#
LED_WWAN#
RESERVED0/UIM_C8
RESERVED1/UIM_C4
GND15
+3.3VAux2
+3.3VAux3
PCIE mini Card
GND16
RESERVED0 Support Half Size Card
RESERVED1
RESERVED2
RESERVED3
PERN0
PERP0
PETN0
PETP0
REFCLKREFCLK+
USB_DUSB_D+
+V3.3S_3G
3GPCIE1
PCIE MINI CARD 4mm
MINIPCIEH40_SL
8
10
12
14
16
17
19
37
39
41
43
45
47
49
51
23
25
31
33
11
13
C376
0.1uF/16V,X7R
C248
0.1uF/16V,X7R
C246
0.1uF/16V,X7R
[13] PCIE_RXN2_SLOT
[13] PCIE_RXP2_SLOT
[13] PCIE_TXN2_SLOT
[13] PCIE_TXP2_SLOT
11
13
36
38
PCIE1
PCIE MINI CARD 4mm
MINIPCIEH40
FB44
100ohm/100MHz,2A
ns
+V3.3Aux
USB_PN3
USB_PP3
[17] CLK_PCIE_MINICARD#
[17] CLK_PCIE_MINICARD
[13]
[13]
MINIPCIE SLOT
2
52
3.3VAux0
+3.3VAUX
GND0
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
GND11
GND12
GND13
9
15
21
27
29
35
4
18
26
34
40
50
53
54
4
PCIE mini Card V1.2
PCIE mini Card V1.2
24
+3.3VAUX1
GND14
55
5
2
52
3.3VAux0
+3.3VAUX
24
+3.3VAUX1
48
28
6
+1.5V0
+1.5V1
1.5V
GND0
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
GND11
GND12
GND13
9
15
21
27
29
35
4
18
26
34
40
50
53
54
GND14
55
48
28
6
+1.5V0
+1.5V1
1.5V
GND17
57
20
5
3
32
30
22
1
7
46
44
42
20
5
3
32
30
22
1
7
46
44
42
0
0
VerB: Add
0
0
R294
R293 ns
Half Size Card Stuff
[15,18,19,22,23,24,28,34,35,36,38]
PLTRST# [7,13,14,25,26,38]
PCIE_WAKE# [25,26]
MINICARD_CLKREQ# [17]
3GPCIE_H2
Match 4mm Boss
ns
3GPCIE_H1
Match 4mm Boss
[26]
2
PLTRST# [7,13,14,25,26,38]
PCIE_WAKE# [25,26]
WIRELESS_LED# [27]
HW_RATIO_OFF_WLAN#
[26]
[4,7,8,9,13,15,33,35,38]
WIRELESS_LED# [27]
+V1.5S
Date:
Size
A3
Title
SIM_RESET
SIM_CLK
SIM_DAT0
SIM_VCC
SIM_GND0
SIM_GND1
SIM_GND2
SIM_GND3
SIM_GND4
SIM_RST
SIM_CLK
SIM_IO
SIM_DAT0
SIM_MCMD
SIM_CDDETECT
SIM_VPP
SIM_VCC
SIMreader
SIMreader
sim9h15
Q10
Mini PCIE connect
1
Thursday, February 26, 2009
Project Name
Sheet
Proconn
SPPN08-A0-5000
1.5mm
1
CZC Technology
2
10
11
12
13
3
5
6
7
8
9
4
1
[5,7,8,9,11,12,13,14,15,17,18,22,23,25,26,27,28,34,35,36,38]
[18,29,31,32,33,36,38]
+V3.3AUX [5,12,13,14,15,18,25,26,27,29,30,31,34,38]
+V5S
+V3.3S
+VDC
2
ICH7M_SMB_DATA [11,14,17]
ICH7M_SMB_CLK [11,14,17]
HW_RATIO_OFF_3G#
VerB:Add
0
0
R295
R292
VerB:Modify
MiniPCIE_H1
Match 4mm Boss
R242
R270
Full Size Card Stuff
TP49
TP23
+V1.5S
+V3.3AUX
+V5S
+V3.3S
+VDC
20
of
Rev
B
48
A
B
C
D
A
B
C
D
5
5
[13]
[13]
4
[20] USB_PP7_3G
[20] USB_PN7_3G
USB_PP7
USB_PN7
4
R655
R639
L4S2012
0
0
ns
CHK8
90ohm@100MHz,0.5A
1
2
4
3
3
3
2
Date:
Size
A4
Title
Q10
Thursday, February 26, 2009
Project Name
BLOCK DIAGRAM
1
1
Sheet
CZC Technology
VerB: Del Express Card circle
2
21
of
Rev
B
48
A
B
C
D
A
B
C
D
BTL_BEEP
R259
10K
51K
R251
R252
4.7K
15K
R258
10K
5
1
1
LOUT+
ROUT-
ROUT+
VDD
PVDD1
PVDD2
SHDWN# GND1
GND2
GAIN0
GND3
GND4
GAIN1
GND5
LINNC
BYPASS LOUT-
LIN+
RIN+
RIN-
15.6dB
21.6dB
Av(inv)
6dB
10dB
3
GAIN1
GAIN0 GAIN1
0
0
0
1
1
0
2
19
5
12
10
9
7
17
R268
15K
U11
TPA6017A2
Tssop20_p65_4p4g
GND_AUD
GAIN0
SHUTDOWN#
C271 0.47uF/16V,X7R
C0603
C272 0.47uF/16V,X7R
C0603
C273 1uF/10V,X5R
R263
15K
C0402
R261
R269
15K
R267
2.2K
R266
16
6
15
1
11
13
20
21
8
4
14
18
1K
1K
LINEOUT_R_MB
LINEOUT_L_MB
4
D16
1N4148WS
SOD323
ns
SHUTDOWN#
1uF/10V,X5R
C0402
ns
C259
R245
10M
ns
VCC5CDC
24
23
22
21
20
18
17
16
15
14
13
12
8
5
10
6
11
3
FB23
LINE1-R
LINE1-L
MIC1-R
MIC1-L
CD-R
CD-L
MIC2-R
MIC2-L
LINE2-R
LINE2-L
Sense A
PC-BEEP
SDIN
SDOUT
SYNC
BITCLK
REST#
GPIO1
GPIO0
+V5S
C254
10UF/6.3V,X5R
C0805
220ohm/100MHz,1.5A
C277 FB0603
4.7uF/10V,X5R
VCC5CDC
C276
0.1uF/16V,X7R
C268 1uF/10V,X5R
C0402
C269 1uF/10V,X5R
C0402
C264 10UF/6.3V,X5R
C0805
C265 10UF/6.3V,X5R
C0805
33
A_GPIO1
2
C253
0.1uF/16V,X7R
A_GPIO0
JACK_DET_A
PC_Beep
R254
ns
ns
C275
0.1uF/16V,X7R
-INTSPL
+INTSPL
-INTSPR
+INTSPR
MIC1_R
MIC1_L
TP32
TP31
C252
0.1uF/16V,X7R
20K,1%
[12] HDA_SDATAIN0
[12] HDA_SDATAOUT
[12] HDA_SYNC
[12] HDA_BITCLK
MIC1_JD_MB R255
Mic1_R_MB
R264
MIC1_VREFO_L
2.2K
C263
100pF/50V,NPO
[12] HDA_RST#
PC_Beep
Mic1_L_MB
R265
MIC1_VREFO_R
R257
10K
ns
GAIN0
GAIN1
R253
4.7K
C260 1uF/10V,X5R
C0402
C262 1uF/10V,X5R
C0402
All of JD resistors should be
placed as close as possible to
the sense pin of codec.
51K
R250
C270 1uF/10V,X5R
C0402
VCC5CDC
AMP_OUT_L
AMP_OUT_R
SPKR
[26]
[14]
FB0603
U10
ALC662
LQFP48_P5
CD-GND
3
GND_AUD
19
FB20
220ohm/100MHz,1.5A
AGND1
AGND2
26
42
+V3.3S
25
38
AVDD1
AVDD2
1
9
VDD1
VDD2
GND1
GND2
4
7
3
C256
1
2
1
2
41
40
39
48
47
46
45
44
43
34
33
32
31
30
28
27
+INTSPR
-INTSPR
R246
0
0
R249
10K
1
R260
R256
2
Q13
2N7002K
SOT23
SHUTDOWN#
R244
10K
VCC5CDC
C258
HP_JD_MB
Date:
Size
A3
Title
GND_AUD
HP_JD_MB
LINEOUT_R_MB
LINEOUT_L_MB
MIC1_JD_MB
Mic1_R_MB
Mic1_L_MB
0.1uF/16V,X7R
GND_AUD
R247
100K
ACES
85204-02X01
GND_AUD
20K,1%
AMP_SHDW
JACK_DET_B
MIC1_VREFO_R
MIC1_VREFO_L
C261 10UF/6.3V,X5R
C0805
AMP_OUT_R
RSPK1
W-B-2P-R
HWS2_1P25R
1
2
AMP_SHDW R248 ns
A_GPIO0
AMP_OUT_L
+V5S
39.2K,1%
C257
220ohm/100MHz,1.5A
10UF/6.3V,X5R
FB0603
C0805
Cross moat place
FB21
R274 ns
0
GND_AUD [23]
HP_JD_MB [23]
LINEOUT_R_MB [23]
LINEOUT_L_MB [23]
MIC1_JD_MB [23]
Mic1_R_MB [23]
Mic1_L_MB [23]
Q10
ALC662 Audio codec
1
Thursday, February 26, 2009
Project Name
CZC Technology
IN
IN
IN
IN
IN
IN
IN
Sheet
GND_AUD
C284 0.1uF/16V,X7R
ns
1
VerB: Del MIC circle
[15,18,19,23,24,28,34,35,36,38]
+V5S
36
37
29
2
[5,7,8,9,11,12,13,14,15,17,18,20,23,25,26,27,28,34,35,36,38]
+V3.3S
35
LSPK1
W-B-2P-R
HWS2_1P25R
+INTSPL
1
-INTSPL
2
SURR-OUT-R
JDREF
SURR-OUT-L
SPDIFO
SPDIFI/EAPD
NC4
NC3
LFE-OUT
CEN-OUT
Sense B
NC5
MIC1-VREFO-R
LINE2-VREFO
MIC2-VREFO
MIC1-VREFO-L
VREF
NC1
NC2
FRONT-OUT-R
FRONT-OUT-L
GND_AUD
0.1uF/16V,X7R
C255
VCC5CODEC
+V5S
+V3.3S
0.1uF/16V,X7R
4
3
3
4
3
3
4
4
4
5
3
2
22
of
Rev
B
48
A
B
C
D
A
B
C
D
[13]
[13]
USB_PN0
USB_PP0
5
+V5AUX
[25]
[25]
[25]
[25]
[13]
[13]
[13]
[13]
R290
R289
LAN_TXD+ BI
BI
LAN_TXDLAN_RXIN+ BI
LAN_RXIN- BI
[22]
Mic1_L_MB
[22]
Mic1_R_MB
[22] MIC1_JD_MB
[22]
GND_AUD
USB_PN2
USB_PP2
USB_OC1#
USB_OC2#
+V5S +V5AUX
4
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
HOLE0
HOLE1
HOLE2
HOLE3
5
6
7
8
+V5AUX
3
IN
IN
IN
IN
CRT_RED [7]
CRT_GREEN [7]
CRT_BLUE [7]
CRT_HSYNC [7]
CRT_VSYNC [7]
CRT_DDC_CLK [7]
CRT_DDC_DATA [7]
LINEOUT_L_MB [22]
LINEOUT_R_MB [22]
HP_JD_MB [22]
GND_AUD [22]
USB_PN1 [13]
USB_PP1 [13]
PN:620903023204
ACES: 88242-3001
0
ns
[13]
+V5AUX
+V5S
+V3.3S
[13]
[13]
ALLTOP: C10753-104A3
4P USB
USB4H35IN
GND
-DATA1
+DATA1
VCC1
VerB: Modify PN
IOCN1
Panel CON. 2x15Pin
LCDS2X15H39_1P0R
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
R291
4
2
3
1
USB1
3
USB port (620700410003)
USB_OC3#
C291
1000pF/50V,X7R
USB_GND3
R286
560K
D22
EGA10603V05A1-B
470K
USB_GND3
2
1
LAN_TXD+
LAN_TXDLAN_RXIN+
LAN_RXIN-
2
1
IN
IN
IN
IN
D21
EGA10603V05A1-B
0
ns
0
ns
L9
R285
C292100ohm/100MHz,2A
0.1uF/16V,X7R
USB_VCC3
CHK4
90ohm@100MHz,0.5A
L4S2012
4
3
1
2
F4
1.6A
P
4
CT4
CT4
100uF/10V,TAN
5
C293
C293
680pF/25V,X7R
680pF/25V,X7R
31
32
+V5AUX
+V5S
+V3.3S
2
4
Date:
1
2
3
4
1
2
3
4
6
5
Q10
Thursday, February 26, 2009
Project Name
1
Sheet
USB Port & Fan control
6
5
FB4
100ohm/100MHz,2A
CZC Technology
FB5
100ohm/100MHz,2A
ns
+V5AUX
[15,18,26,31,32,33,34,35,38]
[15,18,19,22,24,28,34,35,36,38]
+V3.3S
3
1
23
of
Rev
B
USB5
HWS4_1P25R
W-B-4P-R
[5,7,8,9,11,12,13,14,15,17,18,20,22,25,26,27,28,34,35,36,38]
Size
A4
Title
2
1
USB_PN5
USB_PP5
2
48
A
B
C
D
A
B
C
D
[13]
[13]
FB28
VREG
R302
5
C312
4.7uF/10V,X5R
C0603
0
R301
470K
27pF/50V,NPO
C302
C301
27pF/50V,NPO
C313
4.7uF/10V,X5R
C0603
VBUS
AV_PLL
XI_3IN1
Y3
12MHz,20pF
X2S
XO_3IN1
RREF
6.19K,1%
R299
FSDP
0
R298
FSDM
0
R297
220ohm/100MHz,1.5A
+V5S
USB_PP4
USB_PN4
5
1
2
C314
0.1uF/16V,X7R
MS_CLK_R
4
SD_CLK_F
SD_3V3
C307
4.7uF/10V,X5R
4
ns
C318
10pF/50V,NPO
0.1uF/16V,X7R
C319
ns
C310
0.1uF/16V,X7R
C306
1uF/10V,X5R
C0402
ns
MS_CLK
XTLI
XTLO
AV_PLL
RREF
AV33
DM
DP
AG33
A3V3_OUT
5V_IN
VREG
D3V3_OUT
3
C311
4.7uF/10V,X5R
1
2
3
4
5
6
7
8
9
10
11
12
R300
15K
Resistors put near IC
CAP put near Socket
100
C320
10pF/50V,NPO
R307
VBUS
VREG
D3.3V
XI_3IN1
XO_3IN1
AV_PLL
RREF
A3.3V
FSDM
FSDP
C304
4.7uF/10V,X5R
Reserved For EMI Issue
C near Socket
ns
C308
0.1uF/16V,X7R
A3.3V
C303
0.1uF/16V,X7R
C298
680pF/25V,X7R
3
D3.3V
T3
ns
T4
ns
SD_DAT2
SD_DAT3
SD_DAT4
SD_CMD
SD_DAT5
SD_3V3
RST#_3IN1
48
47
46
45
44
43
42
41
40
39
38
37
LQFP48_P5
RTS5156
U12
MS_3V3
T5
T6
1
2
17
9
4
3
22
20
SD_CD#
SD_WP
SD_CMD
SD_CLK_F
SD_DAT0
SD_DAT1
SD_DAT2
SD_DAT3
6
5
14
12
2
MS_SDIO
MS_DATA1
MS_DATA2
MS_DATA3
MS_SCLK
MS_INS
MS_BS
MS_VSS1
MS_VSS2
MS_VCC
2
SD_DAT0
SD_DAT1
SD_DAT2
SD_CD/DAT3
CD/WP/GND_SD4
CD/WP/GND_SD3
CD/WP/GND_SD2
CD/WP/GND_SD1
SD_CLK
SD_CD
SD_WP
SD_CMD
SD_VSS1
WP_VSS1
SD_VSS2
SD_VDD
CARDREADER1
Proconn MSD019-A0-10A0
cr22in3_std
C309
0.1uF/16V,X7R
26
25
24
23
11
10
13
16
18
15
8
7
21
19
RST#_3IN1
+V3.3S
+V5S
C305 0.1uF/16V,X7R
ns
ns
C299
1uF/10V,X5R
C0402
R296
100K
A3.3V
+V3.3S
+V5S
D3.3V
GND
D3.3V
SD_CLK
SD_DAT6
SD_DAT7
SD_DAT0
SD_DAT1
SD_CD#
SD_WP
SD_3V3
36
35
34
33
32
31
30
29
28
27
26
25
C300
0.1uF/16V,X7R
SD_CLK
SD_DAT6
SD_DAT7
SD_DAT0
SD_DAT1
SD_CD#
SD_WP
D3V3_1
DGND3
GPIO0
MS_3V3
D3V3_2
AG_PLL
MODE_SEL
DGND4
D3V3_3
RST#
EEDO
SD_DAT2
SD_DAT3
SD_DAT4
SD_CMD
SD_DAT5
SD_3V3
DGND1
EECS
EESK
EEDI
MS_BS
MS_D1
MS_D0
MS_D2
MS_INS#
MS_D3
MS_CLK
DGND2
MS_BS
MS_D1
MS_SDIO
MS_D2
MS_INS#
MS_D3
MS_CLK
13
14
15
16
17
18
19
20
21
22
23
24
GND
R303
Date:
Size
A3
Title
MS_SDIO
MS_D1
MS_D2
MS_D3
MS_CLK_R
MS_INS#
MS_BS
MS_3V3
SD_CLK
33
Q10
1
Sheet
Cardreader SD/MMC/MS
Thursday, February 26, 2009
Project Name
24
of
No Push to Push function.
Proconn MSD019-A0-10A0
C317
4.7uF/10V,X5R
CZC Technology
ns
C316
0.1uF/16V,X7R
SD_CLK_F
Reserved For EMI Issue, R near IC
[5,7,8,9,11,12,13,14,15,17,18,20,22,23,25,26,27,28,34,35,36,38]
[15,18,19,22,23,28,34,35,36,38]
1
Rev
B
48
A
B
C
D
A
B
C
CT11
CT11
22uF/6.3V,TAN
R312
[7,13,14,20,26,38] PLTRST#
[20,26] PCIE_WAKE#
[17] CLK_PCIE_LAN#
[17] CLK_PCIE_LAN
[13] PCIE_TXP1_LAN
[13] PCIE_TXN1_LAN
[13] PCIE_RXN1_LAN
[13] PCIE_RXP1_LAN
C334
0.1uF/16V,X7R
5
VDD33LAN
C322 to C325 close U15
Pin 16,37,46,53
C413 close PIn 2
close Pin 15,21,43,49,58
EVDD18_R
EVDD12_R
DVDD12
220ohm/100MHz,1.5A
FB0603
FB31
C331
C331
0.1uF/16V,X7R
D
C328
0.1uF/16V,X7R
0.1uF/16V,X7R
+V3.3AUX
VDD33LAN
PCIE_RXP1_LANR
C397 0.1uF/16V,X7R
PCIE_RXN1_LANR
C411 0.1uF/16V,X7R
PERSTB
PCIE_WAKE#
CLK_PCIE_LAN#
CLK_PCIE_LAN
PCIE_TXP1_LAN
4
C335 to C336 close Pin 28
very important
C336
0.1uF/16V,X7R
EVDD12
C335
1uF/10V,X5R
PCIE_TXN1_LAN
0
C332
0.1uF/16V,X7R
C323
0.1uF/16V,X7R
C329
0.1uF/16V,X7R
220ohm/100MHz,1.5A
FB0603
ns
C322
0.1uF/16V,X7R
C333
0.1uF/16V,X7R
C324
0.1uF/16V,X7R
C330
C330
0.1uF/16V,X7R
FB30
C325
C325
0.1uF/16V,X7R
+V3.3S
[23]
[23]
[23]
[23]
C413
C413
0.1uF/16V,X7R
4
LAN_TXD+
LAN_TXDLAN_RXIN+
LAN_RXIN-
DVDD12
VDD33LAN
BI
BI
BI
BI
LAN_RXIN+
LAN_RXIN-
EVDD12_R
VDD33LAN
LAN_TXD+
LAN_TXD-
RSET
DVDD12
3
VCTRL18
AVDD33_1
MDIP0
MDIN0
AVDD18_1
MDIP1
MDIN1
AVDD18_2
MDIP2
MDIN2
AVDD18_3
MDIP3
MDIN3
AVDD18_4
VDD15_1
VDD33_1
LAN_TXD+
LAN_TXDLAN_RXIN+
LAN_RXIN-
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
R308
2.49K,1%
3
LAN_XTALOUT
LAN_XTALIN
PCIE_WAKE#
PERSTB
DVDD12
5
+V5AUX
+V3.3AUX
+V3.3S
+V5S
DVDD12
VDD33LAN
DVDD12
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
RTL8102E
U15
EESK
EEDI
VDD33_3
EEDO
EECS
VDD15_6
NC7
VDD1
NC6
NC5
VDD15_5
VDD33_2
ISOLATEB
NC4
NC3
VDD15_4
RSET
VCTRL15
GVDD
CKTAL2
CKTAL1
AVDD33_2
VDD15_9
LED0
LED1
LED2
LED3
VDD33_4
VDD15_8
NC9
NC8
VDD15_7
NC1
NC2
LANWAKEB
PERSTB
VDD15_2
EVDD18
HSIP
HSIN
EGND_1
REFCLK_P
REFCLK_N
EVDD18
HSOP
HSON
EGND_2
VDD15_3
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PCIE_TXP1_LAN
PCIE_TXN1_LAN
GND
CLK_PCIE_LAN
CLK_PCIE_LAN#
EVDD12
PCIE_RXP1_LANR
PCIE_RXN1_LANR
GND
PAD
65
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
2
[15,18,19,22,23,24,28,34,35,36,38]
+V3.3S
Date:
Size
A4
Title
0
2
8
7
6
5
Q10
Thursday, February 26, 2009
Project Name
PCI-E LAN
1
Sheet
25
of
Rev
B
48
C338
27pF/50V,NPO
LAN_CLKREQ# [17]
Y4
25MHz,20pF
X2S
1
C326
0.1uF/16V,X7R
VDD33LAN
CZC Technology
R421
R311
15K
R310
1K
+V3.3S
C337
27pF/50V,NPO
R415
1K
VDD33LAN
VDD33LAN
ISOLATEB
EESK
EEDI
VDD33LAN
EEDO
EECS
DVDD12
VCC
NC1
NC2
GND
AT93C46
ns
VerB:Modify
CS
SK
DI
DO
U14
3.6K
LAN_XTALOUT
LAN_XTALIN
1
2
3
4
R309
VDD33LAN
[15,18,23,26,31,32,33,34,35,38]
EECS
EESK
EEDI
EEDO
+V5AUX
+V3.3AUX [5,12,13,14,15,18,20,26,27,29,30,31,34,38]
[5,7,8,9,11,12,13,14,15,17,18,20,22,23,26,27,28,34,35,36,38]
+V5S
1
A
B
C
D
A
B
C
D
H_RCIN#
10K
10K
10K
10K
10K
10K
100K
100K
100K
100K
100K
100K
100K
100K
100K
R338
R340
R342
R343
R345
R347
R344
R346
R348
R349
R350
R351
R352
R353
R355
R368
R369
TIN2
TEST_TP
4.7K
R366
R367
4.7K
R365
FA5
ns
MMBT3904-F
Q19
3
R731
1K
ns
+V1.05S
3
IMVP_PWROK
MAIN_ON
V0_9S_ON
V1_8_ON
V105S_15S_ON
IMVP_ON
PM_SLP_S5#
PM_SLP_S3#
PM_SLP_S4#
5
100K
100K
4.7K
4.7K
R364
FA4
4.7K
R363
3
Q18
2N7002K
+V3.3S
2
3
ns
EC Output Signal!
EC_RCIN-
3
Panel_ID0
Panel_ID1
PCB_Mark0
PCB_Mark1
PCB_Mark2
[29] AC_IN
[28]
[28]
[28]
[28]
[28]
[30] BATTEP_BATIN#
[37] AD_I
[29] PWRSW#_S5
[20,25] PCIE_WAKE#
[14,35,38] MAIN_PWROK
[7,14,36,38] IMVP_PWROK
32KXCLKIN
32KXCLKO
C362
15pF/50V,NPO
4
[14,31,35,38] PM_RSMRST#
[18] HW_OFF_BKLT#
[5] ThermalAlertON
[14,38] PM_PWRBTN#
[31] ALWAYS_ON
[20] HW_RATIO_OFF_WLAN#
[14] EC_PCIPME-
[37] CHA_OFF
[34,35,38] MAIN_ON
[32,38] V0_9S_ON
[32,38] V1_8_ON
[33,38] V105S_15S_ON
[33,35,38] CHIP_PWROK
[14,32,38] PM_SLP_S4#
[36,38] IMVP_ON
[14] PM_ICH_PWROK
Y5
32.768kHz,10ppm,12.5pF
X4S67X15
1
4
2
C361
15pF/50V,NPO
KBCSCI-
[29,38] PWRSW#_XP
[18,27] LIDSW#
[14]
[28] SCANOUT[0:15]
[28] SCANIN[0:7]
R327
IN
IN
AD_I
R339
R341
IMVP_ON
MAIN_ON
V0_9S_ON
V1_8_ON
V105S_15S_ON
CHIP_PWROK
AC_IN-
Panel_ID0
Panel_ID1
PCB_Mark0
PCB_Mark1
PCB_Mark2
R357
AC_IN-
28
27
175
8
11
12
20
21
22
48
62
63
69
70
75
109
118
119
148
149
155
156
162
168
81
82
83
84
87
88
89
90
2
26
29
30
44
76
172
176
KB910 176 LQFP
PQFP176_P5
DA0/GPODA0
DA1/GPODA1
DA2/GPODA2
DA3/GPODA3
DA4/GPODA4
DA5/GPODA5
DA6/GPODA6
DA7/GPODA7
GPIO0E
GPIO0D
TOUT2/GPIO2F
GPIO04
GPIO05/FAN3PWM
GPIO06/FANFB3
GPIO07
GPIO08
GPIO09
GPIO10
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO24
GPIO25
GPIO26
GPIO27
GPIO28
GPIO29
GPIO2A
GPIO2B
GPIO2D
AD0/GPIAD0
AD1/GPIAD1
AD2/GPIAD2
AD3/GPIAD3
AD4/GPIAD4
AD5/GPIAD5
AD6/GPIAD6
AD7/GPIAD7
GPWU0
GPWU1
GPWU2
GPWU3
GPWU4
GPWU5
GPWU6/TIN1
GPWU7/TIN2/FANFB2
GA20/GPIO02
KBRST#/GPIO03
ECRST#
ECSCI#
PSCLK1
PSDAT1
PSCLK2
PSDAT2
PSCLK3
PSDAT3
KSO0/GPOK0
KSO1/GPOK1
KSO2/GPOK2
KSO3/GPOK3
KSO4/GPOK4
KSO5/GPOK5
KSO6/GPOK6
KSO7/GPOK7
KSO8/GPOK8
KSO9/GPOK9
KSO10/GPOK10
KSO11/GPOK11
KSO12/GPOK12
KSO13/GPOK13
KSO14/GPOK14
KSO15/GPOK15
KSO16/GPOK16
KSO17/GPOK17
KSI0/GPIK0
KSI1/GPIK1
KSI2/GPIK2
KSI3/GPIK3
KSI4/GPIK4
KSI5/GPIK5
KSI6/GPIK6
KSI7/GPIK7
SERIRQ
LFRAME#
LAD0
LAD1
LAD2
LAD3
LCLK
CLKRUN#/GPIO0C
LRST#/GPIO2C
U17
PC11
1000pF/50V,X7R
3
SCL1
SDA1
SCL2
SDA2
MEMCS#
RD#
WR#
IOCS#
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20/GPIO23
D7
D6
D5
D4
D3
D2
D1
D0
C358
0.1uF/16V,X7R
EC_PM_THRM#
ROLL_PUSH
ROLL_DOWN
SOS#
TP41 ns
TP39 ns
VerB:Del
TP34 ns
TP35 ns
SMB_CLK1
SMB_DAT1
BAT_CLK
BAT_DATA
FCSFRDFWR-
AC_OFF
FA0
FA1
FA2
FA3
FA4
FA5
FA6
FA7
FA8
FA9
FA10
FA11
FA12
FA13
FA14
FA15
FA16
FA17
FA18
FD7
FD6
FD5
FD4
FD3
FD2
FD1
FD0
E51CSE51RXD
E51TXD
24
85
86
91
92
93
94
97
98
32
33
36
37
38
39
40
43
171
23
54
41
55
163
164
169
170
173
150
151
152
124
125
126
127
128
131
132
133
143
142
135
134
130
129
121
120
113
112
104
103
108
147
146
145
144
141
140
139
138
159
17
35
46
122
137
167
96
161
16
34
45
123
136
157
166
95
C360
0.1uF/16V,X7R
2
[27]
[27]
[27]
[27]
[22]
[14]
[18]
[28]
[27]
[27]
[5,27]
[5,27]
[5,30]
[5,30]
[29]
0
ECVCC
C363
0.1uF/16V,X7R
C350
0.1uF/16V,X7R
2
ECVCC
0
+V5AUX
ECVCC
12
11
10
9
8
7
6
5
27
26
23
25
4
28
29
3
2
30
GND
VCC
R322
R323
R324
R325
SST39VF040
PLCC32_1P27
CE#
OE#
WE#
R330
R331
R335
ROLL_PUSH
ROLL_DOWN
SOS#
Date:
ECVCC
1
EC_PWROFF#
2N2222
SOT23
Q20
C355
0.1uF/16V,X7R
Q10
KBC3910
1
Thursday, February 26, 2009
Project Name
Sheet
C356
0.1uF/16V,X7R
26
of
Rev
B
Li.wang
48
C357
0.1uF/16V,X7R
ECVCC
VerB:Del EC Debug CN
10K
ns
4.7K
PM_RSMRST#
C353
0.1uF/16V,X7R
ECVCC
+V3.3AUX
FA18
FD0
FD1
FD2
FD3
FD4
FD5
FD6
FD7
CZC Technology
Size
Custom
Title
C354
0.1uF/16V,X7R
10K
10K
10K
10K
2.2K
2.2K
2.2K
2.2K
16
32
1
13
14
15
17
18
19
20
21
120ohm/100MHz,1A
R362
R361
+V3.3AUX
L18
R326
PCIE_WAKE#
ECVCC
D0
D1
D2
D3
D4
D5
D6
D7
VPP
SMB_CLK1
SMB_DAT1
BAT_CLK
BAT_DATA
22
24
31
FCSFRDFWR-
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
U18
[15,18,23,31,32,33,34,35,38]
[28]
HW_RATIO_OFF_3G# [20]
VerB:Add
1
[3,4,5,6,8,9,12,15,17,33,35,38]
[15,18,19,22,23,24,28,34,35,36,38]
[5,12,13,14,15,18,20,25,27,29,30,31,34,38]
[5,7,8,9,11,12,13,14,15,17,18,20,22,23,25,27,28,34,35,36,38]
FA0
FA1
FA2
FA3
FA4
FA5
FA6
FA7
FA8
FA9
FA10
FA11
FA12
FA13
FA14
FA15
FA16
FA17
+V5AUX
ECVCC
+V1.05S
+V5S
+V3.3AUX
+V3.3S
Button_3G# [27]
+V1.05S
+V5S
+V3.3AUX
+V3.3S
120ohm/100MHz,1A
L10
C348
0.1uF/16V,X7R
R359
TP51 ns
TP52 ns
PM_SUS_STAT# [14,18]
Button_CAM# [27]
PM_BATLOW# [14]
R333
Button_USER# [27]
PWR_LED
BTL_LED
CHG_LED
S5_LED
BTL_BEEP
KBCSMITTL_ADJ
FAN_TACH
NUMLED#
CAPLED#
SMB_CLK1
SMB_DAT1
BAT_CLK
BAT_DATA
AC_OFF
ECVCC
RKBCAGND
C349
1uF/10V,X5R
LVCCA
RVCCBAT
32KXCLKIN
160
158
32KXCLKO
3
4
105
106
107
C359
0.1uF/16V,X7R
BATGND
GND0
GND1
GND2
GND3
GND4
GND5
AGND
VCCBAT
VCC0
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCCA
XCLKI
XCLKO
E51IT0/GPIO00
E51IT1/GPIO01
E51CS#/GPIO20/ISPEN_TP
E51RXD/GPIO21/ISPCLK
E51TXD/GPIO22/ISPDAT
GPIO0B
XIO8CS#/GPIO18
XIO9CS#/GPIO19
XIOACS#/GPIO1A
XIOBCS#/GPIO1B
XIOCCS#/GPIO1C
XIODCS#/GPIO1D
XIOECS#/GPIO1E
XIOFCS#/GPIO1F
PWM0/GPOW0
PWM1/GPOW1
PWM2/GPOW2/FAN1PWM
PWM3/GPOW3
PWM4/GPOW4
PWM5/GPOW5
PWM6/GPOW6
PWM7/GPOW7/FAN2PWM
FANFB1/TOUT1/GPIO2E
NUMLOCK#/GPIO0A
CAPLOCK#/GPIO11
SCROLLLOCK#/GPIO0F
FNLOCK#/GPIO12
KB910Q C1
3
VerB: Support KB910QF C1
99
100
101
102
FAN_PWM 1
42
47
174
CLOSE EC
PC84
1000pF/50V,X7R
FAN_PWM
CC_SET
1K
1K
0
BATT_IN#
0
0
TEST_TP
TIN2
R354
R356
EC_PWROFF#
BATT_IN#
[28]
[37]
1K
5
6
19
31
110
111
114
115
116
117
KBSCLK
KBSDATA
MSCLK
MSDATA
TPD_CLK
TPD_DAT
EC_A20GATEEC_RCINKBCRST
49
50
51
52
53
56
57
58
59
60
61
64
65
66
67
68
153
154
71
72
73
74
77
78
79
80
7
9
15
14
13
10
18
25
165
SCANOUT0
SCANOUT1
SCANOUT2
SCANOUT3
SCANOUT4
SCANOUT5
SCANOUT6
SCANOUT7
SCANOUT8
SCANOUT9
SCANOUT10
SCANOUT11
SCANOUT12
SCANOUT13
SCANOUT14
SCANOUT15
SCANIN0
SCANIN1
SCANIN2
SCANIN3
SCANIN4
SCANIN5
SCANIN6
SCANIN7
EC_PROCHOT#
R329
0
MAIN_PWROK
R332
0
TP36
1K
ns R426
KBCSCI-
TPD_CLK
TPD_DAT
TP40 ALL_PWROK_SYS
ns PM_RSMRST#
HW_OFF_BKLT#
[28]
[28]
[14,27] SERIRQ
[12,27,38] LPC_FRAME#
[12,27,38] LPC_AD0
[12,27,38] LPC_AD1
[12,27,38] LPC_AD2
[12,27,38] LPC_AD3
[17] PCICLK_KBC
[14] PM_CLKRUN#
[7,13,14,20,25,38] PLTRST#
4
[14] PM_SLP_S5#
[14,27,32,33,34,35,38] PM_SLP_S3#
CLOSE TO CHIP
R730
10K
ns
EC Input Signal!
EC_PROCHOT#
+V3.3S
EC Output Signal!
EC_PM_THRM#
EC Output Signal!
EC_A20GATE-
Q16
2N7002K
Q17
2N7002K
+V3.3S
ECVCC
E51CS-
FA1
2
2
2
+V3.3S
KBSCLK
KBSDATA
MSCLK
MSDATA
TPD_CLK
TPD_DAT
HW STRAP OPTION
+V5AUX
[3,36] H_PROCHOT#
[14] PM_THRM#
[12] CPU_A20GATE-
[12]
KBCRST
D29
1N4148WS
C347
0.1uF/16V,X7R
R321
51K
KBC RESET CIRUCT
1
1
1
ECVCC
1
5
C351
10UF/6.3V,X5R
3
2
A
B
C
D
A
B
C
D
R755
0
R816
4.7K
ns
VCC_TCM
[14,26,32,33,34,35,38]
PP
R754
0
PM_SLP_S3#
[14,26] SERIRQ
[12,26,38] LPC_AD0
[12,26,38] LPC_AD1
[12,26,38] LPC_AD2
[12,26,38] LPC_AD3
[12,26,38] LPC_FRAME#
[13] PLT_RST#
[17] PCICLK_TCM
PP
ns
ns
ns
0
13
4
3
10
11
14
31
30
29
24
21
16
23
15
22
1
2
3
4
VCC_TCM
1
2
3
4
NC_P
PP
GPIO3
GPIO15
GPIO16
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
BADD0
BADD1
U42
SSX44B
qfn40_p5
CLKRUN#
LPCPD#
SERIRQ
LAD0
LAD1
LAD2
LAD3
LFRAME#
LRESET#
LCLK
VCC3_1
VCC3_2
VCC3_3
VCC3_4
VCC3_5
VCC3_6
2
12
32
33
34
35
36
37
39
5
38
1
8
9
17
18
27
28
40
6
7
19
20
25
26
R817
R818
VCC_TCM1
VCC_TCM
BADD0
BADD1
FB0603
C694
0.1uF/16V,X7R
10K ns
10K ns
+V3.3AUX
FB72
220ohm/100MHz,1.5A
ns
FB0603
S5_LED
[26]
CAPLED#
NUMLED#
6
5
6
5
1
2
3
4
1
2
3
4
IICCN1
W-B-4P-R
HWS4_1P25R
3
1K
Blue
LED2_0603
Blue
LED2_0603
CAPSLK
WIRELESS_LED# WIRELS
Blue
LED2_0603
CAPLED#
VerB: Add I2C bus Interface
SMB_CLK1 [5,26]
SMB_DAT1 [5,26]
R715
R740
R739
R738
LEDCN1
FFC12
FPC12_P5RT
Q10
WIRE+
CAP+
NUM+
13
14
330
330
330
330
Q53
MMBT3904-F
IDE+
[26]
Q52
MMBT3904-F
Blue
LED2_0603
1
BLUE
PWR1
red blue
LED4_0605
+V3.3S
12
11
10
9
8
7
6
5
4
3
2
1
CHG_LED
BTL_LED
+V3.3AUX
VIN
+V5S
2
+V3.3S
[26]
R711
330
NUMLK
R717
100K
ns
R712
100K
ns
1
+V3.3AUX
NUMLED#
IDE
1K
R716
SATA_LED#
R714
330
RED
R543
FB76
220ohm/100MHz,1.5A
FB0603
+V3.3AUX
[20] WIRELESS_LED#
[26]
[26]
[12] SATA_LED#
PWR_LED
[26]
BA0/1 Address
00---EE/EF
01--7E/7F
10--2E/2F
11--4E/4F(Default)
PWRSWVCC_MBXP [29,31]
PWRSWVCC_S5 [29,31]
Button_CAM# [26]
Button_USER# [26]
Button_3G# [26]
LIDSW#
[18,26]
FB75
220ohm/100MHz,1.5A
Button_CAM#
Button_USER#
+V3.3AUX
+V3.3S
+V3.3AUX
PWRSWVCC_MBXP
PWRSWVCC_S5
Button_CAM#
Button_USER#
Button_3G#
LIDSW#
C698
2.2uF/6.3V,X7R
VerB: Add TCM
C697
1uF/10V,X7R
TP37
TP46
TP53
R750
6
5
BTNCN1
W-B-4P-R
HWS4_1P25R
12
11
10
9
8
7
6
5
4
3
2
1
FB77
220ohm/100MHz,1.5A
6
5
13
FB0603
C695
0.1uF/16V,X7R
PCICLK_TCM
C696
0.1uF/16V,X7R
VCC_TCM1
VerB:Del OSPWRBTN2 circle.
PWRBTN1
FFC12
FPC12_P5RT
14
4
R723
100K
VIN
S5_LED+
5
ACES
87152-1207L
0.5mm 12P Bottom
Pad
41
PWR_LED+
1
2
3
2
3
4
3
2
[29,37,38]
1
C556
C555
C547
C546
C545
C559
CHARGE_LED
ns
LEDT1
Date:
LEDT12 ns
LEDT11 ns
Thursday, February 26, 2009
Project Name
Q10
System LED and button connect
Sheet
27
of
Li.wang
Rev
48
B
ACES
87152-1207L
0.5mm 12P Bottom
FB0603
FB0603
CZC Technology
Size
A3
Title
ns
ns
ns
ns
ns
ns
ns
ns
LEDT10
LEDT9
LEDT8
LEDT7
LEDT6
LEDT5
LEDT4
LEDT3
+V3.3S
1000pF/50V,X7R
1000pF/50V,X7R
1000pF/50V,X7R
+V3.3AUX
220ohm/100MHz,1.5A
220ohm/100MHz,1.5A
C558
BAT_STATE_LED
1000pF/50V,X7R
1000pF/50V,X7R
1000pF/50V,X7R
1000pF/50V,X7R
1000pF/50V,X7R
Q58
MMBT3904-F
Q57
MMBT3904-F
C557
1
CHARGE
red blue
LED4_0605
BLUE
R742
330
WIRE+
CAP+
NUM+
IDE+
PWR_LED+
S5_LED+
1K
1K
FB33
FB34
SATA_LED#
NUMLED#
CAPLED#
WIRELESS_LED#
CHG_LED
BTL_LED
PWR_LED
S5_LED
R744
R743
RED
R741
330
+V3.3AUX
1
[5,7,8,9,11,12,13,14,15,17,18,20,22,23,25,26,28,34,35,36,38]
[15,18,19,22,23,24,28,34,35,36,38]
+V3.3AUX [5,12,13,14,15,18,20,25,26,29,30,31,34,38]
VIN
+V5S
+V3.3S
CHARGE_LED
1
2
3
2
3BAT_STATE_LED
4
3
2
A
B
C
D
A
B
RSW1
TMG-533-V
BUTTON4_S
LSW1
TMG-533-V
BUTTON4_S
Pin12
1
3
1
3
TPD_DAT
13
14
6
5
D58
BAT54SPT
SOT23
ns
6
5
1
2
3
4
1
2
3
4
TPCN2
W-B-4P-R
HWS4_1P25R
+V5S
2
4
2
4
5
TPD3
TPD2
TPD9
TPD7
TPD_CLK
C682
100pF/50V,NPO
C0402
+V5S
TPD_DAT
TPD_CLK
ns
ns
+V5S
ns
ns
ns
ns
+V5S
1
Out TPD_DAT
Out TPD_CLK
TPD11
TPD10
C681
100pF/50V,NPO
C0402
LEFT_Button
RIGHT_Button
TPD_DAT
TPD_CLK
Q11:Reservered
3
12
11
10
9
8
7
6
5
4
3
2
1
2
+V5S
1
3
C
Pin1
Bottom contact
R751
330
330
RIGHT_Button
LEFT_button
4
ACES
85204-04X01
D56
BAT54SPT
SOT23
ns
R752
D55
BAT54SPT
SOT23
ns
+V5S
4
ACES
87152-1207L
0.5mm 12P Bottom
[26]
[26]
D57
BAT54SPT
SOT23
ns
3
TPCN1
FFC12
FPC12_P5RT
TM61PUZG450
Touchpad BOTTOM View
2
Synaptics : TM-00450-001
Was TM61PUZG450
Up.
1
3
2
D
1
2
26
27
VerB:Change to Bottom contact
Pin25
Pin1
[26] SCANIN[0:7]
3
[26] SCANOUT[0:15]
KBCON1
fpc25_1p0rb
25PFPC
R704
1K
3
C1
E C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
R706
1
-
+
R707
100K
R708
R709
10K,1%
C297
KBT1
KBT2
KBT3
KBT4
KBT5
KBT6
KBT7
KBT8
KBT9
KBT10
KBT11
KBT12
KBT13
KBT14
KBT15
KBT16
KBT17
KBT18
KBT19
KBT20
KBT21
KBT22
KBT23
KBT24
KBT25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
V0761EMBK1 US
SCANOUT0
SCANOUT1
SCANOUT2
SCANOUT3
SCANOUT4
SCANOUT5
SCANOUT6
SCANOUT7
SCANOUT8
SCANOUT9
SCANOUT10
SCANOUT11
SCANOUT12
SCANOUT13
SCANOUT14
SCANOUT15
SCANIN0
SCANIN1
SCANIN2
SCANIN3
SCANIN4
SCANIN5
SCANIN6
SCANIN7
2
FAN_PWM [26]
0.1uF/16V,X7R
0
10UF/6.3V,X5R
C0805
C296
ACES
85202-25x61
1.0mm Bottom 25P
100K
2
3
C548
0.1uF/16V,X7R
LM358_VCC
R705
4.7
R710
5.11K,1%
ECVCC
IN
+V5S
[15,18,19,22,23,24,34,35,36,38]
[26]
+V5S
Vfan
[5,7,8,9,11,12,13,14,15,17,18,20,22,23,25,26,27,34,35,36,38]
+V3.3S
IN
2
IN
LM358AM
U75A
4
2
Q14
BCP69T1
C549
0.1uF/16V,X7R
R703
1K
+V5S
3
B
1
5
Bottom contact
8
4
*
*
5
4
5
4
6
5
LM358_VCC
W-B-3P-R
HWS3_1P25R
1
2
3
CPUFAN1
[26] PCB_Mark0
[26] PCB_Mark1
[26] PCB_Mark2
1
2
3
1K
-
+
0
1
0
0
VerD
CPT
1
0
1
0
1
0
7
Date:
1
Thursday, February 26, 2009
Project Name
Q10
Touchpad & Keyboard & FAN Connector
R231
10K
ns
R228
10K
LM358AM
U75B
FAN_TACH [26]
1
CZC Technology
Size
A3
Title
0
0
Fuction P.M1 P.M0
[26] Panel_ID0
[26] Panel_ID1
1
0
VerB
0
VerC
0
VerA
Fuction P.M2 P.M1 P.M0
D23
1N4148WS
SOD323
R288
R287
10K
+V3.3S
8
4
R236
10K
Sheet
R238
10K
ns
R233
10K
R230
10K
ns
28
of
Li.wang
Rev
R239
10K
ns
R237
10K
ECVCC
R232
10K
R229
10K
ns
ECVCC
48
B
A
B
C
D
A
B
C
2
ns
R721
GND_AD
ns
R722
0
R0603
0
R0603
5A
FS1206
5
Iac_N
Iac_P
BATT+
VIN
+V3.3AUX
+VDC
R661
100K
1
[18,31,32,33,36,38]
C530
1000pF/50V,X7R
D45
BAT54SPT
SOT23
[26]
[26,38]
Iac_N
Iac_P
BATT+
VIN
[37]
[37]
[30,37,38]
[27,37,38]
4
R569
51K
1
R565
51K
AD+
Q24
2N7002K
SOT23
SOT23
Q23
DTB114EK
2
3
[27,31] PWRSWVCC_S5
PWRSW#_XP
AC_OFF
C417
0.1uF/25V,X7R
C0603
+V3.3AUX [5,12,13,14,15,18,20,25,26,27,30,31,34,38]
+VDC
80ohm/100MHz,3A
FB0805
FB37
80ohm/100MHz,3A
FB0805
FB36
C416
0.1uF/25V,X7R
C0603
GND_AD
Q47
2N7002K
SOT23
R657
20K,1%
+V3.3AUX
Layout:Use bridge connect GND_AD and GND
2
1
[27,31] PWRSWVCC_MBXP
DCJACK1
2pWafer
HW2_2P5RA
2
F5
1
1
3
D
1
3
2
4
3
Q21
SI4435BDY_AO4419
SOIC8_1P27_3P9
1
8
2
7
3
6
S
5
D
G
R664
100K
1
3
2
Q48
2N7002K
SOT23
R662
20K,1%
+V3.3AUX
R568
51K
C418
0.01uF/25V,X7R
4
T10 VerB
3
2
1
[26]
[26]
[5,35] PWR_SHDN#
PWRSW#_S5
3
ns
SSM34PT
SMA
ns
SSM34PT
SMA
D46
BAT54SPT
SOT23
SMPC
D47
SS5P4
C543
1000pF/50V,X7R
2
1
D31
D30
2
AC_IN
R760
1uF/10V,X5R
C419
R566
10
0.050,1%
R2512
R564
OPEN15X50
P8
PWR_PAD
1
2
2
0
R567
10
[37]
R658
1
1
AD+
R659
10K
R656
15K
Q60
2N7002K
SOT23
R571
100K
Date:
1
Thursday, February 26, 2009
Project Name
Q10
Power Adapter IN
CZC Technology
Size
A3
Title
1K
1
Q26
SI4435BDY_AO4419
SOIC8_1P27_3P9
1
8
2
7
3
6
S
5
D
G
R660
20K,1%
+V3.3AUX
Q46
2N7002K
SOT23
5
6
7
8
51K
SOIC8_1P27_3P9
SI4435BDY_AO4419
Q22
R570
100K
3
2
1
C539
1000pF/50V,X7R
C532
1000pF/50V,X7R
R573
51K
R572
100K
Iac_P
C534
0.01uF/25V,X7R
[37]
Iac_N
2008-11-25
VIN
R563
4
3
2
5
3
2
S
S
3
4
G
2
D
3
Sheet
29
Quaf
C531
1000pF/50V,X7R
+VDC
BATT+
of
Rev
48
B
A
B
C
D
A
B
C
D
GND_MBAT
1
2
3
4
5
6
7
8
9
10
11
12
BAT_DATA_R
BAT_CLK_R
BAT_IN#
VBAT_F
5
ACES 87213-1210
BATCN1
1.0mm Wafer
HWS12_1P0R
ns
5
GND_MBAT
13
14
BATCON2
BATTCN
bat7r_in
4
GND_MBAT
GND
GND
TEMP
BAT_IN#
SCLK
SDAT
BATT+
BATT+
8
4
GND_MBAT
9
R465
1
2
R470 ns
R469 ns
R467
0
R0603
0
R0603
100
100
100
Layout: Use bridge connect
GND_AD and GND
BAT_IN#
BAT_CLK_R
4
3
R466
BAT_DATA_R
VBAT_F
5
6
7
F9
7A
FS1206
P
3
+V3.3AUX
R468
10K
[5,26]
[5,26]
BATTEP_BATIN# [26]
BAT_CLK
[29,37,38]
2
2
BAT_CLK
BAT_DATA
3
3
SOT23
C535
0.1uF/16V,X7R
+V3.3AUX
C536
0.1uF/16V,X7R
+V3.3AUX
Date:
Thursday, February 26, 2009
Project Name
Q10
Power Battery IN
CZC Technology
1
2
1
2
Size
Custom
Title
BAT54SPT
D33
SOT23
BAT54SPT
D32
+V3.3AUX [5,12,13,14,15,18,20,25,26,27,29,31,34,38]
BATT+
BATT+
BAT_DATA
+V3.3AUX
BATT+
80ohm/100MHz,3A
FB0805
80ohm/100MHz,3A
FB0805
C504
1000pF/50V,X7R
FB43
FB42
3
1
1
Sheet
30
Quaf
of
Rev
B
48
A
B
C
D
A
B
C
D
5V_LDO
+V5AUX
5
[18,29,32,33,36,38]
C542
0.1uF/16V,X7R
ACAV
[27,29] PWRSWVCC_S5
1
2
1
2
R592
169K,1%
R591
82.5K,1%
R590
3
3
D35
BAT54C
SOT23
3
5V_LDR
1K
5V_VREF
AUX_POK
1
4
ON/SKIP1
VDDA
TSET
Q50
2N7002K
SOT23
R666
34K,1%
+V5AUX
1
CS_V3P
CS_V3N
U19
OZ815LN
QFN24_P5
CS_V5N
CS_V5P
BST2
13
14
15
16
17
18
1N4148WS
SOD323
D37
PM_RSMRST# [14,26,35,38]
V3A_ON
4.7K
R598
3
C445
0.1uF/16V,X7R
C435
0.22uF/16V,X5R
C428
0.22uF/16V,X5R
V5A_ON
2.2K
BST1
LDR1
GNDP
VDDP
LDR2
R597
Q51
2N7002K
SOT23
R667
10K
+V3.3AUX
D36
BZT52C3V6S-F/3.6V
SOD323
GND_AL
C439
1000pF/50V,X7R
C529
1uF/10V,X5R
C0402
R668
10K
6
5
VREF
VIN
ON/SKIP2
5V_VSET
V5A_ON
3
5V_VIN
4
2
V3A_ON
+V3.3AUX
GND_AL
C427
1000pF/50V,X7R
1
GND_AL
C444
0.01uF/25V,X7R
R596
C434
1uF/10V,X5R
GND_AL
10
2008-11-28
0.1uF/16V,X7R
C0402
C688
D59
SOT23
BAT54SPT
D34
BAT54C
SOT23
5V_LDO
R589
24.9K,1%
GND_AL
GND_AL
[27,29] PWRSWVCC_MBXP
[37]
[26] ALWAYS_ON
3V_VSET
GND_AL
2
1
C690
C689
0.47uF/16V,X7R 0.47uF/16V,X7R
C0603
C0603
5V_LDO
[15,18,23,26,32,33,34,35,38]
[38]
C432
0.01uF/25V,X7R
R588
4.7
+VDC
+V10Aux
5V_LDO
+V5AUX
+V3.3AUX [5,12,13,14,15,18,20,25,26,27,29,30,34,38]
25
GNDA0
+VDC
24
VSET2
VSET1
7
3
C446
0.1uF/16V,X7R
8
3
3V_LX
3V_LDR
3
5V_LX
5V_LDR
5
5V_HDR
C433
1uF/10V,X5R
5V_LDO
2
D1
G2
G1
D1
G2
G1
8
5
3V_HDR
S2
D2
S2
D2
6
7
Q27
6
7
Q28
0
R0603
R632
GND_AL
2
GND_AL
GND_AL
R595
47
CS_V5N
GND_AL
C443
1000pF/50V,X7R
C441
0.01uF/25V,X7R
15K
R594
C438
1000pF/50V,X7R
C431
1000pF/50V,X7R
C437
0.1uF/25V,X7R
C0603
4.7UH/5.5A
CKS2D66
L12
R587
47
3V_OUT
C425
1000pF/50V,X7R
C429
CS_V3N
0.01uF/25V,X7R
C442
22pF/50V,NPO
C436
10uF/25V,X5R
C1210
R593
100K
15K
R586
4.7UH/5.5A
CKS2D66
L11
C424
0.1uF/25V,X7R
C0603
C430
22pF/50V,NPO
GND_AL
R585
100K
CS_V5P
5V_LX
SI4914DY_AO4932
SOIC8_1P27_3P9
D1
2
C423
10uF/25V,X5R
C1210
CS_V3P
3V_LX
SI4914DY_AO4932
SOIC8_1P27_3P9
D1
S1
1
S1
4
2
+VDC
4
11
23
CS2N
CS1N
8
3
2
1
+V3.3AUX
5
3
2
12
LX1
22
CS1P
9
CS2P
20
LX2
19
HDR2
HDR1
21
POK2
POK1
10
AUX_POK
4
AUX_POK
+
OPEN15X50
P2
PWR_PAD
1
2
C440
220uF/6.3V,25m
CT7343_19
C426
220uF/6.3V,25m
CT7343_19
OPEN15X50
P1
PWR_PAD
1
2
Date:
1
Thursday, February 26, 2009
Project Name
Q10
Power +V3.3Aux +V5Aux +10V
CZC Technology
+
Size
Custom
Title
5V_OUT
+VDC
+VDC
1
Sheet
31
Quaf
of
+V5AUX
Rev
+V3.3AUX
48
B
A
B
C
D
A
B
C
C452
M_VREF
5
0
R676
ns
0
R675
[26,38] V0_9S_ON
PM_SLP_S3#
0
R665
0
ns
R663
R753
C457
1uF/10V,X5R
GND_DDR
10
0.01uF/25V,X7R
[26,38] V1_8_ON
[14,26,38] PM_SLP_S4#
[11]
[14,26,27,33,34,35,38]
GND_DDR
+V5AUX
C454
0.1uF/16V,X7R
R606
GND_DDR
R602
1K
6
5
M_VTT_ON
M_DDR_ON
GND_DDR
4
7
+V1.8
+V0.9S
+VDC
+V5AUX
DDR_VTTS
LDR
BST
R607
13
14
15
+V1.8
+V0.9S
+VDC
+V5AUX
47
[7,9,11]
[11,38]
3
+V0.9S
C463
10uF/6.3V,X5R
C0805
[15,18,23,26,31,33,34,35,38]
[18,29,31,33,36,38]
DDR_LX
+V5AUX
+V5AUX
C455
1uF/10V,X5R
C462
10uF/6.3V,X5R
C0805
3
D38
1N4148WS
SOD323
C451
0.22uF/16V,X5R
+V1.8
V18_LDR
10K
C461
10uF/6.3V,X5R
C0805
VSS1
VSS2
GNDP
16
17
18
V18_HDR
R600
VDDP
C466
10uF/6.3V,X5R
C0805
C465
C0805
10uF/6.3V,X5R
QFN24_P5
+V1.8
VTTREF
ON_VTT
VDDA
TSET
VREF
VIN
U20
8
OZ812LN
VTTS
ON/SKIP
C464
1000pF/50V,X7R
C460
1uF/10V,X5R
VTTREF
GND_DDR
0
M_VTT_ON
DDR_VDD
3
DDR_VREF
4
2
1
DDR_VIN
M_DDR_ON
GND_DDR GND_DDR
9
+VDC
M_CSP
M_CSN
VDDQ1
C450
1000pF/50V,X7R
25
PAD
VDDQ2
10
R601
64.9K,1%
V18_VSET
24
VSET
V18_PG
VTT1
11
R599
34K,1%
23
CSN
22
CSP
20
VTT2
12
LX
19
HDR
21
PGD
4
2
D1
G2
G1
R609
3
5
8
1
S2
D2
6
7
DDR_LX
R610
10K
+V0.9S
1
Q29
SI4914DY_AO4932
SOIC8_1P27_3P9
D1
1K
S1
4
D
5
Q30
HMBT3904
SOT23
R608
34K,1%
+V5AUX
2
M_CSP
R603
100K
2
1
GND_DDR
Q31
2N7002K
SOT23
0
R0603
R637
+
Date:
1
Thursday, February 26, 2009
Project Name
Q10
Power +V1.8 & +V0.9S
Sheet
OPEN15X50
ns
P3
PWR_PAD
1
2
C453
220uF/2.5V,15m
CT7343_19
1
CZC Technology
Size
A3
Title
V0_9S_PWROK [35]
GND_DDR
GND_DDR
C459
1000pF/50V,X7R
M_CSN
VerB: Change Value
3300pF/50V,X7R
C456
51K
R604
V18_OUT
+VDC
R605
47
1000pF/50V,X7R
C449
3.3UH/6A
CKS2D66
L13
2008-11-25
C448
0.1uF/25V,X7R
C0603
C458
22pF/50V,NPO
C447
10uF/25V,X5R
C1210
3
2
3
2
32
Quaf
of
Rev
48
B
+V1.8
A
B
C
D
A
B
C
D
GND_IC
R614
R615
5
R616
PM_SLP_S3#
+V5Aux
36.5K,1%
GND_IC
[26,38] V105S_15S_ON
[14,26,27,32,34,35,38]
84.5K,1%
+V5Aux
R617
0
R678
0
R677
ns
5
6
V1_5S_ON
ON/SKIP1
VDDA
TSET
VREF
VIN
ON/SKIP2
D41
1N4148WS
SOD323
R622
4.7K
R621
1K
4
C488
0.1uF/16V,X7R
V1_05S_ON
V1_5S_ON
GND_IC
C480
1000pF/50V,X7R
V15_TSET
4
V105_VDD
3
2
1
V15_REF
C474
0.1uF/16V,X7R
GND_IC
C478
1uF/10V,X5R
4.7
V1_05S_ON
+VDC
GND_IC
C470
1000pF/50V,X7R
V105_VSET
[15,18,23,26,31,32,34,35,38]
100K,1%
+V5Aux
CS1_05P
CS1_05N
U21
OZ8138LN
QFN24_P5
BST2
LDR2
BST1
LDR1
GNDP
VDDP
C489
0.1uF/16V,X7R
CS1_5N
CS1_5P
D40
1N4148WS
SOD323
3
0
R0603
8
5
3
V105_HDR
V105_LX
V105_LDR
GND_IC
3
V15_LX
V15_LDR
5
V15_HDR
+V5Aux
8
+V5Aux
+V5Aux
R580
1uF/10V,X5R
C475
SOD323
C479
0.1uF/16V,X7R
CHIP_PWROK [26,35,38]
GND_IC
13
14
15
16
17
18
D39
1N4148WS
C472
0.1uF/16V,X7R
CHIP_PWROK [26,35,38]
VSET1
7
[3,4,5,6,8,9,12,15,17,26,35,38]
8
+V1.05S
CS1N
[4,7,8,9,13,15,20,35,38]
CS1P
9
[18,29,31,32,36,38]
PGD1
10
+VDC
LX1
11
+V1.5S
HDR1
12
+V1.05S
24
VSET2
22
CS2P
23
CS2N
21
PGD2
20
LX2
19
HDR2
PAD
25
+VDC
G2
G1
D1
2
+V1.5S
3
2
D1
S2
D2
S1
6
6
7
Q32
R618
100K
GND_IC
C486
22pF/50V,NPO
CS1_05P
R611
100K
2
CS1_5N
3300pF/50V,X7R
2
R619
47
C481
10uF/25V,X5R
C1210
C487
1000pF/50V,X7R
GND_IC
GND_IC
+VDC
+
+
1
OPEN15X50
P4
PWR_PAD
1
2
Date:
Size
Custom
1
Thursday, February 26, 2009
Project Name
Q10
Power +V1.5S & +V1.05S
CZC Technology
OPEN15X50
P5
PWR_PAD
1
2
C471
220uF/2.5V,15m
CT7343_19
V105_OUT
C484
220uF/2.5V,15m
CT7343_19
Title
V15_OUT
1000pF/50V,X7R
C483
C477
1000pF/50V,X7R
C482
0.1uF/25V,X7R
C0603
CS1_05N
3300pF/50V,X7R
VerB: Change Value
C473
51K
R613
+VDC
1000pF/50V,X7R
C469
R612
47
C468
0.1uF/25V,X7R
C0603
3.3UH/6A
CKS2D66
L14
C467
10uF/25V,X5R
C1210
VerB: Change Value
C485
51K
R620
3.3UH/6A
CKS2D66
L15
GND_IC
C476
22pF/50V,NPO
V105_LX
CS1_5P
V15_LX
SI4914DY_AO4932
SOIC8_1P27_3P9
D1
Q33
7
S2
D2
S1
1
SI4914DY_AO4932
SOIC8_1P27_3P9
D1
G2
G1
4
4
4
5
1
Sheet
33
Quaf
+V1.5S
of
Rev
48
B
+V1.05S
A
B
C
D
A
B
C
PM_SLP_S3#
5
[26,35,38] MAIN_ON
[14,26,27,32,33,35,38]
0
R680
0
ns
R679
+V10Aux
2008-11-28
1
+V3.3S
R626
10K
1K
4
C538
1uF/10V,X5R
R623
Q37
2N7002K
SOT23
DTB114EK
SOT23
Q36
2
3
1
3
2
U24
G905T24U
SOT89
10K
R624
0.01uF/25V,X7R
C490
4
+V5AUX
+VDCS
3
C537
10uF/6.3V,X5R
C0805
+V2.5S
C492
1uF/10V,X5R
Q34
SI4800BDY_AO4468
SOIC8_1P27_3P9
3
+V5S
+V2.5S
R670
20K,1%
R625
1N4148WS
D42
SOD323
1K
R758
10K
0.01uF/25V,X7R
C491
4
+V3.3AUX
+VDCS
+VDC
+V2.5S
+V5AUX
+V3.3AUX
+V5S
+V3.3S
2
5
6
7
8
D
GND
1
5
6
7
8
3
2
1
4
VIN
2
5
VOUT
3
G
2
1
[5,7,8,9,11,12,13,14,15,17,18,20,22,23,25,26,27,28,35,36,38]
[9,38]
[38]
+VDCS
Q59
HMBT3904
SOT23
R724
34K,1%
1
Date:
1
Thursday, February 26, 2009
Project Name
Q10
Power +V5S & +V3.3S & +V25S
CZC Technology
Size
A3
Title
Q54
2N7002K
SOT23
+V3.3S
[18,29,31,32,33,36,38]
+VDC
V25S_PWROK [35]
[15,18,23,26,31,32,33,35,38]
+V2.5S
+V5AUX
+V3.3AUX [5,12,13,14,15,18,20,25,26,27,29,30,31,38]
[15,18,19,22,23,24,28,35,36,38]
+V5S
1uF/10V,X5R
+V5S
1
+V3.3S
Q35
SI4800BDY_AO4468
SOIC8_1P27_3P9
C493
3
D
2
S
3
2
1
S
3
G
2
D
Sheet
34
Quaf
of
Rev
48
B
A
B
C
D
A
B
C
D
[14,26,31,38]
[14,26,27,32,33,34,38]
5
PM_RSMRST#
PM_SLP_S3#
[26,33,38] CHIP_PWROK
[34] V25S_PWROK
[32] V0_9S_PWROK
4
U25
SN74AHC1G08DBV
SOT23_5
R627
10K
+V3.3S
[26,34,38] MAIN_ON
PM_SLP_S3#
GND
VCC
[14,26,27,32,33,34,38]
2
0
R629
+V3.3S
0
R759
1
0
R628
5
3
0
R682
0
ns
R681
2
1
+V3.3S
GND
VCC
5
4
3
4
1
Q45
2N7002K
SOT23
R650
100K
+V5AUX
U26
SN74AHC1G08DBV
SOT23_5
1
3
DISCHARGE
Q41
2N7002K
SOT23
R651
47
R0603
+V5S
MAIN_PWROK [14,26,38]
C236
0.1uF/16V,X7R
+V3.3S
C235
0.1uF/16V,X7R
+V3.3S
3
2
3
1
Q42
2N7002K
SOT23
R652
47
R0603
+V3.3S
[14,26,38] MAIN_PWROK
[26,34,38] MAIN_ON
3
2
1
1
D48
SOD323
1N4148WS
+V1.5S
+V1.05S
+V5AUX
+V5S
+V3.3S
3
2
Q56
2N7002K
SOT23
2
Q43
2N7002K
SOT23
R653
47
R0603
+V1.5S
2
4
3
2
5
3
2
Q44
2N7002K
SOT23
R654
47
R0603
+V1.05S
C509
4.7uF/10V,X5R
C0603
1
[4,7,8,9,13,15,20,33,38]
PWR_SHDN#
[5,29]
Date:
1
Thursday, February 26, 2009
Project Name
Q10
Power Main Power OK
CZC Technology
Size
A3
Title
Q49
2N7002K
SOT23
[3,4,5,6,8,9,12,15,17,26,33,38]
[15,18,23,26,31,32,33,34,38]
MAIN_SHDN
1
1
[5,7,8,9,11,12,13,14,15,17,18,20,22,23,25,26,27,28,34,36,38]
[15,18,19,22,23,24,28,34,36,38]
R725
560K
+V1.5S
+V1.05S
+V5AUX
+V5S
+V3.3S
3
2
3
2
Sheet
35
Quaf
of
Rev
48
B
A
B
C
D
A
B
R672
51K
R673
100K
GND_CPU
C505
1uF/10V,X5R
+V5S
5
[3,26] H_PROCHOT#
GND_CPU
R633
100K,1%
R631
24.9K,1%
GND_CPU
C510
1uF/10V,X5R
R641
470
CORE_VBT
C496
0.01uF/25V,X7R
ns
PAD
VBT
C511
GND_CPU
4
VID4
VID5
VID6
VR_ON
VDDP
LDR
GNDP
BST
9
10
11
12
13
14
15
16
1000pF/50V,X7R
C513
0.01uF/25V,X7R
C508
U22
OZ8291
QFN32_P5
+VDC
R642
10K
CORE_IN
CORE_TSET
CORE_OVP
33
32
VREF
CLK_ENb
VR_TTb
VDDA
IMON
RSN
RSP_LL
0.01uF/25V,X7R
GND_CPU
C512
0.1uF/16V,X7R
GND_CPU
30
29
28
27
26
25
CORE_VREF 31
CORE_VDD
2200pF/25V,X7R
C501
[14] VR_PWRGD_CLKEN#
C527
330pF/50V,X7R
ns
C514
330pF/50V,X7R
ns
R638
10
VSS_SENSE
GND_CPU
VCC_SENSE
CPU_CSN
CPU_CSP
CORE_RSP
C
[4]
[4]
GND_CPU
OVP
1
D
GND_CPU
TSET
2
22pF/50V,NPO
4
VIN
3
C516
23
DSLP
4
5
24
RSP
VID0
5
CSN
22
VID1
6
CSP
21
SLEW
19
VID2
7
PG6
20
COMP
18
VID3
8
LX
17
HDR
CORE_SLEW
CORE_BST
R630
2.2K
+V3.3S
CORE_LDR
1uF/10V,X5R
C494
3
+V5S
[4]
[26,38]
[4]
[4]
[4]
PM_DPRSLPVR [7,14]
CPU_VID0
CPU_VID1
CPU_VID2
[4]
[4]
[4]
CPU_VID3
G2
G1
CPU_VID5
CPU_VID4
2
D1
CPU_VID6
IMVP_ON
C500
1uF/10V,X5R
3
8
CPU_LX 5
CORE_HDR
IMVP_PWROK [7,14,26,38]
3
1
S2
D2
S1
4
CORE_COMP
6
7
CPU_CSN
CPU_CSP
CPU_LX
Q38
SI4914DY_AO4932
SOIC8_1P27_3P9
D1
100K
1K
R674
2
2200pF/25V,X7R
C507
R636
R635
100K
L16
1.0UH/11A
CKS2D66
0
R0603
R640
1000pF/50V,X7R
C515
VCORE
2
OPEN15X50
PWR_PAD
P7
1
ns
P6
PWR_PAD
OPEN15X50 ns
1
2
Date:
1
Thursday, February 26, 2009
Project Name
Q10
Power CPU
CZC Technology
Size
Custom
Title
GND_CPU
+ C503
220uF/2.5V,15m
CT7343_19
C499
10uF/25V,X5R
C1210
+VDC
[15,18,19,22,23,24,28,34,35,38]
[18,29,31,32,33,38]
C498
1000pF/50V,X7R
GND_CPU
1
Sheet
36
Quaf
of
+VCC_CORE
[5,7,8,9,11,12,13,14,15,17,18,20,22,23,25,26,27,28,34,35,38]
+VCC_CORE [4,38]
+VDC
+V5S
+V3.3S
+ C502
220uF/2.5V,15m
CT7343_19
C495
0.1uF/25V,X7R
C0603
+VCC_CORE
+VDC
+V5S
+V3.3S
R671
47
C497
10uF/25V,X5R
C1210
2
Rev
48
B
A
B
C
D
A
B
C
VIN
5
C517
0.1uF/25V,X7R
C0603
[26]
CHA_OFF
Iac_P
[29]
[26]
Iac_N
ACAV
[29]
[31]
C522
0.47uF/16V,X7R
C0603
C518
10uF/25V,X5R
C1210
10
9
4
CC_SET
R649
14
ICHM
CHG_LX
IACP
IACM
ICHM
ICHP
ACAV
CHIGH
HDR
VAC
1K
10K
1
R645
C523
1
GND_CHR
C528
0.01uF/25V,X7R
Charge_Cells
CHG_IOUT
3
2
CHG_VSET
4
5CHG_COMP
3
ns
R726
0
ns
ICHM
ICHP
GND_CHR
R761
0
ns
AD_I
GND_CHR
0.22uF/16V,X5R
0.01uF/25V,X7R
C552
C525
4.7uF/10V,X5R
C0603
4.7uF/10V,X5R
C0603
C519
10uF/25V,X5R
C1210
CHG_LU
Charge_Cells
150,1%
CHG_LV
7
6
C524
CHR_REF
3
8
CHG_ISET
ISET
CELLS
IOUT
VSET
COMP
GND
LV
REF
10uH/2.7A
CKS2D83
L17
Q40
2N7002K
SOT23
U23
OZ8602GN
SOIC16_1p27_3p9
D44
SSM34PT
SMA
R648
16
15
13
ICHP
12
CHG_CHIGH 11
CHR_DRV
Q39
SI4435BDY_AO4419
SOIC8_1P27_3P9
1
8
2
7
3
6
S
5
D
G
4
[26]
R647
49.9K,1%
0
R0603
R581
VIN
BATT+
GND_CHR
2
C526
0.01uF/25V,X7R
CHR_REF
Charge_Cells
GND_CHR
Icharge=Vch/Rcharge
R646
100K,1%
GND_CHR
GND_CHR
C0603
4.7uF/10V,X5R
C521
R644
10
0.050,1%
R2512
R643
VIN
BATT+
2
[29,30,38]
VerB:Add
CELLSLECT1
DIP MSS3
SWS7D67x26
1
Date:
1
Thursday, February 26, 2009
Project Name
Q10
Power Charger OZ8602
CZC Technology
Size
A3
Title
BATT+
GND_CHR
GND_CHR
1
2
3
C520
0.1uF/25V,X7R
C0603
[27,29,38]
4
6
D
5
3
2
5
7
4
CHR_DRV
Sheet
37
Quaf
of
Rev
48
B
A
B
C
D
A
B
C
H_S9
BOSSC237PT276D118
MH24X40X65
ns
5
10
9
8
7
6
5
4
3
2
1
11
12
11
12
MB pin10----DB pin1
PCICLK_LPC
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
PLTRST#
10
9
8
7
6
5
4
3
2
1
LPC_DEBUG
FPC10 1.0mm
FPC10_1p0rt
VerB: Del PWROKLED circle.
[17] PCICLK_LPC
[12,26,27] LPC_AD0
[12,26,27] LPC_AD1
[12,26,27] LPC_AD2
[12,26,27] LPC_AD3
[12,26,27] LPC_FRAME#
[7,13,14,20,25,26] PLTRST#
+V3.3S
GND_MBat
4
3
+V5Aux
+V3.3AUX
5V_LDO
[15,18,19,22,23,24,28,34,35,36]
[34]
+V1.05S
+V1.5S
3
C541
0.1uF/16V,X7R
+V3.3Aux
[4,36] +VCC_CORE
[3,4,5,6,8,9,12,15,17,26,33,35]
[4,7,8,9,13,15,20,33,35]
[9,34] +V2.5S
+V3.3S
+V5S
+VDCS
[11,32] +V0.9S
[15,18,23,26,31,32,33,34,35]
[5,12,13,14,15,18,20,25,26,27,29,30,31,34]
[31]
[29,30,37] BATT+
+VDC
[27,29,37] VIN
[18,29,31,32,33,36]
[5,7,8,9,11,12,13,14,15,17,18,20,22,23,25,26,27,28,34,35,36]
H_S10
BOSSC237PT276D118
MH24X40X65
ns
1
1
H_S8
BOSSC237PT276D118
MH24X40X65
ns
1
1
H_S12
BOSSC237PT276D118
MH24X40X65
ns
VerB:ADD
H_S11
BOSSC237PT276D118
MH24X40X65
ns
1
1
H_S5
H_S7
BOSSC237PT276D118 BOSSC237PT276D118
MH24X40X65
MH24X40X65
ns
ns
USB_GND3
H_S4
BOSSC237PT276D118
MH24X40X65
ns
4
1
1
D
1
1
H_S2
H_S3
BOSSC237PT276D118 BOSSC237PT276D118
MH24X40X65
MH24X40X65
ns
ns
5
1
1
H_S1
BOSSC237PT276D118
MH24X40X65
ns
1
1
1
1
1
1
1
1
1
1
FD2
FD3
FD4
FD5
FD6
FD7
FD8
TestP
VBAT
TestP
TestP
V33S
TestP
TestP
V5S1
TestP
V15S1
TestP
V105S1
TestP
V25S
TestP
VDCS
TestP
V5AL
V09S1
TestP
V33AL
TestP
TestP
VDC
V5LDO
TestP
VIN
CPUCORE
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PM_SLP_S3#
IMVP_PWROK
TPC30 ns
PCIRSTN
CPUDPSLPN
CPUSLPN
CPUADS
[3,6] H_CPUSLP#
[3,6]
CPUSTPCLKN
LPCFRAMEN
[12,26,27] LPC_FRAME#
2
Date:
Size
A3
Q10
1
Thursday, February 26, 2009
Project Name
SCREW HOLE
CZC Technology
Sheet
ns
ns
ns
ns
ns
ns
38
TPC30 ns
TPC30 ns
TPC30 ns
CPURSTN
CPUPWROK
[3,12] H_DPSLP#
Title
TPC30 ns
TPC30 ns
ICHPWROK
IMVPPWROK
IMVPON
CPUDPRSTPN
H_ADS#
TPC30 ns
TPC30 ns
TPC30 ns
TPC30 ns
TPC30 ns
V105S15SPWROK TPC30 ns
V105S15SON
MAINPWROK
VTTON
MAINON
DDR2ON
TPC30 ns
SLPS3N
[3,12] H_DPRSTP#
PLTRST#
TPC30 ns
TPC30 ns
SLPS4N
TPC30 ns
PWRBTNN
TPC30 ns
RSMRSTN
PWRSWN
[14,17] PM_STPCPU#
[7,13,14,20,25,26]
[3,6] H_CPURST#
[3,12] CPU_PWRGD
[14] ICH_PWROK
[7,14,26,36]
[26,36] IMVP_ON
[26,33,35] CHIP_PWROK
[26,33] V105S_15S_ON
[14,26,35] MAIN_PWROK
[26,32] V0_9S_ON
[26,34,35] MAIN_ON
[26,32] V1_8_ON
[14,26,27,32,33,34,35]
[14,26,32] PM_SLP_S4#
[14,26] PM_PWRBTN#
PM_RSMRST#
[26,29] PWRSW#_XP
[14,26,31,35]
1
Layout note:
This Test point must be place same side and follow CPU side.
TPC60
TPC60
TPC60
TPC60
TPC60
TPC60
TPC60
TPC60
TPC60
TPC60
TPC60
TPC60
TPC60
TPC60
FMARKC FMARKC FMARKC FMARKC FMARKC FMARKC FMARKC FMARKC
ns
ns
ns
ns
ns
ns
ns
ns
FD1
2
of
Rev
B
48
A
B
C
D
5
4
3
2
Title
Date:
Thursday, February 26, 2009
CustomQ10
1
Project Name
Anfeng
Sheet
48
B
of
Rev
39
A
A
Power Map
Size
B
B
1
C
2
C
3
D
4
D
5
A
B
C
D
DC_IN
ACAV
S4
S5
DEVICE
1
+VDC
X
X
X
X
X
X
5
X
X
3.3V
1.5V
1.8VDIMM
X
X
2.5V
X
LCDVDD,LEDVDD
VCCA
X
X
0.9V
X
X
5V
ECVCC(BATT)
ECVCC(AC)
2
EN1
AUX_POK
EN2
+V1.05S
9a
+V1.5S
8a
+V1.8
9a
4
+V3.3S
OZ8138
4
CHIP_PWROK
+V0.9S PWRGD
AMS1117
+V5S
PWRSWVCC_MBS5
PWRSWVCC_MBXP
QZ812LN
MOS SW
MOS SW
OZ815
VREG5
+V0.9S
3.3VAUX(BATT)
X
X
3.3VAUX(AC)
X
X
X
X
X
5VAUX(BATT)
X
X
X
5VAUX(AC)
X
+V1.05S
X
X
X
X
X
VCORE
S3
3
9 PM_SLP_S3#
X
S0/S1
Battary
OZ8604
Charge
+V5AUX
+V3.3AUX
ACAV
9b
8b
PWRGD
Circuits
+V1.05S_ON
+V1.5S_ON
+V2.5S
PM_SLP_S3#
PM_SLP_S4#
9C
5
MAIN_PWROK
BUFFER
3
8
9
PM_RSMRST#
KB910
6
PWRSWVCC_MBS5
KB910
KB910
5
PLTRST#
82801GBM
15
7
Delay 99ms send VR_ON
PM_ICH_PWROK
3
PWRSWVCC_MBXP
PWROK
4
SB_PWRBTNPWRBTN#
5
PM_RSMRST#
RSMRST#
16
17
PLT_RST#
13a
BUFFER
11 IMVP_ON
IMVP_OK
ALL_PWROK_SYS
H_PWRGD
2
PLTRST#
2
PWRGOOD
+VCC_CORE
945GSE
18
Date:
IMVP_OK
CK505
+VDC
1
Q10
1
Thursday, February 26, 2009
Project Name
Power block
Sheet
CZC Technology
Size
Custom
Title
PWROK
13a
CLK_PWRGD_GEN
12
ATOM N270 CPU
13
IMVP6
ISL6261
RSTIN#
14
RESET#
H_CPURST#
40
of
Rev
B
48
A
B
C
D
A
B
C
D
CPURST#
5
VCCRTC
RTCRST#
IacN
(PRESS POWER BUTTON)
PWRSWVCC2
PWRSW#(Input to EC)
+VDC
+V3.3AL,+V5AL
EC_RTC,+V5_STBY
PM_RSMRST#(Input to EC/ICH)
SB_PWRBTN-(EC Output to SB)
PM_SLP_S4#(Input to EC)
PM_SLP_S3#(Input to EC)
ALWAYS_ON(EC Output)
MAIN_ON(PM_SLP_S3#)
V1_8_ON(SLP_S4#)
V0_9S_ON(SLP_S3#)
+V3.3S,+V5S,
+V1.5S,+V1.05S,+V2.5S,
MAIN_PWROK(Input to EC)
IMVP_ON(EC Output)
+VCC_Core
Clock Gen Output
CK410M_CLK_EN#
IMVP_OK
PM_ICH_PWROK (EC output to ICH)
H_CPUPWRGD
SUS_STAT#
PLTRST#
PCIRST#
T01
G3
T02
G3
T03
T04
T06
S5
PLUG
Main
Battery
T08
T10
S3/S4/S5
Keep up +VDC
T49
99ms
Power On Sequence(Battery mode)
5. Power on Sequence:
5
4
4
T23
T14
T17
T15
T24
S0
T16
S0
3
3
VCCRTC
RTCRST#
IacN
+VDC
+V3.3AL,+V5AL
EC_RTC,+V5_STBY
PM_RSMRST#(Input to EC/SB)
(PRESS POWER
BUTTON) PWRSWVCC2
PWRSW#(Input to EC)
SB_PWRBTN-(EC Output to SB)
SLP_S4#(Input to EC)
SLP_S3#(Input to EC)
ALWAYS_ON(EC Output)
MAIN_ON(PM_SLP_S3#)
V1_8_ON(SLP_S4#)
V0_9S_ON(SLP_S3#)
MAIN_PWROK(Input to EC)
+V3.3S,+V5S,
+V1.5S,+V1.05S,+V2.5S,
IMVP_ON(EC Output)
+VCC_CORE
Clock Gen Output
CK505M_CLK_EN#
IMVP_OK
PM_ICH_PWROK (EC output to ICH)
H_CPUPWRGD
SUS_STAT#
PCIRST#
PLTRST#
CPURST#
T01
G3
2
T02
G3
T03
T04
T06
S5
T08
T14
T17
T15
T24
S0
T16
1
Date:
1
Thursday, February 26, 2009
Project Name
Q10
Power ON Sequence
CZC Technology
Size
A3
Title
T23
PLUG
Adapter
T10
S3/S4/S5
Press Power Button
T49
99ms
PLUG
Main
Battery
Power On Sequence(Adapter mode)
2
S0
Sheet
41
of
Li.wang
Rev
48
B
A
B
C
D
t280
t283
t284
t287
t289
t291
S0
t294
& lt; 2ms
S5
& lt; 2ms
0ms
0ms
S5
4
G3
3
3
+V0.9S
+V2.5S
+V1.05S,+V1.5S
VT5
2
VT6
Title
VT7
CZC Technology
+V3.3S,+V5S,+V1.8S,+V1.8
+V1.5S,+V1.2SPCIE,+V1.05S,+V2.5S,+GPU_CORE
1
Sheet
Li.wang
Rev
B
C
D
5
Date:
Size
A3
1
Thursday, February 26, 2009
Project Name
Q10
Power OFF Sequence
42
of
48
A
V0_9S_ON(PM_SLP_S3#)
V1_8_ON(PM_SLP_S4#)
MAIN_ON(PM_SLP_S3#)
VT1
VT2
A
Pull out Adapter
Pull out Main Battery
+V1.8
+V5S
+V3.3S
VT3
VT4
Detail of VCC Power on
2
B
IacN
+V3.3AL,+V5AL
EC_RTC,+V5_STBY RSMRST#(Input to EC)
VDC
ALWAYS_ON(EC Output)
+V3.3S,+V5S,+V1.8S,+V1.8
+V1.5S,+V1.2SPCIE,+V1.05S,+V2.5S,+GPU_CORE
V0_9S_ON(PM_SLP_S3#)
V1_8_ON(PM_SLP_S4#)
MAIN_ON(PM_SLP_S3#)
IMVP_ON(EC Output)
MAIN_PWROK
SLP_S4#(Input to EC)
SLP_S3#(Input to EC)
PLT_RST#
SUS_STAT#
DMI Message
STPCLK#
S0
4
B
C
D
5. Power on & off Sequence;
5
A
5
4
3
Title
Blank
Date:
Size
A
2
Thursday, February 26, 2009
Project Name
Q10
ACPI Sequence
CZC Technology
1
Sheet
Li.wang
Rev
B
43
of
48
A
B
B
1
C
2
C
3
D
4
D
5
A
B
C
D
14.318MHz
PCIF
48M
PCIF5
REF
5
PCI
PCI
4
100MHz
100MHz
33MHz
48MHz
14.318MHz
100MHz
100MHz
100MHz
100MHz
96MHz
96MHz
100MHz
100MHz
100MHz
100MHz
133/166MHz
133/166MHz
133/166MHz
133/166MHz
4
ENE910
mini PCIE
card
CLK_ICHPCI
CLK_USB48
CLK_ICH14
CLK_PCIE_SATA#
CLK_PCIE_SATA
ICH7-M
CLK_PCIE_ICH#
CLK_PCIE_ICH
RTL8102E
CLK_PCIE_LAN#
CLK_PCIE_LAN
DREFCLK#
DREFCLK
DREF_SSCLK#
DREF_SSCLK
945GSE
CLK_PCIE_3GPLL#
CLK_PCIE_3GPLL
CLK_MCH_BCLK#
CLK_MCH_BCLK
CLK_CPU_BCLK#
CLK_CPU_BCLK
Diamondville
CLOCK Distribution:
REF
SRC9#
SRC9
SRC2#
SRC2
SRC3#
SRC3
SRC8#
SRC8
DOT96#
DOT96
SRC1#
SRC1
SRC10#
SRC10
CPU#
CPU
CPU#
CPU
CK410M
5
32.768KHz
12.288MHz
32.768KHz
25MHz
133/166MHz
M_CLK_DDR2/2#
M_CLK_DDR3/3#
133/166MHz
M_CLK_DDR0/0#
M_CLK_DDR1/1#
3
SODIMM0 DDRII
3
AC'97 MDC
Audio Codec
ALC650
SODIMM1 DDRII
no
no
no
Check ICH7M
no
Check
945PM/945GM/940GML
Check CPU
Check ICH7M
Check ICH7M
no
2
H_CPUPWRGD
PLT_RST#
yes
H_CPURST#
yes
CPUBUS
ADS#
yes
PCI
Frame#
yes
LPC
Frame#
ADAPTER MODE
2
yes
A3
no
no
Size
Project Name
1
44
Sheet
Check Clock chip
48
of
Check VR of Dothan CPU
Check Power Good logic
Check PWM & MOS Switch
B
Rev
Check EC output PWRBTN#
Check EC Xtal
Check TPS51020DBT
& G913C
Check RTC
Xtal & Battery
Thursday, February 26, 2009
Date:
Q10
CLOCK Title
Distribution
All Clock
yes
IMVP_PWRGD
yes
no
no
no
no
no
no
MAIN_PWROK
yes
Sytem Main
Power
Plane
yes
SLP_S4#
SLP_S3#
yes
Press
PWRSW
yes
EC XTAL
32.768K
yes
+V3.3AL
+V5AL
yes
RTCCLK
1
A
B
C
D
A
5
4
3
2
Title
Date:
Size
A4
Thursday, February 26, 2009
Project Name
Q10
Notes and Annotations
CZC Technology
1
Sheet
Blank
Li.wang
Rev
B
45
of
48
A
B
B
1
C
2
C
3
D
4
D
5
A
5
4
3
2
Title
Date:
Size
A4
Thursday, February 26, 2009
Project Name
Q10
PCB Block
CZC Technology
1
Sheet
46
of
Li.wang
Blank
Rev
B
48
A
B
B
1
C
2
C
3
D
4
D
5
3
A
History1
Q10
Sheet
47
of
Rev
B
C
D
5
Date:
Size
2
Thursday, February 26, 2009
Project Name
1
48
A
4
Title
1
A
SATAHDD
B101AW01 V3
2
B
20. (2009.2.17)
T11
CLAA101NA0ACN
3
B
C
D
4
1. MiniPCIE 4.0mm
BOSS
PCB
2.
10.1 Panel 1024X576 HSD101PFW1,CLAA101NA0ACG
3. CLK
FSB
+V1.05S
4.
EC I2Cbus
;
5. Q10
BOM
VGA P/N
DSUB03151005D 620501510002
6. Match 4.0mm MiniPCIE Boss
7.IO
30Pin
88742-3001
620903023204
8. 3GPCIE1
5.6mm MiniPCIE SLOT Alltop C15702
9. LAN 93C46
10. EC
KB910Q C1
11.KB
PCB
VERA
12. PWRBTN1
13.
OSPWRBTN2
14.
PWROKLED
15. PCB
B
R228
R231
16.
3G
MiniPCIE Ver1.2
17.
TCM
18.
Sanyo POSCAP MOSFET AOS
19.
3 Panel
VerA To VerB List
5
A
5
4
3
Title
Project Name
Q10
2
Date: Thursday, February 26, 2009
Size
A
History2
Blank
48
of
Rev
B
1
Sheet
48
A
B
B
1
C
2
C
3
D
4
D
5