https://obrazki.elektroda.pl/8092930600_1590693331_thumb.jpg Witajcie Jest to mój pierwszy post w tym dziale forum, więc proszę o wyrozumiałość :) Do napisania tego artykułu zmotywował mnie post użytkownika p.kaczmarek2, znajdujący się tutaj: https://www.elektroda.pl/rtvforum/topic3692552.html Przedstawił on działanie i budowę taniego huba USB czyli chińszczyzny, która nie imponowała ani jakością, ani rozwiązaniami konstrukcyjnymi. Niestety takiego sprzętu jest coraz więcej, a ludzie kupują tańsze i nie zwracają uwagi na droższe i lepsze urządzenia w myśl zasady "Jak działa to nie dotykaj!" W dzisiejszej prezentacji bohaterem będzie HUB TP-LINK UH720. Jest to rozdzielacz, pracujący w standardzie USB 3.0. Dodatkiem są dwa porty szybkiego ładowania i wyłącznik zasilania urządzenia. Nie będę skupiał się na testach (co nie oznacza, że żadnego nie zrobię), bo działanie huba USB jest raczej w każdym przypadku takie samo i może to być po prostu nudne. Zaczynamy! PREZENTACJA Urządzenie (a raczej jego obudowa) jest w całości wykonana z tworzywa sztucznego w kolorze czarnym. Górna powierzchnia zawierająca przycisk zasilania oraz logotyp jest gładka i błyszcząca. Nie był to dobry pomysł ze strony producenta, ponieważ na błyszczącej obudowie widać KAŻDĄ nawet najmniejszą rysę. Druga część górnej skorupy znajduje się bezpośrednio nad portami. Jest ona lekko perforowana, przez co okienka na diody LED są świetnie wkomponowane i widać je tylko wtedy gdy świecą. Zanim ktoś napisze: "Ale ten HUB to mogłeś chociaż wyczyścić...". Odpowiadam: mój egzemplarz ma trzy lata i nie wygląda już najlepiej (zarysowania), w dodatku na obudowie widać nawet najmniejsze drobiny kurzu. Czyściłem go 3 razy przed zdjęciami... Nie wyszło zbyt dobrze, ale mimo wszystko z chęcią Wam go pokażę. https://obrazki.elektroda.pl/5762058100_1590659474_thumb.jpg Od frontu widzimy 7 portów USB 3.0. Po prostu. https://obrazki.elektroda.pl/8476876300_1590674127_thumb.jpg Z tyłu (ponieważ jest to HUB aktywny) oprócz gniazda USB micro B znajduje się gniazdo zasilania 12V. https://obrazki.elektroda.pl/9823527200_1590674202_thumb.jpg Z prawej strony - miły dodatek - 2 gniazda szybkiego ładowania z maksymalnym prądem 2.4A (nie połączone magistralą z komputerem) https://obrazki.elektroda.pl/7725079400_1590674230_thumb.jpg Na dole są przyklejone dwa kawałki gumy, zabezpieczające przed ślizganiem. ELEMENTY ZESTAWU W komplecie otrzymujemy: ► Hub TP-LINK UH720 USB 3.0 ► Zasilacz ► Przewód USB 3.0 ► Instrukcja TESTY Pisząc, że nie będzie ich dużo nie kłamałem. Oto one: 1. Zasilanie pasywne, USB 3.0 Do huba udało się podłączyć: - 6 przenośnych pamięci FLASH - dodatkowy hub 2.0 - mysz - chiński czytnik kart pamięci https://obrazki.elektroda.pl/2169345500_1590677537_thumb.jpg Widok "Ten komputer": https://obrazki.elektroda.pl/4128474300_1590677598_thumb.jpg Menadżer urządzeń: https://obrazki.elektroda.pl/8509716200_1590677639_thumb.jpg Dalsze obciążanie spowodowało reset wszystkich podłączonych do huba urządzeń, a system wyświetlił stosowny komunikat: https://obrazki.elektroda.pl/3368141000_1590865546_thumb.jpg 2. Zasilanie aktywne, USB 3.0 Teraz oprócz rzeczy powyżej udało się przyłączyć dysk twardy, jedną dodatkową pamięć (mały hub 2.0 się poddał i więcej już nie zasilił) i naładować dwa telefony przez gniazda ładowania. 3. Czy hub zmniejsza prędkość transferu? Pamięć flash (testowane w USBDeview): TestZapisOdczytPróba kontrolna (pamięć bezpośrednio w porcie USB komputera)31.48 MB/s130.81 MB/sHUB bez zasilania zewnętrznego16.55 MB/s30.00 MB/sHUB z zasilaniem zewnętrznym61.94 MB/s125.17 MB/s Jeżeli do kogoś bardziej przemawiają obrazki to zapraszam :) ►próba kontrolna (pamięć bezpośrednio w porcie USB komputera): https://obrazki.elektroda.pl/3830714800_1590680946_thumb.jpg ► hub bez zasilania zewnętrznego: https://obrazki.elektroda.pl/7678603500_1590681008_thumb.jpg ► hub z zasilaniem: https://obrazki.elektroda.pl/5245005500_1590681033_thumb.jpg Dysk przenośny (testowane w HDTune): TestTransfer minimalnyTransfer maksymalnyTransfer przeciętnyPróba kontrolna (pamięć bezpośrednio w porcie USB komputera)43.7 MB/s114.7 MB/s89.2 MB/sHUB bez zasilania zewnętrznego20.5 MB/s33.1 MB/s26.0 MB/sHUB z zasilaniem zewnętrznym44.8 MB/s114.7 MB/s88.7 MB/s Wykresy prędkości transferu i szczegółowe informacje... ► próba kontrolna (pamięć bezpośrednio w porcie USB komputera): https://obrazki.elektroda.pl/5946136000_1590681088_thumb.jpg ► hub bez zasilania zewnętrznego: https://obrazki.elektroda.pl/5641282400_1590681129_thumb.jpg ► hub z zasilaniem: https://obrazki.elektroda.pl/5834212400_1590681152_thumb.jpg Wyniki testu postanowiłem pozostawić do własnej interpretacji. :D WNĘTRZE Teraz coś na co wszyscy czekali! Czas otworzyć obudowę! Otwarcie nie jest bardzo skomplikowane, ale wymaga trochę zabawy z zatrzaskami. Urządzenie otwiera się od spodu. Polecam wyposażyć się w specjalną blaszkę do otwierania - zostawia mniej śladów. Wciskamy ją w zatrzask i podważamy. Uwaga! Nie polecam wkrętaków, próbników czy noży! - zostawiają mnóstwo brzydkich śladów i zadziorów! Na szczęście zatrzaski są grube i mocne, więc przy delikatnym odpinaniu nie mają opcji się złamać. https://obrazki.elektroda.pl/7289392000_1590682439_thumb.jpg Mapa zatrzasków: https://obrazki.elektroda.pl/3358000400_1590682421_thumb.jpg Po zdjęciu skorupy ukazuje nam się płyta główna, która zapełnia całą dostępną przestrzeń. https://obrazki.elektroda.pl/1659782500_1590682762_thumb.jpg Samą płytę możemy podzielić na 4 sekcje. Oznaczyłem je literami A,B,C,D. https://obrazki.elektroda.pl/8499424200_1590683212_thumb.jpg A - sekcja zasilania B - 7 portów USB 3.0 C - porty ładowania D - obsługa portów USB Teraz rozpiszę poszczególne sekcje: Zasilanie: https://obrazki.elektroda.pl/4519397300_1590687768_thumb.jpg Zasilanie trafia na stabilizator GH15B. Jest to właściwie AZ1117 (nota w załączniku) w wersji ADJ, ustawiony rezystorami R8 i R9 (odpowiednio 10Ω i 30Ω) na 5V. Napięcie to zasila najprawdopodobniej malutki układzik U4, który wraz z tranzystorami odpowiada za włączanie i wyłączanie całego urządzenia przyciskiem monostabilnym SW1 i sterowanie diodą świecącą D1. Dookoła niej znajduje się gąbka mająca na celu zatrzymanie światła w obrębie przycisku. https://obrazki.elektroda.pl/6783590100_1590688440_thumb.jpg Następnie zasilany jest układ scalony głównej przetwornicy impulsowej zbudowanej na układzie APW8720B (nota w załączniku). Widzimy tam również cewkę, kondensatory wygładzające oraz dwa duże tranzystory MOSFET CED3172 (nota w załączniku). Przetwornica wytwarza napięcie 5V o dużym prądzie, zasilającym wszystkie porty USB. Porty USB 3.0: Ciekawostką przy nich jest to, że każdy jest zabezpieczony osobnym bezpiecznikiem. https://obrazki.elektroda.pl/3811769200_1590689193_thumb.jpg Porty ładowania: Wbrew pozorom jest to coś więcej niż port podłączony do 5V. Linie danych są kierowane do maleńkiego, ale sprytnego układu U34 oznaczonego jako 3004. Nie znalazłem o nim żadnych informacji, ale może to być coś w rodzaju TPS2513. Układ informuje ładowane urządzenie o sposobie ładowania. https://obrazki.elektroda.pl/2170684300_1590691266_thumb.jpg Link do ciekawego artykułu na ten temat tutaj Obsługa portów USB: Całość obsługują dwa układy scalone RTS5411 (nota w załączniku). Każdy z nich może obsłużyć 4 porty USB. Gdzie się więc podział ósmy port w hubie? Został wykorzystany do połączenia układów między sobą. Dlatego system operacyjny wykrywa całe urządzenie jako 2 huby. https://obrazki.elektroda.pl/1865519100_1590692623_thumb.jpg Obok każdego procesora widzimy układ w srebrnej obudowie. Jest to generator kwarcowy taktujący scalak RTS5411 zegarem o częstotliwości 12MHz. Oprócz nich możemy także dostrzec pamięć flash na interfejs SPI zawierającą oprogramowanie proceduralne (firmware). Druga kość jest na spodzie płytki. https://obrazki.elektroda.pl/4134025200_1590692164_thumb.jpg https://obrazki.elektroda.pl/7089045000_1590692726_thumb.jpg SŁOWEM ZAKOŃCZENIA Jest to naprawdę dobre urządzenie. Polecam je każdemu, kto ma trochę urządzeń USB i ograniczoną ilość portów w ulubionym urządzeniu. Pamiętajcie tylko o jego zasileniu :) Minusy? ► Fabryczny zasilacz STRASZNIE głośno piszczy i jest bardzo toporny. Niedawno wymieniłem go na mocniejszy zasilacz 12V/5A. https://obrazki.elektroda.pl/9753800300_1590693747_thumb.jpg Niestety - po tej operacji musiałem kupić i wlutować nowe gniazdo DC12V ponieważ tamto miało za mały bolec wewnątrz i nie kontaktowało. ► Przewód USB dołączony do zestawu jest dobrej jakości, ale polecam zaopatrzyć się w zapasowy, bo w moim po dwóch latach złamał się wtyk micro USB B ► obudowa strasznie się rysuje Na tym mogę już chyba zakończyć. Mam nadzieję, że ten artykuł Wam się podobał. Tak jak obiecałem - wszystkie noty są w załącznikach. Dodatkowo udostępniam plik z firmwarem dla ukadu RTS5411 (w zapisie HEX oznakowany rokiem 2015 - dostępny w Internecie jest oznaczony jako 2014). UWAGA! Nie polecam używać programów aktualizacyjnych, ponieważ są przeznaczone do aktualizacji tylko jednego układu naraz (drugi pozostanie przestarzały co może doprowadzić do licznych błędów w działaniu urządzenia). Jedyny sposób to wylutowanie obu kości i zaprogramowanie programatorem pamięci (np. CH341A). Jeżeli czegoś zapomniałem, lub popełniłem błąd - napiszcie. Pozdrawiam wszystkich czytelników!
APW8720B
Single Buck Voltage Mode PWM Controller
Features
General Description
•
Wide 5V to 12V Supply Voltage
The APW8720B is a voltage mode, fixed 300kHz switch-
•
Power-On-Reset Monitoring on VCC
•
Excellent Output Voltage Regulations
ing frequency, synchronous buck converter. The
APW8720B allows wide input voltage that is either a single
5~12V or two supply voltage(s) for various applications. A
power-on-reset (POR) circuit monitors the VCC supply
- 0.8V Internal Reference
- ±1% Over-Temperature Range
•
•
voltage to prevent wrong logic controls. A built-in soft-start
circuit prevents the output voltages from overshoot as
Integrated Soft-Start
Voltage Mode PWM Operation with External
well as limits the input current. An internal 0.8V temperature-compensated reference voltage with high accuracy
Compensation
•
Up to 90% Duty Ratio for Fast Transient Response
•
Constant Switching Frequency
is designed to meet the requirement of low output voltage applications. The APW8720B provides excellent out-
- 300kHz ±10%
•
put voltage regulations against load current variation.
The controller’ over-current protection monitors the outs
put current by using the voltage drop across the RDS(ON) of
9V Driver Voltage for BOOT Supply with Internal
Bootstrap Diode
•
low-side MOSFET, eliminating the need for a current sensing resistor that features high efficiency and low cost. In
Drive Dual Low Cost N-MOSFETs with Adaptive
Dead-Time Control
•
•
125% Over-Voltage Protection
•
Adjustable Over-Current Protection Threshold
•
Shutdown Control by COMP
•
addition, the APW8720B also integrates excellent protection functions: The over-voltage protection (OVP) , under-
50% Under-Voltage Protection
Power Good Monitoring (TDFN-10 3mmx3mm
voltage protection (UVP). OVP circuit which monitors the
FB voltage to prevent the PWM output from over-voltage,
- Using the RDS(ON) of Low-Side MOSFET
and UVP circuit which monitors the FB voltage to prevent
the PWM output from under-voltage or short-circuit.
The APW8720B is available in SOP-8P and TDFN3x3-10
packages.
Package Only)
•
SOP-8P and TDFN3x3-10 Packages
•
Lead Free and Green Devices Available
Simplified Application Circuit
(RoHS Compliant)
VCC
Applications
•
•
Wireless Lan
•
Notebook Computer
•
VCCBOOT
UGATE
COMP
PHASE
Mother Board
•
APW8720B
DSL, Switch HUB
•
VIN
LCD Monitor/TV
Graphic Cards
OFF
VOUT
ON
LGATE
FBGND
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright © ANPEC Electronics Corp.
Rev. A.5 - Mar., 2012
1
www.anpec.com.tw
Free Datasheet http://www.datasheet4u.com/
APW8720B
Ordering and Marking Information
APW8720B
Package Code
KA : SOP-8P QB : TDFN3x3-10
Operating Ambient Temperature Range
I : -40 to 85 oC
Handling Code
TR : Tape & Reel
Assembly Material
G : Halogen and Lead Free Device
Assembly Material
Handling Code
Temperature Range
Package Code
APW8720B
KA :
APW8720B
QB :
APW8720B
XXXXX
XXXXX - Date Code
APW
8720B
XXXXX
XXXXX - Date Code
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Pin Configuration
BOOT 1
UGATE 2
GND 3
LGATE/OCSET 4
BOOT
UGATE
PHASE
GND
LGATE/OCSET
8 PHASE
7 COMP
9
GND
6 FB
5 VCC
1
2
3
4
5
10
9
8
7
6
11
GND
NC
POK
COMP
FB
VCC
TDFN3x3-10
(Top View)
SOP-8P
(Top View)
Absolute Maximum Ratings (Note 1)
Parameter
Rating
Unit
VCC Supply Voltage (VCC to GND)
-0.3 ~ 16
V
BOOT Supply Voltage (BOOT to PHASE)
-0.3 ~ 16
V
Symbol
VVCC
VBOOT
BOOT Supply Voltage (BOOT to GND)
VPHASE
PHASE Voltage (PHASE to GND)
-0.3 ~ VVCC+0.3
V
-5 ~ VVCC+5
V
-0.3 ~ 16
V
& lt; 20ns
Copyright © ANPEC Electronics Corp.
Rev. A.5 - Mar., 2012
2
V
150
Maximum Junction Temperature
V
V
-0.3~VCC+0.3
POK to GND
-5 ~ 21
-0.3 ~ 7
FB and COMP to GND
TJ
V
& gt; 20ns
LGATE Voltage (LGATE to GND)
-5 ~ VBOOT+5
& lt; 20ns
VLGATE
V
& gt; 20ns
UGATE Voltage (UGATE to PHASE)
V
-0.3 ~ VBOOT+0.3
& lt; 20ns
VUGATE
-0.3 ~ 30
& gt; 20ns
°C
www.anpec.com.tw
Free Datasheet http://www.datasheet4u.com/
APW8720B
Absolute Maximum Ratings (Note 1)
Symbol
Parameter
Rating
-65 ~ 150
TSTG
TSDR
Maximum Lead Soldering Temperature, 10 Seconds
°C
260
Storage Temperature
Unit
°C
Note1: Stresses beyond those listed under " absolute maximum ratings " may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under
" recommended operating conditions " is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
Thermal Characteristics
Symbol
θJA
Parameter
Thermal Resistance -Junction to Ambient
Typical Value
Unit
(Note 2)
°C/W
SOP-8P
60
TDFN3x3-10
55
Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air.
Recommended Operating Conditions (Note 3)
Parameter
Range
Unit
VIN Supply Voltage
3.3 ~ 13.2
V
VVCC
VCC Supply Voltage
4.5 ~ 13.2
V
VOUT
Converter Output Voltage
0.8 ~ 5.5
V
IOUT
Converter Output Current
0 ~ 20
A
Symbol
VIN
TA
Ambient Temperature
-40 ~ 85
°C
TJ
Junction Temperature
-40 ~ 125
°C
Note 3: Refer to the application circuit for further information.
Electrical Characteristics
Refer to the typical application circuit. These specifications apply over VVCC = 12V, TA = -40°C to 85°C, unless otherwise
noted. Typical values are at TA = 25°C.
Symbol
Parameter
APW8720B
Test Conditions
Unit
Min.
Typ.
Max.
INPUT SUPPLY VOLTAGE AND CURRENT
VCC Supply Current (Shutdown Mode)
UGATE and LGATE open;
COMP=GND
-
-
700
µA
VCC Supply Current
UGATE and LGATE open
-
2
3
mA
Rising VCC POR Threshold
3.8
4.1
4.4
V
VCC POR Hysteresis
IVCC
0.3
0.5
0.6
V
270
300
330
kHz
-
1.5
-
V
-
-
90
%
0.792
0.8
0.808
V
-0.2
-
0.2
%
POWER-ON-RESET(POR)
OSCILLATOR
FOSC
Oscillator Frequency
∆VOSC
Oscillator Sawtooth Amplitude
DMAX
Maximum Duty Cycle
(Note 4)
(1.2V~2.7V typical)
REFERENCE
Reference Voltage
TA = -40 ~ 85°C
Converter Line/Load Regulation (Note 4)
VREF
VCC=4.5~13.2V, IOUT = 0 ~ 20A
Copyright © ANPEC Electronics Corp.
Rev. A.5 - Mar., 2012
3
www.anpec.com.tw
Free Datasheet http://www.datasheet4u.com/
APW8720B
Electrical Characteristics (Cont.)
Refer to the typical application circuit. These specifications apply over VVCC = 12V, TA = -40°C to 85°C, unless otherwise
noted. Typical values are at TA = 25°C.
Symbol
Parameter
APW8720B
Test Conditions
Unit
Min.
Typ.
Max.
-
667
-
µA/V
ERROR AMPLIFIER
gm
Transconductance (Note 4)
Open-Loop Bandwidth
(Note 4)
RL = 10kΩ, CL = 10pF
-
20
-
MHz
FB Input Leakage Current
VFB = 0.8V
-
-
0.1
µA
COMP High Voltage
RL = OPEN
-
3
-
COMP Low Voltage
RL = OPEN
-
1.5
-
Maximum COMP Source Current
VCOMP = 2V
-
200
-
Maximum COMP Sink Current
VCOMP = 2V
-
200
-
High-Side Gate Driver Source Current
VBOOT-GND= 9V, VUGATE-PHASE = 3V
-
1.0
-
High-Side Gate Driver Sink Current
VBOOT-GND= 9V, VUGATE-PHASE = 3V
-
1.1
-
Low-Side Gate Driver Source Current
VVCC = 12V, VLGATE-GND = 6V
-
1.5
-
Low-Side Gate Driver Sink Current
VVCC = 12V, VLGATE-GND = 6V
-
1.8
-
-
30
-
ns
40
45
50
%
-
2
-
µs
1
1.5
2
ms
115
125
135
%
-
5
-
%
Over-Voltage Debounce Interval
-
2
-
µs
Built-in Maximum OCP Voltage
350
-
-
mV
9
10
11
µA
150
-
-
mV
-
-
0.4
V
1
1.5
2
ms
-
0.1
1
µA
85
90
95
%
V
µA
GATE DRIVERS
TD
Dead-Time (Note 4)
A
A
PROTECTIONS
VFB_UV
FB Under-Voltage Protection Trip Point
Percentage of VREF
Under-Voltage Debounce Interval
Under-Voltage Protection Enable
Delay
VFB_OV
The same as soft -start interval
FB Over-Voltage Protection Trip Point
VFB rising
FB Over-Voltage Protection Hysteresis
VOCP_MAX
IOCSET
VROCEST
OCSET Current Source
OCP Threshold Setting Range
VOCCSET-GND Voltage, Over All
Temperature
SOFT-START
VDISABLE
TSS
Shutdown Threshold of VCOMP
Internal Soft-Start Interval
(Note 4)
POWER OK INDICATOR (POK) (ONLY FOR TDFN3X3-10 PACKAGE)
IPOK
POK Leakage Current
VPOK=5V
VFB is from low to target value
(POK Goes High)
VPOK
POK Threshold
VFB Falling, POK Goes Low
45
50
55
%
VFB Rising, POK Goes Low
120
125
130
%
1
3
5
ms
POK Delay Time
Note 4: Guaranteed by design, not production tested.
Copyright © ANPEC Electronics Corp.
Rev. A.5 - Mar., 2012
4
www.anpec.com.tw
Free Datasheet http://www.datasheet4u.com/
APW8720B
Operating Waveforms
Refer to the typical application circuit. The test condition is VIN=12V, TA=25oC unless otherwise specified.
Power On
Power Off
VIN
VIN
1
1
VOUT
VOUT
2
2
VUGATE
VUGATE
3
3
CH1: VIN, 5V/Div
CH2: VOUT, 500mV/Div
CH3: VUGATE, 10V/Div
TIME: 1ms/Div
CH1: VIN, 5V/Div
CH2: VOUT, 500mV/Div
CH3: VUGATE, 10V/Div
TIME: 2ms/Div
Enable
Shutdown
RLOAD=10Ω
VCOMP
VCOMP
1
1
VOUT
VOUT
2
2
VPHASE
VPHASE
3
3
CH1: VCOMP, 1V/Div
CH2: VOUT, 500mV/Div
CH3: VPHASE, 10V/Div
TIME: 1ms/Div
Copyright © ANPEC Electronics Corp.
Rev. A.5 - Mar., 2012
CH1: VCOMP, 1V/Div
CH2: VOUT, 500mV/Div
CH3: VPHASE, 10V/Div
TIME: 2ms/Div
5
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APW8720B
Operating Waveforms (Cont.)
Refer to the typical application circuit. The test condition is VIN=12V, TA=25oC unless otherwise specified.
Over-Current Protection
Under-Voltage Protection
OCP
OCP
OCP
VOUT
OCP
VOUT
1
1
UVP
IL
IL
2
2
CH1: VOUT, 500mV/Div
CH2: IL,10A/Div
TIME: 5ms/Div
CH1: VOUT, 500mV/Div
CH2: IL,10A/Div
TIME: 5ms/Div
UGATE Falling
1
UGATE Rising
VUGATE
1
VUGATE
VLGATE
2
2
3
VLGATE
VPHASE
VPHASE
3
CH1: VUGATE, 20V/Div
CH2: VLGATE ,10V/Div
CH3: VPHASE ,10V/Div
TIME: 50ns/Div
CH1: VUGATE, 20V/Div
CH2: VLGATE ,10V/Div
CH3: VPHASE ,10V/Div
TIME: 50ns/Div
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APW8720B
Operating Waveforms (Cont.)
Refer to the typical application circuit. The test condition is VIN=12V, TA=25oC unless otherwise specified.
Power OK
Load Transient
VOUT
1
VOUT
1
VP OK
IOUT
2
2
CH1: VOUT, 50mV/Div, AC
CH2: IOUT, 5A/Div
TIME: 200µs/Div
CH1: VOUT, 500mV/Div
CH2: VPOK, 5V/Div
TIME: 1ms/Div
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APW8720B
Pin Description
PIN
FUNCTION
NO.
NAME
SOP-8P
TDFN3x3-10
1
1
BOOT
This pin provides the bootstrap voltage to the high-side gate driver for driving the
N-channel MOSFET. An external capacitor from PHASE to BOOT, an internal
diode, and the boot supply voltage (9V), generates the bootstrap voltage for the
high-side gate driver (UGATE).
2
2
UGATE
High-side Gate Driver Output. This pin is the gate driver for high-side MOSFET.
3
4
GND
4
5
LGATE
Low-side Gate Driver Output and Over-Current Setting Input. This pin is the gate
driver for low-side MOSFET. It also used to set the maximum inductor current.
Refer to the section in “Function Description” for detail.
Power Supply Input. Connect a nominal 5V to 12V power supply voltage to this
pin. A power-on-reset function monitors the input voltage at this pin. It is
recommended that a decoupling capacitor (1 to 10µF) is connected to GND for
noise decoupling.
Signal and Power ground. Connecting this pin to system ground.
5
6
VCC
6
7
FB
7
8
COMP
8
3
PHASE
9
(Exposed Pad)
11
(Exposed Pad)
GND
Thermal Pad. Connect this pad to the system ground plan for good thermal
conductivity.
-
9
POK
POK is an open drain output used to indicate the status of the output voltage.
Connect the POK pin to 5 to 12V through a pull-high resistor.
-
10
NC
Copyright © ANPEC Electronics Corp.
Rev. A.5 - Mar., 2012
Feedback Input of Converter. The converter senses feedback voltage via FB and
regulates the FB voltage at 0.8V. Connecting FB with a resistor-divider from the
output sets the output voltage of the converter.
This is a multiplexed pin. During soft-start and normal converter operation, this pin
represents the output of the error amplifier. It is used to compensate the regulation
control loop in combination with the FB pin.
Pulling COMP low (VDISABLE = 0.4V max.) will shut down the controller. When the
pull-down device is released, the COMP pin will start to rise. When the COMP pin
rises above the VDISABLE trip point, the APW8720B will begin a new initialization
and soft-start cycle.
This pin is the return path for the high-side gate driver. Connecting this pin to the
high-side MOSFET source and connect a capacitor to BOOT for the bootstrap
voltage. This pin is also used to monitor the voltage drop across the low-side
MOSFET for over-current protection.
No Connect
8
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APW8720B
Block Diagram
VCC
9V
Sample
and
Hold
IOCSET
Regulator (10µA typical)
VREF
9V
(0.8V typical)
To LGATE
0.5
UGATE
Sense Low Side
VROCSET
UVP
Comparator
BOOT
Power-On-Reset
PHASE
VROCSET
Soft-Start
and
Fault Logic
VCC
Inhibit
Gate
Control
1.25
LGATE
OVP Comparator
Soft-start
Error Amplifier
PWM Comparator
0.9
Delay
Time
VREF
Oscillator
0.4V
FB
Disable
GND
COMP
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POK
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APW8720B
Typical Application Circuit
1. APW8720B 12V Application Circuit
VIN Supply 12V
C4
1µF
R4
2R2
APW8720B
VCC
OFF
ON
Q3
2N7002
R6
C2 10k
47nF
C1
33pF
R2
10k
C3
0.1µF
BOOT
Q1
APM2510
L1
COMP UGATE
PHASE
CIN2
220µF x 2
VOUT=1.2V
0.5µH
POK
Q2
APM2556
LGATE
FB
CIN1
1µF
ROCSET
GND
COUT
1000µF x 2
~680µF x 2
R1
1k
R3
2k
C5
10nF
R5
22
2. APW8720B 5V Application Circuit
D1
Schottky Diode
C4
1µF
R4
2R2
APW8720B
VCC
OFF
ON
Q3
2N7002
C1
33pF
R6
C2 10k
47nF
R2
10k
C3
0.1µF
BOOT
CIN1
1µF
Q1
APM2510
L1
COMP UGATE
PHASE
CIN2
220µF x 2
VOUT=1.2V
0.5µH
POK
Q2
APM2556
LGATE
FB
VIN Supply 5V
ROCSET
GND
COUT
1000µF x 2
~680µF x 2
R1
1k
R3
2k
C5
10nF
R5
22
Note: Power OK Indicator (POK) (only for TDFN3x3-10 package).
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APW8720B
Function Description
Power-On-Reset (POR)
A resistor (ROCSET), connected from the LGATE/OCSET to
The Power-On-Reset (POR) function of APW8720B con-
GND, programs the over-current trip level. Before the IC
initiates a soft-start process, an internal current source,
tinually monitors the input supply voltage (VCC) and ensures that the IC has sufficient supply voltage and can
IOCSET (10µA typical), flowing through the ROCSET develops
a voltage (VROCSET) across the ROCSET. The device holds
work well. The POR function initiates a soft-start process
while the VCC voltage just exceeds the POR threshold;
VROCSET and stops the current source IOCSET during normal
operation. When the voltage across the low-side MOSFET
the POR function also inhibits the operations of the IC
while the VCC voltage falls below the POR threshold.
exceeds the VROCSET, the APW8720B turns off the highside and low-side MOSFET,and the device will enters
hiccup mode until the over-current phenomenon is
released.
Soft-Start
The APW8720B builds in a soft-start function about
1.5ms (Typ.) interval, which controls the output voltage
For avoid large inductor current occurring in short circuit
before power on, the controller reduces internal current
rising as well as limiting the current surge at the start-up.
During soft-start, an internal ramp voltage connected to
source, Iocset, to half during soft start time.
It means that when APW8720B is in soft start interval, the
the one of the positive inputs of the error amplifier replaces the reference voltage (0.8V typical) until the ramp
internal current source, Iocset, is only 5µA (typical).
voltage reaches the reference voltage. The soft-start circuit interval is shown as figure 1. The UVP function en-
The APW8720B has an internal OCP voltage, VOCP_MAX,
and the value is 0.35V (minimum). When the ROCSET x
able delay is from t2 to t3.
I OCSET exceed 0.35V or the R OCSET is floating or not
connected, the VROCSET will be the default value 0.35V. The
Voltage(V)
POK Delay Time
over current threshold would be 0.35V across low-side
VVCC
MOSFET. The threshold of the valley inductor current-limit
is therefore given by:
OCSET count completed
OCSET count start
(OCSET duratiom, t2-t1, less than 1.3ms)
VPOK
0.9xVREF
ILIMIT =
VOUT
IOCSET × ROCSET
RDS(ON) (low − side)
For the over-current is never occurred in the normal opert0
t1 t2
t3
t4
ating load range, the variation of all parameters in the
above equation should be considered:
Time
- The RDS(ON) of low-side MOSFET is varied by temperature and gate to source voltage. Users should deter-
Figure 1. Soft-Start Interval
mine the maximum RDS(ON) by using the manufacturer’
s
datasheet.
Over-Current Protection of the PWM Converter
The over-current function protects the switching converter
- The minimum IOCSET (9µA) and minimum ROCSET should
be used in the above equation.
against over-current or short-circuit conditions. The controller senses the inductor current by detecting the drain-
- Note that the ILIMIT is the current flow through the lowside MOSFET; ILIMIT must be greater than valley inductor
to-source voltage which is the product of the inductor’
s
current and the on-resistance of the low-side MOSFET
current which is output current minus the half of inductor ripple current.
during it’ on-state. This method enhances the converter’
s
s
efficiency and reduces cost by eliminating a current sensing resistor required.
Copyright © ANPEC Electronics Corp.
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APW8720B
Function Description (Cont.)
Over-Current Protection of the PWM Converter(Cont.)
ILIMIT
Adaptive Shoot-Through Protection of the PWM Converter
The gate drivers incorporate an adaptive shoot-through
protection to prevent high-side and low-side MOSFETs
∆I
& gt; IOUT(MAX) −
2
from conducting simultaneously and shorting the input
supply. This is accomplished by ensuring the falling gate
Where ∆I = output inductor ripple current
- The overshoot and transient peak current also should
has turned off one MOSFET before the other is allowed to
rise.
be considered.
Under-Voltage Protection
During turn-off the low-side MOSFET, the LGATE voltage
is monitored until it is below 1.5V threshold, at which
The under-voltage function monitors the voltage on FB
(VFB) by Under-Voltage (UV) comparator to protect the PWM
time the UGATE is released to rise after a constant delay.
During turn-off of the high-side MOSFET, the UGATE-to-
converter against short-circuit conditions. When the VFB
falls below the falling UVP threshold (50% VREF), a fault
PHASE voltage is also monitored until it is below 1.5V
threshold, at which time the LGATE is released to rise
signal is internally generated and the device turns off highside and low-side MOSFETs. The device will enters hic-
after a constant delay.
cup mode until the under-voltage phenomenon is
released.
Power OK Indicator
The APW8720B features an open-drain POK output pin
to indicate one of the IC's working statuses including
Over-Voltage Protection (OVP) of the PWM Converter
soft-start, under-voltage fault, over-current fault.
The over-voltage protection monitors the FB voltage to
In normal operation, when the output voltage rises 90%
of its target value, the POK goes high. When the output
prevent the output from over-voltage condition. When the
output voltage rises above 125% of the nominal output
voltage outruns 50% or 125% of the target voltage, POK
signal will be pulled low immediately.
voltage, the APW8720B turns off the high-side MOSFET
and turns on the low-side MOSFET until the output voltage falls below the falling OVP threshold.
Shutdown and Enable
The APW8720B can be shut down or enabled by pulling
low the voltage on COMP. The COMP is a dual-function
pin. During normal operation, this pin represents the output of the error amplifier. It is used to compensate the
regulation control loop in combination with the FB pin.
Pulling the COMP low (VDISABLE = 0.4V maximum) places
the controller into shutdown mode which UGATE and
LGATE are pulled to PHASE and GND respectively.
When the pull-down device is released, the COMP voltage will start to rise. When the COMP voltage rises above
the VDISABLE threshold, the APW8720B will begin a new
initialization and soft-start process.
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APW8720B
Application Information
Output Voltage Selection
lower output ripple voltage. The ripple current and ripple
The output voltage can be programmed with a resistive
voltage can be approximated by:
IRIPPLE =
divider. Use 1% or better resistors for the resistive divider
is recommended. The FB pin is the inverter input of the
VIN − VOUT VOUT
×
FSW × L
VIN
where Fs is the switching frequency of the regulator.
error amplifier, and the reference voltage is 0.8V. The
output voltage is determined by:
∆VOUT = IRIPPLE x ESR
R
VOUT = 0.8 × 1 + 1
R2
A tradeoff exists between the inductor’ ripple current and
s
the regulator load transient response time. A smaller in-
R2 is the resistor connected from FB to the GND.
ductor will give the regulator a faster load transient response at the expense of higher ripple current and vice
Output Capacitor Selection
versa. The maximum ripple current occurs at the maximum input voltage. A good starting point is to choose the
Where R1 is the resistor connected from VOUT to FB and
ripple current to be approximately 30% of the maximum
output current.
The selection of COUT is determined by the required effective series resistance (ESR) and voltage rating rather than
the actual capacitance requirement. Therefore, selecting
Once the inductance value has been chosen, selecting
an inductor is capable of carrying the required peak cur-
high performance low ESR capacitors is intended for
switching regulator applications. In some applications,
rent without going into saturation. In some types of
inductors, especially core that is make of ferrite, the ripple
multiple capacitors have to be paralleled to achieve the
desired ESR value. If tantalum capacitors are used, make
current will increase abruptly when it saturates. This will
result in a larger output ripple voltage.
sure they are surge tested by the manufactures. If in doubt,
consult the capacitors manufacturer.
Compensation
Input Capacitor Selection
The input capacitor is chosen based on the voltage rat-
The output LC filter of a step down converter introduces a
double pole, which contributes with -40dB/decade gain
ing and the RMS current rating. For reliable operation,
select the capacitor voltage rating to be at least 1.3 times
slope and 180 degrees phase shift in the control loop. A
compensation network between COMP pin and ground
higher than the maximum input voltage. The maximum
RMS current rating requirement is approximately IOUT/2
should be added. The simplest loop compensation network is shown in Figure 5.
where IOUT is the load current. During power up, the input
capacitors have to handle large amount of surge current.
The output LC filter consists of the output inductor and
output capacitors. The transfer function of the LC filter is
If tantalum capacitors are used, make sure they are surge
tested by the manufactures. If in doubt, consult the ca-
given by:
GAINLC =
pacitors manufacturer.
For high frequency decoupling, a ceramic capacitor be-
The poles and zero of this transfer function are:
tween 0.1µF to 1µF can connect between VCC and ground
pin.
FLC =
Inductor Selection
1
2 × π × L × COUT
FESR =
The inductance of the inductor is determined by the out-
1
2 × π × ESR × COUT
The FLC is the double poles of the LC filter, and FESR is
the zero introduced by the ESR of the output capacitor.
put voltage requirement. The larger the inductance, the
lower the inductor’ current ripple. This will translate into
s
Copyright © ANPEC Electronics Corp.
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1 + s × ESR × COUT
s × L × COUT + s × ESR × COUT + 1
2
13
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APW8720B
Application Information (Cont.)
Compensation (Cont.)
The compensation circuit is shown in Figure 5. R2 and
C2 introduce a zero and C1 introduces a pole to reduce
L
Output
PHASE
the switching noise. The transfer function of error amplifier is given by:
COUT
1 1
//
GAIN AMP = gm × ZO = gm × R2 +
sC2 sC1
ESR
= gm ×
1
s + R2 × C2
s × s +
Figure 2. The Output LC Filter
C2 + C1
× C1
R2 × C1× C2
The pole and zero of the compensation network are:
1
FP =
C1× C2
2 × π × R2 ×
C1 + C2
1
FZ =
2 × π × R2 × C2
FLC
-40dB/dec
FESR
Gain
VOUT
-20dB/dec
Error
Amplifier
R1
FB
-
COMP
Frequency
R3
Figure 3. The LC Filter Gain & Frequency
+
R2
VREF
The PWM modulator is shown in Figure 4. The input is
the output of the error amplifier and the output is the PHASE
C1
C2
node. The transfer function of the PWM modulator is given
by:
GAINPWM =
VIN
∆VOSC
Figure 5. Compensation Network
VIN
The closed loop gain of the converter can be written as:
Driver
GAINLC × GAINPWM ×
PWM
Comparator
R3
× GAINAMP
R1 + R3
Figure 6 shows the converter gain and the following guidelines will help to design the compensation network.
VOSC
1.Select the desired zero crossover frequency FO:
Output of
Error
Amplifier
PHASE
(1/5 ~ 1/10) x FSW & gt; FO & gt; FZ
Use the following equation to calculate R2:
R2 =
Driver
∆VOSC FESR R1 + R3 FO
×
×
×
VIN
R3
gm
FLC 2
Where:
gm = 667µA/V
Figure 4. The PWM Modulator
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APW8720B
Application Information (Cont.)
where IOUT is the load current
Compensation (Cont.)
TC is the temperature dependency of RDS(ON)
FSW is the switching frequency
2. Place the zero FZ before the LC filter double poles FLC:
FZ = 0.75 x FLC
tsw is the switching interval
D is the duty cycle
Calculate the C2 by the equation:
C2 =
1
2 × π × R2 × 0.75 × FLC
Note that both MOSFETs have conduction losses while
the upper MOSFET includes an additional transition loss.
The switching internal, tsw, is the function of the reverse
transfer capacitance CRSS. Figure 7 illustrates the switch-
3. Set the pole at the half the switching frequency:
FP = 0.5xFSW
ing waveform internal of the MOSFET.
The (1+TC) term factors in the temperature dependency
Calculate the C1 by the equation:
C1 =
C2
π × R2 × C2 × FSW − 1
of the RDS(ON) and can be extracted from the “RDS(ON) vs Temperature” curve of the power MOSFET.
VDS
FZ=0.75FLC
FP=0.5FSW
Voltage across
Compensation
Gain
Gain
FLC
20.log
VIN
∆VOSC
FO
FESR
PWM &
Filter Gain
Converter
Gain
drain and source of MOSFET
20 . log(gm . R2)
Frequency
tsw
Figure 6. Converter Gain & Frequency
Figure 7. Switching Waveform Across MOSFET
MOSFET Selection
Layout Consideration
The selection of the N-channel power MOSFETs is deter-
In any high switching frequency converter, a correct lay-
mined by the RDS(ON), reverse transfer capacitance (CRSS),
and maximum output current requirement.The losses in
out is important to ensure proper operation of the
regulator. With power devices switching at 300kHz,the
the MOSFETs have two components: conduction loss and
transition loss. For the upper and lower MOSFET, the
resulting current transient will cause voltage spike across
the interconnecting impedance and parasitic circuit
losses are approximately given by the following equations:
PUPPER = I
2
OUT
Time
elements. As an example, consider the turn-off transition
of the PWM MOSFET. Before turn-off, the MOSFET is car-
(1+ TC)(RDS(ON))D + (0.5)(Iout)(VIN)(tsw)FSW
rying the full load current. During turn-off, current stops
flowing in the MOSFET and is free-wheeling by the lower
PLOWER = IOUT2 (1+ TC)(RDS(ON))(1-D)
MOSFET and parasitic diode. Any parasitic inductance of
the circuit generates a large voltage spike during the
switching interval. In general, using short and wide printed
circuit traces should minimize interconnecting imped
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APW8720B
Application Information (Cont.)
Layout Consideration (Cont.)
APW8720B
VIN
ances and the magnitude of voltage spike. And signal
and power grounds are to be kept separate till combined
using ground plane construction or single point
VCC
grounding. Figure 8. illustrates the layout, with bold lines
indicating high current paths; these traces must be short
BOOT
and wide. Components along the bold lines should be
placed lose together. Below is a checklist for your layout:
- Keep the switching nodes (UGATE, LGATE, and PHASE)
away from sensitive small signal nodes since these
L
O
A
D
UGATE
PHASE
LGATE
ROCSET
VOUT
nodes are fast moving signals. Therefore, keep traces
to these nodes as short as possible.
Close to IC
- The traces from the gate drivers to the MOSFETs (UG
and LG) should be short and wide.
Figure 8. Layout Guidelines
- Place the source of the high-side MOSFET and the drain
of the low-side MOSFET as close as possible. Minimizing the impedance with wide layout plane between the
two pads reduces the voltage bounce of the node.
- Decoupling capacitor, compensation component, the
resistor dividers, and boot capacitors should be close
their pins. (For example, place the decoupling ceramic
capacitor near the drain of the high-side MOSFET as
close as possible. The bulk capacitors are also placed
near the drain).
- The input capacitor should be near the drain of the upper MOSFET; the output capacitor should be near the
loads. The input capacitor GND should be close to the
output capacitor GND and the lower MOSFET GND.
- The drain of the MOSFETs (VIN and PHASE nodes) should
be a large plane for heat sinking.
- The ROCSET resistance should be placed near the IC as
close as possible.
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APW8720B
Package Information
SOP-8P
D
SEE VIEW A
h X 45o
E
E1
THERMAL
PAD
E2
D1
b
NX
aaa c
S
Y
M
B
O
L
0.25
A
GAUGE PLANE
SEATING PLANE
L
A1
A2
c
θ
e
VIEW A
SOP-8P
INCHES
MILLIMETERS
MIN.
MAX.
MIN.
A
MAX.
1.60
0.063
0.000
0.15
0.006
A1
0.00
A2
1.25
b
0.31
0.51
0.012
0.020
0.049
c
0.17
0.25
0.007
0.010
D
4.80
5.00
0.189
0.197
D1
2.50
3.50
0.098
0.138
E
5.80
6.20
0.228
0.244
E1
3.80
4.00
0.150
0.157
E2
2.00
3.00
0.079
0.118
0.50
0.010
0.020
0.016
0.050
0°
8°
e
h
1.27 BSC
0.25
0.050 BSC
L
0.40
1.27
θ
0°
8°
aaa
0.10
0.004
Note : 1. Followed from JEDEC MS-012 BA.
2. Dimension " D " does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion or gate burrs shall not exceed 6 mil per side .
3. Dimension " E " does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 10 mil per side.
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APW8720B
Package Information
TDFN3x3-10
D
E
A
b
Pin 1
A1
D2
A3
NX
aaa C
L
K
E2
Pin 1 Corner
e
S
Y
M
B
O
L
A
TDFN3x3-10
MILLIMETERS
INCHES
MIN.
MAX.
MIN.
MAX.
0.70
0.80
0.028
0.031
0.05
0.000
0.002
A1
A3
0.00
b
0.18
0.30
0.008 REF
0.007
0.012
D
2.90
3.10
0.114
0.122
2.70
0.087
0.106
3.10
0.114
0.122
1.75
0.055
0.069
0.50
0.016 BSC
0.012
0.020
D2
E
E2
0.20 REF
2.20
2.90
1.40
e
L
0.30
K
0.20
0.50 BSC
aaa
0.008
0.08
0.003
Note : 1. Followed from JEDEC MO-229 VEED-5.
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APW8720B
Carrier Tape & Reel Dimensions
P0
P2
P1
A
B0
W
F
E1
OD0
K0
A0
A
OD1 B
B
T
SECTION A-A
SECTION B-B
H
A
d
T1
Application
H
T1
C
d
D
330.0±
2.00
SOP-8P
A
50 MIN.
12.4+2.00
-0.00
13.0+0.50
-0.20
W
E1
1.5 MIN.
20.2 MIN.
P0
P1
P2
D0
D1
T
A0
B0
K0
1.5 MIN.
0.6+0.00
-0.40
6.40±
0.20
5.20±
0.20
2.10±
0.20
W
E1
F
12.0±
0.30 1.75±
0.10
F
5.5±
0.05
4.0±
0.10
TDFN3x3-10
2.0±
0.05
A
H
T1
C
d
D
330.0±
2.00
Application
8.0±
0.10
1.5+0.10
-0.00
50 MIN.
12.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
P0
P1
P2
D0
D1
T
A0
B0
K0
2.0±
0.05
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.40
3.30±
0.20
3.30±
0.20
1.30±
0.20
4.0±
0.10
8.0±
0.10
12.0±
0.30 1.75±
0.10
5.5±
0.05
(mm)
Devices Per Unit
Package Type
SOP-8P
TDFN3x3-10
Unit
Tape & Reel
Tape & Reel
Copyright © ANPEC Electronics Corp.
Rev. A.5 - Mar., 2012
Quantity
2500
3000
19
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Free Datasheet http://www.datasheet4u.com/
APW8720B
Taping Direction Information
SOP-8P
USER DIRECTION OF FEED
TDFN3x3-10
USER DIRECTION OF FEED
Copyright © ANPEC Electronics Corp.
Rev. A.5 - Mar., 2012
20
www.anpec.com.tw
Free Datasheet http://www.datasheet4u.com/
APW8720B
Classification Profile
Classification Reflow Profiles
Profile Feature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
3 °C/second max.
3 °C/second max.
183 °C
60-150 seconds
217 °C
60-150 seconds
See Classification Temp in table 1
See Classification Temp in table 2
Time (tP)** within 5°C of the specified
classification temperature (Tc)
20** seconds
30** seconds
Average ramp-down rate (Tp to Tsmax)
6 °C/second max.
6 °C/second max.
6 minutes max.
8 minutes max.
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
Average ramp-up rate
(Tsmax to TP)
Liquidous temperature (TL)
Time at liquidous (tL)
Peak package body Temperature
(Tp)*
Time 25°C to peak temperature
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Copyright © ANPEC Electronics Corp.
Rev. A.5 - Mar., 2012
21
www.anpec.com.tw
Free Datasheet http://www.datasheet4u.com/
APW8720B
Classification Reflow Profiles (Cont.)
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Package
Thickness
& lt; 2.5 mm
≥2.5 mm
Volume mm
& lt; 350
235 °C
220 °C
3
Volume mm
≥350
220 °C
220 °C
3
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness
& lt; 1.6 mm
1.6 mm – 2.5 mm
≥2.5 mm
Volume mm
& lt; 350
260 °C
260 °C
250 °C
3
Volume mm
350-2000
260 °C
250 °C
245 °C
3
Volume mm
& gt; 2000
260 °C
245 °C
245 °C
3
Reliability Test Program
Test item
SOLDERABILITY
HOLT
PCT
TCT
HBM
MM
Latch-Up
Method
JESD-22, B102
JESD-22, A108
JESD-22, A102
JESD-22, A104
MIL-STD-883-3015.7
JESD-22, A115
JESD 78
Description
5 Sec, 245°C
1000 Hrs, Bias @ Tj=125°C
168 Hrs, 100%RH, 2atm, 121°C
500 Cycles, -65°C~150°C
VHBM≧2KV
VMM≧200V
10ms, 1tr≧100mA
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
Copyright © ANPEC Electronics Corp.
Rev. A.5 - Mar., 2012
22
www.anpec.com.tw
Free Datasheet http://www.datasheet4u.com/