Podobno to SM pod tą płytę , patrz np. str.60
8
7
6
5
4
3
2
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
1
REV
ECN
DESCRIPTION OF REVISION
DATE
2012-05-09
SCHEM,MLB,KEPLER,2PHASE,D2
苹果笔记本维修交流群群号：３２５７４２６３４
FSB, 5/9/2012
(.csa)
D
Date
Page
Contents
TABLE_TABLEOFCONTENTS_HEAD
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
C
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
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TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
B
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
Sync
(.csa)
TABLE_TABLEOFCONTENTS_ITEM
01/13/2012
TABLE_TABLEOFCONTENTS_ITEM
01/13/2012
TABLE_TABLEOFCONTENTS_ITEM
D2_KEPLER
System Block Diagram
TABLE_TABLEOFCONTENTS_HEAD
01/13/2012
Table of Contents
D2_KEPLER
2
3
Power Block Diagram
D2_KEPLER
Revision History
D2_KEPLER
4
01/13/2012
TABLE_TABLEOFCONTENTS_ITEM
01/13/2012
TABLE_TABLEOFCONTENTS_ITEM
01/13/2012
TABLE_TABLEOFCONTENTS_ITEM
01/13/2012
BOM Configuration
TABLE_TABLEOFCONTENTS_ITEM
01/13/2012
5
TABLE_TABLEOFCONTENTS_ITEM
D2_KEPLER
6
BOM Variants
D2_KEPLER
7
Functional / ICT Test
D2_KEPLER
8
Power Aliases
D2_KEPLER
Signal Aliases
D2_KEPLER
9
01/13/2012
TABLE_TABLEOFCONTENTS_ITEM
01/13/2012
TABLE_TABLEOFCONTENTS_ITEM
01/13/2012
TABLE_TABLEOFCONTENTS_ITEM
03/05/2012
TABLE_TABLEOFCONTENTS_ITEM
03/05/2012
TABLE_TABLEOFCONTENTS_ITEM
D2_KEPLER
CPU CLOCK/MISC/JTAG
TABLE_TABLEOFCONTENTS_ITEM
01/13/2012
CPU DMI/PEG/FDI/RSVD
TABLE_TABLEOFCONTENTS_ITEM
01/13/2012
10
D2_KEPLER
11
12
CPU DDR3 INTERFACES
D2_KEPLER
13
CPU POWER
D2_KEPLER
14
CPU POWER AND GND
D2_KEPLER
16
CPU DECOUPLING-I
D2_SEAN
CPU DECOUPLING-II
D2_SEAN
17
01/13/2012
TABLE_TABLEOFCONTENTS_ITEM
01/13/2012
TABLE_TABLEOFCONTENTS_ITEM
01/13/2012
TABLE_TABLEOFCONTENTS_ITEM
03/19/2012
TABLE_TABLEOFCONTENTS_ITEM
01/13/2012
TABLE_TABLEOFCONTENTS_ITEM
03/19/2012
PCH SATA/PCIe/CLK/LPC/SPI
TABLE_TABLEOFCONTENTS_ITEM
01/13/2012
18
TABLE_TABLEOFCONTENTS_ITEM
D2_KEPLER
19
PCH DMI/FDI/PM/Graphics
D2_KEPLER
20
PCH PCI/USB/TP/RSVD
D2_KEPLER
21
PCH GPIO/MISC/NCTF
D2_KEPLER
22
PCH POWER
D2_CLEAN
23
PCH GROUNDS
D2_KEPLER
PCH DECOUPLING
D2_CLEAN
24
01/13/2012
TABLE_TABLEOFCONTENTS_ITEM
01/13/2012
TABLE_TABLEOFCONTENTS_ITEM
01/13/2012
TABLE_TABLEOFCONTENTS_ITEM
01/13/2012
TABLE_TABLEOFCONTENTS_ITEM
01/13/2012
TABLE_TABLEOFCONTENTS_ITEM
01/13/2012
CPU & PCH XDP
TABLE_TABLEOFCONTENTS_ITEM
01/13/2012
25
TABLE_TABLEOFCONTENTS_ITEM
D2_KEPLER
26
Chipset Support
D2_KEPLER
27
USB HUB & MUX
D2_KEPLER
28
CPU Memory S3 Support
D2_KEPLER
29
DDR3 SDRAM Bank A (1 OF 2)
D2_KEPLER
30
DDR3 SDRAM Bank A (2 OF 2)
D2_KEPLER
DDR3 SDRAM Bank B (1 OF 2)
D2_KEPLER
31
01/13/2012
TABLE_TABLEOFCONTENTS_ITEM
01/13/2012
TABLE_TABLEOFCONTENTS_ITEM
01/13/2012
TABLE_TABLEOFCONTENTS_ITEM
01/13/2012
TABLE_TABLEOFCONTENTS_ITEM
01/13/2012
TABLE_TABLEOFCONTENTS_ITEM
01/13/2012
TABLE_TABLEOFCONTENTS_ITEM
01/13/2012
TABLE_TABLEOFCONTENTS_ITEM
01/13/2012
TABLE_TABLEOFCONTENTS_ITEM
01/13/2012
TABLE_TABLEOFCONTENTS_ITEM
01/13/2012
TABLE_TABLEOFCONTENTS_ITEM
01/13/2012
DDR3 SDRAM Bank B (2 OF 2)
TABLE_TABLEOFCONTENTS_ITEM
01/13/2012
32
TABLE_TABLEOFCONTENTS_ITEM
D2_KEPLER
33
DDR3 Termination
D2_KEPLER
34
DDR3/FRAMEBUF VREF MARGINING
D2_KEPLER
35
X29/ALS/CAMERA CONNECTOR
D2_KEPLER
36
Thunderbolt Host (1 of 2)
D2_KEPLER
37
Thunderbolt Host (2 of 2)
D2_KEPLER
Thunderbolt Power Support
D2_KEPLER
38
44
RIO CONNECTOR
D2_KEPLER
45
SSD CONNECTOR
D2_KEPLER
46
USB 3.0 CONNECTORS
D2_KEPLER
49
SMC
D2_KEPLER
SMC Support
D2_KEPLER
50
01/13/2012
TABLE_TABLEOFCONTENTS_ITEM
03/05/2012
LPC+SPI Debug Connector
TABLE_TABLEOFCONTENTS_ITEM
01/13/2012
51
TABLE_TABLEOFCONTENTS_ITEM
D2_KEPLER
52
SMBus Connections
D2_KEPLER
53
Voltage & Load Side Current Sensing
D2_SEAN
TABLE_TABLEOFCONTENTS_ITEM
Date
Page
01/13/2012
1
1
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3
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7
8
9
10
11
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14
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25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
TABLE_TABLEOFCONTENTS_ITEM
CK
APPD
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
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67
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70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
Contents
Sync
(.csa)
03/05/2012
TABLE_TABLEOFCONTENTS_ITEM
01/13/2012
TABLE_TABLEOFCONTENTS_ITEM
D2_SEAN
Thermal Sensors
TABLE_TABLEOFCONTENTS_ITEM
01/13/2012
High Side and CPU/AXG Current Sensing
TABLE_TABLEOFCONTENTS_HEAD
03/05/2012
54
D2_SEAN
55
56
Fan Connectors
D2_KEPLER
KEYBOARD/TRACKPAD (1 OF 2)
D2_KEPLER
57
01/13/2012
TABLE_TABLEOFCONTENTS_ITEM
01/13/2012
TABLE_TABLEOFCONTENTS_ITEM
03/16/2012
TABLE_TABLEOFCONTENTS_ITEM
03/16/2012
KEYBOARD/TRACKPAD (2 OF 2)
TABLE_TABLEOFCONTENTS_ITEM
01/13/2012
58
TABLE_TABLEOFCONTENTS_ITEM
D2_KEPLER
59
DIGITAL ACCELEROMETER & GYRO
D2_KEPLER
61
SPI ROM
D2_KEPLER
62
AUDIO: CODEC/REGULATOR
D2_CARA
AUDIO: HEADPHONE FILTER
D2_CARA
63
64
03/16/2012
AUDIO: IV SENSE
D2_SEAN
KEPLER GPIOS,CLK & STRAPS
D2_SEAN
KEPLER PEX PWR/GNDS
D2_SEAN
GFX IMVP VCore Regulator
01/13/2012
TABLE_TABLEOFCONTENTS_ITEM
D2_SEAN
KEPLER EDP/DP/GPIO
D2_KEPLER
D2_SEAN
GDDR5 Frame Buffer B
D2_SEAN
SMC12 SENSORS EXTENDED
D2_SEAN
GDDR5 Frame Buffer A
03/05/2012
DEBUG SENSORS AND ADC
132
D2_SEAN
1V05 GPU / 1V35 FB POWER SUPPLY
01/13/2012
D2_SEAN
KEPLER FRAME BUFFER I/F
D2_KEPLER
130
D2_KEPLER
KEPLER CORE/FB POWER
PCB Rule Definitions
03/15/2012
D2_KEPLER
KEPLER PCI-E
D2_CLEAN
109
D2_KEPLER
Power Control 1/ENABLE
Project Specific Constraints
01/13/2012
D2_KEPLER
Power FETs
D2_KEPLER
108
D2_KEPLER
Misc Power Supplies
GPU (Kepler) CONSTRAINTS
01/13/2012
107
D2_SEAN
CPU VCCIO (1V0R1V05 S0) POWER SUPPLY
D2_KEPLER
D2_SEAN
CPU IMVP7 & AXG VCore Output
D2_KEPLER
D2_KEPLER
CPU IMVP7 & AXG VCore Regulator
01/13/2012
Thunderbolt Constraints
SMC Constraints
106
D2_KEPLER
1V5R1V35V DDR3 SUPPLY
01/13/2012
D2_KEPLER
5V / 3.3V Power Supply
D2_KEPLER
105
D2_KEPLER
System Agent Supply
D2_KEPLER
PCH Constraints 2
D2_KEPLER
PBus Supply & Battery Charger
PCH Constraints 1
103
D2_CARA
DC-In & Battery Connectors
01/13/2012
D2_CARA
AUDIO: JACK TRANSLATORS
102
D2_CARA
AUDIO: JACK
Sync
D2_CARA
AUDIO: SPEAKER AMP
Contents
D2_CARA
AUDIO: IV SENSE FILTER
91
92
93
94
95
96
97
98
99
D
Date
Page
D2_SEAN
65
03/16/2012
66
03/16/2012
67
03/16/2012
68
03/16/2012
69
01/13/2012
70
01/13/2012
71
C
01/13/2012
72
01/13/2012
73
01/13/2012
74
03/05/2012
75
03/05/2012
76
01/13/2012
77
01/13/2012
78
01/13/2012
79
01/13/2012
80
01/13/2012
81
03/05/2012
82
03/05/2012
83
03/05/2012
84
03/05/2012
85
03/05/2012
86
03/05/2012
87
03/05/2012
88
03/05/2012
89
B
03/05/2012
90
01/13/2012
eDP Display Connector
D2_KEPLER
eDP Mux
D2_SEAN
eDP Muxed Graphics Support
D2_SEAN
Thunderbolt Connector A
D2_KEPLER
Thunderbolt Connector B
D2_KEPLER
91
03/05/2012
92
03/05/2012
94
01/13/2012
96
01/13/2012
97
01/13/2012
LCD Backlight Driver (LP8545)
D2_KEPLER
PCH VCCIO (1.05V) POWER SUPPLY
D2_KEPLER
Power Sequencing EG/PCH S0
D2_KEPLER
CPU Constraints
D2_KEPLER
Memory Constraints
D2_KEPLER
98
01/13/2012
99
01/13/2012
100
01/13/2012
101
01/13/2012
TABLE_TABLEOFCONTENTS_ITEM
苹果笔记本维修交流群群号：３２５７４２６３４
A
A
DRAWING TITLE
SCHEM,MLB,KEPLER,2PHASE,D2
DRAWING NUMBER
Schematic / PCB #’s
PART NUMBER
QTY
Apple Inc.
DESCRIPTION
REFERENCE DES
CRITICAL
051-9589
1
SCHEM,MLB,KEPLER_2PHASE,D2
SCH
1
PCBF,MLB,KEPLER_2PHASE,D2
PCB
R
NOTICE OF PROPRIETARY PROPERTY:
CRITICAL
820-3332
BOM OPTION
CRITICAL
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
DRAWING
TITLE=MLB
ABBREV=ABBREV
LAST_MODIFIED=Wed May
9 13:50:52 2012
8
7
6
051-9589
REVISION
5
4
3
2
4.18.0
BRANCH
PAGE
1 OF 132
SHEET
1 OF 99
1
SIZE
D
8
7
6
5
4
J2500,J2550
GRAPHICS
2
1
苹果笔记本维修交流群群号：３２５７４２６３４
INTEL CPU
U8000
3
XDP CONN
2.X GHZ
PG 23
AMD WHISTLER
IVY BRIDGE
J2900
PG 9
PG 73
J3100
2 DIMMS
DDR3-1067/1333MHZ
DIMM
D
J6950
D
PG 26,28
DC/BATT
POWER SUPPLY
PG 63
GPIO
FDI
DMI
RTC
PG 19
PG 17
PG 17
PG 16
U4900
U6100
SPI
TEMP SENSOR
Boot ROM
CLOCK
U2700
Misc
CK5G05
PG 55
PG 44
CLK
PG 19
POWER SENSE
BUFFER
PG 24
PG 44
PG 16
J5650,5660
FAN CONN AND CONTROL
SPI
5
J4501
PG 51
SATA2.0/3(GB/S)
PG 16
4
CONN
SATA2.0/3(GB/S)
3
ODD SATA
SATA2.0/3(GB/S)
PG 41
INTEL
SATA
J5100
2
1
PG 46
ADC
BSB
Fan
SMC
PG 44
U4900
C
PG 16
SATA3.0/6(GB/S)
0
CONN
LPC
MOBILE
SATA2.0/3(GB/S)
B,0
Prt
Port80,serial
PG 16
HDD SATA
C
Ser
LPC + SPI CONN
PANTHER-POINT
J4500
SATA3.0/6(GB/S)
U1800
PG 41
J3402
U3600
PWR
CAMERA
PG 31
CTRL
DP OUT
J4501
IR
USB
PG 17
U9320
PG 41
RGB OUT
HUB 2
DP MUX
PG 84
9 10 11 12 13
33
8
7
U3700
J5713
TRACKPAD/KEYBOARD
PG 53
USB
J3401
BLUETOOTH
PG 31
HUB 1
2
PCI
(RESERVATION) PG
6
PG 18
MINI DP PORT
PG 18
USB
TMDS OUT
J9400
(UP TO 14 DEVICES)
LVDS OUT
PG 33
EXTERNAL C
PG 33
5
DVI OUT
4
PG 83
EXTERNAL B
3
HDMI OUT
XP25-5G
J4610
1
PG 18
0
J4600
EXTERNAL A
U9370
PG 34
PG 34
B
B
JTAG
SMB
DDC MUX
SMBUS
PG 16
PG 16
PG 83
CONNECTION
PCI-E
PG 47
HDA
PEG
(UP TO 16 LINES)
PG 16
PG 16
PG 16
DIMM
LCD PANEL
PG 26,28
U9600
U6201
AUDIO
GMUX
CODEC
PG 86
PG 56
苹果笔记本维修交流群群号：３２５７４２６３４
U6610,6620,6630
U4100
U3900
A
GB
FW643
LINE TIN
E-NET
J3401
HEADPHONE
SPEATKER
FILTER
AMP
PG 58
FILTER
PG 59
SYNC_MASTER=D2_KEPLER
PG 38
PG 57
System Block Diagram
PG 36
AirPort
DRAWING NUMBER
PG 31
J4310
J4000
Apple Inc.
J3500
E-NET
SDCARD READER
CONN
CONN
CONN
PG 37
NOTICE OF PROPRIETARY PROPERTY:
AUDIO
SPEATKER
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
PG 37
PG 63
PG 60
7
6
4.18.0
J6700,J6750
CONN
PG 40
051-9589
REVISION
R
FIREWIRE
8
SYNC_DATE=01/13/2012
PAGE TITLE
BCM57765
5
4
3
2
BRANCH
PAGE
2 OF 132
SHEET
2 OF 99
1
SIZE
D
A
苹果笔记本维修交流群群号：３２５７４２６３４
8
7
6
5
3
2
1
D6990
D2 POWER SYSTEM ARCHITECTURE
PP18V5_DCIN_CONN
4
SMC PWRGD
SMC_RESET_L
NCP303LSN
U5000
(PAGE 45)
R6990
ENABLE
PPBUS_G3H
SMC AVREF SUPPLY
3.425V G3HOT
PP3V3_S5_AVREF_SMC
PP3V42_G3H
PM6640
SMC_PBUS_VSENSE
VIN
U6990
J6900
V
F7040
D
VOUT
PP3V3_S5_SMC
(PAGE 45)
Q5315
SMC_TPAD_RST_L
D
PPBUS_G3H
F6905
6A FUSE
AC
(PAGE 62)
REF3333
SMC_ONOFF_L
R7020
U5001
DCIN(16.5V)
8A FUSE
A
ADAPTER
U7000
PPVBAT_G3H
VIN
VIN
VOUT
IN
PP5V_S3_GFXIMVP6_VDD
VDD
ISL6259HRTZ
SMC_DCIN_ISENSE
V
A
VOUT
R7640
SMC_GPU_VSENSE
PPVCORE_GPU
PP5V_S0_CPUVTTS0
VIN
1.05V
GPU VCORE
ISL6263C
A
R7050
SMC_GPU_ISENSE
CPUVTTS0_EN
VR_ON
SMC_BATT_ISENSE
TPS22924
U4202
CPUVTTS0_PGOOD
U8900
SMC_RESET_L
SMC_CPU_FSB_ISENSE
ISL95870
U7600
U5410
PBUS SUPPLY/
BATTERY CHARGER
PPCPUVTT_S0
A
VOUT
PGOOD
EN
EN
PGOOD
(PAGE 70)
GPUVCORE_PGOOD
GPUVCORE_EN
FW_PWR_EN
(PAGE 82)
(PAGE 64)
PP1V0_FW_FWPHY
(PAGE 39)
SMC_CPU_VSENSE
J6950
PPVBAT_G3H_CHGR_R
CPU VCORE
SMC_CPU_HI_ISENSE
A
(9 TO 12.6V)
3S2P
V
R5388/U5388
Q7055
PPVBATT_G3H_CONN
A
VOUT
VIN
PANTHER_POINT
SMC_CPU_ISENSE
SYS_RERST#
U7400
CPUIMVP7_VR_ON
VR_ON
RSMRST#
CPUIMVP7_AXG_PGOOD
PGOOD
ACPRESENT
(PAGE 67)
www.qdzbwx.com
PM_PCH_PWRGD
PLT_RERST_L
PS_PWRGD
PLTRST#
CPU_PWRGD
U1800
C
GMUX
PB16B
PROCPWRGD
PM_MEM_PWRGD
U9600
PB17B
EG_RAIL2_EN
P3V3GPU_EN
EG_RAIL3_EN
B
DRAMPWROK
U5440
PB17A
C
SMC_ADAPTER_EN
P1V1GPU_EN
EG_RAIL1_EN
PM_PWRBTN_L
PWRBTN#
ISL95831
CHGR_BGATE
PPVCORE_S0_CPU
U2850
GPUVCORE_EN
PP5V_S3_DDRREG
(PAGE 16~21)
SMC_CPU_DDR_VSENSE
R7350
XP25-5
PB18A
EG_RAIL4_EN
S5
P1V0GPU_EN
(PAGE 86)
EN1
PPDDR_S3_REG
VOUT1
DDRVTT_EN
VOUT1
S3
R5413
1.003V(L/H)
A
VOUT2
EN2
1.503V(R/H)
0.75V
PP1V5_S3
A
PP1V0_S0GPU_REG
VIN
P1V5FB_EN
SMC
VLDOIN
1.5V
DDRREG_EN
PM_ALL_GPU_PGOOD
PL32A
V
SMC_DDR_ISENSE
VIN
PPVTT_S0_DDR_LDO
VOUT2
SM_DRAMPWROK
CPU
PP1V5_GPU_REG
TPS51116
U7300
SMC_GPU_1V8_ISENSE
DDRREG_PGOOD
4.5V
VIN MAX8840
EN
U6200
PGOOD
(PAGE 66)
U4900
ISL6236
RC
P60
(PAGE 85)
DELAY
SMC_PM_G2_EN
P1V0GPU_PGOOD
POK1
U1000
PP3V3_S0
U9500
P3V3S5_EN
PP4V5_AUDIO_ANALOG
PP1V5_S3
P1V5FB_PGOOD
POK2
VCCCPUPWRGD
VOUT
(PAGE 9~14)
RESET*
Q7860
Q7801
P1V5CPU_EN
(PAGE 44)
PP5V_S0
VIN
ON
PP1V5_S3RS0
G
SLG5AP020
U7801
VIN
P5VS3_EN
EN1
PANTHER-POINT
VREG5
5V
VOUT1
PP5V_S3
P5VS0_EN
P1V5S0FET_GATE
PM_ALL_GPU_PGOOD
(L/H)
MOBILE
PP3V3_S5
PM_SLP_S5_L
P3V3S5_EN
SLP_S5#(E4)
EN2
Q9806
B
3.3V
PP3V3_S5
VOUT2
U7980
RC
TPS51125
U7201
P5VS3_EN
P1V8FB_EN
BKLT_PLT_RST_L
& &
LCD_BKLT_NO
DDRREG_EN
DELAY
U1800
PWRGD(P12)
PP1V8_GPUIFPX
(P64)
G
SLG5AP020
U7880
RSMRST_PWRGD
RSMRST_OUT(P15)
CPUIMVP_VR_ON
P3V3GPU_EN
IMVP_VR_ON(P16)
PM_SYSRST_L
Q7810
SYSRST(PA2)
U9701
ENA
PM_RSMRST_L
99ms DLY
PWR_BUTTON(P90)
VIN
LP8550
BKLT_EN
RSMRST_IN(P13)
SMC_ONOFF_L
P1V8GPUIFPXFET_GATE
P5V3V3_PGOOD
P3V3S3_EN
VIN
ON
PP3V3_S0GPU
(PAGE 65)
PGOOD
RC
ALL_SYS_PWRGD
Q7880
Q7870
DELAY
SMC
PP1V8_S0
(R/H)
VOUT
PP3V3_S3
PPVOUT_S0_LCDBKLT
Q7922
PP3V3_ENET
PP3V3_S0_PWRCTL
PM_PWRBTN_L
P17(BTN_OUT)
(PAGE 87)
PM_SLP_S4_L
P1V8S0_PGOOD
PM_SLP_S5_L
SLP_S4#(H7)
SLP_S5_L(P95)
P3V3S3_EN
P5V3V3_PGOOD
PM_SLP_S3_L & & WOL_EN||SMC_ADAPTER_EN
Q4260
U4201
PP3V3_S0_FET
RES*
SLP_S4_L(P94)
TPS22924
PFWBOOST
SLP_S3#(P12)
SMC_RESET_L
PM_SLP_S4_L
Q7830
PM_SLP_S3_L
S0PGOOD_PWROK
PP3V3_FW_FWPHY
PM_SLP_S3_L
SLP_S3_L(P93)
H8S2117
(PAGE 39)
(PAGE 16~21)
EN
U4900
(PAGE 45)
PP3V3_S0
P3V3S0_EN
FW_PWR_EN
SMC_ADAPTER_EN & & PM_SLP_S3_L
VCC
PP3V3_S0
R7978
V2MON
U7971
ISL8014A
EN
A
RC
V4MON (PAGE
Q7850
PP1V2_S0
TRST = 200mS
SYNC_MASTER=D2_KEPLER
SYNC_DATE=01/13/2012
PAGE TITLE
Power Block Diagram
P3V3S0_EN
P1V2S0_EN
VIN
P1V2ENET_EN
CPUVTTS0_EN
DELAY
ISL8014A
U7760
(PAGE 70)
VOUT
PGOOD
DRAWING NUMBER
PP1V2_ENET
Apple Inc.
P1V2ENET_PGOOD
PBUSVSENS_EN
NOTICE OF PROPRIETARY PROPERTY:
P1V5CPU_EN
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
7
6
5
051-9589
REVISION
R
DELAY
8
苹果笔记本维修交流群群号：３２５７４２６３４
72)
P1V2S0_EN
EN
RC
RST*
PP1V05_S0
P1V8S0_PGOOD
P5VS0_EN
DELAY
RC
PGOOD
V3MON
P1V8S0_EN
DELAY
RC
PP1V8_S0
VOUT
U7720
(PAGE 70)
ISL88042IRTJJZ
PP1V5_S0
VIN
P1V8_S0_EN
PM_SLP_S3_L_R
4
3
2
4.18.0
BRANCH
PAGE
3 OF 132
SHEET
3 OF 99
1
SIZE
D
A
8
7
6
5
4
3
2
1
D
D
C
C
B
B
A
SYNC_MASTER=D2_KEPLER
SYNC_DATE=01/13/2012
PAGE TITLE
Revision History
DRAWING NUMBER
Apple Inc.
051-9589
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
4.18.0
BRANCH
PAGE
4 OF 132
SHEET
4 OF 99
1
SIZE
D
A
8
7
6
5
BOM Variants (continued on CSA 6)
4
3
2
Bar Code Labels / EEEE #’s (continued on CSA 6)
1
Alternate Parts
TABLE_BOMGROUP_HEAD
BOM NUMBER
BOM NAME
TABLE_ALT_HEAD
PART NUMBER
BOM OPTIONS
QTY
DESCRIPTION
REFERENCE DES
CRITICAL
BOM OPTION
PART NUMBER
ALTERNATE FOR
PART NUMBER
128S0257
BOM OPTION
REF DES
COMMENTS:
128S0264
ALL
Kemet alt to Sanyo
353S3527
353S3528
ALL
Pericom eDP MUX
353S3526
353S3528
ALL
TI eDP MUX
376S0855
376S0613
ALL
Diodes alt to Toshiba
376S0855
376S0613
ALL
Diodes alt to Toshiba
376S1076
376S0634
ALL
Diodes alt to On Semi
376S0903
376S0796
ALL
Fairchild alt to Siliconix
376S0977
376S0859
ALL
Diodes alt to Toshiba
376S1053
376S0604
ALL
Diodes alt to Fairchild
128S0311
128S0329
ALL
NEC alt to Sanyo
138S0739
138S0706
ALL
Samsung alt to Murata
197S0434
197S0343
ALL
Epson Alt to TXC
197S0435
197S0343
ALL
NDK Alt to TXC
197S0432
197S0431
ALL
NDK Alt to Epson
197S0452
197S0181
ALL
Epson Alt to TXC
197S0453
197S0181
ALL
NDK Alt to TXC
685-0017
685-0016
ALL
Sanyo POSCAP/Mylar alt to Kemet
376S0975
376S1081
ALL
Toshiba alt to diodes
371S0709
371S0652
ALL
NXP alt to infineon
371S0713
371S0558
ALL
DDS alt to ST
377S0126
377S0066
ALL
New Semtech package
377S0147
377S0066
ALL
On Semi alt to Semtech
152S0461
152S1645
ALL
Cyntec alt to Vishay
376S1080
376S0820
ALL
Diodes alt to On Semi
155S0667
155S0583
ALL
Panasonic alt to TDK
TABLE_BOMGROUP_ITEM
085-3726
D2,MLB,KEPLER,DEV
D2_DEVEL:ENG
085-4776
D2,MLB,KEPLER,FSB DEV
D2_DEVEL:FSB
825-7563
607-9546
D2,MLB,KEPLER_2PHASE,COMMON
D2_COMMON,POSCAP_MYLAR_PAIR
685-0016
PBUS PAIR,KEMET POSCAP,TALL MYLAR,D2
PBUS_CAP:KEMET
685-0017
PBUS PAIR,SANYO POSCAP,SHORT MYLAR,D2
PBUS_CAP:SANYO
639-3378
PCBA,2.3G,8G_HYN,VRAM_HYN,MLB_KEPLER,D2,DY3V
BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_HYNIX_A_DIE,EEEE:DY3V,DEVEL_BOM,RAM_2G_HYNIX_1600
639-3379
PCBA,2.3G,8G_HYN,VRAM_SAM,MLB_KEPLER,D2,DY3W
BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_SAMSUNG,EEEE:DY3W,DEVEL_BOM,RAM_2G_HYNIX_1600
639-3380
PCBA,2.3G,8G_SAM,VRAM_HYN,MLB_KEPLER,D2,DY3Y
BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_HYNIX_A_DIE,EEEE:DY3Y,DEVEL_BOM,RAM_2G_SAMSUNG_1600
1
LABEL,MLB/LIO,MBA
[EEEE:DY3V]
CRITICAL
EEEE:DY3V
825-7563
1
LABEL,MLB/LIO,MBA
[EEEE:DY3W]
CRITICAL
EEEE:DY3W
825-7563
1
LABEL,MLB/LIO,MBA
[EEEE:DY3Y]
CRITICAL
EEEE:DY3Y
825-7563
1
LABEL,MLB/LIO,MBA
[EEEE:DY40]
CRITICAL
EEEE:DY40
825-7563
1
LABEL,MLB/LIO,MBA
[EEEE:DY43]
CRITICAL
EEEE:DY43
825-7563
1
LABEL,MLB/LIO,MBA
[EEEE:DY44]
CRITICAL
EEEE:DY44
825-7563
1
LABEL,MLB/LIO,MBA
[EEEE:DY45]
CRITICAL
EEEE:DY45
825-7563
1
LABEL,MLB/LIO,MBA
[EEEE:DY4C]
CRITICAL
EEEE:DY4C
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
TABLE_ALT_ITEM
VREFDQ:M1_M3
TABLE_BOMGROUP_ITEM
D
TABLE_ALT_ITEM
D
TABLE_BOMGROUP_ITEM
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
639-3381
PCBA,2.3G,8G_SAM,VRAM_SAM,MLB_KEPLER,D2,DY40
BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_SAMSUNG,EEEE:DY40,DEVEL_BOM,RAM_2G_SAMSUNG_1600
639-3384
PCBA,2.3G,16G_HYN,VRAM_HYN,MLB_KEPLER,D2,DY43
BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_HYNIX_A_DIE,EEEE:DY43,DEVEL_BOM,RAM_4G_HYNIX_1600
639-3385
PCBA,2.3G,16G_HYN,VRAM_SAM,MLB_KEPLER,D2,DY44
BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_SAMSUNG,EEEE:DY44,DEVEL_BOM,RAM_4G_HYNIX_1600
639-3386
PCBA,2.3G,16G_SAM,VRAM_HYN,MLB_KEPLER,D2,DY45
BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_HYNIX_A_DIE,EEEE:DY45,DEVEL_BOM,RAM_4G_SAMSUNG_1600
639-3387
PCBA,2.3G,16G_SAM,VRAM_SAM,MLB_KEPLER,D2,DY4C
BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_SAMSUNG,EEEE:DY4C,DEVEL_BOM,RAM_4G_SAMSUNG_1600
639-2821
PCBA,2.6G,8G_HYN,VRAM_HYN,MLB_KEPLER,D2,DRF1
BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_HYNIX_A_DIE,EEEE:DRF1,DEVEL_BOM,RAM_2G_HYNIX_1600
639-2825
PCBA,2.6G,8G_HYN,VRAM_SAM,MLB_KEPLER,D2,DRF4
BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_SAMSUNG,EEEE:DRF4,DEVEL_BOM,RAM_2G_HYNIX_1600
639-2817
PCBA,2.6G,8G_SAM,VRAM_HYN,MLB_KEPLER,D2,DRDN
BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_HYNIX_A_DIE,EEEE:DRDN,DEVEL_BOM,RAM_2G_SAMSUNG_1600
639-2815
PCBA,2.6G,8G_SAM,VRAM_SAM,MLB_KEPLER,D2,DRDW
BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_SAMSUNG,EEEE:DRDW,DEVEL_BOM,RAM_2G_SAMSUNG_1600
639-2979
PCBA,2.6G,16G_HYN,VRAM_HYN,MLB_KEPLER,D2,DT9H
BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_HYNIX_A_DIE,EEEE:DT9H,DEVEL_BOM,RAM_4G_HYNIX_1600
639-2980
PCBA,2.6G,16G_HYN,VRAM_SAM,MLB_KEPLER,D2,DT9D
BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_SAMSUNG,EEEE:DT9D,DEVEL_BOM,RAM_4G_HYNIX_1600
639-2981
PCBA,2.6G,16G_SAM,VRAM_HYN,MLB_KEPLER,D2,DT9F
825-7563
BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_HYNIX_A_DIE,EEEE:DT9F,DEVEL_BOM,RAM_4G_SAMSUNG_1600
1
LABEL,MLB/LIO,MBA
[EEEE:DRF1]
CRITICAL
EEEE:DRF1
825-7563
1
LABEL,MLB/LIO,MBA
[EEEE:DRF4]
CRITICAL
EEEE:DRF4
825-7563
1
LABEL,MLB/LIO,MBA
[EEEE:DRDN]
CRITICAL
EEEE:DRDN
825-7563
1
LABEL,MLB/LIO,MBA
[EEEE:DRDW]
CRITICAL
EEEE:DRDW
825-7563
1
LABEL,MLB/LIO,MBA
[EEEE:DT9H]
CRITICAL
EEEE:DT9H
825-7563
1
LABEL,MLB/LIO,MBA
[EEEE:DT9D]
CRITICAL
EEEE:DT9D
825-7563
1
LABEL,MLB/LIO,MBA
[EEEE:DT9F]
CRITICAL
EEEE:DT9F
825-7563
1
LABEL,MLB/LIO,MBA
[EEEE:DT9G]
CRITICAL
EEEE:DT9G
825-7563
1
LABEL,MLB/LIO,MBA
[EEEE:F0HN]
CRITICAL
EEEE:F0HN
825-7563
1
LABEL,MLB/LIO,MBA
[EEEE:F0HR]
CRITICAL
EEEE:F0HR
825-7563
1
LABEL,MLB/LIO,MBA
[EEEE:DYW4]
CRITICAL
EEEE:DYW4
825-7563
1
LABEL,MLB/LIO,MBA
[EEEE:F0HV]
CRITICAL
EEEE:F0HV
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
639-2982
PCBA,2.6G,16G_SAM,VRAM_SAM,MLB_KEPLER,D2,DT9G
BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_SAMSUNG,EEEE:DT9G,DEVEL_BOM,RAM_4G_SAMSUNG_1600
639-3618
PCBA,2.7G,8G_HYN,VRAM_HYN,MLB_KEPLER,D2,F0HN
BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_HYNIX_A_DIE,EEEE:F0HN,DEVEL_BOM,RAM_2G_HYNIX_1600
639-3619
PCBA,2.7G,8G_HYN,VRAM_SAM,MLB_KEPLER,D2,F0HR
BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_SAMSUNG,EEEE:F0HR,DEVEL_BOM,RAM_2G_HYNIX_1600
639-3561
PCBA,2.7G,8G_SAM,VRAM_HYN,MLB_KEPLER,D2,DYW4
BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_HYNIX_A_DIE,EEEE:DYW4,DEVEL_BOM,RAM_2G_SAMSUNG_1600
639-3620
PCBA,2.7G,8G_SAM,VRAM_SAM,MLB_KEPLER,D2,F0HV
BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_SAMSUNG,EEEE:F0HV,DEVEL_BOM,RAM_2G_SAMSUNG_1600
639-3627
PCBA,2.7G,16G_HYN,VRAM_HYN,MLB_KEPLER,D2,F0HM
BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_HYNIX_A_DIE,EEEE:F0HM,DEVEL_BOM,RAM_4G_HYNIX_1600
639-3562
PCBA,2.7G,16G_HYN,VRAM_SAM,MLB_KEPLER,D2,DYW5
825-7563
1
LABEL,MLB/LIO,MBA
[EEEE:F0HM]
CRITICAL
EEEE:F0HM
825-7563
1
LABEL,MLB/LIO,MBA
[EEEE:DYW5]
CRITICAL
EEEE:DYW5
825-7563
1
LABEL,MLB/LIO,MBA
[EEEE:F0HY]
CRITICAL
EEEE:F0HY
825-7563
1
LABEL,MLB/LIO,MBA
[EEEE:F0HT]
CRITICAL
EEEE:F0HT
BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_SAMSUNG,EEEE:DYW5,DEVEL_BOM,RAM_4G_HYNIX_1600
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
C
TABLE_ALT_ITEM
C
TABLE_BOMGROUP_ITEM
Programmables
TABLE_BOMGROUP_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
341S3584
1
IC,TRKPD/KYBD CNTRLR,DVB,D2
U5701
CRITICAL
TPAD_PSOC:PROG
107S0232
107S0129
ALL
Cyntec alt to TFT
337S2983
1
IC,TP PSOC,QFN,BLANK
U5701
CRITICAL
TPAD_PSOC:BLANK
197S0466
197S0464
ALL
Epson alt to NDK
341S3597
1
IC,EEPROM,CACTUS RIDGE (8.1) FSB,D2
U3690
CRITICAL
TBTROM:PROG
341S3564
341S3565
ALL
Avnet eDP MUX alt to Renesas
335S0865
1
EEPROM,256KBIT,SPI,5MHZ,1.8V,2X3QFN
U3690
CRITICAL
TBTROM:BLANK
335S0852
1
IC,GPU ROM,D2,BLANK
U8701
CRITICAL
GPUROM:BLANK
341S3565
1
IC,EDP MUX-95C, (RENESAS) V3.2.8,DVB,D2
U9100
CRITICAL
DPMUXMCU:PROG
337S4313
1
IC,MCU,H8S/2113,9X9MM,TLP-145V
U9100
CRITICAL
DPMUXMCU:BLANK
TABLE_BOMGROUP_ITEM
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
639-3628
PCBA,2.7G,16G_SAM,VRAM_HYN,MLB_KEPLER,D2,F0HY
BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_HYNIX_A_DIE,EEEE:F0HY,DEVEL_BOM,RAM_4G_SAMSUNG_1600
639-3629
PCBA,2.7G,16G_SAM,VRAM_SAM,MLB_KEPLER,D2,F0HT
BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_SAMSUNG,EEEE:F0HT,DEVEL_BOM,RAM_4G_SAMSUNG_1600
TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
BOM Groups
TABLE_BOMGROUP_HEAD
BOM GROUP
BOM OPTIONS
D2_COMMON
ALTERNATE,COMMON,D2_COMMON1,D2_COMMON2,D2_PROGPARTS,D2_PVB
D2_COMMON1
CPUMEM_S0,SMC_DEBUG_YES,DPMUX:HOCO,TBTRTR:PRQ,TBTBST:Y,TBTHV:P15V,HUB_2NONREM,USBHUB2512B,SPEAKERID,SMC_PACKAGE:PROD,SKIP_5V3V3:AUDIBLE,CHGR_5V:LDO,P1V5S0:LDO
D2_COMMON2
EDP:YES,MIKEY,PPCPUVCCIO:IVB,PPDDR:1V35,LPCPLUS_CONN:YES,LPCPLUS_R:YES,KBD_BL:SANDWICH,CAPS:INT,BTPWR:S4,XDP,XDP_CPU:BPM,GPU:2P,TPAD_5V:LDO_S5
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
DRAM VREF Configs
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_HEAD
BOM GROUP
BOM OPTIONS
TABLE_BOMGROUP_ITEM
D2_PVB
VREF:PROD,D_BKL:PROD,SENSOR_NONPROD:N
D2_PROGPARTS
SMC_PROG:FSB,BOOTROM_PROG:FSB,DPMUXMCU:PROG,TPAD_PSOC:PROG,TBTROM:PROG
D2_DEVEL:ENG
ALTERNATE,IVB_PPT_XDP,S0PGOOD_ISL,DPMUX_DEBUG,DDRVREF_DAC,VREF:ENG_M3,SENSOR_NONPROD:Y,D_BKL:DEV
D2_DEVEL:FSB
ALTERNATE,IVB_PPT_XDP
IVB_PPT_XDP
XDP_CONN,XDP_PCH
TABLE_BOMGROUP_ITEM
VREF:PROD
VREFDQ:M1_M3,VREFCA:LDO
VREF:ENG_M3
VREFDQ:M1_M3,VREFCA:LDO_DAC
VREF:ENG_LDO
VREFDQ:M1_DAC,VREFCA:LDO_DAC
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
DRAM SPD Straps
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_HEAD
BOM GROUP
B
PART NUMBER
337S4266
QTY
1
BOM OPTIONS
RAM_4G_HYNIX_1600_S
RAMCFG3:L,RAMCFG2:L,RAMCFG1:L,RAMCFG0:L
RAM_1G_SAMSUNG_1600
RAMCFG3:L,RAMCFG2:L,RAMCFG1:L,RAMCFG0:H
RAM_4G_SAMSUNG_1600_S
Module Parts
RAMCFG3:L,RAMCFG2:L,RAMCFG1:H,RAMCFG0:L
TABLE_BOMGROUP_ITEM
DESCRIPTION
REFERENCE DES
CRITICAL
U1000
IVB,S R0MP,PRQ,E1,2.3,45W,4+2,1.2,6M,BGA
CRITICAL
BOM OPTION
TABLE_BOMGROUP_ITEM
337S4267
1
IVB,S R0MM,PRQ,E1,2.6,45W,4+2,1.25,6M,BGA
U1000
CRITICAL
1
IVB,S R0MK,PRQ,E1,2.7,45W,4+2,1.25,8M,BGA
U1000
CRITICAL
CPU_IVY:2_7GHZ
337S4269
1
PANTHER POINT,C1,SLJ8C,PRQ,BD82HM77
U1800
CRITICAL
337S4256
1
IC,GPU,NV GK107-GTX-PS-A2
U8000
CRITICAL
338S1113
1
IC,TBT,CR-4C,B1,PRQ,CIO,228 12X12 FC-CSP
U3600
CRITICAL
TBTRTR:PRQ
333S0622
32
IC,SDRAM,DDR3-1600,256MX8,78FBGA,HYNIX,C-DIE,38NM
CRITICAL
2G_HYNIX_1600
333S0623
32
IC,SDRAM,DDR3-1600,256MX8,78FBGA,SAMSUNG
CRITICAL
2G_SAMSUNG_1600
333S0628
32
IC,SDRAM,DDR3-1600,256MX8,78FBGA,D-DIE,ELPIDA
CRITICAL
TABLE_BOMGROUP_ITEM
CPU_IVY:2_6GHZ
337S4268
2G_ELPIDA_1600
RAMCFG3:L,RAMCFG2:L,RAMCFG1:H,RAMCFG0:H
RAMCFG3:L,RAMCFG2:H,RAMCFG1:L,RAMCFG0:L
RAM_2G_SAMSUNG_1600
2G_SAMSUNG_1600,RAMCFG3:L,RAMCFG2:H,RAMCFG1:L,RAMCFG0:H
RAM_2G_SAMSUNG_1333
RAMCFG3:L,RAMCFG2:H,RAMCFG1:H,RAMCFG0:L
2G_HYNIX_1600,RAMCFG3:L,RAMCFG2:H,RAMCFG1:H,RAMCFG0:H
RAM_4G_SAMSUNG_1600
U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970,U3000,U3010,U3020,U3030,U3040,U3050,U3060,U3070,U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170,U3200,U3210,U3220,U3230,U3240,U3250,U3260,U3270
RAM_1G_HYNIX_1600
RAM_4G_ELPIDA_1600_S
RAM_2G_HYNIX_1600
U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970,U3000,U3010,U3020,U3030,U3040,U3050,U3060,U3070,U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170,U3200,U3210,U3220,U3230,U3240,U3250,U3260,U3270
4G_SAMSUNG_1600,RAMCFG3:H,RAMCFG2:L,RAMCFG1:L,RAMCFG0:L
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
RAM_4G_HYNIX_1600
333S0624
IC,SDRAM,DDR3-1600,512MX8,78FBGA,C-DIE,SAMSUNG
333S0629
32
IC,SDRAM,DDR3-1600,512MX8,78FBGA,B-DIE,ELPIDA
333S0630
4
IC,SDRAM,GDDR5,64MX32,A-DIE,HYNIX
333S0631
4
IC,SDRAM,GDDR5,64MX32,D-DIE,SAMSUNG
128S0264
30
CAP,TANT,POLY,68UF,20%,16V,50MOHM,D2E
128S0257
A
32
30
CAP,TANT,POLY,68UF,20%,16V,50MOHM,D,LF
725-1614
1
INSULATOR,SHORT,REAR,MLB,D2
CRITICAL
CRITICAL
CRITICAL
FB_2G_SAMSUNG
CRITICAL
PBUS_CAP:SANYO
CRITICAL
PBUS_CAP:KEMET
CRITICAL
RAM_2G_HYNIX_1600_S
FB_2G_HYNIX_A_DIE
U8400,U8450,U8500,U8550
RAMCFG3:H,RAMCFG2:H,RAMCFG1:L,RAMCFG0:H
RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:L
4G_ELPIDA_1600
U8400,U8450,U8500,U8550
TABLE_BOMGROUP_ITEM
4G_SAMSUNG_1600
CRITICAL
TABLE_BOMGROUP_ITEM
4G_HYNIX_1600
CRITICAL
4G_ELPIDA_1600,RAMCFG3:H,RAMCFG2:H,RAMCFG1:L,RAMCFG0:L
RAM_2G_SAMSUNG_1600_S
IC,SDRAM,DDR3-1600,512MX8,78FBGA,HYNIX
2G_ELPIDA_1600,RAMCFG3:H,RAMCFG2:L,RAMCFG1:H,RAMCFG0:H
RAM_4G_ELPIDA_1600
32
RAMCFG3:H,RAMCFG2:L,RAMCFG1:H,RAMCFG0:L
RAM_2G_ELPIDA_1600
333S0625
4G_HYNIX_1600,RAMCFG3:H,RAMCFG2:L,RAMCFG1:L,RAMCFG0:H
RAM_2G_ELPIDA_1600_S
U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970,U3000,U3010,U3020,U3030,U3040,U3050,U3060,U3070,U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170,U3200,U3210,U3220,U3230,U3240,U3250,U3260,U3270
PBUS_CAP:SANYO
U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970,U3000,U3010,U3020,U3030,U3040,U3050,U3060,U3070,U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170,U3200,U3210,U3220,U3230,U3240,U3250,U3260,U3270
U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970,U3000,U3010,U3020,U3030,U3040,U3050,U3060,U3070,U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170,U3200,U3210,U3220,U3230,U3240,U3250,U3260,U3270
U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970,U3000,U3010,U3020,U3030,U3040,U3050,U3060,U3070,U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170,U3200,U3210,U3220,U3230,U3240,U3250,U3260,U3270
C8921,C8922,C8920,C8926,C7554,C7560,C7561,C7513,C7514,C7523,C7524,C7533,C7534,C7570,C7571,C7572,C7040,C7240,C7242,C7280,C7282,C7330,C7331,C7575,C7620,C7621,C8307,C8356,C9820,C9821
C8921,C8922,C8920,C8926,C7554,C7560,C7561,C7513,C7514,C7523,C7524,C7533,C7534,C7570,C7571,C7572,C7040,C7240,C7242,C7280,C7282,C7330,C7331,C7575,C7620,C7621,C8307,C8356,C9820,C9821
REAR_INSULATOR
725-1648
1
INSULATOR,TALL,REAR,MLB,D2
REAR_INSULATOR
CRITICAL
725-1568
1
INSULATOR,CPU,D2
CPU_INSULATOR
CRITICAL
725-1569
1
INSULATOR,GPU,D2
GPU_INSULATOR
1
INSULATOR,PCH,D2
PCH_INSULATOR
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
DEVELOPMENT/BASE BOM
PART NUMBER
CRITICAL
D2 MLB KEPLER DEVEL BOM
DEVEL
CRITICAL
DEVEL_BOM
1
D2 MLB KEPLER FSB DEVEL BOM
DEVEL_FSB
CRITICAL
DEVEL_FSB_BOM
607-9546
PD Parts
REFERENCE DES
1
085-4776
PBUS_CAP:KEMET
DESCRIPTION
085-3726
CRITICAL
725-1621
B
TABLE_BOMGROUP_ITEM
CPU_IVY:2_3GHZ
1
D2 MLB KEPLER 2PHASE BASE BOM
BASE
CRITICAL
BASE_BOM
685-0016
QTY
1
PBUS PAIR,KEMET POSCAP,TALL MYLAR,D2
POSCAP_MYLAR
CRITICAL
CRITICAL
BOM OPTION
SYNC_MASTER=D2_KEPLER
SYNC_DATE=01/13/2012
PAGE TITLE
BOM Configuration
POSCAP_MYLAR_PAIR
DRAWING NUMBER
SMC
Apple Inc.
051-9589
REVISION
R
806-2897
2
825-7697
946-3819
825-7841
CAN,COVER,2,J5
CAN_COVER1,CAN_COVER2
CRITICAL
341S3308
1
IC,SMC,DEVELOPMENT-FSB,A3,D2
U4900
CRITICAL
1
TEXT,LABEL,MLB,D2
TEXT_LABEL
CRITICAL
341S3309
1
IC,SMC,PVB,A3,2.2F36,D2
U4900
CRITICAL
SMC_PROG:PVB
1
D2 MLB DYMAX ADHESIVE SEE-CURE 29993-SC
EDGE_BOND
CRITICAL
1
LBL,PART CONFIG,BOARDS,D2
CONFIG_LABEL
CRITICAL
NOTICE OF PROPRIETARY PROPERTY:
EFI ROM
341S3595
8
4.18.0
SMC_PROG:FSB
7
6
5
1
IC,EFI,ROM,FSB, D2
4
U6100
CRITICAL
3
BOOTROM_PROG:FSB
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
2
BRANCH
PAGE
5 OF 132
SHEET
5 OF 99
1
SIZE
D
A
8
7
6
5
BOM Variants (continued from CSA 5)
4
3
2
1
Bar Code Labels / EEEE #’s (continued from CSA 5)
TABLE_BOMGROUP_HEAD
BOM NUMBER
BOM NAME
639-3382
PCBA,2.3G,8G_ELP,VRAM_HYN,MLB_KEPLER,D2,DY41
PCBA,2.3G,8G_ELP,VRAM_SAM,MLB_KEPLER,D2,DY42
639-3445
PCBA,2.3G,16G_ELP,VRAM_HYN,MLB_KEPLER,D2,DYJ5
639-3446
PCBA,2.3G,16G_ELP,VRAM_SAM,MLB_KEPLER,D2,DYJ6
[EEEE:DY41]
CRITICAL
EEEE:DY41
1
LABEL,MLB/LIO,MBA
[EEEE:DY42]
CRITICAL
EEEE:DY42
1
LABEL,MLB/LIO,MBA
[EEEE:DYJ5]
CRITICAL
EEEE:DYJ5
825-7563
1
LABEL,MLB/LIO,MBA
[EEEE:DYJ6]
CRITICAL
EEEE:DYJ6
825-7563
1
LABEL,MLB/LIO,MBA
[EEEE:DRF0]
CRITICAL
EEEE:DRF0
825-7563
1
LABEL,MLB/LIO,MBA
[EEEE:DRDP]
CRITICAL
EEEE:DRDP
825-7563
1
LABEL,MLB/LIO,MBA
[EEEE:DRDT]
CRITICAL
EEEE:DRDT
825-7563
1
LABEL,MLB/LIO,MBA
[EEEE:DRDQ]
CRITICAL
EEEE:DRDQ
825-7563
1
LABEL,MLB/LIO,MBA
[EEEE:F0JD]
CRITICAL
EEEE:F0JD
825-7563
1
LABEL,MLB/LIO,MBA
[EEEE:F0J3]
CRITICAL
EEEE:F0J3
825-7563
1
LABEL,MLB/LIO,MBA
[EEEE:F0J4]
CRITICAL
EEEE:F0J4
825-7563
BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_SAMSUNG,EEEE:DYJ6,DEVEL_BOM,RAM_4G_ELPIDA_1600
LABEL,MLB/LIO,MBA
825-7563
BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_HYNIX_A_DIE,EEEE:DYJ5,DEVEL_BOM,RAM_4G_ELPIDA_1600
REFERENCE DES
1
825-7563
BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_SAMSUNG,EEEE:DY42,DEVEL_BOM,RAM_2G_ELPIDA_1600
DESCRIPTION
825-7563
BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_HYNIX_A_DIE,EEEE:DY41,DEVEL_BOM,RAM_2G_ELPIDA_1600
639-3383
PART NUMBER
BOM OPTIONS
QTY
CRITICAL
BOM OPTION
1
LABEL,MLB/LIO,MBA
[EEEE:F0JC]
CRITICAL
EEEE:F0JC
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
639-2818
PCBA,2.6G,8G_ELP,VRAM_HYN,MLB_KEPLER,D2,DRF0
BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_HYNIX_A_DIE,EEEE:DRF0,DEVEL_BOM,RAM_2G_ELPIDA_1600
639-2820
PCBA,2.6G,8G_ELP,VRAM_SAM,MLB_KEPLER,D2,DRDP
BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_SAMSUNG,EEEE:DRDP,DEVEL_BOM,RAM_2G_ELPIDA_1600
639-2823
PCBA,2.6G,16G_ELP,VRAM_HYN,MLB_KEPLER,D2,DRDT
BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_HYNIX_A_DIE,EEEE:DRDT,DEVEL_BOM,RAM_4G_ELPIDA_1600
639-2819
PCBA,2.6G,16G_ELP,VRAM_SAM,MLB_KEPLER,D2,DRDQ
BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_SAMSUNG,EEEE:DRDQ,DEVEL_BOM,RAM_4G_ELPIDA_1600
639-3632
PCBA,2.7G,8G_ELP,VRAM_HYN,MLB_KEPLER,D2,F0JD
BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_HYNIX_A_DIE,EEEE:F0JD,DEVEL_BOM,RAM_2G_ELPIDA_1600
639-3633
PCBA,2.7G,8G_ELP,VRAM_SAM,MLB_KEPLER,D2,F0J3
BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_SAMSUNG,EEEE:F0J3,DEVEL_BOM,RAM_2G_ELPIDA_1600
639-3630
PCBA,2.7G,16G_ELP,VRAM_HYN,MLB_KEPLER,D2,F0J4
BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_HYNIX_A_DIE,EEEE:F0J4,DEVEL_BOM,RAM_4G_ELPIDA_1600
TABLE_BOMGROUP_ITEM
D
Elipda DQ’d
Keeping for PRQ
D
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
639-3631
PCBA,2.7G,16G_ELP,VRAM_SAM,MLB_KEPLER,D2,F0JC
BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_SAMSUNG,EEEE:F0JC,DEVEL_BOM,RAM_4G_ELPIDA_1600
C
C
B
B
A
SYNC_MASTER=D2_KEPLER
SYNC_DATE=01/13/2012
PAGE TITLE
BOM Variants
DRAWING NUMBER
Apple Inc.
051-9589
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
4.18.0
BRANCH
PAGE
6 OF 132
SHEET
6 OF 99
1
SIZE
D
A
8
7
6
FUNC_TEST
Functional Test Points
FUNC_TEST
I1596
TRUE
I1599
TRUE
I1600
TRUE
I1601
TRUE
I1602
TRUE
I1603
D
TRUE
I1604
TRUE
I1605
TRUE
I1606
I1608
TRUE
TRUE
I1609
TRUE
I1607
J3501 - airport
TRUE
I1652
TRUE
I1655
TRUE
I1656
TRUE
I1658
TRUE
I1659
TRUE
I1657
TRUE
I1661
TRUE
I1660
TRUE
I1663
TRUE
I1664
I1662
TRUE
TRUE
I1665
TRUE
I1666
TRUE
TRUE
I1668
I1669
J3502 - ALS camera
I1610
TRUE
I1613
TRUE
I1614
PP5V_S3_ALSCAMERA_F
SMBUS_SMC_2_S3_SCL
SMBUS_SMC_2_S3_SDA
USB_CAMERA_CONN_N
USB_CAMERA_CONN_P
GND
TRUE
I1612
TRUE
TRUE
TRUE
I1671
TRUE
I1670
TRUE
7 41 44 94
I1673
TRUE
7 41 44 94
I1674
TRUE
34
34 91
I1672
TRUE
TRUE
I1675
34 91
J4400 - rio coax
I1616
TRUE
I1617
TRUE
I1621
TRUE
I1620
TRUE
I1623
TRUE
I1624
TRUE
I1622
TRUE
I1625
TRUE
I1626
TRUE
I1628
TRUE
I1629
TRUE
I1627
TRUE
I1631
TRUE
I1630
TRUE
I1633
TRUE
I1634
TRUE
I1632
TRUE
I1635
C
TRUE
I1619
HDMI_EG_CLK_C_N
HDMI_EG_CLK_C_P
HDMI_EG_DATA_C_N & lt; 0 & gt;
HDMI_EG_DATA_C_N & lt; 1 & gt;
HDMI_EG_DATA_C_N & lt; 2 & gt;
HDMI_EG_DATA_C_P & lt; 0 & gt;
HDMI_EG_DATA_C_P & lt; 1 & gt;
HDMI_EG_DATA_C_P & lt; 2 & gt;
PCIE_CLK100M_ENET_N
PCIE_CLK100M_ENET_P
PCIE_ENET_D2R_N
PCIE_ENET_D2R_P
PCIE_ENET_R2D_C_N
PCIE_ENET_R2D_C_P
USB3_EXTB_RX_N
USB3_EXTB_RX_P
USB3_EXTB_TX_C_N
USB3_EXTB_TX_C_P
USB_EXTB_N
USB_EXTB_P
GND
TRUE
I1618
TRUE
TRUE
I1676
TRUE
I1678
I1615
TRUE
TRUE
I1667
I1611
TRUE
I1731
FUNC_TEST
AP_CLKREQ_Q_L
34
AP_RESET_CONN_L
34
PCIE_AP_D2R_PI_N
34 92
PCIE_AP_D2R_PI_P
34 92
PCIE_AP_R2D_N
34 92
PCIE_AP_R2D_P
34 92
PCIE_CLK100M_AP_CONN_N 34 96
PCIE_CLK100M_AP_CONN_P 34 96
PCIE_WAKE_L
18 34
PP3V3_S3RS4_BT_F
34
PP3V3_WLAN
34 42
USB_BT_CONN_N
34 91
USB_BT_CONN_P
34 91
WIFI_EVENT_L
34 41 42
GND
4X GND
TRUE
I1597
TRUE
I1679
TRUE
38 77 95
I1677
TRUE
38 77 95
I1681
TRUE
TRUE
38 77 95
38 77 95
I1685
TRUE
38 77 95
I1686
TRUE
38 77 95
I1687
TRUE
38 77 95
I1689
TRUE
17 38 92
I1688
TRUE
17 38 92
I1691
TRUE
17 38 92
I1690
TRUE
17 38 92
I1692
TRUE
17 38 92
I1694
TRUE
17 38 92
I1693
TRUE
19 38 91
I1695
TRUE
19 38 91
I1799
TRUE
38 97
38 97
I1800
TRUE
I1697
TRUE
26 38 91
I1797
TRUE
26 38 91
I1798
TRUE
I1817
TRUE
TRUE
19X GND
TRUE
J4410 - rio flex
I1636
I1638
TRUE
I1639
TRUE
I1637
TRUE
I1641
TRUE
I1640
TRUE
I1643
TRUE
I1644
TRUE
I1645
TRUE
I1646
TRUE
I1648
TRUE
I1649
TRUE
I1647
TRUE
I1651
B
TRUE
I1642
TRUE
I1650
TRUE
I1785
TRUE
I1802
I1803
TRUE
I1696
TRUE
I1698
TRUE
I1699
TRUE
I1700
TRUE
I1702
TRUE
I1701
TRUE
I1703
TRUE
I1704
TRUE
I1705
TRUE
I1707
TRUE
I1706
TRUE
I1708
TRUE
I1654
PP3V42_G3H
SMC_LID_R
GND
TRUE
I1709
TRUE
I1710
TRUE
TRUE
I1711
TRUE
I1713
TRUE
I1715
J5050 - hall effect
TRUE
TRUE
42
I1714
TRUE
TRUE
I1716
I1720
TRUE
I1793
TRUE
TRUE
48
7
8
3X P5V_S0
5X GND
TRUE
I1719
48
TRUE
TRUE
I1722
TRUE
I1721
TRUE
I1723
I1683
FAN_LT_PWM
FAN_LT_TACH
PP5V_S0
GND
TRUE
TRUE
I1718
J5650 - left fan
I1680
TRUE
J5660 - right fan
I1684
I1682
TRUE
I1795
FAN_RT_PWM
FAN_RT_TACH
PP5V_S0
GND
TRUE
TRUE
TRUE
I1735
TRUE
I1734
TRUE
I1736
TRUE
I1738
TRUE
I1737
TRUE
I1740
TRUE
I1739
TRUE
I1741
TRUE
20 43
25 43
17 41 43 82
92
17 41 43 82
92
17 41 43 82
92
17 41 43 82
92
Z2_CS_L
Z2_DEBUG3
Z2_MOSI
Z2_MISO
Z2_SCLK
Z2_HOST_INTN
Z2_CLKIN
Z2_KEY_ACT_L
Z2_RESET
PSOC_F_CS_L
PICKB_L
PP3V3_S4
PP5V_S5
PSOC_MISO
PSOC_MOSI
PSOC_SCLK
SMBUS_SMC_2_S3_SCL
SMBUS_SMC_2_S3_SDA
GND
PP3V3_S4
PP3V42_G3H
WS_CONTROL_KBD
WS_KBD1
WS_KBD10
WS_KBD11
WS_KBD12
WS_KBD13
WS_KBD14
WS_KBD15_CAP
WS_KBD16_NUM
WS_KBD17
WS_KBD18
WS_KBD19
WS_KBD2
WS_KBD20
WS_KBD21
WS_KBD22
WS_KBD23
WS_KBD3
WS_KBD4
WS_KBD5
WS_KBD6
WS_KBD7
WS_KBD8
WS_KBD9
WS_KBD_ONOFF_L
WS_LEFT_OPTION_KBD
WS_LEFT_SHIFT_KBD
GND
TRUE
A
I1730
TRUE
I1729
KBDLED_ANODE1
KBDLED_ANODE2
SMC_KBDLED_PRESENT_L
GND
TRUE
TRUE
TRUE
AUD_HP_PORT_L
AUD_HP_PORT_R
AUD_SPDIF_OUT_JACK
AUD_TIPDET_INV
AUD_TYPEDET
CH_HS_GND
CH_HS_MIC
PP3V3_S0
US_HS_GND
US_HS_MIC
GND
53 54 58
I1759
TRUE
53 54 58
I1760
TRUE
53 58
I1761
TRUE
59
I1763
TRUE
TRUE
58 59
4X 58
I1762
TRUE
I1764
TRUE
I1766
TRUE
TRUE
I1768
TRUE
59
I1767
TRUE
59
I1769
TRUE
59
I1770
TRUE
59
I1771
TRUE
I1773
TRUE
TRUE
I1774
TRUE
I1775
TRUE
57 59 96
I1776
TRUE
57 59 96
I1777
TRUE
57 59 96
I1779
TRUE
57 59 96
I1778
TRUE
I1780
TRUE
58
2X GND
J6801 - 3-mic
18 41 43
I1743
I1742
TRUE
I1745
TRUE
I1744
CON_DMIC_CLK
CON_DMIC_PWR
CON_DMIC_SDA1
CON_DMIC_SDA2
GND
TRUE
TRUE
7 8
41 42 43 61
42 43
41 42 43
TRUE
41 42 43
41 42 43
J6802 - L speaker
41 42 43
I1746
I1748
TRUE
I1747
TRUE
I1750
TRUE
I1749
SPKRCONN_L_ID
SPKRCONN_L_OUT_N
SPKRCONN_L_OUT_P
SPKRCONN_SL_OUT_N
SPKRCONN_SL_OUT_P
GND
TRUE
TRUE
41 42 43
41 42 43
20 43 52
43
43
TRUE
59
43
I1781
TRUE
I1782
TRUE
43
J6803 - R speaker
43
I1751
TRUE
I1755
TRUE
I1754
49
TRUE
I1752
2X GND
TRUE
TRUE
49
TRUE
SPKRCONN_R_ID
SPKRCONN_R_OUT_N
SPKRCONN_R_OUT_P
SPKRCONN_SR_OUT_N
SPKRCONN_SR_OUT_P
GND
TRUE
I1753
43
DP_INT_AUX_N
DP_INT_AUX_P
DP_INT_ML_N & lt; 0 & gt;
DP_INT_ML_N & lt; 1 & gt;
DP_INT_ML_N & lt; 2 & gt;
DP_INT_ML_N & lt; 3 & gt;
DP_INT_ML_P & lt; 0 & gt;
DP_INT_ML_P & lt; 1 & gt;
DP_INT_ML_P & lt; 2 & gt;
DP_INT_ML_P & lt; 3 & gt;
LCD_FSS
LCD_HPD_CONN
LED_RETURN_1
LED_RETURN_2
LED_RETURN_3
LED_RETURN_4
LED_RETURN_5
LED_RETURN_6
PP5VR3V3_SW_LCD
PPVOUT_S0_LCDBKLT
GND
57 59 96
57 59 96
TRUE
TRUE
TRUE
J6900 - DC PWR
49
I1756
49
I1758
TRUE
49
I1757
ADAPTER_SENSE
PP18V5_DCIN_FUSE
TDM_ONEWIRE_MPM
GND
TRUE
TRUE
TRUE
TRUE
TRUE
60
2X 60
TRUE
TRUE
60
2X GND
TRUE
TRUE
49
POWER RAILS
49
7 8
TRUE
FUNC_TEST
TRUE
TRUE
7 8
TRUE
PM_SLP_S3_L
TRUE
PP0V75_S0_DDRVTT
PP1V05_S0
49
49
TRUE
7 18 27 38 41 70
TRUE
8
TRUE
8
TRUE
49
7 41 44 94
TRUE
TRUE
PP1V8_S0
8
TRUE
PP3V3_S0
7 8 96
7 41 44 94
2X GND
TRUE
PP3V3_S0GPU
PP3V3_S3
7 8
TRUE
PP3V3_S5
7 8
TRUE
TRUE
49
49
TRUE
49
TRUE
49
TRUE
PP3V3_S5_AVREF_SMC
PP3V42_G3H
PP5V_S0
TRUE
TRUE
8
TRUE
7 8
TRUE
8 96
TRUE
41 42
TRUE
7 8
TRUE
7 8
TRUE
49
TRUE
49
TRUE
PP5V_S3
PP5V_S5
PPBUS_G3H
PPDCIN_G3H
49
TRUE
PPVCORE_GPU
8
49
TRUE
PPVCORE_S0_CPU
8
49
TRUE
PPVTTDDR_S3
8
8
TRUE
7 8
TRUE
8
TRUE
8
TRUE
TRUE
8X GND
81 95
81 95
TRUE
TRUE
49
17
49
17
49
17
17
49
TP_PCIE_5_D2RN
TP_PCIE_5_D2RP
TP_PCIE_5_R2D_CN
TP_PCIE_5_R2D_CP
81 95
18
81 95
18
81 95
18
81 95
18
81 95
18
81 95
18
81 82
18
81
18
81 86
18
81 86
18
81 86
17
81 86
17
81 86
17
3X 81
81 86 99
16X GND
84 93
84 93
7 35 84 93
19
7 35 84 93
19
7 35 84 93
35 84 93
84 93
84 93
85 93
85 93
35 85 93
35 85 93
7 35 85 93
35 85 93
17
85 93
17
85 93
35 77 95
35 77 95
35 95
35 95
35 83 95
35 83 95
49
35 95
35 95
35 77 95
35 77 95
35 95
17
35 95
17
35 83 95
17
35 83 95
17
35 95
17
35 95
17
17
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
NC_PCIE_5_D2RN
NC_PCIE_5_D2RP
NC_PCIE_5_R2D_CN
NC_PCIE_5_R2D_CP
17
17
17
17
MAKE_BASE=TRUE
49
17
49
17
49
17
49
17
TP_PCIE_6_D2RN
TP_PCIE_6_D2RP
TP_PCIE_6_R2D_CN
TP_PCIE_6_R2D_CP
TRUE
TP_PCIE_7_D2RN
TP_PCIE_7_D2RP
TP_PCIE_7_R2D_CN
TP_PCIE_7_R2D_CP
TRUE
TP_PCIE_8_D2RN
TP_PCIE_8_D2RP
TP_PCIE_8_R2D_CN
TP_PCIE_8_R2D_CP
TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
NC_PCIE_6_D2RN
NC_PCIE_6_D2RP
NC_PCIE_6_R2D_CN
NC_PCIE_6_R2D_CP
49
17
49
17
49
17
49
17
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
NO_TEST
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TP_CRT_IG_BLUE
TP_CRT_IG_GREEN
TP_CRT_IG_RED
TP_CRT_IG_DDC_CLK
TP_CRT_IG_DDC_DATA
TP_CRT_IG_HSYNC
TP_CRT_IG_VSYNC
TP_LVDS_IG_CTRL_CLK
TP_LVDS_IG_CTRL_DATA
TP_PCH_LVDS_VBG
TRUE
NC_CRT_IG_BLUE
NC_CRT_IG_GREEN
NC_CRT_IG_RED
NC_CRT_IG_DDC_CLK
NC_CRT_IG_DDC_DATA
NC_CRT_IG_HSYNC
NC_CRT_IG_VSYNC
NC_LVDS_IG_CTRL_CLK
NC_LVDS_IG_CTRL_DATA
NC_PCH_LVDS_VBG
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TP_HDA_SDIN1
TP_HDA_SDIN2
TP_HDA_SDIN3
TP_PCI_AD & lt; 31..0 & gt;
TP_PCI_C_BE_L & lt; 3..0 & gt;
TP_PCI_GNT3_L
TP_PCI_GNT2_L
TP_PCI_GNT1_L
TP_PCI_GNT0_L
TP_PCI_PAR
TP_PCI_RESET_L
TP_PCI_PME_L
TP_PCI_CLK33M_OUT3
TP_PCH_NV_RCOMP
TP_NV_DQ & lt; 15..0 & gt;
TP_NV_DQS & lt; 1..0 & gt;
TP_NV_CE_L & lt; 3..0 & gt;
TP_NV_ALE
TP_NV_CLE
TP_NV_RB_L
TP_NV_WR_RE_L & lt; 1..0 & gt;
TP_NV_WE_CK_L & lt; 1..0 & gt;
TP_PCIE_CLK100M_PE4N
TP_PCIE_CLK100M_PE4P
TP_PCIE_CLK100M_PE5N
TP_PCIE_CLK100M_PE5P
TP_PCIE_CLK100M_PE6N
TP_PCIE_CLK100M_PE6P
TP_PCIE_CLK100M_PE7N
TP_PCIE_CLK100M_PE7P
TP_PSOC_P1_3
TP_SATA_B_D2RN
TP_SATA_B_D2RP
TP_SATA_B_R2D_CN
TP_SATA_B_R2D_CP
TP_SATA_D_D2RN
TP_SATA_D_D2RP
TP_SATA_D_R2D_CN
TP_SATA_D_R2D_CP
TP_SATA_E_D2RN
TP_SATA_E_D2RP
TP_SATA_E_R2D_CN
TP_SATA_E_R2D_CP
TP_SATA_F_D2RN
TP_SATA_F_D2RP
TP_SATA_F_R2D_CN
TP_SATA_F_R2D_CP
TP_SMC_P41
TRUE
NC_HDA_SDIN1
TRUE
MAKE_BASE=TRUE
NC_HDA_SDIN2
TRUE
MAKE_BASE=TRUE
NC_HDA_SDIN3
TRUE
MAKE_BASE=TRUE
NC_PCI_AD & lt; 31..0 & gt;
TRUE
MAKE_BASE=TRUE
NC_PCI_C_BE_L & lt; 3..0 & gt;
TRUE
MAKE_BASE=TRUE
NC_PCI_GNT3_L
TRUE
MAKE_BASE=TRUE
NC_PCI_GNT2_L
TRUE
MAKE_BASE=TRUE
NC_PCI_GNT1_L
TRUE
MAKE_BASE=TRUE
NC_PCI_GNT0_L
TRUE
MAKE_BASE=TRUE
NC_PCI_PAR
TRUE
MAKE_BASE=TRUE
NC_PCI_RESET_L
TRUE
MAKE_BASE=TRUE
NC_PCI_PME_L
TRUE
MAKE_BASE=TRUE
NC_PCI_CLK33M_OUT3
TRUE
MAKE_BASE=TRUE
NC_PCH_NV_RCOMP
TRUE
MAKE_BASE=TRUE
NC_NV_DQ & lt; 15..0 & gt;
TRUE
MAKE_BASE=TRUE
NC_NV_DQS & lt; 1..0 & gt;
TRUE
MAKE_BASE=TRUE
NC_NV_CE_L & lt; 3..0 & gt;
TRUE
MAKE_BASE=TRUE
NC_NV_ALE
TRUE
MAKE_BASE=TRUE
NC_NV_CLE
TRUE
MAKE_BASE=TRUE
NC_NV_RB_L
TRUE
MAKE_BASE=TRUE
NC_NV_WR_RE_L & lt; 1..0 & gt;
TRUE
MAKE_BASE=TRUE
NC_NV_WE_CK_L & lt; 1..0 & gt;
TRUE
MAKE_BASE=TRUE
NC_PCIE_CLK100M_PE4N
TRUE
MAKE_BASE=TRUE
NC_PCIE_CLK100M_PE4P
TRUE
MAKE_BASE=TRUE
NC_PCIE_CLK100M_PE5N
TRUE
MAKE_BASE=TRUE
NC_PCIE_CLK100M_PE5P
TRUE
MAKE_BASE=TRUE
NC_PCIE_CLK100M_PE6N
TRUE
MAKE_BASE=TRUE
NC_PCIE_CLK100M_PE6P
TRUE
MAKE_BASE=TRUE
NC_PCIE_CLK100M_PE7N
TRUE
MAKE_BASE=TRUE
NC_PCIE_CLK100M_PE7P
TRUE
MAKE_BASE=TRUE
NC_PSOC_P1_3
TRUE
MAKE_BASE=TRUE
NC_SATA_B_D2RN
TRUE
MAKE_BASE=TRUE
NC_SATA_B_D2RP
TRUE
MAKE_BASE=TRUE
NC_SATA_B_R2D_CN
TRUE
MAKE_BASE=TRUE
NC_SATA_B_R2D_CP
TRUE
MAKE_BASE=TRUE
NC_SATA_D_D2RN
TRUE
MAKE_BASE=TRUE
NC_SATA_D_D2RP
TRUE
MAKE_BASE=TRUE
NC_SATA_D_R2D_CN
TRUE
MAKE_BASE=TRUE
NC_SATA_D_R2D_CP
TRUE
MAKE_BASE=TRUE
NC_SATA_E_D2RN
TRUE
MAKE_BASE=TRUE
NC_SATA_E_D2RP
TRUE
MAKE_BASE=TRUE
NC_SATA_E_R2D_CN
TRUE
MAKE_BASE=TRUE
NC_SATA_E_R2D_CP
TRUE
MAKE_BASE=TRUE
NC_SATA_F_D2RN
TRUE
MAKE_BASE=TRUE
NC_SATA_F_D2RP
TRUE
MAKE_BASE=TRUE
NC_SATA_F_R2D_CN
TRUE
MAKE_BASE=TRUE
NC_SATA_F_R2D_CP
TRUE
MAKE_BASE=TRUE
NC_SMC_P41
TRUE
MAKE_BASE=TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TP_HDMI_CEC
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
7
NC_PCIE_7_D2RN
NC_PCIE_7_D2RP
NC_PCIE_7_R2D_CN
NC_PCIE_7_R2D_CP
7
NO_TEST
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TP_DVPDATA & lt; 21..4 & gt;
TP_DVPCNTL_M & lt; 1..0 & gt;
TP_DVPCNTL & lt; 2..0 & gt;
TP_DVPCNTL & lt; 2..0 & gt;
17
49
17
2X GND
17
48
17
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
93 85 35 7
93 84 35 7
3X P5V_S0
5X GND
TP_PCIE_PE6_D2RN
TP_PCIE_PE6_D2RP
TP_PCIE_PE6_R2D_CN
TP_PCIE_PE6_R2D_CP
2X 50
2X 50
50
4X GND
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
TP_PCIE_PE7_D2RN
TP_PCIE_PE7_D2RP
TP_PCIE_PE7_R2D_CN
TP_PCIE_PE7_R2D_CP
93 84 35 7
93 84 35 7
1 TP
SM BEAD-PROBE
TP_PCIE_PE8_D2RN
TP_PCIE_PE8_D2RP
TP_PCIE_PE8_R2D_CN
TP_PCIE_PE8_R2D_CP
BP0734 SIGNAL_MODEL=EMPTY
SM BEAD-PROBE
BP0735 SIGNAL_MODEL=EMPTY
TRUE
TRUE
BP0733 SIGNAL_MODEL=EMPTY
SM BEAD-PROBE
SM BEAD-PROBE
35
35
35
35
NC_PCIE_PE5_D2RN
NC_PCIE_PE5_D2RP
NC_PCIE_PE5_R2D_CN
NC_PCIE_PE5_R2D_CP
35
35
35
35
NC_PCIE_PE6_D2RN
NC_PCIE_PE6_D2RP
NC_PCIE_PE6_R2D_CN
NC_PCIE_PE6_R2D_CP
35
TP_TBT_XTAL25OUT
TP_TBT_PCIE_RESET0_L
TP_TBT_PCIE_RESET1_L
TP_TBT_PCIE_RESET2_L
TP_TBT_PCIE_RESET3_L
TP_DP_TBTSRC_ML_CP & lt; 3..0 & gt;
TP_DP_TBTSRC_ML_CN & lt; 3..0 & gt;
TP_DP_TBTSRC_AUXCH_CP
TP_DP_TBTSRC_AUXCH_CN
NO_TEST
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
BP0732 SIGNAL_MODEL=EMPTY
7
41
42
42
41
42
42
8
69 98
69 98
99
99
81 98
81 98
99
99
C
NC_DP_IG_D_HPD
TRUE
MAKE_BASE=TRUE
NC_DP_IG_D_CTRL_CLK
TRUE
MAKE_BASE=TRUE
NC_DP_IG_D_CTRL_DATA
TRUE
MAKE_BASE=TRUE
NC_DP_IG_D_MLP & lt; 3..0 & gt;
TRUE
MAKE_BASE=TRUE
NC_DP_IG_D_MLN & lt; 3..0 & gt;
TRUE
MAKE_BASE=TRUE
NC_DP_IG_D_AUXP
TRUE
MAKE_BASE=TRUE
NC_DP_IG_D_AUXN
TRUE
MAKE_BASE=TRUE
TP_SDVO_TVCLKINN
TP_SDVO_TVCLKINP
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
NC_SDVO_TVCLKINN
NC_SDVO_TVCLKINP
TP_SDVO_STALLN
TP_SDVO_STALLP
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
NC_SDVO_STALLN
NC_SDVO_STALLP
TP_SDVO_INTN
TP_SDVO_INTP
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
NC_SDVO_INTN
NC_SDVO_INTP
TP_GPU_BUFRST_L
TP_GPU_GSTATE & lt; 0 & gt;
TP_GPU_GSTATE & lt; 1 & gt;
TP_GPU_MIOA_D & lt; 9..0 & gt;
TP_GPU_MIOA_DE
NC_DVPDATA & lt; 21..4 & gt;
NC_DVPCNTL_M & lt; 1..0 & gt;
NC_DVPDATA & lt; 2..0 & gt;
NC_DVPDATA & lt; 2..0 & gt;
TP_LVDS_EG_BKL_PWM
LVDS_IG_B_CLK_N
LVDS_IG_B_CLK_P
LVDS_IG_BKL_PWM
18
18
7
18
B
NC_GPU_BUFRST_L
TRUE
MAKE_BASE=TRUE
NC_GPU_GSTATE & lt; 0 & gt;
TRUE
MAKE_BASE=TRUE
NC_GPU_GSTATE & lt; 1 & gt;
TRUE
MAKE_BASE=TRUE
NC_GPU_MIOA_D & lt; 9..0 & gt;
TRUE
MAKE_BASE=TRUE
NC_GPU_MIOA_DE
TRUE
MAKE_BASE=TRUE
NC_LVDS_EG_BKL_PWM
TRUE
MAKE_BASE=TRUE
NC_LVDS_IG_B_CLKN
TRUE
MAKE_BASE=TRUE
NC_LVDS_IG_B_CLKP
TRUE
MAKE_BASE=TRUE NC_LVDS_IG_BKL_PWM
TRUE
MAKE_BASE=TRUE
7
TRUE
MAKE_BASE=TRUE
NC_SMC_BS_ALRT_L
NC_TBT_XTAL25OUT
NC_TBT_PCIE_RESET0_L
NC_TBT_PCIE_RESET1_L
NC_TBT_PCIE_RESET2_L
NC_TBT_PCIE_RESET3_L
NC_DP_TBTSRC_ML_CP & lt; 3..0 & gt;
NC_DP_TBTSRC_ML_CN & lt; 3..0 & gt;
NC_DP_TBTSRC_AUXCH_CP
NC_DP_TBTSRC_AUXCH_CN
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
6
5
TRUE
PCH_VSS_NCTF & lt; 1 & gt;
PCH_VSS_NCTF & lt; 2 & gt;
PCH_VSS_NCTF & lt; 5 & gt;
PCH_VSS_NCTF & lt; 7 & gt;
PCH_VSS_NCTF & lt; 9 & gt;
PCH_VSS_NCTF & lt; 11 & gt;
PCH_VSS_NCTF & lt; 12 & gt;
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
PCH_VSS_NCTF & lt; 15 & gt;
PCH_VSS_NCTF & lt; 17 & gt;
PCH_VSS_NCTF & lt; 19 & gt;
PCH_VSS_NCTF & lt; 19 & gt;
PCH_VSS_NCTF & lt; 21 & gt;
PCH_VSS_NCTF & lt; 25 & gt;
PCH_VSS_NCTF & lt; 27 & gt;
PCH_VSS_NCTF & lt; 29 & gt;
SYNC_MASTER=D2_KEPLER
7
7
SYNC_DATE=01/13/2012
PAGE TITLE
Functional / ICT Test
NC_PCIE_PE7_D2RN
NC_PCIE_PE7_D2RP
NC_PCIE_PE7_R2D_CN
NC_PCIE_PE7_R2D_CP
NC_LPC_DREQ0_L
MAKE_BASE=TRUE
TP_LPC_DREQ0_L
DRAWING NUMBER
17
TRUE
Apple Inc.
17
17
NC_PCIE_PE8_D2RN
NC_PCIE_PE8_D2RP
NC_PCIE_PE8_R2D_CN
NC_PCIE_PE8_R2D_CP
17
17
17
TP_CLINK_CLK
TP_CLINK_DATA
TP_CLINK_RESET_L
TP_PCIE_CLK100M_PEBN
TP_PCIE_CLK100M_PEBP
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
8
26
26
TP_DP_IG_D_HPD
TP_DP_IG_D_CTRL_CLK
TP_DP_IG_D_CTRL_DATA
TP_DP_IG_D_MLP & lt; 3..0 & gt;
TP_DP_IG_D_MLN & lt; 3..0 & gt;
TP_DP_IG_D_AUXP
TP_DP_IG_D_AUXN
PCH ALIASES
MAKE_BASE=TRUE
BP0731 SIGNAL_MODEL=EMPTY
SM BEAD-PROBE
26
Thunderbolt NO_TESTs
NC_PCIE_8_D2RN
NC_PCIE_8_D2RP
NC_PCIE_8_R2D_CN
NC_PCIE_8_R2D_CP
MAKE_BASE=TRUE
1 TP
1 TP
26
NC_HDMI_CEC
TRUE
MAKE_BASE=TRUE
SMC_BS_ALRT_L
MAKE_BASE=TRUE
48
1 TP
1 TP
26
MAKE_BASE=TRUE
49
PLACEABLE BEAD-PROBES FOR TBT
TBT_B_R2D_C_P & lt; 1 & gt;
TBT_B_R2D_C_P & lt; 0 & gt;
TBT_A_R2D_C_P & lt; 1 & gt;
TBT_A_D2R_P & lt; 1 & gt;
TBT_A_D2R_N & lt; 1 & gt;
26
NC_DP_IG_C_HPD
TRUE
MAKE_BASE=TRUE
NC_DP_IG_C_CTRL_CLK
TRUE
MAKE_BASE=TRUE
NC_DP_IG_C_CTRL_DATA
TRUE
MAKE_BASE=TRUE
NC_DP_IG_C_MLP & lt; 3..0 & gt;
TRUE
MAKE_BASE=TRUE
NC_DP_IG_C_MLN & lt; 3..0 & gt;
TRUE
MAKE_BASE=TRUE
NC_DP_IG_C_AUXP
TRUE
MAKE_BASE=TRUE
NC_DP_IG_C_AUXN
TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
93 85 35 7
D
TP_DP_IG_C_HPD
TP_DP_IG_C_CTRL_CLK
TP_DP_IG_C_CTRL_DATA
TP_DP_IG_C_MLP & lt; 3..0 & gt;
TP_DP_IG_C_MLN & lt; 3..0 & gt;
TP_DP_IG_C_AUXP
TP_DP_IG_C_AUXN
GPU NO_TESTs
MAKE_BASE=TRUE
49
TRUE
81 86
17
TRUE
TRUE
81 95
NO_TEST
49
TRUE
NC NO_TESTs
NC NO_TESTs
49
NC_TP_CPU_RSVD & lt; 65..62 & gt;
NC_TP_CPU_RSVD & lt; 58..45 & gt;
NC_TP_CPU_RSVD & lt; 43..32 & gt;
NC_TP_CPU_RSVD & lt; 27..26 & gt;
NC_TP_CPU_RSVD & lt; 24..15 & gt;
NC_TP_CPU_RSVD & lt; 2..1 & gt;
NC_TP_CPU_RSVD_NCTF & lt; 8..5 & gt;
TRUE
81 95
TBT_A_D2R_C_P & lt; 1..0 & gt;
TBT_A_D2R_C_N & lt; 1..0 & gt;
TBT_A_D2R_P & lt; 1..0 & gt;
TBT_A_D2R_N & lt; 1..0 & gt;
TBT_A_R2D_C_P & lt; 1..0 & gt;
TBT_A_R2D_C_N & lt; 1..0 & gt;
TBT_A_R2D_P & lt; 1..0 & gt;
TBT_A_R2D_N & lt; 1..0 & gt;
TBT_B_D2R_C_P & lt; 1..0 & gt;
TBT_B_D2R_C_N & lt; 1..0 & gt;
TBT_B_D2R_P & lt; 1..0 & gt;
TBT_B_D2R_N & lt; 1..0 & gt;
TBT_B_R2D_C_P & lt; 1..0 & gt;
TBT_B_R2D_C_N & lt; 1..0 & gt;
TBT_B_R2D_P & lt; 1..0 & gt;
TBT_B_R2D_N & lt; 1..0 & gt;
DP_TBTSNK0_ML_C_P & lt; 3..0 & gt;
DP_TBTSNK0_ML_C_N & lt; 3..0 & gt;
DP_TBTSNK0_ML_P & lt; 3..0 & gt;
DP_TBTSNK0_ML_N & lt; 3..0 & gt;
DP_TBTSNK0_AUXCH_C_P
DP_TBTSNK0_AUXCH_C_N
DP_TBTSNK0_AUXCH_P
DP_TBTSNK0_AUXCH_N
DP_TBTSNK1_ML_C_P & lt; 3..0 & gt;
DP_TBTSNK1_ML_C_N & lt; 3..0 & gt;
DP_TBTSNK1_ML_P & lt; 3..0 & gt;
DP_TBTSNK1_ML_N & lt; 3..0 & gt;
DP_TBTSNK1_AUXCH_C_P
DP_TBTSNK1_AUXCH_C_N
DP_TBTSNK1_AUXCH_P
DP_TBTSNK1_AUXCH_N
49
NC_SMC_FAN_3_TACH
NC_SMC_FAN_3_CTL
NC_SMC_FAN_2_TACH
NC_SMC_FAN_2_CTL
NC_FW2_TPBP
NC_FW2_TPBN
NC_FW2_TPBIAS
NC_FW2_TPAP
NC_FW2_TPAN
NC_FW0_TPBP
NC_FW0_TPBN
NC_FW0_TPAP
NC_ESTARLDO_EN
NC_ALS_GAIN
NC_USB_HUB_PRTPWR2
NC_USB_HUB_PRTPWR3
NC_USB_HUB_PRTPWR4
NC_USB_HUB_OCS2
NC_USB_HUB_OCS3
NC_USB_HUB_OCS4
NC_SMC_XOSC1
NC_SMC_ODD_DETECT
NC_SMC_SYS_LED
NC_SMC_HIB_L
NC_SMBUS_SMC_4_ASF_SDA
NC_SMBUS_SMC_4_ASF_SCL
NC_SMC_T25_EN_L
NC_SMC_T25_ISENSE
NC_ISNS_P1V5R1V35_CPUDDRP
NC_ISNS_P1V5R1V35_CPUDDRN
NC_ISNS_LCDBKLTP
NC_ISNS_LCDBKLTN
NC_ISNS_LCD_PANELP
NC_ISNS_LCD_PANELN
NC_ISNS_AIRPORTP
NC_ISNS_AIRPORTN
TRUE
NO_TEST
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TP_CPU_RSVD & lt; 65..62 & gt;
TP_CPU_RSVD & lt; 58..45 & gt;
TP_CPU_RSVD & lt; 43..32 & gt;
TP_CPU_RSVD & lt; 27..26 & gt;
TP_CPU_RSVD & lt; 24..15 & gt;
TP_CPU_RSVD & lt; 2..1 & gt;
TP_CPU_RSVD_NCTF & lt; 8..5 & gt;
60
NC NO_TESTs
NO_TEST
TRUE
41 44
57 59 96
TRUE
1
CPU NO_TESTs
NO_TEST=TRUE
57 59 96
2
61
59
49
49
8X 60
41 44
J9000 - eDP
7 8 96
18 25 41 43
17 41 43
PPVBAT_G3H_CONN
SMBUS_SMC_5_G3_SCL
SMBUS_SMC_5_G3_SDA
SYS_DETECT_L
GND
58
I1772
TRUE
3
ICT Test Points
J6950 - battery
4X 58
I1765
25 43 92
17 41 43 82
92
J5815 - kbd backlight
I1728
4
FUNC_TEST
TP_PCIE_PE5_D2RN
TP_PCIE_PE5_D2RP
TP_PCIE_PE5_R2D_CN
TP_PCIE_PE5_R2D_CP
7 8
I1717
TRUE
LPCPLUS_GPIO
LPCPLUS_RESET_L
LPC_AD & lt; 0 & gt;
LPC_AD & lt; 1 & gt;
LPC_AD & lt; 2 & gt;
LPC_AD & lt; 3 & gt;
LPC_CLK33M_LPCPLUS
LPC_FRAME_L
LPC_PWRDWN_L
LPC_SERIRQ
PM_CLKRUN_L
PP5V_S0
SMC_RESET_L
SMC_ROMBOOT
SMC_RX_L
SMC_TCK
SMC_TDI
SMC_TDO
SMC_TMS
SMC_TX_L
SPIROM_USE_MLB
SPI_ALT_CLK
SPI_ALT_CS_L
SPI_ALT_MISO
SPI_ALT_MOSI
TP_SMC_MD1
TP_SMC_TRST_L
GND
J5713 - keyboard
TRUE
I1712
I1653
J5100 - lpc + spi
TRUE
TRUE
ENET_CLKREQ_L
17 38
ENET_RESET_L
25
HDMI_EG_DDC_CLK
38 77
HDMI_EG_DDC_DATA
38 77
HDMI_HPD_L
38 42 82
I2C_DPMUX_A_SCL
44
I2C_DPMUX_A_SDA
44
PM_SLP_S3_L
7 18 27 38 41 70
PM_SLP_S4_L
18 27 34 38 40 41 70
PP1V5_S0_RIO
8
PP3V3_S3
7 3X P3V3_S3
8
PP3V3_S4
7 8
PP5V_S4
8 5X P5V_S4
SDCONN_STATE_CHANGE_RIO 25 38
SD_PWR_EN
9 38
USB_EXTB_OC_L
24 38
GND
10X GND
TRUE
TRUE
I1733
J5700 - ipd flex
38 77 95
I1818
TRUE
5
J6701 - audio flex
4
3
NC_CLINK_CLK
NC_CLINK_DATA
NC_CLINK_RESET_L
NC_PCIE_CLK100M_PEBN
NC_PCIE_CLK100M_PEBP
051-9589
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
2
4.18.0
BRANCH
PAGE
7 OF 132
SHEET
7 OF 99
1
SIZE
D
A
8
61 60
=PPBUS_G3H
7
6
PPBUS_G3H
G3H Rails
7
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
=PPBUS_S0_LCDBKLT
=PPVIN_S5_HS_OTHER_ISNS_R
46
46
46
D
46
=PPVIN_S5_HS_GPU_ISNS
67
66
65 66
64
46
=PPVIN_S5_HS_OTHER_ISNS
60
=PP18V5_DCIN_CONN
=PP18V5_DCIN_ISOL
=PP3V42_G3H_AUDIO
=PP3V42_G3H_TDM
=PP3V42_S3_HALL
58
60
42
For PCH RTC Power
=PPVRTC_G3_OUT
25
5V Rails
=PP5V_S5_LDO
63
69
61
VOLTAGE=18.5V
MAKE_BASE=TRUE
61
45
PP3V42_G3H
7
VOLTAGE=3.42V
MAKE_BASE=TRUE
=PP3V3_S5_LPCPLUS
=PP3V3_S5_SMC
=PP3V42_G3H_CHGR
=PP3V42_G3H_ONEWIREPROT
=PP3V42_G3H_PWRCTL
=PP3V42_G3H_SMBUS_SMC_5
=PP3V42_G3H_SMCUSBMUX
=PP3V42_G3H_TPAD
=PPVIN_S5_SMCVREF
=PPVBAT_G3_SYSCLK
43
41 42 78
61 70
60
70
44
40
49
42
25
=PPVRTC_G3_PCH
69
=PP5V_S3_FET
7
VOLTAGE=5V
MAKE_BASE=TRUE
69
69
49
PP5V_SUS
VOLTAGE=5V
MAKE_BASE=TRUE
23
PP5V_S4
7
VOLTAGE=5V
MAKE_BASE=TRUE
=PP5V_S4_RIO
=PP5V_S4_P5VS0FET
=PP5V_S4_P5VS3FET
=PP5V_S0_LCD
=PP5V_S3_LTUSB
=PP5V_S4_ISNS
=PP5V_S4_TPAD
=PP5V_S4_AUDIO
PP5V_S3
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm
38
69
69
81
40
49
53 59
7
VOLTAGE=5V
MAKE_BASE=TRUE
=PP5V_S3_ISNS
=PP5V_S3_ALSCAMERA
=PP5V_S3_DDRREG
69
=PP5V_S0_FET
99
34
64
=PP5V_S3_DEBUG_ADC_AVDD
=PP5V_S3_DEBUG_ADC_DVDD
=PP5V_S3_DEBUG_ISNS
=PP5V_S3_MEMRESET
PP5V_S0
=PP5V_S0_P1V5_LDO
3.3V Rails
A
69
=PP3V3_S4_FET
36
=PP3V3_S4_TBT_R
38
=PP3V3_S4_RIO
69
=PP3V3_SUS_FET
=PP5V_S0GPU_P1V0P1V35_GPU
=PP5V_S0_AUDIO_XW
=PP5V_S0_BKL
=PP5V_S0_CPUIMVP
=PP5V_S0_CPUVCCIOS0
=PP5V_S0_FAN_LT
=PP5V_S0_FAN_RT
=PP5V_S0_GFXIMVP
=PP5V_S0_KBDLED
=PP5V_S0_LPCPLUS
=PP5V_S0_PCH
=PP5V_S0_PCHVCCIOS0
=PP5V_S0_RMC
=PP5V_S0_VCCSAS0
=PP5V_S0_VMON
PP3V3_S4
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.1 MM
98
98
98
7
74
9
86
65 66
67
48
48
80
50
43
23 25
87
37
7
8
=PP1V5_S3RS0_FET_ISNS
69
27
38
=PP1V05_TBTCIO_FET
44
=PP1V5_S0_REG
68
26
=PP1V8_S0_PCH_VCC_DFTERM
=PPVDDIO_S0_SBCLK
=PP1V8_S0_P1V5_LDO
PP1V8_S0_CPU_VCCPLL_R
20 21 23
25
69
=PP3V3_S0GPU_MISC_FET
PP3V3_S0GPU_MISC
68
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.10MM
VOLTAGE=3.3V
MAKE_BASE=TRUE
VOLTAGE=1.8V
MAKE_BASE=TRUE
D
=PP3V3_GPU_MISC
PP1V5R1V35_S3
77
27
33
69
64
VOLTAGE=3.3V
45
PP1V5R1V35_MEM
28 29
30 31
PP1V5_S3RS0_CPUDDR
96
70
TP_P1V8GPU_EN
=P1V8GPU_EN
88
11 14 16 27
PP1V5_S0
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.5V
MAKE_BASE=TRUE
26
74
26
33
=PP1V5_S0_AUDIO
34
=PP3V3R1V5_S0_PCH_VCCSUSHDA
PP1V5R1V35_S0GPU
=PP1V5R1V35_GPU_REG
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.5V
MAKE_BASE=TRUE
21 23 25
PP1V5_S0_RIO
7
51
=PP1V5_S0_RIO_LDO
68
51
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
25
53
=PPVTT_S3_DDR_BUF
64 33
72 75 76
73
38
PPVTTDDR_S3
C
=PP1V35_GPU_FBVDDQ
=PP1V35_GPU_S0_FB
VOLTAGE=1.5V
MAKE_BASE=TRUE
=PP1V5_S0_RIO
7 96
7
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=0.75V
MAKE_BASE=TRUE
59
53 58
=PPVTT_S0_DDR_LDO
64
PP0V75_S0_DDRVTT
7
88
TP_GPU_PGOOD2
=PP1V8_GPU_FET
MIN_LINE_WIDTH=2 mm
MIN_NECK_WIDTH=0.17 mm
VOLTAGE=0.75V
MAKE_BASE=TRUE
86
47
13
82 83
44
35 78 82
68
=PP1V05_SUS_LDO
MAKE_BASE=TRUE
=PP0V75_S0_MEM_VTT_A
=PP0V75_S0_MEM_VTT_B
=PPVTT_S0_VTTCLAMP
PP1V05_SUS
32
32
74
PP1V0_S0GPU_ISNS
=PP1V05_S0GPU_REG
27
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
48
47
46
67
=PPCPUVCCIO_S0_REG
=PP1V05_SUS_PCH_JTAG
PP1V05_S0
24
7
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE
46
45 98 99
81
=PP1V05_S0_CPU_VCCIO
17 23
17 18 19 20 25 37
23
68
24
45
=PPVCORE_GPU_REG
=PP3V3_SUS_PCH_VCCSUS_USB
21 23
87
=PPPCHVCCIO_S0_REG
21 23
21 23
23
70 88
25
39
25 70
44
44
44
39
25
37
50
70
47
24
MIN_NECK_WIDTH=0.15 MM
MAKE_BASE=TRUE
20
7
VOLTAGE=1.0V
MAKE_BASE=TRUE
=PPVCORE_GPU
72 79
=PPVCORE_S0_GFX_REG
42
80
70
98
PP1V05_PCHVCCIO_S0
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE
=PP1V05_S0_PCH_VCCIO_PLLPCIE
=PP1V05_S0_PCH_VCCADPLL
=PP1V05_S0_PCH_VCCIO
=PP1V05_S0_PCH_VCCIO_PCIE
=PP1V05_S0_PCH_VCCIO_SATA
=PP1V05_S0_PCH_VCCIO_CLK
=PP1V05_S0_PCH_VCCIO_USB
=PP1V05_S0_PCH_VCC_CORE
=PP1V05_S0_PCH_VCCASW
=PP1V05_S0_PCH_VCCIO_CLK
=PP1V05_S0_PCH_VCCDIFFCLK
=PP1V05_S0_PCH
=PP1V05_S0_PCH_VCCSSC
=PP1V05_S0_PCH_V_PROC_IO
=PP1V05_S0_PCH_VCCIO_PLLUSB
=PP1V05_S0_PCH_VCC_DMI
=PP1V05_S0_PCH_VCCIO_PLLFDI
=PP1V05_S0_PCH_VCCDMI_FDI
=PP1V05_S0_P1V05TBTFET_R
GND
21
=LVDS_VCCA
23
21 23
21
MAKE_BASE=TRUE
18
17 21 23
Chipset " VCore " Rails
8 21 23
21 23
66
=PPVCORE_S0_CPU_REG
PPVCORE_S0_CPU
7
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
21 23
MAKE_BASE=TRUE
VOLTAGE=1.25V
=PPVCORE_S0_CPU
21 23
8 21 23
66 45
=PPVCORE_S0_AXG_REG
13 15 45 98
PPVCORE_S0_AXG
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
17 21 23
17 23
MAKE_BASE=TRUE
VOLTAGE=1.05V
=PPVCORE_S0_CPU_VCCAXG
13 14 16
21 23
16 13
21 23
=PP1V5_S3_CPU_VCCDQ
PP1V5_S3_CPU_VCCDQ
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
21
21 23
15 13
=PP1V05_S0_CPU_VCCPQE
99 62
=PPVCCSA_S0_REG
PP1V05_S0_CPU_VCCPQE
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
21
21
MAKE_BASE=TRUE
VOLTAGE=1.5V
VOLTAGE=1.05V
MAKE_BASE=TRUE
PPVCCSA_S0_REG
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
99
VOLTAGE=0.9V
MAKE_BASE=TRUE
=PPVCCSA_S0_CPU
13 16
VOLTAGE=12.8V
35 36 37
SYNC_DATE=01/13/2012
PAGE TITLE
37
VOLTAGE=1.05V
MAKE_BASE=TRUE
Power Aliases
Backlight Rails
99
36
=PPBUS_SW_BKL
PPBUS_SW_BKL
DRAWING NUMBER
MIN_LINE_WIDTH=0.5 MM
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.25 MM VOLTAGE=12.6V
PP1V05_TBTCIO
PPBUS_S0_LCDBKLT_PWR
VOLTAGE=1.05V
MAKE_BASE=TRUE
Apple Inc.
86
051-9589
REVISION
R
36
41
SMC_T25_EN_L
NC_SMC_T25_EN_L
7
NOTICE OF PROPRIETARY PROPERTY:
4.18.0
BRANCH
MAKE_BASE=TRUE
37 9
=PP15V_TBT_REG
PP15V_TBT
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=15V
MAKE_BASE=TRUE
=PPHV_SW_TBTAPWRSW
=PPHV_SW_TBTBPWRSW
70
42
6
5
B
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.085MM
VOLTAGE=0V
Defined here since TBT page does not know PBUS voltage
PPVIN_SW_TBTBST 37
I1679
25
=PP1V05_TBTCIO_RTR
21 23
77 79
PPVCORE_GPU
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
65
21 23
17 18 19 20
77
73 79
21 23
21 23
=PP3V3_SUS_PCH_GPIO
77
10 11 13 14 15
=PPVCCIO_S0_XDP
=PPVCCIO_S0_CPUIMVP
=PPVCCIO_S0_SMC
=PP1V05_S0_VMON
=PP1V05_S0_RMC
37
VOLTAGE=1.05V
MAKE_BASE=TRUE
=PP1V0_GPU_DPLL
=PP1V0_GPU_DP_AB
=PP1V0_GPU_DP_CD
=PP1V05_GPU_IFPCD_IOVDD
=PP1V05_GPU_IFPEF_IOVDD
=PP1V05_GPU_PEX_IOVDD
=PP1V05_GPU_PEX_PLLVDD
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
MAKE_BASE=TRUE
48
PP1V05_TBTLC
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
7
71 77 78 79
23
=PP1V5_S3RS0_VMON
=PP1V5_S3_CPU_VCCDDR
44
=PP1V05_TBTLC_RTR
37
=PP3V3_SUS_CNTRL
=PP3V3_SUS_SMC
80
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.5V
MAKE_BASE=TRUE
19 25
34
=PP3V3_SUS_PCH_VCCSUS_GPIO
=PP3V3_SUS_ROM
77
99
PP3V3_TBTLC
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
MAKE_BASE=TRUE
=PP3V3_SUS_PCH_VCCSUS
=PP3V3_SUS_PCH_VCC_SPI
=PP1V05_TBTLC_FET
25 42
PP3V3_SUS
=PP3V3_SUS_P1V05SUSLDO
=PP3V3_GPU_IFPX_PLLVDD
=PP3V3_S0_GFX3V3BIAS
=PP3V3_GPU_VDD33
15
SYNC_MASTER=D2_KEPLER
37
=PP3V3_S4_BT
21
=PP1V5R1V35_S3_MEM_A
=PP1V5R1V35_S3_MEM_B
34
82
VOLTAGE=3.3V
MAKE_BASE=TRUE
=PP3V3_TBT_PCH_GPIO
=PPVDDIO_TBT_CLK
=PP3V3_TBTLC_RTR
70
7
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.17 mm
VOLTAGE=1.5V
MAKE_BASE=TRUE
7
VOLTAGE=3.3V
MAKE_BASE=TRUE
=PP3V3_S3_BT
=PP3V3_S3_DPMUX_UC
=PP3V3_S3_ISNS
=PP3V3_S3_MEMRESET
=PP3V3_S3_PCH_GPIO
=PP3V3_S3_RIO
=PP3V3_S3_SMBUS_SMC_2_S3
=PP3V3_S3_SMBUS_SMC_3
=PP3V3_S3_TPAD
=PP3V3_S3_USBMUX
=PP3V3_S3_USB_HUB
=PP3V3_S3_USB_RESET
=PP3V3_S3_VREFMRGN
=PP3V3_S3_WLAN
=PP3V3_S3_GYRO
=PP3V3_S3_SMS
=PP3V3_S3_SDBUF
PP3V3_S0
MIN_LINE_WIDTH=0.4 MM
62
49
MIN_NECK_WIDTH=0.2 MM
52
=PP3V3_TBTLC_FET
98
VOLTAGE=3.3V
MAKE_BASE=TRUE
=PP3V3_S4_SMC
=PPVIN_S3_MEM_ISNS
45
TBT RAILS
=PP3V3_S4_TPAD
MIN_LINE_WIDTH=0.6 MM
23 21
PP3V3_S3
=PP3V3_S0_SB_PM
=PP3V3_S0_SMBUS_PCH
=PP3V3_S0_SMBUS_SMC_0_S0
=PP3V3_S0_SMBUS_SMC_1_S0
=PP3V3_S0_SSD
=PP3V3_S0_SYSCLK
=PP3V3_S0_TBTI2C
=PP3V3_S0_TBTPWRCTL
=PP3V3_S0_TPAD
=PP3V3_S0_VMON
=PP3V3_S0_X29THMSNS
=PP3V3_S0_XDP
=PP3V3_S0_DDR3THMSNS
=PP3V3_S0_SPKRTHMSNS
27
VOLTAGE=5V
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
68
85
=PP3V3_S0_AUDIO
=PP3V3_S0_AUDIO_DIG
=PP3V3_S0_BKL_VDDIO
=PP3V3_S0_CPUTHMSNS
=PP3V3_S0_CPU_VCCIO_SEL
=PP3V3_S0_DPMUX
=PP3V3_S0_DPMUXI2C
=PP3V3_S0_DPMUX_UC
=PP3V3_S0_FAN_LT
=PP3V3_S0_FAN_RT
=PP3V3_S0_GPUTHMSNS
=PP3V3_S0_HS_ISNS
=PP3V3_S0_IMVPISNS
=PP3V3_S0_ISNS
=PP3V3_S0_LCD
=PP3V3_S0_P1V8GPUFET
=PP3V3_S0_P3V3TBTFET
=PP3V3_S0_PCH
=PP3V3_S0_PCH_GPIO
=PP3V3_S0_PCH_VCC3_3_CLK
=PP3V3_S0_PCH_VCC3_3_GPIO
=PP3V3_S0_PCH_VCC3_3_HVCMOS
=PP3V3_S0_PCH_VCC3_3_PCI
=PP3V3_S0_PCH_VCC3_3_SATA
=PP3V3_S0_PCH_VCCADAC
=PP3V3_S0_PWRCTL
=PP3V3_S0_RSTBUF
=PP3V3_S0_SATAMUX
17 18 21
PP5V_S5
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm
B
=PP3V3_S0_FET
VOLTAGE=3.42V
MAKE_BASE=TRUE
=PP5V_SUS_PCH
=PP5V_S4_REG
24
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.075 mm
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
63
69
PPVRTC_G3H
PP3V3_S0GPU
84
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
=PP5V_S5_P1V5S3RS0FET
=PP5V_S5_P5VSUSFET
=PP5V_S5_TPAD
=PP5V_SUS_FET
=PP3V3_S3_FET
7
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.1 MM
69
70
=PP3V3_S4_TBTBPWRSW
=PP3V3_S0GPU_FET
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.10MM
VOLTAGE=3.3V
MAKE_BASE=TRUE
=PP1V5_S3_MEMRESET
=PPDDR_S3_MEMVREF
=PPVIN_S3_P1V5S3RS0_FET
=PPVIN_S0_DDRREG_LDO
=PPVIN_S3_MEM_ISNS_R
25
=PP3V3_S4_TBTAPWRSW
" GPU " Rails
88 69
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.17 mm
VOLTAGE=1.5V
MAKE_BASE=TRUE
42
=PP3V3_S5_VMON
74
=PPDCIN_S5_CHGR
PPDCIN_G3H_ISOL
=PPDDR_S3_REG
64
70
VOLTAGE=18.5V
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
63
70
=PP3V3_S5_SMCBATLOW
=PP3V3_S5_SYSCLK
1
7
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
18
=PP3V3_S5_PWRCTL
=PPVIN_S5_P5VP3V3
PPDCIN_G3H
=PP1V8_S0_CPU_VCCPLL_R
15 13
20
VOLTAGE=12.8V
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
C
69
80
=PPDCIN_S5_CHGR_ISOL
=PPDCIN_S5_VSENSE
=PP3V42_G3H_REG
68
=PP3V3_S5_XDP
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
60
68
21 23
VOLTAGE=12.8V
MAKE_BASE=TRUE
PP1V8_S0
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.5V
MAKE_BASE=TRUE
=PP1V8_S0_PCH_VCCTX_LVDS
27
=PP3V3_S5_PCH_VCCDSW
PPVIN_S5_HS_OTHER_ISNS
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
60
69
=PP3V3_S5_PCH_GPIO
2
=PP1V8R1V5_S0_PCH_VCCVRM
=PP1V8_S0_AUDIO
=PP1V8_S0_CPU_VCCPLL
=PP1V8_S0_GPUFET
69
87
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
4A max supply
69
62
PPVIN_S5_HS_GPU_ISNS
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
=PP1V8_S0_REG
68
69
=PP3V3_S5_PCHPWRGD
VOLTAGE=12.8V
MAKE_BASE=TRUE
=PPVIN_S0_GFXIMVP
=PPVIN_S0GPU_P1V5P1V0
3
1.8V/1.5V/1.2V/1.05V Rails
69
=PP3V3_S4_DPBPWRSW
=PP3V3_S4_P3V3S4FET
=PP3V3_S5_CPU_VCCDDR
=PP3V3_S5_P1V2P1V8
=PP3V3_S5_P1V5S0
=PP3V3_S5_P3V3SUSFET
=PP3V3_S5_PCH
45
=PPVIN_S0_CPUIMVP
=PPVIN_S3_DDRREG
=PPVIN_S0_CPUVCCIOS0
=PPVIN_S0_CPUAXG
=PPVIN_S0_VCCSAS0
=PPVIN_S0_PCHVCCIOS0
4
7 96
VOLTAGE=3.3V
MAKE_BASE=TRUE
=PP3V3_S4_DPAPWRSW
9 37
PPVIN_S5_HS_COMPUTING_ISNS
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
5
PP3V3_S5
=PP3V3_GPU_P3V3GPUFET
=PP3V3_GPU_MISC_P3V3GPUMISCFET
=PP3V3_S0_P3V3S0FET
=PP3V3_S3_P3V3S3FET
86
=PPVIN_S5_HS_GPU_ISNS_R
=PPVIN_SW_TBTBST
=PPBUS_S0_VSENSE
=PPBUS_G3H_T25_R
=PPVIN_S5_HS_COMPUTING_ISNS
=PP3V3_S5_REG
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
=PPVIN_S5_HS_COMPUTING_ISNS_R
46
63
VOLTAGE=12.8V
MAKE_BASE=TRUE
84
99 37
=PP1V05_S0_P1V05TBTFET
PP1V05_S0_P1V05TBTFET
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
85
4
VOLTAGE=1.05V
MAKE_BASE=TRUE
3
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
2
PAGE
8 OF 132
SHEET
8 OF 99
1
SIZE
D
A
8
7
6
5
4
Frame Holes
ZT0915
3
T29 / GMUX JTAG Signals
GND_BATT_CHGND
ZT0970
TH-NSP
GND_CHASSIS_MLBCAN1
ZT0950
TH-NSP
1
GND_CHASSIS_FAN
=DDRVTT_EN
TBT_LSOE & lt; 3 & gt;
TBT_LSOE & lt; 2 & gt;
TBT_LSEO_LSOE3
TBT_LSEO & lt; 3 & gt;
Unused PEG signals
NC_PEG_D2R_P & lt; 15..14 & gt;
=PEG_D2R_P & lt; 15..14 & gt;
NO_TEST=TRUE
TBT_LSEO_LSOE2
TBT_LSEO & lt; 2 & gt;
MAKE_BASE=TRUE
NO_TEST=TRUE
1
GND_CHASSIS_MLBCAN3
MAKE_BASE=TRUE
MAKE_BASE=TRUE
EG_RESET_L
82
GPU_RESET_L
82
SL-1.1X0.45-1.4x0.75
18
LVDS_IG_BKL_ON
18
THERMAL MODULE STANDOFFS
EG_CLKREQ_IN_L
78 82
EG_CLKREQ_OUT_L
82
82
SH0926
STDOFF-4.5OD2.15H-SM
STDOFF-4.5OD2.15H-SM
STDOFF-4.5OD2.15H-SM
DP_TBTSNK0_HPD_IG
82
STDOFF-4.5OD1.8H-SM
DPB_IG_HPD
STDOFF-4.5OD2.15H-SM
PCIE_EXCARD_D2R_N
PCIE_EXCARD_D2R_P
PCIE_EXCARD_R2D_C_N
PCIE_EXCARD_R2D_C_P
MAKE_BASE=TRUE
17
SH0923
17
STDOFF-4.5OD1.8H-SM
17
1
1
PEG_D2R_P & lt; 7..0 & gt;
PEG_D2R_N & lt; 7..0 & gt;
10
MAKE_BASE=TRUE
=PEG_D2R_N & lt; 7..0 & gt;
10
MAKE_BASE=TRUE
89 71
=PEG_R2D_C_P & lt; 7..0 & gt;
10
=PEG_R2D_C_N & lt; 7..0 & gt;
PEG_R2D_C_N & lt; 7..0 & gt;
10
MAKE_BASE=TRUE
SH0930
MAKE_BASE=TRUE
NC_PCIE_CLK100M_EXCARD_P
TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
TBT_D2R_N & lt; 3..2 & gt;
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
TBT_R2D_C_P & lt; 3..2 & gt;
MAKE_BASE=TRUE
NC_TBT_R2D_CP & lt; 3..2 & gt;
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NC_TBT_R2D_CN & lt; 3..2 & gt;
MAKE_BASE=TRUE
TP_PCH_CLKOUT_DPN
DPLL_REF_CLKN
TRUE
MAKE_BASE=TRUE
17
TP_PCH_CLKOUT_DPP
DPLL_REF_CLKP
TRUE
MAKE_BASE=TRUE
11 89
17
TP_PCH_GPIO64_CLKOUTFLEX0
17
TP_PCH_GPIO65_CLKOUTFLEX1
17
TP_PCH_GPIO66_CLKOUTFLEX2
17
PCIE_FW_R2D_C_P
TP_PCH_GPIO67_CLKOUTFLEX3
APN 806-2247
BR0901
DPMUX_UC_RX
SATA_ODD_D2R_N
17 91
SATA_ODD_D2R_P
17 91
SATA_ODD_R2D_C_N
17 91
SATA_ODD_R2D_C_P
17 91
NO_TEST=TRUE
82
82
NC_SATA_ODD_D2R_P
SSD PCIE SIGNALS
PCIE_SSD_D2R_P & lt; 1..0 & gt;
=PEG_D2R_P & lt; 13..12 & gt;
92 39
NC_SATA_ODD_R2D_C_N
25
MAKE_BASE=TRUE
=PEG_D2R_N & lt; 13..12 & gt;
PCIE_SSD_D2R_N & lt; 1..0 & gt;
25
FW_PWR_EN
MAKE_BASE=TRUE
10
MAKE_BASE=TRUE
20 24 25
ENET_LOW_PWR
SD_PWR_EN
NC_SATA_ODD_D2R_N
MAKE_BASE=TRUE
92 39
ENET_LOW_PWR_PCH
TP_FW_PWR_EN
TH
SM
DPMUX_UC_TX
DPMUX_UC_BOOT_RX
10
NC_SATA_ODD_R2D_C_P
MAKE_BASE=TRUE
PCIE_SSD_R2D_C_P & lt; 1..0 & gt;
92 39
MAKE_BASE=TRUE
=PEG_R2D_C_P & lt; 13..12 & gt;
10
=PEG_R2D_C_N & lt; 13..12 & gt;
10
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MLB-MTG-BRKT-J5
PCIE_SSD_R2D_C_N & lt; 1..0 & gt;
92 39
MAKE_BASE=TRUE
MAKE_BASE=TRUE
1
TP_PCIE_CLK100M_FW_P
SM
SHLD-J5-CAN-FENCE-MDP-2
DPMUX_UC_BOOT_TX
MAKE_BASE=TRUE
38 7
SM
17
C
MAKE_BASE=TRUE
NC_PCH_GPIO64_CLKOUTFLEX0
TRUE
MAKE_BASE=TRUE
NC_PCH_GPIO65_CLKOUTFLEX1
TRUE
MAKE_BASE=TRUE
NC_PCH_GPIO66_CLKOUTFLEX2
TRUE
MAKE_BASE=TRUE
NC_PCH_GPIO67_CLKOUTFLEX3
TRUE
MAKE_BASE=TRUE
SD_PWR_EN_PCH
SHLD-J5-USB
82
MAKE_BASE=TRUE
1
SH0951
MAKE_BASE=TRUE
82
STDOFF-4.9OD2.38H-SM-SL-2.6X2NP-2
1
17
NO_TEST=TRUE
11 89
SH0945
SH0952
17
PCIE_FW_R2D_C_N
NO_TEST=TRUE
NC_PCIE_FW_R2D_CP
DPMUX TX & RX
17
1
17
PCIE_FW_D2R_P
NO_TEST=TRUE
NC_PCIE_FW_R2D_CN
NO_TEST=TRUE
1
SH0950
18
PCIE_FW_D2R_N
NO_TEST=TRUE
NC_PCIE_FW_D2RP
NO_TEST=TRUE
1
1
18
LVDS_IG_DDC_DATA
NO_TEST=TRUE
NC_PCIE_FW_D2RN
NO_TEST=TRUE
MAKE_BASE=TRUE
STDOFF-4.9OD2.38H-SM-2
18 91
LVDS_IG_DDC_CLK
NO_TEST=TRUE
NC_LVDS_IG_DDC_DATA
NC_TBT_D2RN & lt; 3..2 & gt;
TBT_R2D_C_N & lt; 3..2 & gt;
SH0946
18 91
LVDS_IG_B_DATA_P & lt; 2..0 & gt;
NO_TEST=TRUE
NC_LVDS_IG_DDC_CLK
UNUSED TBT PORTS
TBT_D2R_P & lt; 3..2 & gt;
NC_TBT_D2RP & lt; 3..2 & gt;
1
STDOFF-4.5OD2.15H-SM
18 91
LVDS_IG_B_DATA_N & lt; 2..0 & gt;
NC_LVDS_IG_B_DATA_P & lt; 2..0 & gt;
MAKE_BASE=TRUE
STDOFF-4.5OD1.9H-SM
SH0922
18 91
LVDS_IG_A_DATA_P & lt; 2..0 & gt;
NO_TEST=TRUE
NC_LVDS_IG_B_DATA_N & lt; 2..0 & gt;
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
SH0924
LVDS_IG_A_DATA_N & lt; 2..0 & gt;
NO_TEST=TRUE
NC_LVDS_IG_A_DATA_P & lt; 2..0 & gt;
MAKE_BASE=TRUE
PEG_R2D_C_P & lt; 7..0 & gt;
NC_PCIE_CLK100M_EXCARD_N
PCIE_CLK100M_EXCARD_N
PCIE_CLK100M_EXCARD_P
92 17
18 91
NO_TEST=TRUE
NC_LVDS_IG_A_DATA_N & lt; 2..0 & gt;
=PEG_D2R_P & lt; 7..0 & gt;
89 71
1
92 17
18 91
LVDS_IG_A_CLK_P
NO_TEST=TRUE
NC_LVDS_IG_A_CLK_P
18 82
NC_PCIE_EXCARD_D2R_N
NC_PCIE_EXCARD_D2R_P
NC_PCIE_EXCARD_R2D_C_N
NC_PCIE_EXCARD_R2D_C_P
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
LVDS_IG_A_CLK_N
NC_LVDS_IG_A_CLK_N
MAKE_BASE=TRUE
17
1
10
MAKE_BASE=TRUE
89 88 71
STDOFF-4.5OD2.15H-SM
10
=PEG_R2D_C_N & lt; 11..8 & gt;
GPU signals
MAKE_BASE=TRUE
SH0928
18
NO_TEST=TRUE
18 82
1
SH0929
=PEG_R2D_C_P & lt; 11..8 & gt;
MAKE_BASE=TRUE
DPA_IG_HPD
DP_TBTSNK1_HPD_IG
1
18
LVDS_IG_B_DATA_N & lt; 3 & gt;
NC_LVDS_IG_B_DATAN & lt; 3 & gt;
MAKE_BASE=TRUE
89 88 71
1
LVDS_IG_B_DATA_P & lt; 3 & gt;
NO_TEST=TRUE
10
PCIE_TBT_R2D_C_N & lt; 3..0 & gt;
MAKE_BASE=TRUE
SH0925
=PEG_D2R_N & lt; 11..8 & gt;
PCIE_TBT_R2D_C_P & lt; 3..0 & gt;
92 35
MAKE_BASE=TRUE
SH0927
10
MAKE_BASE=TRUE
92 35
PEG_CLKREQ_L
18 91
MAKE_BASE=TRUE
MAKE_BASE=TRUE
SH0920
PCIE_TBT_D2R_N & lt; 3..0 & gt;
82
LVDS_IG_A_DATA_N & lt; 3 & gt;
NO_TEST=TRUE
NC_LVDS_IG_B_DATAP & lt; 3 & gt;
=PEG_D2R_P & lt; 11..8 & gt;
MAKE_BASE=TRUE
IG_LCD_PWR_EN
PEX_CLKREQ_L
17
STDOFF-4.5OD2.15H-SM
MAKE_BASE=TRUE
MAKE_BASE=TRUE
PCIE_TBT_D2R_P & lt; 3..0 & gt;
92 35
LVDS_IG_PANEL_PWR
18 91
NO_TEST=TRUE
NC_LVDS_IG_A_DATAN & lt; 3 & gt;
T29 Signals Through PEG
MAKE_BASE=TRUE
STDOFF-4.5OD2.15H-SM-1
10
LVDS_IG_A_DATA_P & lt; 3 & gt;
NO_TEST=TRUE
92 35
MAKE_BASE=TRUE
SH0921
=PEG_R2D_C_N & lt; 15..14 & gt;
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
1
10
NO_TEST=TRUE
71 78
IG_BKLT_EN
NC_LVDS_IG_A_DATAP & lt; 3 & gt;
=PEG_R2D_C_P & lt; 15..14 & gt;
NC_PEG_R2D_C_N & lt; 15..14 & gt;
MAKE_BASE=TRUE
1
D
10
NO_TEST=TRUE
MAKE_BASE=TRUE
GMUX ALIASES
ZT0973
TH-NSP
GND_CHASSIS_MLBCAN4
=PEG_D2R_N & lt; 15..14 & gt;
NC_PEG_R2D_C_P & lt; 15..14 & gt;
GND_CHASSIS_MLBCAN6
SL-1.1X0.45-1.4x0.75
10
NO_TEST=TRUE
NC_PEG_D2R_N & lt; 15..14 & gt;
SL-1.1X0.45-1.4x0.75
GND
27 64
MAKE_BASE=TRUE
MAKE_BASE=TRUE
ZT0975
TH-NSP
1
CPU_VTTSELECT
MAKE_BASE=TRUE
MEMVTT_EN
27
ZT0972
TH-NSP
GND_CHASSIS_MLBCAN5
SL-1.1X0.45-1.4x0.75
C
TP_CPU_VTT_SELECT
1
SL-1.1X0.45-1.4x0.75
ZT0974
TH-NSP
1
CPUIMVP_VID & lt; 0..6 & gt;
MAKE_BASE=TRUE
ZT0971
TH-NSP
GND_CHASSIS_MLBCAN2
D
CPU_VID & lt; 0..6 & gt;
1
SL-1.1X0.45-1.4x0.75
SL-2.3X3.9-2.9X4.5
1
1
CPU signals
2.8R2.3
1
2
SHLD-J5-CAN-FENCE-MDP-1
PCIE_CLK100M_FW_P
17 92
PCIE_CLK100M_FW_N
17 92
MAKE_BASE=TRUE
TP_PCIE_CLK100M_FW_N
MAKE_BASE=TRUE
NC_DP_IG_MLP & lt; 3..0 & gt;
MAKE_BASE=TRUE
TP_DP_IG_B_MLP & lt; 3..0 & gt;
POGO PINS
SMT GND TEST PONTS
NC_PCH_FDI_DATA_N & lt; 7..0 & gt;
MAKE_BASE=TRUE
B
ZT0990
SH0932
POGO-2.3OD-5.5H-SM-LOW-FORCE
POGO-2.3OD-5.5H-SM-LOW-FORCE
SM
SM
1
SM
1
2.1SM2.0MM-CIR
2.1SM2.0MM-CIR
SMT-PAD-NSP
1
MAKE_BASE=TRUE
ZT0992
SMT-PAD-NSP
1
POGO-2.3OD-5.5H-SM-LOW-FORCE
ZT0991
2.1SM2.0MM-CIR
SH0933
SMT-PAD-NSP
1
=FDI_DATA_N & lt; 7..0 & gt;
18
=FDI_DATA_P & lt; 7..0 & gt;
18
=FDI_FSYNC & lt; 1..0 & gt;
18
NC_PCH_FDI_FSYNC & lt; 1..0 & gt;
MAKE_BASE=TRUE
R0950
37 8
=PPVIN_SW_TBTBST
NC_PCH_FDI_LSYNC & lt; 1..0 & gt;
MAKE_BASE=TRUE
=FDI_LSYNC & lt; 1..0 & gt;
0
2
8 37
=PP15V_TBT_REG
B
SYNC_DATE=01/13/2012
1
A
5%
1/8W
MF-LF
805
NO_TEST=TRUE
18
NO_TEST=TRUE
1
MAKE_BASE=TRUE
SH0936
POGO-2.3OD-5.5H-SM-LOW-FORCE
POGO-2.3OD-5.5H-SM-LOW-FORCE
POGO-2.3OD-5.5H-SM-LOW-FORCE
SM
SM
10 89
FDI_DATA_P & lt; 7..0 & gt;
10 89
NC_CPU_FDI_FSYNC & lt; 1..0 & gt;
NC_CPU_FDI_LSYNC & lt; 1..0 & gt;
MAKE_BASE=TRUE
10 89
NC_USB3_EXTD_TX_N
FDI_LSYNC & lt; 1..0 & gt;
10 89
NC_USB3_EXTD_RX_P
MAKE_BASE=TRUE
SM
1
1
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
SH0960
91 34
2.8OD1.2ID-1.35H-SM
26
USBHUB_DN1_N
USB_BT_P
26
MAKE_BASE=TRUE
MAKE_BASE=TRUE
91 34
1
USB_BT_N
91 49
USB_TPAD_P
91 49
SH0941
SH0944
SH0961
USBHUB_DN2_P
26
USBHUB_DN2_N
2.8OD1.2ID-1.35H-SM
2.8OD1.2ID-1.35H-SM
2.8OD1.2ID-1.35H-SM
2.8OD1.2ID-1.35H-SM
1
1
26
USBHUB_DN3_P
26
USBHUB_DN3_N
USB_TPAD_N
26
USBHUB_DN4_P
26
MAKE_BASE=TRUE
91 41
USB_SMC_P
MAKE_BASE=TRUE
1
91 41
USB_SMC_N
MAKE_BASE=TRUE
PU_USBHUB_DN4P
MAKE_BASE=TRUE
Digital Ground
A
PU_USBHUB_DN4N
2.8OD1.2ID-1.35H-SM
20
SH0943
2.8OD1.2ID-1.35H-SM
1
20
1
20
MLB_RAMCFG1
1
R09101
1K
5%
1/20W
MF
201 2
6
R09121
RAMCFG1:L
MLB_RAMCFG0
RAMCFG0:L
7
RAMCFG2:L
R0911
1K
5%
1/20W
MF
201 2
1K
5%
1/20W
MF
201 2
R09131
19 91
USB3_EXTC_TX_N
19 91
USB3_EXTC_RX_P
19 91
USB3_EXTC_RX_N
19 91
USB_EXTC_P
19 91
USB_EXTC_N
NO_TEST=TRUEI1188
NC_USB3_EXTC_TX_N
MAKE_BASE=TRUE
NO_TEST=TRUEI1189
NC_USB3_EXTC_RX_P
MAKE_BASE=TRUE
NO_TEST=TRUEI1190
NC_USB3_EXTC_RX_N
MAKE_BASE=TRUE
NO_TEST=TRUEI1192
NC_USB_EXTC_P
MAKE_BASE=TRUE
NO_TEST=TRUEI1191
NC_USB_EXTC_N
USBHUB_DN4_N
19 91
NO_TEST=TRUE
26
SYNC_MASTER=D2_KEPLER
PAGE TITLE
8
=PP5V_S0_AUDIO_XW
Signal Aliases
1K
5%
1/20W
MF
201 2
DRAWING NUMBER
XW0902
Apple Inc.
SM
1
2
XW0903
PP5V_S0_AUDIO_AMP_L
57
MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=5V
2
PP5V_S0_AUDIO_AMP_R
MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=5V
4
3
57
051-9589
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
SM
1
5
19
USB3_EXTC_TX_P
NO_TEST=TRUEI1187
NC_USB3_EXTC_TX_P
MAKE_BASE=TRUE
RAMCFG3:L
MLB_RAMCFG2
19
USB_EXTD_EHCI_N
NO_TEST=TRUE
MAKE_BASE=TRUE
MLB_RAMCFG3
20
SH0942
19
USB_EXTD_EHCI_P
NO_TEST=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
SH0940
19
USB3_EXTD_RX_N
NO_TEST=TRUE
NC_USB_EXTD_EHCI_N
MAKE_BASE=TRUE
MAKE_BASE=TRUE
19
USB3_EXTD_RX_P
NO_TEST=TRUE
NC_USB_EXTD_EHCI_P
USB SIGNALS
USBHUB_DN1_P
19
USB3_EXTD_TX_N
NC_USB3_EXTD_RX_N
1
1
UNUSED USB SIGNALS
USB3_EXTD_TX_P
NO_TEST=TRUE
FDI_FSYNC & lt; 1..0 & gt;
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_USB3_EXTD_TX_P
MAKE_BASE=TRUE
NO_TEST=TRUE
SMT-PAD-NSP
1
SM
SH0935
MAKE_BASE=TRUE
2.1SM2.0MM-CIR
POGO-2.3OD-5.5H-SM-LOW-FORCE
SH0934
FDI_DATA_N & lt; 7..0 & gt;
NO_TEST=TRUE
NC_CPU_FDI_DATA_P & lt; 7..0 & gt;
ZT0993
SH0937
8
TBTBST:N
NO_TEST=TRUE
NC_CPU_FDI_DATA_N & lt; 7..0 & gt;
1
18
NO_TEST=TRUE
NO_TEST=TRUE
NC_PCH_FDI_DATA_P & lt; 7..0 & gt;
SH0931
MAKE_BASE=TRUE
18
TP_DP_IG_B_MLN & lt; 3..0 & gt;
NO_TEST=TRUE
NC_DP_IG_MLN & lt; 3..0 & gt;
UNUSED FDI SIGNALS
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
2
4.18.0
BRANCH
PAGE
9 OF 132
SHEET
9 OF 99
1
SIZE
D
8
7
6
5
4
=PP1V05_S0_CPU_VCCIO
1
OMIT_TABLE
U1000
BGA
IN
R8
89 18
IN
DMI_S2N_N & lt; 3 & gt;
U10
N8
89 18
89 18
IN
DMI_S2N_P & lt; 1 & gt;
T9
89 18
IN
DMI_S2N_P & lt; 2 & gt;
R6
89 18
D
IN
DMI_S2N_P & lt; 0 & gt;
IN
DMI_S2N_P & lt; 3 & gt;
U8
89 18
OUT
DMI_N2S_N & lt; 0 & gt;
N4
89 18
OUT
DMI_N2S_N & lt; 1 & gt;
R4
89 18
OUT
DMI_N2S_N & lt; 2 & gt;
OUT
DMI_N2S_N & lt; 3 & gt;
89 18
P1
U6
N2
OUT
DMI_N2S_P & lt; 0 & gt;
OUT
DMI_N2S_P & lt; 1 & gt;
89 18
OUT
DMI_N2S_P & lt; 2 & gt;
P3
89 18
OUT
DMI_N2S_P & lt; 3 & gt;
T5
89 18
89 18
R2
OUT
FDI_DATA_N & lt; 0 & gt;
V7
OUT
FDI_DATA_N & lt; 1 & gt;
W8
89 9
OUT
FDI_DATA_N & lt; 2 & gt;
AA8
89 9
OUT
FDI_DATA_N & lt; 3 & gt;
AC10
89 9
89 9
U4
89 9
OUT
FDI_DATA_N & lt; 4 & gt;
89 9
OUT
FDI_DATA_N & lt; 5 & gt;
W2
89 9
OUT
FDI_DATA_N & lt; 6 & gt;
V1
89 9
OUT
FDI_DATA_N & lt; 7 & gt;
Y5
W6
OUT
FDI_DATA_P & lt; 0 & gt;
89 9
OUT
FDI_DATA_P & lt; 1 & gt;
89 9
OUT
FDI_DATA_P & lt; 2 & gt;
Y9
89 9
OUT
FDI_DATA_P & lt; 3 & gt;
AA10
89 9
C
89 9
W10
FDI_DATA_P & lt; 4 & gt;
OUT
U2
W4
89 9
OUT
FDI_DATA_P & lt; 5 & gt;
89 9
OUT
FDI_DATA_P & lt; 6 & gt;
V3
OUT
FDI_DATA_P & lt; 7 & gt;
AA6
89 9
89 9
IN
FDI_FSYNC & lt; 0 & gt;
AC8
89 9
IN
FDI_FSYNC & lt; 1 & gt;
AA2
89 18
IN
FDI_INT
AD9
89 9
IN
FDI_LSYNC & lt; 1 & gt;
AB3
89 9
IN
FDI_LSYNC & lt; 0 & gt;
AB7
89 82
OUT
DP_INT_IG_ML_N & lt; 0 & gt;
AG2
89 82
OUT
DP_INT_IG_ML_N & lt; 1 & gt;
AF1
89 82
OUT
DP_INT_IG_ML_N & lt; 2 & gt;
AE6
89 82
OUT
DP_INT_IG_ML_N & lt; 3 & gt;
AG6
89 82
OUT
DP_INT_IG_ML_P & lt; 0 & gt;
AG4
89 82
OUT
DP_INT_IG_ML_P & lt; 1 & gt;
AF3
89 82
OUT
DP_INT_IG_ML_P & lt; 2 & gt;
AF7
89 82
OUT
DP_INT_IG_ML_P & lt; 3 & gt;
AG8
89 82
BI
DP_INT_IG_AUX_P
AE4
89 82
BI
DP_INT_IG_AUX_N
AE2
15 14 13 11 10 8 =PP1V05_S0_CPU_VCCIO
1
OMIT_TABLE
1K
5%
2
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
AB1
DMI_TX0*
DMI_TX1*
DMI_TX2*
DMI_TX3*
DMI_TX0
DMI_TX1
DMI_TX2
DMI_TX3
FDI0_TX0*
FDI0_TX1*
FDI0_TX2*
FDI0_TX3*
FDI1_TX0*
FDI1_TX1*
FDI1_TX2*
FDI1_TX3*
FDI0_TX0
FDI0_TX1
FDI0_TX2
FDI0_TX3
FDI1_TX0
FDI1_TX1
FDI1_TX2
FDI1_TX3
FDI0_FSYNC
FDI1_FSYNC
FDI_INT
D
PEG_RX0
PEG_RX1
PEG_RX2
PEG_RX3
PEG_RX4
PEG_RX5
PEG_RX6
PEG_RX7
PEG_RX8
PEG_RX9
PEG_RX10
PEG_RX11
PEG_RX12
PEG_RX13
PEG_RX14
PEG_RX15
PEG_TX0*
PEG_TX1*
PEG_TX2*
PEG_TX3*
PEG_TX4*
PEG_TX5*
PEG_TX6*
PEG_TX7*
PEG_TX8*
PEG_TX9*
PEG_TX10*
PEG_TX11*
PEG_TX12*
PEG_TX13*
PEG_TX14*
PEG_TX15*
FDI1_LSYNC
FDI0_LSYNC
EDP_TX0*
EDP_TX1*
EDP_TX2*
EDP_TX3*
EDP_TX0
EDP_TX1
EDP_TX2
EDP_TX3
EDP_AUX
EDP_AUX*
EDP_ICOMPO
EDP_COMPIO
AE8
DP_INT_IG_HPD_L
PEG_TX0
PEG_TX1
PEG_TX2
PEG_TX3
PEG_TX4
PEG_TX5
PEG_TX6
PEG_TX7
PEG_TX8
PEG_TX9
PEG_TX10
PEG_TX11
PEG_TX12
PEG_TX13
PEG_TX14
PEG_TX15
EDP_HPD*
3
Q1031
82
1
DP_INT_IG_HPD
IN
2N7002TXG
G
SOT-523-3
S
89 24 10
CPU_CFG & lt; 6 & gt;
2
G2
1%
1/16W
MF-LF
402
89 CPU_PEG_COMP
H1
F3
=PEG_D2R_N & lt; 0 & gt;
IN
U1000
BB57
IVY-BRIDGE
BB43
BGA
BB25
(IPU)
(5 OF 11)
RESERVED
BB17
(IPU)
OMIT_TABLE
CPU_CFG & lt; 0 & gt;
B57
89 24 10
F23
CPU_CFG & lt; 1 & gt;
D57
89 24 10
CPU_CFG & lt; 2 & gt;
B55
89 24 10
CPU_CFG & lt; 3 & gt;
A54
89 24 10
CPU_CFG & lt; 4 & gt;
A58
89 24 10
CPU_CFG & lt; 5 & gt;
D55
(IPU)
BB13
89 24 10
CPU_CFG & lt; 6 & gt;
C56
(IPU)
BA48
89 24 10
CPU_CFG & lt; 7 & gt;
E54
(IPU)
BA16
89 24
CPU_CFG & lt; 8 & gt;
J54
(IPU)
AY45
89 24
CPU_CFG & lt; 9 & gt;
G56
(IPU)
AY41
89 24
CPU_CFG & lt; 10 & gt;
F55
(IPU)
AY17
89 24
CPU_CFG & lt; 11 & gt;
K55
(IPU)
AY15
89 24
CPU_CFG & lt; 12 & gt;
F57
(IPU)
AY13
89 24
CPU_CFG & lt; 13 & gt;
E58
(IPU)
AW50
89 24
CPU_CFG & lt; 14 & gt;
H57
(IPU)
AW46
89 24
CPU_CFG & lt; 15 & gt;
H55
(IPU)
AW42
89 24 10
CPU_CFG & lt; 16 & gt;
D53
(IPU)
AW14
89 24
CPU_CFG & lt; 17 & gt;
K57
(IPU)
9
H23
=PEG_D2R_N & lt; 1 & gt;
IN
9
H21
=PEG_D2R_N & lt; 2 & gt;
IN
9
H19
=PEG_D2R_N & lt; 3 & gt;
IN
9
J20
=PEG_D2R_N & lt; 4 & gt;
IN
9
G18
=PEG_D2R_N & lt; 5 & gt;
IN
=PEG_D2R_N & lt; 6 & gt;
IN
=PEG_D2R_N & lt; 7 & gt;
IN
9
IN
SM BEAD-PROBE BP1004
9
F15
SIGNAL_MODEL=EMPTY
9
K17
1 TP
9
H15
=PEG_D2R_N & lt; 8 & gt;
H13
=PEG_D2R_N & lt; 9 & gt;
IN
9
H11
=PEG_D2R_N & lt; 10 & gt;
IN
9
J12
=PEG_D2R_N & lt; 11 & gt;
IN
9
IN
9
E8
=PEG_D2R_N & lt; 12 & gt;
G10
=PEG_D2R_N & lt; 13 & gt;
IN
9
J8
=PEG_D2R_N & lt; 14 & gt;
IN
9
=PEG_D2R_N & lt; 15 & gt;
IN
9
F7
(IPU)
(IPU)
(IPU)
BB15
CFG
G22
=PEG_D2R_P & lt; 0 & gt;
IN
9
AJ10
K23
=PEG_D2R_P & lt; 1 & gt;
IN
9
K21
=PEG_D2R_P & lt; 2 & gt;
IN
9
F19
=PEG_D2R_P & lt; 3 & gt;
IN
9
K19
=PEG_D2R_P & lt; 4 & gt;
IN
9
IN
1 TP
1 TP
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
SIGNAL_MODEL=EMPTY
SM BEAD-PROBE BP1011
SM BEAD-PROBE BP1012
9
H17
=PEG_D2R_P & lt; 5 & gt;
K15
=PEG_D2R_P & lt; 6 & gt;
IN
9
G14
=PEG_D2R_P & lt; 7 & gt;
IN
9
J16
=PEG_D2R_P & lt; 8 & gt;
IN
9
=PEG_D2R_P & lt; 9 & gt;
IN
SIGNAL_MODEL=EMPTY
9
K13
F11
=PEG_D2R_P & lt; 10 & gt;
IN
9
K11
=PEG_D2R_P & lt; 11 & gt;
IN
9
F9
=PEG_D2R_P & lt; 12 & gt;
IN
NOTE:
9
H9
=PEG_D2R_P & lt; 13 & gt;
IN
9
H7
=PEG_D2R_P & lt; 14 & gt;
IN
Intel is investigating processor driven VREF_DQ generation.
This connection is to support the same.
9
89 33
G6
=PEG_D2R_P & lt; 15 & gt;
IN
9
A22
=PEG_R2D_C_N & lt; 0 & gt;
OUT
9
B23
=PEG_R2D_C_N & lt; 1 & gt;
OUT
=PEG_R2D_C_N & lt; 2 & gt;
OUT
9
D21
=PEG_R2D_C_N & lt; 3 & gt;
OUT
9
B19
=PEG_R2D_C_N & lt; 4 & gt;
OUT
9
E20
=PEG_R2D_C_N & lt; 5 & gt;
OUT
9
A14
=PEG_R2D_C_N & lt; 6 & gt;
OUT
9
D17
=PEG_R2D_C_N & lt; 7 & gt;
OUT
9
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.75V
89 33
B15
=PEG_R2D_C_N & lt; 8 & gt;
OUT
E16
=PEG_R2D_C_N & lt; 9 & gt;
OUT
9
D13
=PEG_R2D_C_N & lt; 10 & gt;
OUT
=PEG_R2D_C_N & lt; 11 & gt;
OUT
9
B11
=PEG_R2D_C_N & lt; 12 & gt;
OUT
9
D9
=PEG_R2D_C_N & lt; 13 & gt;
OUT
9
B7
=PEG_R2D_C_N & lt; 14 & gt;
OUT
9
E12
=PEG_R2D_C_N & lt; 15 & gt;
OUT
9
C22
=PEG_R2D_C_P & lt; 0 & gt;
OUT
9
D23
=PEG_R2D_C_P & lt; 1 & gt;
OUT
9
A18
=PEG_R2D_C_P & lt; 2 & gt;
OUT
=PEG_R2D_C_P & lt; 3 & gt;
OUT
=PEG_R2D_C_P & lt; 4 & gt;
OUT
=PEG_R2D_C_P & lt; 5 & gt;
OUT
=PEG_R2D_C_P & lt; 6 & gt;
OUT
=PEG_R2D_C_P & lt; 7 & gt;
OUT
=PEG_R2D_C_P & lt; 8 & gt;
OUT
=PEG_R2D_C_P & lt; 9 & gt;
OUT
=PEG_R2D_C_P & lt; 10 & gt;
OUT
=PEG_R2D_C_P & lt; 11 & gt;
OUT
=PEG_R2D_C_P & lt; 12 & gt;
OUT
=PEG_R2D_C_P & lt; 13 & gt;
OUT
=PEG_R2D_C_P & lt; 14 & gt;
OUT
=PEG_R2D_C_P & lt; 15 & gt;
OUT
K49
(DDR_VREF1)
(THERMDA)
K47
BF63
K9
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
BE32
G52
BE16
G48
K7
BF43
BF41
K5
RSVD
BF35
J50
BF25
J4
BF23
J2
BF21
H49
BF19
H47
(THERMDC)
H5
(DDR_VREF0)
BE6
G4
BD33
F5
BD29
D49
BD19
D25
BD15
D3
BD13
C52
BC42
C24
BC30
C4
BC14
B53
C
9
F13
L2
BG22
9
D7
L4
BG26
9
B9
L6
BG34
9
D11
BG62
9
C10
M5
L10
9
B13
M9
BH19
9
F17
N6
BH21
9
D15
BH23
9
B17
BH25
9
C14
P7
RSVD
9
F21
AA4
BH35
D
9
D19
AC4
BH43
9
B21
AC6
BJ22
BF3
9
A10
AD5
NC
NC
NC
NC
NC
NC
NC
NC
PPCPU_MEM_VREFDQ_A
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.75V
9
AH5
BJ34
BG4
PPCPU_MEM_VREFDQ_B
9
C18
G64
BJ42
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
9
B25
B
CPU_CFG & lt; 7 & gt;
89 24 10
EDP:YES
2
R1010
AJ6
AC2
89 CPU_EDP_COMP
PEG_RX0*
PEG_RX1*
PEG_RX2*
PEG_RX3*
PEG_RX4*
PEG_RX5*
PEG_RX6*
PEG_RX7*
PEG_RX8*
PEG_RX9*
PEG_RX10*
PEG_RX11*
PEG_RX12*
PEG_RX13*
PEG_RX14*
PEG_RX15*
DMI_RX0
DMI_RX1
DMI_RX2
DMI_RX3
PLACE_NEAR=U1000.AB1:12.7mm
2
1
89 24 10
24.9
1
R1031
B
R1030
(1 OF 11) PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
DMI_RX0*
DMI_RX1*
DMI_RX2*
DMI_RX3*
DMI
R10
DMI_S2N_N & lt; 2 & gt;
INTEL FLEXIBLE DISPLAY INTERFACE SIGNALS
PCI EXPRESS BASED INTERFACE SIGNALS
N10
DMI_S2N_N & lt; 1 & gt;
IN
EMBEDDED DISPLAY PORT
DMI_S2N_N & lt; 0 & gt;
IN
89 18
89 18
2
24.9
IVY-BRIDGE
89 18
3
8 10 11 13 14 15
PART NUMBER
89 24 10 CPU_CFG & lt; 16 & gt;
89 24 10
CPU_CFG & lt; 5 & gt;
CPU_CFG & lt; 4 & gt;
89 24 10 CPU_CFG & lt; 1 & gt;
89 24 10
CPU_CFG & lt; 2 & gt;
89 24 10 CPU_CFG & lt; 0 & gt;
QTY
DESCRIPTION
REFERENCE DES
CRITICAL
BOM OPTION
89 24 10 CPU_CFG & lt; 3 & gt;
89 24 10
116S0066
1
RES,MTL FILM,1/16W,1K,0402,SMD,LF
R1031
EDP:YES
116S0090
1
RES,MTL FILM,1/16W,10K,0402,SMD,LF
R1031
EDP:NO
EDP:YES
NOSTUFF
1
1
R1042
R1044
1K
R1045
1K
1
1
R1046
1K
NOSTUFF
NOSTUFF
1
R1047
1K
1
R1040
1K
NOSTUFF
1
NOSTUFF
R1041
1K
NOSTUFF
1
R1043
1K
R1049
1K
1K
5%
5%
5%
5%
5%
5%
5%
5%
5%
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
MF-LF
A
1
MF-LF
MF-LF
MF-LF
MF-LF
MF-LF
MF-LF
MF-LF
MF-LF
402
2
402
2
402
2
402
2
402
402
2
2
402
402
2
402
2
A
2
PAGE TITLE
CPU DMI/PEG/FDI/RSVD
DRAWING NUMBER
These can be Placed close to J2500 and Only for debug access
CPU_CFG & lt; 4 & gt; should be pulled down to enable EDP
Apple Inc.
051-9589
R
CFG [7] :PEG DEFER TRAINING
1 = (DEFAULT) IMMEDIATELY AFTER xxRESETB
CFG [6:5] :PCIE BIFURCATION
11 = 1 X16 (DEFAULT)
CFG [4] :eDP ENABLE/DISABLE
1 = DISABLED
CFG [3] :PCIE x4 LANE REVERSAL
1 = NORMAL OPERATION
1 = NORMAL OPERATION
0 = WAIT FOR BIOS
0 = LANES REVERSED
7
01 = RSVD
NOTICE OF PROPRIETARY PROPERTY:
0 = LANES REVERSED
CFG [2] :PCIE x16 LANE REVERSAL
8
10 = 2 X8
00 = X8, X4, X4
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
0 = ENABLED
6
5
4
3
2
SIZE
D
REVISION
4.18.0
BRANCH
PAGE
10 OF 132
SHEET
10 OF 99
1
8
7
6
5
4
3
2
1
D
D
=PP1V05_S0_CPU_VCCIO
15 14 13 11 10 8
=PP1V05_S0_CPU_VCCIO
15 14 13 11 10 8
NOSTUFF
R1100
1
NOSTUFF
1
1
1K
R1101
5%
MF
201
1/16W
NOSTUFF
1
5%
1/16W
MF-LF
2
2
402
R1102
1K
51
5%
1/20W
68
R1104
2
OMIT_TABLE
5%
1/20W
MF
201
U1000
IVY-BRIDGE
BGA
402
NC
89 20
B59
PROC_DETECT*
(2 OF 11)
PROC_SELECT*
OUT
CPU_PROC_SEL_L
AH9
OUT
CPU_CATERR_L
H53
CLOCKS
2
R1103
89 41
1
5%
1/16W
MF-LF
402
89 42 20
CPU_PECI
BI
1
F53
PECI
CPU_PROCHOT_R_L
15 14 13 11 10 8 =PP1V05_S0_CPU_VCCIO
R1126
H51
PROCHOT*
75
1%
1/16W
MF-LF
402
25 24
89 42 20
F51
PM_THRMTRIP_L
OUT
AJ4
DPLL_REF_CLKP
IN
9 89
AJ2
DPLL_REF_CLKN
IN
9 89
BCLK_ITP
BCLK_ITP*
K63
ITPCPU_CLK100M_P
IN
17 89
K65
ITPCPU_CLK100M_N
IN
17 89
BCLK
BCLK*
D5
DMI_CLK100M_CPU_P
IN
17 89
C6
DMI_CLK100M_CPU_N
IN
17 89
PRDY*
PREQ*
J62
XDP_CPU_PRDY_L
OUT
24 89
H65
XDP_CPU_PREQ_L
IN
24 89
TCK
TMS
TRST*
J58
XDP_CPU_TCK
IN
24 89
H59
XDP_CPU_TMS
IN
24 89
H63
XDP_CPU_TRST_L
IN
24 89
TDI
TDO
K61
XDP_CPU_TDI
IN
24 89
K59
XDP_CPU_TDO
OUT
24 89
H61
XDP_DBRESET_L
OUT
24 25 89
BPM0*
BPM1*
BPM2*
BPM3*
BPM4*
BPM5*
BPM6*
BPM7*
C62
XDP_BPM_L & lt; 0 & gt;
BI
24 89
D61
XDP_BPM_L & lt; 1 & gt;
BI
24 89
E62
XDP_BPM_L & lt; 2 & gt;
BI
24 89
F63
XDP_BPM_L & lt; 3 & gt;
BI
24 89
D59
XDP_BPM_L & lt; 4 & gt;
BI
24 89
F61
XDP_BPM_L & lt; 5 & gt;
BI
24 89
F59
XDP_BPM_L & lt; 6 & gt;
BI
24 89
G60
XDP_BPM_L & lt; 7 & gt;
BI
24 89
(IPU)
(IPU)
(IPD)
2
43.2
(IPU)
1
K51
1%
1/16W
MF-LF
402
89 18
89 24 20
PM_SYNC
IN
PM_SYNC
C60
CPU_PWRGD
IN
RESET*
K53
PLT_RESET_LS1V1_L
AY25
PM_MEM_PWRGD_R
UNCOREPWRGOOD
(IPU)
(IPU)
SM_DRAMPWROK
27 16 14 11 8
BE24
=MEM_RESET_L
OUT
=PP1V5_S3_CPU_VCCDDR
BJ44
CPU_DDR_VREF
PLACE_NEAR=R1121.2:1mm
R1120 1
200
B
IN
89 CPU_SM_RCOMP & lt; 0 & gt;
BJ46
1%
1/16W
MF-LF
402
89 27 18
89 CPU_SM_RCOMP & lt; 1 & gt;
BG46
89 CPU_SM_RCOMP & lt; 2 & gt;
BF45
R1121
2
1
1%
1/16W
MF-LF
402
PLACE_NEAR=U1000.AY25:51.562mm
R1112
1
140
R1113
1
25.5
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
1
200
1%
1%
1/16W
2
1/16W
PLACE_NEAR=U1000.BF45:12.7mm
1/16W
MF-LF
MF-LF
402
2
402
2
B
R1114
1%
R1111
10K
5%
402
PLACE_NEAR=U1800.AY11:157mm
1/16W
MF-LF
=PP1V5_S3_CPU_VCCDDR
2
402
PLACE_NEAR=U1000.BG46:12.7mm
1
R1130
1K
PLACE_NEAR=U1000.BJ46:12.7mm
1%
1/16W
MF-LF
402 2
R11311
1
1K
PLACE_NEAR=U1000.BJ44:2.54mm
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
(IPU)
1
MF-LF
PLACE_NEAR=U1000.BJ44:2.54mm
SM_VREF
(IPU)
130
2
PM_MEM_PWRGD
R1120 and R1121 are Intel recommended values
27 16 14 11 8
SM_DRAMRST*
DDR3 MISC
(IPU)
27
C
THERMTRIP*
R1125
2
CPU_RESET_L
IN
CATERR*
THERMAL
2
CPU_PROCHOT_L
BI
PWR MGMT
89 65 42 41
JTAG & BPM
C
56
DPLL_REF_CLK
DPLL_REF_CLK*
DBR*
MF-LF
1%
1/16W
MF-LF
402 2
C1130
0.1UF
2
10%
16V
X7R-CERM
0402
PLACE_NEAR=U1000.BJ44:2.54mm
A
A
PAGE TITLE
CPU CLOCK/MISC/JTAG
DRAWING NUMBER
Apple Inc.
051-9589
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
4.18.0
BRANCH
PAGE
11 OF 132
SHEET
11 OF 99
1
6
90 29 28
BI
MEM_A_DQ & lt; 0 & gt;
AL6
90 29 28
BI
MEM_A_DQ & lt; 1 & gt;
AL8
BI
MEM_A_DQ & lt; 2 & gt;
AP7
90 29 28
BI
MEM_A_DQ & lt; 3 & gt;
AM5
90 29 28
BI
MEM_A_DQ & lt; 4 & gt;
AK7
90 29 28
BI
MEM_A_DQ & lt; 5 & gt;
AL10
90 29 28
BI
MEM_A_DQ & lt; 6 & gt;
AN10
90 29 28
BI
MEM_A_DQ & lt; 7 & gt;
AM9
90 29 28
BI
MEM_A_DQ & lt; 8 & gt;
AR10
90 29 28
D
BI
MEM_A_DQ & lt; 9 & gt;
AR8
90 29 28
BI
MEM_A_DQ & lt; 10 & gt;
AV7
90 29 28
BI
MEM_A_DQ & lt; 11 & gt;
AY5
90 29 28
BI
MEM_A_DQ & lt; 12 & gt;
AT5
90 29 28
BI
MEM_A_DQ & lt; 13 & gt;
AR6
90 29 28
BI
MEM_A_DQ & lt; 14 & gt;
AW6
90 29 28
BI
MEM_A_DQ & lt; 15 & gt;
AT9
90 29 28
MEM_A_DQ & lt; 16 & gt;
BA6
BI
MEM_A_DQ & lt; 17 & gt;
BA8
90 29 28
BI
MEM_A_DQ & lt; 18 & gt;
BG6
90 29 28
BI
MEM_A_DQ & lt; 19 & gt;
AY9
90 29 28
BI
90 29 28
BI
MEM_A_DQ & lt; 20 & gt;
AW8
90 29 28
BI
MEM_A_DQ & lt; 21 & gt;
BB7
90 29 28
BI
MEM_A_DQ & lt; 22 & gt;
BC8
BI
MEM_A_DQ & lt; 23 & gt;
BE4
AW12
90 29 28
90 29 28
BI
MEM_A_DQ & lt; 24 & gt;
90 29 28
BI
MEM_A_DQ & lt; 25 & gt;
AV11
90 29 28
BI
MEM_A_DQ & lt; 26 & gt;
BB11
90 29 28
BI
MEM_A_DQ & lt; 27 & gt;
BA12
90 29 28
BI
MEM_A_DQ & lt; 28 & gt;
BE8
90 29 28
BI
MEM_A_DQ & lt; 29 & gt;
BA10
BI
MEM_A_DQ & lt; 30 & gt;
BD11
BE12
90 29 28
90 29 28
C
BI
MEM_A_DQ & lt; 31 & gt;
90 29 28
BI
MEM_A_DQ & lt; 32 & gt;
BB49
90 29 28
BI
MEM_A_DQ & lt; 33 & gt;
AY49
90 29 28
BI
MEM_A_DQ & lt; 34 & gt;
BE52
90 29 28
BI
MEM_A_DQ & lt; 35 & gt;
BD51
90 29 28
BI
MEM_A_DQ & lt; 36 & gt;
BD49
90 29 28
BI
MEM_A_DQ & lt; 37 & gt;
BE48
BA52
90 29 28
BI
MEM_A_DQ & lt; 38 & gt;
90 29 28
BI
MEM_A_DQ & lt; 39 & gt;
AY51
90 29 28
BI
MEM_A_DQ & lt; 40 & gt;
BC54
90 29 28
BI
MEM_A_DQ & lt; 41 & gt;
AY53
90 29 28
BI
MEM_A_DQ & lt; 42 & gt;
AW54
90 29 28
BI
MEM_A_DQ & lt; 43 & gt;
AY55
90 29 28
BI
MEM_A_DQ & lt; 44 & gt;
BD53
BB53
90 29 28
BI
MEM_A_DQ & lt; 45 & gt;
90 29 28
BI
MEM_A_DQ & lt; 46 & gt;
BE56
90 29 28
BI
MEM_A_DQ & lt; 47 & gt;
BA56
90 29 28
BI
MEM_A_DQ & lt; 48 & gt;
BD57
90 29 28
BI
MEM_A_DQ & lt; 49 & gt;
BF61
90 29 28
BI
MEM_A_DQ & lt; 50 & gt;
BA60
90 29 28
BI
90 29 28
90 29 28
MEM_A_DQ & lt; 51 & gt;
BB61
BI
MEM_A_DQ & lt; 52 & gt;
BE60
90 29 28
BI
MEM_A_DQ & lt; 53 & gt;
BD63
90 29 28
BI
MEM_A_DQ & lt; 54 & gt;
BB59
BI
MEM_A_DQ & lt; 55 & gt;
BC58
90 29 28
BI
MEM_A_DQ & lt; 56 & gt;
AW58
90 29 28
BI
MEM_A_DQ & lt; 57 & gt;
AY59
90 29 28
BI
MEM_A_DQ & lt; 58 & gt;
AL60
90 29 28
BI
MEM_A_DQ & lt; 59 & gt;
AP61
90 29 28
BI
MEM_A_DQ & lt; 60 & gt;
AW60
90 29 28
BI
MEM_A_DQ & lt; 61 & gt;
AY57
90 29 28
BI
MEM_A_DQ & lt; 62 & gt;
AN60
BI
MEM_A_DQ & lt; 63 & gt;
AR60
90 32 29 28
OUT
90 32 29 28
90 29 28
B
90 29 28
MEM_A_BA & lt; 0 & gt;
BA36
OUT
MEM_A_BA & lt; 1 & gt;
BC38
90 32 29 28
OUT
MEM_A_BA & lt; 2 & gt;
BB19
90 32 29 28
OUT
MEM_A_CAS_L
BE44
90 32 29 28
OUT
MEM_A_RAS_L
BE36
OUT
MEM_A_WE_L
BA44
90 32 29 28
SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63
U1000
IVY-BRIDGE
SA_CLK0
SA_CLK0*
5
4
3
BB31
MEM_A_CLK_P & lt; 0 & gt;
OUT
28 32 90
90 31 30
BI
MEM_B_DQ & lt; 0 & gt;
AL4
BA32
MEM_A_CLK_N & lt; 0 & gt;
OUT
28 32 90
90 31 30
BI
MEM_B_DQ & lt; 1 & gt;
AK3
BGA
BI
MEM_B_DQ & lt; 2 & gt;
90 31 30
BI
MEM_B_DQ & lt; 3 & gt;
AR2
90 31 30
(3 OF 11)
AP3
BI
MEM_B_DQ & lt; 4 & gt;
AL2
90 31 30
SA_CKE0
BC18
MEM_A_CKE & lt; 0 & gt;
OMIT_TABLE
OUT
28 32 90
SA_CLK1
SA_CLK1*
AW34
MEM_A_CLK_P & lt; 1 & gt;
OUT
29 32 90
90 31 30
BI
MEM_B_DQ & lt; 5 & gt;
AK1
AY33
MEM_A_CLK_N & lt; 1 & gt;
OUT
29 32 90
90 31 30
BI
MEM_B_DQ & lt; 6 & gt;
AP1
90 31 30
BI
MEM_B_DQ & lt; 7 & gt;
AR4
SA_CKE1
BD17
MEM_A_CKE & lt; 1 & gt;
OUT
29 32 90
90 31 30
BI
MEM_B_DQ & lt; 8 & gt;
AV3
90 31 30
BI
MEM_B_DQ & lt; 9 & gt;
AU4
SA_CS0*
SA_CS1*
BD41
MEM_A_CS_L & lt; 0 & gt;
OUT
28 32 90
90 31 30
BI
MEM_B_DQ & lt; 10 & gt;
BA4
BD45
MEM_A_CS_L & lt; 1 & gt;
OUT
29 32 90
90 31 30
BI
MEM_B_DQ & lt; 11 & gt;
BB1
90 31 30
BI
MEM_B_DQ & lt; 12 & gt;
AV1
SA_ODT0
SA_ODT1
BB41
MEM_A_ODT & lt; 0 & gt;
OUT
28 32 90
90 31 30
BI
MEM_B_DQ & lt; 13 & gt;
AU2
BC46
MEM_A_ODT & lt; 1 & gt;
OUT
29 32 90
90 31 30
BI
MEM_B_DQ & lt; 14 & gt;
BA2
90 31 30
BI
MEM_B_DQ & lt; 15 & gt;
BB3
BC2
SA_DQS0*
SA_DQS1*
SA_DQS2*
SA_DQS3*
SA_DQS4*
SA_DQS5*
SA_DQS6*
SA_DQS7*
AN8
MEM_A_DQS_N & lt; 0 & gt;
BI
28 29 90
90 31 30
BI
MEM_B_DQ & lt; 16 & gt;
AU6
MEM_A_DQS_N & lt; 1 & gt;
BI
28 29 90
90 31 30
BI
MEM_B_DQ & lt; 17 & gt;
BF7
BC6
MEM_A_DQS_N & lt; 2 & gt;
BI
28 29 90
90 31 30
BI
MEM_B_DQ & lt; 18 & gt;
BF11
BD9
MEM_A_DQS_N & lt; 3 & gt;
BI
28 29 90
90 31 30
BI
MEM_B_DQ & lt; 19 & gt;
BJ10
BC50
MEM_A_DQS_N & lt; 4 & gt;
BI
28 29 90
90 31 30
BI
MEM_B_DQ & lt; 20 & gt;
BC4
BB55
MEM_A_DQS_N & lt; 5 & gt;
BI
28 29 90
90 31 30
BI
MEM_B_DQ & lt; 21 & gt;
BH7
BD59
MEM_A_DQS_N & lt; 6 & gt;
BI
28 29 90
90 31 30
BI
MEM_B_DQ & lt; 22 & gt;
BH11
BI
MEM_B_DQ & lt; 23 & gt;
BG10
BJ14
AU60
MEM_A_DQS_N & lt; 7 & gt;
BI
28 29 90
90 31 30
BI
MEM_B_DQ & lt; 24 & gt;
BI
28 29 90
90 31 30
BI
MEM_B_DQ & lt; 25 & gt;
BG14
BI
28 29 90
90 31 30
BI
MEM_B_DQ & lt; 26 & gt;
BF17
BI
MEM_B_DQ & lt; 27 & gt;
BJ18
BI
MEM_B_DQ & lt; 28 & gt;
BF13
BI
MEM_B_DQ & lt; 29 & gt;
BH13
BI
MEM_B_DQ & lt; 30 & gt;
BH17
BG18
90 31 30
SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7
AN6
MEM_A_DQS_P & lt; 0 & gt;
AU8
MEM_A_DQS_P & lt; 1 & gt;
BD5
MEM_A_DQS_P & lt; 2 & gt;
BI
28 29 90
90 31 30
BC10
MEM_A_DQS_P & lt; 3 & gt;
BI
28 29 90
90 31 30
BB51
MEM_A_DQS_P & lt; 4 & gt;
BI
28 29 90
90 31 30
BD55
MEM_A_DQS_P & lt; 5 & gt;
BD61
MEM_A_DQS_P & lt; 6 & gt;
AV61
MEM_A_DQS_P & lt; 7 & gt;
BI
28 29 90
90 31 30
28 29 90
90 31 30
BI
BI
28 29 90
90 31 30
BI
MEM_B_DQ & lt; 32 & gt;
BH49
90 31 30
SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_MA14
SA_MA15
BI
MEM_B_DQ & lt; 31 & gt;
BI
MEM_B_DQ & lt; 33 & gt;
BF47
BD27
MEM_A_A & lt; 0 & gt;
OUT
28 29 32 90
90 31 30
BI
MEM_B_DQ & lt; 34 & gt;
BH53
BA28
MEM_A_A & lt; 1 & gt;
OUT
28 29 32 90
90 31 30
BI
MEM_B_DQ & lt; 35 & gt;
BG50
BB27
MEM_A_A & lt; 2 & gt;
OUT
28 29 32 90
90 31 30
BI
MEM_B_DQ & lt; 36 & gt;
BF49
AW26
MEM_A_A & lt; 3 & gt;
OUT
28 29 32 90
90 31 30
BI
MEM_B_DQ & lt; 37 & gt;
BH47
BB23
MEM_A_A & lt; 4 & gt;
OUT
28 29 32 90
90 31 30
BI
MEM_B_DQ & lt; 38 & gt;
BF53
BA24
MEM_A_A & lt; 5 & gt;
OUT
28 29 32 90
90 31 30
BI
MEM_B_DQ & lt; 39 & gt;
BJ50
AY21
MEM_A_A & lt; 6 & gt;
OUT
28 29 32 90
90 31 30
BI
MEM_B_DQ & lt; 40 & gt;
BF55
BD21
MEM_A_A & lt; 7 & gt;
OUT
28 29 32 90
90 31 30
BI
MEM_B_DQ & lt; 41 & gt;
BH55
BC22
MEM_A_A & lt; 8 & gt;
OUT
28 29 32 90
90 31 30
BI
MEM_B_DQ & lt; 42 & gt;
BJ58
BB21
MEM_A_A & lt; 9 & gt;
OUT
28 29 32 90
90 31 30
BI
MEM_B_DQ & lt; 43 & gt;
BH59
AW38
MEM_A_A & lt; 10 & gt;
OUT
28 29 32 90
90 31 30
BI
MEM_B_DQ & lt; 44 & gt;
BJ54
AW22
MEM_A_A & lt; 11 & gt;
OUT
28 29 32 90
90 31 30
BI
MEM_B_DQ & lt; 45 & gt;
BG54
BA20
MEM_A_A & lt; 12 & gt;
OUT
28 29 32 90
90 31 30
BI
MEM_B_DQ & lt; 46 & gt;
BG58
BB45
MEM_A_A & lt; 13 & gt;
OUT
28 29 32 90
90 31 30
BI
MEM_B_DQ & lt; 47 & gt;
BF59
28 29 32 90
90 31 30
BI
MEM_B_DQ & lt; 48 & gt;
OUT
28 29 32 90
90 31 30
BI
MEM_B_DQ & lt; 49 & gt;
BC62
BI
MEM_B_DQ & lt; 50 & gt;
AU62
BI
90 31 30
MEM_A_A & lt; 15 & gt;
OUT
90 31 30
MEM_A_A & lt; 14 & gt;
AW18
BA64
90 31 30
BE20
MEM_B_DQ & lt; 51 & gt;
AW64
BI
MEM_B_DQ & lt; 52 & gt;
BA62
90 31 30
BI
MEM_B_DQ & lt; 53 & gt;
BC64
90 31 30
BI
MEM_B_DQ & lt; 54 & gt;
AU64
90 31 30
BI
MEM_B_DQ & lt; 55 & gt;
AW62
90 31 30
BI
MEM_B_DQ & lt; 56 & gt;
AR64
90 31 30
BI
MEM_B_DQ & lt; 57 & gt;
AT65
90 31 30
BI
MEM_B_DQ & lt; 58 & gt;
AL64
90 31 30
BI
MEM_B_DQ & lt; 59 & gt;
AM65
90 31 30
BI
MEM_B_DQ & lt; 60 & gt;
AR62
90 31 30
BI
MEM_B_DQ & lt; 61 & gt;
AT63
90 31 30
BI
MEM_B_DQ & lt; 62 & gt;
AL62
BI
MEM_B_DQ & lt; 63 & gt;
AM63
90 31 30
SA_BS0
SA_BS1
SA_BS2
90 32 31 30
OUT
MEM_B_BA & lt; 0 & gt;
BJ38
90 32 31 30
OUT
MEM_B_BA & lt; 1 & gt;
BD37
90 32 31 30
OUT
MEM_B_BA & lt; 2 & gt;
AY29
SA_CAS*
SA_RAS*
SA_WE*
90 32 31 30
OUT
MEM_B_CAS_L
BH39
90 32 31 30
OUT
MEM_B_RAS_L
BG38
OUT
MEM_B_WE_L
BF39
90 32 31 30
SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63
2
U1000
1
SB_CLK0
SB_CLK0*
BF33
MEM_B_CLK_P & lt; 0 & gt;
OUT
30 32 90
BH33
MEM_B_CLK_N & lt; 0 & gt;
OUT
30 32 90
SB_CKE0
BD25
MEM_B_CKE & lt; 0 & gt;
OUT
30 32 90
SB_CLK1
SB_CLK1*
BF37
MEM_B_CLK_P & lt; 1 & gt;
OUT
31 32 90
BH37
MEM_B_CLK_N & lt; 1 & gt;
OUT
31 32 90
SB_CKE1
BJ26
MEM_B_CKE & lt; 1 & gt;
OUT
31 32 90
SB_CS0*
SB_CS1*
BE40
MEM_B_CS_L & lt; 0 & gt;
OUT
30 32 90
BH41
MEM_B_CS_L & lt; 1 & gt;
OUT
31 32 90
SB_ODT0
SB_ODT1
BG42
MEM_B_ODT & lt; 0 & gt;
OUT
30 32 90
BH45
MEM_B_ODT & lt; 1 & gt;
OUT
31 32 90
SB_DQS0*
SB_DQS1*
SB_DQS2*
SB_DQS3*
SB_DQS4*
SB_DQS5*
SB_DQS6*
SB_DQS7*
AN4
MEM_B_DQS_N & lt; 0 & gt;
BI
30 31 90
AW2
MEM_B_DQS_N & lt; 1 & gt;
BI
30 31 90
BH9
MEM_B_DQS_N & lt; 2 & gt;
BI
30 31 90
BF15
MEM_B_DQS_N & lt; 3 & gt;
BI
30 31 90
BF51
MEM_B_DQS_N & lt; 4 & gt;
BI
30 31 90
BH57
MEM_B_DQS_N & lt; 5 & gt;
BI
30 31 90
AY63
MEM_B_DQS_N & lt; 6 & gt;
BI
30 31 90
AN62
MEM_B_DQS_N & lt; 7 & gt;
BI
30 31 90
SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7
AN2
MEM_B_DQS_P & lt; 0 & gt;
BI
30 31 90
AW4
MEM_B_DQS_P & lt; 1 & gt;
BI
30 31 90
BF9
MEM_B_DQS_P & lt; 2 & gt;
BI
30 31 90
BH15
MEM_B_DQS_P & lt; 3 & gt;
BI
30 31 90
BH51
MEM_B_DQS_P & lt; 4 & gt;
BI
30 31 90
BF57
MEM_B_DQS_P & lt; 5 & gt;
BI
30 31 90
AY65
MEM_B_DQS_P & lt; 6 & gt;
BI
30 31 90
AN64
MEM_B_DQS_P & lt; 7 & gt;
BI
30 31 90
SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_MA14
SB_MA15
IVY-BRIDGE
BF31
MEM_B_A & lt; 0 & gt;
OUT
30 31 32 90
BH31
MEM_B_A & lt; 1 & gt;
OUT
30 31 32 90
BB37
MEM_B_A & lt; 2 & gt;
OUT
30 31 32 90
BC34
MEM_B_A & lt; 3 & gt;
OUT
30 31 32 90
BF27
MEM_B_A & lt; 4 & gt;
OUT
30 31 32 90
BB33
MEM_B_A & lt; 5 & gt;
OUT
30 31 32 90
BH27
MEM_B_A & lt; 6 & gt;
OUT
30 31 32 90
BG30
MEM_B_A & lt; 7 & gt;
OUT
30 31 32 90
BH29
MEM_B_A & lt; 8 & gt;
OUT
30 31 32 90
BF29
MEM_B_A & lt; 9 & gt;
OUT
30 31 32 90
AY37
MEM_B_A & lt; 10 & gt;
OUT
30 31 32 90
BJ30
MEM_B_A & lt; 11 & gt;
OUT
30 31 32 90
AW30
MEM_B_A & lt; 12 & gt;
OUT
30 31 32 90
BA40
MEM_B_A & lt; 13 & gt;
OUT
30 31 32 90
BB29
MEM_B_A & lt; 14 & gt;
OUT
30 31 32 90
BE28
MEM_B_A & lt; 15 & gt;
OUT
30 31 32 90
BGA
(4 OF 11)
OMIT_TABLE
MEMORY CHANNEL B
7
MEMORY CHANNEL A
8
D
C
B
SB_BS0
SB_BS1
SB_BS2
SB_CAS*
SB_RAS*
SB_WE*
A
SYNC_DATE=01/13/2012
PAGE TITLE
CPU DDR3 INTERFACES
DRAWING NUMBER
Apple Inc.
051-9589
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
4.18.0
BRANCH
PAGE
12 OF 132
SHEET
12 OF 99
1
A
8
7
6
5
4
3
2
1
D
D
=PP3V3_S0_CPU_VCCIO_SEL
8
98 45 15 13 8 =PPVCORE_S0_CPU
=PPVCORE_S0_CPU
8 13 15 45 98
For Future Compatibility
R1320
1
R46
16 13 8
=PP1V05_S0_CPU_VCCIO
=PPVCCSA_S0_CPU
402
8 10 11 13 14 15
H31
BGA
H29
R36
2
H35
IVY-BRIDGE
R40
5%
MF-LF
U1000
R42
10K
1/16W
(6 OF 11)
CORE POWER
H25
R34
=PP1V05_S0_CPU_VCCIO
PLACE_NEAR=R1310.1:2.54mm
1
R1300
1
75
MF-LF
89 65
CPU_VIDSOUT
BI
MF-LF
R1312
402
0
1/16W
2
1
2
5%
89 65
OUT
402
0
1/16W
IN
CPU_VIDALERT_L
402
1
2
5%
2
5%
43
PLACE_NEAR=U1000.B51:38mm
F45
F43
AK63
N33
F41
N30
F37
N26
F35
N24
F31
AT21
N20
F29
AP21
M46
F25
AL21
M42
E44
M40
E40
BJ60
VCCPQE
M12
8 10 11 13 14 15
=PPVCORE_S0_CPU
=PPVCORE_S0_CPU_VCCAXG
G26
N37
=PPVCORE_S0_CPU_VCCAXG
8 13 14
16
8 13 15 45 98
M36
E38
=PP1V8_S0_CPU_VCCPLL_R
AV21
M15
8 13 15 45 98
=PP1V05_S0_CPU_VCCIO
G28
N43
=PP1V5_S3_CPU_VCCDQ
8 16
8 15
VCCSA
N16
M17
C
N45
AK61
N18
CPU_VIDALERT_L_R
MF-LF
VCCPLL
N14
=PPVCORE_S0_CPU
G32
AP23
CPU_VCCIO_SEL
AK65
T14
CPU_VIDSCLK_R
MF-LF
T11
1
1/16W
G34
R21
N39
VCCDQ
G38
R23
AL23
OMIT_TABLE
G40
AJ8
T16
R1310
89 65
AT23
=PP1V05_S0_CPU_VCCPQE
8 15
M11
8 13 14 16
G44
OMIT_TABLE
R29
R27
VCCIO_SEL
U12
CPU_VIDSOUT_R
R1311
CPU_VIDSCLK
AV23
(9 OF 11)
U15
402
MF-LF
BGA
U17
1/16W
402
IVY-BRIDGE
W12
PLACE_NEAR=U1000.A50:2.54mm
U1000
W15
1%
1/16W
2
W17
R1302
130
1%
8 10 11 13 14 15
L18
BJ6
NOSTUFF
R1360
1
1
100
PLACE_NEAR=U1000.B47:50.8mm
5%
1/16W
MF-LF
402
PLACE_SIDE=BOTTOM
R1362
100
R1366
R1364
100
NOSTUFF
NOSTUFF
1%
1/16W
1/16W
1
MF-LF
MF
402
2
201
PLACE_SIDE=BOTTOM
1/16W
MF
2
1%
MF-LF
201
2
402
89 62
89 62
OUT
OUT
CPU_VCCSA_VID & lt; 0 & gt;
AE10
CPU_VCCSA_VID & lt; 1 & gt;
AG10
89 65
OUT
CPU_VCCSENSE_P
B47
89 65
OUT
CPU_VCCSENSE_N
A46
89 65
89 65
89 67
89 67
OUT
CPU_AXG_SENSE_P
F49
OUT
CPU_AXG_SENSE_N
E50
OUT
CPU_VCCIOSENSE_P
AW10
OUT
CPU_VCCIOSENSE_N
AU10
TP_CPU_VDDQSENSEP
AY19
TP_CPU_VDDQSENSEN
AW20
VCCIO_SENSE
VSS_SENSE_VCCIO
PLACE_NEAR=U1000.E50:50.8mm
1
PLACE_SIDE=BOTTOM
R1367
VDDQ_SENSE
VSS_SENSE_VDDQ
100
1%
1/16W
89 62
MF-LF
2
K3
CPU_VCCSASENSE
OUT
NOSTUFF
B
VCCSA_SENSE
402
TP_CPU_DIE_SENSE
F47
CPU_VCC_VALSENSE_P
D47
CPU_VCC_VALSENSE_N
C48
CPU_AXG_VALSENSE_P
B49
CPU_AXG_VALSENSE_N
A48
VCC_DIE_SENSE
VCC_VAL_SENSE
VSS_VAL_SENSE
VAXG_VAL_SENSE
VSSAXG_VAL_SENSE
PLACE_SIDE=BOTTOM
PLACE_NEAR=U1000.A46:50.8mm
PLACE_NEAR=U1000.AU10:50.8mm
PLACE_SIDE=BOTTOM
R1361
1
1
100
5%
1/16W
MF-LF
402
R1363
100
1%
PLACE_SIDE=BOTTOM
NOSTUFF
R1314
1
1
R1313
1/16W
MF-LF
2
2
R1365
402
10K
1
1
49.9
NOSTUFF
1%
1%
MF
201
5%
1/16W
1/16W
MF-LF
49.9
1/20W
10K
5%
R1371
PLACE_SIDE=BOTTOM
MF-LF
402
402
2
NOSTUFF
2
1/20W
D41
L38
D37
F1
L34
D35
L32
D31
E2
L28
D29
L26
C44
B5
L22
C40
A60
K45
C38
K43
C34
K41
DC_TEST_A4
DC_TEST_A62
DC_TEST_A64
DC_TEST_B3
DC_TEST_B63
DC_TEST_B65
DC_TEST_BF1
DC_TEST_BF65
DC_TEST_BG2
DC_TEST_BG64
DC_TEST_BH1
DC_TEST_BH3
DC_TEST_BH63
DC_TEST_BH65
DC_TEST_BJ2
DC_TEST_BJ4
DC_TEST_BJ62
DC_TEST_BJ64
DC_TEST_C2
DC_TEST_C64
DC_TEST_D1
DC_TEST_D65
L40
E64
VAXG_SENSE
VSSAXG_SENSE
L44
F65
VCC_SENSE
VSS_SENSE
M21
BD1
VSS_NCTF
PLACE_NEAR=U1000.F49:50.8mm
E28
M23
BE2
VCCSA_VID0
VCCSA_VID1
M27
BE64
100
1/20W
2
B51
R1368
1%
1%
402
R1370
1
49.9
1/20W
MF-LF
2
1
49.9
1%
2
D51
NOSTUFF
1
VIDSOUT
VIDSCLK
VIDALERT*
E32
BH5
BD65
A50
PLACE_NEAR=U1000.AW10:50.8mm
E34
A6
PLACE_SIDE=BOTTOM
8 13
16
M29
B61
=PPVCCSA_S0_CPU
M34
BH61
L14
PLACE_SIDE=BOTTOM
PLACE_SIDE=BOTTOM
C32
TP_DC_TEST_A4
K37
C28
A62
TP_DC_TEST_A62
K35
C26
A64
DC_TEST_B63_A64
K31
B45
B3
DC_TEST_B3_C2
K29
B43
B63
K25
B41
B65
DC_TEST_B65_C64
J44
B37
BF1
TP_DC_TEST_BF1
J40
B35
BF65
TP_DC_TEST_BF65
J38
B31
BG2
DC_TEST_BH1_BG2
J34
B29
BG64
DC_TEST_BG64_BH65
J32
C
A44
A4
E26
D45
VCC
VCC
D43
J28
A40
DC_TEST_BH3_BJ2
J26
A38
DC_TEST_BJ64_BH63
H45
A34
BH65
H43
A32
BJ2
H41
A28
H37
B
A26
BH1
BH3
BH63
BJ4
TP_DC_TEST_BJ4
BJ62
TP_DC_TEST_BJ62
BJ64
C2
C64
D1
TP_DC_TEST_D1
D65
TP_DC_TEST_D65
MF
2
2
201
NOTE: Intel validation sense lines per doc 439028 rev1.0
HR_PPDG sections 6.2.1 and 6.3.1.
A
SYNC_MASTER=D2_KEPLER
SYNC_DATE=01/13/2012
PAGE TITLE
CPU POWER
DRAWING NUMBER
Apple Inc.
051-9589
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
4.18.0
BRANCH
PAGE
13 OF 132
SHEET
13 OF 99
1
A
8
7
6
5
BJ56
U1000
AW16
AG12
U1000
IVY-BRIDGE
AV65
AF65
IVY-BRIDGE
AV63
AF63
BGA
AV59
AF61
(11 OF 11)
BJ40
OMIT_TABLE
L8
AV57
AF11
BJ24
AV50
AF9
BJ20
AV44
AF5
BJ16
AV38
AE57
K1
BJ12
AV31
AD16
J64
BJ8
AV25
AD14
J60
BG60
BJ32
D
1
L12
(10 OF 11)
2
L16
BGA
3
L20
BJ52
BJ48
4
K39
OMIT_TABLE
K33
K27
D
=PPVCORE_S0_CPU_VCCAXG
=PP1V5_S3_CPU_VCCDDR
16 13 8
8 11 16 27
AV19
AD7
J56
BG56
AV9
AD3
J52
AH65
U1000
BJ36
BG52
AV5
AD1
J48
AH63
IVY-BRIDGE
BJ28
BG48
AU54
AC64
J46
AH61
BGA
BG40
BG44
AU47
AC62
J42
AH58
(8 OF 11)
BG32
BG36
AU41
AC60
J36
AH56
BG28
AU35
AC57
J30
OMIT_TABLE
AG64
BD47
=PP1V05_S0_CPU_VCCIO
=PP1V05_S0_CPU_VCCIO
15 14 13 11 10 8
8 10 11 13 14 15
BD43
AV55
AU28
AB11
J24
AG62
BD39
BG20
AU22
AB9
J22
AG60
BD31
BG16
AU16
AB5
J18
AF58
AN20
AV53
BG24
U1000
BD23
J14
AA57
AU14
AN18
BGA
AN16
AV17
BG12
IVY-BRIDGE
AV48
(7 OF11)
IO POWER
AN14
BB35
AF56
AV15
BG8
AT61
AA17
J10
AE64
AY47
BF5
AT57
AA15
J6
AE62
AM11
AY43
OMIT_TABLE
AV12
AL55
AU58
AL48
AU52
AL17
AU49
AL15
AU20
AL12
AU18
AK58
AT55
AK56
AT53
AJ17
AT48
H39
AA12
AT50
AL53
AU56
BE62
AJ15
AY39
AE60
BE58
AT44
Y65
H33
AD65
AY35
BE54
AT38
Y63
H27
AD63
AY31
BE50
AT31
Y61
H3
AD61
AY27
BE46
Y7
AT25
AY23
AD58
G62
BE42
AT19
Y3
G58
AD56
AV46
BE38
AT11
Y1
G54
AB65
AV42
AT7
BE34
W57
AV40
AB63
G50
BE30
AT3
V16
G46
AB61
AV36
BE26
AT1
V14
G42
AB58
AV34
BE22
AR54
V11
G36
AB56
AV29
AT17
AT15
AJ12
VCCIO
VCCIO
AH16
G30
V9
AR47
BE18
AH11
AF16
AR52
AF14
AR49
AE17
AR20
AE15
AR18
AE12
AR16
AD11
AR14
AC17
AP55
AC15
AP53
AC12
AP48
AB16
AV27
AA64
AR41
V5
G24
AA62
AU45
AR35
U64
G20
AA60
AU43
AR28
U62
G16
Y58
BD7
AR22
U60
G12
Y56
BD3
AP65
U57
G8
W64
BC60
AP63
T7
F39
W62
AP57
BC56
VSS
VSS
T3
F33
W60
BC52
AP50
T1
F27
V65
BC48
AP44
R57
E60
V63
AP38
R50
E56
V61
BC44
VSS
VSS
AP31
BC40
R44
E52
VAXG
AU39
IO POWER DDR3
BD35
GRAPHIC CORE POWER
BE14
BE10
AU37
AU33
AU30
AU26
AU24
AT46
AT42
AT40
V58
AN58
R38
E48
V56
BC32
AP19
R31
E46
T65
VDDQ
AB14
Y16
Y14
AN49
AP25
AN56
AN52
BC36
Y11
AT36
AT34
BC28
AP17
R25
E42
T63
AT29
BC26
AP15
R19
E36
T61
AT27
BC24
AP12
R17
E30
T58
AR45
BC20
AP11
R15
E24
T56
AR43
BC16
AP9
R12
E22
R64
AR39
BC12
AP5
P65
E18
R62
AR37
BB65
AN54
P63
E14
R60
AR33
BB63
AN47
P61
E10
R55
AR30
BB47
AN41
P11
E6
R53
AR26
BB39
AN35
P9
E4
R48
AR24
BB9
AN28
P5
D63
N64
AP46
BB5
AN22
N54
D39
N62
AP42
BA58
AM61
N47
D33
N60
AP40
BA54
AM7
N41
D27
N58
AP36
BA50
AM3
N35
C58
N56
AP34
BA46
AM1
N28
C54
N52
AP29
BA42
AL57
N22
C50
N49
AP27
BA38
AL50
M57
C46
M65
AN45
BA34
AL44
M50
C42
M63
AN43
BA30
AL38
M44
C36
M61
AN39
BA26
AL31
M38
C30
M59
AN37
BA22
AL25
M31
C20
M55
AN33
BA18
AL19
M25
C16
M53
AN30
BA14
AK16
M19
C12
M48
AN26
AY61
AK14
M7
C8
L56
AN24
AY11
AK11
M3
B39
L52
AL46
AK9
M1
B33
L48
AL42
AY3
AK5
L64
B27
AL40
AY1
AJ64
L62
A56
AL36
AW56
AJ62
L60
A52
AL34
AW52
AJ60
L58
A42
AL29
AW48
AJ57
L54
A36
AL27
AW44
B
C
AH14
AR58
AR56
C
AT12
AH7
L50
A30
AY7
AW40
AH3
L46
A24
AW36
AH1
L42
A20
AW32
AG57
L36
A16
AW28
AG17
L30
A12
AW24
AG15
L24
B
A8
A
A
PAGE TITLE
CPU POWER AND GND
DRAWING NUMBER
Apple Inc.
051-9589
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
4.18.0
BRANCH
PAGE
14 OF 132
SHEET
14 OF 99
1
8
7
6
5
4
3
2
1
CPU VCORE DECOUPLING
Intel recommendation: 4x 470uF 4mOhm, 2x 470uF 4mOhm (NOSTUFF), 16x 22uF 0805, 4x 10uF 0603, 20x 1uF 0402, 28x 1uF 0402 (NOSTUFF)
Apple Implementation: 8x 270uF 6mOhm, 0x 470uF 4mOhm
, 16x 22uF 0402, 4x 10uF 0402, 20x 1uF 0402, 28x 1uF 0201 (NOSTUFF), 4x 22uF 0402 (NOSTUFF)
PLACEMENT_NOTE (C1600-C16C7):
98 45 13 8
=PPVCORE_S0_CPU
Place on bottom side of U1000
U100.
C1600
1
1
C1601
C1602
1
1
C1603
1
C1604
1
C1605
1
C1606
1
C1607
1
C1608
1
C1609
1
C1610
C1611
1
1
C1612
1
C1613
1
C1614
1
C1615
1
C1616
C1617
1
1
C1618
1UF
D
1UF
1UF
1UF
1UF
1UF
1UF
1UF
1UF
1UF
1UF
1UF
1UF
1UF
1UF
1UF
1UF
1UF
10%
10V
X6S-CERM
0402
10%
10V
X6S-CERM
0402
10%
10V
X6S-CERM
0402
10%
10V
X6S-CERM
0402
10%
10V
X6S-CERM
0402
10%
10V
X6S-CERM
0402
10%
10V
X6S-CERM
0402
10%
10V
X6S-CERM
0402
10%
10V
X6S-CERM
0402
10%
10V
X6S-CERM
0402
2
10%
10V
X6S-CERM
0402
2
10%
10V
X6S-CERM
0402
2
10%
10V
X6S-CERM
0402
2
10%
10V
X6S-CERM
0402
2
10%
10V
X6S-CERM
0402
2
10%
10V
X6S-CERM
0402
10%
10V
X6S-CERM
0402
10%
10V
X6S-CERM
0402
1
C16B1
1
C16B2
1
C16B3
1
C16B4
1
C16B5
1
C16B6
2
2
NOSTUFF
1
NOSTUFF
1
1UF
20%
4V
CERM-X6S
0201
2
20%
4V
CERM-X6S
0201
2
2
1
20%
4V
CERM-X6S
0201
2
1UF
20%
4V
CERM-X6S
0201
2
1
20%
4V
CERM-X6S
0201
2
NOSTUFF
C16A8
1
NOSTUFF
C16A9
1UF
2
2
1
20%
4V
CERM-X6S
0201
1UF
20%
4V
CERM-X6S
0201
2
NOSTUFF
C16B0
1UF
20%
4V
CERM-X6S
0201
2
NOSTUFF
1UF
20%
4V
CERM-X6S
0201
2
NOSTUFF
1UF
20%
4V
CERM-X6S
0201
2
NOSTUFF
1UF
2
NOSTUFF
1UF
20%
4V
CERM-X6S
0201
2
2
1
C1621
1
1
C1623
1
1
1UF
20%
4V
CERM-X6S
0201
2
NOSTUFF
C16B8
1
1UF
20%
4V
CERM-X6S
0201
2
C16B9
1UF
20%
4V
CERM-X6S
0201
2
20%
4V
CERM-X6S
0201
NOSTUFF
NOSTUFF
CRITICAL
CRITICAL
C1690
1
C1691
1
C1698
NOSTUFF
CRITICAL
1
CRITICAL
1
C1693
C1694
CRITICAL
1
CRITICAL
1
C1695
C
10UF
10UF
10UF
20UF
20UF
20UF
20UF
20UF
20UF
20UF
20%
4V
X6S
0402
20%
4V
X6S
0402
20%
4V
X6S
0402
20%
4V
X6S
0402
20%
2V
X6T-CERM
0402
20%
2V
X6T-CERM
0402
20%
2V
X6T-CERM
0402
20%
2V
X6T-CERM
0402
20%
2V
X6T-CERM
0402
20%
2V
X6T-CERM
0402
CRITICAL
1
C1696
10UF
2
D
10%
10V
X6S-CERM
0402
20%
4V
CERM-X6S
0201
NOSTUFF
C1622
2
NOSTUFF
C16B7
C1619
1UF
2
C16C7
2
CRITICAL
C1620
NOSTUFF
1
1UF
20%
4V
CERM-X6S
0201
2
1UF
20%
4V
CERM-X6S
0201
PLACEMENT_NOTE (C1620-C1623):
Place near inductors on bottom side.
Place near U1000 on bottom side
1
NOSTUFF
1UF
20%
4V
CERM-X6S
0201
2
NOSTUFF
1
C16C6
1UF
20%
4V
CERM-X6S
0201
1
20%
4V
CERM-X6S
0201
2
2
NOSTUFF
C16A7
1UF
NOSTUFF
1
C16C5
2
NOSTUFF
C16A6
1UF
NOSTUFF
1
C16C4
2
NOSTUFF
C16A5
1UF
1UF
20%
4V
CERM-X6S
0201
2
1
NOSTUFF
1
C16C3
1UF
20%
4V
CERM-X6S
0201
2
2
2
NOSTUFF
C16A4
1UF
NOSTUFF
1
C16C2
1UF
20%
4V
CERM-X6S
0201
2
NOSTUFF
1
C16C1
1UF
1
20%
4V
CERM-X6S
0201
2
2
NOSTUFF
C16A3
1UF
20%
4V
CERM-X6S
0201
2
NOSTUFF
1
C16C0
1
1UF
20%
4V
CERM-X6S
0201
2
2
NOSTUFF
C16A2
1
1UF
20%
4V
CERM-X6S
0201
2
NOSTUFF
C16A1
1UF
2
2
NOSTUFF
C16A0
1
1
1UF
10%
10V
X6S-CERM
0402
20%
2V
X6T-CERM
0402
2
2
2
2
2
2
2
2
2
2
C1699
20UF
20%
2 2V
X6T-CERM
0402
C
PLACEMENT_NOTE (C1624-C16D5):
Place near inductors on bottom side.
CRITICAL
CRITICAL
C1624
1
1
1
1
2
CRITICAL
C1633
20UF
20%
2V
X6T-CERM
0402
2
NOSTUFF
CRITICAL
C1632
1
20UF
20%
2V
X6T-CERM
0402
2
NOSTUFF
CRITICAL
C1631
1
20UF
20%
2V
X6T-CERM
0402
2
CRITICAL
C1630
1
20UF
20%
2V
X6T-CERM
0402
2
CRITICAL
C1629
1
20UF
20%
2V
X6T-CERM
0402
2
CRITICAL
C1628
1
20UF
20%
2V
X6T-CERM
0402
2
NOSTUFF
CRITICAL
C1627
1
20UF
20%
2V
X6T-CERM
0402
2
CRITICAL
C1626
20UF
20%
2V
X6T-CERM
0402
2
CRITICAL
C1625
20UF
NOSTUFF
1
20UF
20%
2V
X6T-CERM
0402
2
CRITICAL
C1634
1
20UF
20%
2V
X6T-CERM
0402
2
CRITICAL
C1635
1
20UF
20%
2V
X6T-CERM
0402
2
C1636
CRITICAL
1
20UF
20%
2V
X6T-CERM
0402
2
20%
2V
X6T-CERM
0402
C1637
CRITICAL
1
20UF
2
C1638
CRITICAL
1
20UF
20%
2V
X6T-CERM
0402
2
20%
2V
X6T-CERM
0402
C1639
NOSTUFF
1
20UF
2
C16D0
NOSTUFF
1
20UF
20%
2V
X6T-CERM
0402
2
20%
2V
X6T-CERM
0402
NOSTUFF
C16D1
1
20UF
2
NOSTUFF
C16D2
1
20UF
20%
2V
X6T-CERM
0402
2
C16D3
NOSTUFF
1
20UF
20%
2V
X6T-CERM
0402
2
20%
2V
X6T-CERM
0402
NOSTUFF
C16D4
1
20UF
2
C16D5
20UF
20%
2V
X6T-CERM
0402
2
20%
2V
X6T-CERM
0402
PLACEMENT_NOTE (C1640-C1645):
CRITICAL
1
CRITICAL
1
C1640
CRITICAL
1
C1641
270UF
270UF
20%
2 2V
TANT
CASE-B2-SM
CRITICAL
1
C1642
270UF
20%
2 2V
TANT
CASE-B2-SM
CRITICAL
1
C1643
20%
2 2V
TANT
CASE-B2-SM
CRITICAL
1
C1644
270UF
20%
2 2V
TANT
CASE-B2-SM
CRITICAL
1
C1645
270UF
270UF
20%
2 2V
TANT
CASE-B2-SM
CRITICAL
1
C1688
270UF
20%
2 2V
TANT
CASE-B2-SM
C1689
270UF
20%
2 2V
TANT
CASE-B2-SM
20%
2 2V
TANT
CASE-B2-SM
CPU VCCIO/VCCPQ DECOUPLING
Intel recommendation: 2x 330uF, 10x 10uF 0603, 26x 1uF 0402
Apple Implementation: 2x 330uF, 10x 10uF 0603, 26x 1uF 0402
PLACEMENT_NOTE (C1646-C1671):
B
13 11 10 8 =PP1V05_S0_CPU_VCCIO
14
CPU VCCPLL DECOUPLING
Place on bottom side of U1000
U100.
R1600
1
C1646
1
C1647
C1648
1
1
C1649
1
C1650
1
C1651
1
C1652
1
C1653
1
C1654
1
C1655
1
C1656
1
C1657
1
C1658
1UF
2
1UF
1UF
1UF
1UF
1UF
1UF
1UF
1UF
1UF
1UF
1UF
1UF
10%
10V
X6S-CERM
0402
10%
10V
X6S-CERM
0402
10%
10V
X6S-CERM
0402
10%
10V
X6S-CERM
0402
10%
10V
X6S-CERM
0402
10%
10V
X6S-CERM
0402
10%
10V
X6S-CERM
0402
10%
10V
X6S-CERM
0402
10%
10V
X6S-CERM
0402
10%
10V
X6S-CERM
0402
10%
10V
X6S-CERM
0402
10%
10V
X6S-CERM
0402
2
2
2
2
2
2
2
2
2
2
2
2
=PP1V8_S0_CPU_VCCPLL_R
B
8 13
0
8 =PP1V8_S0_CPU_VCCPLL
10%
10V
X6S-CERM
0402
1
2
5%
1/16W
MF-LF
402
PLACE_NEAR=U1000.AK61:5MM
CRITICAL
1
1
C1686
1UF
2
PLACE_NEAR=U1000.AK63:2.54 mm:NO_VIA
C1685
1UF
10%
10V
X6S-CERM
0402
10%
10V
X6S-CERM
0402
2
1
C1687
220UF
20%
2 2.5V
TANT
B16
(Z = 1.2mm, place on short side behind CPU)
PLACE_NEAR=U1000.AK65:2.54 mm:NO_VIA
1
C1659
1
1UF
2
C1660
C1661
1
1UF
10%
10V
X6S-CERM
0402
2
1
1UF
10%
10V
X6S-CERM
0402
1
1UF
10%
10V
X6S-CERM
0402
2
C1662
2
C1675
1
1UF
10%
10V
X6S-CERM
0402
1
C1663
2
C1664
1
1UF
10%
10V
X6S-CERM
0402
2
C1665
1
1UF
10%
10V
X6S-CERM
0402
2
C1666
1
1UF
10%
10V
X6S-CERM
0402
2
C1667
1
1UF
10%
10V
X6S-CERM
0402
2
C1668
1
1UF
10%
10V
X6S-CERM
0402
2
10%
10V
X6S-CERM
0402
C1669
1
1UF
2
10%
10V
X6S-CERM
0402
C1670
1
1UF
2
10%
10V
X6S-CERM
0402
C1671
CPU VCCPLL Low pass filter
1UF
2
10%
10V
X6S-CERM
0402
PLACEMENT_NOTE (C1672-C1681):
Place near U1000 on bottom side
1
C1672
1
C1673
1
C1674
1
C1676
1
C1677
1
C1678
1
C1679
1
C1680
10UF
2
10UF
10UF
10UF
10UF
10UF
10UF
10UF
20%
4V
X6S-CERM
0603
20%
4V
X6S-CERM
0603
20%
4V
X6S-CERM
0603
20%
4V
X6S-CERM
0603
20%
4V
X6S-CERM
0603
20%
4V
X6S-CERM
0603
20%
4V
X6S-CERM
0603
20%
4V
X6S-CERM
0603
2
2
CRITICAL
1
2
2
2
2
2
2
C1681
10UF
2
20%
4V
X6S-CERM
0603
CRITICAL
C1682
1
330UF-6MOHM
20%
3 2 2.0V
POLY-TANT
D15T-ECGLT-COMBO
A
1
10UF
20%
4V
X6S-CERM
0603
C1683
330UF-6MOHM
20%
3 2 2.0V
POLY-TANT
D15T-ECGLT-COMBO
(Z = 1.5mm, place on tall side next to CPU & under heat pipe)
SYNC_MASTER=D2_SEAN
SYNC_DATE=03/05/2012
PAGE TITLE
CPU DECOUPLING-I
Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402
DRAWING NUMBER
R1601
1
0.010
2
Apple Inc.
=PP1V05_S0_CPU_VCCPQE
1%
1/4W
MF
0603
1
R
NOTICE OF PROPRIETARY PROPERTY:
C1684
1UF
2
8
8 13
7
051-9589
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
10%
10V
X6S-CERM
0402
6
5
4
3
2
SIZE
D
REVISION
4.18.0
BRANCH
PAGE
16 OF 132
SHEET
15 OF 99
1
A
8
7
6
5
4
2
3
1
VAXG DECOUPLING
INTEL RECOMMENDATION: 2X 470UF 4MOHM, 2X 470UF 4MOHM (NOSTUFF), 6X 22UF 0805, 2X 22UF 0805 (NOSTUFF), 6X 10UF 0603, 2X 10UF 0603 (NOSTUFF), 9X 1UF 0402, 9X 1UF 0402 (NOSTUFF)
APPLE IMPLEMENTATION: 0X 470UF 4MOHM, 3X 330UF 9MOHM
, 6X 22UF 0603, 2X 22UF 0603 (NOSTUFF), 6X 10UF 0402, 2X 10UF 0402 (NOSTUFF), 9X 1UF 0402, 9X 1UF 0402 (NOSTUFF)
PLACEMENT_NOTE (C1700-C1708):
14 13 8
=PPVCORE_S0_CPU_VCCAXG
Place on bottom side of U1000
U100.
D
NOSTUFF
C1700
1
1
1UF
1
1UF
10%
10V
X6S-CERM
0402
2
C1701
2
C1702
1
C1703
1UF
10%
10V
X6S-CERM
0402
10%
10V
X6S-CERM
0402
2
C1704
1
1UF
10%
10V
X6S-CERM
0402
2
C1705
1
1UF
1
C1706
1UF
2
10%
10V
X6S-CERM
0402
2
10%
10V
X6S-CERM
0402
1
C1722
1
1
C1707
1UF
C1723
10%
10V
X6S-CERM
0402
2
1
1UF
1
1UF
10%
10V
X6S-CERM
0402
2
C1708
2
NOSTUFF
C1709
1
1UF
10%
10V
X6S-CERM
0402
2
C1710
NOSTUFF
1
1UF
10%
10V
X6S-CERM
0402
2
C1711
NOSTUFF
1
1UF
10%
10V
X6S-CERM
0402
2
10%
10V
X6S-CERM
0402
NOSTUFF
C1712
1
1UF
2
C1713
NOSTUFF
1
1UF
10%
10V
X6S-CERM
0402
2
NOSTUFF
C1714
1
1UF
10%
10V
X6S-CERM
0402
2
NOSTUFF
C1715
1
1UF
10%
10V
X6S-CERM
0402
2
1
1UF
10%
10V
X6S-CERM
0402
2
D
NOSTUFF
C1716
C1717
1UF
10%
10V
X6S-CERM
0402
2
10%
10V
X6S-CERM
0402
PLACEMENT_NOTE (C1718-C1723):
Place close to U1000 on bottom side
NOSTUFF
C1718
1
1
10UF
C1720
1
10UF
20%
4V
X6S
0402
2
C1719
2
C1721
1
10UF
20%
4V
X6S
0402
10UF
20%
4V
X6S
0402
2
10UF
20%
4V
X6S
0402
2
20%
4V
X6S
0402
2
1
10UF
1
10UF
20%
4V
X6S
0402
2
NOSTUFF
C1724
2
C1725
10UF
20%
4V
X6S
0402
2
20%
4V
X6S
0402
PLACEMENT_NOTE (C1726-C1731):
Place near inductors on bottom side.
NOSTUFF
C1726
1
1
22UF
1
22UF
20%
4V
X6S
0603
2
C1727
2
C1728
1
C1729
22UF
20%
4V
X6S
0603
2
1
22UF
20%
4V
X6S
0603
2
C1730
1
C1731
22UF
20%
4V
X6S
0603
2
1
20%
4V
X6S
0603
2
NOSTUFF
C1732
22UF
1
C1733
22UF
20%
4V
X6S
0603
2
22UF
20%
4V
X6S
0603
2
20%
4V
X6S
0603
PLACEMENT_NOTE (C1734-C1735):
CRITICAL
C
1
1
330UF-6MOHM
20%
2 2.0V
POLY-TANT
D15T
3
CRITICAL
CRITICAL
C1734
C1735
1
330UF-6MOHM
3
20%
2 2.0V
POLY-TANT
D15T
C
C1737
330UF-6MOHM
20%
2 2.0V
POLY-TANT
D15T
3
(Z = 1.5mm, place on tall side next to CPU & under heat pipe)
CPU VCCSA DECOUPLING
CPU VDDQ/VCCDQ DECOUPLING
Intel recommendation: 1x 330uF, 5x 10uF 0603, 5x 1uF 0402
Apple Implementation: 1x 330uF, 5x 10uF 0603, 5x 1uF 0402
Intel recommendation: 1x 330uF, 8x 10uF 0603, 10x 1uF 0402
Apple Implementation: 1x 330uF, 8x 10uF 0603, 10x 1uF 0402
PLACEMENT_NOTE (C1758-C1762):
PLACEMENT_NOTE (C1738-C1747):
27 14 11 8
=PP1V5_S3_CPU_VCCDDR
Place on bottom side of U1000
U100.
1
C1738
1
1UF
C1739
C1740
1UF
10%
10V
X6S-CERM
0402
2
13 8
1
2
1
1UF
10%
10V
X6S-CERM
0402
C1741
1UF
10%
10V
X6S-CERM
0402
2
1
2
10%
10V
X6S-CERM
0402
C1742
1
1UF
2
C1743
1
1UF
10%
10V
X6S-CERM
0402
2
C1752
1
C1744
1
1UF
10%
10V
X6S-CERM
0402
2
C1745
1
1UF
10%
10V
X6S-CERM
0402
2
10%
10V
X6S-CERM
0402
C1746
1
1UF
2
10%
10V
X6S-CERM
0402
=PPVCCSA_S0_CPU
Place on bottom side of U1000
U100.
C1747
1
1UF
2
C1758
1
C1759
1
C1760
1
C1761
1UF
1UF
1UF
10%
10V
X6S-CERM
0402
2
10%
10V
X6S-CERM
0402
10%
10V
X6S-CERM
0402
10%
10V
X6S-CERM
0402
1
C1763
1
C1764
1
1UF
2
10%
10V
X6S-CERM
0402
2
2
C1762
1UF
2
10%
10V
X6S-CERM
0402
1
C1767
Place close to U1000 on bottom side
1
C1748
1
10UF
B
C1749
1
C1750
10UF
20%
4V
X6S-CERM
0603
2
2
1
10UF
20%
4V
X6S-CERM
0603
2
C1751
1
10UF
20%
4V
X6S-CERM
0603
2
20%
4V
X6S-CERM
0603
10UF
2
20%
4V
X6S-CERM
0603
C1753
1
10UF
2
20%
4V
X6S-CERM
0603
C1754
1
10UF
2
C1755
10UF
20%
4V
X6S-CERM
0603
2
20%
4V
X6S-CERM
0603
2
Place near inductors on bottom side
1
C1765
1
C1766
10UF
10UF
10UF
20%
4V
X6S-CERM
0603
20%
4V
X6S-CERM
0603
20%
4V
X6S-CERM
0603
20%
4V
X6S-CERM
0603
2
2
2
10UF
2
B
20%
4V
X6S-CERM
0603
C1756
CRITICAL
330UF-0.006OHM
2
1
10UF
20%
2V
POLY
CASE-D2-SM
1
C1768
330UF-6MOHM
3
20%
2 2.0V
POLY-TANT
D15T-ECGLT-COMBO
(Z = 1.5mm, place on tall side next to CPU & under heat pipe)
Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402
R1700
1
0.010
1%
1/4W
MF
0603
2
=PP1V5_S3_CPU_VCCDQ
1
8 13
C1757
1UF
2
10%
10V
X6S-CERM
0402
A
SYNC_MASTER=D2_SEAN
SYNC_DATE=03/05/2012
PAGE TITLE
CPU DECOUPLING-II
DRAWING NUMBER
Apple Inc.
051-9589
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
4.18.0
BRANCH
PAGE
17 OF 132
SHEET
16 OF 99
1
A
7
6
5
4
3
2
OMIT_TABLE
C20
C38
(IPU) LDRQ0*
LDRQ1*/GPIO23
(IPU)
SERIRQ
PANTHERPOINT
MOBILE
FCBGA
(1 OF 10)
17
D20
RTC_RESET_L
RTCRST*
D
PCH_SRTCRST_L
G22
SRTCRST*
17
PCH_INTRUDER_L
K22
INTRUDER*
17
C17
PCH_INTVRMEN_L
RTC
LPC
17
INTVRMEN
LPC_AD_R & lt; 0 & gt;
LPC_AD_R & lt; 1 & gt;
LPC_AD_R & lt; 2 & gt;
LPC_AD_R & lt; 3 & gt;
17
D36
LPC_FRAME_R_L
17
E36
TP_LPC_DREQ0_L
TBT_PWR_EN_PCH
A38
B37
C37
17
92 38 7
IN
17
92 38 7
IN
=PP3V3_S0_PCH
17
K36
V5
92 38 7
R1820
5%
1/20W
MF
2 201
OUT
25
LPC_SERIRQ
OUT
92 34
10K
7
OUT
92 38 7
1
8 23
IN
92 34
IN
92 34
OUT
92 34
OUT
7 41 43
BI
9
IN
9
92 17
92 17
HDA_BIT_CLK_R
N34
HDA_SYNC_R
L34
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
HDA_BCLK
HDA_SYNC (IPD-BOOT)
VSel strap not functional (VCCVRM = 1.8V)
92 53
IN
7
7
7
92 25 17
20
17
K34
HDA_RST_R_L
E34
HDA_SDIN0
TP_HDA_SDIN1
TP_HDA_SDIN2
TP_HDA_SDIN3
G34
C34
A34
A36
HDA_SDOUT_R
C36
JTAG_ISP_TMS
ENET_MEDIA_SENSE_RDIV
OUT
IN
N32
SPKR (IPD-PLTRST#)
HDA_RST*
HDA_SDIN0
HDA_SDIN1
HDA_SDIN2
HDA_SDIN3
(IPD)
(IPD)
(IPD)
(IPD)
HDA_DOCK_EN*/GPIO33
HDA_DOCK_RST*/GPIO13
JTAG_TCK (IPD)
XDP_PCH_TMS
H7
IN
JTAG_TMS (IPU)
24
92 43
92 43
OUT
XDP_PCH_TDO
H1
T3
OUT
SPI_CLK_R
OUT
SPI_CS0_R_L
Y14
TP_SPI_CS1_L
T1
SPI_MOSI_R
V4
AD7
AM8
AP10
92 43
OUT
AH5
AH4
JTAG_TDI (IPU)
JTAG_TDO
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
=PPVRTC_G3_PCH
SPI_CS1*
SATAICOMPO
SATAICOMPI
SATA3RCOMPO
SATA3COMPI
SATA3RBIAS
1
39 91
OUT
39 91
9
IN
9
IN
IN
9 91
9
OUT
9
OUT
IN
9 91
OUT
9 91
OUT
9 91
7
7
7
7
7
TP_SATA_D_D2RN
TP_SATA_D_D2RP
TP_SATA_D_R2D_CN
TP_SATA_D_R2D_CP
AF3
AF1
Y7
7
7
7
7
7
7
7
TP_SATA_E_D2RN
TP_SATA_E_D2RP
TP_SATA_E_R2D_CN
TP_SATA_E_R2D_CP
Y5
AD3
AD1
Y3
7
Y1
AB3
AB1
Y11
91
=PP1V05_S0_PCH_VCCIO_SATA
7
1
R1830
7
37.4
7
7
1%
1/20W
MF
2 201
7
7
7
7
7
=PP1V05_S0_PCH
8 23
7
92 38 7
PCH_SATAICOMP
AB12
2
P3
92 38 7
P1
OUT
39 17
1%
1/20W
MF
201
PCIE_AP_D2R_N
PCIE_AP_D2R_P
PCIE_AP_R2D_C_N
PCIE_AP_R2D_C_P
BE34
PCIE_FW_D2R_N
PCIE_FW_D2R_P
PCIE_FW_R2D_C_N
PCIE_FW_R2D_C_P
BG36
R1800
1
330K
1M
5%
1/20W
MF
201 2
AY32
BJ36
AV34
AU34
BF36
TP_PCIE_5_D2RN
TP_PCIE_5_D2RP
TP_PCIE_5_R2D_CN
TP_PCIE_5_R2D_CP
BG37
TP_PCIE_6_D2RN
TP_PCIE_6_D2RP
TP_PCIE_6_R2D_CN
TP_PCIE_6_R2D_CP
BJ38
TP_PCIE_7_D2RN
TP_PCIE_7_D2RP
TP_PCIE_7_R2D_CN
TP_PCIE_7_R2D_CP
BG40
TP_PCIE_8_D2RN
TP_PCIE_8_D2RP
TP_PCIE_8_R2D_CN
TP_PCIE_8_R2D_CP
BE38
BE36
AY34
BB34
BH37
AY36
BB36
BG38
AU36
AV36
BJ40
AY40
BB40
92 9
17
BC38
AW38
AY38
Y40
PCIE_CLK100M_ENET_N
PCIE_CLK100M_ENET_P
Y39
J2
SSD_CLKREQ_L
AB49
PCIE_CLK100M_FW_N
PCIE_CLK100M_FW_P
AB47
M1
FW_CLKREQ_L
V14
R1832
OUT
OUT
24
24
92 34
OUT
750
17
XDP_DC2_PCH_GPIO21_DP_AUXCH_ISOL
XDP_DC3_PCH_GPIO19_SATARDRVR_EN
92 34
OUT
1%
1/20W
MF
2 201
34 17
AA48
PCIE_CLK100M_AP_N
PCIE_CLK100M_AP_P
AA47
IN
AP_CLKREQ_L
V10
Y37
92 9
OUT
20K
92 9
OUT
PCIE_CLK100M_EXCARD_N
PCIE_CLK100M_EXCARD_P
5%
1/20W
MF
2 201
IN
EXCARD_CLKREQ_L
17
RTC_RESET_L
PCH_SRTCRST_L
PCH_INTRUDER_L
PCH_INTVRMEN_L
C1802
1
2
2
1UF
10%
10V
X5R
402
7
17
7
17
17
C1803
17
17
10%
10V
X5R
402
17
LPC_AD_R & lt; 0 & gt;
LPC_AD_R & lt; 1 & gt;
LPC_AD_R & lt; 2 & gt;
LPC_AD_R & lt; 3 & gt;
LPC_FRAME_R_L
R1860
R1861
R1862
R1863
R1864
33
33
33
33
33
1
Y36
A8
OUT
92 17
92 17
92 25 17
1
2
1
2
5%
1/20W
MF
201
5%
1/20W
MF
201
1
2
1
2
1
MF
201
5%
1/20W
MF
201
1/20W
MF
OUT
2
ENET_CLKREQ_L
7 41 43 82 92
OUT
53 92
7 41 43 82 92
BI
1
1
2
R1842
R1869
R1844
R1845
R1847
R1814
R1815
A
10K
10K
10K
10K
10K
10K
10K
10K
10K
1
33
HDA_BIT_CLK_R
R1810
PLACE_NEAR=U1800.N34:1.27mm
33
HDA_SYNC_R
R1811
PLACE_NEAR=U1800.L34:1.27mm
33
HDA_RST_R_L
R1812
PLACE_NEAR=U1800.K34:1.27mm
33
HDA_SDOUT_R
R1813
PLACE_NEAR=U1800.A36:1.27mm
5%
1/20W
MF
201
7
1
2
10K
10K
10K
10K
10K
10K
1
1
2
10K
1
1/20W
MF
201
1/20W
MF
1
1/20W
MF
1/20W
MF
1/20W
MF
201
2
1
1
2
2
1
2
1
2
2
1
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
2
1
2
1
2
201
1/20W
MF
53 92
201
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
1/20W
MF
MF
5%
1/20W
MF
OUT
201
PCH_SPKR
PCH_SATALED_L
ITPCPU_CLK100M_N
C13
BI
USB_EXTD_SEL_XHCI
E14
SML_PCH_1_CLK
SML_PCH_1_DATA
44 92
44 92
M16
D
44 92
OUT
17
OUT
44 92
BI
M7
TP_CLINK_CLK
T11
TP_CLINK_DATA
7
CL_RST1*
P10
TP_CLINK_RESET_L
44 92
7
(IPU/IPD) CL_DATA1
7
17
(IPU/IPD) CL_CLK1
PERN6
PERP6
PETN6
PETP6
PEGCLKRQA_L_GPIO47
AB37
TP_PCIE_CLK100M_PEGAN
TP_PCIE_CLK100M_PEGAP
CLKOUT_DMI_N
CLKOUT_DMI_P
AV22
CLKOUT_DP_N
CLKOUT_DP_P
PERN7
PERP7
PETN7
PETP7
M10
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
AM12
PERN8
PERP8
PETN8
PETP8
CLKOUT_PCIE0N
Controlled by PCIECLKRQ5#
CLKOUT_PCIE0P
CLKIN_DMI_N
PCIECLKRQ0*/GPIO73
CLKIN_DMI_P
CLKOUT_PCIE1N
CLKOUT_PCIE1P
CLKIN_GND1_N
CLKIN_GND1_P
PCIECLKRQ1*/GPIO18
CLKOUT_PCIE2N
CLKOUT_PCIE2P
AB38
DMI_CLK100M_CPU_N
DMI_CLK100M_CPU_P
AM13
BF18
OUT
11 89
OUT
11 89
TP_PCH_CLKOUT_DPN
TP_PCH_CLKOUT_DPP
AU22
OUT
9
OUT
9
PCIE_CLK100M_PCH_N
PCIE_CLK100M_PCH_P
C
17 92
IN
17 92
IN
17 92
IN
17 92
PCH_CLK100M_SATA_N
PCH_CLK100M_SATA_P
IN
17 92
IN
17 92
PCH_CLK14P3M_REFCLK
IN
17 92
PCH_CLK33M_PCIIN
BJ30
IN
PCH_CLK96M_DOT_N
PCH_CLK96M_DOT_P
BE18
IN
25 92
PCH_CLKIN_GNDN1
PCH_CLKIN_GNDP1
BG30
G24
CLKIN_SATA_N
CLKIN_SATA_P
AK7
K45
CLKIN_PCILOOPBACK
CLKOUT_PCIE3N
CLKOUT_PCIE3P
CLKIN_DOT_96N
CLKIN_DOT_96P
REFCLK14IN
PCIECLKRQ2*/GPIO20
17
17
H45
E24
AK5
PCIECLKRQ3*/GPIO25
CLKOUT_PCIE4N
CLKOUT_PCIE4P
DP_AUXCH_ISOL
SATARDRVR_EN
NO STUFF
17
R1841
FW_CLKREQ_L
AP_CLKREQ_L
EXCARD_CLKREQ_L
JTAG_DPMUXUC_TRST_L
ENET_CLKREQ_L
PEG_CLKREQ_L
TBT_CLKREQ_L
24 25
89 11
33MHz clocks must be matched within 5 "
V46
AB42
TP_PCIE_CLK100M_PEBN
TP_PCIE_CLK100M_PEBP
AB40
ITPCPU_CLK100M_P
E6
17
PEGCLKRQB_L_GPIO56
V40
T13
OUT
PCIE_CLK100M_TBT_N
PCIE_CLK100M_TBT_P
V38
OUT
37 17
1
0
2
5%
1/20W
MF
201
TBT_CLKREQ_L
K12
IN
89 24
89 24
V37
AK14
ITPXDP_CLK100M_N
ITPXDP_CLK100M_P
AK13
CLKOUT_PCIE6N
CLKOUT_PCIE6P
XCLK_RCOMP
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P
IN
SYSCLK_CLK25M_SB
1
PCH_CLK96M_DOT_P
PCH_CLK96M_DOT_N
R1891
R1892
10K
10K
1
1
2
PCH_CLK100M_SATA_P
PCH_CLK100M_SATA_N
R1893
R1894
10K
10K
1
2
1
2
PCIE_CLK100M_PCH_P
PCIE_CLK100M_PCH_N
R1895
R1896
10K
10K
1
2
5%
1/20W
MF
201
1/20W
MF
201
5%
1/20W
MF
1/20W
MF
ENET_MEDIA_SENSE_RDIV
GPU:2P
7
17
92 17
201
17
92 17
17 26
92 17
PCH_CLK14P3M_REFCLK
R1897
10K
1
1/20W
MF
9
K49
TP_PCH_GPIO67_CLKOUTFLEX3
9
SYSCLK_CLK25M_SB_R
2
1
17 91
1.8V - & gt; 1.1V
R1873
1%
1/20W
MF
2 201
201
1/20W
MF
201
PCH_CLKIN_GNDP1
PCH_CLKIN_GNDN1
R1870
R1871
10K
10K
1
SYNC_MASTER=D2_KEPLER
Apple Inc.
4
2
051-9589
1/20W
MF
201
5%
1/20W
MF
201
1/20W
MF
201
3
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
2
SIZE
D
REVISION
R
2
1
SYNC_DATE=01/13/2012
PCH SATA/PCIe/CLK/LPC/SPI
DRAWING NUMBER
5%
17
5
TP_PCH_GPIO66_CLKOUTFLEX2
PAGE TITLE
5%
17
6
H47
2
17
17
9
CLKOUTFLEX2/GPIO66
(IPD-PWROK)
201
5%
5%
92 17
PEGCLKRQB_L_GPIO56
CLKOUTFLEX1/GPIO65
(IPD-PWROK)
201
5%
92 17
17 39
MF
9
TP_PCH_GPIO65_CLKOUTFLEX1
2
1
17 37
1/20W
TP_PCH_GPIO64_CLKOUTFLEX0
F47
1K
2
5%
92 17
604
1%
1/16W
MF-LF
402
Unused clock terminations for FCIM Mode
92 17
9 17
5%
K43
R1872
7 17 38
2
PLACE_NEAR=U1800.Y47:2.54mm
PCH_XCLK_RCOMP
CLKOUTFLEX3/GPIO67
(IPD-PWROK)
PCIECLKRQ7*/GPIO46
(IPU-RSMRST#)
Y47
CLKOUTFLEX0/GPIO64
(IPD-PWROK)
2
17
1
1
90.9
CLKOUT_PCIE7N
CLKOUT_PCIE7P
IN
PEG_CLKREQ_L
17 9
0
B
=PP1V05_S0_PCH_VCCDIFFCLK
PCIECLKRQ6*/GPIO45
V42
17
10K
17 91
1%
1/20W
MF
201 2
PEG_CLK100M_N
PEG_CLK100M_P
91 25
R1880
SYSCLK_CLK25M_SB_R
NC
PEG_B_CLKRQ*/GPIO56
OUT
17 34
17
V49
CLKOUT_PEG_B_N
CLKOUT_PEG_B_P
5%
1/20W
MF
201
24
17
V47
23 21 8
OUT
53 92
201
SSD_CLKREQ_L
PEGCLKRQA_L_GPIO47
PEGCLKRQB_L_GPIO56
SMBUS_PCH_ALERT_L
USB_EXTB_SEL_XHCI
USB_EXTD_SEL_XHCI
XTAL25_IN
XTAL25_OUT
PCIECLKRQ5*/GPIO44
(IPU-RSMRST#)
92 71
1
17
Connect to ENET_MEDIA_SENSE via alias if HDA = 3.3V.
Connect to ENET_MEDIA_SENSE via 12K R if HDA = 1.5V.
If HDA = S0, must also ensure that signal cannot be high in S3.
8
G12
PEG_A_CLKRQ*/GPIO47
PERN5
PERP5
PETN5
PETP5
201
1/20W
PERN4
PERP4
PETN4
PETP4
92 71
HDA_SDOUT
2
201
5%
5%
2
1
MF
5%
1
1/20W
5%
GPU:1P
5%
BI
53 92
OUT
201
5%
OUT
HDA_RST_L
5%
201
5%
2
R1879
5%
2
44 92
17
R1890
17
HDA_SYNC
201
2
R1843
R1846
R1848
R1853
R1854
R1855
201
MF
5%
R1834
R1833
MF
1/20W
17 26
OUT
7 41 43 82 92
38 17 7
R1840
1/20W
OUT
SML_PCH_0_CLK
SML_PCH_0_DATA
SML1CLK/GPIO58
SML1DATA/GPIO75
L14
IN
7 41 43 82 92
BI
201
2
1
1/20W
2
1
5%
89 11
5%
USB_EXTB_SEL_XHCI
C8
CLKOUT_PCIE5N
CLKOUT_PCIE5P
92 35
5%
A12
SML0CLK
SML0DATA
PCIECLKRQ4*/GPIO26
OUT
7 41 43 82 92
BI
NO STUFF
2
SML0ALERT*/GPIO60
C9
SML1ALERT*/PCHHOT*/GPIO74
V45
92 35
2
PERN3
PERP3
PETN3
PETP3
L12
92 39
BI
8 18 19 20 25 37
1
PERN2
PERP2
PETN2
PETP2
JTAG_DPMUXUC_TRST_L
Y45
PCIE_CLK100M_SSD_N
PCIE_CLK100M_SSD_P
8 18 19 20
1
OUT
FCBGA
Y43
OUT
7
4.7K
4.7K
SMBUS_PCH_CLK
SMBUS_PCH_DATA
(2 OF 10)
TP_PCIE_CLK100M_PE4N
TP_PCIE_CLK100M_PE4P
92 39
LPC_AD & lt; 0 & gt;
LPC_AD & lt; 1 & gt;
LPC_AD & lt; 2 & gt;
LPC_AD & lt; 3 & gt;
LPC_FRAME_L
HDA_BIT_CLK
2
5%
17
17
R1877
R1878
SMBUS_PCH_ALERT_L
H14
MOBILE
17
92 17
=PP3V3_SUS_PCH_GPIO
=PP3V3_S0_PCH_GPIO
E12
SMBCLK
SMBDATA
PANTHERPOINT
17
1UF
1
SMBALERT*/GPIO11
U1800
PERN1
PERP1
PETN1
PETP1
PLACE_NEAR=U1800.AH1:2.54mm
1
R1803
5%
1/20W
MF
2 201
B
AU32
BB32
5%
1/20W
MF
201 2
R1801
AV32
BF34
20K
1
BJ34
PCIE_EXCARD_D2R_N
PCIE_EXCARD_D2R_P
PCIE_EXCARD_R2D_C_N
PCIE_EXCARD_R2D_C_P
IN
92 9
PLACE_NEAR=U1800.AB12:2.54mm
PCH_SATALED_L
91
OUT
R1831
49.9
PCH_SATA3COMP
PCH_SATA3RBIAS
SPI_MISO (IPU)
8 21 23
BG34
PLACE_NEAR=U1800.Y11:2.54mm
7
Y10
AB13
7
7
TP_SATA_F_D2RN
TP_SATA_F_D2RP
TP_SATA_F_R2D_CN
TP_SATA_F_R2D_CP
AH1
SPI_MOSI (IPD-BOOT)
8 18 21
R1802 1
OUT
1
SPI_CLK
SPI_CS0*
AB8
AB10
SATA0GP/GPIO21
SATA1GP/GPIO19
(IPU)
U3
SPI_MISO
IN
OUT
9
TP_SATA_C_D2RN
TP_SATA_C_D2RP
TP_SATA_C_R2D_CN
TP_SATA_C_R2D_CP
AD5
SATALED*
92 43
9
39 91
OUT
SATA_ODD_D2R_N
SATA_ODD_D2R_P
SATA_ODD_R2D_C_N
SATA_ODD_R2D_C_P
AP11
39 91
IN
7
SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP
SPI
C
IN
AM10
SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP
JTAG
XDP_PCH_TCK
J3
IN
K5
AP5
IN
7
24
XDP_PCH_TDI
AP7
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
HDA_SDO (IPD-BOOT)
24
24
SATA_HDD_D2R_N
SATA_HDD_D2R_P
SATA_HDD_R2D_C_N
SATA_HDD_R2D_C_P
AM1
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
IHDA
92 17
T10
PCH_SPKR
SATA
17
AM3
IN
PCIE_ENET_D2R_N
PCIE_ENET_D2R_P
PCIE_ENET_R2D_C_N
PCIE_ENET_R2D_C_P
SMBUS
NC
1
OMIT_TABLE
FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3
(IPU)
FWH4/LFRAME*
U1800
RTCX1
RTCX2
CLOCKS
A20
SYSCLK_CLK32K_RTC
IN
PCI-E*
C-LINK
91 25
FLEX
CLOCKS
8
4.18.0
BRANCH
PAGE
18 OF 132
SHEET
17 OF 99
1
A
8
7
=PP3V3_SUS_PCH_GPIO
=PP1V05_S0_PCH_VCCIO_PCIE
6
5
4
3
2
1
8 17 18 19 20
8
PLACE_NEAR=U1800.BJ24:12.7mm
R1900
49.9
OMIT_TABLE
89 10
D
IN
89 10
IN
89 10
IN
89 10
IN
89 10
IN
89 10
IN
89 10
OUT
89 10
OUT
89 10
OUT
89 10
OUT
89 10
OUT
89 10
OUT
89 10
DMI0RXN
DMI1RXN
DMI2RXN
DMI3RXN
BE24
BC20
BJ18
BJ20
AW24
AW20
BB18
AV18
AY24
AY20
AY18
AU18
FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7
PANTHERPOINT
MOBILE
FCBGA
(3 OF 10)
DMI0TXP
DMI1TXP
DMI2TXP
DMI3TXP
FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7
DMI0TXN
DMI1TXN
DMI2TXN
DMI3TXN
DMI_S2N_P & lt; 0 & gt;
DMI_S2N_P & lt; 1 & gt;
DMI_S2N_P & lt; 2 & gt;
DMI_S2N_P & lt; 3 & gt;
OUT
OMIT_TABLE
U1800
DMI0RXP
DMI1RXP
DMI2RXP
DMI3RXP
DMI_S2N_N & lt; 0 & gt;
DMI_S2N_N & lt; 1 & gt;
DMI_S2N_N & lt; 2 & gt;
DMI_S2N_N & lt; 3 & gt;
OUT
89 10
BC24
BE20
BG18
BG20
DMI_N2S_P & lt; 0 & gt;
DMI_N2S_P & lt; 1 & gt;
DMI_N2S_P & lt; 2 & gt;
DMI_N2S_P & lt; 3 & gt;
IN
89 10
DMI_N2S_N & lt; 0 & gt;
DMI_N2S_N & lt; 1 & gt;
DMI_N2S_N & lt; 2 & gt;
DMI_N2S_N & lt; 3 & gt;
IN
BJ24
BG25
PCH_DMI_COMP
BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9
FDI_INT AW16
=FDI_DATA_N & lt; 0 & gt;
=FDI_DATA_N & lt; 1 & gt;
=FDI_DATA_N & lt; 2 & gt;
=FDI_DATA_N & lt; 3 & gt;
=FDI_DATA_N & lt; 4 & gt;
=FDI_DATA_N & lt; 5 & gt;
=FDI_DATA_N & lt; 6 & gt;
=FDI_DATA_N & lt; 7 & gt;
=FDI_DATA_P & lt; 0 & gt;
=FDI_DATA_P & lt; 1 & gt;
=FDI_DATA_P & lt; 2 & gt;
=FDI_DATA_P & lt; 3 & gt;
=FDI_DATA_P & lt; 4 & gt;
=FDI_DATA_P & lt; 5 & gt;
=FDI_DATA_P & lt; 6 & gt;
=FDI_DATA_P & lt; 7 & gt;
FDI_INT
IN
9
18 9
IN
9
18 9
OUT
IN
9
7
C12
PCH_SUSACK_L
18
SUSACK* (IPU)
K3
IN
PM_SYSRST_L
70 41 24
IN
PM_PCH_SYS_PWROK
P12
SYS_PWROK
70 25
IN
PM_PCH_PWROK
L22
PWROK
41 25
C
70
89 27 11
70
IN
PM_PCH_APWROK
L10
APWROK
OUT
PM_MEM_PWRGD
B13
DRAMPWROK
70 42 41
42
9
9
OUT
IN
9
IN
9
7
IN
9
IN
9
IN
9
IN
9
IN
9
IN
9
IN
9
91 9
OUT
IN
9
91 9
OUT
91 9
OUT
PLACE_NEAR=U1800.AF37:2.54mm
OUT
10 89
91 9
91 9
OUT
91 9
OUT
OUT
9
1
R1915
390K
5%
1/20W
MF
2 201
PCH_DSWVRMEN
PM_DSW_PWRGD
CLKRUN*/GPIO32 N3
PM_CLKRUN_L
SUS_STAT*/GPIO61 G8
SUSCLK/GPIO62 N14
SLP_S5*/GPIO63 D10
PCH_SUSWARN_L
K16
SUSWARN*/SUSPWRDNACK/GPIO30
IN
PM_PWRBTN_L
E20
IN
SMC_ADAPTER_EN
H20 ACPRESENT/GPIO31
PWRBTN* (IPU)
BI
7 18 34
7 18 41 43
OUT
7 25 41 43
PM_CLK32K_SUSCLK_R
OUT
OUT
OUT
7
PM_SLP_S3_L
A10
91 9
91 9
OUT
91 9
R1909
100K
5%
1/20W
MF
2 201
OUT
OUT
OUT
OUT
9
7 18 27 38 41 70
OUT
91 9
7 18 27 34 38 40 41 70
OUT
91 9
OUT
9
91 9
OUT
PMSYNCH AP14
SLP_LAN*/GPIO29 K14
RI*
PM_SLP_SUS_L
PM_SYNC
MEM_VDD_SEL_1V5_L
OUT
18 70
OUT
OUT
7
A
1K
1
5%
2
1/20W
MF
R1986
2
0
1
1
2
1
100K
100K
2
2
1
1/20W
MF
9
9
9
9
TP_DP_IG_C_MLN & lt; 0 & gt;
TP_DP_IG_C_MLP & lt; 0 & gt;
TP_DP_IG_C_MLN & lt; 1 & gt;
TP_DP_IG_C_MLP & lt; 1 & gt;
TP_DP_IG_C_MLN & lt; 2 & gt;
TP_DP_IG_C_MLP & lt; 2 & gt;
TP_DP_IG_C_MLN & lt; 3 & gt;
TP_DP_IG_C_MLP & lt; 3 & gt;
83
83
83 95
83 95
9 82
C
7
7
7
7
7
7
7
7
M43
M36
TP_DP_IG_D_CTRL_CLK
TP_DP_IG_D_CTRL_DATA
AT45
AT43
BH41
TP_DP_IG_D_AUXN
TP_DP_IG_D_AUXP
TP_DP_IG_D_HPD
DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P
BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42
TP_DP_IG_D_MLN & lt; 0 & gt;
TP_DP_IG_D_MLP & lt; 0 & gt;
TP_DP_IG_D_MLN & lt; 1 & gt;
TP_DP_IG_D_MLP & lt; 1 & gt;
TP_DP_IG_D_MLN & lt; 2 & gt;
TP_DP_IG_D_MLP & lt; 2 & gt;
TP_DP_IG_D_MLN & lt; 3 & gt;
TP_DP_IG_D_MLP & lt; 3 & gt;
7
7
7
7
7
7
7
7
7
7
7
7
7
B
18 24 41
18 64
7 18 34
NOSTUFF
201 MAKE_BASE=TRUE
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
1/20W
MF
1/20W
MF
201
PM_SLP_S3_L
PM_SLP_S4_L
PM_SLP_S5_L
PM_SLP_SUS_L
0
2
7 18 27 38 41 70
SYNC_MASTER=D2_KEPLER
R1999
1
=TBT_WAKE_L
1/20W
MF
LVDS_IG_BKL_ON
LVDS_IG_PANEL_PWR
PCH DMI/FDI/PM/Graphics
35 42
5%
1/20W
MF
201
DRAWING NUMBER
Apple Inc.
7 18 27 34 38 40 41 70
18 41 70
051-9589
18 70
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
9 18
9 18
6
5
4
3
2
SIZE
D
REVISION
R
201
7
SYNC_DATE=01/13/2012
PAGE TITLE
IN
201
5%
5%
8
9
7 18 41 43
MEM_VDD_SEL_1V5_L
5%
1
AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49
9
DPB_IG_AUX_CH_N
DPB_IG_AUX_CH_P
DPB_IG_HPD
DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P
9
DPB_IG_DDC_CLK
DPB_IG_DDC_DATA
AP47
AP49
AT38
9
5%
1/20W
MF
2 201
18
PCIE_WAKE_L
1
2
P46
P42
83 95
1K
PCH_SUSACK_L
201
1
2
DAC_IREF
CRT_IRTN
DDPC_CTRLCLK
DDPC_CTRLDATA
(IPD-PLTRST#)
DDPC_AUXN
DDPC_AUXP
DDPC_HPD
83 95
9 82
201
2
100K
100K
100K
100K
T43
T42
TP_DP_IG_B_MLN & lt; 0 & gt;
TP_DP_IG_B_MLP & lt; 0 & gt;
TP_DP_IG_B_MLN & lt; 1 & gt;
TP_DP_IG_B_MLP & lt; 1 & gt;
TP_DP_IG_B_MLN & lt; 2 & gt;
TP_DP_IG_B_MLP & lt; 2 & gt;
TP_DP_IG_B_MLN & lt; 3 & gt;
TP_DP_IG_B_MLP & lt; 3 & gt;
83
201
MF
5%
R1924
R1921
R1922
R1923
R1981
R1984
CRT_HSYNC
CRT_VSYNC
AV42
AV40
AV45
AV46
AU48
AU47
AV47
AV49
83
R1951
PM_CLKRUN_L
MF
1/20W
2
1
M47
M49
DPA_IG_AUX_CH_N
DPA_IG_AUX_CH_P
DPA_IG_HPD
DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P
7
DPA_IG_DDC_CLK
DPA_IG_DDC_DATA
AT49
AT47
AT40
7
1
PM_PWRBTN_L
1/20W
5%
1
CRT_DDC_CLK
CRT_DDC_DATA
7
TP_SDVO_INTN
TP_SDVO_INTP
P38
M39
D
7
DDPD_CTRLCLK
DDPD_CTRLDATA
(IPD-PLTRST#)
DDPD_AUXN
DDPD_AUXP
DDPD_HPD
CRT_BLUE
CRT_GREEN
CRT_RED
T39
M40
7
TP_SDVO_STALLN
TP_SDVO_STALLP
8
5%
1K
N48
P49
T49
7
8 17 19 20 25 37
2
10K
TP_SDVO_TVCLKINN
TP_SDVO_TVCLKINP
SDVO_STALLN AM42
(IPD)
SDVO_STALLP AM40
(IPD)
SDVO_INTN AP39
(IPD)
SDVO_INTP AP40
(IPD)
8 17 18 19 20
2
1
LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3
PLACE_NEAR=U1800.T43:2.54mm
5%
1/20W
MF
201
8.2K
AH43
AH49
AF47
AF43
18 64
7
10K
R1985
R1991
R1982
R1925
LVDSB_DATA0*
LVDSB_DATA1*
LVDSB_DATA2*
LVDSB_DATA3*
TP_CRT_IG_HSYNC
TP_CRT_IG_VSYNC
11 89
R19831
=PP3V3_SUS_PCH_GPIO
=PP3V3_S0_PCH_GPIO
=PP3V3_S5_PCH
AH45
AH47
AF49
AF45
TP_CRT_IG_DDC_CLK
TP_CRT_IG_DDC_DATA
7
7
B
LVDSB_CLK*
LVDSB_CLK
TP_CRT_IG_BLUE
TP_CRT_IG_GREEN
TP_CRT_IG_RED
7
=PP3V3_SUS_PCH_GPIO
PCH_SUSWARN_L
AF40
AF39
TP_PM_SLP_A_L
7
18
LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3
LVDS_IG_B_DATA_P & lt; 0 & gt;
LVDS_IG_B_DATA_P & lt; 1 & gt;
LVDS_IG_B_DATA_P & lt; 2 & gt;
LVDS_IG_B_DATA_P & lt; 3 & gt;
OUT
1
7
5%
1/20W
MF
201 2
AN47
AM49
AK49
AJ47
PCH_DAC_IREF
(IPD-DeepS4/S5)
BATLOW*/GPIO72 (IPU)
E10
PM_BATLOW_L
PCH_RI_L
20 19 18 17 8
LVDSA_DATA0*
LVDSA_DATA1*
LVDSA_DATA2*
LVDSA_DATA3*
LVDS_IG_B_DATA_N & lt; 0 & gt;
LVDS_IG_B_DATA_N & lt; 1 & gt;
LVDS_IG_B_DATA_N & lt; 2 & gt;
LVDS_IG_B_DATA_N & lt; 3 & gt;
OUT
18 41 70
SLP_S3* F4
AN48
AM47
AK47
AJ48
LVDS_IG_B_CLK_N
LVDS_IG_B_CLK_P
OUT
42
PM_SLP_S5_L
PM_SLP_S4_L
SLP_A* G10
G16
SLP_SUS*
41
OUT
7
IN
LPC_PWRDWN_L
SLP_S4* H4
RSMRST*
91 9
91 9
IN
LVDSA_CLK*
LVDSA_CLK
LVDS_IG_A_DATA_P & lt; 0 & gt;
LVDS_IG_A_DATA_P & lt; 1 & gt;
LVDS_IG_A_DATA_P & lt; 2 & gt;
LVDS_IG_A_DATA_P & lt; 3 & gt;
OUT
9
PCIE_WAKE_L
AK39
AK40
LVDS_IG_A_DATA_N & lt; 0 & gt;
LVDS_IG_A_DATA_N & lt; 1 & gt;
LVDS_IG_A_DATA_N & lt; 2 & gt;
LVDS_IG_A_DATA_N & lt; 3 & gt;
OUT
91 9
8 17 21
SDVO_TVCLKINN AP43
AP45
SDVO_CTRLCLK
SDVO_CTRLDATA
(IPD-PLTRST#)
DDPB_AUXN
DDPB_AUXP
DDPB_HPD
LVD_VREFH
LVD_VREFL
LVDS_IG_A_CLK_N
LVDS_IG_A_CLK_P
OUT
91 9
=PPVRTC_G3_PCH
FCBGA
(4 OF 10)
LVD_IBG
LVD_VBG
AE48
AE47
1%
1/20W
MF
201 2
OUT
WAKE* B9
AF37
AF36
2.37K
=FDI_LSYNC & lt; 0 & gt;
=FDI_LSYNC & lt; 1 & gt;
C21
IN
7
PCH_LVDS_IBG
TP_PCH_LVDS_VBG
IN
9
DPWROK E22
T45
P39
OUT
OUT
PM_RSMRST_L
IN
18
41 24 18
SYS_RESET*
SYSTEM POWER
MANAGEMENT
1%
1/20W
MF
2 201
TP_LVDS_IG_CTRL_CLK
TP_LVDS_IG_CTRL_DATA
L_DDC_CLK
L_DDC_DATA
(IPD-PLTRST#)
L_CTRL_CLK
L_CTRL_DATA
9
PLACE_NEAR=U1800.BH21:2.54mm
750
T40
K47
9
OUT
DSWVRMEN A18
LVDS_IG_DDC_CLK
LVDS_IG_DDC_DATA
9
9
R1920
L_BKLTCTL
IN
R19501
U1800
(IPD)
PANTHERPOINT
SDVO_TVCLKINP
MOBILE
(IPD)
P45
OUT
IN
=FDI_FSYNC & lt; 0 & gt;
=FDI_FSYNC & lt; 1 & gt;
1
L_BKLTEN
L_VDD_EN
LVDS_IG_BKL_PWM
7
FDI_LSYNC0 AV14
FDI_LSYNC1 BB10
DMI2RBIAS
J47
M45
LVDS_IG_BKL_ON
LVDS_IG_PANEL_PWR
OUT
FDI_FSYNC0 AV12
FDI_FSYNC1 BC10
DMI_ZCOMP
DMI_IRCOMP
BH21
PCH_DMI2RBIAS
BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9
DIGITAL DISPLAY INTERFACE
89 10
LVDS
1%
1/20W
MF
2 201
CRT
10K
5%
1/20W
MF
201 2
1
DMI
FDI
R19051
4.18.0
BRANCH
PAGE
19 OF 132
SHEET
18 OF 99
1
A
8
7
6
5
4
3
2
1
OMIT_TABLE
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
D
BG26
BJ26
BH25
BJ16
BG16
AH38
AH37
AK43
AK45
C18
N30
H3
AH12
AM4
AM5
Y13
K24
L24
AB46
AB45
B21
NC
NC
M20
AY16
TP_PCH_TP23
U1800
TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18
TP19
TP20
PANTHERPOINT
MOBILE
FCBGA
(5 OF 10)
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
TP21
TP22
TP23
TP24
AY7
AV7
AU3
BG4
AT10
BC8
AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6
91 9
IN
9
IN
C
91 40
IN
91 38 7
IN
91 9
IN
9
IN
91 40
OUT
91 38
OUT
91 9
OUT
9
OUT
91 40
OUT
91 38
OUT
9
OUT
10K
10K
10K
10K
1
2
1
2
1
2
1
2
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
OUT
B
NO STUFF
R2054
10K
2
1
5%
1/20W
MF
IN
59 19
IN
35 19
IN
58 19
IN
7
27 25
OUT
92 25
8 25
7
8 17 18 19 20 25 37
2
2
2
25
1
5%
1/20W
MF
201
5%
1/20W
MF
201
1/20W
MF
1/20W
MF
A
10K
10K
1
2
5%
1/20W
MF
201
1/20W
MF
1
1/20W
MF
MF
R2067
10K
2
1
2
1
2
2
K38
PIRQA*
PIRQB*
PIRQC*
PIRQD*
H38
G38
JTAG_GMUX_TMS
BLC_I2C_MUX_SEL
USE_HDD_OOB_L
C46
D47
G42
TP_PCI_PME_L
K10
C44
E40
E42
F46
OUT
G40
C42
D44
C6
PLT_RESET_L
H49
LPC_CLK33M_SMC_R
LPC_CLK33M_LPCPLUS_R
TP_PCI_CLK33M_OUT2
TP_PCI_CLK33M_OUT3
PCH_CLK33M_PCIOUT
H43
J48
K42
H40
REQ1*/GPIO50
REQ2*/GPIO52
REQ3*/GPIO54
GNT1*/GPIO51
GNT2*/GPIO53
GNT3*/GPIO55
(IPU-PCIERST#)
PIRQE*/GPIO2
PIRQF*/GPIO3
PIRQG*/GPIO4
PIRQH*/GPIO5
PME* (IPU)
PLTRST*
CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4
(IPD)
USBP8N
USBP8P
L30
USBP9N
USBP9P
G30
USBP10N
USBP10P
C30
USBP11N
USBP11P
L32
USBP12N
USBP12P
G32
USBP13N
USBP13P
(IPD)
C32
USBRBIAS*
USBRBIAS
C33
OC0*/GPIO59
OC1*/GPIO40
OC2*/GPIO41
OC3*/GPIO42
OC4*/GPIO43
OC5*/GPIO9
OC6*/GPIO10
OC7*/GPIO14
A14
26 91
BI
9 91
BI
9 91
BI
26 91
BI
26 91
Ext B (XHCI)
Ext D (XHCI) (Mobiles: Trackpad?)
TP_USB_4N
TP_USB_4P
B29
RSVD: SD
TP_USB_WLANN
TP_USB_WLANP
A28
Unused
TP_USB_SDN
TP_USB_SDP
D28
RSVD: WiFi
USB_HUB_UP_N
USB_HUB_UP_P
E30
26 91
BI
26 91
BI
34 91
BI
34 91
USB_EXTB_EHCI_N
USB_EXTB_EHCI_P
K30
BI
USB_CAMERA_N
USB_CAMERA_P
M28
BI
26 91
BI
26 91
BI
9
BI
9
USB_EXTD_EHCI_N
USB_EXTD_EHCI_P
A30
USB Hub (All LS/FS Devices)
Camera
Ext B (EHCI)
Ext D (EHCI)
TP_USB_BT_HSN
TP_USB_BT_HSP
A32
91
Unused
TP_USB_13N
TP_USB_13P
E32
RSVD: BT (HS)
TP_USB_12N
TP_USB_12P
K32
C
Ext C (XHCI/EHCI)
Unused
B
PCH_USB_RBIAS
B33
PLACE_NEAR=U1800.B33:2.54mm
1
K20
B17
C16
L16
A16
D14
C14
XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L
XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L
XDP_DA2_PCH_GPIO41_USB_EXTC_OC_L
XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L
XDP_DB0_PCH_GPIO43_USB_EXTB_OC_EHCI_L
XDP_DB1_PCH_GPIO9_USB_EXTD_OC_EHCI_L
XDP_DB2_PCH_GPIO10_AP_PWR_EN
XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE
IN
IN
19 24
IN
19 24
IN
19 24
IN
22.6
19 24
IN
R2070
19 24
19 24
OUT
IN
1%
1/20W
MF
2 201
24
19 24
19
19
19
19
XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L
R2020
1K
1
2
24 19
XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L
R2021
1K
1
2
XDP_DB0_PCH_GPIO43_USB_EXTB_OC_EHCI_L
5%
1/20W
5%
19 59
1/20W
MF
MF
19 24
201
XDP_DB1_PCH_GPIO9_USB_EXTD_OC_EHCI_L
19 24
201
19 35
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
1/20W
MF
SYNC_MASTER=D2_KEPLER
SYNC_DATE=01/13/2012
PAGE TITLE
19 58
PCH PCI/USB/TP/RSVD
201
XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE
1
1/20W
MF
DRAWING NUMBER
19 24
XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L
XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L
XDP_DA2_PCH_GPIO41_USB_EXTC_OC_L
XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L
AP_PWR_EN
5%
8
USBP7N
USBP7P
N28
26 91
BI
Ext A (XHCI/EHCI)
201
2
1
K40
PCI_INTA_L
PCI_INTB_L
PCI_INTC_L
PCI_INTD_L
C29
BI
USB_EXTD_XHCI_N
USB_EXTD_XHCI_P
H28
40 91
USB_EXTC_N
USB_EXTC_P
A26
40 91
BI
USB_EXTB_XHCI_N
USB_EXTB_XHCI_P
B25
BI
201
1/20W
2
1
5%
5%
1
10K
10K
10K
10K
1/20W
5%
10K
AW30
C28
USB_EXTA_N
USB_EXTA_P
A24
24 19
AUD_IP_PERIPHERAL_DET
TBT_PWR_REQ_L
AUD_I2C_INT_L
5%
R2060
R2061
R2062
R2068
AV28
E28
USBP6N
USBP6P
USB3TP1
USB3TP2
USB3TP3
USB3TP4
USBP4N
USBP4P
NC
NC
K28
USBP5N
USBP5P
USB3TN1
USB3TN2
USB3TN3
USB3TN4
NC
NC
C26
USBP3N
USBP3P
NC
C25
USBP2N
USBP2P
NC
NC
C24
USBP1N
USBP1P
USB3RP1
USB3RP2
USB3RP3
USB3RP4
D
Redundant to pull-up on audio page
2
R2069
AY26
BF3
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
201
NO STUFF
10K
AY30
Redundant to pull-up on audio page
5%
R2033
JTAG_GMUX_TMS
BLC_I2C_MUX_SEL
USE_HDD_OOB_L
BLC_GPIO
2
1
AU28
201
2
NO STUFF
R2014
R2031
BB26
AT12
BA2
NC
NC
201
5%
10K
OUT
25
5%
R2030
OUT
25
8 17 18 20
1
BG32
201
19
1
AU26
BF32
BLC_GPIO
AUD_IP_PERIPHERAL_DET
TBT_PWR_REQ_L
AUD_I2C_INT_L
OUT
19
1
USB3_EXTA_TX_P
USB3_EXTB_TX_P
USB3_EXTC_TX_P
USB3_EXTD_TX_P
BE30
TP_PCH_STRP_BBS1
TP_PCH_STRP_ESI_L
PCH_STRP_TOPBLK_SWP_L
OUT
19
10K
10K
10K
AV26
BJ32
AY5
AV10
USBP0N
USBP0P
USB3RN1
USB3RN2
USB3RN3
USB3RN4
201
19
R2016
R2017
R2018
USB3_EXTA_TX_N
USB3_EXTB_TX_N
USB3_EXTC_TX_N
USB3_EXTD_TX_N
BE32
=PP3V3_S0_PCH_GPIO
R2010
R2011
R2012
R2013
=PP3V3_SUS_PCH_GPIO
=PP3V3_S3_PCH_GPIO
=PP3V3_S0_PCH_GPIO
BC28
BC30
PCI
37 25 20 19 18 17 8
OUT
91 9
BE28
USB3_EXTA_RX_P
USB3_EXTB_RX_P
USB3_EXTC_RX_P
USB3_EXTD_RX_P
IN
USB
USB3_EXTA_RX_N
USB3_EXTB_RX_N
USB3_EXTC_RX_N
USB3_EXTD_RX_N
IN
AT8
RSVD28
RSVD29
91 40
AV5
RSVD26
RSVD27
91 38 7
RSVD23
RSVD24
RSVD25
NC
BG46
NC
NC
NC
NC
Apple Inc.
19 24
19 24
R
19 24
NOTICE OF PROPRIETARY PROPERTY:
SIZE
D
4.18.0
BRANCH
19 24
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
24 34 70
201
7
051-9589
REVISION
6
5
4
3
2
PAGE
20 OF 132
SHEET
19 OF 99
1
A
8
7
6
5
4
3
2
1
TABLE_BOMGROUP_HEAD
BOM GROUP
BOM OPTIONS
RAMCFG_SLOT
RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:H
TABLE_BOMGROUP_ITEM
Systems with no chip-down memory should pull all 4 RAMCFG GPIOs high.
Systems with chip-down memory should add pull-downs on another page and set straps per software.
37 25 20 19 18 17 8
=PP3V3_S0_PCH_GPIO
RAMCFG3:H
R2172 1
RAMCFG2:H
1
10K
D
OMIT_TABLE
(TBT_CIO_PLUG_EVENT_ISOL)
T7
U1800
XDP_FC1_PCH_GPIO0
FW_PME_L
A42
IN
TACH1/GPIO1
82 20
IN
DPMUX_UC_IRQ
H36
TACH2/GPIO6
(6 OF 10)
41 20
IN
SMC_RUNTIME_SCI_L
E38
TACH3/GPIO7
TP_PCH_GPIO8
C10
PANTHERPOINT
WOL_EN
C4
OUT
U2
OUT
XDP_DD2_PCH_GPIO16_AUD_IPHS_SWITCH_EN_PCH
SATA4GP/GPIO16
2
D
5%
1/20W
MF
201
SMC_WAKE_SCI_L
OUT
24
XDP_DC0_PCH_GPIO28_ISOLATE_CPU_MEM_L
2
20
5%
MF
1/20W
201
24
OUT
GPIO27 (IPU-DeepS4/S5)
P8
GPIO28 (IPU-RSMRST#)
TBT_SW_RESET_R_L
K1
K4
OUT
XDP_DD0_PCH_GPIO36_DP_GPU_TBT_SEL
24
XDP_DD1_PCH_GPIO37_JTAG_ISP_TCK
M5
OUT
20
JTAG_ISP_TDO
N2
IN
20
OUT
JTAG_ISP_TDI
OUT
FW_PWR_EN_PCH
25 20
24
52 43 20 7
PROCPWRGD
R2170
PCH_RCIN_L
AY11
PCH_PROCPWRGD
43
1
CPU_PECI
2
BI
1/20W
201
11 42 89
20
THRMTRIP*
M3
0
1
AY10
42
R2156
PM_THRMTRIP_L_R
390
1
INIT3_3V*
(IPU)
T14
DF_TVS
(IPD-PLTRST#?)
AY1
AH8
P37
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_NCTF_22
VSS_NCTF_23
VSS_NCTF_24
VSS_NCTF_25
VSS_NCTF_26
VSS_NCTF_27
VSS_NCTF_28
VSS_NCTF_29
VSS_NCTF_30
VSS_NCTF_31
=PP1V8_S0_PCH_VCC_DFTERM
CPU_PWRGD
2
OUT
1/20W
201
IN
1/20W
201
8 21 23
11 24 89
1
PM_THRMTRIP_L
2
5%
MF
11 42 89
R2179
2.2K
5%
1/20W
MF
201
BG2
SATA2GP/GPIO36
(IPD-PLTRST#)
SATA3GP/GPIO37
(IPD-PLTRST#)
SLOAD/GPIO38
SDATAOUT0/GPIO39
V13
R2140
5%
MF
NC_1
GPIO35
24 20
20
P5
TS_VSS1
TS_VSS2
TS_VSS3
TS_VSS4
STP_PCI*/GPIO34
XDP_DC1_PCH_GPIO35_MXM_GOOD
V8
C
RCIN*
GPIO24
E16
IN
41 20
PCH_PECI
SCLOCK/GPIO22
E8
TBT_GO2SX_BIDIR
PCH_A20GATE
AU16
5%
MF
TACH0/GPIO17
PCH_INIT3V3_L
R2178
PCH_DF_TVS
2
NO STUFF
R2130 1
AK11
1K
AH10
5%
1/20W
MF
201
AK10
1K
1
5%
1/20W
MF
201
This has internal pull up and should not pulled low.
2
CPU_PROC_SEL_L
11 89
DF_TVS:DMI & FDI Term Voltage
Set to Vss when Low
Set to Vcc when High
C
THIS SIGNAL IS INTENDED FOR FIRMWARE HUB AND WE ARE NOT USING IT.
2
SDATAOUT1/GPIO48
OUT
XDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCH
V3
SPIROM_USE_MLB
D6
BI
SATA5GP/GPIO49/TEMP_ALERT*
GPIO57
A4
VSS_NCTF_0
VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
A44
A45
A46
A5
A6
B3
B47
BD1
BD49
BE1
BE49
BF1
BF49
NCTF
35 20
P4
NO STUFF
(IPD) PECI
CPU/MISC
ODD_PWR_EN_L
T5
OUT
A20GATE
GPIO
LPCPLUS_GPIO
D40
BI
20
1
2
MLB_RAMCFG0
GPIO15 (IPU)
43 20 7
R2180
10K
LAN_PHY_PWR_CTRL/GPIO12
XDP_FC0_PCH_GPIO15
G2
IN
24
TBT_SW_RESET_L
9
R2175
MLB_RAMCFG1
A40
5%
1/20W
MF
201
FCBGA
24
OUT
9
5%
1/20W
MF
201
MLB_RAMCFG2
C41
2
1
10K
MLB_RAMCFG3
9
2
RAMCFG0:H
R2174 1
10K
GPIO8 (IPU-RSMRST#)
BMBUSY*/GPIO0
20
37
9
B41
TACH6/GPIO70
MOBILE
C40
TACH7/GPIO71
IN
20
TACH4/GPIO68
TACH5/GPIO69
24 20
0
5%
1/20W
MF
201
RAMCFG1:H
R2173
NC
BG48
BH3
BH47
BJ4
BJ44
BJ45
BJ46
BJ5
BJ6
C2
C48
D1
D49
E1
E49
F1
F49
B
B
JTAG Isolation due to glitch in and out of sleep
NOTE: TCK from PCH is Push-Pull CMOS
NOTE: TMS/TDI from PCH is Open Drain
NOTE: TDO from CR is Push-Pull CMOS
37 25 20 19 18 17 8
=PP3V3_S0_PCH_GPIO
1 C2113
0.1UF
CRITICAL
8
8 17 18 19
CRITICAL
=PP3V3_S0_PCH_GPIO
37 25 20 19 18 17 8
=PP3V3_TBT_PCH_GPIO
Q2160
8 17 18 19 20 25 37
1
MF
201
1/20W
MF
201
5%
1
1
2
R2150
R2155
10K
10K
1
2
1
2
R2194
R2192
R2193
10K
10K
100K
1
2
5%
1/20W
MF
201
5%
1/20W
MF
1/20W
MF
201
5%
A
2
1
2
R2191
10K
1
20K
100K
10K
10K
2
1
2
1
2
1
201
5%
1/20W
MF
201
1/20W
MF
2
5%
5%
1/20W
1/20W
MF
MF
MF
5%
1/20W
MF
1/20W
MF
JTAG_ISP_TDI
MF
20 35
7 20 43 52
37 25 20 19 18 17 8
GND
1
R2166
Y2
7
JTAG_TBT_TCK
3
TBT_CIO_PLUG_EVENT_ISOL
OUT 24
Connects to PCH through
current limiting 1K resistor R2574
OUT
35
4
10K
2
5%
1/20W
MF
201
R2161
10K
5%
1/20W
MF
2 201
JTAG_TBT_TDI
OUT
35
SYNC_MASTER=D2_KEPLER
CRITICAL
=PP3V3_S0_PCH_GPIO
Q2162
20 41
1
SOD-VESM-HF
10K
20 82
5%
1/20W
MF
2 201
24 25
20
20
20 24
OUT
JTAG_ISP_TDO
PCH GPIO/MISC/NCTF
8 20
1
DRAWING NUMBER
R2162
10K
Apple Inc.
5%
1/20W
MF
2 201
JTAG_TBT_TDO
5
051-9589
IN
NOTICE OF PROPRIETARY PROPERTY:
35
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
4
3
2
SIZE
D
REVISION
R
9 24 25
6
SYNC_DATE=01/13/2012
PAGE TITLE
=PP3V3_TBT_PCH_GPIO
201
7
Y1
SSM3K15FV
201
ENET_LOW_PWR_PCH
1/20W
IN
5
A1
B1
A2
B2
20
R2186
DPMUX_UC_IRQ
201
AUD_IPHS_SWITCH_EN_PCH
201
ODD_PWR_EN_L
201
XDP_DD0_PCH_GPIO36_DP_GPU_TBT_SEL
1
SOT563
2 201
20
201
1
5%
8
5%
1/20W
MF
20
20
WOL_EN
TBT_GO2SX_BIDIR
SPIROM_USE_MLB
SMC_WAKE_SCI_L
1/20W
5%
10K
10K
20 25
2
6
5%
1/20W
MF
201 2
8 20
08
1
1
R2199 SSM6N15AFE
201
5%
R2116
PCH_A20GATE
PCH_RCIN_L
IN
35
10K
=PP3V3_TBT_PCH_GPIO
Q2160
1
20
201
MF
1
2
MF
1/20W
2
R2111
R2195
R2112
R2198
1/20W
5%
5%
1
=PP3V3_S0_PCH_GPIO
201
5%
OUT
CRITICAL
7 20 43
37 25 20 19 18 17 8
TBT_SW_RESET_R_L
FW_PWR_EN_PCH
JTAG_TBT_TMS
R2113
20 41
201
2
35
20
G 1
10K
10K
MF
2
IN
1
Must stuff R2197 when R2180 NO STUFFed.
NO STUFF
R2197
R2184
1/20W
JTAG_ISP_TMS
IN
G 5
1/20W
5%
17
20 24
S
5%
XDP_FC1_PCH_GPIO0
FW_PME_L
SMC_RUNTIME_SCI_L
LPCPLUS_GPIO
24
TBT_PWR_EN
JTAG_ISP_TCK
TBT_CIO_PLUG_EVENT
4
201
S
2
MF
5%
1/20W
MF
201
IN
2
2
1
1/20W
D
1
5%
3
2
6
2
1
D
1
3
10K
10K
10K
100K
35 25
10%
16V
X5R-CERM
0201
U2100
SOT833
TBT_PWR_EN goes high for JTAG Programming
10K
S
2
NO STUFF
R2160
R2185
R2196
R2190
D
Stuff R2160 or R2574, not both
SOT563
5%
1/20W
MF
201
8 20
R2163
G 2
10K
VCC
1
R2188 SSM6N15AFE
2
8
74LVC2G08GT
=PP3V3_S5_PCH_GPIO
=PP3V3_SUS_PCH_GPIO
=PP3V3_S0_PCH_GPIO
4.18.0
BRANCH
PAGE
21 OF 132
SHEET
20 OF 99
1
A
8
7
6
5
4
3
2
1
D
D
23 21 8
AL29
NC
AA19
AA21
AA24
AA26
AA27
AA29
AA31
AC26
AC27
AC29
AC31
AD29
AD31
W21
W23
W24
W26
W29
W31
W33
=PP1V05_S0_PCH_VCCASW
C
PCH output, for decoupling only
PLACE_NEAR=U1800.N16:2.54mm
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
21 8
1 VOLTAGE=3.3V
C2210
0.1UF
23
20%
10V
CERM 2
402
23
23 21 8
23 17 8
VCCASW_3_CLK
VCCASW_4_CLK
VCCASW_5_CLK
VCCASW_6_CLK
VCCASW_7_CLK
VCCASW_8_CLK
VCCASW_9_CLK
VCCASW_10_CLK
VCCASW_11_CLK
VCCASW_12_CLK
VCCASW_13_CLK
VCCASW_14_CLK
VCCASW_15_CLK
VCCASW_16_CLK
VCCASW_17_CLK
VCCASW_18_CLK
VCCASW_19_CLK
VCCASW_20_CLK
NC
8 23
NC-ed per DG
=PP3V3_SUS_PCH_VCCSUS
8 23
=PP5V_S0_PCH_V5REF
23
=PP3V3_SUS_PCH_VCCSUS_GPIO
8 23
N20
N22
P20
P22
=PP3V3_S0_PCH_VCC3_3_GPIO
=PP3V3_S0_PCH_VCC3_3_SATA
AN21
AN26
AN27
AP21
AP23
AP24
AP26
AT24
VCCIO_12_SATA3 AH13
VCCIO_13_SATA3 AH14
AF33 VCCDIFFCLKN
AF34 VCCDIFFCLKN
AG34 VCCDIFFCLKN
VCCIO_17_PCIE
VCCIO_18_PCIE
VCCIO_19_PCIE
VCCIO_20_PCIE
VCCIO_21_PCIE
VCCIO_22_PCIE
VCCIO_23_PCIE
VCCIO_24_PCIE
VCCIO_2_SATA AC16
VCCIO_3_SATA AC17
VCCIO_4_SATA AD17
23 8
NC VCCAPLLSATA pin left as NC per DG
=PP1V8R1V5_S0_PCH_VCCVRM
=PP1V05_S0_PCH_VCCIO_SATA
=PP3V3_S0_PCH_VCC3_3_PCI
=PP1V8R1V5_S0_PCH_VCCVRM
VCCAFDIPLL pin left as NC per DG
NC
BG6 VCCAFDIPLL
23 8
18 17 8
T17 DCPSUS_1_CLK
V19 DCPSUS_2_CLK
NC-ed per DG NC
NC
PLACE_NEAR=U1800.V16:2.54mm
=PP1V05_S0_PCH_V_PROC_IO
BJ8 V_PROC_IO
=PPVRTC_G3_PCH
A22 VCCRTC
C2231
1
1UF
10%
6.3V 2
CERM
402
PLACE_NEAR=U1800.A22:2.54mm
1
C2232
0.1UF
20%
2 10V
CERM
402
MISC
20%
10V
CERM 2
402
1
CPU
1
0.1UF
RTC
C2222
VCCASW_22_MISC T21
VCCASW_23_MISC V21
VCCASW_21_MISC T19
HDA
V16 DCPSST
PPVOUT_S0_PCH_DCPSST
B
=PP1V05_S0_PCH_VCCIO_PLLFDI
AP17 VCCIO_27_PLLFDI
=PP1V05_S0_PCH_VCCDMI_FDI
AU20 VCCDMI_2_FDI
AG33 VCCSSC
=PP1V05_S0_PCH_VCCSSC
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
8
8
23 8
VCCSUSHDA P32
=PP1V05_S0_PCH_VCCASW
8
PP1V8_S0_PCH_VCCTX_LVDS_F
VCCTX_LVDS
VCCTX_LVDS
VCCTX_LVDS
VCCTX_LVDS
23
AM37
AM38
AP36
AP37
C
=PP3V3_S0_PCH_VCC3_3_HVCMOS
8 23
VCCVRM_3_DMI AT16
=PP1V8R1V5_S0_PCH_VCCVRM
8 21
VCCDMI_1_DMI AT20
=PP1V05_S0_PCH_VCC_DMI
8 23
PP1V05_S0_PCH_VCCCLKDMI_F
23
8 20 23
=PP3V3_SUS_PCH_VCC_SPI
8 23
VCC3_3_6_HVCMOS V33
VCC3_3_7_HVCMOS V34
VCCCLKDMI AB36
AP16 VCCVRM_2_FDI
8 21
8 17 21 23
=LVDS_VCCA
BH29 VCC3_3_3_PCIE
21 8
VCCVRM_1_SATA AF11
CKPLUS_WAIVE=PwrTerm2Gnd
AN33 VCCIO_25_DP
AN34 VCCIO_26_DP
VCCIO_6_PLLSATA3 AF14
VCCAPLLSATA AK1
23
VSSADAC U47
VSSALVDS AK37
AN16 VCCIO_15_FDI
AN17 VCCIO_16_FDI
8 17 21 23
VCCIO_5_PLLSATA AF13
PP3V3_S0_PCH_VCCA_DAC_F
BJ22 VCCAPLLEXP
=PP1V05_S0_PCH_VCCIO
VCCADAC U48
VCCALVDS AK36
AN19 VCCIO_28_PLLPCIE
8 23
=PP1V05_S0_PCH_VCCIO_SATA
=PP1V05_S0_PCH_VCCIO_PLLPCIE
8 23
VCC3_3_2_SATA AJ2
FCBGA
(7 OF 10)
=PP1V8_S0_PCH_VCC_DFTERM
23 8
VCC3_3_1_GPIO AA16
VCC3_3_8_GPIO W16
VCC3_3_4_GPIO T34
U1800
PANTHERPOINT
MOBILE
TP_1V05_S0_PCH_VCCAPLLEXP
8
VCCSUS3_3_2_GPIO
VCCSUS3_3_3_GPIO
VCCSUS3_3_4_GPIO
VCCSUS3_3_5_GPIO
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
CRT
23
V5REF P34
AF17 VCCIO_7_CLK
=PP1V05_S0_PCH_VCCDIFFCLK
55mA Max, 5mA Idle
=PP5V_SUS_PCH_V5REFSUS
VCCSUS3_3_1_USB AN24
BD47 VCCADPLLA
BF47 VCCADPLLB
=PP1V05_S0_PCH_VCCIO_CLK
8
V5REF_SUS M26
Y49 VCCVRM_4_CLK
=PP1V8R1V5_S0_PCH_VCCVRM
PP1V05_S0_PCH_VCCADPLLA_F
PP1V05_S0_PCH_VCCADPLLB_F
=PP1V05_S0_PCH_VCCIO_PLLUSB
DCPSUS_4_USB AN23
N16 DCPRTC
PPVOUT_G3_PCH_DCPRTC
T26
AA23
AC23
AD21
AD23
AF21
AF23
AG21
AG23
AG24
AG26
AG27
AG29
AJ23
AJ26
AJ27
AJ29
AJ31
HVCMOS
AL24
=PP3V3_SUS_PCH_VCCSUS_USB
OMIT_TABLE
=PP1V05_S0_PCH_VCC_CORE
1.44 A Max, 474mA Idle
VCCIO
AL24 left as NC per DG
T23
T24
V23
V24
P24
8 23
DMI
BH23
=PP1V05_S0_PCH_VCCIO_USB
FDI
VCCAPLLDMI2 pin left as NC per DG NC
=PP1V05_S0_PCH_VCCIO_CLK
23 21 8
N26
P26
P28
T27
T29
DFT/SPI
T38
USB
V12
PP3V3_S0_PCH_VCC3_3_CLK_F
CLK/MISC
TP_PPVOUT_PCH_DCPSUSBYP
23
PCI/GPIO/
LPC
T16
=PP3V3_S5_PCH_VCCDSW
VCCIO_29_USB
PANTHERPOINT
VCCIO_30_USB
VCCDSW3_3
MOBILE
VCCIO_31_USB
FCBGA
DCPSUSBYP
(8 OF 10) VCCIO_32_USB
VCCIO_33_USB
VCC3_3_5_CLK
VCCSUS3_3_7_USB
VCCAPLLDMI2
VCCSUS3_3_8_USB
VCCIO_14_PLLCLK
VCCSUS3_3_9_USB
VCCSUS3_3_10_USB
DCPSUS_3_CLK
VCCSUS3_3_6_USB
VCCASW_1_CLK
VCCIO_34_PLLUSB
VCCASW_2_CLK
SATA
23 8
U1800
VCC CORE
23 8
AD49 VCCACLK
NC
LVDS
OMIT_TABLE
VCCACLK pin left as NC per DG
VCCDFTERM
VCCDFTERM
VCCDFTERM
VCCDFTERM
AG16
AG17
AJ16
AJ17
VCCSPI V1
8 21 23
B
=PP3V3R1V5_S0_PCH_VCCSUSHDA
10 mA Max, 1mA Idle
8 23 25
C2233
0.1UF
20%
10V
2 CERM
402
PLACE_NEAR=U1800.A22:2.54mm
PLACE_NEAR=U1800.A22:2.54mm
A
SYNC_MASTER=D2_CLEAN
SYNC_DATE=03/19/2012
PAGE TITLE
PCH POWER
DRAWING NUMBER
Apple Inc.
051-9589
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
4.18.0
BRANCH
PAGE
22 OF 132
SHEET
21 OF 99
1
A
8
7
6
5
4
3
OMIT_TABLE
H5
AA17
AA2
AA3
AA33
AA34
AB11
AB14
AB39
AB4
AB43
AB5
AB7
AC19
AC2
AC21
AC24
AC33
AC34
AC48
AD10
AD11
AD12
AD13
AD19
AD24
AD26
AD27
AD33
AD34
AD36
AD37
AD38
AD39
AD4
AD40
AD42
AD43
AD45
AD46
AD8
AE2
AE3
AF10
AF12
AD14
AD16
AF16
AF19
AF24
AF26
AF27
AF29
AF31
AF38
AF4
AF42
AF46
AF5
AF7
AF8
AG19
AG2
AG31
AG48
AH11
AH3
AH36
AH39
AH40
AH42
AH46
AH7
AJ19
AJ21
AJ24
AJ33
AJ34
AK12
AK3
D
C
B
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
U1800
PANTHERPOINT
MOBILE
FCBGA
(9 OF 10)
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AY4 VSS
AK38
AK4
AK42
AK46
AK8
AL16
AL17
AL19
AL2
AL21
AL23
AL26
AL27
AL31
AL33
AL34
AL48
AM11
AM14
AM36
AM39
AM43
AM45
AM46
AM7
AN2
AN29
AN3
AN31
AP12
AP19
AP28
AP30
AP32
AP38
AP4
AP42
AP46
AP8
AR2
AR48
AT11
AT13
AT18
AT22
AT26
AT28
AT30
AT32
AT34
AT39
AT42
AT46
AT7
AU24
AU30
AV11
AV16
AV20
AV24
AV30
AV38
AV4
AV43
AV8
AW14
AW18
AW2
AW22
AW26
AW28
AW32
AW34
AW36
AW40
AW48
AY12
AY22
AY28
AY42 VSS
AY46 VSS
AY8 VSS
B11 VSS
B15 VSS
B19 VSS
B23 VSS
B27 VSS
B31 VSS
B35 VSS
B39 VSS
B7 VSS
F45 VSS
BB12 VSS
BB16 VSS
BB20 VSS
BB22 VSS
BB24 VSS
BB28 VSS
BB30 VSS
BB38 VSS
BB4 VSS
BB46 VSS
BC14 VSS
BC18 VSS
BC2 VSS
BC22 VSS
BC26 VSS
BC32 VSS
BC34 VSS
BC36 VSS
BC40 VSS
BC42 VSS
BC48 VSS
BD46 VSS
BD5 VSS
BE22 VSS
BE26 VSS
BE40 VSS
BF10 VSS
BF12 VSS
BF16 VSS
BF20 VSS
BF22 VSS
BF24 VSS
BF26 VSS
BF28 VSS
BD3 VSS
BF30 VSS
BF38 VSS
BF40 VSS
BF8 VSS
BG17 VSS
BG21 VSS
BG33 VSS
BG44 VSS
BG8 VSS
BH11 VSS
BH15 VSS
BH17 VSS
BH19 VSS
H10 VSS
BH27 VSS
BH31 VSS
BH33 VSS
BH35 VSS
BH39 VSS
BH43 VSS
BH7 VSS
D3 VSS
D12 VSS
D16 VSS
D18 VSS
D22 VSS
D24 VSS
D26 VSS
D30 VSS
D32 VSS
D34 VSS
D38 VSS
D42 VSS
D8 VSS
E18 VSS
E26 VSS
G18 VSS
G20 VSS
G26 VSS
G28 VSS
G36 VSS
G48 VSS
H12 VSS
H18 VSS
H22 VSS
H24 VSS
H26 VSS
H30 VSS
H32 VSS
H34 VSS
F3 VSS
A
8
7
2
1
OMIT_TABLE
6
5
4
3
U1800
PANTHERPOINT
MOBILE
FCBGA
(10 OF 10)
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
H46
K18
K26
K39
K46
K7
L18
L2
L20
L26
D
L28
L36
L48
M12
P16
M18
M22
M24
M30
M32
M34
M38
M4
M42
M46
M8
N18
P30
N47
P11
P18
T33
P40
P43
P47
P7
R2
C
R48
T12
T31
T37
T4
W34
T46
T47
T8
V11
V17
V26
V27
V29
V31
V36
V39
V43
V7
W17
W19
W2
W27
W48
Y12
Y38
Y4
B
Y42
Y46
Y8
BG29
N24
AJ3
AD47
VSS B43
VSS BE10
VSS BG41
VSS G14
VSS H16
VSS T36
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
BG22
BG24
C22
AP13
M14
AP3
AP1
BE16
BC16
SYNC_MASTER=D2_KEPLER
SYNC_DATE=01/13/2012
PAGE TITLE
PCH GROUNDS
BG28
DRAWING NUMBER
BJ28
Apple Inc.
051-9589
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
2
SIZE
D
REVISION
4.18.0
BRANCH
PAGE
23 OF 132
SHEET
22 OF 99
1
A
8
21 8
8
7
=PP3V3_SUS_PCH_VCCSUS
=PP5V_SUS_PCH
1 mA S0-S5
R2404
10
17 8
PCH V5REF_SUS Filter & Follower
(PCH Reference for 5V Tolerance on USB)
25 8
5
=PP3V3_S0_PCH
=PP5V_S0_PCH
1 mA
4
2
R2405
100
BAT54DW-X-G
3
5%
1/16W
MF-LF
402 1
SOT-363
D
C2439
=PP5V_SUS_PCH_V5REFSUS
20%
10V
CERM 2
402
NC
1
1UF
10%
10V
X5R 2
402
21
PLACE_NEAR=U1800.M26:2.54mm
1
=PP3V3_S0_PCH_VCC3_3_GPIO
21 8
=PP1V05_S0_PCH_VCCSSC
C2475
1
BAT54DW-X-G
6
SOT-363
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=5V
MAKE_BASE=TRUE
C2486
0.1UF
10%
25V
2 X5R
402
PP5V_S0_PCH_V5REF
VOLTAGE=5V
MAKE_BASE=TRUE
1
0.1UF
21 8
2
D2400
5
PP5V_SUS_PCH_V5REFSUS
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.25 MM
& lt; 1 mA S0-S5
C2438
3
PCH V5REF Filter & Follower
(PCH Reference for 5V Tolerance on PCI)
NC
NC
4
1
2
D2400
2
NC
5%
1/16W
MF-LF
402 1
6
& lt; 1 mA
=PP5V_S0_PCH_V5REF
1
1
1UF
C2485
10%
6.3V 2
CERM
402
0.1UF
10%
25V
2 X5R
402
PLACE_NEAR=U1800.AG33:2.54mm
PLACE_NEAR=U1800.T34:2.54mm
PLACE_NEAR=U1800.AA16:2.54mm
21
21 17 8
PLACE_NEAR=U1800.P34:2.54mm
21 8
D
=PP1V05_S0_PCH_VCCDIFFCLK
C2434
=PP3V3_S0_PCH_VCC3_3_HVCMOS
1
1UF
10%
6.3V 2
CERM
402
C2424 1
0.1UF
10%
16V
X7R-CERM 2
0402
PLACE_NEAR=U1800.AF34:2.54mm
PLACE_NEAR=U1800.V33:2.54mm
PP1V8_S0_PCH_VCCTX_LVDS_F
NO STUFF
L2407
8
0.1UH
=PP1V8_S0_PCH_VCCTX_LVDS
1
21
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=1.8V
21 8
21 8
2
=PP3V3_S5_PCH_VCCDSW
21 8
=PP1V05_S0_PCH_VCCIO_CLK
C2469
=PP3V3_S0_PCH_VCC3_3_PCI
NOSTUFF
NO STUFF
C2400
1
22UF
20%
6.3V
X5R-CERM-1 2
603
1
C2406
0.01UF
10%
2 16V
X7R-CERM
0402
NO STUFF
1
C2499 1
1
R2401
C2408
10%
2 16V
X7R-CERM
0402
0.1UF
20%
10V
CERM 2
402
5%
1/20W
MF
2 201
0.01UF
C2421 1
0.1UF
0
10%
6.3V 2
CERM
402
10%
16V
X7R-CERM 2
0402
PLACE_NEAR=U1800.T16:2.54mm
PLACE_NEAR=U1800.AF17:2.54mm
PLACE_NEAR=U1800.BH29:2.54mm
PLACE_NEAR=U1800.AM37:2.54MM
PLACE_NEAR=U1800.AM37:2.54mm
PLACE_NEAR=U1800.AM37:2.54mm
PLACE_NEAR=U1800.AM37:2.54mm
21 17 8
21 8
=PP3V3_SUS_PCH_VCC_SPI
21 8
=PP1V05_S0_PCH_VCCIO_SATA
=PP3V3_S0_PCH_VCC3_3_SATA
C2444 1 C2452
8
R2450
=PP3V3_S0_PCH_VCCADAC
0
1
C2442 1
PP3V3_S0_PCH_VCCA_DAC_F
10%
16V
X7R-CERM 2
0402
C2450
10UF
20%
6.3V 2
X5R
603
1
C2451
0.1UF
10%
2 16V
X7R-CERM
0402
1
0.01UF
21 8
=PP3V3_SUS_PCH_VCCSUS_GPIO
21 8
C2476
PLACE_NEAR=U1800.U48:2.54mm
PLACE_NEAR=U1800.U48:2.54mm
PLACE_NEAR=U1800.U48:2.54mm
10%
6.3V
CERM 2
402
PCH VCCIO BYPASS
(PCH USB 1.05V PWR)
=PP1V05_S0_PCH_VCCIO_USB
C2446
1
1UF
1
1UF
10%
6.3V
CERM 2
402
10%
6.3V
CERM 2
402
PLACE_NEAR=U1800.P22:2.54mm
21 8
C
PLACE_NEAR=U1800.AH13:2.54mm
PLACE_NEAR=U1800.AC17:2.54mm
PLACE_NEAR=U1800.AJ2:2.54mm
C2455
10%
2 16V
X7R-CERM
0402
1
1UF
10%
6.3V
CERM 2
402
0.1UF
10%
6.3V
CERM 2
402
PLACE_NEAR=U1800.V1:2.54mm
1
1UF
C2423 1
1UF
21
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
2
5%
1/20W
MF
201
C
1
1UF
0805
PLACE_NEAR=U1800.P28:2.54mm
PCH VCCSUS3_3 BYPASS
(PCH SUSPEND USB 3.3V PWR)
=PP3V3_SUS_PCH_VCCSUS_USB
21 8
=PP1V05_S0_PCH_VCCIO
CRITICAL
8
=PP3V3_S0_PCH_VCC3_3_CLK
R2451
1
1
2
L2451
10UH-0.12A-0.36OHM
1
2
PP3V3_S0_PCH_VCC3_3_CLK_R
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.075 MM
VOLTAGE=3.3V
5%
1/16W
MF-LF
402
0603
C2453
1
10UF
20%
6.3V
X5R 2
603
PP3V3_S0_PCH_VCC3_3_CLK_F
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.075 MM
VOLTAGE=3.3V
1
1
21
0.1UF
10%
2 16V
X7R-CERM
0402
C2454
8
=PP1V05_S0_PCH_VCCADPLL
R2490
1
0
2
L2490
10UH-0.12A-0.36OHM
1
2
PP1V05_S0_PCH_VCCADPLLA_R
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
5%
1/16W
MF-LF
402
C2413
10UF
20%
6.3V 2
X5R
603
10%
2 16V
X7R-CERM
0402
PCH VCCADPLLA Filter
(PCH DPLLA PWR)
PP1V05_S0_PCH_VCCADPLLA_F
MIN_LINE_WIDTH=0.4 MM
68 mA
MIN_NECK_WIDTH=0.2 MM
CRITICAL
PCH VCCSUSHDA BYPASS
=PP3V3R1V5_S0_PCH_VCCSUSHDA
C2441
220UF
(Z = 1.2MM, PLACE ON SHORT SIDE BEHIND PCH)
20%
2.5V 2
TANT
B16
1
21 8
C2420 1
20%
6.3V
X5R-CERM-1 2
603
22UF
PLACE_NEAR=U1800.P32:2.54mm
10%
2 6.3V
CERM
402
1
C2414
1UF
10%
2 6.3V
CERM
402
1
C2407
1UF
1
C2463
1UF
10%
2 6.3V
CERM
402
10%
2 6.3V
CERM
402
1UF
=PP1V8_S0_PCH_VCC_DFTERM
21 8
PLACE_NEAR=U1800.BD47:2.54MM
PLACE_NEAR=U1800.BD47:2.54MM
C2440
C2428 1
22UF
20%
6.3V
X5R-CERM-1 2
603
1
C2426
1UF
10%
6.3V
2 CERM
402
1
C2456
1UF
1
C2496
1UF
10%
6.3V
2 CERM
402
10%
6.3V
2 CERM
402
PLACE_NEAR=U1800.AC27:2.54mm
PLACE_NEAR=U1800.AC27:2.54mm
PLACE_NEAR=U1800.AC27:2.54mm
PLACE_NEAR=U1800.AC27:2.54mm
PLACE_NEAR=U1800.AC27:2.54mm
C2492
21 20 8
1UF
B
1
20%
10V
CERM 2
402
10%
6.3V
2 CERM
402
C2429
=PP1V05_S0_PCH_VCCASW
0.1UF
21
NO STUFF
C2491 1
1
PLACE_NEAR=U1800.AN27:2.54mm
PLACE_NEAR=U1800.AN27:2.54mm
PLACE_NEAR=U1800.AN27:2.54mm
PLACE_NEAR=U1800.AN27:2.54mm
PLACE_NEAR=U1800.AN27:2.54mm
VOLTAGE=1.05V
0603
C2401 1
0.1UF
PLACE_NEAR=U1800.P24:2.54mm
PLACE_NEAR=U1800.V24:2.54mm
1UF
25 21 8
CRITICAL
1
10%
10V
2 X5R
402
PLACE_NEAR=U1800.T38:2.54mm
PLACE_NEAR=U1800.T38:2.54mm
B
C2484
PCH VCCCORE BYPASS
(PCH 1.05V CORE PWR)
=PP1V05_S0_PCH_VCC_CORE
1
0.1UF
CRITICAL
R2491
1
0
5%
1/16W
MF-LF
402
2
L2491
10UH-0.12A-0.36OHM
1
2
PP1V05_S0_PCH_VCCADPLLB_R
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
PCH VCCADPLLB Filter
(PCH DPLLB PWR)
PP1V05_S0_PCH_VCCADPLLB_F
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
69 mA
20%
10V
CERM 2
402
C2493
1
C2494
21 8
L2406
10%
6.3V
2 CERM
402
C2416
4.7UF
MIN_LINE_WIDTH=0.5 MM
1098AS-SM
MIN_NECK_WIDTH=0.25 MM
(Z = 1.2MM, PLACE ON SHORT SIDE BEHIND PCH) VOLTAGE=1.05V
1
1
20%
6.3V 2
X5R
402
1
C2417
PP1V05_S0_PCH_VCCCLKDMI_F
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=1.05V
2
5%
1/16W
MF-LF
402
1
C2482
1UF
10%
6.3V
2 CERM
402
1
C2483
1UF
10%
6.3V
2 CERM
402
C2430
0.1UF
SYNC_MASTER=D2_CLEAN
DRAWING NUMBER
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
10%
6.3V
CERM 2
402
PLACE_NEAR=U1800.AT20:2.54mm
PCH VCCIO BYPASS
PLACE_NEAR=U1800.AB36:2.54mm
PCH VCC3_3 BYPASS
(PCH PCI 3.3V PWR)
5
4
051-9589
3
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
2
SIZE
D
REVISION
R
1
1UF
1
20%
6.3V
X5R 2
603
6
SYNC_DATE=03/19/2012
PAGE TITLE
=PP1V05_S0_PCH_VCC_DMI
10UF
7
10%
6.3V
2 CERM
402
PCH DECOUPLING
C2419
8
1UF
10%
16V
2 X7R-CERM
0402
21
21 8
C2411
1
0.1UF
10%
16V
2 X7R-CERM
0402
PLACE_NEAR=U1800.BJ8:2.54mm
PLACE_NEAR=U1800.BJ8:2.54mm
PLACE_NEAR=U1800.BJ8:2.54mm
R2415
0
C2481
1UF
20%
2.5V 2
TANT
B16
CRITICAL
10UH-0.58A-0.35OHM
1
2
PP1V05_S0_PCH_VCCCLKDMI_R
1
PLACE_NEAR=U1800.AG26:2.54mm
PLACE_NEAR=U1800.AD21:2.54mm
PLACE_NEAR=U1800.AG24:2.54mm
PLACE_NEAR=U1800.AJ27:2.54mm
=PP1V05_S0_PCH_V_PROC_IO
PLACE_NEAR=U1800.BF47:2.54MM
PLACE_NEAR=U1800.BF47:2.54MM
=PP1V05_S0_PCH
20%
6.3V
X5R 2
603
21
NO STUFF
1
220UF
17 8
10UF
VOLTAGE=1.05V
0603
CRITICAL
(Z = 1.2MM, PLACE ON SHORT SIDE BEHIND PCH)
A
C2460 1
PLACE_NEAR=U1800.AJ16:2.54mm
4.18.0
BRANCH
PAGE
24 OF 132
SHEET
23 OF 99
1
A
8
7
6
5
24 8
4
R2510
51
2
89 24 11
XDP_CPU_TDI
R2511
51
2
89 24 11
XDP_CPU_TMS
R2512
51
2
89 24 11
XDP_CPU_TCK
R2513
51
2
89 24 11
XDP_CPU_TRST_L
R2514
51
2
5%
M-ST-SM
5%
62
61
XDP
89 11
(R2560-R2563)
BI
IN
1
4
3
6
OBSFN_A0
OBSFN_A1
5
7
OBSDATA_A0
OBSDATA_A1
IN
89 11
IN
1
2
1
2
1/20W
MF
18
5%
1/20W
MF
1/20W
MF
201
1/20W
MF
201
89 11
IN
89 11
IN
22
89 10
IN
89 10
IN
89 10
IN
89 10
R2564
R2565
R2566
R2567
CPU_CFG & lt; 12 & gt;
CPU_CFG & lt; 13 & gt;
CPU_CFG & lt; 14 & gt;
CPU_CFG & lt; 15 & gt;
IN
89 10
IN
0
0
0
0
1
2
1
2
1
2
5%
1/20W
MF
201
5%
1/20W
MF
5%
1/20W
MF
201
5%
1/20W
MF
201
89 20 11
IN
CPU_PWRGD
OUT
PM_PWRBTN_L
OUT
CPU_CFG & lt; 0 & gt;
1K
1
R2500
PLACE_NEAR=U1000.C60:2.54mm
2
89
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
XDP
41 24 18
0
1
R2502
PLACE_NEAR=U4900.P17:2.54mm
2
XDP_CPU_CFG & lt; 0 & gt;
XDP_VR_READY
XDP
89 24 10
1K
1
R2501
PLACE_NEAR=U1000.B57:2.54mm
44 24
BI
44 24
IN
XDP
70 41 18
R2504
PM_PCH_SYS_PWROK
OUT
330
1
2
C
89 24 11
OUT
XDP_CPU_TCK
(R2520-R2537)
XDP SIGNALS
24
OUT
24
OUT
24
OUT
24
OUT
33
33
33
33
47
49
52
51
54
53
56
55
58
57
59
PCH SIGNALS
2
1
2
1
2
1
2
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L
XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L
XDP_DA2_PCH_GPIO41_USB_EXTC_OC_L
XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L
C2500
201
10%
16V
X7R-CERM
0402
IN
10 89
IN
10 89
XDP
R2515
0
1
2
PLACE_NEAR=R1841.1:2.54mm
ITPXDP_CLK100M_P
5%
1/20W
MF
PLACE_NEAR=U1000.G3:2.54mm
2
CPU_RESET_L
IN
5%
1/20W
MF
201
5%
1
1/20W
MF
33
33
33
33
33
1
OUT
R2524
R2525
R2526
R2527
R2528
1
2
OUT
XDP_FC1
R2529
33
1
2
OUT
24
IN
24
OUT
24
24
24
IN
24
IN
24
IN
24
IN
24
IN
24
IN
24
24
IN
IN
2
1
2
1
2
1
2
5%
1/20W
5%
1/20W
5%
1/20W
5%
1/20W
5%
1/20W
R2530
R2531
R2532
R2533
R2534
R2535
33
33
33
33
33
33
1
2
1
2
1/20W
MF
2
1
MF
1
2
1
2
1
2
201
XDP_FC1_PCH_GPIO0
5%
XDP_DC0_ISOLATE_CPU_MEM_L
XDP_DC1_MXM_GOOD
XDP_DC2_DP_AUXCH_ISOL
XDP_DC3_SATARDRVR_EN
XDP_DD0_DP_GPU_TBT_SEL
XDP_DD1_JTAG_ISP_TCK
XDP_DB0_PCH_GPIO43_USB_EXTB_OC_EHCI_L
MF
201
XDP_DB1_PCH_GPIO9_USB_EXTD_OC_EHCI_L
MF
201
XDP_DB2_PCH_GPIO10_AP_PWR_EN
MF
201
XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE
MF
201
XDP_FC0_PCH_GPIO15
1
64
63
C2501
IN
19 24
IN
19
24 19
OUT
IN
19
24 19
OUT
2
998-2516
2
Non-XDP Signals
10%
16V
X7R-CERM
0402
19 24
R2590
R2591
R2596
R2597
0
0
0
0
5%
1/20W
MF
5%
1/20W
MF
5%
1/20W
MF
201
XDP_DC0_PCH_GPIO28_ISOLATE_CPU_MEM_L
201
XDP_DC1_PCH_GPIO35_MXM_GOOD
201
XDP_DC2_PCH_GPIO21_DP_AUXCH_ISOL
201
XDP_DC3_PCH_GPIO19_SATARDRVR_EN
201
XDP_DD0_PCH_GPIO36_DP_GPU_TBT_SEL
201
XDP_DD1_PCH_GPIO37_JTAG_ISP_TCK
B
33
33
1
2
MF
1/20W
MF
5%
XDP_DD2_PCH_GPIO16_AUD_IPHS_SWITCH_EN_PCH
1/20W
MF
201
XDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCH
1/20W
2
1
MF
1/20W
5%
R2536
R2537
1/20W
5%
5%
XDP_DD2_AUD_IPHS_SWITCH_EN
XDP_DD3_ENET_LOW_PWR
5%
MF
201
IN
19
19 24
IN
19 24
IN
OUT
20 24
OUT
20
OUT
OUT
17 24
OUT
20
OUT
20 24
OUT
20 24
PCH Micro2-XDP
OUT
20 24
6
IN
ALL_SYS_PWRGD
OUT
PM_PWRBTN_L
R2584
1K
1
PLACE_NEAR=J2550.39:2.54mm
5%
1/20W
MF
201
XDP_DA0_USB_EXTA_OC_L
XDP_DA1_USB_EXTB_OC_L
OBSDATA_A0
OBSDATA_A1
12
11
16
15
18
17
22
21
24
23
27
30
29
A
1/20W
MF
33
36
35
44 24
44 24
24 17
BI
IN
OUT
39
XDP_DB2_AP_PWR_EN
XDP_DB3_SDCONN_STATE_CHANGE
OBSDATA_B2
OBSDATA_B3
PWRGD/HOOK0
HOOK1
VCC_OBS_AB
HOOK2
HOOK3
=SMBUS_XDP_SDA
=SMBUS_XDP_SCL
XDP_PCH_TCK
42
MF
R2574
1K
IN
201
SATARDRVR_EN
2
1
OUT
201
1/20W
IN
MF
MF
19 34 70
201
17
OUT
201
1/20W
7 38
25
OUT
ISOLATE_CPU_MEM_L
1/20W
40
27
DP_AUXCH_ISOL
5%
1/20W
MF
OUT
TBT_CIO_PLUG_EVENT_ISOL
2
IN
20
OUT
20
201
17 25
8
OUT
OUT
OUT
XDP_DD1_PCH_GPIO37_JTAG_ISP_TCK
XDP_DD2_PCH_GPIO16_AUD_IPHS_SWITCH_EN_PCH
XDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCH
R2575
R2576
R2577
0
0
0
1
2
1
2
1
2
5%
1/20W
5%
1/20W
5%
1/20W
JTAG_ISP_TCK
MF
201
AUD_IPHS_SWITCH_EN_PCH
MF
201
ENET_LOW_PWR_PCH
MF
OUT
20 25
OUT
201
9 20 25
OBSDATA_D2
OBSDATA_D3
6
5
24
24
24
R2550
2
PLACE_NEAR=J2550.52:2.54mm
1
5%
XDP
24
XDP_PCH_TDI
R2551
51
2
24
24 17
XDP_PCH_TMS
R2552
51
MF
201
1
XDP
24
1/20W
PLACE_NEAR=U1800.K5:2.54mm
2
1/20W
MF
201
PLACE_NEAR=U1800.H7:2.54mm
1
5%
59
XDP
1/20W
MF
201
PLACE_NEAR=U1800.J3:2.54mm
1
5%
1/20W
MF
201
SYNC_DATE=01/13/2012
CPU & PCH XDP
1
63
998-2516
2
TP_XDP_PCH_HOOK4
ITPCLK/HOOK4
51
2
XDP_PCH_TCK
R2556
24 17
ITPCLK#/HOOK5 TP_XDP_PCH_HOOK5
VCC_OBS_CD
XDPPCH_PLTRST_L
RESET#/HOOK6
1K series R on PCH Support Page
IN 25
XDP_DBRESET_L
DBR#/HOOK7
OUT 11 24 25 89
NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page
XDP_PCH_TDO
TDO
IN 17 24
SYNC_MASTER=D2_KEPLER
TP_XDP_PCH_TRST_L
TRSTn
PAGE TITLE
XDP_PCH_TDI
TDI
OUT 17 24
XDP_PCH_TMS
TMS
OUT 17 24
XDP_PRESENT#
57
64
51
5%
55
1
=PP1V05_SUS_PCH_JTAG
XDP
XDP_PCH_TDO
24
Apple Inc.
XDP
0.1UF
10%
16V
X7R-CERM
0402
XDP_DD2_AUD_IPHS_SWITCH_EN
XDP_DD3_ENET_LOW_PWR
24
24 17
53
56
XDP_DD0_DP_GPU_TBT_SEL
XDP_DD1_JTAG_ISP_TCK
24
24 17
51
58
NC
OBSDATA_D0
OBSDATA_D1
49
54
TP_XDP_PCH_OBSFN_D & lt; 0 & gt;
TP_XDP_PCH_OBSFN_D & lt; 1 & gt;
24
8
47
52
XDP_DC2_DP_AUXCH_ISOL
XDP_DC3_SATARDRVR_EN
OBSFN_D0
OBSFN_D1
45
48
XDP_DC0_ISOLATE_CPU_MEM_L
XDP_DC1_MXM_GOOD
OBSDATA_C2
OBSDATA_C3
43
46
XDP_FC0
XDP_FC1
OBSDATA_C0
OBSDATA_C1
41
44
SDA
SCL
TCK1
TCK0
C2580
7
1
MF
5%
OBSFN_C0
OBSFN_C1
XDP
8
0
1/20W
37
40
OBSDATA_B0
OBSDATA_B1
TP_XDPPCH_HOOK2
TP_XDPPCH_HOOK3
201
XDP_FC1_PCH_GPIO0
MF
5%
31
34
OBSFN_B0
OBSFN_B1
XDP_DB0_USB_EXTB_OC_EHCI_L
XDP_DB1_USB_EXTD_OC_EHCI_L
2
5%
OUT
1/20W
5%
R2573
25
28
OBSDATA_A2
OBSDATA_A3
60
0
1
PLACE_NEAR=U4900.P17:2.54mm
2
201
5%
IN
201
MF
19
XDP_DA2_USB_EXTC_OC_L
XDP_DA3_USB_EXTD_OC_L
50
R2585
1
MF
1/20W
13
XDP
41 24 18
0
2
1/20W
5%
B
9
XDP_PCH_S5_PWRGD
XDP_PCH_PWRBTN_L
2
R2572
1
5%
7
XDP
70 41
XDP_DC2_PCH_GPIO21_DP_AUXCH_ISOL
24 20
5
10
38
24
IN
24 20
3
32
24
2
2
1
4
26
24
1
24 20
OBSFN_A0
OBSFN_A1
TP_XDP_PCH_OBSFN_B & lt; 0 & gt;
TP_XDP_PCH_OBSFN_B & lt; 1 & gt;
24
0
=PP3V3_S5_XDP
61
20
R252x, R253x, R257x and R259x should be placed where signal path
needs to split between route from PCH to J2550
and path to non-XDP signal destination.
R2570
M-ST-SM
62
14
24
XDP_DC0_PCH_GPIO28_ISOLATE_CPU_MEM_L
2
1
5%
J2550
8
24
OUT
USB_EXTA_OC_L
USB_EXTB_OC_L
AP_PWR_EN
201
SDCONN_STATE_CHANGE
2
1
CRITICAL
XDP_CONN
2
24
24 20
1
17 24
TP_XDP_PCH_OBSFN_A & lt; 0 & gt;
TP_XDP_PCH_OBSFN_A & lt; 1 & gt;
24
XDP_DC3_PCH_GPIO19_SATARDRVR_EN
24 20
PCH/XDP Signal Isolation Notes:
- Following Intel’s Debug Prot Design Guid for HR and CR v1.3
doc id 404081.
Initially, stuffing both 33 and 0 ohms and validate whether
it is functional in that state, else add BOM options.
- For isolated GPIOs:
- ’Output’ non-XDP signals require pulls.
- ’Output’ PCH/XDP signals require pulls.
IN
24 17
20 24
DF40RC-60DP-0.4V
201
OUT
XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L
XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L
XDP_DB2_PCH_GPIO10_AP_PWR_EN
XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE
20
IN
NOTE: This is not the standard XDP pinout.
Use with 921-0133 Adapter Flex to
support chipset debug.
IN
24 19
19
OUT
11 25
C
PCH SIGNALS
0.1UF
IN
IN
201
201
17 89
XDP
24 17
24
XDP_DB0_USB_EXTB_OC_EHCI_L
XDP_DB1_USB_EXTD_OC_EHCI_L
XDP_DB2_AP_PWR_EN
XDP_DB3_SDCONN_STATE_CHANGE
XDP_FC0
OUT
IN
PLACE_NEAR=R1840.1:2.54mm
2
ITPXDP_CLK100M_N
1
MF
17 89
XDP
24 19
24
IN
201
1/20W
XDP
1
0.1UF
1
10 89
CPU_CFG & lt; 6 & gt;
CPU_CFG & lt; 7 & gt;
5%
ITPCLK/HOOK4 89 XDP_CPU_CLK100M_P
0
R2516
ITPCLK#/HOOK5 89 XDP_CPU_CLK100M_N
VCC_OBS_CD
XDP_CPURST_L
RESET#/HOOK6
1K
XDP_DBRESET_L
R2505
DBR#/HOOK7
OUT 11 24 25 89
NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page
XDP_CPU_TDO
TDO
IN 11 24 89
XDP_CPU_TRST_L
TRSTn
OUT 11 24 89
XDP_CPU_TDI
TDI
OUT 11 24 89
XDP_CPU_TMS
TMS
OUT 11 24 89
XDP_PRESENT#
XDP
XDP
R2520
R2521
R2522
R2523
XDP_DA0_USB_EXTA_OC_L
XDP_DA1_USB_EXTB_OC_L
XDP_DA2_USB_EXTC_OC_L
XDP_DA3_USB_EXTD_OC_L
45
48
NC
43
46
SDA
SCL
TCK1
TCK0
=SMBUS_XDP_SDA
=SMBUS_XDP_SCL
41
44
2
39
42
PWRGD/HOOK0
HOOK1
VCC_OBS_AB
HOOK2
HOOK3
XDP_CPU_PWRGD
XDP_CPU_PWRBTN_L
10 89
IN
37
40
XDP
35
IN
OBSDATA_D2
OBSDATA_D3
33
CPU_CFG & lt; 4 & gt;
CPU_CFG & lt; 5 & gt;
31
36
OBSDATA_B2
OBSDATA_B3
XDP_OBSDATA_B & lt; 2 & gt;
XDP_OBSDATA_B & lt; 3 & gt;
29
10 89
OBSDATA_D0
OBSDATA_D1
27
34
201
D
201
10 89
IN
MF
25
30
OBSDATA_B0
OBSDATA_B1
XDP_OBSDATA_B & lt; 0 & gt;
XDP_OBSDATA_B & lt; 1 & gt;
2
1
IN
1/20W
PLACE_NEAR=U1000.H63:2.54mm
1
10 89
CPU_CFG & lt; 8 & gt;
CPU_CFG & lt; 9 & gt;
201
10 89
IN
OBSFN_D0
OBSFN_D1
23
28
XDP_CPU:CFG
IN
MF
10 89
OBSDATA_C2
OBSDATA_C3
21
24
OBSFN_B0
OBSFN_B1
CPU_CFG & lt; 10 & gt;
CPU_CFG & lt; 11 & gt;
IN
89 10
(R2564-R2567)
OBSDATA_A2
OBSDATA_A3
IN
XDP
10 24 89
CPU_CFG & lt; 2 & gt;
CPU_CFG & lt; 3 & gt;
1/20W
PLACE_NEAR=U1000.J58:2.54mm
5%
IN
201
1
10 89
CPU_CFG & lt; 0 & gt;
CPU_CFG & lt; 1 & gt;
MF
19
32
201
5%
XDP_BPM_L & lt; 2 & gt;
XDP_BPM_L & lt; 3 & gt;
17
20
201
15
26
5%
IN
1/20W
13
50
2
11
16
2
1
IN
12
38
1
5%
IN
89 11
0
0
0
0
IN
10 89
OBSDATA_C0
OBSDATA_C1
9
60
89 11
R2560
R2561
R2562
R2563
XDP_BPM_L & lt; 4 & gt;
XDP_BPM_L & lt; 5 & gt;
XDP_BPM_L & lt; 6 & gt;
XDP_BPM_L & lt; 7 & gt;
IN
IN
89 11
XDP_CPU:BPM
89 11
XDP_BPM_L & lt; 0 & gt;
XDP_BPM_L & lt; 1 & gt;
10
14
89 11
CPU_CFG & lt; 16 & gt;
CPU_CFG & lt; 17 & gt;
201
PLACE_NEAR=U1000.H59:2.54mm
XDP
OBSFN_C0
OBSFN_C1
MF
1
5%
2
2
XDP_CPU_PREQ_L
XDP_CPU_PRDY_L
1/20W
PLACE_NEAR=U1000.K61:2.54mm
1
1
8
D
PLACE_NEAR=J2500.52:2.54mm
1
XDP
1K
89 11
=PPVCCIO_S0_XDP
XDP
XDP_CPU_TDO
89 24 11
DF40RC-60DP-0.4V
NO STUFF
5%
1/16W
MF-LF
402
1
24 8
NOTE: This is not the standard XDP pinout.
Use with 921-0133 Adapter Flex to
support chipset debug.
J2500
=PP3V3_S0_XDP
R2540
2
CPU Micro2-XDP
=PPVCCIO_S0_XDP
CRITICAL
XDP_CONN
8
3
C2581
DRAWING NUMBER
051-9589
R
10%
16V
X7R-CERM
0402
4
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
3
2
D
4.18.0
0.1UF
2
SIZE
REVISION
BRANCH
PAGE
25 OF 132
SHEET
24 OF 99
1
A
8
7
6
5
GPIO Glitch Prevention
25 19 8
1
IN
IN
20
IN
08
ENET_LOW_PWR_PCH
PM_PCH_PWROK
FW_PWR_EN_PCH
1
2
5
6
D
A1
B1
A2
B2
Unbuffered
0.1UF
74LVC2G08GT
24 20 9
70 25 18
C2650
Y1
Y2
1
R2695
27 19
4.7K
7
FW_PWR_EN
9
OUT
R2696
9
OUT
89 24 11
XDP_DBRESET_L
IN
0
1
PM_SYSRST_L
OMIT
2
5%
1/16W
MF-LF
402
GND
IN
1
LPC_RESET_L
LPCPLUS_RESET_L
R2697
1
0
0
20%
10V
2 CERM
402
IN
IN
24 20
IN
70 25 18
IN
08
TBT_PWR_EN_PCH
LPC_PWRDWN_L
AUD_IPHS_SWITCH_EN_PCH
PM_PCH_PWROK
2
5
6
74LVC2G08GT
17
43 41 18 7
A1
B1
A2
B2
SDCONN_STATE_CHANGE ISOLATION
0.1UF
U2652
SOT833
1
1
C2652
Y1
=PP3V3_S3_SDBUF
TBT_PWR_EN
3
AUD_IPHS_SWITCH_EN
OUT
20 35
OUT
OUT
SDCONN_STATE_CHANGE
0.1UF
58
CRITICAL
Y2
10%
6.3V
X5R
201
2
TC7SZ08AFEAPE
SOT665
470K
Y
25 8
5
SDCONN_STATE_CHANGE_RIO
IN
7 38
2
3
R2640
Q2640
PLACE_NEAR=U1800.N52
92 19
IN
LPC_CLK33M_SMC_R
1
22
LPC_CLK33M_SMC
2
5%
1/20W
MF
201
19
IN
LPC_CLK33M_LPCPLUS_R
PLACE_NEAR=U1800.P46
1
19
IN
IN
22
G 2
S
1
6
=PP3V3_S0_PCH_GPIO
10K
OUT
DP_AUXIO_EN
24 17
OUT
34
BKLT_PLT_RST_L
OUT
86
CPU_RESET_L
OUT
11 24
R2693
1
0
2
D 3
C2639
10%
16V
X5R-CERM
0201
S 2
1
C2690 1
1
0.1UF
0.1UF
G
PLT_RST_CPU_BUF_L
MAKE_BASE=TRUE
84 85
20%
10V
CERM 2
402
2
R2690
3
100K
5%
1/16W
MF-LF
2 402
NC
DP_AUXCH_ISOL
IN
1 NO STUFF
22
R2631
10K
PCH_CLK33M_PCIIN
2
OUT
5%
1/20W
MF
17 92
2 201
8
8
NOTE: VDD_25M must be powered if any VDDIO_25M_x is powered.
=PP3V3_S0_SYSCLK
PCH ME Disable Strap
B
PCH uses HDA_SDO as a power-up strap. If low, ME functions normally.
If high, ME is disabled. This allows for full re-flashing of SPI ROM.
SMC controls strap enable to allow in-field control of strap setting.
Q2620 & 5V pull-up allows circuit to work regardless of HDA voltage.
=PPVBAT_G3_SYSCLK
Coin-Cell:
VBAT (300-ohm & 10uF RC)
No Coin-Cell: 3.42V G3Hot (no RC)
=PP3V3_S5_SYSCLK
Coin-Cell & G3Hot:
3.42V G3Hot
Coin-Cell & No G3Hot: 3.3V S5
No Coin-Cell:
3.3V S5
No bypass necessary
23 8
=PP5V_S0_PCH
1
R2620
100K
5%
1/20W
MF
2 201
Q2620
R2607
SOT563
SYSCLK_25M_B_GND
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=0V
NO STUFF
C2624 1
C2622 1
0.1UF
0.1UF
20%
10V
CERM 2
402
SYSCLK_CLK25M_X2
CRITICAL
3
4 2
1
1
C2606
NC Y2605
NC SM-3.2X2.5MM
1
0
2
5%
1/16W
MF-LF
402
25.000MHZ-12PF-20PPM
12PF
1
8
SLG3NB148A
TQFN
CRITICAL
SYSCLK_CLK25M_X2_R
NO STUFF
1
R2606
1M
3
4
VDDIO_25M_A
32KHZ_A
CKPLUS_WAIVE=PwrTerm2Gnd
VDDIO_25M_B
VDDIO_25M_C
25MHZ_A
25MHZ_B
X2
25MHZ_C
X1
VDD_RTC_OUT
GND
5%
1/16W
MF-LF
2 402
D
3
SYSCLK_CLK32K_RTC
9
8
15
SYSCLK_CLK25M_SB
TP_SYSCLK_CLK25M_ENET
SYSCLK_CLK25M_TBT
=PPVRTC_G3_OUT 8
For SB RTC Power
1
THRM
PAD
1
1
Q2620
6
2
42 41
1K
5%
1/20W
MF
2 201
OUT
17 91
OUT
17 91
OUT
IN
G
HDA_SDOUT_R
IPD = 9-50k
S 1
17 92
OUT
SPI_DESCRIPTOR_OVERRIDE_L
35 91
SYNC_MASTER=D2_KEPLER
SYNC_DATE=01/13/2012
PAGE TITLE
Chipset Support
DRAWING NUMBER
Apple Inc.
051-9589
1UF
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
4
3
2
SIZE
D
REVISION
R
C2610
10%
6.3V
2 CERM
402
5
R2621
D 6
SOT563
NOTE: 30 PPM crystal required
7
SPI_DESCRIPTOR_OVERRIDE
SSM6N37FEAPE
+V3.3A should be first
available ~3.3V power
to reduce VBAT draw.
12
SPI_DESCRIPTOR_OVERRIDE_LS5V
=PP3V3R1V5_S0_PCH_VCCSUSHDA
VBAT and +V3.3A are
internally ORed to
create VDD_RTC_OUT.
SYSCLK_CLK25M_X1
2
5%
50V
C0G-CERM
0402
10%
10V 2
X5R
402-1
R2605
12PF
5%
50V
C0G-CERM
0402
U2600
1UF
5%
1/16W
MF-LF
2 402
20%
10V
CERM 2
402
1
11
6
14
C2605
2
0
C2602
7
10
16
A
R2608
C2620 1
0.1UF
1
+3.42V 13
5%
1/16W
MF-LF
402
23 21 8
17
2
+V3.3A 2
Ethernet XTAL Power (Unused on 15 " MBP)
=PPVDDIO_S0_SBCLK
SB XTAL Power
8
=PPVDDIO_TBT_CLK
TBT XTAL Power
8
0
VDD_25M 5
1
G 5
SSM6N37FEAPE
4 S
NO STUFF
20%
10V
CERM 2
402
C
VTT pullup on CPU page
1
SOD-VESM-HF
82
OUT
NC
Q2630
7 43 92
R2659
VDDIO_25M_A: SB power rail for XTAL circuit.
VDDIO_25M_B: Ethernet power rail for XTAL circuit.
VDDIO_25M_C: Thunderbolt power rail for XTAL circuit.
8
AP_RESET_L
2
U2690
SC70
4
2
System RTC Power Source & 32kHz / 25MHz Clock Generator
GreenClk 25MHz Power
0
74LVC1G07
2
5%
1/20W
MF
201
41 92
5%
1/20W
MF
201
B
1
1
LPC_CLK33M_DPMUX_UC
PLACE_NEAR=U1800.P48 1
PCH_CLK33M_PCIOUT
OUT
37
CRITICAL
5
SSM3K15FV
2
5%
1/20W
MF
201
TP_PCI_CLK33M_OUT2
LPC_CLK33M_LPCPLUS
2
OUT
=TBT_RESET_L
Buffered CPU reset
=PP3V3_S0_RSTBUF
R2630
5%
1/20W
MF
201
R2657
MAKE_BASE=TRUE
19
22
38
5%
1/16W
MF-LF
402
R2656
PLACE_NEAR=U1800.P53 1
LPC_CLK33M_DPMUX_UC_R
OUT
OUT
7
Series R on Pg38, R3803
R2688
1
DP_AUXIO_EN INVERSION
37 20 19 18 17 8
39
MAKE_BASE=TRUE
5%
1/16W
MF-LF
402
25 8
LPC 33MHz Clock R2655
Series Termination
OUT
=ENET_RESET_L
ENET_RESET_L
2
S
SDCONN_STATE_CHANGE_SMC
SDCONN_STATE_CHANGE_INV
5%
1/16W
MF-LF
2 402
20%
10V
CERM 2
402
2
5%
1/16W
MF-LF
402
100K
0.1UF
0
4
OUT
3
42
D
SOT563
SOT563
G 5
SSM6N15FEAPE
1
R2680
3
C2680 1
SSM6N15FEAPE
5%
1/20W
MF
201 2
Q2640
C
PLT_RST_BUF_L
MAKE_BASE=TRUE
0
5%
1/16W
MF-LF
402
R2686
SC70-HF
1
1
470K
82
R2685
MC74VHC1G08
U2680 4
=PP3V3_S4_SMC
D
42 25 8
OUT
SSD_RESET_L
2
2
CRITICAL
1
1
1K
5%
1/16W
MF-LF
402
1
U2630
B
24
R2689
Buffered
=PP3V3_S0_RSTBUF
5%
1/20W
MF
201 2
A
4
OUT
D
5%
1/16W
MF-LF
402
8 25 42
R2641
2
4
33
XDP
1
5
GND
=PP3V3_S4_SMC
OUT
DPMUX_LRESET_L
2
0
41
XDPPCH_PLTRST_L
2
C2630
1
24
7
8
33
5%
1/16W
MF-LF
402
R2687
1
CRITICAL 8
VCC
OUT
PCA9557D_RESET_L
1
1
=PP3V3_S3_PCH_GPIO
7 43
R2683
SILK_PART=SYS RESET
25 19 8
92
OUT
MAKE_BASE=TRUE
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
2 402
OUT
SMC_LRESET_L
2
R2671
1
4
33
5%
1/16W
MF-LF
402
18 41
OUT
1
R2681
PLT_RESET_L
MAKE_BASE=TRUE
5%
1/16W
MF-LF
2 402
XDP
ENET_LOW_PWR
3
2
Platform Reset Connections
=PP3V3_S0_SB_PM
70 8
20%
10V
2 CERM
402
U2650
SOT833
3
PCH Reset Button
=PP3V3_S3_PCH_GPIO
CRITICAL 8
VCC
4
4.18.0
BRANCH
PAGE
26 OF 132
SHEET
25 OF 99
1
A
8
7
6
5
4
3
2
1
TABLE_BOMGROUP_HEAD
BOM GROUP
BOM OPTIONS
HUB_ALLREM
HUB_NONREM1_0,HUB_NONREM0_0
HUB_1NONREM
HUB_NONREM1_0,HUB_NONREM0_1
HUB_2NONREM
HUB_NONREM1_1,HUB_NONREM0_0
HUB_3NONREM
HUB_NONREM1_1,HUB_NONREM0_1
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
USB MUX FOR LS/FS INTERNAL DEVICES
D
26 8
C2700
C2701
1
4.7UF
20%
6.3V
X5R
603
NON_REM 1 : NON_REM 0
STRAP PIN CFG
0
:
0
ALL PORTS ARE REMOVABLE
0
:
1
PORT 1 IS NON REMOVABLE
1
:
0
PORT 1 & 2 ARE NON REMOVABLE
1
:
1
PORT 1 & 2 & 3 ARE NON REMOVABLE
CANNOT INDICATE ALL 4 PORTS ARE NON REMOVABLE ON USB2514B VIA STARPPING, PROGRAM NON_REMOVABLE DEVICE REGISTER 09H
BYPASS=U2700.36::2MM
BYPASS=U27000.5::5MM
=PP3V3_S3_USB_HUB
TABLE_BOMGROUP_ITEM
1
2
C2702
1
2
0.1UF
10%
16V
X7R-CERM
0402
2
1
0.1UF
C2703
D
0.1UF
10%
16V
X7R-CERM
0402
2
10%
16V
X7R-CERM
0402
BOM TABLE
TABLE_5_HEAD
PART#
BYPASS=U2700.10::2MM
BYPASS=U2700.29::2MM
BYPASS=U2700.23::5MM
BYPASS=U2700.15::2MM
QTY
DESCRIPTION
1
REFERENCE DESIGNATOR(S)
USB HUB 2514B
CRITICAL
BOM OPTION
CRITICAL
USBHUB2514B
CRITICAL
USBHUB2513B
CRITICAL
USBHUB2512B
TABLE_5_ITEM
338S0824
U2700
TABLE_5_ITEM
338S0923
1
U2700
USB HUB 2513B
TABLE_5_ITEM
0.1UF
VOLTAGE=1.8V
SM-2
VDD33
24.000MHZ-16PF
1
2
1
18PF
HUB_NONREM1_1
C
R2702
1
HUB_NONREM0_1
1
10K
5%
1/16W
MF-LF
402
5%
50V
C0G-CERM
0402
2
CRITICAL
1
1M
2
2
R2703
5%
1/16W
MF-LF
402
R2701
5%
50V
C0G-CERM
0402
11
USB_HUB_TEST
2
TEST
OMIT
5%
1/16W
MF-LF
402
26
26
USB_HUB_RESET_L
33
USB_HUB_XTAL1
USB_HUB_XTAL2
CRITICAL
32
RESET*
5%
1/16W
MF-LF
402
1
2
14
34
0.1UF
2
10%
16V
X7R-CERM
0402
2
C2712
1UF
10%
16V
X7R-CERM
0402
2
2
10%
16V
X5R
402
=PP3V3_S3_USB_HUB
1
5%
1/16W
MF-LF
402
1
R2706
22
2
5%
1/16W
MF-LF
402
25
6
NC
NC
8
SCL/SMBCLK/CFG_SEL0
HS_IND/CFG_SEL1
SUSP_IND/LOCAL_PWR/NON_REM0
BI
9
BI
9
BLUETOOTH FOR 15 " MBP & MBP OG
9 26
R2707
12
OCS1*
OCS2*
OSC3*
NC
13
5%
1/16W
MF-LF
402
IPU
IPU
IPU
IPU
16
18
20
17
19
21
BI
9 26
BI
1
R2717
R2718
1
R2719
NOSTUFF
1
R2722
10K
10K
10K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
R2723
10K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
2
2
2
2
8 26
NOSTUFF
1
10K
5%
1/16W
MF-LF
C
2 402
BI
9 26
BI
USBHUB_DN3_N
USBHUB_DN3_P
9 26
26 9
SMC DEBUG PORT FOR 15 " MBP, IR for MBP OG
35
27
=PP3V3_S3_USB_HUB
7
30
USB_HUB_UP_N
USB_HUB_UP_P
8 26
USBHUB_DN2_P
7
1
7
R2708
10K
7
7
5%
1/16W
MF-LF
402
USB_HUB_VBUS_DET
USBDM_UP
USBDP_UP
USBHUB_DN2_N
26 9
7
TP_USB_HUB_OCS1
NC_USB_HUB_OCS2
NC_USB_HUB_OCS3
NC_USB_HUB_OCS4
RBIAS
USBHUB_DN4_N
USBHUB_DN4_P
26 9
TP_USB_HUB_PRTPWR1
NC_USB_HUB_PRTPWR2
NC_USB_HUB_PRTPWR3
NC_USB_HUB_PRTPWR4
VBUS_DET
26 9
26 9
NC FOR 15 " MBP, SMC DEBUG PORT FOR MBP OG
2
15 " MBP USES 197S0181 FOR Y2700 DUE TO HEIGHT LIMITATION
MBP OG USES 197S0284 FOR Y2700 TO SAVE COST
1
NOSTUFF
9 26
USBHUB_DN4_N
USBHUB_DN4_P
9
NOSTUFF
TRACKPAD/KEYBOARD FOR 15 " MBP & MBP OG
9 26
USBHUB_DN3_N
USBHUB_DN3_P
7
PRTPWR1/BC_EN1*
PRTPWR2/BC_EN2*
PRTPWR3/BC_EN3*
NC
10K
2
USBHUB_DN2_N
USBHUB_DN2_P
4
USBDM_DN3/PRT_DIS_M3
USBDP_DN3/PRT_DIS_P3
SDA/SMBDATA/NON_REM1
24
10K
3
R2716
NOSTUFF
10K
USBHUB_DN1_N
USBHUB_DN1_P
2
26 9
28
1
1
USBDM_DN1/PRT_DIS_M1
USBDP_DN1/PRT_DIS_P1
USBDM_DN2/PRT_DIS_M2
USBDP_DN2/PRT_DIS_P2
XTALIN/CLKIN
XTALOUT
USB_HUB_CFG_SEL1
R2705
USB_HUB_RBIAS
CRITICAL
CKPLUS_WAIVE=NdifPr_badTerm
31
THRM_PAD
BI
19 91
BI
1
19 91
R2709
TO CONNECT TP/KB TO PCH XHCI
NOSTUFF R5701 & R5702, STUFF R2720 & R2721
12K
PCH PORT 7 (EHCI1)
=PP3V3_S3_USB_RESET
2
37
8
10%
16V
X5R
402
1UF
NOSTUFF
10K
2
1
2
USB_HUB_CFG_SEL0
HUB_NONREM0_0
10K
C2711
QFN
100
1
USB_HUB_NONREM1
R2704 1
1
C2714
U2700
USB_HUB_NONREM0
HUB_NONREM1_0
1
U2700
USB HUB 2512B
USB2513B
18PF
R2700
1
SYM VER 1
C2710
5%
1/16W
MF-LF
402
10K
2
2
4
NC
NC
CRITICAL
C2709
3
VOLTAGE=1.8V
C2713
0.1UF
MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM
PLLFILT
BYPASS=U2700.5::2MM
BYPASS=U2650.23::2MM
Y2700
1
PPUSB_HUB2_VDD1V8PLL
1
15 " MBP ENGINEERING: USE USB2513B PRODUCTION: USE USB2512B
MBP OG ENGINEERING: USE USB2514B PRODUCTION: USE USB2513B
MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM
2
36
10%
16V
X7R-CERM
0402
2
5
CRITICAL
0.1UF
10%
16V
X7R-CERM
0402
2
PPUSB_HUB2_VDD1V8
CRFILT
0.1UF
10%
16V
X7R-CERM
0402
2
338S0983
1
29
20%
6.3V
X5R
603
C2708
1
23
4.7UF
C2706
1
15
C2705
1
10
C2704
1%
1/16W
MF
402
NOSTUFF
R2720
91 19
B
BI
USB_EXTD_XHCI_N
1
NOSTUFF
TO PCH XHCI
1
R2712
10K
91 19
5%
1/16W
MF-LF
R2721
BI
USB_EXTD_XHCI_P
C2715
27
2
USB_TPAD_R_N
BI
49 96
B
TO TP/KB
2
USB_TPAD_R_P
BI
49 96
5%
1/16W
MF-LF
402
2 402
USB_HUB_RESET_L
1
27
5%
1/16W
MF-LF
402
26
1
0.1UF
2
BYPASS=U2700.26::2MM
USB XHCI/EHCI2 PORT MUX FOR EXT B
8
=PP3V3_S3_USBMUX
C2760
1
9
10%
16V
X7R-CERM
0402
0.1UF
19
91
91 19
PCH PORT 9 (EHCI2)
BI
BI
A
USB_EXTB_EHCI_P
USB_EXTB_EHCI_N
20%
10V
CERM
402
VCC
2
5 M+
4 M-
Y+ 1
Y- 2
U2760
USB_EXTB_P
USB_EXTB_N
BI
7 38 91
BI
7 38 91
TO CONNECTOR
PI3USB102ZLE
19
91
BI
91 19
PCH PORT 1 (XHCI)
BI
USB_EXTB_XHCI_P
USB_EXTB_XHCI_N
7 D+
6 D-
SYNC_MASTER=D2_KEPLER
TQFN
CRITICAL
USB HUB & MUX
PULL-UP TO 3.3V SUS ON PCH PAGE, SEL PIN IS LEAKAGE-SAFE
8
SEL 10
OE*
3
GND
SYNC_DATE=01/13/2012
PAGE TITLE
USB_EXTB_SEL_XHCI
IN
SEL=0 CHOOSE USB EHCI2 PORT
SEL=1 CHOOSE USB XHCI PORT
17
DRAWING NUMBER
PCH GPIO60
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
051-9589
3
2
SIZE
D
REVISION
4.18.0
BRANCH
PAGE
27 OF 132
SHEET
26 OF 99
1
A
8
7
6
5
4
3
PART NUMBER
QTY
2
DESCRIPTION
REFERENCE DES
1
CRITICAL
BOM OPTION
114S0365
RES,MTL FILM,1/16W,33.2K,1,0402,SMD,LF
R2821
PPDDR:1V5
114S0376
The circuit below handles CPU and VTT power during S0- & gt; S3- & gt; S0 transitions, as well
as isolating the CPU’s SM_DRAMRST# output from the SO-DIMMs when necessary.
1
1
RES,MTL FILM,1/16W,43.2K,1,0402,SMD,LF
R2821
PPDDR:1V35
ISOLATE_CPU_MEM_L GPIO state during S3 & lt; - & gt; S0 transitions determines behavior of signals.
WHEN HIGH: CPU 1.5V remains powered in S3, VTT follows S0 rails, MEM_RESET_L not isolated.
WHEN LOW: CPU 1.5V follows S0 rails, VTT ensures clean CKE transition, MEM_RESET_L isolated.
D
D
1V5 S0 " PGOOD " for CPU
P1V5CPU_EN = (ISOLATE_CPU_MEM_L + PM_SLP_S3_L) * PM_SLP_S4_L
MEMVTT_EN
= (ISOLATE_CPU_MEM_L + PLT_RST_L)
* PM_SLP_S3_L
MEM_RESET_L = !ISOLATE_CPU_MEM_L + CPU_MEM_RESET_L
70 41 40 38 34 18 7
8
=PP3V3_S5_CPU_VCCDDR
PM_SLP_S4_L
IN
PM_MEM_PWRGD pull-up to CPU VTT rail is on CPU page
CPUMEM_S0
1
R2805
16 14 11 8
=PP1V5_S3_CPU_VCCDDR
PM_MEM_PWRGD
10K
8
CPUMEM_S0
R28011
D 6
2 G
S
DMB53D0UV
OMIT_TABLE
CRITICAL
CPUMEM_S0
3 D
1
4 S
C2820 1
33.2K
4700PF
1%
1/16W
MF-LF
402 2
SOT563
ISOLATE_CPU_MEM_L
4
R28211
Q2805
SSM6N15FEAPE
S 4
CRITICAL
Q2820
5
P1V5_S0_DIV
SOT-563
SOT563
5 G
Q2820
SOT-563
S 1
SSM6N15FEAPE
IN
6
D
PM_MEM_PWRGD_L
3
2 G
D 3
Q2800
CRITICAL
DMB53D0UV
1%
1/16W
MF-LF
402 2
P1V5CPU_EN_L
CRITICAL
CPUMEM_S0
5%
1/16W
MF-LF
2 402
R28201
69
SOT563
5%
1/16W
MF-LF
402 2
24
OUT
SSM6N15FEAPE
100K
C
10K
27.4K
Q2805
11 18 89
R2822
P1V5CPU_EN
CRITICAL
CPUMEM_S0
=PP3V3_S3_MEMRESET
OUT
1
5%
1/16W
MF-LF
2 402
10%
100V
CERM 2
402
C
G 5
PM_SLP_S3_L
CPUMEM_S0
IN
7 18 38 41 70
1
R2810
10K
5%
1/16W
MF-LF
2 402
27 8
=PP5V_S3_MEMRESET
MEMVTT_EN
CRITICAL
CPUMEM_S0
CPUMEM_S0
Q2810
CPUMEM_S0
1
R2802
100K
100K
5%
1/16W
MF-LF
402 2
D 6
Q2800
Q2815
3 D
R28501
10
5%
1/10W
MF-LF
603 2
Q2810
SOT563
G 2
SOT563
1 S
4 S
27 8
PLT_RESET_L
IN
19 25
=PP5V_S3_MEMRESET
CPUMEM_S0
CPUMEM_S0
R28511
G 5
SSM6N15FEAPE
CRITICAL
CPUMEM_S0
10%
6.3V
X5R 2
201
=PP1V5_S3_MEMRESET 8
CPUMEM_S0
CPUMEM_S0
1
Q2815
SOT563
=MEM_RESET_L
CPU_MEM_RESET_L
MAKE_BASE=TRUE
R2816
1
1K
CPUMEM_S0
C2816
Q2850
D 3
SSM6N15FEAPE
10%
2 16V
X7R-CERM
0402
OUT
5 G
64 9
IN
2 G
S 1
NO STUFF
C2851 1
20%
50V
CERM 2
402
28 29 30 31
CPUMEM_S3
B
0.001UF
SOT563
MEM_RESET_L
D 6
SOT563
VTTCLAMP_EN
CRITICAL
0.1UF
5%
1/16W
MF-LF
2 402
3 D
IN
4
11
S
G
MEMRESET_ISOL_LS5V_L
5
SSM6N15FEAPE
Q2850
5%
1/16W
MF-LF
402 2
NOSTUFF
C2817 1
0.047UF
75mA max load @ 0.75V
60mW max power
VTTCLAMP_L
CRITICAL
S 1
100K
33
=PPVTT_S0_VTTCLAMP
CPUMEM_S0
SSM6N15FEAPE
2 G
6 D
8
CRITICAL
CPUMEM_S0
SSM6N15FEAPE
SSM6N15FEAPE
B
S 1
CPUMEM_S0
CPUMEM_S0
SOT563
2 G
MEMVTT_EN_L
CRITICAL
MEMVTT Clamp
Ensures CKE signals are held low in S3
SOT563
5%
1/16W
MF-LF
402 2
CRITICAL
9
SSM6N15FEAPE
1
R2815
OUT
D 6
S 4
=DDRVTT_EN
R2817
0
1
2
5%
1/16W
MF-LF
402
Step
A
S0
to
S3
to
S0
PM_SLP_S3_L
PM_SLP_S4_L
CPU_MEM_RESET_L
0
1
2
3
ISOLATE_CPU_MEM_L
1
0
0
0
PLT_RESET_L
1
1
0
0
1
1
1
0
1
1
1
1
1
1
1
X
CPU_MEM_RESET_L
1
1
1
MEM_RESET_L
MEMVTT_EN
1
1
0
0
P1V5CPU_EN
1
1
1
0
4
5
6
7
0
0
0
1
0
1
1
1
1
1
1
1
1
1
1
1
X
0 (*)
1
1
1
1
1
CPU_MEM_RESET_L
0
1
1
1
1
1
1
1
SYNC_MASTER=D2_KEPLER
SYNC_DATE=01/13/2012
PAGE TITLE
CPU Memory S3 Support
DRAWING NUMBER
Apple Inc.
(*) CPU_MEM_RESET_L asserts due to loss of PM_MEM_PWRGD, must wait for software to clear before deasserting ISOLATE_CPU_MEM_L GPIO.
R
NOTICE OF PROPRIETARY PROPERTY:
NOTE: In the event of a S3- & gt; S5 transition ISOLATE_CPU_MEM_L will still be asserted on next S5- & gt; S0
transition. Rails will power-up as if from S3, but MEM_RESET_L will not properly assert. Software
must deassert ISOLATE_CPU_MEM_L and then generate a valid reset cycle on CPU_MEM_RESET_L.
8
7
6
5
051-9589
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
4
3
2
SIZE
D
REVISION
4.18.0
BRANCH
PAGE
28 OF 132
SHEET
27 OF 99
1
A
90 32 29 28 12
CS*
CKE
CK
CK*
ODT
H3 MEM_A_CS_L & lt; 0 & gt;
G10 MEM_A_CKE & lt; 0 & gt;
F8
G8
NC
VSS
MEM_A_CLK_P & lt; 0 & gt; 12
MEM_A_CLK_N & lt; 0 & gt; 12
90 32 29 28 12
VSS
F4
G4
H4
MEM_A_ODT & lt; 0 & gt; G2
MEM_A_ZQ & lt; 4 & gt;
H9
U2940
DDR3-1333
(SYM VER 2)
RESET*
DQ0
DQ1
DQ2
DQ3
NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7
H10
N1
12 28
32 90
MEM_A_CLK_P & lt; 0 & gt; 12
MEM_A_CLK_N & lt; 0 & gt; 12
32
MEM_A_DQ & lt; 32 & gt;
MEM_A_DQ & lt; 33 & gt;
MEM_A_DQ & lt; 34 & gt;
MEM_A_DQ & lt; 35 & gt;
MEM_A_DQ & lt; 36 & gt;
MEM_A_DQ & lt; 37 & gt;
MEM_A_DQ & lt; 38 & gt;
MEM_A_DQ & lt; 39 & gt;
MEM_A_DQS_P & lt; 4 & gt;
MEM_A_DQS_N & lt; 4 & gt;
VSSQ
12 29
90
12 29
90
12 29
90
12 29
90
12 29
90
90 32 29 28 12
F8
G8
ZQ
12 29
90
90 32 29 28 12
NC
H3 MEM_A_CS_L & lt; 0 & gt;
G10 MEM_A_CKE & lt; 0 & gt;
NC
12 29
90
12 29
90 12
90 32 29 28
CK
CK*
ODT
12 29
90
12 28
32 90
12 28
32 90
MEM_A_CLK_P & lt; 0 & gt; 12
MEM_A_CLK_N & lt; 0 & gt; 12
32
A1
NC
A4
NC
A11
NC
F2
NC
F10
MEM_A_A & lt; 0 & gt;
MEM_A_A & lt; 1 & gt;
MEM_A_A & lt; 2 & gt;
MEM_A_A & lt; 3 & gt;
MEM_A_A & lt; 4 & gt;
MEM_A_A & lt; 5 & gt;
MEM_A_A & lt; 6 & gt;
MEM_A_A & lt; 7 & gt;
MEM_A_A & lt; 8 & gt;
MEM_A_A & lt; 9 & gt;
MEM_A_A & lt; 10 & gt;
MEM_A_A & lt; 11 & gt;
MEM_A_A & lt; 12 & gt;
MEM_A_A & lt; 13 & gt;
MEM_A_A & lt; 14 & gt;
MEM_A_A & lt; 15 & gt;
K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8
90 32 29 28 12
J3
K9
J4
MEM_A_ZQ & lt; 2 & gt;
90 32 29 28 12
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14
F4
G4
H4
MEM_A_ZQ & lt; 5 & gt;
VDDQ
OMIT_TABLE
U2950
FBGA
DQ0
DQ1
DQ2
DQ3
NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7
(SYM VER 2)
1%
1/20W
MF
1 201
=PP1V5R1V35_S3_MEM_A
12 29
90
12 29
90
90 32 29 28 12
12 28
32 90
12 28
32 90
MEM_A_CLK_P & lt; 0 & gt; 12
MEM_A_CLK_N & lt; 0 & gt; 12
32
H10
N1
NC
NC
NC
DM/TDQS B8
NF/TDQS* A8
MEM_A_DQ & lt; 40 & gt;
MEM_A_DQ & lt; 41 & gt;
MEM_A_DQ & lt; 42 & gt;
MEM_A_DQ & lt; 43 & gt;
MEM_A_DQ & lt; 44 & gt;
MEM_A_DQ & lt; 45 & gt;
MEM_A_DQ & lt; 46 & gt;
MEM_A_DQ & lt; 47 & gt;
12 29
90
12 29
90
12 29
90
12 29
90
12 29
90
12 29
90
12 29
90
12 29
90
MEM_A_DQS_P & lt; 5 & gt;
MEM_A_DQS_N & lt; 5 & gt;
90 32 29 28 12
NC
90 32 29 28 12
H3 MEM_A_CS_L & lt; 0 & gt;
G10 MEM_A_CKE & lt; 0 & gt;
CK
CK*
F8
G8
NC
ZQ
12 29
90
12 29
90 12
90 32 29 28
12 28
32 90
12 28
32 90
MEM_A_CLK_P & lt; 0 & gt; 12
MEM_A_CLK_N & lt; 0 & gt; 12
32
A1
NC
A4
NC
A11
NC
F2
NC
F10
MEM_A_A & lt; 0 & gt;
MEM_A_A & lt; 1 & gt;
MEM_A_A & lt; 2 & gt;
MEM_A_A & lt; 3 & gt;
MEM_A_A & lt; 4 & gt;
MEM_A_A & lt; 5 & gt;
MEM_A_A & lt; 6 & gt;
MEM_A_A & lt; 7 & gt;
MEM_A_A & lt; 8 & gt;
MEM_A_A & lt; 9 & gt;
MEM_A_A & lt; 10 & gt;
MEM_A_A & lt; 11 & gt;
MEM_A_A & lt; 12 & gt;
MEM_A_A & lt; 13 & gt;
MEM_A_A & lt; 14 & gt;
MEM_A_A & lt; 15 & gt;
K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14
MEM_A_BA & lt; 0 & gt;
MEM_A_BA & lt; 1 & gt;
MEM_A_BA & lt; 2 & gt;
32 29 28 12
90
27 28 29
90 32 29 28 12 30 31
B4
C8
C3
C9
E4
E9
D3
E8
J3
K9
J4
90 32 29 28 12
90 32 29 28 12
90 32 29 28 12
F4
G4
H4
MEM_A_ODT & lt; 0 & gt; G2
90 32 28 12
MEM_A_ZQ & lt; 6 & gt;
MEM_A_ZQ & lt; 3 & gt;
240
1%
1/20W
MF
1 201
H9
1%
1/20W
MF
1 201
VREFCA J9
NC
VREFDQ E2
B10
C2
E3
E10
(SYM VER 2)
NC
NC
NC
N11
NC
N3
H10
N1
B4
C8
C3
C9
E4
E9
D3
E8
DQS C4
DQS* D4
DM/TDQS B8
NF/TDQS* A8
2.2UF
20%
10V
X5R-CERM 2
402
C2901
1
2.2UF
1
2.2UF
20%
10V
X5R-CERM 2
402
F8
G8
20%
10V
X5R-CERM 2
402
8
C2941
2.2UF
1
C2911
1
C2920 1
C2921 1
C2930 1
20%
10V
X5R-CERM 2
402
20%
10V
X5R-CERM 2
402
20%
10V
X5R-CERM 2
402
20%
10V
X5R-CERM 2
402
2.2UF
20%
10V
X5R-CERM 2
402
20%
10V
X5R-CERM 2
402
C2950
2.2UF
12 29 90
12 29 90
12 29 90
12 29 90
12 29 90
12 29 90
12 29
90
12 29
90
12 28 32 90
12 28 32 90
28 32 90
28 32 90
A1
NC
A4
NC
A11
NC
F2
NC
F10
NC
ZQ
NC
VSSQ
VDDQ
OMIT_TABLE
U2960
=PP1V5R1V35_S3_MEM_A
RESET*
FBGA
DQ0
DQ1
DQ2
DQ3
NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7
(SYM VER 2)
H10
N1
NC
NC
NC
1
VDD
VSS
28 12
90 32 29
28 12
90 32 29
MEM_A_DQS_P & lt; 6 & gt;
MEM_A_DQS_N & lt; 6 & gt;
12 29
90
12 29
90
12 29
90
12 29
90
12 29
90
12 29
90 12
90 32 29 28
90 32 29 28 12
NC
90 32 29 28 12
CK
CK*
F8
G8
ZQ
12 29
90
12 29
90
12 28
32 90
12 28
32 90
MEM_A_CLK_P & lt; 0 & gt; 12
MEM_A_CLK_N & lt; 0 & gt; 12
32
A1
NC
A4
NC
A11
NC
F2
NC
F10
MEM_A_A & lt; 0 & gt;
MEM_A_A & lt; 1 & gt;
MEM_A_A & lt; 2 & gt;
MEM_A_A & lt; 3 & gt;
MEM_A_A & lt; 4 & gt;
MEM_A_A & lt; 5 & gt;
MEM_A_A & lt; 6 & gt;
MEM_A_A & lt; 7 & gt;
MEM_A_A & lt; 8 & gt;
MEM_A_A & lt; 9 & gt;
MEM_A_A & lt; 10 & gt;
MEM_A_A & lt; 11 & gt;
MEM_A_A & lt; 12 & gt;
MEM_A_A & lt; 13 & gt;
MEM_A_A & lt; 14 & gt;
MEM_A_A & lt; 15 & gt;
K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14
MEM_A_BA & lt; 0 & gt;
MEM_A_BA & lt; 1 & gt;
MEM_A_BA & lt; 2 & gt;
32 29 28 12
H3 MEM_A_CS_L & lt; 0 & gt;
G10 MEM_A_CKE & lt; 0 & gt;
NC
20%
4V
CERM-X5R-1 2
201
20%
2 4V
CERM-X5R-1
201
CS*
CKE
RAS*
CAS*
WE*
C2978
0.47UF
0.47UF
MEM_A_DQ & lt; 48 & gt;
MEM_A_DQ & lt; 49 & gt;
MEM_A_DQ & lt; 50 & gt;
MEM_A_DQ & lt; 51 & gt;
MEM_A_DQ & lt; 52 & gt;
MEM_A_DQ & lt; 53 & gt;
MEM_A_DQ & lt; 54 & gt;
MEM_A_DQ & lt; 55 & gt;
J3
K9
J4
VDDQ
OMIT_TABLE
BA0
BA1
BA2
U2970
FBGA
MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L
90 32 29 28 12
90 32 29 28 12
F4
G4
H4
MEM_A_ODT & lt; 0 & gt; G2
90 32 28 12
MEM_A_ZQ & lt; 7 & gt;
H9
H10
N1
C2979
0.47UF
20%
2 4V
CERM-X5R-1
201
NC
NC
NC
N11
NC
N3 MEM_RESET_L
B4
C8
C3
C9
E4
E9
D3
E8
DQS C4
DQS* D4
DM/TDQS B8
NF/TDQS* A8
MEM_A_DQ & lt; 56 & gt;
MEM_A_DQ & lt; 57 & gt;
MEM_A_DQ & lt; 58 & gt;
MEM_A_DQ & lt; 59 & gt;
MEM_A_DQ & lt; 60 & gt;
MEM_A_DQ & lt; 61 & gt;
MEM_A_DQ & lt; 62 & gt;
MEM_A_DQ & lt; 63 & gt;
MEM_A_DQS_P & lt; 7 & gt;
MEM_A_DQS_N & lt; 7 & gt;
ODT
H3 MEM_A_CS_L & lt; 0 & gt;
G10 MEM_A_CKE & lt; 0 & gt;
CK
CK*
RAS*
CAS*
WE*
F8
G8
NC
ZQ
VSS
27 28 29 30 31
12 29 90
12 29 90
12 29 90
12 29 90
12 29 90
12 29 90
12 29 90
B
12 29 90
12 29
90
12 29
90
NC
CS*
CKE
28 32 90
28
90
1
20%
4V
CERM-X5R-1 2
201
H2
DQ0
DQ1
DQ2
DQ3
NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7
(SYM VER 2)
1
0.47UF
RESET*
DDR3-1333
A15
NC
VSSQ
8 28 29
C2977 1
C2969
32 29 28 12
90
27 28 29
90 32 29 28 12 30 31
B4
C8
C3
C9
E4
E9
D3
E8
DM/TDQS B8
NF/TDQS* A8
ODT
H9
1
90
N11
NC
N3 MEM_RESET_L
DQS C4
DQS* D4
A15
PP0V75_S3_MEM_VREFDQ_A
PP0V75_S3_MEM_VREFCA_A
89 33 29 28
20%
4V
CERM-X5R-1 2
201
H2
C
12 28 32 90
12 28 32 90
MEM_A_CLK_P & lt; 0 & gt; 12
MEM_A_CLK_N & lt; 0 & gt; 12
28 32 90
28 32 90
A1
NC
A4
NC
A11
NC
F2
NC
F10
VSSQ
NC
2
R2960
240
1%
1/20W
MF
1 201
R2970
240
1%
1/20W
MF
1 201
2.2UF
2.2UF
2.2UF
C2931
1
1
2.2UF
C2903
1
0.1UF
20%
10V
X5R-CERM 2
402
10%
2 6.3V
X5R
201
C2904
1
0.1UF
10%
2 6.3V
X5R
201
C2905
1
0.1UF
10%
2 6.3V
X5R
201
C2913
1
0.1UF
10%
2 6.3V
X5R
201
C2914
1
0.1UF
10%
2 6.3V
X5R
201
C2915
1
0.1UF
10%
2 6.3V
X5R
201
C2923
1
0.1UF
10%
2 6.3V
X5R
201
C2924
1
0.1UF
10%
2 6.3V
X5R
201
C2925
1
0.1UF
10%
2 6.3V
X5R
201
C2933
1
0.1UF
10%
6.3V
2 X5R
201
C2934
1
0.1UF
10%
6.3V
2 X5R
201
C2935
0.1UF
SYNC_DATE=01/13/2012
PAGE TITLE
DDR3 SDRAM Bank A (1 OF 2)
10%
6.3V
2 X5R
201
DRAWING NUMBER
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
2.2UF
12 29 90
MEM_A_CLK_P & lt; 0 & gt; 12
MEM_A_CLK_N & lt; 0 & gt; 12
051-9589
1
20%
10V
X5R-CERM 2
402
C2951
1
2.2UF
20%
10V
X5R-CERM 2
402
7
C2960 1
C2961 1
C2970 1
2.2UF
2.2UF
2.2UF
20%
10V
X5R-CERM 2
402
20%
10V
X5R-CERM 2
402
20%
10V
X5R-CERM 2
402
C2971
2.2UF
1
20%
10V
X5R-CERM 2
402
6
1
C2943
0.1UF
10%
6.3V
2 X5R
201
1
C2944
0.1UF
10%
2 6.3V
X5R
201
1
C2945
0.1UF
10%
2 6.3V
X5R
201
5
1
C2953
0.1UF
10%
2 6.3V
X5R
201
1
C2954
0.1UF
10%
2 6.3V
X5R
201
1
C2955
0.1UF
10%
2 6.3V
X5R
201
1
C2963
0.1UF
10%
2 6.3V
X5R
201
4
1
C2964
0.1UF
10%
2 6.3V
X5R
201
1
C2965
0.1UF
10%
2 6.3V
X5R
201
1
C2973
0.1UF
10%
6.3V
2 X5R
201
3
1
C2974
0.1UF
10%
6.3V
2 X5R
201
1
C2975
0.1UF
10%
6.3V
2 X5R
201
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
2
SIZE
D
REVISION
R
C2940 1
12 29 90
NC
CK
CK*
ODT
D
27 28 29 30 31
SDRAM Bypassing (NOTE: 2x 2.2uF and 3x 0.1uF per chip)
8 28 29
C2910
MEM_A_DQS_P & lt; 3 & gt;
MEM_A_DQS_N & lt; 3 & gt;
H3 MEM_A_CS_L & lt; 0 & gt;
G10 MEM_A_CKE & lt; 0 & gt;
SYNC_MASTER=D2_KEPLER
C2900 1
MEM_A_DQ & lt; 31 & gt;
MEM_A_DQ & lt; 24 & gt;
MEM_A_DQ & lt; 27 & gt;
MEM_A_DQ & lt; 28 & gt;
MEM_A_DQ & lt; 30 & gt;
MEM_A_DQ & lt; 25 & gt;
MEM_A_DQ & lt; 26 & gt;
MEM_A_DQ & lt; 29 & gt;
CS*
CKE
89 33 29 28
2
R2950
DQ0
DQ1
DQ2
DQ3
NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7
VSS
0.47UF
DDR3-1333
NC
VSSQ
MEM_A_ODT & lt; 0 & gt; G2
90 32 28 12
8 28 29
BA0
BA1
BA2
MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L
RAS*
CAS*
WE*
MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L
0.47UF
MEM_RESET_L
RESET*
FBGA
A15
PP0V75_S3_MEM_VREFDQ_A
PP0V75_S3_MEM_VREFCA_A
28 32 90
28
90
A3
A10
D8
G9
G3
K2
K10
M2
M10
VREFCA J9
NC
VREFDQ E2
B10
C2
E3
E10
A3
A10
D8
G9
G3
K2
K10
M2
M10
VDD
32 29 28 12
F4
G4
H4
U2930
DDR3-1333
28 32 90
28
90
90 32 29 28 12
240
C2968
20%
4V
CERM-X5R-1 2
201
20%
2 4V
CERM-X5R-1
201
BA0
BA1
BA2
R2930
0.47UF
0.47UF
J3
K9
J4
VDDQ
OMIT_TABLE
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14
NC
C2967 1
C2959
90
N11
NC
N3 MEM_RESET_L
DQS C4
DQS* D4
ODT
H9
1
20%
4V
CERM-X5R-1 2
201
H2
RESET*
DDR3-1333
VSS
B3
D2
B9
C10
D10
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
240
12 29
90
90 32 29 28 12
NC
A1
NC
A4
NC
A11
NC
F2
NC
F10
VSSQ
89 33 29 28
2
R2940
12 29
90
12 29
90
12 29
90 12
90 32 29 28
F8
G8
NC
89 33 29 28
CS*
CKE
NC
2
12 29
90
12 29
90
K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8
C2939
20%
2 4V
CERM-X5R-1
201
2
1%
1/20W
MF
1 201
0.47UF
RAS*
CAS*
WE*
MEM_A_ODT & lt; 0 & gt; G2
90 32 28 12
12 29
90
H3 MEM_A_CS_L & lt; 0 & gt;
G10 MEM_A_CKE & lt; 0 & gt;
ZQ
VSS
12 29
90
MEM_A_DQS_P & lt; 2 & gt;
MEM_A_DQS_N & lt; 2 & gt;
CK
CK*
ODT
H9
32 29 28 12
90
27 28 29
90 32 29 28 12 30 31
MEM_A_DQ & lt; 22 & gt;
MEM_A_DQ & lt; 21 & gt;
MEM_A_DQ & lt; 16 & gt;
MEM_A_DQ & lt; 17 & gt;
MEM_A_DQ & lt; 18 & gt;
MEM_A_DQ & lt; 23 & gt;
MEM_A_DQ & lt; 20 & gt;
MEM_A_DQ & lt; 19 & gt;
MEM_A_A & lt; 0 & gt;
MEM_A_A & lt; 1 & gt;
MEM_A_A & lt; 2 & gt;
MEM_A_A & lt; 3 & gt;
MEM_A_A & lt; 4 & gt;
MEM_A_A & lt; 5 & gt;
MEM_A_A & lt; 6 & gt;
MEM_A_A & lt; 7 & gt;
MEM_A_A & lt; 8 & gt;
MEM_A_A & lt; 9 & gt;
MEM_A_A & lt; 10 & gt;
MEM_A_A & lt; 11 & gt;
MEM_A_A & lt; 12 & gt;
MEM_A_A & lt; 13 & gt;
MEM_A_A & lt; 14 & gt;
MEM_A_A & lt; 15 & gt;
MEM_A_BA & lt; 0 & gt;
MEM_A_BA & lt; 1 & gt;
MEM_A_BA & lt; 2 & gt;
90 32 29 28 12
CS*
CKE
=PP1V5R1V35_S3_MEM_A
BA0
BA1
BA2
MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L
90 32 29 28 12
MEM_A_ODT & lt; 0 & gt; G2
90 32 28 12
8 28 29
28 32 90
28
90
RAS*
CAS*
WE*
DM/TDQS B8
NF/TDQS* A8
A15
PP0V75_S3_MEM_VREFDQ_A
PP0V75_S3_MEM_VREFCA_A
A15
MEM_A_BA & lt; 0 & gt;
MEM_A_BA & lt; 1 & gt;
MEM_A_BA & lt; 2 & gt;
12 29
90
F4
G4
H4
MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L
B4
C8
C3
C9
E4
E9
D3
E8
DQS C4
DQS* D4
28 32 90
28
90
90 32 29 28 12
C2958 1
VDD
32 29 28 12
BA0
BA1
BA2
240
1
20%
4V
CERM-X5R-1 2
201
20%
2 4V
CERM-X5R-1
201
J3
K9
J4
R2920
0.47UF
0.47UF
CS*
CKE
RAS*
CAS*
WE*
C2957
C2949
32 29 28 12
90
27 28 29
90 32 29 28 12 30 31
B4
C8
C3
C9
E4
E9
D3
E8
DM/TDQS B8
NF/TDQS* A8
A15
NC
NC
NC
1
90
N11
NC
N3 MEM_RESET_L
DQS C4
DQS* D4
VSS
A
12 28
32 90
B3
D2
B9
C10
D10
28 12
90 32
20%
4V
CERM-X5R-1 2
201
H2
BA0
BA1
BA2
MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L
90
28 12
32 29
90 32 29 28 12
DQ0
DQ1
DQ2
DQ3
NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7
(SYM VER 2)
VDD
N1
MEM_RESET_L
RESET*
FBGA
NC
VREFCA J9
NC
J3
K9
J4
0.47UF
VREFCA J9
NC
MEM_A_BA & lt; 0 & gt;
MEM_A_BA & lt; 1 & gt;
MEM_A_BA & lt; 2 & gt;
VDDQ
OMIT_TABLE
FBGA
89 33 29 28
=PP1V5R1V35_S3_MEM_A
VREFDQ E2
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14
B10
C2
E3
E10
A3
A10
D8
G9
G3
K2
K10
M2
M10
VDD
K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8
89 33 29 28
8 28 29
C2948 1
MEM_A_A & lt; 0 & gt;
MEM_A_A & lt; 1 & gt;
MEM_A_A & lt; 2 & gt;
MEM_A_A & lt; 3 & gt;
MEM_A_A & lt; 4 & gt;
MEM_A_A & lt; 5 & gt;
MEM_A_A & lt; 6 & gt;
MEM_A_A & lt; 7 & gt;
MEM_A_A & lt; 8 & gt;
MEM_A_A & lt; 9 & gt;
MEM_A_A & lt; 10 & gt;
MEM_A_A & lt; 11 & gt;
MEM_A_A & lt; 12 & gt;
MEM_A_A & lt; 13 & gt;
MEM_A_A & lt; 14 & gt;
MEM_A_A & lt; 15 & gt;
90
28 12
32 29
90 32 29 28 12
NC
B3
D2
B9
C10
D10
1%
1/20W
MF
1 201
1
20%
4V
CERM-X5R-1 2
201
90 32
28 12
29
90
28 12
32 29
12 29
90
12 29
90 12
90 32 29 28
A1
NC
A4
NC
A11
NC
F2
NC
F10
VSSQ
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
240
0.47UF
90
12
29
90
32 29
28 12
MEM_A_DQS_P & lt; 1 & gt;
MEM_A_DQS_N & lt; 1 & gt;
U2920
DDR3-1333
NC
NC
NC
N11
NC
N3
H10
2
R2910
VREFDQ E2
C2947
32
12
12 29
90
F8
G8
NC
PP0V75_S3_MEM_VREFDQ_A
PP0V75_S3_MEM_VREFCA_A
=PP1V5R1V35_S3_MEM_A
90
28
29
28
32
12 29
90
H3 MEM_A_CS_L & lt; 0 & gt;
G10 MEM_A_CKE & lt; 0 & gt;
ZQ
B10
C2
E3
E10
89 33 29 28
90 32
28 12
90
29
32 29
28 12
ODT
H9
MEM_A_ZQ & lt; 1 & gt;
12 29
90
CK
CK*
A3
A10
D8
G9
G3
K2
K10
M2
M10
89 33 29 28
28 12
32 29
90
90
28 12
32 29
90
28 12
32 29
RAS*
CAS*
WE*
MEM_A_ODT & lt; 0 & gt; G2
90 32 28 12
B3
D2
B9
C10
D10
1%
1/20W
MF
1 201
90
28 12
32 29
F4
G4
H4
MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L
MEM_A_BA & lt; 0 & gt;
MEM_A_BA & lt; 1 & gt;
MEM_A_BA & lt; 2 & gt;
12 29
90
CS*
CKE
NC
VSSQ
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
240
90
28 12
32 29
28 12
32 29
90
90
28 12
32 29
90
28 12
32 29
BA0
BA1
BA2
12 29
90
12 29
90
2
R2900
90
28 12
32 29
J3
K9
J4
DM/TDQS B8
NF/TDQS* A8
28 32 90
28
32 90
90 32 29 28 12
A1
NC
A4
NC
A11
NC
F2
NC
F10
ZQ
12 28
32 90
12 28
32 90
A15
12 29
90
VDDQ
OMIT_TABLE
1
20%
4V
CERM-X5R-1 2
H2
201
VREFCA J9
NC
90 32 29 28 12
NC
DQS C4
DQS* D4
12 29
90
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14
1
0.47UF
VREFDQ E2
12 29
90
12 29
90 12
90 32 29 28
32 29 28 12
90
27 28 29
90 32 29 28 12 30 31
MEM_A_DQ & lt; 14 & gt;
MEM_A_DQ & lt; 9 & gt;
MEM_A_DQ & lt; 10 & gt;
MEM_A_DQ & lt; 15 & gt;
MEM_A_DQ & lt; 11 & gt;
MEM_A_DQ & lt; 13 & gt;
MEM_A_DQ & lt; 8 & gt;
MEM_A_DQ & lt; 12 & gt;
K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8
20%
4V
CERM-X5R-1 2
201
20%
2 4V
CERM-X5R-1
201
B3
D2
B9
C10
D10
MEM_A_DQS_P & lt; 0 & gt;
MEM_A_DQS_N & lt; 0 & gt;
B4
C8
C3
C9
E4
E9
D3
E8
MEM_A_A & lt; 0 & gt;
MEM_A_A & lt; 1 & gt;
MEM_A_A & lt; 2 & gt;
MEM_A_A & lt; 3 & gt;
MEM_A_A & lt; 4 & gt;
MEM_A_A & lt; 5 & gt;
MEM_A_A & lt; 6 & gt;
MEM_A_A & lt; 7 & gt;
MEM_A_A & lt; 8 & gt;
MEM_A_A & lt; 9 & gt;
MEM_A_A & lt; 10 & gt;
MEM_A_A & lt; 11 & gt;
MEM_A_A & lt; 12 & gt;
MEM_A_A & lt; 13 & gt;
MEM_A_A & lt; 14 & gt;
MEM_A_A & lt; 15 & gt;
20%
4V
CERM-X5R-1 2
H2
201
C2938
0.47UF
0.47UF
B3
D2
B9
C10
D10
12 29
90
90 32 29 28 12
C2937 1
C2929
B10
C2
E3
E10
12 29
90
DQ0
DQ1
DQ2
DQ3
NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7
(SYM VER 2)
N1
MEM_RESET_L
RESET*
FBGA
VDD
H10
1
8 28 29
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
12 29
90
U2910
DDR3-1333
NC
NC
NC
N11
NC
N3
20%
4V
2 CERM-X5R-1
201
1
0.47UF
A3
A10
D8
G9
G3
K2
K10
M2
M10
12 29
90
12 29
90
2
C
B
12 29
90
28 12
90 32 29
VDDQ
OMIT_TABLE
20%
4V
CERM-X5R-1 2
201
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
DM/TDQS B8
NF/TDQS* A8
12 29
90
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14
20%
4V
CERM-X5R-1 2
H2
201
C2928
0.47UF
0.47UF
VREFCA J9
NC
H9
MEM_A_ZQ & lt; 0 & gt;
32 29 28 12
90
27 28 29
90 32 29 28 12 30 31
MEM_A_DQ & lt; 0 & gt;
MEM_A_DQ & lt; 6 & gt;
MEM_A_DQ & lt; 7 & gt;
MEM_A_DQ & lt; 5 & gt;
MEM_A_DQ & lt; 3 & gt;
MEM_A_DQ & lt; 1 & gt;
MEM_A_DQ & lt; 2 & gt;
MEM_A_DQ & lt; 4 & gt;
K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8
C2927 1
C2919
B3
D2
B9
C10
D10
MEM_A_ODT & lt; 0 & gt; G2
28 12
90 32
B4
C8
C3
C9
E4
E9
D3
E8
MEM_A_A & lt; 0 & gt;
MEM_A_A & lt; 1 & gt;
MEM_A_A & lt; 2 & gt;
MEM_A_A & lt; 3 & gt;
MEM_A_A & lt; 4 & gt;
MEM_A_A & lt; 5 & gt;
MEM_A_A & lt; 6 & gt;
MEM_A_A & lt; 7 & gt;
MEM_A_A & lt; 8 & gt;
MEM_A_A & lt; 9 & gt;
MEM_A_A & lt; 10 & gt;
MEM_A_A & lt; 11 & gt;
MEM_A_A & lt; 12 & gt;
MEM_A_A & lt; 13 & gt;
MEM_A_A & lt; 14 & gt;
MEM_A_A & lt; 15 & gt;
MEM_A_BA & lt; 0 & gt;
MEM_A_BA & lt; 1 & gt;
MEM_A_BA & lt; 2 & gt;
90 32 29 28 12
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
90
28 12
32 29
N1
DQS C4
DQS* D4
A15
VDD
H10
1
0.47UF
VREFDQ E2
RAS*
CAS*
WE*
28 12
32 29
32
90
28 12
29
9090 32
28 12
29
90
28 12
32 29
28 12
32 29
90
90
28 12
32 29
DQ0
DQ1
DQ2
DQ3
NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7
(SYM VER 2)
20%
2 4V
CERM-X5R-1
201
MEM_RESET_L
RESET*
FBGA
C2918 1
20%
4V
CERM-X5R-1 2
201
89 33 29 28
=PP1V5R1V35_S3_MEM_A
B3
D2
B9
C10
D10
F4
G4
H4
90 32
28 12
29
90
28 12
32 29
U2900
DDR3-1333
1
0.47UF
0.47UF
1
PP0V75_S3_MEM_VREFDQ_A
PP0V75_S3_MEM_VREFCA_A
89 33 29 28
8 28 29
B10
C2
E3
E10
MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L
90 32
28 12
90
29
32 29
28 12
90 32
28 12
29
90
28 12
32 29
NC
NC
NC
N11
NC
N3
C2917
C2909
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
BA0
BA1
BA2
90
28 12
32 29
VREFCA J9
NC
J3
K9
J4
20%
4V
CERM-X5R-1 2
H2
201
VREFDQ E2
MEM_A_BA & lt; 0 & gt;
MEM_A_BA & lt; 1 & gt;
MEM_A_BA & lt; 2 & gt;
VDDQ
OMIT_TABLE
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14
90
28 12
32 29
28 12
32 29
90
90
28 12
32 29
D
K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8
B10
C2
E3
E10
A3
A10
D8
G9
G3
K2
K10
M2
M10
VDD
MEM_A_A & lt; 0 & gt;
MEM_A_A & lt; 1 & gt;
MEM_A_A & lt; 2 & gt;
MEM_A_A & lt; 3 & gt;
MEM_A_A & lt; 4 & gt;
MEM_A_A & lt; 5 & gt;
MEM_A_A & lt; 6 & gt;
MEM_A_A & lt; 7 & gt;
MEM_A_A & lt; 8 & gt;
MEM_A_A & lt; 9 & gt;
MEM_A_A & lt; 10 & gt;
MEM_A_A & lt; 11 & gt;
MEM_A_A & lt; 12 & gt;
MEM_A_A & lt; 13 & gt;
MEM_A_A & lt; 14 & gt;
MEM_A_A & lt; 15 & gt;
1
0.47UF
89 33 29 28
2
PP0V75_S3_MEM_VREFDQ_A
PP0V75_S3_MEM_VREFCA_A
=PP1V5R1V35_S3_MEM_A
8 28 29
VREFCA J9
NC
C2908 1
20%
4V
CERM-X5R-1 2
201
3
89 33 29 28
A3
A10
D8
G9
G3
K2
K10
M2
M10
1
0.47UF
90 32
28 12
29
90
28 12
32 29
89 33 29 28
=PP1V5R1V35_S3_MEM_A
8 28 29
4
PP0V75_S3_MEM_VREFDQ_A
PP0V75_S3_MEM_VREFCA_A
B10
C2
E3
E10
=PP1V5R1V35_S3_MEM_A
C2907
5
89 33 29 28
A3
A10
D8
G9
G3
K2
K10
M2
M10
89 33 29 28
6
PP0V75_S3_MEM_VREFDQ_A
PP0V75_S3_MEM_VREFCA_A
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
7
89 33 29 28
VREFDQ E2
8
4.18.0
BRANCH
PAGE
29 OF 132
SHEET
28 OF 99
1
A
1%
1/20W
MF
1 201
89 33 29 28
89 33 29 28
C3047
240
1%
1/20W
MF
1 201
PP0V75_S3_MEM_VREFDQ_A
PP0V75_S3_MEM_VREFCA_A
=PP1V5R1V35_S3_MEM_A
C3048 1
90
28 12
32 29
28 12
32 29
90
90
28 12
32 29
90
28 12
32 29
90 32
28 12
90
29
32 29
28 12
90
28
29
28
32
32
12
90
28
29
28
32
32
12
90
12
29
90
32 29
28 12
90
12
29
28 12
32 29
90
F4
G4
H4
VREFCA J9
NC
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14
U3040
DDR3-1333
FBGA
(SYM VER 2)
RESET*
DQ0
DQ1
DQ2
DQ3
NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7
N1
NC
NC
NC
MEM_A_DQ & lt; 33 & gt;
MEM_A_DQ & lt; 32 & gt;
MEM_A_DQ & lt; 35 & gt;
MEM_A_DQ & lt; 34 & gt;
MEM_A_DQ & lt; 39 & gt;
MEM_A_DQ & lt; 38 & gt;
MEM_A_DQ & lt; 37 & gt;
MEM_A_DQ & lt; 36 & gt;
12 28
90
28 12
90 32 29
28 12
90 32 29
12 28
90
12 28
90
90
12 28
90 32 29 28 12
90 32 29 28 12
NC
90 32 29 28 12
F8
G8
VSSQ
12 28
90
MEM_A_DQS_P & lt; 4 & gt;
MEM_A_DQS_N & lt; 4 & gt;
H3 MEM_A_CS_L & lt; 1 & gt;
G10 MEM_A_CKE & lt; 1 & gt;
ZQ
12 28
90
12 29
32 90
28 12
90 32 29
MEM_A_A & lt; 0 & gt;
MEM_A_A & lt; 1 & gt;
MEM_A_A & lt; 2 & gt;
MEM_A_A & lt; 4 & gt;
MEM_A_A & lt; 3 & gt;
MEM_A_A & lt; 6 & gt;
MEM_A_A & lt; 5 & gt;
MEM_A_A & lt; 8 & gt;
MEM_A_A & lt; 7 & gt;
MEM_A_A & lt; 9 & gt;
MEM_A_A & lt; 10 & gt;
MEM_A_A & lt; 11 & gt;
MEM_A_A & lt; 12 & gt;
MEM_A_A & lt; 13 & gt;
MEM_A_A & lt; 14 & gt;
MEM_A_A & lt; 15 & gt;
K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8
J3
K9
J4
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14
F4
G4
H4
89 33 29 28
89 33 29 28
VDDQ
OMIT_TABLE
U3050
RESET*
DDR3-1333
FBGA
DQ0
DQ1
DQ2
DQ3
NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7
(SYM VER 2)
1
H10
N1
NC
NC
NC
B4
C8
C3
C9
E4
E9
D3
E8
DQS C4
DQS* D4
DM/TDQS B8
NF/TDQS* A8
32 29 28 12
90
27
90 32 29 28 12 28 29 30
31
MEM_A_DQ & lt; 41 & gt;
MEM_A_DQ & lt; 40 & gt;
MEM_A_DQ & lt; 43 & gt;
MEM_A_DQ & lt; 42 & gt;
MEM_A_DQ & lt; 47 & gt;
MEM_A_DQ & lt; 46 & gt;
MEM_A_DQ & lt; 45 & gt;
MEM_A_DQ & lt; 44 & gt;
12 28
90
12 28
90
28 12
90 32 29
12 28
90
28 12
90 32 29
12 28
90
12 28
90
12 28
90
MEM_A_DQS_P & lt; 5 & gt;
MEM_A_DQS_N & lt; 5 & gt;
12 28
90
90
12 28
90 32 29 28 12
90 32 29 28 12
NC
90 32 29 28 12
H3 MEM_A_CS_L & lt; 1 & gt;
G10 MEM_A_CKE & lt; 1 & gt;
CK
CK*
F8
G8
ZQ
NC
VSS
12 29
32 90
12 29
32 90
MEM_A_CLK_P & lt; 1 & gt; 12
MEM_A_CLK_N & lt; 1 & gt; 12
32
A1
NC
A4
NC
A11
NC
F2
NC
F10
1%
1/20W
MF
1 201
=PP1V5R1V35_S3_MEM_A
MEM_A_A & lt; 0 & gt;
MEM_A_A & lt; 1 & gt;
MEM_A_A & lt; 2 & gt;
MEM_A_A & lt; 4 & gt;
MEM_A_A & lt; 3 & gt;
MEM_A_A & lt; 6 & gt;
MEM_A_A & lt; 5 & gt;
MEM_A_A & lt; 8 & gt;
MEM_A_A & lt; 7 & gt;
MEM_A_A & lt; 9 & gt;
MEM_A_A & lt; 10 & gt;
MEM_A_A & lt; 11 & gt;
MEM_A_A & lt; 12 & gt;
MEM_A_A & lt; 13 & gt;
MEM_A_A & lt; 14 & gt;
MEM_A_A & lt; 15 & gt;
K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8
90 32 29 28 12
J3
K9
J4
90 32 29 28 12
90 32 29 28 12
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14
F4
G4
H4
240
1%
1/20W
MF
1 201
2.2UF
20%
10V
X5R-CERM 2
402
C3001
1
2.2UF
1
2.2UF
20%
10V
X5R-CERM 2
402
20%
10V
X5R-CERM 2
402
8
C3041
2.2UF
1
C3011
1
C3020 1
C3021 1
20%
10V
X5R-CERM 2
402
20%
10V
X5R-CERM 2
402
20%
10V
X5R-CERM 2
402
2.2UF
20%
10V
X5R-CERM 2
402
20%
10V
X5R-CERM 2
402
C3050
2.2UF
12 28 90
12 28 90
12 28 90
12 28 90
12 28 90
12 28 90
12 28
90
12 28
90
12 29 32 90
12 29 32 90
29 32 90
29 32 90
VREFDQ E2
B10
C2
E3
E10
VREFCA J9
NC
A1
NC
A4
NC
A11
NC
F2
NC
F10
NC
NC
VSSQ
U3060
RESET*
FBGA
DQ0
DQ1
DQ2
DQ3
NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7
(SYM VER 2)
89 33 29 28
1
H10
N1
NC
NC
NC
1
DM/TDQS B8
NF/TDQS* A8
VDD
MEM_A_DQ & lt; 49 & gt;
MEM_A_DQ & lt; 48 & gt;
MEM_A_DQ & lt; 51 & gt;
MEM_A_DQ & lt; 50 & gt;
MEM_A_DQ & lt; 55 & gt;
MEM_A_DQ & lt; 54 & gt;
MEM_A_DQ & lt; 53 & gt;
MEM_A_DQ & lt; 52 & gt;
12 28
90
12 28
90
12 28
90
12 28
90
12 28
90
12 28
90
12 28
90
MEM_A_DQS_P & lt; 6 & gt;
MEM_A_DQS_N & lt; 6 & gt;
12
90
12
90
90 32 29
28
28
12
28
90 32 29 28 12
NC
90 32 29 28 12
CK
CK*
VSS
12 28
90
F8
G8
12 29
32 90
12 29
32 90
MEM_A_CLK_P & lt; 1 & gt; 12
MEM_A_CLK_N & lt; 1 & gt; 12
32
A1
NC
A4
NC
A11
NC
F2
NC
F10
MEM_A_A & lt; 0 & gt;
MEM_A_A & lt; 1 & gt;
MEM_A_A & lt; 2 & gt;
MEM_A_A & lt; 4 & gt;
MEM_A_A & lt; 3 & gt;
MEM_A_A & lt; 6 & gt;
MEM_A_A & lt; 5 & gt;
MEM_A_A & lt; 8 & gt;
MEM_A_A & lt; 7 & gt;
MEM_A_A & lt; 9 & gt;
MEM_A_A & lt; 10 & gt;
MEM_A_A & lt; 11 & gt;
MEM_A_A & lt; 12 & gt;
MEM_A_A & lt; 13 & gt;
MEM_A_A & lt; 14 & gt;
MEM_A_A & lt; 15 & gt;
K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14
MEM_A_BA & lt; 1 & gt;
MEM_A_BA & lt; 0 & gt;
MEM_A_BA & lt; 2 & gt;
32 29 28 12
H3 MEM_A_CS_L & lt; 1 & gt;
G10 MEM_A_CKE & lt; 1 & gt;
ZQ
20%
4V
CERM-X5R-1 2
201
20%
2 4V
CERM-X5R-1
201
CS*
CKE
NC
C3078
0.47UF
0.47UF
32 29 28 12
90
27 28 29
90 32 29 28 12 30 31
B4
C8
C3
C9
E4
E9
D3
E8
J3
K9
J4
VDDQ
OMIT_TABLE
BA0
BA1
BA2
U3070
FBGA
MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L
90 32 29 28 12
90 32 29 28 12
F4
G4
H4
0.47UF
20%
2 4V
CERM-X5R-1
201
NC
NC
NC
B4
C8
C3
C9
E4
E9
D3
E8
MEM_A_DQ & lt; 57 & gt;
MEM_A_DQ & lt; 56 & gt;
MEM_A_DQ & lt; 59 & gt;
MEM_A_DQ & lt; 58 & gt;
MEM_A_DQ & lt; 63 & gt;
MEM_A_DQ & lt; 62 & gt;
MEM_A_DQ & lt; 61 & gt;
MEM_A_DQ & lt; 60 & gt;
MEM_A_DQS_P & lt; 7 & gt;
MEM_A_DQS_N & lt; 7 & gt;
H3 MEM_A_CS_L & lt; 1 & gt;
G10 MEM_A_CKE & lt; 1 & gt;
CK
CK*
F8
G8
ZQ
NC
VSS
27 28 29 30 31
12 28 90
12 28 90
12 28 90
12 28 90
12 28 90
12 28 90
12 28 90
B
12 28 90
12 28
90
12 28
90
NC
CS*
CKE
ODT
MEM_A_ZQ & lt; 15 & gt; H9
N1
DM/TDQS B8
NF/TDQS* A8
RAS*
CAS*
WE*
MEM_A_ODT & lt; 1 & gt; G2
90 32 29 12
H10
C3079
N11
NC
N3 MEM_RESET_L
DQS C4
DQS* D4
29 32 90
29
90
1
20%
4V
CERM-X5R-1 2
201
H2
DQ0
DQ1
DQ2
DQ3
NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7
(SYM VER 2)
1
0.47UF
RESET*
DDR3-1333
A15
NC
VSSQ
8 28 29
C3077 1
C3069
90
N11
NC
N3 MEM_RESET_L
DQS C4
DQS* D4
ODT
MEM_A_ZQ & lt; 14 & gt; H9
PP0V75_S3_MEM_VREFDQ_A
PP0V75_S3_MEM_VREFCA_A
89 33 29 28
20%
4V
CERM-X5R-1 2
201
H2
C
12 29 32 90
12 29 32 90
MEM_A_CLK_P & lt; 1 & gt; 12
MEM_A_CLK_N & lt; 1 & gt; 12
29 32 90
29 32 90
A1
NC
A4
NC
A11
NC
F2
NC
F10
VSSQ
NC
2
R3060
240
1%
1/20W
MF
1 201
R3070
240
1%
1/20W
MF
1 201
2.2UF
2.2UF
C3030 1 C3031
2.2UF
20%
10V
X5R-CERM 2
402
1
1
2.2UF
C3003
1
0.1UF
20%
10V
X5R-CERM 2
402
10%
2 6.3V
X5R
201
C3004
1
0.1UF
10%
2 6.3V
X5R
201
C3005
1
0.1UF
10%
2 6.3V
X5R
201
C3013
1
0.1UF
10%
2 6.3V
X5R
201
C3014
1
0.1UF
10%
2 6.3V
X5R
201
C3015
1
0.1UF
10%
2 6.3V
X5R
201
C3023
1
0.1UF
10%
2 6.3V
X5R
201
C3024
1
0.1UF
10%
2 6.3V
X5R
201
C3025
1
0.1UF
10%
2 6.3V
X5R
201
C3033
1
0.1UF
10%
6.3V
2 X5R
201
C3034
1
0.1UF
10%
6.3V
2 X5R
201
C3035
0.1UF
SYNC_DATE=01/13/2012
PAGE TITLE
DDR3 SDRAM Bank A (2 OF 2)
10%
6.3V
2 X5R
201
DRAWING NUMBER
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
2.2UF
12 28 90
MEM_A_CLK_P & lt; 1 & gt; 12
MEM_A_CLK_N & lt; 1 & gt; 12
051-9589
1
20%
10V
X5R-CERM 2
402
C3051
1
2.2UF
20%
10V
X5R-CERM 2
402
7
C3060 1
C3061 1
2.2UF
2.2UF
20%
10V
X5R-CERM 2
402
20%
10V
X5R-CERM 2
402
C3070 1 C3071
2.2UF
20%
10V
X5R-CERM 2
402
2.2UF
1
20%
10V
X5R-CERM 2
402
6
1
C3043
0.1UF
10%
2 6.3V
X5R
201
1
C3044
0.1UF
10%
2 6.3V
X5R
201
1
C3045
0.1UF
10%
2 6.3V
X5R
201
5
1
C3053
0.1UF
10%
2 6.3V
X5R
201
1
C3054
0.1UF
10%
2 6.3V
X5R
201
1
C3055
0.1UF
10%
2 6.3V
X5R
201
1
C3063
0.1UF
10%
2 6.3V
X5R
201
4
1
C3064
0.1UF
10%
2 6.3V
X5R
201
1
C3065
0.1UF
10%
2 6.3V
X5R
201
1
C3073
0.1UF
10%
6.3V
2 X5R
201
3
1
C3074
0.1UF
10%
6.3V
2 X5R
201
1
C3075
0.1UF
10%
6.3V
2 X5R
201
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
2
SIZE
D
REVISION
R
C3040 1
12 28 90
SDRAM Bypassing (NOTE: 2x 2.2uF and 3x 0.1uF per chip)
8 28 29
C3010
D
27 28 29 30 31
NC
F8
G8
SYNC_MASTER=D2_KEPLER
C3000 1
MEM_A_DQS_P & lt; 3 & gt;
MEM_A_DQS_N & lt; 3 & gt;
H3 MEM_A_CS_L & lt; 1 & gt;
G10 MEM_A_CKE & lt; 1 & gt;
ZQ
1%
1/20W
MF
1 201
2
R3050
A3
A10
D8
G9
G3
K2
K10
M2
M10
VREFCA J9
NC
VREFDQ E2
B10
C2
E3
E10
VDDQ
OMIT_TABLE
DDR3-1333
NC
VSSQ
ODT
VSS
0.47UF
RAS*
CAS*
WE*
MEM_A_ODT & lt; 1 & gt; G2
90 32 29 12
MEM_A_DQ & lt; 24 & gt;
MEM_A_DQ & lt; 31 & gt;
MEM_A_DQ & lt; 28 & gt;
MEM_A_DQ & lt; 27 & gt;
MEM_A_DQ & lt; 29 & gt;
MEM_A_DQ & lt; 26 & gt;
MEM_A_DQ & lt; 25 & gt;
MEM_A_DQ & lt; 30 & gt;
CK
CK*
RAS*
CAS*
WE*
MEM_A_ZQ & lt; 11 & gt; H9
B4
C8
C3
C9
E4
E9
D3
E8
CS*
CKE
=PP1V5R1V35_S3_MEM_A
BA0
BA1
BA2
MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L
F4
G4
H4
MEM_A_ODT & lt; 1 & gt; G2
90 32 29 12
8 28 29
29 32 90
29
90
A15
PP0V75_S3_MEM_VREFDQ_A
PP0V75_S3_MEM_VREFCA_A
A15
MEM_A_BA & lt; 1 & gt;
MEM_A_BA & lt; 0 & gt;
MEM_A_BA & lt; 2 & gt;
32 29 28 12
MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L
29
32 90
90 32 29 28 12
N1
DM/TDQS B8
NF/TDQS* A8
29 32 90
240
C3068
20%
4V
CERM-X5R-1 2
201
VDD
90
N11
NC
N3 MEM_RESET_L
BA0
BA1
BA2
R3030
0.47UF
20%
2 4V
CERM-X5R-1
201
CS*
CKE
NC
B3
D2
B9
C10
D10
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
240
12 29
32 90
J3
K9
J4
NC
NC
NC
N11
NC
N3
H10
DQS C4
DQS* D4
NC
C3067 1
C3059
0.47UF
20%
4V
CERM-X5R-1 2
201
H2
2
R3040
12 29
32 90
DQ0
DQ1
DQ2
DQ3
NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7
(SYM VER 2)
0.47UF
MEM_RESET_L
RESET*
FBGA
C3039
20%
2 4V
CERM-X5R-1
201
2
1%
1/20W
MF
1 201
0.47UF
ODT
MEM_A_ZQ & lt; 13 & gt; H9
2
12 28
90
MEM_A_CLK_P & lt; 1 & gt; 12
MEM_A_CLK_N & lt; 1 & gt; 12
A1
NC
A4
NC
A11
NC
F2
NC
F10
VSSQ
=PP1V5R1V35_S3_MEM_A
RAS*
CAS*
WE*
MEM_A_ODT & lt; 1 & gt; G2
90 32 29 12
12 28
90
12 28
90
90 32 29 28 12
F8
G8
NC
VSS
8 28 29
BA0
BA1
BA2
MEM_A_CLK_P & lt; 1 & gt; 12 29 32 90
MEM_A_CLK_N & lt; 1 & gt; 28 12 MEM_A_RAS_L
90 32 29
MEM_A_CAS_L
90 32 29 28 12
NC
MEM_A_WE_L
90 32 29 28 12
A1
A4
NC
A11
NC
F2
NC
F10
NC
H3 MEM_A_CS_L & lt; 1 & gt;
G10 MEM_A_CKE & lt; 1 & gt;
ZQ
PP0V75_S3_MEM_VREFDQ_A
PP0V75_S3_MEM_VREFCA_A
A15
MEM_A_BA & lt; 1 & gt;
MEM_A_BA & lt; 0 & gt;
MEM_A_BA & lt; 2 & gt;
28 12
90 32 29
12 28
90
ODT
MEM_A_ZQ & lt; 10 & gt; H9
C3058 1
VDD
32 29 28 12
RAS*
CAS*
WE*
MEM_A_ODT & lt; 1 & gt; G2
90 32 29 12
240
1
20%
4V
CERM-X5R-1 2
201
20%
2 4V
CERM-X5R-1
201
CK
CK*
VSS
A
90 32 29 28 12
F4
G4
H4
R3020
0.47UF
0.47UF
CS*
CKE
NC
C3057
C3049
32 29 28 12
90
27 28 29
90 32 29 28 12 30 31
B4
C8
C3
C9
E4
E9
D3
E8
DM/TDQS B8
NF/TDQS* A8
ODT
MEM_A_ZQ & lt; 12 & gt; H9
H10
1
90
N11
NC
N3 MEM_RESET_L
DQS C4
DQS* D4
RAS*
CAS*
WE*
MEM_A_ODT & lt; 1 & gt; G2
29 12
90 32
20%
4V
CERM-X5R-1 2
201
H2
BA0
BA1
BA2
MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L
90 32
28 12
29
90
28 12
32 29
0.47UF
VREFDQ E2
J3
K9
J4
VDDQ
OMIT_TABLE
A15
MEM_A_BA & lt; 1 & gt;
MEM_A_BA & lt; 0 & gt;
MEM_A_BA & lt; 2 & gt;
90
28 12
32 29
28 12
32 29
90
90
28 12
32 29
90
28 12
32 29
K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8
B10
C2
E3
E10
A3
A10
D8
G9
G3
K2
K10
M2
M10
VDD
MEM_A_A & lt; 0 & gt;
MEM_A_A & lt; 1 & gt;
MEM_A_A & lt; 2 & gt;
MEM_A_A & lt; 4 & gt;
MEM_A_A & lt; 3 & gt;
MEM_A_A & lt; 6 & gt;
MEM_A_A & lt; 5 & gt;
MEM_A_A & lt; 8 & gt;
MEM_A_A & lt; 7 & gt;
MEM_A_A & lt; 9 & gt;
MEM_A_A & lt; 10 & gt;
MEM_A_A & lt; 11 & gt;
MEM_A_A & lt; 12 & gt;
MEM_A_A & lt; 13 & gt;
MEM_A_A & lt; 14 & gt;
MEM_A_A & lt; 15 & gt;
89 33 29 28
=PP1V5R1V35_S3_MEM_A
1
20%
4V
CERM-X5R-1 2
201
MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L
29
90
90 32 29 28 12
12 28
90
90 32 29 28 12
CK
CK*
29 32 90
MEM_A_BA & lt; 1 & gt;
MEM_A_BA & lt; 0 & gt;
MEM_A_BA & lt; 2 & gt;
12 28
90
12 28
90 12
90 32 29 28
CS*
CKE
NC
VSSQ
89 33 29 28
8 28 29
0.47UF
BA0
BA1
BA2
12 28
90
12 28
90
2
R3010
B3
D2
B9
C10
D10
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
240
J3
K9
J4
DM/TDQS B8
NF/TDQS* A8
MEM_A_DQS_P & lt; 2 & gt;
MEM_A_DQS_N & lt; 2 & gt;
12 28
90
U3030
DDR3-1333
VREFCA J9
NC
VSS
12 29
32 90
MEM_A_CLK_P & lt; 1 & gt; 12
MEM_A_CLK_N & lt; 1 & gt; 12
32
A1
NC
A4
NC
A11
NC
F2
NC
F10
NC
12 29
32 90
2
R3000
90
28 12
32 29
F8
G8
ZQ
NC
VSSQ
90 32 29 28 12
H3 MEM_A_CS_L & lt; 1 & gt;
G10 MEM_A_CKE & lt; 1 & gt;
CK
CK*
ODT
H9
MEM_A_ZQ & lt; 9 & gt;
NC
CS*
CKE
RAS*
CAS*
WE*
MEM_A_ODT & lt; 1 & gt; G2
90 32 29 12
90 32 29 28 12
DQS C4
DQS* D4
12 28
90
VDDQ
OMIT_TABLE
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14
VREFDQ E2
VSS
F4
G4
H4
12 28
90
12 28
90 12
90 32 29 28
A15
MEM_A_BA & lt; 1 & gt;
MEM_A_BA & lt; 0 & gt;
MEM_A_BA & lt; 2 & gt;
MEM_A_DQS_P & lt; 1 & gt;
MEM_A_DQS_N & lt; 1 & gt;
32 29 28 12
90
27 28 29
90 32 29 28 12 30 31
MEM_A_DQ & lt; 21 & gt;
MEM_A_DQ & lt; 22 & gt;
MEM_A_DQ & lt; 17 & gt;
MEM_A_DQ & lt; 16 & gt;
MEM_A_DQ & lt; 19 & gt;
MEM_A_DQ & lt; 20 & gt;
MEM_A_DQ & lt; 23 & gt;
MEM_A_DQ & lt; 18 & gt;
K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8
1
20%
4V
CERM-X5R-1 2
H2
201
B3
D2
B9
C10
D10
NC
BA0
BA1
BA2
MEM_A_CLK_P & lt; 1 & gt; 12 29 32 90
MEM_A_CLK_N & lt; 1 & gt; 28 12 MEM_A_RAS_L
90 32 29
MEM_A_CAS_L
90 32 29 28 12
NC
MEM_A_WE_L
90 32 29 28 12
A1
A4
NC
A11
NC
F2
NC
F10
ZQ
12 29
32 90
J3
K9
J4
A3
A10
D8
G9
G3
K2
K10
M2
M10
VREFCA J9
NC
F8
G8
28 12
90 32 29
DM/TDQS B8
NF/TDQS* A8
12 28
90
12 28
90
B4
C8
C3
C9
E4
E9
D3
E8
MEM_A_A & lt; 0 & gt;
MEM_A_A & lt; 1 & gt;
MEM_A_A & lt; 2 & gt;
MEM_A_A & lt; 4 & gt;
MEM_A_A & lt; 3 & gt;
MEM_A_A & lt; 6 & gt;
MEM_A_A & lt; 5 & gt;
MEM_A_A & lt; 8 & gt;
MEM_A_A & lt; 7 & gt;
MEM_A_A & lt; 9 & gt;
MEM_A_A & lt; 10 & gt;
MEM_A_A & lt; 11 & gt;
MEM_A_A & lt; 12 & gt;
MEM_A_A & lt; 13 & gt;
MEM_A_A & lt; 14 & gt;
MEM_A_A & lt; 15 & gt;
1
0.47UF
B3
D2
B9
C10
D10
90 32 29 28 12
DQS C4
DQS* D4
12 28
90
DQ0
DQ1
DQ2
DQ3
NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7
(SYM VER 2)
90 32 29 28 12
MEM_RESET_L
RESET*
FBGA
VDD
N1
B10
C2
E3
E10
NC
H3 MEM_A_CS_L & lt; 1 & gt;
G10 MEM_A_CKE & lt; 1 & gt;
CK
CK*
ODT
90
28
12
90 32 29 28 12
CS*
CKE
RAS*
CAS*
WE*
28
12 28
90
12 28
90
12 28
90
U3020
DDR3-1333
NC
NC
NC
N11
NC
N3
H10
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
12
90
12
90 32 29 28
12 28
90
VDDQ
OMIT_TABLE
A3
A10
D8
G9
G3
K2
K10
M2
M10
MEM_A_DQS_P & lt; 0 & gt;
MEM_A_DQS_N & lt; 0 & gt;
12 28
90
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14
20%
4V
CERM-X5R-1 2
201
20%
4V
2 CERM-X5R-1
201
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
12 28
90
12 28
90
2
C
B
12 28
90
32 29 28 12
90
27 28 29
90 32 29 28 12 30 31
MEM_A_DQ & lt; 9 & gt;
MEM_A_DQ & lt; 14 & gt;
MEM_A_DQ & lt; 15 & gt;
MEM_A_DQ & lt; 10 & gt;
MEM_A_DQ & lt; 12 & gt;
MEM_A_DQ & lt; 8 & gt;
MEM_A_DQ & lt; 13 & gt;
MEM_A_DQ & lt; 11 & gt;
K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8
VREFCA J9
NC
H9
MEM_A_ZQ & lt; 8 & gt;
12 28
90
B4
C8
C3
C9
E4
E9
D3
E8
MEM_A_A & lt; 0 & gt;
MEM_A_A & lt; 1 & gt;
MEM_A_A & lt; 2 & gt;
MEM_A_A & lt; 4 & gt;
MEM_A_A & lt; 3 & gt;
MEM_A_A & lt; 6 & gt;
MEM_A_A & lt; 5 & gt;
MEM_A_A & lt; 8 & gt;
MEM_A_A & lt; 7 & gt;
MEM_A_A & lt; 9 & gt;
MEM_A_A & lt; 10 & gt;
MEM_A_A & lt; 11 & gt;
MEM_A_A & lt; 12 & gt;
MEM_A_A & lt; 13 & gt;
MEM_A_A & lt; 14 & gt;
MEM_A_A & lt; 15 & gt;
C3038
0.47UF
0.47UF
20%
4V
CERM-X5R-1 2
H2
201
8 28 29
C3037 1
C3029
B3
D2
B9
C10
D10
MEM_A_ODT & lt; 1 & gt; G2
29 12
90 32
12 28
90
DQ0
DQ1
DQ2
DQ3
NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7
(SYM VER 2)
90 32 29 28 12
MEM_RESET_L
RESET*
FBGA
VDD
N1
VREFDQ E2
28 12
32 29
90
12 28
90
U3010
DDR3-1333
NC
NC
NC
N11
NC
N3
H10
1
B3
D2
B9
C10
D10
90
12
29
DM/TDQS B8
NF/TDQS* A8
12 28
90
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14
1
0.47UF
B10
C2
E3
E10
F4
G4
H4
MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L
32
12
DQS C4
DQS* D4
12 28
90
VDDQ
OMIT_TABLE
A15
MEM_A_BA & lt; 1 & gt;
MEM_A_BA & lt; 0 & gt;
MEM_A_BA & lt; 2 & gt;
32 29 28 12
90
27 28 29
90 32 29 28 12 30 31
MEM_A_DQ & lt; 6 & gt;
MEM_A_DQ & lt; 0 & gt;
MEM_A_DQ & lt; 5 & gt;
MEM_A_DQ & lt; 7 & gt;
MEM_A_DQ & lt; 4 & gt;
MEM_A_DQ & lt; 2 & gt;
MEM_A_DQ & lt; 1 & gt;
MEM_A_DQ & lt; 3 & gt;
K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8
20%
4V
2 CERM-X5R-1
201
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
90
28
29
28
32
BA0
BA1
BA2
B4
C8
C3
C9
E4
E9
D3
E8
MEM_A_A & lt; 0 & gt;
MEM_A_A & lt; 1 & gt;
MEM_A_A & lt; 2 & gt;
MEM_A_A & lt; 4 & gt;
MEM_A_A & lt; 3 & gt;
MEM_A_A & lt; 6 & gt;
MEM_A_A & lt; 5 & gt;
MEM_A_A & lt; 8 & gt;
MEM_A_A & lt; 7 & gt;
MEM_A_A & lt; 9 & gt;
MEM_A_A & lt; 10 & gt;
MEM_A_A & lt; 11 & gt;
MEM_A_A & lt; 12 & gt;
MEM_A_A & lt; 13 & gt;
MEM_A_A & lt; 14 & gt;
MEM_A_A & lt; 15 & gt;
VREFCA J9
NC
90 32
28 12
29
90
28 12
32 29
J3
K9
J4
90 32 29 28 12
VREFDQ E2
12
29
90
29
12
N1
20%
4V
CERM-X5R-1 2
H2
201
C3028
20%
4V
CERM-X5R-1 2
201
89 33 29 28
=PP1V5R1V35_S3_MEM_A
0.47UF
0.47UF
1
PP0V75_S3_MEM_VREFDQ_A
PP0V75_S3_MEM_VREFCA_A
89 33 29 28
8 28 29
C3027 1
C3019
B3
D2
B9
C10
D10
28
32
90
32
28
VDD
H10
1
0.47UF
B3
D2
B9
C10
D10
90
28 12
32 29
C3018 1
B10
C2
E3
E10
90
28 12
32 29
DQ0
DQ1
DQ2
DQ3
NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7
(SYM VER 2)
20%
4V
2 CERM-X5R-1
201
MEM_RESET_L
RESET*
FBGA
1
20%
4V
CERM-X5R-1 2
201
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
28 12
32 29
90
90
28 12
32 29
90
28 12
32 29
U3000
DDR3-1333
NC
NC
NC
N11
NC
N3
=PP1V5R1V35_S3_MEM_A
0.47UF
0.47UF
A3
A10
D8
G9
G3
K2
K10
M2
M10
90
28 12
32 29
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14
C3017
C3009
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
28 12
32 29
90
90
28 12
32 29
90
28 12
32 29
VDDQ
OMIT_TABLE
A15
MEM_A_BA & lt; 1 & gt;
MEM_A_BA & lt; 0 & gt;
MEM_A_BA & lt; 2 & gt;
90
28 12
32 29
20%
4V
CERM-X5R-1 2
H2
201
VREFDQ E2
D
K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8
B10
C2
E3
E10
A3
A10
D8
G9
G3
K2
K10
M2
M10
VDD
MEM_A_A & lt; 0 & gt;
MEM_A_A & lt; 1 & gt;
MEM_A_A & lt; 2 & gt;
MEM_A_A & lt; 4 & gt;
MEM_A_A & lt; 3 & gt;
MEM_A_A & lt; 6 & gt;
MEM_A_A & lt; 5 & gt;
MEM_A_A & lt; 8 & gt;
MEM_A_A & lt; 7 & gt;
MEM_A_A & lt; 9 & gt;
MEM_A_A & lt; 10 & gt;
MEM_A_A & lt; 11 & gt;
MEM_A_A & lt; 12 & gt;
MEM_A_A & lt; 13 & gt;
MEM_A_A & lt; 14 & gt;
MEM_A_A & lt; 15 & gt;
90
28 12
32 29
1
0.47UF
89 33 29 28
2
PP0V75_S3_MEM_VREFDQ_A
PP0V75_S3_MEM_VREFCA_A
A3
A10
D8
G9
G3
K2
K10
M2
M10
C3008 1
3
89 33 29 28
8 28 29
VREFCA J9
NC
1
0.47UF
20%
4V
CERM-X5R-1 2
201
89 33 29 28
=PP1V5R1V35_S3_MEM_A
8 28 29
4
PP0V75_S3_MEM_VREFDQ_A
PP0V75_S3_MEM_VREFCA_A
B10
C2
E3
E10
=PP1V5R1V35_S3_MEM_A
C3007
5
89 33 29 28
A3
A10
D8
G9
G3
K2
K10
M2
M10
89 33 29 28
6
PP0V75_S3_MEM_VREFDQ_A
PP0V75_S3_MEM_VREFCA_A
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
7
89 33 29 28
VREFDQ E2
8
4.18.0
BRANCH
PAGE
30 OF 132
SHEET
29 OF 99
1
A
90 32 31 30 12
89 33 31 30
89 33 31 30
C3147
1%
1/20W
MF
1 201
30 12
32 31
90
90
30 12
32 31
90
30 12
32 31
30 12
32 31
90
90
30 12
32 31
30 12
32 31
90
90
30 12
32 31
90
30 12
32 31
F4
G4
H4
MEM_B_ODT & lt; 0 & gt; G2
30 12
90 32
VREFCA J9
NC
20%
4V
CERM-X5R-1 2
201
H2
BA0
BA1
BA2
MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L
90
30 12
32 31
0.47UF
VREFDQ E2
J3
K9
J4
VDDQ
OMIT_TABLE
A15
MEM_B_BA & lt; 0 & gt;
MEM_B_BA & lt; 1 & gt;
MEM_B_BA & lt; 2 & gt;
90
30 12
32 31
K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8
B10
C2
E3
E10
A3
A10
D8
G9
G3
K2
K10
M2
M10
VDD
MEM_B_A & lt; 0 & gt;
MEM_B_A & lt; 1 & gt;
MEM_B_A & lt; 2 & gt;
MEM_B_A & lt; 3 & gt;
MEM_B_A & lt; 4 & gt;
MEM_B_A & lt; 5 & gt;
MEM_B_A & lt; 6 & gt;
MEM_B_A & lt; 7 & gt;
MEM_B_A & lt; 8 & gt;
MEM_B_A & lt; 9 & gt;
MEM_B_A & lt; 10 & gt;
MEM_B_A & lt; 11 & gt;
MEM_B_A & lt; 12 & gt;
MEM_B_A & lt; 13 & gt;
MEM_B_A & lt; 14 & gt;
MEM_B_A & lt; 15 & gt;
MEM_B_ZQ & lt; 4 & gt;
H9
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14
U3140
DDR3-1333
FBGA
(SYM VER 2)
89 33 31 30
30 12
32 31 12 30 32 90
90
RESET*
H10
N1
NC
NC
NC
1
C3157
C3149
90 32 31 30 12
MEM_B_ZQ & lt; 2 & gt;
MEM_B_A & lt; 0 & gt;
MEM_B_A & lt; 1 & gt;
MEM_B_A & lt; 2 & gt;
MEM_B_A & lt; 3 & gt;
MEM_B_A & lt; 4 & gt;
MEM_B_A & lt; 5 & gt;
MEM_B_A & lt; 6 & gt;
MEM_B_A & lt; 7 & gt;
MEM_B_A & lt; 8 & gt;
MEM_B_A & lt; 9 & gt;
MEM_B_A & lt; 10 & gt;
MEM_B_A & lt; 11 & gt;
MEM_B_A & lt; 12 & gt;
MEM_B_A & lt; 13 & gt;
MEM_B_A & lt; 14 & gt;
MEM_B_A & lt; 15 & gt;
32 31 30 12
90
90 32 31 30 12
DQ0
DQ1
DQ2
DQ3
NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7
B4
C8
C3
C9
E4
E9
D3
E8
DQS C4
DQS* D4
MEM_B_DQ & lt; 32 & gt;
MEM_B_DQ & lt; 33 & gt;
MEM_B_DQ & lt; 34 & gt;
MEM_B_DQ & lt; 35 & gt;
MEM_B_DQ & lt; 36 & gt;
MEM_B_DQ & lt; 37 & gt;
MEM_B_DQ & lt; 38 & gt;
MEM_B_DQ & lt; 39 & gt; 90
12 31
90
30 12
90 32 31
30
90 32
30
90 32
12
31
12
31
30 12
90 32 31
30 12
90 32 31
30 12
90 32 31
30 12
32 31
90
30 12
32 31
MEM_B_DQS_P & lt; 4 & gt;
MEM_B_DQS_N & lt; 4 & gt;
30 12
32 31
90
90 32 31 30 12
DM/TDQS B8
NF/TDQS* A8
90 32 31 30 12
NC
90 32 31 30 12
CS*
CKE
CK
CK*
RAS*
CAS*
WE*
ODT
H3 MEM_B_CS_L & lt; 0 & gt;
G10 MEM_B_CKE & lt; 0 & gt;
F8
G8
NC
ZQ
VSS
VSSQ
30 12
90 32 31
30 12
90 32 31
MEM_B_CLK_P & lt; 0 & gt;
MEM_B_CLK_N & lt; 0 & gt;
90
A1
NC
A4
NC
A11
NC
F2
NC
F10
K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8
J3
K9
J4
MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L
90 32 31 30 12
90 32 31 30 12
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14
F4
G4
H4
VDDQ
OMIT_TABLE
MEM_B_ZQ & lt; 5 & gt;
U3150
DQ0
DQ1
DQ2
DQ3
NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7
(SYM VER 2)
1%
1/20W
MF
1 201
=PP1V5R1V35_S3_MEM_B
30 12
32 31
90
30 12
90 32 31
N1
NC
NC
NC
VDD
MEM_B_A & lt; 0 & gt;
MEM_B_A & lt; 1 & gt;
MEM_B_A & lt; 2 & gt;
MEM_B_A & lt; 3 & gt;
MEM_B_A & lt; 4 & gt;
MEM_B_A & lt; 5 & gt;
MEM_B_A & lt; 6 & gt;
MEM_B_A & lt; 7 & gt;
MEM_B_A & lt; 8 & gt;
MEM_B_A & lt; 9 & gt;
MEM_B_A & lt; 10 & gt;
MEM_B_A & lt; 11 & gt;
MEM_B_A & lt; 12 & gt;
MEM_B_A & lt; 13 & gt;
MEM_B_A & lt; 14 & gt;
MEM_B_A & lt; 15 & gt;
B4
C8
C3
C9
E4
E9
D3
E8
32 31 30 12
90
MEM_B_DQ & lt; 40 & gt;
MEM_B_DQ & lt; 41 & gt;
MEM_B_DQ & lt; 42 & gt;
MEM_B_DQ & lt; 43 & gt;
MEM_B_DQ & lt; 44 & gt;
MEM_B_DQ & lt; 45 & gt;
MEM_B_DQ & lt; 46 & gt;
MEM_B_DQ & lt; 47 & gt; 90
30 12
90 32 31
30 12
90 32 31
30 12
90 32 31
30 12
90 32 31
30 12
90 32 31
30 12
90 32 31
30 12
90 32 31
30 12
32 31
90
30 12
32 31
MEM_B_DQS_P & lt; 5 & gt;
MEM_B_DQS_N & lt; 5 & gt;
30 12
32 31
90
90 32 31 30 12
DM/TDQS B8
NF/TDQS* A8
90 32 31 30 12
NC
90 32 31 30 12
H3 MEM_B_CS_L & lt; 0 & gt;
G10 MEM_B_CKE & lt; 0 & gt;
CK
CK*
F8
G8
NC
ZQ
30 12
90 32 31
30 12
90 32 31
MEM_B_CLK_P & lt; 0 & gt;
MEM_B_CLK_N & lt; 0 & gt;
90
A1
NC
A4
NC
A11
NC
F2
NC
F10
K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8
J3
K9
J4
MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L
30 12
32 31
90 32 31 30 12
90 32 31 30 12
F4
G4
H4
MEM_B_ODT & lt; 0 & gt; G2
90 32 30 12
MEM_B_ZQ & lt; 6 & gt;
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14
90 32 31 30 12
MEM_B_ZQ & lt; 3 & gt;
240
1%
1/20W
MF
1 201
H9
B4
C8
C3
C9
E4
E9
D3
E8
2.2UF
20%
10V
X5R-CERM 2
402
C3101
1
VREFCA J9
NC
VREFDQ E2
B10
C2
E3
E10
ODT
2.2UF
1
2.2UF
20%
10V
X5R-CERM 2
402
F8
G8
20%
10V
X5R-CERM 2
402
8
C3141
2.2UF
1
C3111
1
C3120 1
C3121 1
20%
10V
X5R-CERM 2
402
20%
10V
X5R-CERM 2
402
20%
10V
X5R-CERM 2
402
2.2UF
20%
10V
X5R-CERM 2
402
20%
10V
X5R-CERM 2
402
C3150
2.2UF
12 31 90
12 31 90
12 31 90
12 31 90
12 31 90
12 31
90
12 31
90
12 30 32 90
12 30 32 90
30 32 90
30 32 90
A1
NC
A4
NC
A11
NC
F2
NC
F10
NC
ZQ
240
NC
VSSQ
1%
1/20W
MF
1 201
VDDQ
OMIT_TABLE
U3160
1
H10
N1
NC
NC
NC
1
DQ0
DQ1
DQ2
DQ3
NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7
(SYM VER 2)
B4
C8
C3
C9
E4
E9
D3
E8
DQS C4
DQS* D4
20%
4V
CERM-X5R-1 2
201
20%
2 4V
CERM-X5R-1
201
VDD
MEM_B_A & lt; 0 & gt;
MEM_B_A & lt; 1 & gt;
MEM_B_A & lt; 2 & gt;
MEM_B_A & lt; 3 & gt;
MEM_B_A & lt; 4 & gt;
MEM_B_A & lt; 5 & gt;
MEM_B_A & lt; 6 & gt;
MEM_B_A & lt; 7 & gt;
MEM_B_A & lt; 8 & gt;
MEM_B_A & lt; 9 & gt;
MEM_B_A & lt; 10 & gt;
MEM_B_A & lt; 11 & gt;
MEM_B_A & lt; 12 & gt;
MEM_B_A & lt; 13 & gt;
MEM_B_A & lt; 14 & gt;
MEM_B_A & lt; 15 & gt;
32 31 30 12
90
MEM_B_DQ & lt; 48 & gt;
MEM_B_DQ & lt; 49 & gt;
MEM_B_DQ & lt; 50 & gt;
MEM_B_DQ & lt; 51 & gt;
MEM_B_DQ & lt; 52 & gt;
MEM_B_DQ & lt; 53 & gt;
MEM_B_DQ & lt; 54 & gt;
MEM_B_DQ & lt; 55 & gt; 90
30 12
90 32 31
30 12
90 32 31
30
90 32
30
90 32
12
31
12
31
30 12
90 32 31
30 12
90 32 31
30 12
90 32 31
30 12
32 31
90
30 12
32 31
MEM_B_DQS_P & lt; 6 & gt;
MEM_B_DQS_N & lt; 6 & gt;
30 12
32 31
90
90 32 31 30 12
NC
90 32 31 30 12
CS*
CKE
CK
CK*
RAS*
CAS*
WE*
H3 MEM_B_CS_L & lt; 0 & gt;
G10 MEM_B_CKE & lt; 0 & gt;
F8
G8
NC
ZQ
VSS
30
90 32
30
90 32
30
32
MEM_B_CLK_P & lt; 0 & gt;
MEM_B_CLK_N & lt; 0 & gt;
90
A1
NC
A4
NC
A11
NC
F2
NC
F10
K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14
MEM_B_BA & lt; 0 & gt;
MEM_B_BA & lt; 1 & gt;
MEM_B_BA & lt; 2 & gt;
32 31 30 12
90 32 31 30 12
DM/TDQS B8
NF/TDQS* A8
C3178
0.47UF
0.47UF
90
N11
NC
N3 MEM_RESET_L
J3
K9
J4
MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L
30 12
32 31
90 32 31 30 12
90 32 31 30 12
F4
G4
H4
MEM_B_ODT & lt; 0 & gt; G2
90 32 30 12
VDDQ
OMIT_TABLE
BA0
BA1
BA2
12
31
12
31
12
31 12 30 32 90
90
MEM_B_ZQ & lt; 7 & gt;
H9
U3170
FBGA
1
H10
N1
C3179
0.47UF
20%
4V
CERM-X5R-1 2
201
H2
DQ0
DQ1
DQ2
DQ3
NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7
(SYM VER 2)
1
0.47UF
RESET*
DDR3-1333
20%
2 4V
CERM-X5R-1
201
NC
NC
NC
N11
NC
N3 MEM_RESET_L
B4
C8
C3
C9
E4
E9
D3
E8
DQS C4
DQS* D4
DM/TDQS B8
NF/TDQS* A8
A15
MEM_B_DQ & lt; 56 & gt;
MEM_B_DQ & lt; 57 & gt;
MEM_B_DQ & lt; 58 & gt;
MEM_B_DQ & lt; 59 & gt;
MEM_B_DQ & lt; 60 & gt;
MEM_B_DQ & lt; 61 & gt;
MEM_B_DQ & lt; 62 & gt;
MEM_B_DQ & lt; 63 & gt;
MEM_B_DQS_P & lt; 7 & gt;
MEM_B_DQS_N & lt; 7 & gt;
H3 MEM_B_CS_L & lt; 0 & gt;
G10 MEM_B_CKE & lt; 0 & gt;
CK
CK*
ODT
F8
G8
NC
ZQ
VSS
27 28 29 30 31
12 31 90
12 31 90
12 31 90
12 31 90
12 31 90
12 31 90
12 31 90
B
12 31 90
12 31
90
12 31
90
NC
CS*
CKE
RAS*
CAS*
WE*
NC
VSSQ
8 30 31
C3177 1
C3169
90 32 31 30 12
ODT
H9
89 33 31 30
=PP1V5R1V35_S3_MEM_B
RESET*
FBGA
PP0V75_S3_MEM_VREFDQ_B
PP0V75_S3_MEM_VREFCA_B
89 33 31 30
20%
4V
CERM-X5R-1 2
201
H2
C
12 30 32 90
12 30 32 90
MEM_B_CLK_P & lt; 0 & gt; 12
MEM_B_CLK_N & lt; 0 & gt; 12
30 32 90
30 32 90
A1
NC
A4
NC
A11
NC
F2
NC
F10
VSSQ
NC
2
R3160
240
1%
1/20W
MF
1 201
R3170
240
1%
1/20W
MF
1 201
2.2UF
2.2UF
C3130 1 C3131
2.2UF
20%
10V
X5R-CERM 2
402
1
1
2.2UF
C3103
1
0.1UF
20%
10V
X5R-CERM 2
402
10%
2 6.3V
X5R
201
C3104
1
0.1UF
10%
2 6.3V
X5R
201
C3105
1
0.1UF
10%
2 6.3V
X5R
201
C3113
1
0.1UF
10%
2 6.3V
X5R
201
C3114
1
0.1UF
10%
2 6.3V
X5R
201
C3115
1
0.1UF
10%
2 6.3V
X5R
201
C3123
1
0.1UF
10%
2 6.3V
X5R
201
C3124
1
0.1UF
10%
2 6.3V
X5R
201
C3125
1
0.1UF
10%
2 6.3V
X5R
201
C3133
1
0.1UF
10%
6.3V
2 X5R
201
C3134
1
0.1UF
10%
6.3V
2 X5R
201
C3135
0.1UF
SYNC_DATE=01/13/2012
PAGE TITLE
DDR3 SDRAM Bank B (1 OF 2)
10%
6.3V
2 X5R
201
DRAWING NUMBER
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
2.2UF
12 31 90
MEM_B_CLK_P & lt; 0 & gt; 12
MEM_B_CLK_N & lt; 0 & gt; 12
051-9589
1
20%
10V
X5R-CERM 2
402
C3151
1
2.2UF
20%
10V
X5R-CERM 2
402
7
C3160 1
C3161 1
2.2UF
2.2UF
20%
10V
X5R-CERM 2
402
20%
10V
X5R-CERM 2
402
C3170 1 C3171
2.2UF
20%
10V
X5R-CERM 2
402
2.2UF
1
20%
10V
X5R-CERM 2
402
6
1
C3143
0.1UF
10%
2 6.3V
X5R
201
1
C3144
0.1UF
10%
2 6.3V
X5R
201
1
C3145
0.1UF
10%
2 6.3V
X5R
201
5
1
C3153
0.1UF
10%
2 6.3V
X5R
201
1
C3154
0.1UF
10%
2 6.3V
X5R
201
1
C3155
0.1UF
10%
2 6.3V
X5R
201
1
C3163
0.1UF
10%
2 6.3V
X5R
201
4
1
C3164
0.1UF
10%
2 6.3V
X5R
201
1
C3165
0.1UF
10%
2 6.3V
X5R
201
1
C3173
0.1UF
10%
6.3V
2 X5R
201
3
1
C3174
0.1UF
10%
6.3V
2 X5R
201
1
C3175
0.1UF
10%
6.3V
2 X5R
201
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
2
SIZE
D
REVISION
R
C3140 1
12 31 90
NC
CK
CK*
RAS*
CAS*
WE*
D
27 28 29 30 31
12 31 90
SDRAM Bypassing (NOTE: 2x 2.2uF and 3x 0.1uF per chip)
8 30 31
C3110
MEM_B_DQS_P & lt; 3 & gt;
MEM_B_DQS_N & lt; 3 & gt;
H3 MEM_B_CS_L & lt; 0 & gt;
G10 MEM_B_CKE & lt; 0 & gt;
SYNC_MASTER=D2_KEPLER
C3100 1
MEM_B_DQ & lt; 27 & gt;
MEM_B_DQ & lt; 25 & gt;
MEM_B_DQ & lt; 26 & gt;
MEM_B_DQ & lt; 29 & gt;
MEM_B_DQ & lt; 30 & gt;
MEM_B_DQ & lt; 28 & gt;
MEM_B_DQ & lt; 31 & gt;
MEM_B_DQ & lt; 24 & gt;
CS*
CKE
VSS
R3130
2
R3150
F4
G4
H4
MEM_B_ODT & lt; 0 & gt; G2
90 32 30 12
0.47UF
DDR3-1333
NC
VSSQ
MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L
30
90
90 32 31 30 12
N1
DM/TDQS B8
NF/TDQS* A8
30 32 90
8 30 31
BA0
BA1
BA2
30 12
32 31 12 30 32 90
90
BA0
BA1
BA2
NC
NC
NC
N11
NC
N3
H10
DQS C4
DQS* D4
A15
PP0V75_S3_MEM_VREFDQ_B
PP0V75_S3_MEM_VREFCA_B
A15
MEM_B_BA & lt; 0 & gt;
MEM_B_BA & lt; 1 & gt;
MEM_B_BA & lt; 2 & gt;
32 31 30 12
J3
K9
J4
DQ0
DQ1
DQ2
DQ3
NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7
(SYM VER 2)
0.47UF
MEM_RESET_L
RESET*
FBGA
NC
VSSQ
C3168
20%
4V
CERM-X5R-1 2
201
20%
2 4V
CERM-X5R-1
201
A3
A10
D8
G9
G3
K2
K10
M2
M10
VREFCA J9
NC
VREFDQ E2
B10
C2
E3
E10
A3
A10
D8
G9
G3
K2
K10
M2
M10
NC
30 12
90 32 31
MEM_B_CLK_P & lt; 0 & gt; 12
MEM_B_CLK_N & lt; 0 & gt; 12
32
A1
NC
A4
NC
A11
NC
F2
NC
F10
0.47UF
0.47UF
90
N11
NC
N3 MEM_RESET_L
DQS C4
DQS* D4
VSS
B3
D2
B9
C10
D10
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
240
30 12
90 32 31
30 12
32 31
90
30 12
32 31
90 32 31 30 12
F8
G8
C3167 1
C3159
90 32 31 30 12
FBGA
ODT
H9
H10
1
2
R3140
NC
H3 MEM_B_CS_L & lt; 0 & gt;
G10 MEM_B_CKE & lt; 0 & gt;
ZQ
89 33 31 30
CS*
CKE
NC
2
RAS*
CAS*
WE*
89 33 31 30
20%
4V
CERM-X5R-1 2
201
H2
RESET*
DDR3-1333
RAS*
CAS*
WE*
MEM_B_ODT & lt; 0 & gt; G2
90 32 30 12
30 12
90 32 31
90 32 31 30 12
CK
CK*
=PP1V5R1V35_S3_MEM_B
BA0
BA1
BA2
30 12
32 31 12 30 32 90
90
30 12
32 31
30 12
90 32 31
U3130
DDR3-1333
C3139
20%
2 4V
CERM-X5R-1
201
2
1%
1/20W
MF
1 201
0.47UF
MEM_B_BA & lt; 0 & gt;
MEM_B_BA & lt; 1 & gt;
MEM_B_BA & lt; 2 & gt;
30 12
90 32 31
MEM_B_DQS_P & lt; 2 & gt;
MEM_B_DQS_N & lt; 2 & gt;
CS*
CKE
ODT
H9
8 30 31
A15
MEM_B_BA & lt; 0 & gt;
MEM_B_BA & lt; 1 & gt;
MEM_B_BA & lt; 2 & gt;
32 31 30 12
DM/TDQS B8
NF/TDQS* A8
VSS
C3158 1
VDD
90
N11
NC
N3 MEM_RESET_L
MEM_B_ODT & lt; 0 & gt; G2
90 32 30 12
240
1
20%
4V
CERM-X5R-1 2
201
20%
2 4V
CERM-X5R-1
201
F4
G4
H4
R3120
0.47UF
0.47UF
MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L
30 12
90 32 31
90 32 31 30 12
PP0V75_S3_MEM_VREFDQ_B
PP0V75_S3_MEM_VREFCA_B
=PP1V5R1V35_S3_MEM_B
C3148 1
BA0
BA1
BA2
30 12
90 32 31
12 31
90
90 32 31 30 12
NC
VSSQ
89 33 31 30
8 30 31
1
20%
4V
CERM-X5R-1 2
201
J3
K9
J4
DQS C4
DQS* D4
30 12
90 32 31
2
240
0.47UF
90 32
30 12
31
90
30 12
32 31
NC
30 12
90 32 31
30 12
90 32 31
MEM_B_CLK_P & lt; 0 & gt;
MEM_B_CLK_N & lt; 0 & gt;
A1
NC
A4
NC
A11
NC
F2
NC
F10
ZQ
PP0V75_S3_MEM_VREFDQ_B
PP0V75_S3_MEM_VREFCA_B
=PP1V5R1V35_S3_MEM_B
90
12
31
F8
G8
VREFCA J9
NC
1%
1/20W
MF
1 201
90 32
30 12
90
31
32 31
30 12
90 32
30 12
31
90
30 12
32 31
90 32 31 30 12
H3 MEM_B_CS_L & lt; 0 & gt;
G10 MEM_B_CKE & lt; 0 & gt;
CK
CK*
VSS
R3110
B3
D2
B9
C10
D10
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
240
32
12
NC
CS*
CKE
NC
VSSQ
90 32 31 30 12
2
R3100
90
30
31
30
32
DM/TDQS B8
NF/TDQS* A8
ODT
H9
MEM_B_ZQ & lt; 1 & gt;
30 12
32 31
90
90 32 31 30 12
RAS*
CAS*
WE*
MEM_B_ODT & lt; 0 & gt; G2
90 32 30 12
MEM_B_DQS_P & lt; 1 & gt;
MEM_B_DQS_N & lt; 1 & gt;
MEM_B_DQ & lt; 18 & gt;
MEM_B_DQ & lt; 20 & gt;
MEM_B_DQ & lt; 19 & gt;
MEM_B_DQ & lt; 16 & gt;
MEM_B_DQ & lt; 23 & gt;
MEM_B_DQ & lt; 21 & gt;
MEM_B_DQ & lt; 22 & gt;
MEM_B_DQ & lt; 17 & gt; 90
VREFCA J9
NC
NC
F4
G4
H4
MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L
30 12
32 31
90 32 31 30 12
A1
NC
A4
NC
A11
NC
F2
NC
F10
ZQ
30 12
32 31 12 30 32 90
90
30 12
90 32 31
30 12
32 31
90
30 12
32 31
A15
MEM_B_BA & lt; 0 & gt;
MEM_B_BA & lt; 1 & gt;
MEM_B_BA & lt; 2 & gt;
30 12
90 32 31
(SYM VER 2)
B4
C8
C3
C9
E4
E9
D3
E8
VREFDQ E2
ODT
MEM_B_CLK_P & lt; 0 & gt;
MEM_B_CLK_N & lt; 0 & gt;
90
BA0
BA1
BA2
30 12
90 32 31
32 31 30 12
90
90 32 31 30 12
DQ0
DQ1
DQ2
DQ3
NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7
VDDQ
OMIT_TABLE
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14
1
20%
4V
CERM-X5R-1 2
H2
201
B3
D2
B9
C10
D10
RAS*
CAS*
WE*
30 12
90 32 31
J3
K9
J4
30 12
90 32 31
30 12
90 32 31
MEM_RESET_L
RESET*
FBGA
K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8
1
0.47UF
B3
D2
B9
C10
D10
CK
CK*
F8
G8
30 12
90 32 31
30 12
90 32 31
U3120
DDR3-1333
MEM_B_A & lt; 0 & gt;
MEM_B_A & lt; 1 & gt;
MEM_B_A & lt; 2 & gt;
MEM_B_A & lt; 3 & gt;
MEM_B_A & lt; 4 & gt;
MEM_B_A & lt; 5 & gt;
MEM_B_A & lt; 6 & gt;
MEM_B_A & lt; 7 & gt;
MEM_B_A & lt; 8 & gt;
MEM_B_A & lt; 9 & gt;
MEM_B_A & lt; 10 & gt;
MEM_B_A & lt; 11 & gt;
MEM_B_A & lt; 12 & gt;
MEM_B_A & lt; 13 & gt;
MEM_B_A & lt; 14 & gt;
MEM_B_A & lt; 15 & gt;
90 32 31 30 12
B10
C2
E3
E10
90 32 31 30 12
H3 MEM_B_CS_L & lt; 0 & gt;
G10 MEM_B_CKE & lt; 0 & gt;
30 12
90 32 31
VDD
N1
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
NC
CS*
CKE
DQS C4
DQS* D4
MEM_B_DQ & lt; 14 & gt;
MEM_B_DQ & lt; 9 & gt;
MEM_B_DQ & lt; 11 & gt;
MEM_B_DQ & lt; 13 & gt;
MEM_B_DQ & lt; 10 & gt;
MEM_B_DQ & lt; 12 & gt;
MEM_B_DQ & lt; 15 & gt;
MEM_B_DQ & lt; 8 & gt; 90
NC
NC
NC
N11
NC
N3
H10
A3
A10
D8
G9
G3
K2
K10
M2
M10
90 32 31 30 12
(SYM VER 2)
B4
C8
C3
C9
E4
E9
D3
E8
VDDQ
OMIT_TABLE
20%
4V
CERM-X5R-1 2
201
20%
2 4V
CERM-X5R-1
201
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
DM/TDQS B8
NF/TDQS* A8
DQ0
DQ1
DQ2
DQ3
NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14
VREFCA J9
NC
MEM_B_DQS_P & lt; 0 & gt;
MEM_B_DQS_N & lt; 0 & gt;
32 31 30 12
90
90 32 31 30 12
FBGA
K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8
C3138
0.47UF
0.47UF
20%
4V
CERM-X5R-1 2
H2
201
8 30 31
C3137 1
C3129
B3
D2
B9
C10
D10
90 32
30 12
31
90
30 12
32 31
MEM_RESET_L
RESET*
MEM_B_A & lt; 0 & gt;
MEM_B_A & lt; 1 & gt;
MEM_B_A & lt; 2 & gt;
MEM_B_A & lt; 3 & gt;
MEM_B_A & lt; 4 & gt;
MEM_B_A & lt; 5 & gt;
MEM_B_A & lt; 6 & gt;
MEM_B_A & lt; 7 & gt;
MEM_B_A & lt; 8 & gt;
MEM_B_A & lt; 9 & gt;
MEM_B_A & lt; 10 & gt;
MEM_B_A & lt; 11 & gt;
MEM_B_A & lt; 12 & gt;
MEM_B_A & lt; 13 & gt;
MEM_B_A & lt; 14 & gt;
MEM_B_A & lt; 15 & gt;
90 32 31 30 12
VREFDQ E2
30 12
90 32 31
90 32 31 30 12
VSS
A
12
31
12
31
2
C
B
30
90 32
30
90 32
VDD
N1
1
B3
D2
B9
C10
D10
H9
MEM_B_ZQ & lt; 0 & gt;
30 12
90 32 31
12 31
90
30 12
90 32 31
U3110
DDR3-1333
NC
NC
NC
N11
NC
N3
H10
1
0.47UF
B10
C2
E3
E10
MEM_B_ODT & lt; 0 & gt; G2
30 12
90 32
DQS C4
DQS* D4
30 12
90 32 31
VDDQ
OMIT_TABLE
A15
MEM_B_BA & lt; 0 & gt;
MEM_B_BA & lt; 1 & gt;
MEM_B_BA & lt; 2 & gt;
32 31 30 12
90
MEM_B_DQ & lt; 6 & gt;
MEM_B_DQ & lt; 1 & gt;
MEM_B_DQ & lt; 3 & gt;
MEM_B_DQ & lt; 5 & gt;
MEM_B_DQ & lt; 2 & gt;
MEM_B_DQ & lt; 4 & gt;
MEM_B_DQ & lt; 7 & gt;
MEM_B_DQ & lt; 0 & gt;
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14
VREFDQ E2
90
30 12
32 31
(SYM VER 2)
B4
C8
C3
C9
E4
E9
D3
E8
K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8
20%
2 4V
CERM-X5R-1
201
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
F4
G4
H4
MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L
90
30 12
32 31
VREFCA J9
NC
BA0
BA1
BA2
MEM_B_A & lt; 0 & gt;
MEM_B_A & lt; 1 & gt;
MEM_B_A & lt; 2 & gt;
MEM_B_A & lt; 3 & gt;
MEM_B_A & lt; 4 & gt;
MEM_B_A & lt; 5 & gt;
MEM_B_A & lt; 6 & gt;
MEM_B_A & lt; 7 & gt;
MEM_B_A & lt; 8 & gt;
MEM_B_A & lt; 9 & gt;
MEM_B_A & lt; 10 & gt;
MEM_B_A & lt; 11 & gt;
MEM_B_A & lt; 12 & gt;
MEM_B_A & lt; 13 & gt;
MEM_B_A & lt; 14 & gt;
MEM_B_A & lt; 15 & gt;
90 32 31 30 12
20%
4V
CERM-X5R-1 2
H2
201
C3128
20%
4V
CERM-X5R-1 2
201
89 33 31 30
=PP1V5R1V35_S3_MEM_B
0.47UF
0.47UF
1
PP0V75_S3_MEM_VREFDQ_B
PP0V75_S3_MEM_VREFCA_B
89 33 31 30
8 30 31
C3127 1
C3119
B3
D2
B9
C10
D10
30 12
32 31
90
90
30 12
32 31
J3
K9
J4
N1
1
0.47UF
B3
D2
B9
C10
D10
30 12
32 31
90
90
30 12
32 31
VDD
H10
90 32 31 30 12
DQ0
DQ1
DQ2
DQ3
NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7
C3118 1
B10
C2
E3
E10
30 12
32 31
90
90
30 12
32 31
90
30 12
32 31
20%
2 4V
CERM-X5R-1
201
MEM_RESET_L
RESET*
FBGA
1
20%
4V
CERM-X5R-1 2
201
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
90
30 12
32 31
U3100
DDR3-1333
NC
NC
NC
N11
NC
N3
=PP1V5R1V35_S3_MEM_B
0.47UF
0.47UF
A3
A10
D8
G9
G3
K2
K10
M2
M10
90 32
30 12
31
90
30 12
32 31
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14
C3117
C3109
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
90 32
30 12
31
90
30 12
32 31
VDDQ
OMIT_TABLE
A15
MEM_B_BA & lt; 0 & gt;
MEM_B_BA & lt; 1 & gt;
MEM_B_BA & lt; 2 & gt;
90 32
30 12
90
31
32 31
30 12
20%
4V
CERM-X5R-1 2
H2
201
VREFDQ E2
D
K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8
B10
C2
E3
E10
A3
A10
D8
G9
G3
K2
K10
M2
M10
VDD
MEM_B_A & lt; 0 & gt;
MEM_B_A & lt; 1 & gt;
MEM_B_A & lt; 2 & gt;
MEM_B_A & lt; 3 & gt;
MEM_B_A & lt; 4 & gt;
MEM_B_A & lt; 5 & gt;
MEM_B_A & lt; 6 & gt;
MEM_B_A & lt; 7 & gt;
MEM_B_A & lt; 8 & gt;
MEM_B_A & lt; 9 & gt;
MEM_B_A & lt; 10 & gt;
MEM_B_A & lt; 11 & gt;
MEM_B_A & lt; 12 & gt;
MEM_B_A & lt; 13 & gt;
MEM_B_A & lt; 14 & gt;
MEM_B_A & lt; 15 & gt;
90 32
30 12
31
90
30 12
32 31
1
0.47UF
89 33 31 30
2
PP0V75_S3_MEM_VREFDQ_B
PP0V75_S3_MEM_VREFCA_B
A3
A10
D8
G9
G3
K2
K10
M2
M10
C3108 1
3
89 33 31 30
8 30 31
VREFCA J9
NC
1
0.47UF
20%
4V
CERM-X5R-1 2
201
89 33 31 30
=PP1V5R1V35_S3_MEM_B
8 30 31
4
PP0V75_S3_MEM_VREFDQ_B
PP0V75_S3_MEM_VREFCA_B
B10
C2
E3
E10
=PP1V5R1V35_S3_MEM_B
C3107
5
89 33 31 30
A3
A10
D8
G9
G3
K2
K10
M2
M10
89 33 31 30
6
PP0V75_S3_MEM_VREFDQ_B
PP0V75_S3_MEM_VREFCA_B
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
7
89 33 31 30
VREFDQ E2
8
4.18.0
BRANCH
PAGE
31 OF 132
SHEET
30 OF 99
1
A
90 32 31 30 12
C3248 1
90
30
31
30
32
90
12
31
90
32 31
30 12
90 32
30 12
31
90
30 12
32 31
F4
G4
H4
VREFCA J9
NC
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14
U3240
DDR3-1333
FBGA
(SYM VER 2)
RESET*
DQ0
DQ1
DQ2
DQ3
NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7
N1
NC
NC
NC
B4
C8
C3
C9
E4
E9
D3
E8
DM/TDQS B8
NF/TDQS* A8
VDD
MEM_B_DQ & lt; 33 & gt;
MEM_B_DQ & lt; 32 & gt;
MEM_B_DQ & lt; 35 & gt;
MEM_B_DQ & lt; 34 & gt;
MEM_B_DQ & lt; 39 & gt;
MEM_B_DQ & lt; 38 & gt;
MEM_B_DQ & lt; 37 & gt;
MEM_B_DQ & lt; 36 & gt;
MEM_B_DQS_P & lt; 4 & gt;
MEM_B_DQS_N & lt; 4 & gt;
12 30
90
12 30
90
12 30
90
12 30
90
12 30
90
12 30
90
90 32 31 30 12
F8
G8
VSSQ
12 30
90
90 32 31 30 12
NC
CK
CK*
ZQ
12 30
90
12 30
90 12
90 32 31 30
H3 MEM_B_CS_L & lt; 1 & gt;
G10 MEM_B_CKE & lt; 1 & gt;
NC
12 30
90
12 31
32 90
12 31
32 90
MEM_B_CLK_P & lt; 1 & gt; 12
MEM_B_CLK_N & lt; 1 & gt; 12
32
A1
NC
A4
NC
A11
NC
F2
NC
F10
K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8
J3
K9
J4
90 32 31 30 12
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14
F4
G4
H4
VDDQ
OMIT_TABLE
U3250
1%
1/20W
MF
1 201
=PP1V5R1V35_S3_MEM_B
FBGA
DQ0
DQ1
DQ2
DQ3
NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7
(SYM VER 2)
1
12 31
32 90
12 31
32 90
MEM_B_CLK_P & lt; 1 & gt; 12
MEM_B_CLK_N & lt; 1 & gt; 12
32
H10
N1
NC
NC
NC
VDD
90
N11
NC
N3 MEM_RESET_L
32 31 30 12
90
27 28 29
90 32 31 30 12 30 31
B4
C8
C3
C9
E4
E9
D3
E8
DQS C4
DQS* D4
DM/TDQS B8
NF/TDQS* A8
MEM_B_DQ & lt; 41 & gt;
MEM_B_DQ & lt; 40 & gt;
MEM_B_DQ & lt; 43 & gt;
MEM_B_DQ & lt; 42 & gt;
MEM_B_DQ & lt; 47 & gt;
MEM_B_DQ & lt; 46 & gt;
MEM_B_DQ & lt; 45 & gt;
MEM_B_DQ & lt; 44 & gt;
12 30
90
12 30
90
12 30
90
12 30
90
30 12
90 32 31
12 30
90
12 30
90
12 30
90
MEM_B_DQS_P & lt; 5 & gt;
MEM_B_DQS_N & lt; 5 & gt;
90 32 31 30 12
NC
90 32 31 30 12
CS*
CKE
H3 MEM_B_CS_L & lt; 1 & gt;
G10 MEM_B_CKE & lt; 1 & gt;
CK
CK*
F8
G8
ZQ
NC
NC
VSS
12 30
90
12 30
90 12
90 32 31 30
12 31
32 90
12 31
32 90
MEM_B_CLK_P & lt; 1 & gt; 12
MEM_B_CLK_N & lt; 1 & gt; 12
32
A1
NC
A4
NC
A11
NC
F2
NC
F10
MEM_B_A & lt; 0 & gt;
MEM_B_A & lt; 1 & gt;
MEM_B_A & lt; 2 & gt;
MEM_B_A & lt; 4 & gt;
MEM_B_A & lt; 3 & gt;
MEM_B_A & lt; 6 & gt;
MEM_B_A & lt; 5 & gt;
MEM_B_A & lt; 8 & gt;
MEM_B_A & lt; 7 & gt;
MEM_B_A & lt; 9 & gt;
MEM_B_A & lt; 10 & gt;
MEM_B_A & lt; 11 & gt;
MEM_B_A & lt; 12 & gt;
MEM_B_A & lt; 13 & gt;
MEM_B_A & lt; 14 & gt;
MEM_B_A & lt; 15 & gt;
K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8
90 32 31 30 12
J3
K9
J4
90 32 31 30 12
90 32 31 30 12
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14
F4
G4
H4
VDDQ
OMIT_TABLE
U3260
1%
1/20W
MF
1 201
240
1%
1/20W
MF
1 201
2.2UF
20%
10V
X5R-CERM 2
402
C3201
1
2.2UF
1
2.2UF
20%
10V
X5R-CERM 2
402
20%
10V
X5R-CERM 2
402
8
C3241
2.2UF
1
C3211
1
C3220 1
C3221 1
20%
10V
X5R-CERM 2
402
20%
10V
X5R-CERM 2
402
20%
10V
X5R-CERM 2
402
2.2UF
20%
10V
X5R-CERM 2
402
20%
10V
X5R-CERM 2
402
C3250
2.2UF
12 30 90
12 30 90
12 30 90
12 30
90
12 30
90
12 31 32 90
12 31 32 90
31 32 90
31 32 90
FBGA
DQ0
DQ1
DQ2
DQ3
NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7
(SYM VER 2)
H10
N1
NC
NC
NC
1
DM/TDQS B8
NF/TDQS* A8
VDD
MEM_B_DQ & lt; 49 & gt;
MEM_B_DQ & lt; 48 & gt;
MEM_B_DQ & lt; 51 & gt;
MEM_B_DQ & lt; 50 & gt;
MEM_B_DQ & lt; 55 & gt;
MEM_B_DQ & lt; 54 & gt;
MEM_B_DQ & lt; 53 & gt;
MEM_B_DQ & lt; 52 & gt;
30 12
90 32 31
12 30
90
12 30
90
12 30
90
12 30
90
12 30
90
MEM_B_DQS_P & lt; 6 & gt;
MEM_B_DQS_N & lt; 6 & gt;
12 30
90
12 30
90 12
90 32 31 30
90 32 31 30 12
NC
90 32 31 30 12
CK
CK*
VSS
12 30
90
12 30
90
F8
G8
12 31
32 90
30 12
90 32 31
MEM_B_A & lt; 0 & gt;
MEM_B_A & lt; 1 & gt;
MEM_B_A & lt; 2 & gt;
MEM_B_A & lt; 4 & gt;
MEM_B_A & lt; 3 & gt;
MEM_B_A & lt; 6 & gt;
MEM_B_A & lt; 5 & gt;
MEM_B_A & lt; 8 & gt;
MEM_B_A & lt; 7 & gt;
MEM_B_A & lt; 9 & gt;
MEM_B_A & lt; 10 & gt;
MEM_B_A & lt; 11 & gt;
MEM_B_A & lt; 12 & gt;
MEM_B_A & lt; 13 & gt;
MEM_B_A & lt; 14 & gt;
MEM_B_A & lt; 15 & gt;
K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14
MEM_B_BA & lt; 1 & gt;
MEM_B_BA & lt; 0 & gt;
MEM_B_BA & lt; 2 & gt;
32 31 30 12
H3 MEM_B_CS_L & lt; 1 & gt;
G10 MEM_B_CKE & lt; 1 & gt;
NC
20%
4V
CERM-X5R-1 2
201
20%
2 4V
CERM-X5R-1
201
CS*
CKE
ZQ
VREFCA J9
NC
VREFDQ E2
B10
C2
E3
E10
C3278
0.47UF
0.47UF
32 31 30 12
90
27 28 29
90 32 31 30 12 30 31
B4
C8
C3
C9
E4
E9
D3
E8
J3
K9
J4
F4
G4
H4
H10
N1
C3279
0.47UF
20%
2 4V
CERM-X5R-1
201
NC
NC
NC
N11
NC
N3 MEM_RESET_L
B4
C8
C3
C9
E4
E9
D3
E8
DQS C4
DQS* D4
DM/TDQS B8
NF/TDQS* A8
MEM_B_DQ & lt; 57 & gt;
MEM_B_DQ & lt; 56 & gt;
MEM_B_DQ & lt; 59 & gt;
MEM_B_DQ & lt; 58 & gt;
MEM_B_DQ & lt; 63 & gt;
MEM_B_DQ & lt; 62 & gt;
MEM_B_DQ & lt; 61 & gt;
MEM_B_DQ & lt; 60 & gt;
MEM_B_DQS_P & lt; 7 & gt;
MEM_B_DQS_N & lt; 7 & gt;
H3 MEM_B_CS_L & lt; 1 & gt;
G10 MEM_B_CKE & lt; 1 & gt;
CK
CK*
F8
G8
ZQ
NC
VSS
27 28 29 30 31
12 30 90
12 30 90
12 30 90
12 30 90
12 30 90
12 30 90
12 30 90
B
12 30 90
12 30
90
12 30
90
NC
CS*
CKE
ODT
MEM_B_ZQ & lt; 15 & gt; H9
1
20%
4V
CERM-X5R-1 2
201
H2
DQ0
DQ1
DQ2
DQ3
NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7
(SYM VER 2)
1
0.47UF
RESET*
FBGA
RAS*
CAS*
WE*
NC
VSSQ
U3270
DDR3-1333
A15
MEM_B_ODT & lt; 1 & gt; G2
90 32 31 12
VDDQ
OMIT_TABLE
BA0
BA1
BA2
MEM_B_CLK_P & lt; 1 & gt; 12 31 32 90
MEM_B_CLK_N & lt; 1 & gt; 30 12 MEM_B_RAS_L
90 32 31
MEM_B_CAS_L
90 32 31 30 12
NC
MEM_B_WE_L
90 32 31 30 12
A1
A4
NC
A11
NC
F2
NC
F10
8 30 31
C3277 1
C3269
90
N11
NC
N3 MEM_RESET_L
DQS C4
DQS* D4
ODT
MEM_B_ZQ & lt; 14 & gt; H9
1
C
12 31 32 90
12 31 32 90
MEM_B_CLK_P & lt; 1 & gt; 12
MEM_B_CLK_N & lt; 1 & gt; 12
31 32 90
31 32 90
A1
NC
A4
NC
A11
NC
F2
NC
F10
VSSQ
NC
2
R3260
240
1%
1/20W
MF
1 201
R3270
240
1%
1/20W
MF
1 201
2.2UF
2.2UF
C3230 1 C3231
2.2UF
20%
10V
X5R-CERM 2
402
1
1
2.2UF
C3203
1
0.1UF
20%
10V
X5R-CERM 2
402
10%
2 6.3V
X5R
201
C3204
1
0.1UF
10%
2 6.3V
X5R
201
C3205
1
0.1UF
10%
2 6.3V
X5R
201
C3213
1
0.1UF
10%
2 6.3V
X5R
201
C3214
1
0.1UF
10%
2 6.3V
X5R
201
C3215
1
0.1UF
10%
2 6.3V
X5R
201
C3223
1
0.1UF
10%
2 6.3V
X5R
201
C3224
1
0.1UF
10%
2 6.3V
X5R
201
C3225
1
0.1UF
10%
2 6.3V
X5R
201
C3233
1
0.1UF
10%
6.3V
2 X5R
201
C3234
1
0.1UF
10%
6.3V
2 X5R
201
C3235
0.1UF
SYNC_DATE=01/13/2012
PAGE TITLE
DDR3 SDRAM Bank B (2 OF 2)
10%
6.3V
2 X5R
201
DRAWING NUMBER
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
2.2UF
12 30 90
MEM_B_CLK_P & lt; 1 & gt; 12
MEM_B_CLK_N & lt; 1 & gt; 12
051-9589
1
20%
10V
X5R-CERM 2
402
C3251
1
2.2UF
20%
10V
X5R-CERM 2
402
7
C3260 1
C3261 1
2.2UF
2.2UF
20%
10V
X5R-CERM 2
402
20%
10V
X5R-CERM 2
402
C3270 1 C3271
2.2UF
20%
10V
X5R-CERM 2
402
2.2UF
1
20%
10V
X5R-CERM 2
402
6
1
C3243
0.1UF
10%
2 6.3V
X5R
201
1
C3244
0.1UF
10%
2 6.3V
X5R
201
1
C3245
0.1UF
10%
2 6.3V
X5R
201
5
1
C3253
0.1UF
10%
2 6.3V
X5R
201
1
C3254
0.1UF
10%
2 6.3V
X5R
201
1
C3255
0.1UF
10%
2 6.3V
X5R
201
1
C3263
0.1UF
10%
2 6.3V
X5R
201
4
1
C3264
0.1UF
10%
2 6.3V
X5R
201
1
C3265
0.1UF
10%
2 6.3V
X5R
201
1
C3273
0.1UF
10%
6.3V
2 X5R
201
3
1
C3274
0.1UF
10%
6.3V
2 X5R
201
1
C3275
0.1UF
10%
6.3V
2 X5R
201
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
2
SIZE
D
REVISION
R
C3240 1
12 30 90
SDRAM Bypassing (NOTE: 2x 2.2uF and 3x 0.1uF per chip)
8 30 31
C3210
12 30 90
NC
SYNC_MASTER=D2_KEPLER
C3200 1
12 30 90
PP0V75_S3_MEM_VREFDQ_B
PP0V75_S3_MEM_VREFCA_B
89 33 31 30
2
R3250
12 30 90
A1
NC
A4
NC
A11
NC
F2
NC
F10
VSSQ
89 33 31 30
20%
4V
CERM-X5R-1 2
201
H2
RESET*
DDR3-1333
NC
VSSQ
D
27 28 29 30 31
NC
F8
G8
NC
VSS
0.47UF
RAS*
CAS*
WE*
MEM_B_ODT & lt; 1 & gt; G2
90 32 31 12
MEM_B_DQS_P & lt; 3 & gt;
MEM_B_DQS_N & lt; 3 & gt;
H3 MEM_B_CS_L & lt; 1 & gt;
G10 MEM_B_CKE & lt; 1 & gt;
ZQ
=PP1V5R1V35_S3_MEM_B
BA0
BA1
BA2
MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L
MEM_B_DQ & lt; 25 & gt;
MEM_B_DQ & lt; 27 & gt;
MEM_B_DQ & lt; 29 & gt;
MEM_B_DQ & lt; 26 & gt;
MEM_B_DQ & lt; 24 & gt;
MEM_B_DQ & lt; 31 & gt;
MEM_B_DQ & lt; 28 & gt;
MEM_B_DQ & lt; 30 & gt;
CK
CK*
ODT
MEM_B_ZQ & lt; 11 & gt; H9
B4
C8
C3
C9
E4
E9
D3
E8
CS*
CKE
RAS*
CAS*
WE*
MEM_B_ODT & lt; 1 & gt; G2
90 32 31 12
8 30 31
31 32 90
31
90
F4
G4
H4
N1
DM/TDQS B8
NF/TDQS* A8
A15
PP0V75_S3_MEM_VREFDQ_B
PP0V75_S3_MEM_VREFCA_B
A15
MEM_B_BA & lt; 1 & gt;
MEM_B_BA & lt; 0 & gt;
MEM_B_BA & lt; 2 & gt;
32 31 30 12
MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L
31
90
90 32 31 30 12
NC
NC
NC
N11
NC
N3
H10
DQS C4
DQS* D4
31 32 90
240
C3268
20%
4V
CERM-X5R-1 2
201
20%
2 4V
CERM-X5R-1
201
BA0
BA1
BA2
R3230
0.47UF
0.47UF
J3
K9
J4
DQ0
DQ1
DQ2
DQ3
NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7
(SYM VER 2)
0.47UF
MEM_RESET_L
RESET*
FBGA
NC
C3267 1
C3259
A3
A10
D8
G9
G3
K2
K10
M2
M10
VREFCA J9
NC
VREFDQ E2
B10
C2
E3
E10
A3
A10
D8
G9
G3
K2
K10
M2
M10
89 33 31 30
20%
4V
CERM-X5R-1 2
201
H2
RESET*
DDR3-1333
ODT
MEM_B_ZQ & lt; 13 & gt; H9
B3
D2
B9
C10
D10
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
240
90 32 31 30 12
A1
NC
A4
NC
A11
NC
F2
NC
F10
VSSQ
89 33 31 30
2
R3240
NC
U3230
DDR3-1333
C3239
20%
2 4V
CERM-X5R-1
201
2
1%
1/20W
MF
1 201
0.47UF
RAS*
CAS*
WE*
MEM_B_ODT & lt; 1 & gt; G2
90 32 31 12
12 30
90
90 32 31 30 12
F8
G8
NC
VSS
12 30
90
H3 MEM_B_CS_L & lt; 1 & gt;
G10 MEM_B_CKE & lt; 1 & gt;
ZQ
=PP1V5R1V35_S3_MEM_B
BA0
BA1
BA2
MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L
90 32 31 30 12
ODT
MEM_B_ZQ & lt; 10 & gt; H9
12 30
90
12 30
90
12 30
90
12 30
90
12 30
90 12
90 32 31 30
CK
CK*
RAS*
CAS*
WE*
MEM_B_ODT & lt; 1 & gt; G2
90 32 31 12
8 30 31
31 32 90
31
90
F4
G4
H4
PP0V75_S3_MEM_VREFDQ_B
PP0V75_S3_MEM_VREFCA_B
A15
MEM_B_BA & lt; 1 & gt;
MEM_B_BA & lt; 0 & gt;
MEM_B_BA & lt; 2 & gt;
32 31 30 12
90
2
A
90 32 31 30 12
C3258 1
MEM_B_A & lt; 0 & gt;
MEM_B_A & lt; 1 & gt;
MEM_B_A & lt; 2 & gt;
MEM_B_A & lt; 4 & gt;
MEM_B_A & lt; 3 & gt;
MEM_B_A & lt; 6 & gt;
MEM_B_A & lt; 5 & gt;
MEM_B_A & lt; 8 & gt;
MEM_B_A & lt; 7 & gt;
MEM_B_A & lt; 9 & gt;
MEM_B_A & lt; 10 & gt;
MEM_B_A & lt; 11 & gt;
MEM_B_A & lt; 12 & gt;
MEM_B_A & lt; 13 & gt;
MEM_B_A & lt; 14 & gt;
MEM_B_A & lt; 15 & gt;
32 31 30 12
MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L
31
90
90 32 31 30 12
12 30
90
VDDQ
OMIT_TABLE
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14
MEM_B_BA & lt; 1 & gt;
MEM_B_BA & lt; 0 & gt;
MEM_B_BA & lt; 2 & gt;
12 30
90
MEM_B_DQS_P & lt; 2 & gt;
MEM_B_DQS_N & lt; 2 & gt;
CS*
CKE
31 32 90
240
1
20%
4V
CERM-X5R-1 2
201
20%
2 4V
CERM-X5R-1
201
BA0
BA1
BA2
R3220
0.47UF
0.47UF
CS*
CKE
VSS
C3257
C3249
90
N11
NC
N3 MEM_RESET_L
DQS C4
DQS* D4
ODT
MEM_B_ZQ & lt; 12 & gt; H9
H10
1
90 32 31 30 12
RAS*
CAS*
WE*
MEM_B_ODT & lt; 1 & gt; G2
31 12
90 32
20%
4V
CERM-X5R-1 2
201
H2
BA0
BA1
BA2
MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L
90 32
30 12
31
90
30 12
32 31
30 12
32 31
90
0.47UF
VREFDQ E2
J3
K9
J4
VDDQ
OMIT_TABLE
A15
MEM_B_BA & lt; 1 & gt;
MEM_B_BA & lt; 0 & gt;
MEM_B_BA & lt; 2 & gt;
32
12
K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8
B10
C2
E3
E10
A3
A10
D8
G9
G3
K2
K10
M2
M10
VDD
MEM_B_A & lt; 0 & gt;
MEM_B_A & lt; 1 & gt;
MEM_B_A & lt; 2 & gt;
MEM_B_A & lt; 4 & gt;
MEM_B_A & lt; 3 & gt;
MEM_B_A & lt; 6 & gt;
MEM_B_A & lt; 5 & gt;
MEM_B_A & lt; 8 & gt;
MEM_B_A & lt; 7 & gt;
MEM_B_A & lt; 9 & gt;
MEM_B_A & lt; 10 & gt;
MEM_B_A & lt; 11 & gt;
MEM_B_A & lt; 12 & gt;
MEM_B_A & lt; 13 & gt;
MEM_B_A & lt; 14 & gt;
MEM_B_A & lt; 15 & gt;
89 33 31 30
=PP1V5R1V35_S3_MEM_B
1
20%
4V
CERM-X5R-1 2
201
J3
K9
J4
DM/TDQS B8
NF/TDQS* A8
NC
VSSQ
89 33 31 30
8 30 31
0.47UF
90 32
30 12
90
31
32 31
30 12
12 31
32 90
MEM_B_CLK_P & lt; 1 & gt; 12
MEM_B_CLK_N & lt; 1 & gt; 12
32
A1
NC
A4
NC
A11
NC
F2
NC
F10
VREFCA J9
NC
C3247
1%
1/20W
MF
1 201
PP0V75_S3_MEM_VREFDQ_B
PP0V75_S3_MEM_VREFCA_B
=PP1V5R1V35_S3_MEM_B
30 12
32 31
90
90
30 12
32 31
90
30 12
32 31
12 31
32 90
DQS C4
DQS* D4
12 30
90
2
240
VREFDQ E2
89 33 31 30
89 33 31 30
90 32
30 12
31
90
30 12
32 31
90 32 31 30 12
F8
G8
NC
VSS
R3210
B3
D2
B9
C10
D10
1%
1/20W
MF
1 201
90
30 12
32 31
NC
H3 MEM_B_CS_L & lt; 1 & gt;
G10 MEM_B_CKE & lt; 1 & gt;
ZQ
NC
VSSQ
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
240
90
30 12
32 31
ODT
H9
MEM_B_ZQ & lt; 9 & gt;
90 32 31 30 12
2
R3200
90
30 12
32 31
MEM_B_ODT & lt; 1 & gt; G2
90 32 31 12
12 30
90 12
90 32 31 30
CK
CK*
RAS*
CAS*
WE*
12 30
90
32 31 30 12
90
27 28 29
90 32 31 30 12 30 31
MEM_B_DQ & lt; 20 & gt;
MEM_B_DQ & lt; 18 & gt;
MEM_B_DQ & lt; 16 & gt;
MEM_B_DQ & lt; 19 & gt;
MEM_B_DQ & lt; 17 & gt;
MEM_B_DQ & lt; 22 & gt;
MEM_B_DQ & lt; 21 & gt;
MEM_B_DQ & lt; 23 & gt;
K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8
VREFCA J9
NC
NC
F4
G4
H4
MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L
31
90
MEM_B_DQS_P & lt; 1 & gt;
MEM_B_DQS_N & lt; 1 & gt;
A15
MEM_B_BA & lt; 1 & gt;
MEM_B_BA & lt; 0 & gt;
MEM_B_BA & lt; 2 & gt;
12 30
90
12 30
90
CS*
CKE
31 32 90
90 32 31 30 12
A1
NC
A4
NC
A11
NC
F2
NC
F10
ZQ
VSS
MEM_B_CLK_P & lt; 1 & gt; 12
MEM_B_CLK_N & lt; 1 & gt; 12
32
BA0
BA1
BA2
12 30
90
B4
C8
C3
C9
E4
E9
D3
E8
MEM_B_A & lt; 0 & gt;
MEM_B_A & lt; 1 & gt;
MEM_B_A & lt; 2 & gt;
MEM_B_A & lt; 4 & gt;
MEM_B_A & lt; 3 & gt;
MEM_B_A & lt; 6 & gt;
MEM_B_A & lt; 5 & gt;
MEM_B_A & lt; 8 & gt;
MEM_B_A & lt; 7 & gt;
MEM_B_A & lt; 9 & gt;
MEM_B_A & lt; 10 & gt;
MEM_B_A & lt; 11 & gt;
MEM_B_A & lt; 12 & gt;
MEM_B_A & lt; 13 & gt;
MEM_B_A & lt; 14 & gt;
MEM_B_A & lt; 15 & gt;
VREFDQ E2
ODT
12 31
32 90
A15
J3
K9
J4
12 30
90
12 30
90
DQ0
DQ1
DQ2
DQ3
NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7
(SYM VER 2)
90 32 31 30 12
MEM_RESET_L
RESET*
FBGA
VDD
N1
1
20%
4V
CERM-X5R-1 2
H2
201
B3
D2
B9
C10
D10
CK
CK*
F8
G8
12 31
32 90
12 30
90
U3220
DDR3-1333
NC
NC
NC
N11
NC
N3
H10
1
0.47UF
B3
D2
B9
C10
D10
90 32 31 30 12
DM/TDQS B8
NF/TDQS* A8
12 30
90
VDDQ
OMIT_TABLE
B10
C2
E3
E10
NC
H3 MEM_B_CS_L & lt; 1 & gt;
G10 MEM_B_CKE & lt; 1 & gt;
DQS C4
DQS* D4
12 30
90
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
12 30
90 12
90 32 31 30
90 32 31 30 12
CS*
CKE
RAS*
CAS*
WE*
12 30
90
32 31 30 12
90
27 28 29
90 32 31 30 12 30 31
MEM_B_DQ & lt; 9 & gt;
MEM_B_DQ & lt; 14 & gt;
MEM_B_DQ & lt; 13 & gt;
MEM_B_DQ & lt; 11 & gt;
MEM_B_DQ & lt; 8 & gt;
MEM_B_DQ & lt; 15 & gt;
MEM_B_DQ & lt; 12 & gt;
MEM_B_DQ & lt; 10 & gt;
K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8
A3
A10
D8
G9
G3
K2
K10
M2
M10
MEM_B_DQS_P & lt; 0 & gt;
MEM_B_DQS_N & lt; 0 & gt;
B4
C8
C3
C9
E4
E9
D3
E8
MEM_B_A & lt; 0 & gt;
MEM_B_A & lt; 1 & gt;
MEM_B_A & lt; 2 & gt;
MEM_B_A & lt; 4 & gt;
MEM_B_A & lt; 3 & gt;
MEM_B_A & lt; 6 & gt;
MEM_B_A & lt; 5 & gt;
MEM_B_A & lt; 8 & gt;
MEM_B_A & lt; 7 & gt;
MEM_B_A & lt; 9 & gt;
MEM_B_A & lt; 10 & gt;
MEM_B_A & lt; 11 & gt;
MEM_B_A & lt; 12 & gt;
MEM_B_A & lt; 13 & gt;
MEM_B_A & lt; 14 & gt;
MEM_B_A & lt; 15 & gt;
20%
4V
CERM-X5R-1 2
201
20%
4V
2 CERM-X5R-1
201
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
12 30
90
30 12
90 32 31
DQ0
DQ1
DQ2
DQ3
NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7
(SYM VER 2)
90 32 31 30 12
MEM_RESET_L
RESET*
FBGA
VDD
N1
VREFCA J9
NC
12 30
90
12 30
90
2
C
B
12 30
90
30 12
90 32 31
U3210
DDR3-1333
NC
NC
NC
N11
NC
N3
H10
C3238
0.47UF
0.47UF
20%
4V
CERM-X5R-1 2
H2
201
8 30 31
C3237 1
C3229
B3
D2
B9
C10
D10
DM/TDQS B8
NF/TDQS* A8
30 12
90 32 31
VDDQ
OMIT_TABLE
VREFDQ E2
DQS C4
DQS* D4
12 30
90
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14
1
B3
D2
B9
C10
D10
H9
MEM_B_ZQ & lt; 8 & gt;
32 31 30 12
90
27 28 29
90 32 31 30 12 30 31
MEM_B_DQ & lt; 1 & gt;
MEM_B_DQ & lt; 6 & gt;
MEM_B_DQ & lt; 5 & gt;
MEM_B_DQ & lt; 3 & gt;
MEM_B_DQ & lt; 0 & gt;
MEM_B_DQ & lt; 7 & gt;
MEM_B_DQ & lt; 4 & gt;
MEM_B_DQ & lt; 2 & gt;
K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8
1
0.47UF
B10
C2
E3
E10
MEM_B_ODT & lt; 1 & gt; G2
31 12
90 32
B4
C8
C3
C9
E4
E9
D3
E8
MEM_B_A & lt; 0 & gt;
MEM_B_A & lt; 1 & gt;
MEM_B_A & lt; 2 & gt;
MEM_B_A & lt; 4 & gt;
MEM_B_A & lt; 3 & gt;
MEM_B_A & lt; 6 & gt;
MEM_B_A & lt; 5 & gt;
MEM_B_A & lt; 8 & gt;
MEM_B_A & lt; 7 & gt;
MEM_B_A & lt; 9 & gt;
MEM_B_A & lt; 10 & gt;
MEM_B_A & lt; 11 & gt;
MEM_B_A & lt; 12 & gt;
MEM_B_A & lt; 13 & gt;
MEM_B_A & lt; 14 & gt;
MEM_B_A & lt; 15 & gt;
MEM_B_BA & lt; 1 & gt;
MEM_B_BA & lt; 0 & gt;
MEM_B_BA & lt; 2 & gt;
90 32 31 30 12
20%
4V
2 CERM-X5R-1
201
B3
D2
B9
C10
D10
30 12
32 31
90
N1
20%
4V
CERM-X5R-1 2
H2
201
C3228
20%
4V
CERM-X5R-1 2
201
89 33 31 30
=PP1V5R1V35_S3_MEM_B
0.47UF
0.47UF
1
PP0V75_S3_MEM_VREFDQ_B
PP0V75_S3_MEM_VREFCA_B
89 33 31 30
8 30 31
C3227 1
C3219
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
F4
G4
H4
MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L
90 32
30 12
31
90
30 12
32 31
VREFCA J9
NC
BA0
BA1
BA2
VDD
H10
1
0.47UF
B3
D2
B9
C10
D10
90 32
30 12
31
90
30 12
32 31
J3
K9
J4
C3218 1
B10
C2
E3
E10
90 32
30 12
31
90
30 12
32 31
90
32 31
30 12
DQ0
DQ1
DQ2
DQ3
NF/DQ4
NF/DQ5
NF/DQ6
NF/DQ7
(SYM VER 2)
20%
2 4V
CERM-X5R-1
201
MEM_RESET_L
RESET*
FBGA
1
20%
4V
CERM-X5R-1 2
201
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
90 32
30 12
90
31
32 31
30 12
U3200
DDR3-1333
NC
NC
NC
N11
NC
N3
=PP1V5R1V35_S3_MEM_B
0.47UF
0.47UF
A3
A10
D8
G9
G3
K2
K10
M2
M10
30 12
32 31
90
90
30 12
32 31
90
30 12
32 31
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC*
A13
A14
C3217
C3209
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
90
30 12
32 31
VDDQ
OMIT_TABLE
A15
MEM_B_BA & lt; 1 & gt;
MEM_B_BA & lt; 0 & gt;
MEM_B_BA & lt; 2 & gt;
90
30 12
32 31
30 12
32 31
90
90
30 12
32 31
90
30 12
32 31
20%
4V
CERM-X5R-1 2
H2
201
VREFDQ E2
D
K4
L8
L4
K3
L9
L3
M9
M3
N9
M4
H8
M8
K8
N4
N8
J8
B10
C2
E3
E10
A3
A10
D8
G9
G3
K2
K10
M2
M10
VDD
MEM_B_A & lt; 0 & gt;
MEM_B_A & lt; 1 & gt;
MEM_B_A & lt; 2 & gt;
MEM_B_A & lt; 4 & gt;
MEM_B_A & lt; 3 & gt;
MEM_B_A & lt; 6 & gt;
MEM_B_A & lt; 5 & gt;
MEM_B_A & lt; 8 & gt;
MEM_B_A & lt; 7 & gt;
MEM_B_A & lt; 9 & gt;
MEM_B_A & lt; 10 & gt;
MEM_B_A & lt; 11 & gt;
MEM_B_A & lt; 12 & gt;
MEM_B_A & lt; 13 & gt;
MEM_B_A & lt; 14 & gt;
MEM_B_A & lt; 15 & gt;
90
30 12
32 31
1
0.47UF
89 33 31 30
2
PP0V75_S3_MEM_VREFDQ_B
PP0V75_S3_MEM_VREFCA_B
A3
A10
D8
G9
G3
K2
K10
M2
M10
C3208 1
3
89 33 31 30
8 30 31
VREFCA J9
NC
1
0.47UF
20%
4V
CERM-X5R-1 2
201
89 33 31 30
=PP1V5R1V35_S3_MEM_B
8 30 31
4
PP0V75_S3_MEM_VREFDQ_B
PP0V75_S3_MEM_VREFCA_B
B10
C2
E3
E10
=PP1V5R1V35_S3_MEM_B
C3207
5
89 33 31 30
A3
A10
D8
G9
G3
K2
K10
M2
M10
89 33 31 30
6
PP0V75_S3_MEM_VREFDQ_B
PP0V75_S3_MEM_VREFCA_B
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
7
89 33 31 30
VREFDQ E2
8
4.18.0
BRANCH
PAGE
32 OF 132
SHEET
31 OF 99
1
A
8
7
6
5
4
3
2
1
JEDEC 4.20.18 Unbuffered SODIMM Raw Card F spec recommends 36 Ohm term to VTT for CS,CKE,ODT and 36 Ohm for BA,A,RAS,CAS,WE
90 29 12
IN
90 28 12
IN
90 29 28 12
IN
90 29 28 12
IN
90 29 28 12
IN
90 29 28 12
D
IN
90 28 12
IN
90 29 28 12
IN
90 29 28 12
90 29 28 12
90 29 28 12
IN
IN
IN
90 29 28 12
IN
90 29 28 12
IN
90 29 28 12
IN
90 29 12
IN
90 29 28 12
IN
90 29 28 12
IN
90 29 28 12
IN
90 29 28 12
IN
90 29 28 12
IN
90 29 28 12
90 29 28 12
IN
IN
MEM_A_CS_L & lt; 1 & gt;
MEM_A_CKE & lt; 0 & gt;
MEM_A_A & lt; 0 & gt;
MEM_A_A & lt; 7 & gt;
MEM_A_A & lt; 5 & gt;
MEM_A_BA & lt; 0 & gt;
MEM_A_ODT & lt; 0 & gt;
MEM_A_A & lt; 15 & gt;
RP3305
RP3301
RP3302
RP3306
RP3303
RP3302
RP3301
RP3305
8
=PP0V75_S0_MEM_VTT_A
36
36
36
36
36
36
36
36
1
8
4
5
5% 1/32W
4X0201
2
7
5% 1/32W
4X0201
2
7
5% 1/32W
4X0201
1
8
5% 1/32W
4X0201
1
8
5% 1/32W
4X0201
2
7
5% 1/32W
4X0201
2
7
5% 1/32W
4X0201
5% 1/32W
1
0.47UF
5% 1/32W
4X0201
1
8
5% 1/32W
4X0201
4X0201
20%
4V
2 CERM-X5R-1
201
3
5
5% 1/32W
4X0201
3
6
5% 1/32W
4X0201
3
6
5% 1/32W
4X0201
4
5
5% 1/32W
4X0201
1
8
5% 1/32W
4X0201
2
7
5% 1/32W
4X0201
4
5
5% 1/32W
4X0201
3
6
5% 1/32W
4X0201
8
5% 1/32W
4X0201
5
5% 1/32W
4X0201
90 29 12
IN
IN
90 29 28 12
IN
90 29 28 12
IN
90 28 12
IN
90 29 28 12
IN
MEM_A_A & lt; 13 & gt;
MEM_A_CKE & lt; 1 & gt;
MEM_A_A & lt; 10 & gt;
MEM_A_CAS_L
MEM_A_CS_L & lt; 0 & gt;
MEM_A_A & lt; 11 & gt;
RP3307
RP3304
RP3304
RP3301
RP3301
RP3306
4X0201
1
4
36
36
36
36
36
36
D
6
4
36
36
36
36
36
36
36
36
36
36
36
6
5% 1/32W
MEM_A_A & lt; 12 & gt;
MEM_A_A & lt; 9 & gt;
MEM_A_BA & lt; 2 & gt;
MEM_A_ODT & lt; 1 & gt;
MEM_A_A & lt; 4 & gt;
MEM_A_RAS_L
MEM_A_A & lt; 1 & gt;
MEM_A_WE_L
MEM_A_A & lt; 6 & gt;
MEM_A_A & lt; 2 & gt;
MEM_A_A & lt; 3 & gt;
RP3305
RP3306
RP3302
RP3304
RP3303
RP3304
RP3307
RP3302
RP3303
RP3307
RP3305
1
7
3
RP3303 36
RP3307 36
RP3306 36
4X0201
2
5% 1/32W
MEM_A_BA & lt; 1 & gt;
MEM_A_A & lt; 14 & gt;
MEM_A_A & lt; 8 & gt;
C3302
0.47UF
1
C3304
0.47UF
20%
2 4V
CERM-X5R-1
201
1
C3306
1
20%
2 4V
CERM-X5R-1
201
C3303
0.47UF
20%
4V
2 CERM-X5R-1
201
1
C3305
0.47UF
20%
2 4V
CERM-X5R-1
201
1
0.47UF
1
90 29 28 12
C3300
20%
2 4V
CERM-X5R-1
201
C3307
0.47UF
20%
2 4V
CERM-X5R-1
201
C3308
0.47UF
4
5
2
7
5% 1/32W
4X0201
4
5
5% 1/32W
4X0201
3
6
5% 1/32W
4X0201
1
8
5% 1/32W
4X0201
3
6
5% 1/32W
4X0201
5% 1/32W
4X0201
20%
4V
2 CERM-X5R-1
201
1
C3310
0.47UF
20%
4V
2 CERM-X5R-1
201
C
8
90 30 12
IN
90 31 30 12
IN
90 31 30 12
IN
90 31 30 12
IN
90 31 30 12
IN
90 31 30 12
IN
MEM Clock Termination
90 30 12
Place RC end termination after last DRAM
Place Source Cterm at neckdown at first DRAM
90 31 30 12
90 31 30 12
IN
IN
IN
90 31 30 12
90 28 12
IN
MEM_A_CLK_N & lt; 0 & gt;
C3350
1
3.3PF
201
B
90 28 12
IN
MEM_A_CLK_P & lt; 0 & gt;
2
MEM_A_CLK0_TERM_R
90 31 30 12
IN
0.1UF
5%
1/20W
MF
201
1
5%
PLACE_NEAR=U2900.F7:3.2mm 25V
CERM 2
30
IN
C3351
R3350
90 31 30 12
IN
1
2
90 31 12
90 31 30 12
10%
6.3V
X5R
201
1
90 29 12
IN
MEM_A_CLK_N & lt; 1 & gt;
C3355
2
3.3PF
5%
25V
CERM 2
201
PLACE_NEAR=U3000.F7:3.2mm
90 29 12
IN
MEM_A_CLK_P & lt; 1 & gt;
90 31 30 12
C3360
1
2
1
25V
CERM 2
201
IN
MEM_B_CLK_P & lt; 0 & gt;
IN
IN
36
36
2
7
1
8
MEM_B_A & lt; 15 & gt;
MEM_B_A & lt; 11 & gt;
36
36
1
8
2
7
MEM_B_CAS_L
MEM_B_A & lt; 1 & gt;
RP3328
RP3325
36
36
2
7
3
6
RP3320
RP3326
RP3330
RP3320
RP3330
RP3330
RP3324
RP3326
RP3324
RP3326
RP3322
RP3326
RP3330
RP3324
RP3324
RP3325
MEM_A_CLK1_TERM_R
1
2
MEM_B_BA & lt; 0 & gt;
MEM_B_A & lt; 10 & gt;
MEM_B_RAS_L
RP3320
RP3320
RP3322
90 31 30 12
IN
90 31 30 12
IN
90 31 30 12
10%
6.3V
X5R
201
IN
36
36
36
4X0201
5% 1/32W
4X0201
5% 1/32W
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
36
4X0201
5% 1/32W
4X0201
5% 1/32W
4X0201
4X0201
5
5% 1/32W
4X0201
2
7
5% 1/32W
4X0201
3
6
5% 1/32W
4X0201
1
8
5% 1/32W
4X0201
3
6
5% 1/32W
4X0201
4
5
5% 1/32W
4X0201
2
7
5% 1/32W
4X0201
8
5% 1/32W
4X0201
3
6
5% 1/32W
4X0201
3
6
5% 1/32W
4X0201
1
8
5% 1/32W
4X0201
5
5% 1/32W
4X0201
3
6
5% 1/32W
4X0201
2
7
5% 1/32W
4X0201
4
5
5% 1/32W
4X0201
5% 1/32W
MEM_B_CS_L & lt; 0 & gt;
MEM_B_A & lt; 14 & gt;
MEM_B_A & lt; 0 & gt;
MEM_B_BA & lt; 2 & gt;
MEM_B_BA & lt; 1 & gt;
MEM_B_A & lt; 4 & gt;
MEM_B_CS_L & lt; 1 & gt;
MEM_B_A & lt; 6 & gt;
MEM_B_A & lt; 12 & gt;
MEM_B_A & lt; 9 & gt;
MEM_B_CKE & lt; 0 & gt;
MEM_B_A & lt; 7 & gt;
MEM_B_A & lt; 5 & gt;
MEM_B_A & lt; 3 & gt;
MEM_B_A & lt; 2 & gt;
MEM_B_A & lt; 8 & gt;
5% 1/32W
5% 1/32W
0.1UF
30
2
90 31 12
30
IN
90 31 12
IN
90 31 30 12
2
4X0201
2
4
1
4
1
C3320
0.47UF
20%
2 4V
CERM-X5R-1
201
7
1
C3322
0.47UF
20%
4V
2 CERM-X5R-1
201
1
C3324
0.47UF
20%
4V
2 CERM-X5R-1
201
1
C3326
0.47UF
20%
2 4V
CERM-X5R-1
201
4
5
8
5% 1/32W
4X0201
1
1
1
8
5% 1/32W
4X0201
5% 1/32W
4X0201
1
C3323
0.47UF
20%
4V
2 CERM-X5R-1
201
1
C3325
0.47UF
20%
4V
2 CERM-X5R-1
201
1
C3327
B
0.47UF
20%
2 4V
CERM-X5R-1
201
20%
2 4V
CERM-X5R-1
201
C3328
0.47UF
IN
MEM_B_ODT & lt; 1 & gt;
MEM_B_CKE & lt; 1 & gt;
MEM_B_WE_L
RP3328
RP3328
RP3322
36
36
36
4
5
6
5% 1/32W
4X0201
1
3
4
5
5% 1/32W
4X0201
5% 1/32W
4X0201
20%
4V
2 CERM-X5R-1
201
C3330
0.47UF
C3361
0.1UF
MEM_B_CLK0_TERM_R
5%
1/20W
MF
201
3.3PF
PLACE_NEAR=U3170.F7:3.2mm
5%
90 30 12
IN
90 31 30 12
C3356
R3360
IN
IN
=PP0V75_S0_MEM_VTT_B
RP3322
RP3325
RP3328
RP3325
MEM_B_ODT & lt; 0 & gt;
MEM_B_A & lt; 13 & gt;
R3356
1
MEM_B_CLK_N & lt; 0 & gt;
IN
90 31 30 12
5%
1/20W
MF
201
90 30 12
IN
90 31 30 12
5%
1/20W
MF
201
1
IN
90 30 12
90 31 30 12
R3355
30
IN
90 31 30 12
5%
1/20W
MF
201
1
IN
90 31 30 12
R3351
30
IN
C
1
2
10%
6.3V
X5R
201
R3361
1
30
2
5%
1/20W
MF
201
A
C3366
R3365
90 31 12
IN
MEM_B_CLK_N & lt; 1 & gt;
C3365
1
90 31 12
IN
5%
25V
CERM 2
201
MEM_B_CLK_P & lt; 1 & gt;
2
5%
1/20W
MF
201
1
3.3PF
PLACE_NEAR=U3270.F7:3.2mm
30
SYNC_MASTER=D2_KEPLER
0.1UF
MEM_B_CLK1_TERM_R
1
DDR3 Termination
10%
6.3V
X5R
201
DRAWING NUMBER
Apple Inc.
30
NOTICE OF PROPRIETARY PROPERTY:
2
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
5%
1/20W
MF
201
8
7
6
051-9589
5
4
3
2
SIZE
D
REVISION
R
R3366
1
SYNC_DATE=01/13/2012
PAGE TITLE
2
4.18.0
BRANCH
PAGE
33 OF 132
SHEET
32 OF 99
1
A
8
8
7
6
5
4
3
2
NOTE: Must not enable more than two SO-DIMM margining
buffers at once or VRef source may be overloaded.
=PP3V3_S3_VREFMRGN
VREFDQ:LDO_DAC
OMIT
R3418
64 8
SHORT
1
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
DDRVREF_DAC
C3400
20%
6.3V
CERM
402-LF
1
1
2
2
D
C3401
DDRVREF_DAC
0.1UF
C3403
CRITICAL
DDRVREF_DAC
20%
10V
CERM
402
U3400
8
7 SDA
9 A0
Addr=0x98(WR)/0x99(RD)
1
2
4
A3
1
CRITICAL
R3401
5%
1/16W
MF-LF
C2
PP3V3_S3_VREFMRGN_CTRL
V+
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
16
C3402
1
0.1UF
PCA9557
3
4
Addr=0x30(WR)/0x31(RD)
5
44
BOM options provided by this page:
44
IN
BI
=I2C_PCA9557D_SCL
=I2C_PCA9557D_SDA
1
2
(OD) P0
6
P1
P2
P3
P4
P5
P6
P7
SCL
SDA
RESET*
THRM
17
NC
VREFMRGN_DQ_SODIMMA_EN
VREFMRGN_DQ_SODIMMB_EN
VREFMRGN_CA_SODIMMA_EN
VREFMRGN_CA_SODIMMB_EN
VREFMRGN_MEMVREG_EN
VREFMRGN_FRAMEBUF_EN
9
10
11
12
13
14
1
2
PLACE_NEAR=R3405.2:1mm
1%
1/16W
MF-LF
402
V-
VREFCA:LDO_DAC
R3409
200
R3402
1
100K
2
133
30 31 33 89
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.75V
2
PLACE_NEAR=J2900.126:2.54mm
CRITICAL
5%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
DDRVREF_DAC
C3404
DDRVREF_DAC
1
20%
10V
CERM
402
NC
A2
V+
MAX4253
R3410
UCSP
2
A1
A3
15
28 29 89
C
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.75V
133
VREFMRGN_CA_SODIMMA_BUF
1
2
PLACE_NEAR=R3409.2:1mm
1%
1/16W
MF-LF
402
A4
V-
GND
PP0V75_S3_MEM_VREFCA_A
VREFCA:LDO_DAC
U3403
B1
0.1UF
B4
8
PAD
VREFDQ:LDO_DAC - Margined LDO outputs sent to DQ inputs.
1
DDRVREF_DAC
7
A0
A1
A2
- Stuffs Apple margining circuit.
VREFDQ:LDO - LDO outputs sent to DQ inputs.
VREFMRGN_DQ_SODIMMB_BUF
B4
U3401
2
QFN
=I2C_VREFDACS_SCL
=I2C_VREFDACS_SDA
=I2C_PCA9557D_SCL
=I2C_PCA9557D_SDA
R3406
UCSP
C4
VCC
20%
10V
CERM
402
Signal aliases required by this page:
C3
PLACE_NEAR=J3100.1:2.54mm
PP0V75_S3_MEM_VREFDQ_B
NC
- =PP3V3_S3_VREFMRGN
- =PPVTT_S3_DDR_BUF
- =PPDDR_S3_MEMVREF
CRITICAL
DDRVREF_DAC
2
VREFDQ:LDO_DAC
U3402
MAX4253
C1
DDRVREF_DAC
200
1%
1/16W
MF-LF
402
DDRVREF_DAC
B1
2 402
Power aliases required by this page:
DDRVREF_DAC
1
100K
NONE
NONE
NONE
402
PLACE_NEAR=R3403.2:1mm
R3405
OMIT
C
V-
DDRVREF_DAC
a DAC output, cannot enable
R3419
Page Notes
A4
D
2
VREFDQ:LDO_DAC
both at the same time!
2
133
1%
1/16W
MF-LF
402
VREFMRGN_MEMVREG_FBVREF
3
1
1
NOTE: MEMVREG and FRAMEBUF share
GND
SHORT
VREFMRGN_DQ_SODIMMA_BUF
28 29 33 89
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.75V
VREFMRGN_SODIMMS_CA
5
A1
VREFMRGN_SODIMMB_DQ
VOUTC
R3404
UCSP
B4
10 A1
PLACE_NEAR=J2900.1:2.54mm
VREFDQ:LDO_DAC
MAX4253
2
VREFMRGN_SODIMMA_DQ
VOUTB
MSOP
V+
NC
6 SCL
=I2C_VREFDACS_SDA
DAC5574
=I2C_VREFDACS_SCL
VOUTA
VOUTD
IN
BI
2
PP0V75_S3_MEM_VREFDQ_A
U3402
B1
A2
20%
10V
CERM
402
200
1%
1/16W
MF-LF
402
DDRVREF_DAC
1
0.1UF
VDD
44
1
CRITICAL
DDRVREF_DAC
2.2UF
44
R3403
=PPVTT_S3_DDR_BUF
10mA max load
PP3V3_S3_VREFMRGN_DAC
2
NONE
NONE
NONE
402
-
1
VREFDQ:M1_M3 - CPU margined DDR voltage divider sent to DQ inputs.
VREFCA:LDO_DAC
VREFDQ:M1_DAC - DAC margined DDR voltage divider sent to DQ inputs.
R3411
VREFCA:LDO - LDO outputs sent to CA inputs.
1
VREFCA:LDO_DAC - DAC margined LDO outputs sent to CA inputs.
IN
DDRVREF_DAC
1
RST* on ’platform reset’ so that system
watchdog will disable margining.
R3407
100K
C2
V+
=PPDDR_S3_MEMVREF
1
2
SOT563
UCSP
1
133
VREFMRGN_CA_SODIMMB_BUF
1
V-
C3405
20%
10V
CERM
402
5
SSM6N15FEAPE
MEMRESET_ISOL_LS5V_L
SOT563
G
33 27
R3416
C3440
5%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
NC
R3413
100K
0
1K
2
1
1
2
5%
1/16W
MF-LF
402
B1
A2
V+
A3
2
DDRREG_FB
OUT
B
64
1%
1/16W
MF-LF
402
D
30 31 33 89
VREFDQ:M1_M3
2
Required zero ohm resistors when no VREF margining circuit stuffed
DDRVREF_DAC
1
R3417
PART NUMBER
0
A4
V-
VREFMRGN_MEMVREG_FBVREF_R
PLACE_NEAR=R3441.2:1mm
U3404
MAX4253
UCSP CRITICAL
2
B4
PP0V75_S3_MEM_VREFDQ_B
5%
1/16W
MF-LF
402
1
1%
1/16W
MF-LF
402
MEM B VREF CA
DESCRIPTION
REFERENCE DES
R3403,R3405
VREFDQ:LDO
2
RES,MTL FILM,0,5%,0402,SM,LF
R3409,R3411
VREFCA:LDO
PART NUMBER
QTY
DESCRIPTION
REFERENCE DES
RES,MTL FILM,1K,1%,0402,SM,LF
R3421,R3422,R3441,R3442
VREFDQ:M1_DAC
114S0171
2
RES,MTL FILM,332,1%,0402,SM,LF
R3404,R3406
VREFDQ:M1_DAC
5%
1/16W
MF-LF
402
GPU Frame Buffer (1.8V, 70% VRef)
A
B
C
C
D
2
3
4
5
SYNC_MASTER=D2_KEPLER
DDR3/FRAMEBUF VREF MARGINING
6
DRAWING NUMBER
Apple Inc.
0.75V (DAC: 0x3A)
1.5V (DAC: 0x3A)
1.267V (DAC: 0x8B)
Margined target:
0.300V - 1.200V (+/- 450mV)
1.000V - 2.000V (+/- 500mV)
1.056V - 1.442V (+/- 180mV)
DAC range:
0.000V - 1.501V (0x00 - 0x74)
0.000V - 3.000V (0x00 - 0x74)
0.000V - 3.300V (0x00 - 0xFF)
VRef current:
+3.4mA - -3.4mA (- = sourced)
8
7
-61uA (- = sourced)
6
5
NOTICE OF PROPRIETARY PROPERTY:
1.51mV / step @ output
4
051-9589
3
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
2
SIZE
D
REVISION
R
+6.0mA - -5.0mA (- = sourced)
8.59mV / step @ output
SYNC_DATE=01/13/2012
PAGE TITLE
D
1
7.69mV / step @ output
BOM OPTION
4
R3415
PCA9557D Pin:
DAC step size:
CRITICAL
114S0218
MEM VREG
+61uA -
BOM OPTION
RES,MTL FILM,0,5%,0402,SM,LF
VREFMRGN_FRAMEBUF_BUF_R
DAC Channel:
Nominal value
CRITICAL
2
116S0004
100K
MEM A VREF CA
QTY
116S0004
DDRVREF_DAC
R3442
2
MEM B VREF DQ
PLACE_NEAR=R7320.2:1mm
V-
33.2K
DDRVREF_DAC
A1
2
1K
MEM A VREF DQ
1
VREFMRGN_FRAMEBUF_BUF
DDRVREF_DAC
DDRVREF_DAC
R3441
1
A
C4
VREFMRGN_MEMVREG_BUF
B4
3
PPCPU_MEM_VREFDQ_B
4
89 10
S
2
C1
1%
1/16W
MF-LF
2 402
1
10%
16V
X7R-CERM
0402
R3414
UCSP
2
1K
0.1UF
1
MAX4253
NC
Q3420
V+
C3
PLACE_NEAR=Q3420.3:1mm
VREFDQ:M1_M3
PLACE_NEAR=Q3420.3:2mm
VREFDQ:M1_M3
C2
DDRVREF_DAC
U3404
B1
0.1UF
28 29 33 89
NOTE: CPU DAC output step sizes:
DDR3 (1.5V)
7.70mV per step
DDR3L (1.35V) 6.99mV per step
CRITICAL
VREFDQ:M1_M3
1
R3422
=PPDDR_S3_MEMVREF
33 8
CRITICAL
DDRVREF_DAC
DDRVREF_DAC
VREFDQ:M1_M3
PLACE_NEAR=R3421.2:1mm
PLACE_NEAR=R3411.2:1mm
R3408
5%
1/16W
MF-LF
2 402
PP0V75_S3_MEM_VREFDQ_A
1
2
1%
1/16W
MF-LF
402
C4
100K
D
2
1%
1/16W
MF-LF
402
6
S
PPCPU_MEM_VREFDQ_A
1
B
89 10
2
10%
16V
X7R-CERM
0402
30 31 89
DDRVREF_DAC
R3421
1K
0.1UF
G
MEMRESET_ISOL_LS5V_L
1
C3420
PP0V75_S3_MEM_VREFCA_B
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.75V
NC
Q3420
SSM6N15FEAPE
33 27
PLACE_NEAR=Q3420.6:1mm
VREFDQ:M1_M3
PLACE_NEAR=Q3420.6:2mm
VREFDQ:M1_M3
PLACE_NEAR=J3100.126:2.54mm
R3412
B4
CRITICAL
VREFDQ:M1_M3
2
VREFCA:LDO_DAC
U3403
MAX4253
C1
C3
200
1%
1/16W
MF-LF
402
CRITICAL
DDRVREF_DAC
B1
5%
1/16W
MF-LF
2 402
NOTE: Margining will be disabled across all
soft-resets and sleep/wake cycles.
33 8
NC
25
PCA9557D_RESET_L
4.18.0
BRANCH
PAGE
34 OF 132
SHEET
33 OF 99
1
A
8
7
6
5
4
3
2
1
OMIT_TABLE
L3570
PLACE_NEAR=J3501.15:2.54MM
1
C3531
PCIE_AP_R2D_PI_P
92
2
1
2
10%
0.6NH+/-0.1NH-0.85A
PCIE_AP_R2D_C_P
0.1UF
IN
17 92
16V X7R-CERM0402
PART NUMBER
0201
QTY
DESCRIPTION
REFERENCE DES
CRITICAL
BOM OPTION
NOSTUFF
NOSTUFF
1 C3570
0.1UF
D
2
117S0002
1 C3571
4
L3570,L3571,L3573,L3574
RES, 0OHM, 0201
D
0.1UF
10%
16V
X5R-CERM
0201
2
10%
16V
X5R-CERM
0201
L3571
1
WIFI_EVENT_L
IN
7 41 42
2
92
1
PCIE_AP_R2D_PI_N
2
10%
0.6NH+/-0.1NH-0.85A
NOSTUFF
OMIT_TABLE
1 C3572
17 92
3V S3 WLAN FET
PLACE_NEAR=J3501.17:2.54MM
MOSFET
DMP2018LFK
CHANNEL
P-TYPE
1 C3573
0.1UF
2
PCIE_AP_R2D_C_N IN
C3530
0201
NOSTUFF
0.1UF
16V X7R-CERM0402
0.1UF
10%
16V
X5R-CERM
0201
10%
16V
X5R-CERM
0201
RDS(ON) @ 2.5V
14 mOhm Typ
20 mOhm Max
LOADING
2
1 A (EDP)
OMIT_TABLE
L3573
CRITICAL
2
DFN2563-6
155S0367
0.1UF
10%
16V
X5R-CERM
0201
10%
16V
X5R-CERM
0201
NOSTUFF
2
L3504
42 7
1
SSD-K99
2
PCIE_AP_D2R_N
1 C3576
1
2
3
92 7
PCIE_AP_D2R_PI_P
4
92 7
1
IN
34 99
OUT
=PP3V3_S3_WLAN
MIN_LINE_WIDTH=1 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=3.3V
1
1
3
0.1uF
0.1uF
20%
10V
CERM
402
10%
16V
X5R
402
2
PCIE_AP_D2R_PI_N
L3501
6
PLACE_NEAR=J3501.29:2.54MM
2
C3550
0.1UF
PLACE_NEAR=J3501.29:2.54MM
1
AIRPORT
CRITICAL
5
2
8 34
R3550
2
5%
1/16W
MF-LF
402
33K
P3V3WLAN_SS
2
R3551
10K
2
1
C
PM_WLAN_EN_L
2
IN
70
5%
1/16W
MF-LF
402
10%
16V
X7R-CERM
0402
90-OHM-100MA
DLP11S
7
C3551
1
0.033UF
20%
10V
CERM
402
10%
16V
X5R-CERM
0201
C3521
PP3V3_WLAN_R
C3522
0.1UF
10%
NOSTUFF
16V
X5R-CERM
0201
2
PP3V3_WLAN_F
MIN_LINE_WIDTH=1 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=3.3V
2
1
NOSTUFF
0201
OMIT_TABLE
0.1UF
2
0603
4
1 C3577
0.6NH+/-0.1NH-0.85A
F-RT-SM1
OUT
1
PP3V3_WLAN
MIN_LINE_WIDTH=1 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
17 92
CURRENT SENSE
FERR-120-OHM-3A
1A PEAK
L3574
514S0335
J3501
C
NOSTUFF
1 C3575
0201
0.1UF
CRITICAL
DMP2018LFK
D
1 C3574
PCIE_AP_R2D_N
17 92
OUT
G
92 7
Q3550
PCIE_AP_D2R_P
0.6NH+/-0.1NH-0.85A
PCIE_AP_R2D_P
92 7
2
S
1
SYM_VER-1
8
96 7
1
2
PCIE_CLK100M_AP_P
IN
17 92
4
PCIE_CLK100M_AP_CONN_P
3
PCIE_CLK100M_AP_N
IN
17 92
9
10
96 7
11
PCIE_CLK100M_AP_CONN_N
PLACE_NEAR=J3501.11:2.54MM
BLUETOOTH
13
PCIE_WAKE_L
OUT
PP3V3_S3RS4_BT_F
SIGNAL_MODEL=EMPTY
BTPWR:S4
7 34
NOSTUFF
BTPWR:S3
1
16
91 7
17
91 7
L3505
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
2
1
1 C3532
20
2
10%
16V
X7R-CERM
0402
NOSTUFF
15K
1
=PP3V3_S3_BT
U3510
TQFN
1%
1/20W
MF
2 201
8
CRITICAL
10 SEL
IN
PM_SLP_S4_L
1
0
2
15K
91
1%
1/20W
MF
2 201
D+ 7
D- 6
1
G
S 2
USB_BT_WAKE_P
USB_BT_WAKE_N
BTPWR:S4
NOSTUFF
1
USB_BT_P
USB_BT_N
BI
9 91
BI
9 91
OE* 8
R3511
0402-LF
PLACE_NEAR=J3501.27:2.54MM
91
R3512 1R3513
15K
15K
1%
1/20W
MF
2 201
1%
1/20W
MF
2 201
Delay = 130 ms +/- 20%
PP3V3_WLAN_F
NOSTUFF
C3511 1
L
H
10%
16V
X7R-CERM 2
0402
USB_BT_WAKE
USB_BT
1
R3553
1
1%
1/16W
MF-LF
402
CRITICAL
R3554
VDD
232K
100K
2
518S0767
1
C3540
0.1uF
SLG4AP041V
TDFN
2
20%
10V
CERM
402
2 SENSE
+
VREF -
BOM OPTION
DLY
CRITICAL
J3502
CONN,HDR,TWIN-AX,P=0.4MM,6P,HF
CRITICAL
1
U3540
1%
1/16W
MF-LF
402
P3V3WLAN_VMON
REFERENCE DES
8 34
OUTPUT
2
DESCRIPTION
=PP3V3_S3_WLAN
34 99
SEL
0.01UF
QTY
B
Supervisor & CLKFREG # Isolation
BTMUX_SEL
5%
1/20W
MF
201
PART NUMBER
42
GND
BTPWR:S4
FERR-120-OHM-1.5A
R3514
PI3USB102ZLE
15K
1%
1/20W
MF
2 201
M+ 5
M- 4
OUT
D 3
SOD-VESM-HF
1
10%
6.3V
2 X5R
201
VCC
1 Y+
2 Y-
R3515 1R3516
L3506
2
NOSTUFF
C3510
0.1UF
1
0402-LF
PLACE_NEAR=J3501.27:2.54MM
BTPWR:S3
B
5%
1/20W
MF
201 2
8
FERR-120-OHM-1.5A
0.01UF
21
=PP3V3_S4_BT
1
0
1%
1/20W
MF
2 201
BTPWR:S4
PP3V3_S3RS4_BT_F
19
15K
SSM3K15FV
3
18
R35181
R3517
USB_BT_CONN_N
USB_BT_CONN_P
NOSTUFF
9
15
=BT_WAKE_L
Q3510
7 18
14
1
12
7
AP_RESET_CONN_L
4 RESET*
OMIT
MR* 3
AP_RESET_L
IN
J3502
EN 6
OUT 8
CCR20-6K710S
AP_CLKREQ_Q_L
7 IN
1
6
5
4
7
3
A
91 7
2
91 7
=I2C_ALS_SDA
=I2C_ALS_SCL
PP5V_S3_ALSCAMERA_F
USB_CAMERA_CONN_N
USB_CAMERA_CONN_P
BI
IN
44
OUT
(OD)
GND
100K
44
1%
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V
275 mA peak
206 mA nominal max
1/16W
PLACE_NEAR=J3502.6:2.54MM
MF-LF
2
ALS
L3508
2
1
CAMERA
CRITICAL
7
402
FERR-120-OHM-1.5A
1
=PP5V_S3_ALSCAMERA
SYNC_MASTER=D2_KEPLER
8
1
90-OHM
DLP0NS
X29/ALS/CAMERA CONNECTOR
C3552
DRAWING NUMBER
0.1uF
SYM_VER-1
2
1
2
USB_CAMERA_N
BI
19 91
4
3
USB_CAMERA_P
BI
Apple Inc.
20%
10V
CERM
402
19 91
NOTICE OF PROPRIETARY PROPERTY:
6
5
051-9589
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
4
3
2
SIZE
D
REVISION
R
PLACE_NEAR=J3502.3:2.54MM
7
SYNC_DATE=01/13/2012
PAGE TITLE
0402-LF
L3507
8
17
AP_CLKREQ_L
THRM
PAD
R3555
19 24 70
AP_PWR_EN
5
7
8
9
F-RT-SM
25
IN
CRITICAL
4.18.0
BRANCH
PAGE
35 OF 132
SHEET
34 OF 99
1
A
8
7
6
5
4
CRITICAL
1
10%
0.1UF
92 9
IN
1
IN
C3602
PCIE_TBT_R2D_C_P & lt; 1 & gt;
10%
1
IN
92 9
IN
1
C3604
PCIE_TBT_R2D_C_P & lt; 2 & gt;
37 36 35
IN
10%
1
92 9
IN
PCIE_TBT_R2D_C_P & lt; 3 & gt;
C3606
IN
PCIE_TBT_R2D_C_N & lt; 3 & gt;
C3607
R36101
92 9
5%
1/20W
MF
201 2
37
X5R-CERM 0201
16V
X5R-CERM 0201
AB15
AA16
2
10%
1
16V
X5R-CERM 0201
16V
X5R-CERM0201
92
92
AA18
PCIE_TBT_R2D_P & lt; 3 & gt;
PCIE_TBT_R2D_N & lt; 3 & gt;
AB19
2
10%
0.1UF
16V
PERP_1
PERN_1
PERP_2
PERN_2
NO_TEST=TRUE
NO_TEST=TRUE
2
10%
1
IN
C3610 1
R6
PWR_ON_POC_RSTN
(TBT_SPI_CLK)
47
D
6
2
Q
(TBT_SPI_MISO)
93
93
93
(TBT_SPI_CS_L)
TBTROM_HOLD_L
C
20
3 W*
7 HOLD*
IN
IN
20
VSS
4
THM
PAD
9
20
R3625
1
1
0
R3629
IN
OUT
95 35 7
0
5%
1/20W
MF
201 2
5%
1/20W
MF
2 201
95 35 7
95 35 7
95 35 7
95 35 7
95 35 7
95 35 7
95 35 7
IN
DP_TBTSNK0_ML_C_P & lt; 0 & gt;
1
95 77 7
IN
DP_TBTSNK0_ML_C_N & lt; 0 & gt;
C3621
95 77 7
IN
DP_TBTSNK0_ML_C_P & lt; 1 & gt;
C3622
95 77 7
IN
DP_TBTSNK0_ML_C_N & lt; 1 & gt;
C3623
1
C3624
IN
DP_TBTSNK0_ML_C_N & lt; 2 & gt;
C3625
1
IN
DP_TBTSNK0_ML_C_P & lt; 3 & gt;
C3626
95 77 7
IN
DP_TBTSNK0_ML_C_N & lt; 3 & gt;
C3627
7 35 95
DP_TBTSNK0_ML_N & lt; 1 & gt;
2
2
95 35 7
7 35 95
100K
5%
1/20W
MF
201
95 35 7
95 35 7
2
95 35 7
95 35 7
95 35 7
DP_TBTSNK0_ML_P & lt; 2 & gt;
2
82
7 35 95
10%
16V
X5R-CERM 0201
1
DP_TBTSNK0_ML_N & lt; 2 & gt;
2
1
7 35 95
95 35 7
7 35 95
DP_TBTSNK0_ML_N & lt; 3 & gt;
95 35 7
100K
5%
1/20W
MF
201
DP_TBTSNK0_ML_P & lt; 3 & gt;
2
OUT
R3631 1
10%
16V
X5R-CERM0201
0.1UF
95 77 7
7 35 95
DP_TBTSNK0_ML_P & lt; 1 & gt;
R3630 1
10%
16V
X5R-CERM 0201
0.1UF
95 77 7
DP_TBTSNK0_ML_N & lt; 0 & gt;
2
OUT
10%
16V
X5R-CERM 0201
1
0.1UF
DP_TBTSNK0_ML_C_P & lt; 2 & gt;
82
7 35 95
10%
16V
X5R-CERM0201
1
0.1UF
IN
DP_TBTSNK0_ML_P & lt; 0 & gt;
2
10%
16V
X5R-CERM 0201
0.1UF
95 77 7
95 35 7
SNK0 AC Coupling
C3620
0.1UF
B
95 35 7
95 35 7
1
2
BI
1
BI
DP_TBTSNK0_AUXCH_C_N
C3629
93 84 7
1
DP_TBTSNK0_AUXCH_N
2
OUT
IN
93 84 7
IN
7 35 95
7 35 95
10%
16V
X5R-CERM 0201
0.1UF
OUT
93 84 7
DP_TBTSNK0_AUXCH_P
2
10%
16V
X5R-CERM0201
0.1UF
95 83 7
84 82
84
95 77 7
IN
DP_TBTSNK1_ML_C_P & lt; 0 & gt;
SNK1 AC Coupling
C3630
1
IN
DP_TBTSNK1_ML_C_N & lt; 0 & gt;
C3631
1
95 77 7
IN
DP_TBTSNK1_ML_C_P & lt; 1 & gt;
C3632
1
IN
DP_TBTSNK1_ML_C_N & lt; 1 & gt;
C3633
1
95 77 7
IN
DP_TBTSNK1_ML_C_P & lt; 2 & gt;
C3634
1
IN
DP_TBTSNK1_ML_C_N & lt; 2 & gt;
IN
DP_TBTSNK1_ML_C_P & lt; 3 & gt;
C3635
1
C3636
1
IN
DP_TBTSNK1_ML_C_N & lt; 3 & gt;
C3637
1
IN
DP_TBTSNK1_ML_P & lt; 1 & gt;
2
7 35 95
84
BI
DP_TBTSNK1_AUXCH_C_P
C3638
BI
DP_TBTSNK1_AUXCH_C_N
C3639
1
95 83 7
0.1UF
8
1
AB3
AA6
R2
N4
AB5
DP_TBTSNK0_ML_P & lt; 3 & gt;
DP_TBTSNK0_ML_N & lt; 3 & gt;
E14
DP_TBTSNK0_ML_P & lt; 2 & gt;
DP_TBTSNK0_ML_N & lt; 2 & gt;
E16
DP_TBTSNK0_ML_P & lt; 1 & gt;
DP_TBTSNK0_ML_N & lt; 1 & gt;
E18
DP_TBTSNK0_ML_P & lt; 0 & gt;
DP_TBTSNK0_ML_N & lt; 0 & gt;
E20
D13
D15
D17
D19
DP_TBTSNK0_AUXCH_P
DP_TBTSNK0_AUXCH_N
A6
U6
B5
DP_TBTSNK1_ML_P & lt; 3 & gt;
DP_TBTSNK1_ML_N & lt; 3 & gt;
E6
DP_TBTSNK1_ML_P & lt; 2 & gt;
DP_TBTSNK1_ML_N & lt; 2 & gt;
E8
DP_TBTSNK1_ML_P & lt; 1 & gt;
DP_TBTSNK1_ML_N & lt; 1 & gt;
E10
DP_TBTSNK1_ML_P & lt; 0 & gt;
DP_TBTSNK1_ML_N & lt; 0 & gt;
E12
DP_TBTSNK1_AUXCH_P
DP_TBTSNK1_AUXCH_N
A4
D5
D7
D9
D11
B3
T5
TBT_A_R2D_C_P & lt; 0 & gt;
TBT_A_R2D_C_N & lt; 0 & gt;
G24
TBT_A_D2R_P & lt; 0 & gt;
TBT_A_D2R_N & lt; 0 & gt;
G22
E24
E22
TBT_A_CONFIG1_BUF
TBT_A_CONFIG2_RC
K1
G4
OUT
OUT
TBT_A_D2R_P & lt; 1 & gt;
TBT_A_D2R_N & lt; 1 & gt;
L22
J22
TBT_A_LSTX
TBT_A_LSRX
N2
J6
DP_TBTPA_ML_C_P & lt; 1 & gt;
DP_TBTPA_ML_C_N & lt; 1 & gt;
A16
DP_TBTPA_ML_C_P & lt; 3 & gt;
DP_TBTPA_ML_C_N & lt; 3 & gt;
A18
F3
B17
OUT
93 84
7 35 95
BI
BI
DP_TBTPA_AUXCH_C_P
DP_TBTPA_AUXCH_C_N
DP_TBTPA_HPD
H1
IN
TBT_A_HV_EN
TBT_A_CIO_SEL
TBT_A_DP_PWRDN
G2
7 35 95
84 35
OUT
84 35
7 35 95
OUT
84
92
U20
W20
TBT_RBIAS
1
16V
9 92
OUT
PCIE_TBT_D2R_P & lt; 3 & gt;
2
9 92
OUT
X5R-CERM 0201
9 92
OUT
X5R-CERM 0201
PCIE_TBT_D2R_N & lt; 2 & gt;
10%
0.1UF
C3646
16V
2
9 92
OUT
PCIE_TBT_D2R_P & lt; 2 & gt;
2
10%
1
X5R-CERM 0201
9 92
D
TBT_RSENSE
U4
TDI
TMS
TCK
TDO
TEST_EN
TEST_PWR_GOOD
PCIE_RST_0_N
PCIE_RST_1_N
PCIE_RST_2_N
PCIE_RST_3_N
10%
0.1UF
C3647
0.1UF
1
16V
X5R-CERM 0201
PCIE_TBT_D2R_N & lt; 3 & gt;
2
10%
16V
X5R-CERM 0201
37 36 35
1
NC
W6
=PP3V3_S4_TBT
R3655
R36851
DPSNK0_1_P
DPSNK0_1_N
DPSNK0_0_P
DPSNK0_0_N
REFCLK_100_IN_P
REFCLK_100_IN_N
10K
84 37 35
7
5%
1/20W
MF
2 201
TBT_A_DP_PWRDN
TBT_B_DP_PWRDN
TBT_A_HV_EN
TBT_B_HV_EN
85 35
7
85 37 35
7
R36881
7
=TBT_CLKREQ_L
OUT
37
=PP3V3_TBTLC_RTR
TBT_EN_LC_PWR
K5
OUT
1
R3687
AD21
1
XTAL_25_IN
XTAL_25_OUT
AA24
AA4
91
AB23
IN
17 92
8 35 36 37
5%
1/20W
MF
2 201
R3698
IN
17 92
5%
1/20W
MF
201
C
R3695
806
SYSCLK_CLK25M_TBT_R
TP_TBT_XTAL25OUT
1
SYSCLK_CLK25M_TBT
2
1%
1/20W
MF
201
7
TBT_TMU_CLK_OUT
TBT_TMU_CLK_IN
Y3
10K
5%
1/20W
MF
201 2
10K
PCIE_CLK100M_TBT_P
PCIE_CLK100M_TBT_N
AB21
37
IN
25 91
Divides 3.3V to 1.8V
=PP3V3_TBTLC_RTR
37 36 35 8
NO STUFF
1
DPSNK1_3_P
DPSNK1_3_N
DPSNK1_0_P
DPSNK1_0_N
U2
TMU_CLK_OUT
TMU_CLK_IN
DPSNK0_HPD
DPSNK1_1_P
DPSNK1_1_N
Y5
R3686
5%
1/20W
MF
201 2
2
DPSNK0_AUX_P
DPSNK0_AUX_N
DPSNK1_2_P
DPSNK1_2_N
T1
1
10K
1%
1/20W
MF
201
10K
EN_LC_PWR
DPSNK0_3_P
DPSNK0_3_N
DPSNK0_2_P
DPSNK0_2_N
Not used in host mode.
TP_TBT_PCIE_RESET0_L
TP_TBT_PCIE_RESET1_L
TP_TBT_PCIE_RESET2_L
TP_TBT_PCIE_RESET3_L
N6
DPSRC_3_P
DPSRC_3_N
A14
DPSRC_2_P
DPSRC_2_N
A12
DPSRC_1_P
DPSRC_1_N
A10
DPSRC_0_P
DPSRC_0_N
A8
TP_DP_TBTSRC_ML_CP & lt; 3 & gt;
TP_DP_TBTSRC_ML_CN & lt; 3 & gt;
B15
R3699
100K
7
1
1
10K
5%
1/20W
MF
2 201
7
R36801
R3696
10K
1K
5%
1/20W
MF
201 2
5%
1/20W
MF
201 2
5%
1/20W
MF
2 201
7
82 35
TP_DP_TBTSRC_ML_CP & lt; 1 & gt;
TP_DP_TBTSRC_ML_CN & lt; 1 & gt;
B11
7
TP_DP_TBTSRC_ML_CP & lt; 0 & gt;
TP_DP_TBTSRC_ML_CN & lt; 0 & gt;
B9
35
R3681
D3
TP_DP_TBTSRC_AUXCH_CP
TP_DP_TBTSRC_AUXCH_CN
V3
TBT_GO2SX_BIDIR
TBT_PWR_EN
=TBT_WAKE_L
TBT_CIO_PLUG_EVENT
=I2C_TBTRTR_SDA
=I2C_TBTRTR_SCL
(TBT_EN_CIO_PWR_L)
TBT_GPIO_9
TBT_GPIO_14
TBT_DDC_XBAR_EN_L
NO STUFF
R36831
5%
1/20W
MF
2 201
GPIO_2/GO2SX
(FORCE_PWR) GPIO_3
GPIO_4/WAKE_N_OD
GPIO_5/CIO_PLUG_EVENT
GPIO_6/CIO_SDA_OD
GPIO_7/CIO_SCL_OD
GPIO_8/EN_CIO_PWR_OD*
GPIO_9/OK2GO2SX_OD*
GPIO_14
GPIO_15
PA_CIO0_TX_P/DP_SRC_0_P
PA_CIO0_TX_N/DP_SRC_0_N
PA_CIO0_RX_P
PA_CIO0_RX_N
PB_CIO2_TX_P/DP_SRC_0_P
PB_CIO2_TX_N/DP_SRC_0_N
PA_CONFIG1/CIO_0_LSEO
PA_CONFIG2/CIO_0_LSOE
PB_CIO2_RX_P
PB_CIO2_RX_N
PB_CONFIG1/CIO_2_LSEO
PB_CONFIG2/CIO_2_LSOE
PA_CIO1_TX_P/DP_SRC_2_P
PA_CIO1_TX_N/DP_SRC_2_N
PA_CIO1_RX_P
PA_CIO1_RX_N
PB_CIO3_TX_P/DP_SRC_2_P
PB_CIO3_TX_N/DP_SRC_2_N
PA_LSTX/CIO_1_LSEO
PA_LSRX/CIO_1_LSOE
1
R3682
10K
10K
5%
1/20W
MF
201 2
5%
1/20W
MF
2 201
DP_TBTSRC_HPD
Y1
TBT_GPIO_9
TBT_GPIO_14
0
7
C2
35
1
7
DPSRC_HPD_OD
DPSNK1_HPD
TBT_DDC_XBAR_EN_L
7
DPSRC_AUX_P
DPSRC_AUX_N
DPSNK1_AUX_P
DPSNK1_AUX_N
R3697
7
TP_DP_TBTSRC_ML_CP & lt; 2 & gt;
TP_DP_TBTSRC_ML_CN & lt; 2 & gt;
B13
W2
J4
AA2
AB1
AC2
P3
M5
T3
V5
R24
N24
R22
N22
P1
H5
PB_CIO3_RX_P
PB_CIO3_RX_N
PB_LSTX/CIO_3_LSEO
PB_LSRX/CIO_3_LSOE
W24
U24
W22
U22
L6
G6
OUT
B19
F1
M3
H3
PA_DPSRC_1_P
PA_DPSRC_1_N
PA_DPSRC_3_P
PA_DPSRC_3_N
PB_DPSRC_1_P
PB_DPSRC_1_N
A20
PB_DPSRC_3_P
PB_DPSRC_3_N
A22
PA_AUX_P
PA_AUX_N
PA_DPSRC_HPD
GPIO_0/PA_HV_EN/BYP0
GPIO_10/PA_CIO_SEL/BYP1
GPIO_12/PA_DP_PWRDN/BYP2
PB_AUX_P
PB_AUX_N
B21
B23
D1
E2
PB_DPSRC_HPD
K3
GPIO_1/PB_HV_EN/BYP0
GPIO_11/PB_CIO_SEL/BYP1
GPIO_13/PB_DP_PWRDN/BYP2
M1
L2
L4
For unused port, pull CONFIG1, CONFIG2, LSRX, HPD and CIO_SEL low (10k).
10%
16V
X5R-CERM 0201
7
J24
93 84
DP_TBTSNK1_AUXCH_N
2
L24
OUT
7 35 95
DP_TBTSNK1_AUXCH_P
2
TBT_A_R2D_C_P & lt; 1 & gt;
TBT_A_R2D_C_N & lt; 1 & gt;
93 84
7 35 95
10%
16V
X5R-CERM 0201
0.1UF
V1
JTAG_TBT_TDI
JTAG_TBT_TMS
JTAG_TBT_TCK
JTAG_TBT_TDO
TBT_TEST_EN
TBT_TEST_PWR_GOOD
93 84
DP_TBTSNK1_ML_N & lt; 3 & gt;
2
IN
93 84
7 35 95
DP_TBTSNK1_ML_P & lt; 3 & gt;
2
OUT
84 37 35
95 83 7
92
1
16V
9 92
OUT
X5R-CERM 0201
35
7
7
BI
20
IN
20 25
OUT
18 42
OUT
20
BI
IN
R3632 1
100K
5%
1/20W
MF
201
CR HPD INPUTS (S4) FORWARDED TO GMUX (S0)
82 78 35 8
TBT_B_R2D_C_P & lt; 0 & gt;
TBT_B_R2D_C_N & lt; 0 & gt;
74LVC2G126GT/S500
8
TBT_EN_CIO_PWR_L
MAKE_BASE=TRUE
19
85 35
IN
DP_TBTPB_HPD
VCC
5
A
DP_TBTPB_HPD_BUF
OUT
OUT
4
IN
82 78 35 8
=PP3V3_S0_DPMUX_UC
1
7 85 93
7 85 93
IN
1K
2
100K
DP_TBTPB_HPD_BUF_EN
=PP3V3_S0_DPMUX_UC
82 85
NOSTUFF
U3610
85
OUT
7 85 93
OUT
5%
1/20W
MF
201 2
5%
1/20W
MF
201
82 78 35 8
OUT
1
R3644
NOSTUFF
R3642
7 85 93
7 85 93
82
OE
37
35 82
IN
TBT_B_R2D_C_P & lt; 1 & gt;
TBT_B_R2D_C_N & lt; 1 & gt;
3
Y
GND
7
OUT
OUT
TBT_B_CONFIG1_BUF
TBT_B_CONFIG2_RC
SOT833
44
35
B
NOSTUFF
U3610
44
TBT_PWR_REQ_L
OUT
TBT_B_D2R_P & lt; 0 & gt;
TBT_B_D2R_N & lt; 0 & gt;
=PP3V3_S0_DPMUX_UC
2
7 85 93
84 35
IN
DP_TBTPA_HPD
74LVC2G126GT/S500
SOT833
VCC
2
A
6
DP_TBTPA_HPD_BUF
OUT
Y
82
GND
OE
TBT_B_D2R_P & lt; 1 & gt;
TBT_B_D2R_N & lt; 1 & gt;
IN
TBT_B_LSTX
TBT_B_LSRX
4
7 85 93
IN
7 85 93
R36451
1
OUT
85
IN
100K
NOSTUFF
R3643
85
82 78 35 8
1
=PP3V3_S0_DPMUX_UC
1K
2
5%
1/20W
MF
201
DP_TBTPA_HPD_BUF_EN
2
7 35 95
DP_TBTSNK1_ML_N & lt; 2 & gt;
2
IN
93 84
DP_TBTSNK1_ML_P & lt; 2 & gt;
2
OUT
IN
84
DP_TBTSNK1_ML_N & lt; 1 & gt;
2
OUT
93 84 7
10%
16V
X5R-CERM 0201
0.1UF
OUT
93 84 7
10%
16V
X5R-CERM 0201
0.1UF
95 77 7
7 35 95
10%
16V
X5R-CERM0201
0.1UF
95 77 7
DP_TBTSNK1_ML_N & lt; 0 & gt;
2
10%
16V
X5R-CERM 0201
0.1UF
95 77 7
93 84 7
10%
16V
X5R-CERM 0201
0.1UF
A
93 84 7
7 35 95
10%
16V
X5R-CERM0201
0.1UF
95 77 7
DP_TBTSNK1_ML_P & lt; 0 & gt;
2
10%
16V
X5R-CERM0201
0.1UF
C3645
16V
PCIE_TBT_D2R_N & lt; 1 & gt;
2
9 92
OUT
PCIE_TBT_D2R_P & lt; 1 & gt;
2
10%
0.1UF
NO_TEST=TRUE
NO_TEST=TRUE
PCIE_TBT_D2R_C_P & lt; 3 & gt;
PCIE_TBT_D2R_C_N & lt; 3 & gt;
AD19
1
OUT
X5R-CERM 0201
9 92
8
10%
16V
X5R-CERM 0201
0.1UF
95 77 7
W4
DP_TBTSNK1_HPD
93 84 7
C3628
C3644
16V
10%
0.1UF
PCIE_TBT_D2R_C_P & lt; 2 & gt;
PCIE_TBT_D2R_C_N & lt; 2 & gt;
AD17
1
OUT
X5R-CERM 0201
7 35 95
10%
16V
X5R-CERM0201
0.1UF
DP_TBTSNK0_AUXCH_C_P
P5
AD3
2
10%
16V
X5R-CERM0201
0.1UF
95 83 7
EE_DI
EE_DO
EE_CS_N
EE_CLK
DP_TBTSNK0_HPD
95 35 7
95 77 7
TBT_SPI_MOSI
TBT_SPI_MISO
TBT_SPI_CS_L
TBT_SPI_CLK
1 S*
20
TBTROM_WP_L
92
PCIE_CLKREQ_OD_N
THERMDA
R4
Use AA8 GND ball for THERM_DN
M95256-RMC6XG
MLP
C
U3690
Y7
TP_TBT_THERM_DP
PCIE RESET
5
92
AD15
10%
0.1UF
C3643
16V
PCIE_TBT_D2R_N & lt; 0 & gt;
2
84 35
DEBUG: For monitoring clock
93
(TBT_SPI_MOSI)
AD13
MONOBS_P
MONOBS_N
CLOCKS
2
W16
DISPLAYPORT
2
W18
TBT_MONOBSP
TBT_MONOBSN
PORT2
8
VCC
CRITICAL
OMIT_TABLE
NONE
NONE
NONE
0201 2
5%
1/20W
MF
201
PORT3
2
NOSTUFF
3.3K
SOURCE PORT 0
R3693
5%
1/20W
MF
201
PORT0
2
1
3.3K
PORT1
2
R3692 1
C3642
2
PORTS
5%
1/20W
MF
201
1
1UF
10%
6.3V
CERM
402
PETP_2
PETN_2
1
0.1UF
PCIE_TBT_D2R_C_P & lt; 1 & gt;
PCIE_TBT_D2R_C_N & lt; 1 & gt;
DEBUG: For monitoring current/voltage
JTAG/TEST PORT
5%
1/20W
MF
201
C3690
3.3K
92
PCIE_TBT_D2R_P & lt; 0 & gt;
2
10%
1K
SINK PORT 0
R3691
R3615
C3641
NO_TEST=TRUE
NO_TEST=TRUE
NC
SINK PORT 1
1
3.3K
1
AC24
MONDC0
MONDC1
EEPROM
R3690 1
AD23
TP_TBT_MONDC0
TP_TBT_MONDC1
OMIT
10%
16V
X5R-CERM 2
0201
92
RBIAS
PERST_N
J2
MISC
0.1UF
AD9
AD11
PETP_3
PETN_3
NO STUFF
8 35 36 37
PETP_1
PETN_1
1
0.1UF
NO_TEST=TRUE
TBT_PCIE_RESET_L
IN
C3640
NO_TEST=TRUE
NO_TEST=TRUE
RSENSE
PERP_3
PERN_3
TBT_PWR_ON_POC_RST_L
=PP3V3_TBTLC_RTR
92
NO_TEST=TRUE
X5R-CERM 0201
37
AD7
PCIE_TBT_D2R_C_P & lt; 0 & gt;
PCIE_TBT_D2R_C_N & lt; 0 & gt;
(SYM 1 OF 2)
AB13
PCIE_TBT_R2D_P & lt; 2 & gt;
PCIE_TBT_R2D_N & lt; 2 & gt;
92
FCBGA
NO_TEST=TRUE
NO_TEST=TRUE
92
AD5
CACTUSRIDGE4C
AA12
PCIE_TBT_R2D_P & lt; 1 & gt;
PCIE_TBT_R2D_N & lt; 1 & gt;
2
0.1UF
47K
16V
10%
1
0.1UF
=PP3V3_S4_TBT
92
X5R-CERM 0201
92
C3605
PCIE_TBT_R2D_C_N & lt; 2 & gt;
16V
PETP_0
PETN_0
U3600
NO_TEST=TRUE
NO_TEST=TRUE
2
0.1UF
92 9
AA10
PERP_0
PERN_0
1
NO_TEST=TRUE
OMIT_TABLE
2
0.1UF
D
PCIE_TBT_R2D_P & lt; 0 & gt;
PCIE_TBT_R2D_N & lt; 0 & gt;
X5R-CERM 0201
92
C3603
PCIE_TBT_R2D_C_N & lt; 1 & gt;
16V
10%
0.1UF
92 9
92
X5R-CERM0201
AB9
2
0.1UF
92 9
16V
92
C3601
PCIE_TBT_R2D_C_N & lt; 0 & gt;
NO_TEST=TRUE
2
TRANSMIT
C3600
PCIE_TBT_R2D_C_P & lt; 0 & gt;
PCIE GEN2
IN
RECEIVE
92 9
2
3
6
5
4
DP_TBTPB_ML_C_P & lt; 1 & gt;
DP_TBTPB_ML_C_N & lt; 1 & gt;
OUT
OUT
85 93
DP_TBTPB_ML_C_P & lt; 3 & gt;
DP_TBTPB_ML_C_N & lt; 3 & gt;
OUT
85 93
OUT
85 93
DP_TBTPB_AUXCH_C_P
DP_TBTPB_AUXCH_C_N
BI
85 93
BI
5%
1/20W
MF
201
85 93
85 93
SYNC_MASTER=D2_KEPLER
SYNC_DATE=01/13/2012
PAGE TITLE
Thunderbolt Host (1 of 2)
DRAWING NUMBER
Apple Inc.
051-9589
R
DP_TBTPB_HPD
IN
OUT
85
OUT
35 85
All other port signals can be NC.
3
BRANCH
35 37 85
OUT
D
4.18.0
35 85
NOTICE OF PROPRIETARY PROPERTY:
TBT_B_HV_EN
TBT_B_CIO_SEL
TBT_B_DP_PWRDN
SIZE
REVISION
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
2
PAGE
36 OF 132
SHEET
35 OF 99
1
A
8
7
4
3
2
1
=PP1V05_TBTLC_RTR
???? mW (Single Port)
250 mW (Dual Port)
EDP: 1600 mA
=PP1V05_TBTCIO_RTR
C3700
1
1
10UF
20%
6.3V
CERM-X5R
0402-1
C3710
1
1.0UF
2
2
20%
10V
X5R-CERM
0201-1
C3711
1
1.0UF
2
20%
10V
X5R-CERM
0201-1
C3712
1
1.0UF
20%
10V
X5R-CERM
0201-1
2
C3713
1
1.0UF
2
20%
10V
X5R-CERM
0201-1
CRITICAL
C3714
1.0UF
2
20%
10V
X5R-CERM
0201-1
J10
J12
J14
J16
J8
K17
C3701
1
1
10UF
20%
6.3V
CERM-X5R
0402-1
C3715
1
C3716
1.0UF
2
2
20%
10V
X5R-CERM
0201-1
1
1.0UF
20%
10V
X5R-CERM
0201-1
2
C3717
T15
1.0UF
2
20%
10V
X5R-CERM
0201-1
U14
V7
W8
G10
G12
G14
G16
G18
H19
K19
M19
P19
T19
V15
V19
W12
W14
C
G8
H9
AD1
K13
K9
L12
L16
L8
M13
M17
M9
N12
N16
N8
P13
P17
P9
R12
R16
R8
T13
T17
T9
U12
U16
B
U8
V9
A2
A24
AA14
AA20
AA22
AA8
AB11
AB17
AB7
AC10
AC12
AC14
AC16
AC18
AC20
AC22
AC4
AC6
AC8
B1
B7
C10
C12
A
C14
C16
C18
C20
VCC1P0_ON
VCC1P0_ON
VCC1P0_ON
VCC1P0_ON
VCC1P0_ON
VCC1P0_ON
VCC1P0_ON
VCC1P0_ON
VCC1P0_ON
VCC1P0_ON
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
OMIT_TABLE
CACTUSRIDGE4C
FCBGA
(SYM 2 OF 2)
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
M7
K15
L10
C3740
L14
1.0UF
1.0UF
1.0UF
1.0UF
1.0UF
1.0UF
20%
10V
X5R-CERM
0201-1
20%
10V
X5R-CERM
0201-1
20%
10V
X5R-CERM
0201-1
20%
10V
X5R-CERM
0201-1
20%
10V
X5R-CERM
0201-1
20%
10V
X5R-CERM
0201-1
M11
M15
8
D
???? mW (Single-Port)
2700 mW (Dual-Port)
EDP: 1100 mA
K11
1
C3741
2
1
2
C3742
1
C3743
2
1
2
C3744
1
2
C3745
1
1
2
2
C3705
10UF
20%
6.3V
CERM-X5R
0402-1
N10
N14
P11
P15
R10
R14
T11
U10
V11
=PP3V3_TBTLC_RTR
W10
T7
C3770
C3771
1
1
C3772
C3773
1
1
C3774
1.0UF
L18
VCC3P3_DP
VCC3P3_DP
VCC3P3_DP
VCC3P3_DP
8 35 37
??? mW (Single-Port)
250 mW (Dual-Port)
EDP: 240 mA
P7
VCC3P3_CIO
VCC3P3_CIO
VCC3P3_CIO
VCC1P0_DPAUX
VCC1P0_DPAUX
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC1P0
VCC3P3
VCC3P3
VCC3P3
U3600
VCC
D
5
1.0UF
1.0UF
1.0UF
20%
10V
X5R-CERM
0201-1
20%
10V
X5R-CERM
0201-1
20%
10V
X5R-CERM
0201-1
20%
10V
X5R-CERM
0201-1
1
1
2
2
1.0UF
20%
10V
X5R-CERM
0201-1
C3760
10UF
H11
VCC3P3_DPAUX
N18
2
2
20%
6.3V
CERM-X5R
0402-1
C
H15
H17
H7
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.1 MM
37 35
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
2
H13
VOLTAGE=3.3V
MAKE_BASE=TRUE
VCC3P3_POC
2
R18
PP3V3_S4_TBT
GND
8
6
K7
=PP3V3_S4_TBT
EDP: 10 mA
C22
C3790
C24
R3790
1
0
2
=PP3V3_S4_TBT_R
8
5%
1/16W
MF-LF
402
1.0UF
C4
C6
20%
10V
X5R-CERM
0201-1
1
2
C8
D21
D23
E4
F11
F13
F15
F17
F19
F21
F23
F5
F7
B
F9
G20
H21
H23
J18
J20
K21
K23
L20
M21
M23
N20
P21
P23
R20
T21
T23
U18
V13
V17
V21
V23
Y11
Y13
Y15
Y17
Y19
SYNC_MASTER=D2_KEPLER
Y21
SYNC_DATE=01/13/2012
PAGE TITLE
Y23
Thunderbolt Host (2 of 2)
Y9
DRAWING NUMBER
Apple Inc.
051-9589
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
4.18.0
BRANCH
PAGE
37 OF 132
SHEET
36 OF 99
1
A
6
Q3880
C3880
1
470K
D
L3895
3.3UH-6.5A
PPVIN_SW_TBTBST
1
TBTBST:Y
C3860
20%
25V
X5R-CERM 2
0603
1
10%
25V
2 X5R
402
R3891
C3861
10UF
TBTBST_SNS1
TBTBST:Y
20%
25V
X5R-CERM 2
0603
1%
1/16W
MF-LF
402 2
TBTBST:Y
VIN
& lt; R1 & gt; TBTBST_EN_UVLO
1
R3881
25 EN/UVLO
330K
5%
1/16W
MF-LF
402 2
TBTBST_INTVCC
SSM6N37FEAPE
C3890
20%
10V
X5R-CERM 2
402
SOT563
5 G
S 1
TBTBST:Y
1
2.2UF
SSM6N37FEAPE
SOT563
2 G
TBTBST:Y
D 3
Q3805
C3891
TBTBST:Y
C3892
1
2.2UF
TBTBST:Y
1
1
2.2UF
TBTBST_VC_RC
TBTBST:Y
S 4
TBTBST:Y
IN
IN
R3892
TBT_A_HV_EN
85 35
TBT_B_HV_EN
1%
1/16W
MF-LF
402 2
SNS2
3
1
73.2K
R3894
C3893
28.7K
0.0033UF
1%
1/16W
MF-LF
2 402
1
SGND
1
PLACE_NEAR=C3895.1:2 mm
=PP15V_TBT_REG
MF-LF
402 2
TBTBST:Y
& lt; Ra & gt;
1
TBTBST_FBX
TBTBST:Y
NO STUFF
1
31
C3889
C3896
10UF
TBTBST:Y
& lt; Rb & gt;
POLY-TANT
1
2
10%
50V
2 X7R-CERM
0402
0.001UF
CASE-D3L
SGND shorted to
GND inside package,
no XW necessary.
C3899
1
20%
25V
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=0V
UVLO(falling) = 1.22 * (R1 + R2) / R2
UVLO(rising) = UVLO(falling) + (2uA * R1)
UVLO = 4.55V (falling), 4.95 (rising)
C3897
10%
2 25V
X5R
805
8 9
Vout = 15.47V
Max Current = 2A?
Freq = 300KHz
TBTBST:Y
1%
1/16W
MF-LF
402 2
5%
50V
2 CERM
402
1
10%
2 25V
X5R
1206-2
15.8K
100PF
GND
NO STUFF
C3895
10UF
R3896
GND_TBTBST_SGND
C
PDS540XF
TBTBST_VSNS
TBTBST:Y
TBTBST:Y R38951
137K
C3888
1%
10PF
1/16W
5%
50V
2 C0G-CERM
0402
C3894
10%
6.3V
2 CERM-X5R
402
& lt; R2 & gt;
1
1
0.33UF
1%
1/16W
MF-LF
402 2
10%
50V
2 X7R-CERM
0402
NC
34 SYNC
TBTBST:Y
D3895
PWRDI5
3
XW3895
SM
32 SS
1
2
10
35
36
FBX
1
CRITICAL
TBTBST:Y
TBTBST_SNS2
QFN
NC
49.9K
5%
50V
2 COG-CERM
0402
20%
10V
X5R-CERM 2
402
20%
10V
X5R-CERM 2
402
1
84 35
6
33 RT
TBTBST_SS
SNS1
30 VC
TBTBST_RT
R38931
68PF
2
5%
1/20W
MF
201 2
TBTBST:Y
C3887
1
0
2
TBTBST:Y
D 6
D
R38891
SW
U3890
4
23
24
37
Q3805
CRITICAL
TBTBST:Y
LT3957
28 INTVCC
TBTBST_VC
TBTBST_PWREN_L
TBTBST:Y
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
SWITCH_NODE=TRUE
DIDT=TRUE
1
200K
TBTBST_PWREN_DIV_L
TBTBST_BOOST
2
PIMB063T-SM
TBTBST:Y
1
10UF
TBTBST:Y
0.1UF
5%
1/16W
MF-LF
402 2
1
CRITICAL
TBTBST:Y
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
Voltage not specified here,
add property on another page.
2
4
8
TBTBST:Y
R38801
BOM options provided by this page:
TBTBST:Y - Stuffs 15V boost circuitry.
S
3
BGA
2
Thunderbolt 15V Boost Regulator
G
Signal aliases required by this page:
- =TBT_CLKREQ_L
- =TBT_RESET_L
SI8409DB
=PPVIN_SW_TBTBST
8-13V Input
Changes required
for 2S.
TBTBST:Y
3
-30V
+/-12V
-1.4V
46mOhm @ 4.5V Vgs
3.7A @ 70C
1
D
SI8409DB:
Vds(max):
Vgs(max):
Vgs(th):
Rds(on):
Id(max):
CRITICAL
TBTBST:Y
9 8
4
12
13
14
15
16
17
Power aliases required by this page:
- =PPVIN_SW_TBTBST
(8-13V Boost Input)
- =PP15V_TBT_REG
(15V Boost Output)
- =PP3V3_TBT_P3V3TBTFET
(3.3V FET Input)
- =PP3V3_TBTLC_FET
(3.3V FET Output)
- =PP3V3_S0_TBTPWRCTL
- =PP1V05_TBT_P1V05TBTFET (1.05V FET Input)
- =PP1V05_TBTLC_FET
(1.05V FET Output)
5
8
9
20
21
38
7
27
8
Page Notes
33UF-0.06OHM
Vout = 1.6V * (1 + Ra / Rb)
C
Supervisor & CLKREQ# Isolation
8
=PP3V3_S0_TBTPWRCTL
TBTBST:Y
6 D
C3800
1
=PP3V3_TBTLC_RTR
Q3888
5%
1/20W
MF
2 201
S
D
TBT_EN_LC_PWR
G 2
1 S
PP1V05_TBTLC
+ SENSE
- 0.7V
3
330K
5%
1/16W
MF-LF
2 402
Max Vgs: 10V
TBTBST_SHDN_DIV
TBTBST:Y
8
TBTBST:Y
1
R3887
2
3 D
330K
RESET*
MR*
4
TBT_PCIE_RESET_L
OUT
35
IN
SOT563
35
4 S
DLY = 60 ms +/- 20%
TBT_CLKREQ_L
8
IN
(OD)
Pull-ups provided by SB page.
G 5
SMC_DELAYED_PWRGD
EN
OUT
5
7
IN
41 42 70
MAKE_BASE=TRUE
THRM
PAD
GND
=TBT_CLKREQ_L
TBT_CLKREQ_ISOL_L
9
OUT
Q3888
SSM6N37FEAPE
5%
1/16W
MF-LF
2 402
DLY
6
17
2
TDFN
=TBT_RESET_L
IN
5%
1/20W
MF
201
SLG4AP016V
Platform (PCIe) Reset
25
R3888
R3807
100K
2
3
IN
1
U3800
10K
SOD-VESM-HF
CRITICAL
VDD
R3840
G 1
SSM3K15FV
35
2
1
Q3840
1
SOT563
1
10%
16V
X5R-CERM
0201
TBTBST:Y
SSM6N37FEAPE
8 35 36 37
0.1UF
TBT " POC " Power-up Reset
B
B
Intel investigating whether RC is sufficient.
36 35
=PP3V3_S4_TBT
1
3.3V TBT " LC " Switch
U3810
1UF
20%
6.3V
X5R
0201
2
1%
1/20W
MF
201
U3810
CRITICAL
36.5K2
1
TBT_EN_LC_3V3
C2
ON
Part
GND
C3811 1
Type
10%
6.3V
CERM 2
402
1
C3831
18.3 mOhm Typ
24 mOhm Max
QFN
3 CT
1
0.1UF
10%
2 25V
CERM
0402
MR* 4
TBTPOCRST_MR_L
TPS3808G25
Vt = 2.33V +/- 2%
Delay = 27.3ms
10%
25V 2
X5R
402
100K
SOT563
1
TBT_EN_LC_ISOL
5%
1/20W
MF
2 201
TBT_SW_RESET_L
IN
20
C3825
330PF
0
1.05V TBT " CIO " Switch
5%
1/20W
MF
201 2
99 37 8
37 36 35 8
1.05V TBT " LC " Switch
=PP1V05_S0_P1V05TBTFET
=PP3V3_TBTLC_RTR
R3820
U3815
=PP1V05_S0_P1V05TBTFET
TPS22924
A2
B2
A
CSP
VIN
VOUT
A1
B1
2
Part
TPS22924C
Type
Load Switch
R(on)
@ 1.0V
NOSTUFF
Q3825
20.3 mOhm Typ
28.6 mOhm Max
C3816 must be 10%
RC guarantees minimum 5ms to reach 0.5V
7
U3820
Part
G
C3820
1UF
TPS22920
Type
Load Switch
R(on)
@ 1.05V
8 mOhm Typ
11.5 mOhm Max
SYNC_MASTER=D2_KEPLER
Thunderbolt Power Support
DRAWING NUMBER
Apple Inc.
6
NOTICE OF PROPRIETARY PROPERTY:
S 1
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
5
051-9589
4
3
2
SIZE
D
REVISION
R
TBT_EN_CIO_PWR_L
IN
SYNC_DATE=01/13/2012
PAGE TITLE
20%
6.3V
2 X5R
0201
SOT563
2
1UF
35
VOUT
=PP1V05_TBTCIO_FET 8
Max Current = 4A (85C)
D2 ON
1
D 6
SSM6N37FEAPE
C3816 1
10%
6.3V
CERM 2
402
VIN
A1
B1
C1
GND
GND
1UF
20%
6.3V
X5R
0201
C2 ON
CSP
CRITICAL
TBT_EN_CIO_PWR
C1
1
5%
1/20W
MF
2 201
U3815
CRITICAL
C3815
A2
B2
C2
100K
=PP1V05_TBTLC_FET 8
Max Current = 2A (85C)
10%
16V
2 X7R-CERM
0201
U3820
TPS22920
1
D1
TBT_EN_LC_1V05
8
Q3825
SSM6N37FEAPE
R38161
99 37 8
R3830
THRM
PAD
GND
C3830 1
0.0047UF
Load Switch
R(on)
@ 2.5V
1UF
TBTPOCRST_CT
TPS22924C
8 17 18 19 20 25
35
TPS3808
C1
1
B1
OUT
G 5
R3811
C3810
=PP3V3_S0_PCH_GPIO
U3830
TBT_PWR_ON_POC_RST_L
S
B2
VOUT
RESET* 6
4
VIN
2 SENSE
Max Current = 2A (85C)
D
A1
Pull-up: R3610
8
3
A2
CRITICAL
VDD
=PP3V3_TBTLC_FET
CSP
7
TPS22924
=PP3V3_S0_P3V3TBTFET
5
8
4.18.0
BRANCH
PAGE
38 OF 132
SHEET
37 OF 99
1
A
8
7
6
5
4
3
2
1
D
D
J4400
20525-130E-01
F-RT-SM
SIGNAL_MODEL=EMPTY
BP4405 BEAD-PROBE SM
SIGNAL_MODEL=EMPTY
31
TP 1
TP 1
SIGNAL_MODEL=EMPTY
BP4401 BEAD-PROBE SM
BP4402 BEAD-PROBE SM
TP 1
TP 1
GND_VOID=TRUE
91 19
IN
91 19
IN
USB3_EXTB_TX_P
USB3_EXTB_TX_N
0.1UF
C4402
1
2
X5R-CERM 0201
SIGNAL_MODEL=EMPTY
91 19 7
516S0853
C4401
91 19 7
OUT
OUT
12
USB3_EXTB_RX_P
USB3_EXTB_RX_N
2
1%
J4410
5%
AXK732327G
1
12
1
17 7
9 7
25 7
24 7
IN
OUT
IN
OUT
OUT
8
8
2
3
4
5
6
7
8
9
10
11
95 77 7
SIGNAL_MODEL=EMPTY
1%
IN
BP4404 BEAD-PROBE SM
SIGNAL_MODEL=EMPTY
MF 201
95 77 7
TP 1
TP 1
IN
95 77 7
IN
95 77 7
IN
95 77 7
BP4403 BEAD-PROBE SM
R4404
GND_VOID=TRUE
GND_VOID=TRUE
7
HDMI_EG_DATA_C_P & lt; 0 & gt;
HDMI_EG_DATA_C_N & lt; 0 & gt;
GND_VOID=TRUE
GND_VOID=TRUE
10
HDMI_EG_DATA_C_P & lt; 1 & gt;
HDMI_EG_DATA_C_N & lt; 1 & gt;
GND_VOID=TRUE
GND_VOID=TRUE
IN
7 18 27 41 70
IN
7 18 27 34 40 41 70
IN
7 77
BI
15PF
1
2
HDMI_EG_DATA_C_P & lt; 2 & gt;
HDMI_EG_DATA_C_N & lt; 2 & gt;
GND_VOID=TRUE
GND_VOID=TRUE
IN
NP0-CERM
95 77 7
0201
IN
IN
95 77 7
25V
11
13
14
C
15
C4404
95 77 7
5%
8
12
GND_VOID=TRUE
IN
16
17
18
GND_VOID=TRUE
7 77
12
13
PM_SLP_S3_L
PM_SLP_S4_L
HDMI_EG_DDC_CLK
HDMI_EG_DDC_DATA
HDMI_HPD_L
USB3_EXTB_RX_RC_P
USB3_EXTB_RX_RC_N
5
9
C4403
2
4
GND_VOID=TRUE
GND_VOID=TRUE
6
97
NP0-CERM 0201
1/20W
1
97
97
GND_VOID=TRUE
33
=ENET_RESET_L
ENET_CLKREQ_L
SD_PWR_EN
SDCONN_STATE_CHANGE_RIO
USB_EXTB_OC_L
=PP1V5_S0_RIO
=PP3V3_S3_RIO
10% 16V
R4403
F-ST-SM
25
3
MF 201
2
25V
2
USB3_EXTB_TX_C_P
7 USB3_EXTB_TX_C_N
97 7
GND_VOID=TRUE
15PF
C
BI
GND_VOID=TRUE
0.1UF
1
2
X5R-CERM 0201
1
USB_EXTB_P
USB_EXTB_N
BI
10% 16V
1
1/20W
91 26 7
91 26 7
BP4406 BEAD-PROBE SM
19
HDMI_EG_CLK_C_P
HDMI_EG_CLK_C_N
14
OUT
7 42 82
20
21
15
16
92 17 7
17
18
92 17 7
19
22
PCIE_CLK100M_ENET_P
PCIE_CLK100M_ENET_N
20
IN
IN
23
24
8
=PP3V3_S4_RIO
=I2C_HDMIRDRV_SCL
=I2C_HDMIRDRV_SDA
OUT
23
24
92 17 7
OUT
28
92 17 7
IN
30
92 17 7
IN
GND_VOID=TRUE
GND_VOID=TRUE
PCIE_ENET_R2D_C_P
PCIE_ENET_R2D_C_N
GND_VOID=TRUE
GND_VOID=TRUE
25
26
29
=PP5V_S4_RIO
92 17 7
31
8
22
27
44
21
25
44
PCIE_ENET_D2R_P
PCIE_ENET_D2R_N
32
26
27
28
29
30
33
34
34
35
36
37
38
39
40
41
B
B
32
518S0829
A
SYNC_MASTER=D2_KEPLER
SYNC_DATE=01/13/2012
PAGE TITLE
RIO CONNECTOR
DRAWING NUMBER
Apple Inc.
051-9589
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
4.18.0
BRANCH
PAGE
44 OF 132
SHEET
38 OF 99
1
A
8
7
6
5
4
3
2
1
D
D
CRITICAL
PLACE_NEAR=J4501.9:3mm
R4599
CRITICAL
0.005
1%
1W
MF
0612
L4500
FERR-26-OHM-6A
PP3V3_S0_SSD_R
0603
1
C4501
1
1
MIN_LINE_WIDTH=0.6mm
MIN_NECK_WIDTH=0.25mm
VOLTAGE=3.3V
PP3V3_S0_SSD_FLT
MIN_LINE_WIDTH=0.6mm
MIN_NECK_WIDTH=0.25mm
VOLTAGE=3.3V
2
4
3
2
0.1UF
20%
10V
CERM
402
8
ISNS_SSD_P
ISNS_SSD_N
C4502
0.1UF
=PP3V3_S0_SSD
OUT
97 99
OUT
97 99
20%
10V
CERM
402
2
8
=PP3V3_S0_SATAMUX
1
514S0393
C
2
J4501
20%
10V
CERM
402
1
C4514
1
0.1UF
2
20%
10V
CERM
402
C4519
0.01UF
2
C
20%
16V
X7R-CERM
0402
Per PCIe spec, only TX side should have AC cap
SSD-J5
PLACE_NEAR=U4510.10:2 mm
1
R4505
F-RT-SM
PLACE_NEAR=U4510.6:2 mm
100K
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
OUT
1
10
6
OUT
9 92
A1_P
A1_N
9
SATAMUX_EN_L
IN
C4513
0.1UF
1
9 92
PCIE_SSD_D2R_N & lt; 0 & gt;
OUT
9 92
PCIE_SSD_R2D_C_P & lt; 0 & gt;
IN
PCIE_SSD_R2D_C_N & lt; 0 & gt;
IN
92 PCIE_SSD_R2D_MUX_IN_N
0.1UF
1
5%
1/20W
MF
2 201
2
=P3V3S0_EN
IN
2
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
C1_P 13
C1_N 12
91 SATA_SSD_D2R_MUX_OUT_P
C4516
0.01UF
1
2
SATA_HDD_D2R_P
10%
C4515
C4511
0.01UF
0.01UF
1
1
69 70
91 SATA_SSD_R2D_MUX_IN_N
C4510
0.01UF
1
25V
X7R
10%
91 SATA_SSD_D2R_MUX_OUT_N
5%
1/20W
MF
201
27
28
29
30
31
32
33
34
35
SIGNAL_MODEL=EMPTY
SM BEAD-PROBE BP4502
10% 16V
0201
X5R-CERM
91 SATA_SSD_R2D_MUX_IN_P
0
1 TP
SM BEAD-PROBE BP4501
16V
0201
X5R-CERM
25V
X7R
25V
X7R
25V
X7R
2
OUT
17 91
IN
BP4503
17 91
IN
SM BEAD-PROBE
17 91
17 91
402
SATA_HDD_R2D_C_P
2
SIGNAL_MODEL=EMPTY
1 TP
OUT
402
SATA_HDD_D2R_N
2
R4520
1
SIGNAL_MODEL=EMPTY
9 92
10%
C4512
1 TP
9 92
2
10%
25
OUT
92 PCIE_SSD_R2D_MUX_IN_P
OUT
10%
10K
17
IN
B1_P 17
B1_N 16
5% 1/20W
PCIE_SSD_D2R_P & lt; 0 & gt;
2 0
MF 201
R4517 1
92 PCIE_SSD_D2R_MUX_OUT_N
C0_P 15
C0_N 14
5
11
20
IN
CRITICAL
XSD
R4510
SSD_CLKREQ_L
SSD_RESET_L
SATA_PCIE_SEL
SMC_OOB1_RX_L
SMC_OOB1_TX_L
SSD_P3V3S0_EN
B0_P 19
B0_N 18
SEL
2
VQFN
THRM
PAD
IN
9 92
A0_P
A0_N
7
8
9 92
2 0
MF 201
5% 1/20W
U4510
IN
R4518 1
92 PCIE_SSD_D2R_MUX_OUT_P
CBTL02043ABQ
3
4
1
19
20
21
22
23
24
25
26
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
21
R4525
9 92
VDD
VDD
VDD
R4526
5%
1/16W
MF-LF
2 402
VSS
VSS
VSS
1
2
3
1
2 0
PCIE_SSD_D2R_P & lt; 1 & gt;
92 PCIE_SSD_D2R_C_P & lt; 1 & gt;
4 GND_VOID=TRUE
5% 1/20W
MF 201
5 GND_VOID=TRUE 92 PCIE_SSD_D2R_C_N & lt; 1 & gt;
1
2 0
PCIE_SSD_D2R_N & lt; 1 & gt;
5% 1/20W
MF 201
6
7 GND_VOID=TRUE
91 SATA_SSD_D2R_P
8 GND_VOID=TRUE
91 SATA_SSD_D2R_N
9
C4521 0.1UF 1
2
PCIE_SSD_R2D_C_P & lt; 1 & gt;
92 PCIE_SSD_R2D_P & lt; 1 & gt;
10 GND_VOID=TRUE
X5R-CERM
10% 16V
0201
11 GND_VOID=TRUE 92 PCIE_SSD_R2D_N & lt; 1 & gt; C4520 0.1UF
1
2
PCIE_SSD_R2D_C_N & lt; 1 & gt;
X5R-CERM
10% 16V
0201
12
13 GND_VOID=TRUE
91 SATA_SSD_R2D_P
14 GND_VOID=TRUE
91 SATA_SSD_R2D_N
15
16
PCIE_CLK100M_SSD_P
IN 17 92
17
PCIE_CLK100M_SSD_N
IN 17 92
18
B
C4505
0.1UF
CRITICAL
B
402
SATA_HDD_R2D_C_N
402
353S3361
PCIE/SATA GUMSTICK2 CONNECTOR
A
SYNC_MASTER=D2_KEPLER
SYNC_DATE=01/13/2012
PAGE TITLE
SSD CONNECTOR
DRAWING NUMBER
Apple Inc.
051-9589
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
4.18.0
BRANCH
PAGE
45 OF 132
SHEET
39 OF 99
1
A
8
7
6
D
5
4
3
2
1
D
USB Port Power Switch
Left USB Port A
8
=PP5V_S3_LTUSB
CRITICAL
PM_SLP_S4_L
CRITICAL
U4600
L4605
TPS2557DRB
SON
2 IN_0
3 IN_1
5%
1/16W
MF-LF
402
2
24
OUT USB_EXTA_OC_L
OUT1 6
OUT2 7
8 FAULT*
5.1K
ILIM 5
4 EN
GND
CRITICAL
C4692
1
C4696
0.47UF
10%
10V
X5R
0402
C4690
1
20%
6.3V
POLY-TANT
CASE-B2-SM1
1
2
2
10UF
220UF-35MOHM
2
1
1
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=5V
THRM
PAD
C4605
C4691
USB_ILIM_R
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=5V
1
CRITICAL
514-0804
CRITICAL
TCM0605-1
20%
16V
X7R-CERM
0402
USB3.0-J5
L4600
90-OHM-50MA
2
J4600
F-RT-TH
SYM_VER-1
C4695
91
1
1
USB_EXTA_MUXED_N
4
10UF
R46001
20%
10V
CERM
402
22.1K
Place L4605 and L4615 at connector pin
PP5V_S3_LTUSB_A_F
0.01UF
22.1K
1%
1/20W
MF
201 2
2
0603
USB_ILIM
0.1UF
20%
6.3V
X5R
603
2
PP5V_S3_LTUSB_A_ILIM
R46011
1
USB_PWR_EN
We can add protection to 5V if we want, but leaving NC for now
FERR-120-OHM-3A
9
R4690
1
20%
6.3V
X5R
603
91
91
2
2
USB_EXTA_MUXED_P
3
91
USB_LT1_N
USB_LT1_P
1%
1/16W
MF-LF
402 2
97
2
6 VBUS
5
3
4
NC
IO
NC
IO
70 41 38 34 27 18 7
97
97
1 GND
CURRENT LIMIT (R4600+R4601): 2.19A MIN / 2.76A MAX
C
97
USB3_EXTA_RX_RC_N
USB3_EXTA_RX_RC_P
USB3_EXTA_TX_C_N
USB3_EXTA_TX_C_P
D4600
USB/SMC Debug Mux
RCLAMP0502N
SLP1210N6
1
2
3
4
5
6
7
8
9
10
11
12
13
VBUS
DD+
GND
STDA_SSRXSTDA_SSRX+
GND_DRAIN
STDA_SSTXSTDA_SSTX+
SHLD
SHLD
SHLD
SHLD
C
CRITICAL
8
14
15
16
17
18
=PP3V42_G3H_SMCUSBMUX
SMC_DEBUG_YES
1
SMC_DEBUG_YES
IN
OUT
SMC_DEBUGPRT_RX_L
SMC_DEBUGPRT_TX_L
5
M+
4
M-
Y+
U4650
BP4602
12
1
Y-
2
BI
91 19
BI
USB_EXTA_P
USB_EXTA_N
7
D+
6
D-
8
2
SM
R4613
MF 201
GND_VOID=TRUE
PI3USB102ZLE
91 19
1
1/20W 1%
1
42 41
42 41
5%
1/16W
MF-LF
2 402
VCC
2
TQFN
CRITICAL
91 19
SMC_DEBUG_YES
OE*
SEL
OUT
15PF
NO_TEST=TRUE
USB3_EXTA_RX_N
5%
1
25V
2
C4613
NP0-CERM
1
0.1UF
20%
10V
CERM
402
SIGNAL_MODEL=EMPTY
SIGNAL_MODEL=EMPTY BEAD-PROBE
BP4604
BEAD-PROBE
SM
R4650
10K
9
C4650
1
0201
NO_TEST=TRUE
GND_VOID=TRUE
SMC_DEBUGPRT_EN_L
10
IN
41
91 19
SEL=0 Choose SMC
SEL=1 Choose USB
3
GND
OUT
12
USB3_EXTA_RX_P
NO_TEST=TRUE
1
1/20W 1%
2
NO_TEST=TRUE
R4612
MF 201
GND_VOID=TRUE
15PF
CRITICAL
SMC_DEBUG_NO
1
25V
2
C4612
D4610
1
0
5%
1/20W
MF
201
2
2
2
D4611
ESD0P2RF-02LS
TSSLP-2-1
GND_VOID=TRUE
CRITICAL
1
ESD0P2RF-02LS
NP0-CERM 0201
R4651
B
2
1
5%
TSSLP-2-1
B
2
SMC_DEBUG_NO
R4652
1
0
2
5%
1/20W
MF
201
SIGNAL_MODEL=EMPTY
SIGNAL_MODEL=EMPTY
BEAD-PROBE
BEAD-PROBE
BP4606
BP4605
IN
NO_TEST=TRUE
USB3_EXTA_TX_N
SM
C4610
GND_VOID=TRUE
0.1UF
1
2
NO_TEST=TRUE
1
91 19
1
SM
10% 16V
0201
X5R-CERM
C4611
USB3_EXTA_TX_P
0.1UF
1
2
10%
NO_TEST=TRUE
16V
0201
X5R-CERM
1
IN
1
91 19
NO_TEST=TRUE
GND_VOID=TRUE
SM
CRITICAL
D4612
SM
BP4608
BP4607
BEAD-PROBE
ESD0P2RF-02LS
CRITICAL
D4613
ESD0P2RF-02LS
BEAD-PROBE
SIGNAL_MODEL=EMPTY
TSSLP-2-1
TSSLP-2-1
1
SIGNAL_MODEL=EMPTY
A
1
SYNC_MASTER=D2_KEPLER
SYNC_DATE=01/13/2012
PAGE TITLE
USB 3.0 CONNECTORS
DRAWING NUMBER
Apple Inc.
051-9589
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
4.18.0
BRANCH
PAGE
46 OF 132
SHEET
40 OF 99
1
A
8
7
6
5
4
3
2
1
NOTE: Unused pins have " SMC_Pxx " names. Unused
pins designed as outputs can be left floating,
those designated as inputs require pull-ups.
L4901
78 42 8
30-OHM-1.7A
=PP3V3_S5_SMC
1
2
C4902
1
1UF
C4904
1
C4905
1
C4906
0.1UF
20%
10V
X5R-CERM 2
0603-1
D
C4903
1
2
0.1UF
0.1UF
20%
10V
CERM
402
20%
10V
CERM
402
20%
10V
CERM
402
2
2
2
1
R4902
61 43 42 7
2
LM4FSXAH5BB
BI
92 82 43 17 7
BI
92 82 43 17 7
BI
92 82 43 17 7
BI
92 25
IN
92 82 43 17 7
IN
25
IN
43 17 7
BI
43 18 7
OUT
43 25 18 7
IN
20
OUT
20
OUT
94 44
BI
94 44
BI
94 44
C
BI
94 44
BI
94 44 7
BI
94 44 7
BI
94 44
BI
94 44
BI
42
BI
42
BI
44 7
BI
44 7
BI
48
OUT
48
IN
48
OUT
48
IN
50
OUT
8
OUT
60
BI
60
BI
42
IN
42
IN
42
BI
42
OUT
42
IN
42
IN
42
B
IN
42
IN
70 42
OUT
LPC_AD & lt; 0 & gt;
LPC_AD & lt; 1 & gt;
LPC_AD & lt; 2 & gt;
LPC_AD & lt; 3 & gt;
LPC_CLK33M_SMC
LPC_FRAME_L
SMC_LRESET_L
LPC_SERIRQ
PM_CLKRUN_L
LPC_PWRDWN_L
SMC_RUNTIME_SCI_L
SMC_WAKE_SCI_L
SMBUS_SMC_0_S0_SCL
SMBUS_SMC_0_S0_SDA
SMBUS_SMC_1_S0_SCL
SMBUS_SMC_1_S0_SDA
SMBUS_SMC_2_S3_SCL
SMBUS_SMC_2_S3_SDA
SMBUS_SMC_3_SCL
SMBUS_SMC_3_SDA
SMBUS_SMC_4_ASF_SCL
SMBUS_SMC_4_ASF_SDA
SMBUS_SMC_5_G3_SCL
SMBUS_SMC_5_G3_SDA
(OD)
(OD)
(OD)
(OD)
(OD)
(OD)
(OD)
(OD)
(OD)
(OD)
(OD)
(OD)
(OD)
(OD)
B13
A13
C12
D11
H12
D12
C13
H13
G11
F13
F12
B12
E10
D13
M4
N2
N8
M8
L8
K8
N7
M7
N4
N3
SMC_FAN_0_CTL
SMC_FAN_0_TACH
SMC_FAN_1_CTL
SMC_FAN_1_TACH
TP_SMC_MPM5_LED_PWR
TP_SMC_MPM5_LED_CHG
L11
N12
N11
M11
PM6/FAN0PWM0
PM7/FAN0TACH0
PK6/FAN0PWM1
PK7/FAN0TACH1
PN2/FAN0PWM2
D10 PN3/FAN0TACH2
PN4/FAN0PWM3
PN5/FAN0TACH3
PN6/FAN0PWM4
PN7/FAN0TACH4
J4 PH2/FAN0PWM5
J2 PH3/FAN0TACH5
C4 PECI0RX
C6 PECI0TX
CPU_PECI_R
SMC_PECI_L
M13
L12
M5
J12
SMC_BIL_BUTTON_L
SMC_DP_HPD_L
SMC_PME_S4_WAKE_L
SMC_PME_S4_DARK_L
SMC_S4_WAKESRC_EN
SMC_LID
K6
PP0/IRQ116
PP1/IRQ117
PP2/IRQ118
PP3/IRQ119
PP4/IRQ120
PP5/IRQ121
PP6/IRQ122
PP7/IRQ123
ENET_ASF_GPIO
SMS_INT_L
SMC_BC_ACOK
G3_POWERON_L
PM_SLP_S3_L
PM_SLP_S4_L
PM_SLP_S5_L
SMC_ONOFF_L
D4
E4
F5
N5
N6
K5
M6
L6
PQ0/IRQ124
PQ1/IRQ125
PQ2/IRQ126
PQ3/IRQ127
PQ4/IRQ128
PQ5/IRQ129
PQ6/IRQ130
PQ7/IRQ131
SMC_RX_L
SMC_TX_L
L3 U0RX
M1 U0TX
J13
L5
NC
NC D8
49 42
42
IN
OUT
51 42
IN
60 42
IN
42
IN
70 38 27 18 7
IN
70 40 38 34 27 18 7
IN
70 18
IN
49 42
IN
43 42 7
IN
43 42 7
OUT
91 9
91 9
A
BI
BI
I2C0SCL
I2C0SDA
I2C1SCL
I2C1SDA
I2C2SCL
I2C2SDA
I2C3SCL
I2C3SDA
I2C4SCL
I2C4SDA
I2C5SCL
I2C5SDA
H11
L13
C11
A12
G3
SMC_SYS_KBDLED
SMC_T25_EN_L
SYS_TDM_ONEWIRE
SYS_ONEWIRE
HISIDE_ISENSE_OC
SMC_ODD_DETECT
BGA
E13 USB0DM
E12 USB0DP
USB_SMC_N
USB_SMC_P
AIN00
AIN01
AIN02
AIN03
AIN04
AIN05
AIN06
AIN07
AIN08
AIN09
AIN10
AIN11
AIN12
AIN13
AIN14
AIN15
AIN16
AIN17
AIN18
AIN19
AIN20
AIN21
AIN22
AIN23
E2
E1
F2
F1
B3
A3
B4
A4
B5
A5
B6
A6
C1
C2
B1
B2
G2
G1
H1
H2
B7
A7
B8
A8
C0C0+
C1PC5/C1+
T3CCP1/PJ5/C2T3CCP0/PJ4/C2+
K2
K1
L2
L1
C5
D5
SSI0CLK/PA2
SSI0FSS/PA3
SSI0RX/PA4
SSI0TX/PA5
M2
M3
L4
N1
LPC0AD0
(1 OF 2)
LPC0AD1
LPC0AD2
OMIT_TABLE
LPC0AD3
LPC0CLK
LPC0FRAME*
LPC0RESET*
LPC0SERIRQ
LPC0CLKRUN*
LPC0PD*
LPC0SCI*
PK5
1
C4908
U1RX/B0
U1TX/PB1
T0CCP0/PB6
T0CCP1/PB7
F11
E11
F4
F3
SSI1RX/PF0
SSI1TX/PF1
SSI1CLK/PF2
SSI1FSS/PF3
PF4
PF5
SMC_ADC0
SMC_ADC1
SMC_ADC2
SMC_ADC3
SMC_ADC4
SMC_ADC5
SMC_ADC6
SMC_ADC7
SMC_ADC8
SMC_ADC9
SMC_ADC10
SMC_ADC11
SMC_ADC12
SMC_ADC13
SMC_ADC14
SMC_ADC15
SMC_ADC16
SMC_ADC17
SMC_ADC18
SMC_ADC19
SMC_ADC20
SMC_ADC21
SMC_ADC22
SMC_ADC23
CPU_PROCHOT_L
SMC_VCCIO_CPU_DIV2
SMC_S5_PWRGD_VIN
SPI_DESCRIPTOR_OVERRIDE_L
CPU_CATERR_L
CPU_THRMTRIP_3V3
SMC_PM_G2_EN
PM_DSW_PWRGD
SMC_DELAYED_PWRGD
SMC_PROCHOT
M9
N9
L10
K10
L9
K9
(OD)
SMC_DEBUGPRT_RX_L
SMC_DEBUGPRT_TX_L
SMC_SYS_LED
SMC_GFX_THROTTLE_L
SPI_SMC_MISO
SPI_SMC_MOSI
SPI_SMC_CLK
SPI_SMC_CS_L
S5_PWRGD
PM_PCH_SYS_PWROK
WT0CCP0/PG4 K7
WT0CCP1/PG5 L7
SMC_DEBUGPRT_EN_L
SMC_GFX_OVERTEMP
WT2CCP0/PH0 K3
WT2CCP1/PH1 K4
ALL_SYS_PWRGD
SMC_THRMTRIP
WT3CCP0/PH4
WT3CCP1/PH5
WT4CCP0/PH6
WT4CCP1/PH7
J3
H4
H3
G4
PM_PWRBTN_L
PM_SYSRST_L
MEM_EVENT_L
SMC_ADAPTER_EN
T1CCP0/PJ0
T1CCP1/PJ1
T2CCP0/PJ2
T2CCP1/PJ3
C9
B9
A9
C8
WT5CCP1/PM3 H10
(OD)
(OD)
IN
42
IN
42
IN
42
IN
42
IN
42
IN
42
IN
42
IN
42
IN
(2 OF 2)
RST*
SWCLK/TCK
OMIT_TABLE
SWDIO/TMS
PK4/RTCCLK
SWO/TDO
WAKE*
TDI
HIB*
NC
XOSC0
XOSC1
VDDA
OSC0
OSC1
VREFA+
VREFAVBAT
42
IN
B11
N13
M12
42
IN
G10
WIFI_EVENT_L (OD)
SMC_WAKE_L
NC_SMC_HIB_L
42
IN
7
42
IN
2
42
IN
2
42
42
IN
7
42
42
SMC_CLK32K
NC_SMC_XOSC1
M10
SMC_EXTAL
SMC_XTAL
G12
G13
N10
K12
99 46 45 42
IN
42
IN
42
IN
42
IN
42
IN
42
IN
GNDA
C10
A10
A11
B10
A2
SMC_TCK 7
SMC_TMS 7
SMC_TDO 7
SMC_TDI 7
42 43
42 43
42 43
42 43
NC
D3
D2
D1
C3
E3
PP3V3_S5_AVREF_SMC
7 42
XW4900
SM
GND_SMC_AVSS
2
1
PLACE_NEAR=U4900.A1:4MM
VDD
GND
A1
C7
D9
E5
F9
H5
H9
J5
J8
J11
1
1
C4920
C4921
0.01UF
2
1UF
10%
10V
X5R-CERM
0201
10%
6.3V
2 CERM
402
42
IN
D7
E6
E8
E9
F10
J7
J9
J10
42
IN
D
402
BGA
42
IN
BI
20%
10V
CERM
402
42
IN
42 34 7
0.1UF
20%
10V
CERM
402
42
IN
0.1UF
20%
10V
CERM
402
2 CERM
LM4FSXAH5BB
5%
1/20W
MF
201
SMC_RESET_L
IN
C4909
0.1UF
U4900
92 82 43 17 7
1
C4907
C4901
20%
10V
U4900
1M
2
1
1
0.1UF
0.1UF
20%
10V
CERM
402
PP3V3_S5_SMC_VDDA
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.1 MM
VOLTAGE=3.3V
0402
1
11 42 65 89
42
NO STUFF
1
C4910
1UF
10%
25V
1
C4911
1UF
1
C4912
1UF
10%
25V
10%
25V
2 X5R
2 X5R
2 X5R
402
402
402
1
C4913
0.1UF
20%
10V
2 CERM
402
1
C4914
0.1UF
20%
10V
2 CERM
402
1
C4915
0.1UF
20%
10V
2 CERM
402
1
C4916
0.1UF
20%
10V
2 CERM
402
1
C4917
0.1UF
PP1V2_S5_SMC_VDDC
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.1 MM
VOLTAGE=1.2V
J1
J6
K13
D6
VDDC
C
K11
20%
10V
2 CERM
402
42
42
OUT
25 42
IN
11 89
IN
42
OUT
42 70
OUT
18
OUT
37 42 70
OUT
42
IN
40 42
OUT
40 42
OUT
42
BI
78
IN
42
OUT
42
OUT
42
OUT
70
IN
B
42
IN
18 24 70
OUT
40
IN
42 78
IN
24 70
OUT
42
OUT
18 24
OUT
BI
OUT
SMC_OOB1_RX_L
SMC_OOB1_TX_L
IR_RX_OUT_RC
BDV_BKL_PWM
OUT
SMC_BATLOW_L
IN
18 25
42
18 42 70
39
39 42
IN
42
OUT
42
OUT
42 70
NOTE: SMS Interrupt can be active high or low, rename net accordingly.
If SMS interrupt is not used, pull up to SMC rail.
SYNC_MASTER=D2_KEPLER
SYNC_DATE=01/13/2012
PAGE TITLE
SMC
DRAWING NUMBER
Apple Inc.
051-9589
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
4.18.0
BRANCH
PAGE
49 OF 132
SHEET
41 OF 99
1
A
8
7
6
5
4
SMC Reset " Button " , Supervisor & AVREF Supply
R5027
41 8
78 42
=PP3V3_S5_SMC
1
47
41
5%
1/16W
MF-LF
402
1
C5027
MEM_EVENT_L
1
NC_ENET_ASF_GPIO
MAKE_BASE=TRUE
NC_SMC_SYS_LED
SMC12 PECI SUPPORT
7
MAKE_BASE=TRUE
NC_MEM_EVENT_L
MAKE_BASE=TRUE
41
IR_RX_OUT_RC
NC_SMC_ODD_DETECT
=PPVCCIO_S0_SMC
7
MAKE_BASE=TRUE
100K
=CHGR_ACOK
61 45
5%
1/16W
MF-LF
402 2
=PPVIN_S5_SMCVREF
SMC_ODD_DETECT
41
R50001
4.7UF
20%
2 6.3V
X5R
402
8
SMC_SYS_LED
41
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.1 mm
VOLTAGE=3.42V
ENET_ASF_GPIO
41
PP3V42_G3H_SMC_SPVSR
2
2
3
SMC_BC_ACOK
41 42 60
HISIDE_ISENSE_OC
41
Q5030
MAKE_BASE=TRUE
NC_HISIDE_ISENSE_OC
SSM3K15AMFVAPE
MAKE_BASE=TRUE
41
SMC_ADC0
41
SMC_ADC1
8 42
CRITICAL
NC_IR_RX_OUT_RC
MAKE_BASE=TRUE
D 3
VESM
SMC_CPU_VSENSE
45
D
C5020 1
3
1
MAKE_BASE=TRUE
Mac Mini: 5V
Mobiles: 3.42V
V+
0.47UF
10%
6.3V
CERM-X5R 2
402
R5028
VIN
U5010
SMC_RESET_R_L
VREF-3.3V-VDET-3.0V
6
SMC_TPAD_RST_L
SMC_ONOFF_L
IN
7
4
SMC_MANUAL_RST_L
MR1*
MR2*
C5001
0
2
1
C5025
0.01UF
5%
1/10W
MF-LF
603
10%
16V
X7R-CERM
0402
7 41
1
2
2
10uF
SILK_PART=SMC_RST
C5028
C5026
SMC_ADC6
41
45
CPU_PROCHOT_L
BI
SMC_PECI_L
IN
1
2
SMC_PECI_L_R
5%
1/16W
MF-LF
402
From SMC
OMIT
1
1
41
41
99
SMC_ADC8
6
SMC_CHGR_BMON_ISENSE
46
D
MAKE_BASE=TRUE
5%
25V
NP0-C0G 2
402
R5031
NOSTUFF
SMC_SSD_ISENSE
SMC_ADC7
1
R5033
MAKE_BASE=TRUE
Q5059
2
330
5%
1/16W
MF-LF
NONE
NONE
NONE
402
2 402
SSM6N15FEAPE
SMC_CPU_HI_ISENSE
SOT563
46
MAKE_BASE=TRUE
41
SMC_ADC9
41
SMC_ADC10
SMC_OTHER_HI_ISENSE
46
R5034
MAKE_BASE=TRUE
SMC_P1V5MEM_ISENSE
1
45
MAKE_BASE=TRUE
41 45 46 99
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.1 mm
VOLTAGE=0V
MR1* and MR2* must both be low to cause manual reset.
Used on mobiles to support SMC reset via keyboard.
89 65 41 11
SMC_PBUS_VSENSE
1000PF
10%
16V
X7R-CERM
0402
GND_SMC_AVSS
PLACEMENT_NOTE=Place R5001 on BOTTOM side
41
46
0
MAKE_BASE=TRUE
0.01UF
20%
6.3V
X5R
603
2
45
SMC_DCIN_ISENSE
SMC_ADC5
41
NOSTUFF
1
D
S 2
R5032
SMC_DCIN_VSENSE
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.1 mm
VOLTAGE=3.3V
8
SMC_ADC4
G
1
46
MAKE_BASE=TRUE
MAKE_BASE=TRUE
PAD
GND
R5001
REFOUT
THRM
46
SMC_GPU_HI_ISENSE
SMC_ADC3
41
PP3V3_S5_AVREF_SMC
CRITICAL
2
1
5
(IPU)
DELAY
OMIT
RESET*
(IPU)
SN0903048
OUT
SMC_ADC2
41
7 41 43 61
41
9
IN
SMC_CPU_ISENSE
MAKE_BASE=TRUE
2 SMC_RESET_L
5%
1/20W
MF
201
DFN
49
49 42 41
0
1
SMC_ADC11
41
S
G
2
SMC_CPUVCCIO_ISENSE
41
SMC_PROCHOT
ADC10 AND ADC11 ARE SHARED WITH COMPARATORS ON STACK BOARD
IN
45
41
SMC_ADC12
41
SMC_ADC13
SMC_GFX_VSENSE
45
MAKE_BASE=TRUE
20
SMC_CPU_SA_ISENSE
1
PM_THRMTRIP_L_R
OUT
43
CPU_PECI
2
5%
1/16W
MF-LF
402
To SMC
MAKE_BASE=TRUE
NOTE: Internal pull-ups are to VIN, not V+.
CPU_PECI_R
OUT
41
11 20 89
BI
From/To CPU/PCH
45
MAKE_BASE=TRUE
41
PP1V2_S5_SMC_VDDC
41
SMC_ADC14
41
SMC_ADC15
3
SMC_GPU_CORE_VSENSE
45
D
MAKE_BASE=TRUE
SMC_PACKAGE:ENG
1
R5099
41
SMC_ADC16
5%
1/16W
MF-LF
41
SMC_LCDBKLT_VSENSE
SMC_ADC17
SMC_ONOFF_L
SMC_LCDBKLT_ISENSE
C
R5016
1
0
PLACE_SIDE=TOP
5%
1/10W
MF-LF
603
41 42 49
42 41
41
SMC_ADC23
2
PLACE_SIDE=BOTTOM
5%
1/10W
MF-LF
603
SMC_ADC19
SMC_THRMTRIP
99
41
SMC_CPU_SA_VSENSE
99
3
MAKE_BASE=TRUE
ENG PACKAGE REQUIRES 1.2V ON SMC_ADC23 PIN
41
SMC_ADC21
41
SMC_ADC22
SMC_PCH_CORE_ISENSE
99
=PPVCCIO_S0_SMC
SMC_ADC23
0
1
2
SMC_TBT_ISENSE
2
R5010
41
2.49K
2
1%
1/20W
MF
201
SMBUS_SMC_4_ASF_SDA
41
12PF
G 5
41
SMC_GFX_OVERTEMP
IN
SPI_SMC_CLK
IN
41
SPI_SMC_CS_L
1
SDCONN_STATE_CHANGE_SMC
R5012
18
22
1
41 39
PLACE_NEAR=U1800.N14:5.1mm
42 41
SMC_CLK32K
2
OUT
5%
1/20W
MF
201
41
49 42 41
41
42 41
12PF
49 42 41
CPU_THRMTRIP_3V3
OUT
43 41 7
CRITICAL
=PP3V3_S4_SMC
B
43 41 7
3
HDMI HPD ESD PROTECTION
Q5058
MMBT3904LP-7
DFN1006-3
1
3.3K 2
43 41 7
PM_THRMTRIP_L
5%
1/20W
MF
201
R5059
SMC USB CLOCK REQUIRE THESE CRYSTAL VALUES:5,6,8,10,12,16,18,20,24,25 MHZ
41 40
R5058
2
8 25 42
41 40
PM_THRMTRIP_B_L
1
1
100K
OUT
1
1K
2
41
51 41
42 41
HDMI_HPD_L
IN
7 38 82
41 25
5%
1/20W
MF
201
APN: 998-3029
=PP3V3_S4_SMC
1K for ESD protection
OMIT_TABLE
43 41 7
60 42 41
R5057
SMC_DP_HPD_L
11 20 89
41
5%
1/20W
MF
41
43 41 7
IN
43 41 7
2 201
Hall Effect pads
1
SMC_OOB1_TX_L
SMC_PME_S4_DARK_L
SMC_ONOFF_L
G3_POWERON_L
SMC_LID
SMC_TX_L
SMC_RX_L
SMC_DEBUGPRT_TX_L
SMC_DEBUGPRT_RX_L
SMC_TMS
SMC_TDO
SMC_TDI
SMC_TCK
SMC_BIL_BUTTON_L
SMC_BC_ACOK
SMC_S5_PWRGD_VIN
SMS_INT_L
CPU_THRMTRIP_3V3
SPI_DESCRIPTOR_OVERRIDE_L
43 7
SM
NC
6
5
1
2
1
2
1
2
NOSTUFF
1
NC
=PP3V42_S3_HALL
SMC_LID_R
7
R5050
1
0
SMC_LID
2
5%
1/16W
MF-LF
402
NC
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
C5050
=PSOC_WAKE_L
IN
34
MF
201
1/20W
MF
201
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
1/20W
MF
201
B
1K
5%
1/20W
MF
2 201
42 41
SMC_PME_S4_WAKE_L
SMC_THRMTRIP
R5086
10K
1
2
SMC_DELAYED_PWRGD
SMC_PM_G2_EN
SMC_ADAPTER_EN
SMC_S4_WAKESRC_EN
R5091
R5098
R5085
R5090
100K
100K
10K
100K
1
2
1
2
1
2
5%
=BT_WAKE_L
MAKE_BASE=TRUE
OUT
70 41 37
BATLOW# ISOLATION
=PP3V3_S5_SMCBATLOW
=PP3V3_SUS_SMC
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
5%
1/20W
MF
201
1/20W
MF
201
MF
201
41
70 41
0.001UF
8
70 41 18
70 41
1
2
8
PP3V3_WLAN
34 7
41 34 7
R5089
WIFI_EVENT_L
10K
1
2
5%
DESCRIPTION
REFERENCE DES
CRITICAL
1
SUBASSY,PCBA HALL EFFECT,K99
J5050
CRITICAL
BOM OPTION
100K
5%
1/20W
MF
201
70 41
IN
Q5040
2
SOD-VESM-HF
Internal 20K pull-up on PM_BATLOW_L in PCH.
PM_BATLOW_L
OUT
Apple Inc.
18
2
0
5%
1/16W
MF-LF
402
5
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
2
NOSTUFF
4
051-9589
3
2
SIZE
D
REVISION
R
R5041
1
6
SMC Support
DRAWING NUMBER
SMC_BATLOW_L
3
7
SYNC_DATE=01/13/2012
PAGE TITLE
1
SSM3K15FV
G
QTY
607-6811
SYNC_MASTER=D2_KEPLER
S
PART NUMBER
1/20W
1
D
R5040
8
1/20W
5%
5%
IN
49
41 42 49
10%
2 50V
X7R-CERM
0402
A
2
5%
5%
R5088
5%
1/20W
MF
201
7
100K
100K
10K
10K
100K
10K
100K
10K
100K
10K
10K
10K
10K
10K
470K
100K
10K
100K
10K
SMC_ROMBOOT
100K
3
4
R5068
R5069
R5070
R5072
R5071
R5073
R5074
R5075
R5076
R5077
R5078
R5079
R5080
R5081
R5087
R5092
R5093
R5094
R5095
8 25 42
R5082
HALL-SENSOR-MLB-PADS-K99
2
=PP3V3_S5_SMC
78 42 41 8
=PP3V3_S4_SMC
1
J5050
8
43 52
5%
PM_CLK32K_SUSCLK_R
IN
C5011
5%
50V
2 C0G-CERM
0402
OUT
SPI_MLB_CS_L
PLACE_NEAR=U6100.1:1MM
NO STUFF
4
1
43 52
PLACE_NEAR=U6100.6:1MM
42 25 8
1%
1/20W
MF
3
OUT
SPI_MLB_CLK
2
5%
1/16W
MF-LF
402
2
43 52
PLACE_NEAR=U6100.5:1MM
18 35
Inversion now taking place on RIO
1
33
OUT
C
43 52
25
=TBT_WAKE_L
MAKE_BASE=TRUE
2 201
5%
50V
2 C0G-CERM
0402
NC
1
33
IN
SPI_MLB_MOSI
R5023
R5024
IN
SPI_MLB_MISO
5%
1/16W
MF-LF
402
SMC_PME_S4_DARK_L
42 41
2
5%
1/16W
MF-LF
402
41 78
2
100K
NC
NC
C5010
S
33
12
5%
1/16W
MF-LF
402
R5096
Y5010
1
1
SPI_SMC_MOSI
IN
NC_BDV_BKL_PWM
1
3.2X2.5MM-SM-1
2
1
MAKE_BASE=TRUE
12.000MHZ-30PPM-10PF
1
4
7
BDV_BKL_PWM
41
SMC_VCCIO_CPU_DIV2
CRITICAL
SMC_EXTAL
41
MAKE_BASE=TRUE
SMC_XTAL_R
1%
1/20W
MF
201
NC_SMBUS_SMC_4_ASF_SDA
99
IN
5%
1/16W
MF-LF
402
7
MAKE_BASE=TRUE
100K
SMC Crystal Circuit
R5021
R5022
SOT563
SMC_TBT_ISENSE_R
NC_SMBUS_SMC_4_ASF_SCL
OUT
R5013
99
MAKE_BASE=TRUE
SMBUS_SMC_4_ASF_SCL
41
41 42
Q5057
SMC_PACKAGE:PROD
SMC_X29_ISENSE
IN
SPI_SMC_MISO
SSM6N15FEAPE
MAKE_BASE=TRUE
42 41
1
D
MAKE_BASE=TRUE
SILK_PART=PWR_BTN
R5097
41
5
46
SMC_GPU_P1V35_ISENSE
SMC_ADC20
41
1
SMC_XTAL
G
MAKE_BASE=TRUE
42 8
41
S
MAKE_BASE=TRUE
0
2
SMC_CPU_GFX_ISENSE
SMC_ADC18
R5015
SILK_PART=PWR_BTN
4
99
MAKE_BASE=TRUE
41
OUT
OMIT
1
SMC12 SPI SUPPORT
99
MAKE_BASE=TRUE
2 402
OMIT
SOT563
45
MAKE_BASE=TRUE
0
Debug Power " Buttons "
Q5059
SSM6N15FEAPE
SMC_GPU_CORE_ISENSE
4.18.0
BRANCH
PAGE
50 OF 132
SHEET
42 OF 99
1
A
8
7
6
5
4
3
2
1
D
D
LPC+SPI Connector
CRITICAL
LPCPLUS_CONN:YES
J5100
55909-0374
M-ST-SM
8
8
31
=PP3V3_S5_LPCPLUS
=PP5V_S0_LPCPLUS
32
1
43 7
OUT
IN
41 18 7
OUT
42 41 7
OUT
25 7
42 41 7
IN
OUT
7
7
42 41 7
IN
10
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
C
8
11
SPI_ALT_MOSI
SPI_ALT_MISO
LPC_FRAME_L
PM_CLKRUN_L
SMC_TMS
LPCPLUS_RESET_L
SMC_TDO
TP_SMC_TRST_L
TP_SMC_MD1
SMC_TX_L
IN
43 7
92 82 41 17 7
6
28
30
33
BI
LPC_CLK33M_LPCPLUS
LPC_AD & lt; 2 & gt;
LPC_AD & lt; 3 & gt;
4
9
LPC_AD & lt; 0 & gt;
LPC_AD & lt; 1 & gt;
BI
2
5
29
92 82 41 17 7
3
7
92 82 41 17 7
34
7 25 92
IN
BI
SPIROM_USE_MLB
SPI_ALT_CLK
SPI_ALT_CS_L
LPC_SERIRQ
LPC_PWRDWN_L
SMC_TDI
SMC_TCK
SMC_RESET_L
SMC_ROMBOOT
SMC_RX_L
LPCPLUS_GPIO
7 17 41 82 92
BI
7 17 41 82 92
7 20 52
BI
IN
7 43
IN
7 43
7 17 41
BI
7 18 25 41
IN
OUT
7 41 42
OUT
7 41 42
OUT
7 41 42 61
OUT
7 42
OUT
7 41 42
7 20
BI
C
516S0573
SPI Bus Series Termination
SPI_ALT_MISO
SPI_ALT_MOSI
SPI_ALT_CLK
SPI_ALT_CS_L
LPCPLUS_R:YES
1
R5128
12
PLACE_NEAR=U1800.AV3:5mm
IN
B
92 17
IN
92 17
IN
R5111
SPI_MOSI_R
R5112
1
15
2
OUT
92
2
92
33
1
PLACE_NEAR=J5100.14:5mm
PLACE_NEAR=J5100.12:5mm
PLACE_NEAR=J5100.9:5mm
PLACE_NEAR=J5100.11:5mm
1
R5123
1
60.4 2
1%
1/16W
MF-LF
402
SPI_MLB_CS_L
33
5%
1/16W
MF-LF
402
33
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
OUT
42 52
OUT
42 52
OUT
42 52
SPI_MLB_MISO
1
SPI_MOSI
2
SPI_MLB_MOSI
SPI_CLK
R5122
SPI_MISO
R5125
5%
1/16W
MF-LF
2 402
R5121
92
2
7 43
1
33
5%
1/16W
MF-LF
2 402
SPI_CS0_L
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
92 17
33
5%
1/16W
MF-LF
402
15
1
PLACE_NEAR=U1800.AY1:5mm
R5126
5%
1/16W
MF-LF
2 402
7 43
R5120
15
1
SPI_CLK_R
R5127
7 43
LPCPLUS_R:YES
R5110
SPI_CS0_R_L
PLACE_NEAR=U1800.BA2:5mm
LPCPLUS_R:YES
1
33
5%
1/16W
MF-LF
2 402
92 17
LPCPLUS_R:YES
1
7 43
IN
42 52
PLACE_NEAR=R5125.2:5mm
B
SPI_MLB_CLK
2
PLACE_NEAR=R5126.2:5mm
2
PLACE_NEAR=R5127.2:5mm
PLACE_NEAR=U6100.2:5mm
A
SYNC_MASTER=D2_KEPLER
SYNC_DATE=01/13/2012
PAGE TITLE
LPC+SPI Debug Connector
DRAWING NUMBER
Apple Inc.
051-9589
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
4.18.0
BRANCH
PAGE
51 OF 132
SHEET
43 OF 99
1
A
8
7
6
5
PCH SMBus " 0 " Connections
44 8
92 17
1
1K
5%
1/16W
MF-LF
402
U1800
(MASTER)
D
8
R5200 1
R5201
2
5%
1/16W
MF-LF
402
R5251
SMB_0_S0_CLK
94
41
SMB_0_S0_DATA
94
41
GPU Temp (Ext)
4.7K
5%
1/16W
MF-LF
402
U4900
(MASTER)
SMBUS_PCH_CLK
1
4.7K
5%
1/16W
MF-LF
402
2
2
R5280 1
SMC
EMC1414-A: U5550
(Write: 0x98 Read: 0x99)
SMBUS_SMC_0_S0_SCL
=PP3V42_G3H_SMBUS_SMC_5
47
SMB_5_CLK
=SMBUS_GPUTHMSNS_SDA
47
MAKE_BASE=TRUE
R5281
SMB_5_DATA
Battery Charger
2.0K
5%
1/16W
MF-LF
402
U4900
(MASTER)
=SMBUS_GPUTHMSNS_SCL
1
2.0K
5%
1/16W
MF-LF
402
2
2
ISL6258 - U7000
(Write: 0x12 Read: 0x13)
=SMBUS_CHGR_SCL
61
=SMBUS_CHGR_SDA
SMBUS_SMC_5_G3_SCL
MAKE_BASE=TRUE
TBT
SMBUS_PCH_DATA
1
SMC " 5 " SMBUS CONNECTIONS
8
R5250 1
MAKE_BASE=TRUE
92 17
2
=PP3V3_S0_SMBUS_SMC_0_S0
SMC
1K
2
3
SMC " 0 " SMBus Connections
=PP3V3_S0_SMBUS_PCH
Panther Point
4
61
D
MAKE_BASE=TRUE
SMBUS_SMC_0_S0_SDA
SMBUS_SMC_5_G3_SDA
MAKE_BASE=TRUE
MAKE_BASE=TRUE
U3600
(WRITE: 0xFE READ: 0xFF)
VRef DACs
=I2C_TBTRTR_SCL
35
U3300
(Write: 0x98 Read: 0x99)
=I2C_TBTRTR_SDA
35
33
=I2C_VREFDACS_SCL
33
GPU Temp (Int)
Battery
GK107: U8000
(Write: 0x9E Read: 0x9F)
VBIOS may overwrite as 0x82/0x83
GPU_SMB_CLK_R
78
=I2C_VREFDACS_SDA
GPU_SMB_DAT_R
J6950
(Write: 0x16 Read: 0x17)
=SMBUS_BATT_SCL
60
=SMBUS_BATT_SDA
78
60
SMC " 2 " SMBUS CONNECTIONS
Margin Control
NOTE: SMC RMT bus remains powered and may be active in S3 state
U3301
(Write: 0x30 Read: 0x31)
8
SMC " 3 " SMBUS CONNECTIONS
=PP3V3_S3_SMBUS_SMC_2_S3
The bus formerly known as " Battery B "
33
=I2C_PCA9557D_SCL
33
=I2C_PCA9557D_SDA
8
R5270 1
SMC
SMB_2_S3_CLK
R5271
Trackpad
1K
5%
1/16W
MF-LF
402 2
U4900
(MASTER)
Audio
1
1K
=PP3V3_S3_SMBUS_SMC_3
5%
1/16W
MF-LF
2 402
SMBUS_SMC_2_S3_SCL
=I2C_TPAD_SCL
R5290
SMC
J5800
(Write: 0x90 Read: 0x91)
U4900
(MASTER)
49
C
58
SMBUS_SMC_2_S3_SDA
SMB_3_CLK
49
94
41
MAKE_BASE=TRUE
R5291
4.7K
5%
1/16W
MF-LF
2 402
SMBUS_SMC_3_SCL
DEBUG SENSOR ADC A
UD100
(Write: 0x10 Read: 0x11)
=I2C_SMC_ADCS_SCL
98
=I2C_SMC_ADCS_SDA
98
C
MAKE_BASE=TRUE
=I2C_MIKEY_SCL
58
=I2C_TPAD_SDA
94
41
SMB_3_DATA
SMB_2_S3_DATA
Mikey (WRITE: 0X72 READ: 0X73)
China HS (WRITE: 0X76 READ: 0X77)
1
5%
1/16W
MF-LF
402 2
MAKE_BASE=TRUE
U6751 & U6750
1
4.7K
=I2C_MIKEY_SDA
SMBUS_SMC_3_SDA
MAKE_BASE=TRUE
J3502
ALS
(Write: 0x72 Read: 0x73)
XDP Connectors
=I2C_ALS_SCL
24
=SMBUS_XDP_SCL
24
=SMBUS_XDP_SDA
34
=I2C_ALS_SDA
J2500 & J2550
(MASTER)
34
SMS
U5920
(WRITE: 0X30/31 READ: 0X32/33)
GYRO
51
=I2C_SMC_SMS_SCL
51
=I2C_SMC_SMS_SDA
U5940
(WRITE: 0XD0 READ: 0XD1)
=I2C_SMC_GYRO_SCL
51
=I2C_SMC_GYRO_SDA
51
SMC " 1 " SMBUS CONNECTIONS
B
PCH " SMLink 0 " Connections
44 8
8
44 8
R5260
SMC
R5210
Panther Point
1
8.2K
5%
1/16W
MF-LF
402
U1800
(MASTER)
92 17
HDMI REDRIVER SMBUS CONNECTION
=PP3V3_S0_SMBUS_PCH
1
8.2K
5%
1/16W
MF-LF
402 2
5%
1/16W
MF-LF
402
2
SMB_1_S0_CLK
94
41
SMB_1_S0_DATA
2
1
1K
U4900
(MASTER)
R5211
94
41
1
R5261
1K
DPMUX IC
CPU/DDR3/PCH/AIRFLOW TEMP
5%
1/16W
MF-LF
2 402
EMC1414-A: U5570
(Write: 0x98 Read: 0x99)
SMBUS_SMC_1_S0_SCL
1
R5237
4.7K
HDMI Redriver (on RIO)
4.7K
5%
1/20W
MF
201 2
J4410 - & gt; U9700
5%
1/20W
MF
2 201
(WRITE: 0xCC READ: 0xCD)
82
7
I2C_DPMUX_A_SCL
=I2C_DPMUX_A_SDA
7
I2C_DPMUX_A_SDA
47
=I2C_CPUTHMSNS_SDA
=I2C_DPMUX_A_SCL
82
=I2C_CPUTHMSNS_SCL
SMBUS_SMC_1_S0_SDA
R52361
U9100
(MASTER)
47
=I2C_HDMIRDRV_SCL
38
=I2C_HDMIRDRV_SDA
38
MAKE_BASE=TRUE
MAKE_BASE=TRUE
SML_PCH_0_CLK
B
=PP3V3_S0_DPMUXI2C
=PP3V3_S0_SMBUS_SMC_1_S0
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
92 17
SML_PCH_0_DATA
MAKE_BASE=TRUE
44 8
=PP3V3_S0_DPMUXI2C
LED BACKLIGHT SMBUS CONNECTION
X29 TEMP
TMP105: U5523
(WRITE: 0X92 READ: 0X93)
PCH " SMLink 1 " Connections
44 8
DPMUX IC
U9100
(MASTER)
R5234
1
4.7K
=PP3V3_S0_SMBUS_PCH
=I2C_X29THMSNS_SCL
47
=I2C_X29THMSNS_SDA
47
5%
1/16W
MF-LF
402 2
1
R5235
LED BACKLIGHT
4.7K
U9700
5%
1/16W
MF-LF
2 402
(WRITE: 0x58 READ: 0x59)
82
NO STUFF
Panther Point
A
U1800
(Write: 0x88 Read: 0x89)
92 17
R5220
1
1
8.2K
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
SML_PCH_1_CLK
2
2
I2C_DPMUX_UC_SCL
=I2C_DPMUX_UC_SDA
I2C_DPMUX_UC_SDA
86
MAKE_BASE=TRUE
0
5%
1/16W
MF-LF
402
1
SML_PCH_1_DATA
86
=I2C_BKL_1_SDA
R5223
SYNC_MASTER=D2_KEPLER
1
SMBus Connections
2
DRAWING NUMBER
MAKE_BASE=TRUE
R5222
Apple Inc.
0
5%
1/16W
MF-LF
402
SMLink 1 is slave port to
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
7
051-9589
6
5
4
3
2
SIZE
D
REVISION
R
access PCH & CPU via PECI.
8
SYNC_DATE=01/13/2012
PAGE TITLE
2
MAKE_BASE=TRUE
92 17
=I2C_BKL_1_SCL
MAKE_BASE=TRUE
R5221
8.2K
=I2C_DPMUX_UC_SCL
82
NO STUFF
4.18.0
BRANCH
PAGE
52 OF 132
SHEET
44 OF 99
1
A
8
7
6
5
4
3
2
1
NOSTUFF
PBUS Voltage Sense Enable & Filter
80
CRITICAL
=PP3V3_S0_ISNS
98 45 8
99
1
IN
0.1UF
6
PBUSVSENS_EN_L
D
R5302
SENSOR_NONPROD:Y
1
EDP:50A
100K
G
2
1%
1/16W
MF-LF
402
S
D
1
3
V+
SMC Key VP0R
SMC_ADC5
1%
1/16W
MF-LF
402
S
=PPBUS_S0_VSENSE
4
1
4.53K
THRM
SMC_GPU_CORE_ISENSE
2
1%
1/20W
MF
201
4
C5308
1
0.22UF
9
RTHEVENIN = 4573 Ohms
Gain: 3.004x
SENSOR_NONPROD:Y
1
SMC_PBUS_VSENSE
R5301 1
1
5.49K
1%
1/16W
MF-LF
402
2
PBUSVSENS_EN_L_DIV
R5309
42
0.22UF
2
2
1M
1
2
1%
1/16W
MF-LF
402
20%
6.3V
X5R
402
SIGNAL_MODEL=EMPTY
GND_SMC_AVSS
PLACE_NEAR=U4900.L8:5MM
R5307
1%
1/16W
MF-LF
2 402
C5304
GND_SMC_AVSS
SENSOR_NONPROD:Y
499K
PLACE_NEAR=U4900.L8:5MM
R5304 1
100K
OUT
PLACE_NEAR=U4900.N11:5mm
20%
6.3V
X5R
0201
2
2
D
42
OUT
SENSOR_NONPROD:Y
PLACE_NEAR=U4900.L8:5MM
P-CHANNEL
1%
1/16W
MF-LF
402
GPUVCORE_IOUT
27.4K
G
5
1
V-
2
SMC Key IG0C
SMC_ADC15
R5308
DFN
PBUS_S0_VSENSE
GPUVCORE_INV
SENSOR_NONPROD:Y
PLACE_NEAR=U4900.N11:5mm
OPA2333
8
3
2
R5303 1
20%
10V
CERM
402
CRITICAL
U5310
Vimon=3x50A*(0.2/R8915)*R8912=1V
D
8
CRITICAL
C5310
2
=PBUSVSENS_EN
2
1%
1/20W
MF
201
SENSOR_NONPROD:Y
SOT-963
70
4.53K
1
Q5300
N-CHANNEL
R5310
GFXIMVP6_IMON
IN
NTUD3169CZ
Enables PBUS VSense
divider when in S0.
PLACE_NEAR=U4900.N11:5mm
GPU VCore Load Side Current Sense / Filter
41 42 45 46 99
DC-In Voltage Sense Enable & Filter
5%
1/20W
MF
2 201
SOT-963
Enables DC-In VSense
divider when AC present.
N-CHANNEL
96 67
6
IN
CPUVCCIOS0_CS_P
DCINVSENS_EN_L
D
DCINVSENS_EN
1%
1/16W
MF-LF
402
S
1
R5316
1
0
3
Enables DC-In VSense
5%
1/20W
MF
divider when SUS present.
2 201
PM_SUS_EN
8
IN
70
96 67
R53131
30.9K
1%
1/16W
MF-LF
402 2
S
V+
CPUVCCIOS0_CS_N
1
6.49K
THRM
ISENSE_CPUVCCIO_IOUT
SENSOR_NONPROD:Y
R5325
2
4.53K
4
CPUVCCIOISNS_R_N
1
1
SMC_CPUVCCIO_ISENSE
2
1%
1/16W
MF-LF
402
9
2 96
OUT
C5327
0.22UF
Gain: 154x
2
SENSOR_NONPROD:Y
R5326
1
C
PLACE_NEAR=U4900.L12:5mm
20%
6.3V
X5R
402
GND_SMC_AVSS
1M
1%
1/16W
MF-LF
402
42
OUT
SENSOR_NONPROD:Y
1
41 42 45 46 99
2
1%
1/16W
MF-LF
402
SIGNAL_MODEL=EMPTY
42
PLACE_NEAR=U4900.N9:5MM
R5314
1
5.36K
PDCINVSENS_EN_L_DIV
CPU SA Current Sense / Filter
C5314
2
=PP3V3_S0_ISNS
99 98 45 8
0.22UF
1%
1/16W
MF-LF
402 2
2
20%
6.3V
X5R
402
1
41 42 45 46 99
CRITICAL
U5360
Vi=Voltage across R7140=0.006V
R5363
96 62
CPU Vcore Voltage Sense / Filter
XW5320
2
CPUVSENSE_IN
1%
1/16W
MF-LF
402
PLACE_NEAR=R7510.2:5 MM
SMC_CPU_VSENSE
2
OUT
2
VCCSAISNS_R_P
VCCSAS0_CS_N
1
1.82K
C5320
2
V+
ISENSE_SA_IOUT
1
4.53K
SMC_CPU_SA_ISENSE
2
1%
1/16W
MF-LF
402
4
1
2
GAIN:549X
1
R5365
2
1%
1/16W
MF-LF
402
1M
1
OUT
42
PLACE_NEAR=U4900.M10:5mm
20%
6.3V
X5R
402
GND_SMC_AVSS
R5366
1M
C5367
0.22UF
VCCSAISNS_R_N
20%
6.3V
X5R
402
GND_SMC_AVSS
1
9
2 96
SMC Key IC2C
SMC_ADC13
R5367
VTHRM
0.22UF
PLACE_NEAR=U4900.N10:5MM
20%
10V
X7R-CERM
0402
PLACE_NEAR=U4900.M10:5mm
DFN
3
2
1%
1/16W
MF-LF
402
42
2
OPA2333
8
96
R5364
IN
PLACE_NEAR=U4900.N10:5MM
1
1.82K
1
1%
1/16W
MF-LF
402
96 62
4.53K
1
VCCSAS0_CS_P
SMC Key VC0C
SMC_ADC0
R5320
SM
1
IN
C5360
0.1UF
EDP:6A
GND_SMC_AVSS
B
7
Divider set for Vin max of 22.32V
RTHEVENIN = 4567 Ohms
1
=PPVCORE_S0_CPU
R5327
PLACE_NEAR=U4900.N9:5MM
100K
98 15 13 8
SENSOR_NONPROD:Y
V-
6
SMC KEY VD0R
PLACE_NEAR=U4900.N9:5MM
SMC_ADC3
SMC_DCIN_VSENSE
1
5
1M
P-CHANNEL
1%
1/16W
MF-LF
402
CPUVCCIOISNS_R_P
DCIN_S5_VSENSE
4
R5311
96
1%
1/16W
MF-LF
402
G
5
IN
2
D
=PPDCIN_S5_VSENSE
2
SMC Key IC1C
SMC_ADC11
PLACE_NEAR=U4900.L12:5mm
OPA2333
DFN
R5324
100K
G
2
1
1%
1/16W
MF-LF
SENSOR_NONPROD:Y 402
R5312 1
C
6.49K
8
NC
0
R5323
NTUD3169CZ
NC
R5315
CRITICAL
U5310
SENSOR_NONPROD:Y
Q5310
1
SENSOR_NONPROD:Y
NC
Vi=Voltage across R7640=0.02139V
42 61
IN
CPU 1.05V VCCIO Current Sense / Filter
EDP:21.329A
CRITICAL
=CHGR_ACOK
NOSTUFF
B
41 42 45 46 99
2
1%
1/16W
MF-LF
402
41 42 45 46 99
SIGNAL_MODEL=EMPTY
GFX Vcore Voltage Sense / Filter
2
GFXVSENSE_IN
1
SMC_GFX_VSENSE
2
1%
1/16W
MF-LF
402
PLACE_NEAR=R7550.2:5 MM
1
OUT
1
2
C5308
SENSOR_NONPROD:N
EDP CURRENT:8A
SMC_GPU_CORE_VSENSE
2
1%
1/16W
MF-LF
402
PLACE_NEAR=R8940.1:5 MM
RES,MF,1/20W,100K OHM,5,0201,SMD
DDR3 1.5V DRAM ONLY CURRENT SENSE / FILTER
41 42 45 46 99
IN
=PPVIN_S3_MEM_ISNS_R
SMC KEY VG0C
SMC_ADC14
4.53K
1
SENSOR_NONPROD:N
1
20%
6.3V
X5R
402
R5335
GPUVSENSE_IN
OUT
0612
MF
1W
1%
42
96
96
1 3
8
OUT
7.32K
2
8
96
ISNS_1V5_MEM_R_P
ISNS_1V5_MEM_P
1%
1/16W
MF-LF
402
V+
1
7.32K
1%
1/16W
MF-LF
402
=PPVIN_S3_MEM_ISNS
THRM
SMC KEY IM0C
SMC_ADC10
PLACE_NEAR=U4900.N13:5mm
OPA2333
R5377
7
ISENSE_P1V5MEM_IOUT
V-
6
R5374
ISNS_1V5_MEM_N
CRITICAL
U5360
DFN
5
4
CRITICAL
20%
6.3V
X5R
402
GND_SMC_AVSS
2
1
0.003
C5335
0.22UF
2
R5373
R5360
PLACE_NEAR=U4900.L10:5MM
1
PLACE_NEAR=U4900.L10:5MM
1
4.53K
1%
1/16W
MF-LF
402
4
ISNS_1V5_MEM_R_N
1
R5375
5
1
2
1%
1/16W
MF-LF
402
4
C5377
42
DRAWING NUMBER
PLACE_NEAR=U4900.N13:5mm
Apple Inc.
3
051-9589
42 45 46 99
NOTICE OF PROPRIETARY PROPERTY:
2
SIZE
D
REVISION
R
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
SIGNAL_MODEL=EMPTY
SYNC_DATE=03/05/2012
PAGE TITLE
20%
6.3V
X5R
402
GND_SMC_AVSS 41
1M
1
1%
1/16W
MF-LF
402
SYNC_MASTER=D2_SEAN
OUT
Voltage & Load Side Current Sensing
2
R5376
1M
41 42 45 46 99
6
SMC_P1V5MEM_ISENSE
0.22UF
GAIN:136.6X
Gain: 182x
7
2
9
2 96
2
8
BOM OPTION
117S0008
8
SM
CRITICAL
C5327
42
GPU Vcore Voltage Sense / Filter
XW5335
REFERENCE DES
RES,MTL FILM,100K,5,1/16W,0402,SMD,LF
C5330
GND_SMC_AVSS
=PPVCORE_GPU_REG
DESCRIPTION
1
0.22UF
2
8
QTY
PLACE_NEAR=U4900.N12:5MM
PLACE_NEAR=U4900.N12:5MM
A
PART NUMBER
116S0114
4.53K
NC
SM
1
SMC Key VN0C
SMC_ADC12
R5330
NC
XW5330
NC
66 8
=PPVCORE_S0_AXG_REG
4.18.0
BRANCH
PAGE
53 OF 132
SHEET
45 OF 99
1
A
8
7
6
5
4
3
2
1
COMPUTING High Side Current Sense / Filter
SIGNAL_MODEL=EMPTY
=PP3V3_S0_HS_ISNS
46 8
SENSOR_NONPROD:Y
1
C5401
0.1UF
3
EDP Current:20.1A
8
2
=PPVIN_S5_HS_COMPUTING_ISNS
OUT
V+
0612
MF
1W
1%
96
2
ISNS_HS_COMPUTING_N
ISNS_HS_COMPUTING_P
0.003
4 IN+
SC70
6
HS_COMPUTING_IOUT
1
4.53K
SMC_CPU_HI_ISENSE
2
1%
1/16W
MF-LF
402
REF 1
1 3
CRITICAL
OUT
42
97 66 65
IN
C5403
1
20%
6.3V
X5R
2
97 66 65
IN
CPUIMVP_ISNS2_P
1
2
0.5%
1/16W
MF
402
97 66
IN
5.23K
1
=PP3V3_S0_HS_ISNS
1
3
EDP Current:4.9A
2
V+
=PPVIN_S5_HS_GPU_ISNS
0612
MF
1W
1%
4
96
96
0.003
C5411
0.1UF
1
HS_GPU_IOUT
SC70
4.53K
2
SMC_GPU_HI_ISENSE
1%
1/16W
MF-LF
402
REF 1
OUT
IN
C5413
1
CPUIMVP_ISUM_IOUT
1%
1/16W
MF-LF
402
V-
-
SMC_CPU_ISENSE
2
2
1
42
C5451
0.22UF
SENSOR_NONPROD:Y
1
OUT
SENSOR_NONPROD:Y
PLACE_NEAR=U4900.M11:5MM
GND_SMC_AVSS
R5455
R5454
1
732K
41 42 45 46 99
2
732K
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
2 402
20%
6.3V
X5R
402
Gain:140x
SIGNAL_MODEL=EMPTY
Scale: 28.55A / V
Max VOut: 3.3V at 94.2A
R5472
CPUIMVP_ISNS3_N
1
5.23K
2
SIGNAL_MODEL=EMPTY
0.5%
1/16W
MF
402
Sense R is R7510, R7520 & R7530
Individual Sense R is 0.75mOhm
0.22UF
20%
6.3V
X5R
2 402
2
4.53K
4
2
2
PLACE_NEAR=U4900.K9:5MM
1
PLACE_NEAR=U4900.M11:5MM
R5451
SC70-5
CPUIMVP_ISUM_R_N
1%
1/16W
MF-LF
402
0.5%
1/16W
MF
402
SIGNAL_MODEL=EMPTY
42
EDP: 94A
Gain:200x
C
1
SENSOR_NONPROD:Y
97 66
GND
=PPVIN_S5_HS_GPU_ISNS_R
CPUIMVP_ISNS2_N
SIGNAL_MODEL=EMPTY
R5413
1 3
IN
2 97
5.23K
PLACE_NEAR=R7530.4:5MM
4 IN+
ISNS_HS_GPU_P
IN
PLACE_NEAR=U4900.K9:5MM
OUT 6
CRITICAL
5 IN-
ISNS_HS_GPU_N
97 66
SMC Key IG0R
SMC_ADC2
20%
10V
CERM
402
INA210
CRITICAL
8
3.48K
R5471
SENSOR_NONPROD:Y
U5410
R5410
2
3
1
OPA333DCKG4
5
+
V+
SENSOR_NONPROD:Y
PLACE_NEAR=R7520.4:5MM
OUT
1
R5453
CPUIMVP_ISNS_N
2
0.5%
1/16W
MF
402
SENSOR_NONPROD:Y
8
CPUIMVP_ISUM_R_P
97
1%
1/16W
MF-LF
402
R5470
CPUIMVP_ISNS1_N
SIGNAL_MODEL=EMPTY
46 8
2
SENSOR_NONPROD:Y
PLACE_NEAR=R7510.4:5MM
GRAPHICS High Side Current Sense / Filter
3.48K
1
SMC_ADC1
SENSOR_NONPROD:Y
U5450
R5452
CPUIMVP_ISNS_P
96
D
SMC Key IC0C
CRITICAL
SENSOR_NONPROD:Y
5.23K
41 42 45 46 99
20%
10V
2 X7R-CERM
0402
SENSOR_NONPROD:Y
1
C5450
0.1UF
2
0.5%
1/16W
MF
402
R5458
CPUIMVP_ISNS3_P
SIGNAL_MODEL=EMPTY
GND_SMC_AVSS
SENSOR_NONPROD:Y
PLACE_NEAR=U5450.5:3MM
1
SIGNAL_MODEL=EMPTY
5.23K
PLACE_NEAR=R7530.3:5MM
2 402
=PP3V3_S0_IMVPISNS
46 8
SENSOR_NONPROD:Y
R5457
SENSOR_NONPROD:Y
0.22UF
=PPVIN_S5_HS_COMPUTING_ISNS_R
IN
2
PLACE_NEAR=U4900.N8:5MM
GND
Gain:50x
8
OUT
IN
1
PLACE_NEAR=R7520.3:5MM
R5403
CRITICAL
96
Power Drop across R5400 at EDP becomes 1.21W
5 IN-
5.23K
CPUIMVP_ISNS1_P
0.5%
1/16W
MF
402
PLACE_NEAR=U4900.N8:5MM
INA213
4
97 66 65
CPU VCore Load Side Current Sense / Filter
R5456
PLACE_NEAR=R7510.3:5MM
SMC_ADC8
20%
10V
CERM
402
U5400
R5400
D
SMC Key IC0R
GND_SMC_AVSS
TDP :45A
C
(Effective Sense R is 0.25mOhm due to summing of the 3 phases)
41 42 45 46 99
OTHER High Side Current Sense / Filter
46 8
GFX/IG VCore Load Side Current Sense / Filter
=PP3V3_S0_HS_ISNS
1
EDP Current:12.546A
8
OUT
SMC Key IO0R
C5431
3
0.1UF
=PPVIN_S5_HS_OTHER_ISNS
2
V+
R5430
0612
MF
1W
1%
0.005
2
96
96
ISNS_HS_OTHER_N
ISNS_HS_OTHER_P
1 3
5 IN-
97 66
OUT
CRITICAL
SC70
6
HS_OTHER_IOUT
1
4.53K
2
1%
1/16W
MF-LF
402
SMC_OTHER_HI_ISENSE
REF 1
2
=PPVIN_S5_HS_OTHER_ISNS_R
OUT
5.23K
1
=PP3V3_S0_IMVPISNS
SENSOR_NONPROD:Y
PLACE_NEAR=U5460.5:3MM
1
2
SENSOR_NONPROD:Y
PLACE_NEAR=R7550.3:5MM
96 66
CPUIMVP_ISNS1G_P
IN
1
5.23K
SIGNAL_MODEL=EMPTY
1
5.49K
2 97
CPUIMVP_ISUMG_R_P
1
V+
SENSOR_NONPROD:Y
41 42 45 46 99
SENSOR_NONPROD:Y
PLACE_NEAR=R7550.4:5MM
96 66
IN
B
R5467
CPUIMVP_ISNS1G_N
1
SIGNAL_MODEL=EMPTY
PLACE_NEAR=R7560.4:5MM
97 66
2
CPUIMVP_ISNS1G_R_N
1
0.5%
1/16W
MF
402
5.49K
2
SIGNAL_MODEL=EMPTY
5.23K
R5461
SC70-5
4
CPUIMVP_ISUMG_IOUT
1
4.53K
1%
1/16W
MF-LF
402
2
SENSOR_NONPROD:Y
1%
1/16W
MF-LF
402
SENSOR_NONPROD:Y
OUT
42
PLACE_NEAR=U4900.M13:5MM
1
C5461
0.22UF
20%
6.3V
X5R
402
GND_SMC_AVSS
B
41 42 45 46 99
R5465
1
2
SENSOR_NONPROD:Y
0.5%
1/16W
MF
402
1
TDP: 21.5A
732K
1%
1/16W
MF-LF
402
Gain:90.31x
2
SIGNAL_MODEL=EMPTY
R5464
732K
SENSE R IS R7550, R7560, 0.75MOHM
EDP: 33A
SMC_CPU_GFX_ISENSE
2
2
CPUIMVP_ISUMG_R_N
R5469
1
PLACE_NEAR=U4900.M13:5MM
V-
-
SMC_ADC18
SENSOR_NONPROD:Y
OPA333DCKG4
R5463
SENSOR_NONPROD:Y
CPUIMVP_ISNS2G_N
IN
5.23K
+
1%
1/16W
MF-LF
402
3
GND_SMC_AVSS
5
SMC Key IN0C
20%
10V
X7R-CERM
0402
U5460
R5462
CPUIMVP_ISNS1G_R_P
2
0.5%
1/16W
MF
402
Gain:50x
CRITICAL
SENSOR_NONPROD:Y
R5466
0.22UF
C5460
0.1UF
SENSOR_NONPROD:Y
C5433
20%
6.3V
X5R
402
46 8
2
0.5%
1/16W
MF
402
42
PLACE_NEAR=U4900.L7:5MM
GND
IN
1
SIGNAL_MODEL=EMPTY
2
4 IN+
R5468
CPUIMVP_ISNS2G_P
IN
R5433
INA213
CRITICAL
8
PLACE_NEAR=R7560.3:5MM
PLACE_NEAR=U4900.L7:5MM
U5430
4
SENSOR_NONPROD:Y
SMC_ADC9
20%
10V
CERM
402
2
1%
1/16W
MF-LF
402
SIGNAL_MODEL=EMPTY
CHARGER BMON HIGH SIDE (BATTERY DISCHARGE) CURRENT SENSE & FILTER
PART NUMBER
116S0114
R5423
61
IN
CHGR_BMON
1
45.3K
1%
1/16W
MF-LF
402
From charger
2
1
1
0
2
2
DESCRIPTION
REFERENCE DES
CRITICAL
BOM OPTION
C5451,C5461
RES,MTL FILM,100K,5,1/16W,0402,SMD,LF
SENSOR_NONPROD:N
IPBR
SMC_ADC7
R5420
SMC_CHGR_BMON_INSENSE_R
QTY
SMC_CHGR_BMON_ISENSE
OUT
42
5%
1/16W
MF-LF
402
C5421
0.022UF
10%
16V
2 X5R-X7R-CERM
0402
A
GND_SMC_AVSS
41 42 45 46 99
SYNC_MASTER=D2_SEAN
61
IN
CHGR_AMON
R5441
45.3K
1
2
1%
1/16W
MF-LF
402
High Side and CPU/AXG Current Sensing
SMC Key ID0R
SMC_ADC4
PLACE_NEAR=U4900.K10:5MM
EDP Current:4.6A
SMC_DCIN_ISENSE
OUT
DRAWING NUMBER
Apple Inc.
42
NOTICE OF PROPRIETARY PROPERTY:
C5441
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
0.0022UF
10%
50V
2 CERM
402
GND_SMC_AVSS
8
7
051-9589
41 42 45 46 99
6
5
4
3
2
SIZE
D
REVISION
R
PLACE_NEAR=U4900.K10:5MM
1
SYNC_DATE=03/05/2012
PAGE TITLE
DC-IN (AMON) Current Sense Filter
4.18.0
BRANCH
PAGE
54 OF 132
SHEET
46 OF 99
1
A
8
7
6
5
4
3
2
1
GPU PROXIMITY/GPU DIE/LEFT FIN STACK/RIGHT FIN STACK
R5550
8
47
=PP3V3_S0_GPUTHMSNS
1
2
5%
1/16W
MF-LF
402
PP3V3_S0_GPUTHMSNS_R
MIN_LINE_WIDTH=0.38 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
1
96 77
D
GPU_TDIODE_P
BI
Detect GPU Die Temperature
96 77
CRITICAL
BC846BMXXH
96
SIGNAL_MODEL=EMPTY
10%
50V
CERM
402
C5552
1
2
5%
1/16W
MF-LF
402
D
1
10%
50V
CERM
402
2
THERM*/ADDR
ALERT*
8 GPUTHMSNS_ALERT_L
SMDATA
9
=SMBUS_GPUTHMSNS_SDA
BI
44
5 DN2/DP3
GND
6
0.0022uF
96
2
4 DP2/DN3
BI
GPUTHMSNS_D_P
SOT732-3
3
10K
3 DN1
BC846BMXXH
PLACE Q5501 ON TOP SIDE
CLOSE TO THE LEFT FIN STACK
R5552
2 DP1
SIGNAL_MODEL=EMPTY
Q5503
5%
1/16W
MF-LF
402
DFN
2
GPU_TDIODE_N
1
Placement note:
1
10K
EMC1414-A-AIA
0.0022uF
3
CRITICAL
R5551 1
U5550
1
2
SOT732-3
20%
10V
X7R-CERM
0402
1
VDD
C5551
Q5501
2
PLACE_NEAR=U5550.3:5mm
TG0D
C5550
0.1UF
PLACE_NEAR=U5550.2:5mm
7 GPUTHMSNS_THM_L
SMCLK
10
=SMBUS_GPUTHMSNS_SCL
BI
44
THRM_PAD
11
TG0P
GPU PROXIMITY TEMPERATURE
2
Placement note:
GPUTHMSNS_D_N
PLACE U5550 ON TOP SIDE UNDER GPU
Th2H
Th1H
LEFT FIN STACK TEMPERATURE
PLACE_NEAR=U5550.4:5mm
RIGHT FIN STACK TEMPERATURE
TBT DIE
THSP
PLACE_NEAR=U5550.5:5mm
Placement note:
35
Write Address: 0x98
Read Address: 0x99
PLACE Q5503 ON BOTTOM SIDE NEAR RIGHT FIN STACK
BI
TP_TBT_THERM_DP
97 TBT_THERMD_P
MAKE_BASE=TRUE
NOSTUFF
1
R5520
10K
PLACE_SIDE=BOTTOM
DDR3 PROXIMITY/CPU PROXIMITY/PCH PROXIMITY/AIRFLOW PROXIMITY
2
PLACE_NEAR=U3600.B1:2mm
1
8
1
PP3V3_S0_CPUTHMSNS_R
2
MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
5%
1/16W
MF-LF
402
TM0P
SOT732-3
SIGNAL_MODEL=EMPTY
2
Ta0P
R5572
10K
2
2
5%
1/16W
MF-LF
402
THERM*/ADDR
ALERT*
8 CPUTHMSNS_ALERT_L
4 DP2/DN3
SMDATA
9
=I2C_CPUTHMSNS_SDA
BI
44
5 DN2/DP3
GND
6
10%
50V
CERM
402
7 CPUTHMSNS_THM_L
SMCLK
10
=I2C_CPUTHMSNS_SCL
BI
44
2
DDR3THMSNS_D1_N
THRM_PAD
11
TC0P
CPU PROXIMITY TEMPERATURE
AIRFLOW PROXIMITY TEMPERATURE
CRITICAL
96
Placement note:
CPUTHMSNS_D2_P
PLACE U5570 ON TOP SIDE UNDER CPU
Q5502
BC846BMXXH
2
C5590
Q5504
1
SIGNAL_MODEL=EMPTY
3
CRITICAL
SOT732-3
10%
50V
CERM
402
SOT732-3
2
3
96
TP0P
1
0.0022uF
1
BC846BMXXH
2
Write Address: 0x98
Read Address: 0x99
CPUTHMSNS_D2_N
PCH PROXIMITY TEMPERATURE
PLACE_NEAR=U5570.4:5mm
PLACE_NEAR=U5570.5:5mm
Placement note:
B
5%
1/16W
MF-LF
402
3 DN1
1
0.0022uF
BC846BMXXH
1
10K
DFN
C5571
96
R5571 1
2 DP1
PLACE_NEAR=U5570.3:5mm
1
Q5506
20%
10V
X7R-CERM
0402
EMC1414-A-AIA
DDR3THMSNS_D1_P
PLACE_NEAR=U5570.2:5mm
PLACE Q5503 ON TOP SIDE NEAR DDR3
2
Use GND pin B1 on U3600 for N leg
C5570
0.1UF
1
VDD
U5570
3
CRITICAL
Placement note:
1
DDR3 PROXIMITY TEMPERATURE
96
C
SM
47
=PP3V3_S0_CPUTHMSNS
97 TBT_THERMD_N
XW5520
R5570
C
2
5%
1/16W
MF-LF
402
PLACE Q5502 ON TOP SIDE
CLOSE TO BOARD EDGE
B
Placement note:
PLACE Q5504 ON TOP SIDE UNDER PCH
TW0P
X29 PROXIMITY
8 =PP3V3_S0_X29THMSNS
1 C5523
PLACE_NEAR=J3501
PLACE_SIDE=BOTTOM
0.1uF
C1
2
V+
U5523
20%
10V
CERM
402
1
R5522
10K
5%
1/16W
MF-LF
2 402
TMP105
WCSP-6
44
44
BI
BI
=I2C_X29THMSNS_SDA
=I2C_X29THMSNS_SCL
A1
B1
A0
C2
X29THMSNS_A0
ALERT
B2
NC
SDA
CRITICAL
SCL
GNDS
A2
WRITE ADDRESS: 0X92
READ ADDRESS: 0X93
A
SYNC_MASTER=D2_SEAN
SYNC_DATE=03/05/2012
PAGE TITLE
Thermal Sensors
DRAWING NUMBER
Apple Inc.
Placement note:
PLACE U5523 ON BOTTOM NEAR X29 CONN
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
051-9589
4
3
2
SIZE
D
REVISION
4.18.0
BRANCH
PAGE
55 OF 132
SHEET
47 OF 99
1
A
8
7
6
5
4
3
2
1
D
D
C
Left Fan
8
8
C
Right Fan
=PP5V_S0_FAN_LT
=PP3V3_S0_FAN_LT
8
8
=PP5V_S0_FAN_RT
=PP3V3_S0_FAN_RT
CRITICAL
47K
41
OUT
SMC_FAN_0_TACH
1
47K
2
7
NC
R5651
SMC_FAN_0_CTL
41
OUT
2N7002DW-X-G
R5661
5
S
D
3
7
FAN_LT_PWM
2
7
2
3
4
1
NC
518S0769
41
IN
SMC_FAN_1_CTL
5
NC
5%
1/16W
MF-LF
402 2
7
F-RT-SM
6
1
FAN_RT_TACH
100K
SOT-363
4
47K
NC
5%
1/16W
MF-LF
402
4
Q5660
G
1
3
NC
5
SMC_FAN_1_TACH
FF14A-5C-R11DL-B-3H
5%
1/16W
MF-LF
402 2
R5665
1
5%
1/16W
MF-LF
402 2
IN
F-RT-SM
6
2
100K
41
47K
1
FAN_LT_TACH
5%
1/16W
MF-LF
402
J5660
R5660 1
FF14A-5C-R11DL-B-3H
5%
1/16W
MF-LF
402 2
R5655
CRITICAL
J5650
R5650 1
2
Q5660
2N7002DW-X-G
G
NC
7
SOT-363
1
S
D 6
7
FAN_RT_PWM
518S0769
B
B
A
SYNC_MASTER=D2_KEPLER
SYNC_DATE=01/13/2012
PAGE TITLE
Fan Connectors
DRAWING NUMBER
Apple Inc.
051-9589
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
4.18.0
BRANCH
PAGE
56 OF 132
SHEET
48 OF 99
1
A
8
7
6
5
IC
PSOC USB CONTROLLER
-
TMP102
PSOC
2 1.5 1
BYPASS=U5701.49:50:11 mm
BYPASS=U5701.49:50:8 mm
BYPASS=U5701.49:50:5 mm
PP3V3_S3_PSOC
D
1
220K
5%
1/20W
MF
201 2
49 7
49
49 7
49
C5705
1
0.1UF
=PP3V3_S4_TPAD
C5706
70
TPAD_VBUS_EN
IN
49 7
49 7
49 7
49 7
C
NC
49 7
49 7
49 7
49 7
NC
NC
PSOC_MISO
PSOC_F_CS_L
PSOC_MOSI
PSOC_SCLK
Z2_MISO
Z2_CS_L
Z2_MOSI
Z2_SCLK
1
Keyboard Connector
IPD Flex Connector
49 8
CRITICAL
J5700
NOSTUFF
1
C5708
0.1UF
10%
2 6.3V
X5R
201
PLACE_NEAR=J5800.18:3MM
P2_5
P2_7
P0_1
P0_3
P0_5
P0_7
VSS
VDD
P0_6
P0_4
P0_2
P0_0
P2_6
P2_4
CRITICAL
OMIT
U5701
CY8C24794
MLF
(SYM-VER2)
337S2983
2
Z2_CS_L
NC
Z2_MOSI
Z2_MISO
Z2_SCLK
49 7
7 49
8
=PP5V_S4_TPAD
1
7 49
TPAD_5V_SW_S4
7 49
1
7 49
49 7
VOLTAGE=5V
MIN_NECK_WIDTH=0.20MM
MIN_LINE_WIDTH=0.50MM
0402-LF
5
49 7
Z2_CLKIN
C5700
8
NC
PSOC_F_CS_L
PICKB_L
PSOC_MISO
PSOC_MOSI
PSOC_SCLK
=I2C_TPAD_SDA
=I2C_TPAD_SCL
13
15
17
19
21
7 49
7 49
49 7
7 49
49 7
7 49
49 7
7 49
49 7
7 49
49 7
44
49 7
CAPS:INT
49 7
R5714
49 7
44
NC
R57001
220K
10%
PLACE_NEAR=J5800.18:3MM
10V
2 X5R-CERM
0201
49 7
49 7
11
16
Z2_KEY_ACT_L
9
14
49 7
7
20
NC
Z2_HOST_INTN
0.1UF
7 49
6
12
PP5V_S4_CUMULUS
2
3
10
L5700
FERR-120-OHM-1.5A
7 49
1
4
22
TPAD_5V_SW_S4
29
49 7
18
49 7
30
516S0689
M-ST-SM
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.20MM
MIN_LINE_WIDTH=0.50MM
49 7
WS_KBD15_C
49
1
5%
1/20W
MF
201 2
TPAD_5V_LDO
56.2 2
49 7
49 7
1%
1/16W
MF-LF
402
49 7
7
PLACE_NEAR=J5800.18:3MM
R5715
42
41
40
39
38
37
36
35
34
33
32
31
30
29
WS_KBD17
WS_KBD16N
WS_KBD15_C
WS_KBD14
WS_KBD13
WS_KBD12
WS_KBD11
WS_KBD10
WS_KBD9
WS_KBD8
WS_KBD7
WS_KBD1
WS_KBD2
WS_KBD3
7 49
49
49
FERR-120-OHM-1.5A
2
PP5V_S5RS4_CUMULUS 1
TPAD_5V_LDO
7 49
1
7 49
7 49
2
49 7
1%
1/16W
MF-LF
402
C5707
Left shift, option & control keys combined with power button cause SMC RESET# assertion.
0.1UF
Keys ANDed with PSoC power to isolate when PSoC is not powered.
10%
PLACE_NEAR=J5800.18:3MM
10V
No IPD on OE input pin PP3V3_S4 (symbol error).
42 41
2 X5R-CERM
OUT
0201
49 8 =PP3V42_G3H_TPAD
7 49
49 7
1
SMC Manual Reset & Isolation
0402-LF
49
WS_KBD16N
49
49 7
10K
L5707
P2_2
P2_0
P4_6
P4_4
P4_2
P4_0
P3_6
P3_4
P3_2
P3_0
P5_6
P5_4
P5_2
P5_0
THRML
PAD
SMC_ONOFF_L
1K
1
C5710
C5750
20%
10V
CERM
402
0.1UF
7 49
7 49
VDD
7 49
2
10%
16V
X7R-CERM
0402
49 7
2
7
1
28
WS_KBD1
WS_KBD2
WS_KBD3
WS_KBD4
WS_KBD5
WS_KBD6
WS_KBD7
WS_KBD8
WS_KBD9
WS_KBD10
WS_KBD11
WS_KBD12
WS_KBD13
WS_KBD14
WS_KBD15_CAP
WS_KBD16_NUM
WS_KBD17
WS_KBD18
WS_KBD19
WS_KBD20
WS_KBD21
WS_KBD22
WS_KBD23
WS_KBD_ONOFF_L
49 7
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
49 7
2
49 7
3
WS_LEFT_SHIFT_KBD
WS_LEFT_OPTION_KBD
WS_CONTROL_KBD
2
1
PLACEMENT_NOTE=NEAR J5713
U5750
F-RT-SM
FF14A-30C-R11DL-B-3H
TQFN
49 8
J5713
4 OE
=PP3V3_S4_TPAD
CRITICAL
(IPD)
WS_KBD4
WS_KBD5
WS_KBD6
TP_ISSP_SDATA_P1_0
ISSP SCLK/I2C SCL
R5701
91 9
USB_TPAD_P
1
24
2
96
26
Z2_CLKIN
TP_P7_7
USB_TPAD_R_P
1
24
49 7
WS_LEFT_OPTION_KBD
2 IN_2
49 7
7 49
WS_CONTROL_KBD
3 IN_3
(IPD)
96
26
C5702
100PF
1
0.1UF
5%
2 25V
NP0-CERM
0201
USB_TPAD_R_N
C5703
1
OUT_ALL# 6
7 49
GND
CAPS:EXT
CAPS:EXT
49 8
R57381
CHANNEL
P-TYPE 12V
RDS(ON)
29 mOhm @4.5V
LOADING
16 mA (EDP)
1
R5730
CAPS:EXT
1
R5732
10K
20K
5%
1/20W
MF
2 201
7
R57211
3
IN
G
S
X5R
TPAD_5V_FET
1
D
CAPS:EXT
1
402
=P5VS4_TPAD_EN
3.3K 2
R5731
TPAD_5V_FET
5%
1/20W
MF
2 201
0.01UF
P5VCUMULUS_SS
5%
1/20W
MF
201
1
2
Q5701
D
6
CAP_SOURCE
6
R5733
20K
5%
1/20W
MF
2 201
CAPS:EXT
1
R5735
10K
MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM
113
LM393ADGKR
MSOP
1%
1/20W
MF
201 2
7
WS_KBD15_CAP
CAPS:EXT
1
3
CAP_COMP_H
113
1%
1/20W
MF
201 2
GND
4
5%
1/20W
MF
2 201
CAP_SINK
3
D
PLACE THESE COMPONENTS CLOSE TO J5800
THIS ASSUMES THERE’S A PP3V42_G3H PULL UP ON MLB
7 49
MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM
R57391
CAPS:EXT
CRITICAL
TPAD_5V:SW_S4
TPAD_5V:LDO_S4
TPAD_5V:LDO_S5
CAP_COMP_L_INV
1
MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM
CAPS:EXT
Q5738
G
S
DMN3730UFB4
DFN1006H4-3
Q5734
SSM3K15AMFVAPE
Original implementation off PP5V_S4
PP5V_S5 LDO power in S4 only
PP5V_S5 LDO power
D 3
2
VESM
SYNC_MASTER=D2_KEPLER
KEYBOARD/TRACKPAD (1 OF 2)
CAP_COMP_L
SOT563
1
G
S 2
DRAWING NUMBER
TABLE_BOMGROUP_HEAD
42 41
IN
SMC_LID
G
S
1
TPAD_5V:SW_S4
TPAD_5V_SW_S4
TPAD_5V:LDO_S4
Apple Inc.
BOM OPTIONS
TPAD_5V_FET,TPAD_5V_LDO
TPAD_5V:LDO_S5
2
BOM GROUP
TPAD_5V_NO_FET,TPAD_5V_LDO
TABLE_BOMGROUP_ITEM
7
NOTICE OF PROPRIETARY PROPERTY:
TABLE_BOMGROUP_ITEM
6
5
4
051-9589
REVISION
R
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
TABLE_BOMGROUP_ITEM
8
SYNC_DATE=01/13/2012
PAGE TITLE
SSM6N15FEAPE
THE TPAD BUTTONS WILL BE DISABLE
WHEN THE LID IS CLOSED
LID OPEN = & gt; SMC_LID_LC ~ 3.42V
LID CLOSE = & gt; SMC_LID_LC & lt; 0.50V
B
SOT-563-HF
CAPS:EXT
BOM Options available to CSA 5
BUTTON_DISABLE
Q5736
NTZD3152P
R57371
10%
10V
X5R
201
TPAD Buttons Disable
49
CAPS:EXT
1
10K
C5723
none
source
sink
6
2
CAP_VREF_H
2
R5722
S
8
V+
49
10%
16V
P5VCUMULUS_EN_L 1
2
PP5V_S5RS4_CUMULUS
LED Current
off
off
on
CAPS:EXT
1
5
VOLTAGE=5V
MIN_NECK_WIDTH=0.20MM
MIN_LINE_WIDTH=0.50MM
1
0.033UF
220K
5%
1/20W
MF
201 2
70
C5722
5%
1/20W
MF
201 2
U5730
WS_KBD15_C
G
D
SOD-VESM-HF
S
4
SSM3K15FV
1
TPAD_5V_FET
TPAD_5V_FET
Q5721
3
TPAD_5V_FET
CAPS:EXT
5%
1/20W
MF
2 201
CAP_VREF_L
49
Q5738
off
on
off
D
R5734
5%
1/20W
MF
2 201
SC70-6L
=PP5V_S5_TPAD
10K
5%
1/20W
MF
201 2
CAPS:EXT
10K
SIA413DJ
8
10K
5%
1/20W
MF
201 2
1
10K
CRITICAL
Q5736
1
1
0
R57361
=PP3V3_S4_TPAD
SiA413
CAP_COMP_L
1
0
1
G
CAPS:EXT
MOSFET
Q5720
CAP_COMP_H
CAPS:EXT
R57401
5V TPAD FET
2
TPAD_5V_FET
42
2
R5720
5V TRACKPAD S4 FET
WS_KBD15_C
20%
2 6.3V
X5R
402
5%
1/16W
MF-LF
402
OUT
Z
1
0
TPAD_5V_NO_FET
All RC values are TBD
THRM
PAD
C5701
Caps Lock LED Drive
0
49
Pull-up in U5010.
SMC_TPAD_RST_L
4.7UF
10%
2 6.3V
X5R
201
1
49
(IPD)
BYPASS=U5701.22:19:5 mm
BYPASS=U5701.22:19:8 mm
BYPASS=U5701.22:19:11 mm
B
WS_LEFT_OPTION_KEY
WS_CONTROL_KEY
518S0752
49
OUT_3 7
(IPD)
WS_LEFT_SHIFT_KEY
OUT_2 8
1 IN_1
WS_LEFT_SHIFT_KBD
5
2
5%
1/20W
MF
201
A
OUT_1 9
(PP3V3_S3_PSOC)
1
R5702
USB_TPAD_N
49 7
7 49
ISSP SDATA/I2C SDA
5%
1/20W
MF
201
91 9
7 49
11
7
TP_PSOC_SCL
TP_PSOC_SDA
TP_PSOC_P1_3
TP_ISSP_SCLK_P1_1
C
31
SLG4AP021
57
D
27
4
5%
1/16W
MF-LF
402
0.1UF
1
49 7
R5710
7 49
7 49
49 7
49 7
7 49
7 49
32
=PP3V3_S4_TPAD
=PP3V42_G3H_TPAD
55560-0228
10
49 7
P2_3
P2_1
P4_7
P4_5
P4_3
P4_1
P3_7
P3_5
P3_3
P3_1
P5_7
P5_5
P5_3
P5_1
W
W
W
W
W
W
W
PP3V3_TPAD_CONN
2
20%
6.3V
2 X5R
402
WS_KBD23
WS_KBD22
WS_KBD21
WS_KBD20
WS_KBD19
WS_KBD18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
0
1
4.7UF
10%
2 6.3V
X5R
201
=PSOC_WAKE_L
PICKB_L
BUTTON_DISABLE
Z2_HOST_INTN
WS_LEFT_SHIFT_KEY
WS_LEFT_OPTION_KEY
WS_CONTROL_KEY
Z2_KEY_ACT_L
4.7 OHM
0.255E-6
16.32E-6
36E-3
0.72E-3
96E-6
294E-6
75.2E-6
V
V
V
V
V
V
V
49 7
15 P1_7
16 P1_5
17 P1_3
18 P1_1
19 VSS
20 D+
21 D22 VDD
23 P7_7
24 P7_0
25 P1_0
26 P1_2
27 P1_4
28 P1_6
49
0.0255
0.204
0.6
0.012
0.012
0.021
0.0188
5%
1/20W
MF
201
56
55
54
53
52
51
50
49
48
47
46
45
44
43
49
1
5%
2 25V
NP0-CERM
0201
R5703
OUT
C5704
100PF
1
42
2.55 KOHM
10 OHM
0.2 OHM
1.5 OHM
2
POWER
R5708
49 8
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=3.3V
5%
1/16W
MF-LF
402
VIN
3
V_SNS
49 8
R5704
=PP3V3_S4_TPAD
VDD
VOUT
VDD
18V BOOSTER
USB INTERFACES TO MLB
SPI HOST TO Z2
TRACKPAD PICK BUTTONS
KEYBOARD SCANNER
10UA
80UA
60MA (MAX)
60MA (MAX)
8MA (TYP)
14MA (MAX)
4MA (MAX)
V+
3V3 LDO
PLACE_SIDE=BOTTOM
49 8
4
PIN NAME CURRENT R_SNS
3
2
4.18.0
BRANCH
PAGE
57 OF 132
SHEET
49 OF 99
1
SIZE
D
A
8
7
6
5
4
2
3
8
1
=PP3V3_S0_TPAD
1
R5853
470K
J5815 PIN 4 IS GROUNDED
ON KEYBOARD BACKLIGHT FLEX
CRITICAL
5%
1/16W
MF-LF
2 402
50 41
OUT
J5815
SMC_SYS_KBDLED
AA07A-S010-VA1
F-ST-SM
1
R5854
12
11
4.7K
5%
1/16W
MF-LF
2 402
D
2
4
6
8
SMC_KBDLED_PRESENT_L
1
3
5
7
10
7
D
9
KBDLED_ANODE2
7 50
KBDLED_ANODE1
7 50
NC
13
14
516S0899
Keyboard Backlight Connector
C
C
Keyboard Backlight Driver & Detection
B
B
To detect Keyboard backlight, SMC will
tristate and read SMC_SYS_KBDLED:
If LOW, keyboard backlight present
If HIGH, keyboard backlight not present
R5853 always stuffed, R5854 only
grounded when KB BL flex connected.
R5856
SMC_SYS_KBDLED
CRITICAL
L5850
10K
1
10UF
20%
10V
2 X5R
0603
2
1
NOSTUFF
R5858
4 SW
5%
1/16W
MF-LF
2 402
0
1
5%
1/16W
MF-LF
402
1
R5859
CAP 5
CAP 6
10
2
R5855
1%
1/16W
MF-LF
402
KBD_BL:SANDWICH
KBD_BL:SANDWICH
CRITICAL
1
KBDLED_CAP1
C5855
1.0UF
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM
10%
2 50V
X5R
0603
KBD_BL:TBONE
CRITICAL
1
KBD_BL:TBONE
CRITICAL
C5856
1
1.0UF
C5857
CRITICAL
1
1.0UF
10%
2 50V
X5R
0603
10%
2 50V
X7R
0805
C5858
1.0UF
10%
2 50V
X7R
0805
PART NUMBER
353S1612
QTY
2
DESCRIPTION
REFERENCE DES
U5850,U5860
IC,DC/DC CVTR,BOOST,WHITE LED,1MHZ,DFN8
CRITICAL
BOM OPTION
CRITICAL
2
NOSTUFF
353S3472
OMIT_TABLE
CTRL
8
100K
CRITICAL
L5860
15UH-20%-740MA-0.42OHM
1
2
VLF403212MT-SM
1
C5860
U5860
1 VIN
LED
DFN
3 SW
4 SW
1UF
7
7
LT3591
KBDLED_SW2
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.25 MM
SWITCH_NODE=TRUE
CAP 5
CAP 6
GND PAD
10%
10V
2 X5R
402-1
8
1
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=35V
R5866
NOSTUFF
5%
1/16W
MF-LF
2 402
KBDLED_ANODE1
GND PAD
10%
2 10V
X5R
402-1
120K
DFN
3 SW
1UF
1
7
LT3591
C5850
SMC_SYS_KBDLED_ANALOG
A
1 VIN
KBDLED_SW1
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.25 MM
SWITCH_NODE=TRUE
VLF403212MT-SM
SMC_SYS_KBDLED_FILTER
C5859
U5850
LED
15UH-20%-740MA-0.42OHM
5%
1/16W
MF-LF
2 402
1
353S3472
OMIT_TABLE
CTRL
8
=PP5V_S0_KBDLED
9
8
R5857
6
SYNC_MASTER=D2_KEPLER
SYNC_DATE=01/13/2012
PAGE TITLE
50 7
KBDLED_ANODE2
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=35V
1
10
2
KEYBOARD/TRACKPAD (2 OF 2)
R5865
DRAWING NUMBER
1%
1/16W
MF-LF
402
KBD_BL:SANDWICH
KBD_BL:SANDWICH
KBD_BL:TBONE
KBD_BL:TBONE
CRITICAL
1
KBDLED_CAP2
CRITICAL
CRITICAL
CRITICAL
C5865
1.0UF
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM
10%
50V
2 X5R
0603
9
NOSTUFF
SMC_SYS_KBDLED_R
2
5%
1/16W
MF-LF
402
1
NOSTUFF
0
1
2
IN
2
50 41
5
1
C5866
1
1.0UF
C5867
1.0UF
10%
50V
2 X5R
0603
10%
50V
2 X7R
0805
4
1
Apple Inc.
051-9589
R
C5868
1.0UF
NOTICE OF PROPRIETARY PROPERTY:
10%
50V
2 X7R
0805
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
3
2
SIZE
D
REVISION
4.18.0
BRANCH
PAGE
58 OF 132
SHEET
50 OF 99
1
A
8
7
6
8
5
4
3
2
1
=PP3V3_S3_SMS
BYPASS=U5920.14:13:8 mm
20%
6.3V
X5R
603
D
SMS
1
1
10UF
C5922
0.1UF
2
VDD
10%
6.3V
X5R
201
2
R5924
1
OUT
R5920
VDD_IO
R5925
10K
LIS331DLH
LGA
10
CS
SDO
SDA/SDI/SDO
SCL/SPC
11
INT1
INT2
9
10K
5%
1/20W
MF
201
7
2
0
6
4
2
=I2C_SMC_SMS_SDA
BI
=I2C_SMC_SMS_SCL
IN
44
5%
1/20W
MF
201
SMS_ADDR_SELECT
I2C_SMC_SMS_SDA_R
I2C_SMC_SMS_SCL_R
SMS
SMS
R5921
16
13
5
SMS
R5923
2
1
GND
12
1
SMS_I2C_SEL
8
RESERVED
CRITICAL
15
2
SMS_INT_L
TP_SMS_INT2
NOSTUFF
1
5%
1/20W
MF
201
U5920
NC
3
10K
5%
1/20W
MF
201
SMS
2
NC
NC
SMS
BYPASS=U5920.14:13:8 mm
42 41
SMS
1
C5926
14
D
SMS
R5922
1
0
1
2
10K
338S0687
5%
1/20W
MF
201
PLACEMENT_NOTE=See schematic for orientation.
44
5%
1/20W
MF
201
2
SMS_ADDR_SELECT=0 Addr: 0x30(Wr)/0x31(Rd)
SMS_ADDR_SELECT=1 Addr: 0x32(Wr)/0x33(Rd)
Desired orientation when
placed on board bottom-side (view thru top):
NOTE: SDA and SCL have internal pull-ups to VDD_IO.
+Y
Front of system
+X
+Z (dn)
C
C
Circle indicates pin 1 location when placed
in correct orientation
8
=PP3V3_S3_GYRO
GYRO
1
C5940
0.1UF
10%
6.3V
2 X5R
201
GYRO
GYRO
1
C5941
0.1UF
10%
6.3V
2 X5R
201
GYRO
1
C5943
10UF
20%
6.3V
2 CERM-X5R
0402-1
1
(WRITE: 0XD0
GYRO
5%
1/20W
MF
2 201
RES/VDD
GYRO
VDD_IO
R5946
U5940
CS PU = I2C
0
338S0927 = 8KHZ
AP3GDL8B
INT ARE PUSH-PULL
1
5
6
8
GYRO_CS
SCL_SPC 2
SDA_SDI_SDO 3
SDO_SA0 4
CS
DRDY/
INT2
DEN
I2C_SMC_GYRO_SCL_R
I2C_SMC_GYRO_SDA_R
7 INT1
14 PLLFILT
RES0
RES1
RES2
RES3
=I2C_SMC_GYRO_SCL
IN
44
B
GYRO
R5947
CRITICAL
TP_IRQ_GYRO_INT1_L
2
5%
1/20W
MF
201
LGA
TP_IRQ_GYRO_INT2_L
TP_GYRO_SYNC
READ: 0XD1)
1
10K
15
VDD 16
R5944
B
GYRO
1
9
10
11
12
0
2
=I2C_SMC_GYRO_SDA
BI
44
5%
1/20W
MF
201
13
GND
PLLFILT_GYRO
GYRO
1
C5942
0.47UF
10%
2 6.3V
CERM-X5R
402
PLLFILT_GYRO1
GYRO
1
R5945
10K
5%
1/20W
MF
2 201
GYRO
1
C5945
0.01UF
10%
10V
2 X5R-CERM
0201
A
SYNC_MASTER=D2_KEPLER
SYNC_DATE=01/13/2012
PAGE TITLE
DIGITAL ACCELEROMETER & GYRO
DRAWING NUMBER
Apple Inc.
051-9589
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
4.18.0
BRANCH
PAGE
59 OF 132
SHEET
51 OF 99
1
A
8
7
6
5
4
3
2
1
D
D
C
C
=PP3V3_SUS_ROM
1
R6101
3.3K
5%
1/16W
MF-LF
2 402
43 42
IN
CRITICAL
VDD
8
8
C6100 1
0.1UF
20%
10V
CERM 2
402
U6100
64MBIT
SPI_MLB_CLK
6
SCK
SOIC
SI
5
SPI_MLB_MOSI
IN
42 43
SO
2
SPI_MLB_MISO
OUT
42 43
SST25VF064C
43 20 7
IN
IN
SPI_MLB_CS_L
SPI_WP_L
SPIROM_USE_MLB
NOTE: If HOLD* is asserted
ROM will ignore SPI cycles.
1
3
7
CE*
WP*
HOLD*
OMIT
VSS
4
43 42
B
B
A
SYNC_MASTER=D2_KEPLER
SYNC_DATE=01/13/2012
PAGE TITLE
SPI ROM
DRAWING NUMBER
Apple Inc.
051-9589
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
4.18.0
BRANCH
PAGE
61 OF 132
SHEET
52 OF 99
1
A
8
7
6
5
4
3
2
1
AUDIO CODEC
APPLE P/N 353S2355
L6201
U6201 CONSUMES 40MA MAX. FROM 1.5V RAIL
FERR-22-OHM-1A-0.065-OHM
8
1
=PP1V5_S0_AUDIO
IN
PP5V_AUDIO_HPAMP
2
C6210
D
1
2
C6211
1
2
4.7UF
10%
6.3V
X5R
201
PP4V5_AUDIO_ANALOG
CRITICAL
C6219
IN
1
20%
4V
X5R 2
0402
R6210
2.67K
IN
IN
CS4206_FP
CS4206_FN
FLYP
FLYC
FLYN
29
44
41
MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM
=PP3V3_S0_AUDIO_DIG
GPIO3 = SPKR AMP SHDN CONTROL
SENSE_A
45
43
42
MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM
AUD_SENSE_A
58 53 8
VBIAS_DAC
AUD_DMIC_SDA1
AUD_DMIC_SDA2
TP_XCVR_ADC_RSTN
AUD_GPIO_3
OUT
59
20%
4V
2 X5R
0402
1%
1/20W
MF
201
2
57
MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM
15UF
VD VA_REF VA_HP VA
VBIAS_DAC
HPOUT_L
VHP_FILT+
HPOUT_R
VHP_FILTCS4206B
HPREF
QFN
GPIO0/DMIC_SDA1 LINEOUT_L1+
GPIO1/DMIC_SDA2 LINEOUT_L1/SPDIF_OUT2
GPIO2
LINEOUT_R1+
GPIO3
LINEOUT_R1-
13
1
59
IN
2
IN
12
MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM
MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM
C6222
1
1
2
C6216
2
10%
6.3V
X5R
201
C6223
15UF
20%
4V
2 X5R
0402
U6201
3
VL_HD
1
IN
IN
IN
HDA_SDIN0
IN
2
92
AUD_SDI_R
8
5
5%
1/20W
MF
201
HDA_SDOUT
HDA_RST_L
OUT
92 17
22
53 54 58 59
MIN_NECK_WIDTH=0.1MM
39
MIN_LINE_WIDTH=0.30MM
53 54 58 59
AUD_HP_PORT_L
AUD_HP_PORT_R
MIN_NECK_WIDTH=0.1MM
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.20MM
OUT
OUT
AUD_HP_PORT_REF
IN
AUD_LO1_L_P
AUD_LO1_L_N
AUD_LO1_R_P
AUD_LO1_R_N
35
34
36
37
7 54 58
7 54 58
58
OUT
57 96
OUT
57 96
OUT
57 96
OUT
57 96
OUT
AUD_LO2_L_P
AUD_LO2_L_N
AUD_LO2_R_P
AUD_LO2_R_N
16
BITCLK
10
R6211
1
GND_AUDIO_CODEC
MIN_LINE_WIDTH=0.3MM
57 96
OUT
LFT. SPKR AMP. SIG. SOURCE
57 96
OUT
RT. SUBWOOFER AMP. SIG. SOURCE
57 96
OUT
LFT SUBWOOFER AMP. SIG. SOURCE
57 96
RT. SPKR AMP. SIG. SOURCE
TP_AUD_CODEC_MICBIAS
MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM
CRITICAL
28 CS4206_VCOM
MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM
C
LINEIN_L+
LINEIN_CLINEIN_R+
21
NO_TEST=TRUE
22
NO_TEST=TRUE
23
NO_TEST=TRUE
MICIN_L+
MICIN_LMICIN_R+
MICIN_R-
18
17
19
20
VREF+_ADC
HDA_SYNC
92 17
2
20%
10V
2 X5R-CERM
0402-1
31
30
32
33
VCOM
HDA_BIT_CLK
92 17
2
20%
16V
TANT-POLY
2012-LLP
38
40
LINEOUT_L2+
LINEOUT_L2LINEOUT_R2+
LINEOUT_R2-
MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM
92 17
10UF
C6213
10UF
10%
16V
X5R-CERM 2
0201
C6217
53 58 59
VL_IF
6
CS4206_FLYN
C
1
GND_AUDIO_CODEC
MICBIAS
CS4206_FLYP
CS4206_FLYC
1
20%
4V
X5R 2
0402
0.1UF
10%
10V
X5R
402-1
1
15UF
C6226
1UF
92 17
10%
16V
X7R-CERM
0402
14
15
15UF
59
25
C6220
46
CRITICAL
C6221 1
24
CRITICAL
PP4V5_AUDIO_ANALOG
1
0.1UF
2
9
20%
16V
TANT-POLY
2012-LLP
GND_AUDIO_CODEC
1
0.1UF
C6218
IN
CRITICAL
C6214 1
1
10UF
59 58 53
D
0.1UF
20%
4V
X5R-1
402
59 58 54 53
53
PP1V5_S0_AUDIO_DIG
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.5V
0201
27
NC_AUD_LI_P_L
NC_AUD_LI_REF
NC_AUD_LI_P_R
NC
NC
NC
SYNC
SDI
SDO
11
RESET*
47
48
SPDIF_IN
SPDIF_OUT
AUD_MIC_INL_P
AUD_MIC_INL_N
IN
58 96
IN
58 96
EXT MIC CODEC INPUT
TP_AUD_MIC_INP_R
TP_AUD_SPDIF_IN
AUD_SPDIF_OUT
CS4206_VREF_ADC
TP_AUD_MIC_INN_R
MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM
DMIC_SCL
4
R6241
AUD_DMIC_CLK_R
1
26
49
0
AUD_DMIC_CLK
2
OUT
59
5%
1/16W
MF-LF
402
DGND THRM_PAD AGND
7
NC
C6224
1
1
2
2
1UF
20%
16V
TANT
0603-SM
C6225
10UF
20%
16V
TANT-POLY
2012-LLP
R6220
B
58 7
OUT
33
1
AUD_SPDIF_OUT_JACK
B
2
5%
1/16W
MF-LF
402
59 58 54 53
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.15MM
VOLTAGE=0V
GND_AUDIO_CODEC
4.5V POWER SUPPLY FOR CODEC
NOTES ON CODEC I/O
DIFF FSINPUT= 2.45VRMS
SE FSINPUT= 1.22VRMS
DAC1 FSOUTPUT= 1.34VRMS
DAC2/3 FSOUTPUTDIFF= 2.67VRMS
DAC2/3 FSOUTPUTSE= 1.34VRMS
APPLE P/N 353S2456
L6202
FERR-22-OHM-1A-0.065-OHM
15 " MBP: PLACE XW6201 NEAR 5V SOURCE
1
2
MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM
VOLTAGE=5V
PP5V_AUDIO_HPAMP
53
0201
L6200
XW6201
FERR-22-OHM-1A-0.065-OHM
SM
59 8
IN
=PP5V_S4_AUDIO 1
2 PP5V_S4_AUDIO_XW
1
MIN_LINE_WIDTH=0.60MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=5V
58 53 8
A
IN
=PP3V3_S0_AUDIO_DIG
2
MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM
VOLTAGE=5V
TPS71745
6
IN
4V5_REG_EN
4
EN
0201
SON
OUT
1
PP4V5_AUDIO_ANALOG
OUT
53 58 59
CRITICAL
R6200
2.2K
1
MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM
VOLTAGE=4.5V
U6200
4V5_REG_IN
NR/FB
3
NC
4V5_NR
5
2
5%
1/20W
MF
201
GND
1
1UF
2
10%
10V
X5R
402
CRITICAL
C6202
2
C6200
1
C6201
XW6200
SM
1UF
2
10%
10V
X5R
402
1
2
0.1UF
CRITICAL
1
10%
16V
X5R-CERM 2
0201
1
SYNC_MASTER=D2_CARA
C6203
SYNC_DATE=03/16/2012
PAGE TITLE
1.0UF
AUDIO: CODEC/REGULATOR
20%
10V
2 X5R-CERM
0201-1
DRAWING NUMBER
GND_AUDIO_CODEC
Apple Inc.
53 54 58 59
051-9589
R
PLACE XW6200 BENEATH U6200, BETWEEN PINS 2 & 5
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
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REVISION
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62 OF 132
SHEET
53 OF 99
1
A
8
7
6
5
4
3
2
1
D
D
C
C
ZOBEL NETWORK & 1ST ORDER DAC FILTER PLACEHOLDER
58 53 7
IN
AUD_HP_PORT_L
OUT
CRITICAL
C6300 1
B
B
0.1UF
10%
6.3V
X5R 2
201
NC
1
R6302
10K
AUD_HP_ZOBEL_L
1%
1/20W
MF
2 201
MIN_LINE_WIDTH=0.30MM
MIN_NECK_WIDTH=0.20MM
R63001
39
5%
1/20W
MF
201 2
59 58 53
IN
GND_AUDIO_CODEC
R63101
39
5%
1/20W
MF
201 2
NC
1
R6312
10K
1%
1/20W
MF
2 201
AUD_HP_ZOBEL_R
MIN_LINE_WIDTH=0.30MM
MIN_NECK_WIDTH=0.20MM
CRITICAL
C6310
1
0.1UF
10%
6.3V 2
X5R
201
58 53 7
IN
AUD_HP_PORT_R
OUT
A
SYNC_MASTER=D2_CARA
SYNC_DATE=03/16/2012
PAGE TITLE
AUDIO: HEADPHONE FILTER
DRAWING NUMBER
Apple Inc.
051-9589
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
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REVISION
4.18.0
BRANCH
PAGE
63 OF 132
SHEET
54 OF 99
1
A
8
7
6
5
4
3
2
1
D
D
C
C
B
B
A
SYNC_MASTER=D2_CARA
SYNC_DATE=03/16/2012
PAGE TITLE
AUDIO: IV SENSE
DRAWING NUMBER
Apple Inc.
051-9589
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
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REVISION
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55 OF 99
1
A
8
7
6
5
4
3
2
1
D
D
C
C
B
B
A
SYNC_MASTER=D2_CARA
SYNC_DATE=03/16/2012
PAGE TITLE
AUDIO: IV SENSE FILTER
DRAWING NUMBER
Apple Inc.
051-9589
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
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REVISION
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PAGE
65 OF 132
SHEET
56 OF 99
1
A
8
7
6
5
4
3
57 9
2
1
PP5V_S0_AUDIO_AMP_L
CRITICAL
CRITICAL
L6610
AUD_SPKRAMP_LIN_P
NO_TEST=TRUE
0402
CRITICAL
L6611
4X MONO SPEAKER AMPLIFIERS (MAX98300 & SSM2375)
APN: 353S2888 & 353S2958
GAIN = +3 DB
1ST ORDER FC (L & R) = NOM 569 HZ
1ST ORDER FC (SUB) = NOM 9 HZ
D
1
1
AUD_LO2_L_N
IN
0.01UF
2
96
AUD_SPKRAMP_LIN_N
NO_TEST=TRUE
0402
1
PVDD
96
96
MAX98300
NO_TEST=TRUE
SPKRAMP_LIN_P
SPKRAMP_LIN_N
NO_TEST=TRUE
1
AUD_GPIO_3
R6600
2
5%
1/16W
MF-LF
402
CRITICAL
57 9
L6620
1
IN
96
0402
AUD_LO2_R_N
IN
1
96
2
0402
5%
1/16W
MF-LF
402
2
PLACE_NEAR=U6620.A1
1
0.01UF
AUD_SPKRAMP_RIN_N
NO_TEST=TRUE
1
2
10%
50V
X7R-CERM
0402
CRITICAL
57
C6621
0.1UF
20%
6.3V 2
POLY-TANT
2012-LLP
2
10%
50V
X7R-CERM
0402
C6624
1
47UF
0.01UF
AUD_SPKRAMP_RIN_P
NO_TEST=TRUE
CRITICAL
FERR-1000-OHM
96 53
100K
2
C6622
C6623
2
L6621
C
R6610
PGND
1
CRITICAL
FERR-1000-OHM
AUD_LO2_R_P
MIN_LINE_WIDTH=0.40 MM
MIN_NECK_WIDTH=0.10 MM
PP5V_S0_AUDIO_AMP_R
CRITICAL
7 59 96
D
1
1
100K
0402
7 59 96
SPKRCONN_L_OUT_N OUT
GAIN C3 SPKR_L_GAIN
A2
IN
OUT
MIN_LINE_WIDTH=0.40 MM
MIN_NECK_WIDTH=0.10 MM
B2 NC
FERR-1000-OHM
53
SPKRCONN_L_OUT_P
OUT+ B1
OUT- C1
C2 SHDN*
L6601
96 53
WLP
A3 IN+
B3 IN-
AUD_SPKRAMP_SHUTDOWN_L
57
10%
16V
X7R-CERM
0402
U6610
2
10%
50V
X7R-CERM
0402
CRITICAL
C6611
0.1UF
CRITICAL
2
10%
50V
X7R-CERM
0402
C6614
FERR-1000-OHM
96 53
PLACE_NEAR=U6610.A1
1
2
A1
IN
0.01UF
2
96
20%
6.3V 2
TANT-POLY
CASE-A4
A1
1
AUD_LO2_L_P
1
47UF
C6613
FERR-1000-OHM
96 53
C6612
CRITICAL
CRITICAL
2
PVDD
CRITICAL
10%
16V
X5R-CERM
0201
SPKRCONN_R_OUT_P
U6620
WLP
A3 IN+
B3 IN-
OUT+ B1
7 59 96
7 59 96
C
MIN_LINE_WIDTH=0.40 MM
MIN_NECK_WIDTH=0.10 MM
OUT- C1
C2 SHDN*
AUD_SPKRAMP_SHUTDOWN_L
OUT
SPKRCONN_R_OUT_N OUT
MIN_LINE_WIDTH=0.40 MM
MIN_NECK_WIDTH=0.10 MM
MAX98300
NO_TEST=TRUE
SPKRAMP_RIN_P
96
SPKRAMP_RIN_N
96
NO_TEST=TRUE
GAIN C3 SPKR_R_GAIN
B2 NC
R66201
NOSTUFF
R6601 1
PP5V_S0_AUDIO_AMP_R
5%
1/20W
MF
201 2
IN
1
AUD_LO1_R_P
2
96
0402
20%
C6633
POLY-TANT
2012-LLP
AUD_SPKRAMP_RSUBIN_P
NO_TEST=TRUE
1
2
47UF
2 6.3V
POLY-TANT
2012-LLP
96 53
AUD_LO1_R_N
IN
1
2
96
0402
2
A2
IN+
IN-
OUT+
OUT-
OUT
7 59 96
OUT
7 59 96
C3
SD*
GAIN
A3
EDGE
NO_TEST=TRUE
57 AUD_SPKRAMP_SHUTDOWN_L
0.22UF
1
SPKRCONN_SR_OUT_P
MIN_LINE_WIDTH=0.40 MM
MIN_NECK_WIDTH=0.10 MM
WLCSP
B1
C6634
AUD_SPKRAMP_RSUBIN_N
NO_TEST=TRUE
10%
16V
X5R-CERM
0201
U6630
CRITICAL
L6631
C6631
SSM2375
A1
FERR-1000-OHM
2
CRITICAL
VDD
RSUBIN_P
NO_TEST=TRUE
10%
16V
CERM
402
CRITICAL
5%
1/16W
MF-LF
402 2
0.1UF
20%
2 6.3V
0.22UF
1
C6632
C2
CRITICAL
L6630
FERR-1000-OHM
96 53
C6635
47UF
100K
PLACE_NEAR=U6630.C2
1 CRITICAL 1 CRITICAL
CRITICAL
A2
57 9
PGND
100K
B2
RSUBIN_N
B3
TP_SWR_GAIN
SPKRCONN_SR_OUT_N
MIN_LINE_WIDTH=0.40 MM
MIN_NECK_WIDTH=0.10 MM
GND
C1
10%
16V
CERM
402
B
B
PP5V_S0_AUDIO_AMP_L
CRITICAL
96 53
IN
1
AUD_LO1_L_P
1 CRITICAL
CRITICAL
L6640
2
96
0402
C6645
47UF
C6643
FERR-1000-OHM
0.22UF
1
AUD_SPKRAMP_LSUBIN_P
NO_TEST=TRUE
2
20%
LSUBIN_P
NO_TEST=TRUE
2 6.3V
POLY-TANT
2012-LLP
L6641
96 53
IN
AUD_LO1_L_N
1
96
0402
2
POLY-TANT
2012-LLP
CRITICAL
VDD
10%
16V
X7R-CERM
0402
U6640
SPKRCONN_SL_OUT_P
OUT
7 59 96
MIN_LINE_WIDTH=0.40 MM
MIN_NECK_WIDTH=0.10 MM
WLCSP
2
LSUBIN_N
NO_TEST=TRUE
57 AUD_SPKRAMP_SHUTDOWN_L
10%
16V
CERM
402
A2
IN+
INSD*
OUT+
OUT-
C3
GAIN
A3
EDGE
A1
0.22UF
AUD_SPKRAMP_LSUBIN_N
NO_TEST=TRUE
2
SSM2375
B1
C6644
1
C6641
0.1UF
20%
2 6.3V
CRITICAL
FERR-1000-OHM
1
C6642
47UF
10%
16V
CERM
402
CRITICAL
PLACE_NEAR=U6640.C2
1 CRITICAL
C2
57 9
B2
B3
TP_SWL_GAIN
SPKRCONN_SL_OUT_N
OUT
MIN_LINE_WIDTH=0.40 MM
MIN_NECK_WIDTH=0.10 MM
7 59 96
C1
GND
A
SYNC_MASTER=D2_CARA
SYNC_DATE=03/16/2012
PAGE TITLE
AUDIO: SPEAKER AMP
DRAWING NUMBER
Apple Inc.
051-9589
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
4.18.0
BRANCH
PAGE
66 OF 132
SHEET
57 OF 99
1
A
8
7
=PP3V3_S0_AUDIO_DIG
C6795 1 C6794
1
R6762
10K
I2C PULLUPS ON SOUTHBRIDGE PAGE
R6757
R6758
=I2C_MIKEY_SDA 1
2
2
AUDIO_SCL
C3
AUDIO_SDA
B3
D3
AUD_IPHS_SWITCH_EN
SCL
SDA
1
C1 HS_MIC_BIAS
C6793
NO_TEST=TRUE
1
C6792
1.0UF
2
20%
10V
X5R-CERM
0201-1
1
C6790
1.0UF
20%
10V
X5R-CERM
0201-1
2
CRITICAL
L6701
1.0UF
1
C6754
B2
AUD_PORTA_DET_L
1
47K
1
R6755
2
100K
5%
1/20W
MF
201
59 58 54 53
CS
NO_TEST=TRUE
0.1UF
1
59 58 54 53
58 7
0.01UF
MIKEY
1
2
10%
6.3V
X5R
201
C
MIKEY
CRITICAL
C6753
0.1UF
96 53
OUT AUD_MIC_INL_N
1
CRITICAL
D4
2.2K 2
1
HS_MIC_HI_RC
NO_TEST=TRUE
MIKEY
R67561
CRITICAL
1
100K
5%
1/20W
MF
201 2
C6750
10%
6.3V
X5R
201
5%
25V
2 NP0-C0G
0201 58 54
MIKEY
0
B4
1%
1/20W
MF
201
C6751
10UF
20%
10V
2 X5R-CERM
0402-1
53
59
1
C6791
10UF
20%
2 10V
X5R-CERM
0402-1
D2
D1
MIC
REF
A3
A4
A2
58
BI
AUDIO_SDA
GND_AUDIO_CODEC
XW6751
SM
MIC1 B1
MIC2 C1
J6701
FERR-33-OHM-0.8A-0.09-OHM
1
CH_HS_MIC
51138-0274
F-ST-SM
AUD_CONN_SLEEVE
2
0201
C
22
21
CRITICAL
L6704
120-OHM-25%-1.3A
54 53 7
AUD_HP_PORT_L
IN
MIN_NECK_WIDTH=0.1MM
AUD_CONN_HP_LEFT
2
0402
2
3
4
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.1MM
1
MIN_LINE_WIDTH=0.3MM
GND
1
5
6
1
2
7
PLACE_NEAR=U6750.D1
IN
47K
5%
1/20W
MF
201 2
59 58 54 53
US_HS_GND
IN
R67601
CH_HS_GND
GND_AUDIO_CODEC
58 53 8
12
14
16
18
19
AUD_CONN_TIPDET_INV
8
11
17
OUT
10
15
59
9
13
53 AUD_HP_PORT_REF
R/C6750 FILTER TO ADDRESS OUT-OF-BAND
NOISE ISSUE SEEN ON EARLY HEADSETS
(SEE RADAR # 6210118)
20
=PP3V3_S0_AUDIO_DIG
23
NOSTUFF
53 7
59 58 54 53
CRITICAL
L6703
SCL
SDA
ADDR
2
5%
1/20W
MF
201
APN:510S0009
CRITICAL
7
AUDIO_SCL
AUD_CONN_MIC_XW
MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM
0402
CLAMPO
NO_TEST=TRUE
IN
2
MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.06MM
NO_TEST=TRUE
58
1
CH_HS_GND
OUT
RAMPO
CLAMPI
CHS_CLAMPO
HS_MIC_HI
1
C6758
27PF
1
HS_MIC_LO_RC
2.2K 2
HS_MIC_LO
CRITICAL
1
R6759
2
1%
1/20W
MF
201
MIKEY
6800PF
10%
10V
2 X5R-X7R-CERM
0201
1
2.2K 2
NO_TEST=TRUE
5%
1/20W
MF
201
MIKEY
D3
C4
R6753
1
58 7
CRITICAL
RAMPI
CHS_CLAMPI
R6752
1
5%
1/20W
MF
201
MIKEY
R6750
0.1UF
1K
MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM
120-OHM-25%-1.3A
WCSP
2
AUD_CONN_SLEEVE_XW
0402
L6702
U6750
NO_TEST=TRUE
2
MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.06MM
TS3A8235YFP
CRITICAL
1
US_HS_GND
OUT
VDD
10%
2 10V
X5R-CERM
0201
5%
1/20W
MF
201 2
GND_AUDIO_CODEC
OUT AUD_MIC_INL_P
CRITICAL
L6700
120-OHM-25%-1.3A
GND_AUDIO_CODEC
5%
1/20W
MF
201 2
C6756
AUD_CONN_MIC
2
0201
10%
16V
X5R-CERM
0201
MIKEY
1K
C6752
1
US_HS_MIC
R67541
R6751
96 53
7
A1
NOSTUFF
ENABLE
HDET
FERR-33-OHM-0.8A-0.09-OHM
PLACE_NEAR=U6750.A1
20%
10V
X5R-CERM
0201-1
2
D1 HS_RX_BP
BYPASS
A1
D
PP3V42_GH3_AUDIO_LC
B1 HS_SW_DET
DETECT
INT*
MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM
VOLTAGE=3.42V
2
0201
MICBIAS
A3
R6761
IN
1
2
HS_HDET
59
=PP3V42_G3H_AUDIO
WCSP
AUD_I2C_INT_L
IN
8
U6751
CD3282A1
58
25
L6754
FERR-22-OHM-1A-0.065-OHM
AVDD
58
OUT
1
MIKEY 1A
APN:353S2640
MIKEY ADDRESS: WRITE=72H, READ=73H
5%
1/20W
MF
201
5%
1/20W
MF
201
19
2
1.0UF
20%
10V
2 X5R-CERM
0201-1
GND1
GND2
BI
1.0UF
C2
B2
44
1.0UF
20%
20%
10V
10V
2 X5R-CERM 2 X5R-CERM
0201-1
0201-1
D2 AGND
D
33
3
AUDIO JACK: HP CONNECTOR WITH MIKEY & CHS
PORT B LEFT(HEADSET MIC)
HP=80HZ, LP=10.63KHZ
C6755
A2
1
=I2C_MIKEY_SCL
33
5%
1/20W
MF
201 2
1
C2 DGND
IN
4
B3
C3
1
44
5
PP4V5_AUDIO_ANALOG
59 53
58 53 8
6
OUT
AUD_SPDIF_OUT_JACK
24
GND_AUDIO_CODEC
CRITICAL
L6705
120-OHM-25%-1.3A
B
54 53 7
IN
1
AUD_HP_PORT_R
MIN_LINE_WIDTH=0.3MM
B
2
0402
MIN_NECK_WIDTH=0.1MM
AUD_CONN_HP_RIGHT
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.1MM
CRITICAL
I2C ADDRESSES
MIKEY
MIKEY
CHS
CHS
U6751
U6751
U6750
U6750
L6706
READ
WRITE
READ
WRITE
0111
0111
0111
0111
0011
0010
0111
0110
FERR-470-OHM
0X73
0X72
0X77
0X76
59 7
OUT
AUD_TYPEDET
1
2
AUD_CONN_TYPEDET
0201
A
SYNC_MASTER=D2_CARA
SYNC_DATE=03/16/2012
PAGE TITLE
AUDIO: JACK
DRAWING NUMBER
Apple Inc.
051-9589
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
4.18.0
BRANCH
PAGE
67 OF 132
SHEET
58 OF 99
1
A
8
7
6
5
4
3
CODEC OUTPUT SIGNAL PATHS
3-MIC CONNECTOR
FUNCTION
VOLUME
CONVERTER
PIN COMPLEX
HP/LINE OUT
MUTE CONTROL
DET ASSIGNMENT
0X02 (2)
0X02 (2)
0X09 (9,A)
N/A
0X09 (B)
R6885
0
1
TWEETERS
0X04 (4)
0X04 (4)
0X0B (11)
GPIO_3
N/A
SUB
0X03 (3)
0X03 (03)
0X0A (10)
GPIO_3
N/A
SPDIF OUT
N/A
0X08 (8)
0X10 (16)
N/A
0X0C (A)
59 8
=PP3V3_S0_AUDIO
7
2
CODEC INPUT SIGNAL PATHS
53
FUNCTION
CONVERTER
PIN COMPLEX
VREF
DMIC 1
0X06 (6)
0X0E (D,E)
3V3
0X05 (5)
0X12 (12,C)
3V3
0
0X0C (12,C)
SPDIF IN
0X07 (7)
0X0F (15)
N/A
CRITICAL
0X06 (6)
0X0D (13,V22,B,LEFT)
MIKEY
7
MIKEY
53
OUT
2
7
INT
GPIO
MIKEY INTERRUPT
PIRQ H
GPIO 5
PERIPHERAL DETECT
PIRQ F
GPIO 3
53
MIKEY ENABLE
SATA4GP/GPIO 16
OUT
0
1
AUD_DMIC_CLK
96 57 7
IN
96 57 7
IN
59 7
IN
3
CON_DMIC_SDA2
SPKRCONN_L_OUT_P
SPKRCONN_L_OUT_N
SPKRCONN_L_ID
2
3
4
5
2
96 57 7
IN
96 57 7
IN
SPKRCONN_SL_OUT_P
SPKRCONN_SL_OUT_N
5
6
7
NC
7
D
1
4
R6883
FUNCTION
7
2
5%
1/16W
MF-LF
402
SYSTEM INT AND GPIO LINES
M-RT-SM
1
0
78171-6006
F-RT-SM
6
NC
1
AUD_DMIC_SDA2
CRITICAL
J6802
FF14A-5C-R11DL-B-3H
CON_DMIC_SDA1
R6886
N/A
HEADSET MIC
2
HP=80HZ
J6801
5%
1/16W
MF-LF
402
N/A
DMIC2
1
OUT AUD_DMIC_SDA1
SPEAKER CONNECTOR
CON_DMIC_PWR
5%
1/16W
MF-LF
402
DET ASSIGNMENT
1
APN: 518S0627
R6884
D
2
8
CON_DMIC_CLK
5%
1/16W
MF-LF
402
CRITICAL
J6803
78171-6006
M-RT-SM
PORT B DETECT(SPDIF DELEGATE)
59 53
7
PORT A DETECT (HEADPHONES)
OUT AUD_SENSE_A
96 57 7
1
R6896
D
1%
1/16W
MF-LF
402
2
6
D
Q6896
NC
SPEAKERID
S
G
5
1
S
59 7
4
IN
IN
7 59
R6813
100K
1%
1/16W
MF-LF
402 2
PP4V5_AUDIO_ANALOG
C
SPKRCONN_R_ID
100K
100K 1
2
8
1
R6812
R6802
1%
1/16W
MF-LF
2 402
SPEAKERID
PORT C DETECT(SPEAKER MISMATCH)
SPEAKERID
1
R6801
5%
1/20W
MF
201
P-CHN
R6816
G
1
5
AUD_TYPEDET
IN
R6803
PP4V5_AUDIO_ANALOG
2
4
100K 1
PP4V5_AUDIO_ANALOG
AUD_TYPEDET_OD_INV
SPEAKERID
100K 2
R68941
10K
1%
1/16W
MF-LF
402
7 58
S
SOT563
59 53 8
1%
1/16W
MF-LF
402 2
=PP5V_S4_AUDIO
53 58 59
SPEAKERID
1
5%
1/20W
MF
201
6
C6800 1
B
G
2
AUD_TYPEDET_OD
IN
SPEAKERID
Q6896
MCP6514_POS
1
GND_AUDIO_CODEC
SPEAKERID
1
0
2
AUD_IP_PERIPHERAL_DET
5%
1/16W
MF-LF
402
1
R6865
47K
MCP6514_NEG
OUT
59 53 8
EXTRACTION NOTIFICATION
OUT
2 G
A
7
59 58 54 53
1%
1/16W
MF-LF
402 2
59
Q6897
D 3
R68151
SSM6N15FEAPE
S 1
90.9K
5 G
CRITICAL
1%
1/16W
MF-LF
402 2
1%
1/16W
MF-LF
402
CRITICAL
SPEAKERID
1
C6811
GND_AUDIO_CODEC
AUDIO CONNECTOR DETECT STATES
4.7UF
20%
10V
2 X5R-CERM
0402
AUD_J1_TYPEDET_R
AUD_J1_TIPDET_R
AUD_OUTJACK_INSERT_L
AUD_SENSE_A
S 4
FERR-33-OHM-0.8A-0.09-OHM
1
C6860
NOTHING
1
0
1
1
SPDIF
1
1
0
20K/2.67K RDIV
HEADPHONE
0
1
0
39.2K/2.67K RDIV
2 AUD_TIPDET_FET2
0201
SYNC_MASTER=D2_CARA
1
1UF
Alternate Parts
1UF
2 10%
X5R
25V
402
AUDIO: JACK TRANSLATORS
DRAWING NUMBER
TABLE_ALT_HEAD
PART NUMBER
ALTERNATE FOR
PART NUMBER
BOM OPTION
REF DES
COMMENTS:
Apple Inc.
TABLE_ALT_ITEM
NOM R6892-C6860 FC = 106Hz
SSM6N15FE Vth = 0.8V to 1.5V
SSM6N15FE IGSS = +/-1uA
FLEX-SIDE RPULLDOWN = 100k (TB 49.9k in REV 3)
7
59 58 54 53
353S3452
GND_AUDIO_CODEC
353S1286
U6800
NOTICE OF PROPRIETARY PROPERTY:
5
4
3
051-9589
2
SIZE
D
REVISION
R
MAXIM ALT TO MICROCHIP
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
6
SYNC_DATE=03/16/2012
PAGE TITLE
C6891
10%
2 X5R 25V
402
8
S 1
R6817
L6801
AUD_TIPDET_INV
1
G
SPEAKERID
SPEAKERID
D 6
SOT563
2
2
SPKR_MATCH_DRV
45.3K2
SOT563
1%
1/16W
MF-LF
402
2
1
Q6803
1.5K
33
5%
1/16W
MF-LF
402
274K
AUD_OUTJACK_INSERT_L
AUD_TIPDET_FET1
R6892
1
SPEAKERID
APN:376S0613
SSM6N15FEAPE
1
SPKR_MATCH_DRV_R
R68141
475K
AUD_CONN_TIPDET_INV
2
=PP5V_S4_AUDIO
R6866
IN
1
2
1
58
R6820
FERR-1000-OHM
MCP6514_OUT
0402
4
19
5%
1/20W
MF
2 201
1%
1/20W
MF
2 201
SPEAKERID
L6802
MCP6541T
SC70-5
53 54 58 59
R6867
1
5
3
B
SOT563
SPEAKERID
CRITICAL
U6800
=PP3V3_S0_AUDIO
D 6
SSM6N15FEAPE
59
S
59 8
AUD_PORTC_DET_L
10%
6.3V
2 X5R
201
10%
6.3V
X5R 2
201
N-CHN
SOT563
NC
C6810
0.1UF
PLACE_NEAR=Q6800.4
0.1UF
D
Q6800
DMC2400UV
OUT AUD_SENSE_A
SPEAKERID
1%
1/20W
MF
2 201
D
Q6800
59 53
150K
3
DMC2400UV
59 58 53
6
1%
1/16W
MF-LF
2 402
SPKRCONN_L_ID
59
OUT
5
100K
1
AUD_TYPEDET_OD
SPKRCONN_SR_OUT_P
SPKRCONN_SR_OUT_N
R6811
1%
1/16W
MF-LF
402 2
IN
GND_AUDIO_CODEC
3
1
100K
AUD_OUTJACK_INSERT_L
59 58 54 53
IN
2
SPEAKERID
R68101
3
SOT563
G
IN
96 57 7
SSM6N15FEAPE
2
96 57 7
=PP5V_S4_AUDIO
59 53 8
AUD_PORTB_DET_L
58
SOT563
59
IN
4
1%
1/16W
MF-LF
402
SSM6N15FEAPE
C
59 7
1
39.2K
AUD_PORTA_DET_L
Q6897
IN
R6895
20.0K
2
IN
96 57 7
1
SPKRCONN_R_OUT_P
SPKRCONN_R_OUT_N
SPKRCONN_R_ID
4.18.0
BRANCH
PAGE
68 OF 132
SHEET
59 OF 99
1
A
8
7
6
5
4
2
3
1
CRITICAL
MagSafe DC Power Jack
F6905
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6AMP-32V-0.0095OHM
1
2
=PP18V5_DCIN_CONN
8
TDM LEVEL SHIFT
0603
7
WTB-PWR-M82
0.01UF
1
20%
50V
CERM
0603
2
2
1
TDM_ONEWIRE_MPM
8
C6908
8
5
CRITICAL
6
U6901
2
SMC_BC_ACOK_VCC
TC7SZ08FEAPE
20%
10V
CERM
402
DDZ9694T
PLACEMENT_NOTE=PLACE NEAR U6900 and U6901
SOD523
A
2
SMC_BC_ACOK
IN
TDM:MPM
R69291
VCC
2
B
2.0K
1
20%
10V
CERM
402
MAX9940
R69751
22
7
ADAPTER_SENSE
EXT
INT
SYS_ONEWIRE
4
BI
41
41
TDM:MLB
SYS_TDM_ONEWIRE
BI
22
1
2
7 IN_B2
1
R6974
OUT_D2 8
SOT723
R6972
1%
1/20W
MF
2 201
2
54.9
TDM_PD_DS
1%
1/20W
MF
2 201
TDM:MLB
GND
1
R6971
THRM
PAD
12.1
1%
1/8W
MF-LF
2 805
Q6910
SI5419DU
1-Wire OverVoltage Protection
C
1
MMBT2222AM3T5G
TDM:MLB
1
6.34K
CRITICAL
5
NC
Q6971
TDM:MLB
OUT_D1 3
Input impedance of 22.1K meets
sparkitecture requirements
for 15 " MBP design only
TDM:MLB
CRITICAL 3
TDM_RX
OUT_C 6
4 IN_B1
R6912
1%
1/20W
MF
2 201
1%
1/20W
MF
2 201
TDFN
2 IN_A
TDM_ONEWIRE_MLB
DFN
3
24.9K
U6970
1
22.1K
R6973
SLG4AP030
2
ZXTN619MA
1
VDD
5%
1/20W
MF
201
GND
3
CRITICAL
NC
1%
1/20W
MF
201 2
R6976
SC70-5
5
CRITICAL
Q6970
1
TDM_PD_BASE
TDM:MLB
TDM:MLB
2.21K
5%
1/20W
MF
201 2
3
5%
1/16W
MF-LF
402 2
U6900
1
TDM:MLB
R69771
Y
1
0.1UF
2 TDM:MLB
TDM_RX_D
41 42
4
C6900
D6970
5
SOT665
518S0508
LAYOUT NOTE:
Q0220 NEEDS 10 SQ CM
OF 1 OZ CU FOR THERMAL
TDM:MLB
CRITICAL
=PP3V42_G3H_TDM
0.1UF
1
7
=PP3V42_G3H_ONEWIREPROT
9
3
4
D
C6905
1
M-RT-SM
A
D
MIN_LINE_WIDTH=1MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=18.5V
K
CRITICAL
J6900
PP18V5_DCIN_FUSE
TDM:MLB
1
R6970
12.1
1%
1/8W
MF-LF
2 805
C
POWERPAK
TDM_PD_BASE_R
The chassis ground will otherwise float and can
5A
send transients onto ADAPTER_SENSE when AC is
S
5%
1/20W
MF
2 201
5
G
1
R6910
100K
D
connected.
1
1
C6912
0.047UF
4
10%
25V
2 X5R
0402
1
10K
2
5%
1/20W
MF
201
DCIN_ISOL_GATE_R
8
When input voltage is 2V the FET will be off
blocking the leakage path and 22.1K can be
properly detected.
R6911
When input voltage is at 16V+, FET will
conduct and power charger and 3.42V reg
DCIN_ISOL_GATE
=PP18V5_DCIN_ISOL
K
D6910
GDZT2R6.8
6.8V Zener
GDZ-0201
A
CRITICAL
R6920
10
=PPBUS_G3H
1
2
518-0376
5%
1/8W
MF-LF
805
CRITICAL
3
PPBUS_G3H_R
3.425V " G3Hot " Supply
PPVIN_G3H_P3V42G3H
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=18.5V
2
C6990 1
P3V42G3H_BOOST
DIDT=TRUE
4.7UF
10%
35V
X5R-CERM 2
0603
61 7
10%
35V
X5R-CERM 2
0603
1
4.7UF
10%
35V
X5R-CERM 2
0603
PPVBAT_G3H_CONN
C6993
4.7UF
1
10%
35V
X5R-CERM 2
0603
C6996
4.7UF
NOSTUFF
1
10%
35V
X5R-CERM 2
0603
C6997
C6994
BOOST
10%
10V
CERM
402
LT3470AED
10%
35V
X5R-CERM 2
0603
DFN
8 SHDN*
44
7 NC
CRITICAL
GND
5
SYS_DETECT_L
SW 4
BIAS 2
1
0.22UF
U6990
4.7UF
44
=SMBUS_BATT_SDA
3
VIN
1
NC
=SMBUS_BATT_SCL
CRITICAL
L6995
2
33UH-20%-0.39A-0.435OHM
P3V42G3H_SW
1
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
SWITCH_NODE=TRUE
DIDT=TRUE
1
C6995
22PF
C6950 1
C6960 1
10%
25V
X5R 2
402
2
RCLAMP2402B
10%
25V
X5R 2
603-1
0.1UF
10K
5%
50V
NP0-C0G-CERM
0201
& lt; Ra & gt;
R6995 1
(Switcher limit)
348K
1%
1/20W
MF
201
2
1
C6999
22UF
P3V42G3H_FB
5%
1/16W
MF-LF
2 402
SC-75
1UF
2
R6950
8
Vout = 3.425V
100MA MAX OUTPUT
FB 1
THRM
PAD
1
=PP3V42_G3H_REG
2
DP418C-SM
CRITICAL
D6950
1
7
NOSTUFF
C6992
& lt; Rb & gt;
R6996 1
3
1
2
3
4
5
6
7
8
9
10
11
C6991 1
4.7UF
F-ST-TH
B
Supply needs to guarantee 3.31V delivered to SMC VRef generator
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=18.5V
NOSTUFF
BAT-J5
NC
NC
SOT-323
1
6
J6950
POS
POS
POS
POS
SCL
SDA
SYS_DETECT
NEG
NEG
NEG
NEG
D6905
BAT30CWFILM
R6905
61 8
12
13
14
15
16
17
18
19
20
21
22
PP18V5_DCIN_CONN_R
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=18.5V
1%
1/3W
MF
805
BATTERY CONNECTOR
B
2
9
47
1
20%
2 6.3V
X5R-CERM-1
603
200K
1%
1/20W
MF
201
A
2
Vout = 1.25V * (1 + Ra / Rb)
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SYNC_MASTER=D2_KEPLER
SYNC_DATE=01/13/2012
PAGE TITLE
DC-In & Battery Connectors
DRAWING NUMBER
Apple Inc.
051-9589
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
4.18.0
BRANCH
PAGE
69 OF 132
SHEET
60 OF 99
1
A
8
7
6
5
4
3
2
1
NOSTUFF
CRITICAL
CHGR_5V:LDO
R7092
Q7080
IRF9395TRPBF
61
DIRECTFET-MC
7
10
1
2
8
9
D
S
D
4.7UF
3
6
LT3470A
G
8
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=18.5V
R7080
7
NC
SW
CRITICAL
5%
1/16W
MF-LF
402
2
BIAS
2
GND
FB
THRM
PAD
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
SWITCH_NODE=TRUE
DIDT=TRUE
DP418C-SM
1
CRITICAL
1
& lt; Ra & gt;
R7095 1
C7095
1%
1/20W
MF
201
22PF
5%
50V
NP0-C0G-CERM
0201
2
(CHGR_AGATE)
BAT30CWFILM
0
2
PP5V1_CHGR_VDDP
61
CRITICAL
1
C7098
10UF
D
C7099
10UF
20%
10V
2 X5R
0603
681K
20%
10V
2 X5R
0603
2
Vout = 5.50V
100MA MAX OUTPUT
(Switcher limit)
P5V1_FB
R7081
& lt; Rb & gt;
R7096 1
62K
1%
1/16W
MF-LF
402 2
61
MF-LF 5% 402
1/16W
2
P5V1_BIAS
1
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.25 mm
1
1
33UH-20%-0.39A-0.435OHM
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.5 mm
2
332K
CHGR_DCIN
R7091
L7095
1
CHGR_SGATE_DIV
R7086 1
2
5% 402
1/16W
CHGR_5V:LDO
CRITICAL
2
P5V1_SW
4
SHDN*
NC
100K
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.25 mm
D7005
10%
10V
CERM
402
U7090
PPDCIN_G3H_INRUSH
1
CHGR_AGATE_DIV
CRITICAL
1
0.22UF
9
2
1%
1/16W
MF-LF
402
C7094
BOOST
5
10%
25V
X5R
402
2
MF-LF
DFN
3
470K
0.1UF
=PPDCIN_S5_CHGR_ISOL
R7085
G
C7085
VIN
10%
35V
X5R-CERM 2
0805
C7080
10%
25V
2 X5R-CERM
0603
6
D
1
1
4.7UF
Reverse-Current Protection
0
(P5V1_BIAS) 1
P5V1_BOOST
DIDT=TRUE
C7090
NO STUFF
For EMC
R7090
For Erp Lot6 spec
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.5 mm
P5V1_VIN
2
NC
1
S
1
8
NC
Inrush Limiter
=PPDCIN_S5_CHGR
8
4
5
FROM ADAPTER
0
1
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.5 mm MF-LF 5% 402
1/16W
NC
NC
CHGR_DCIN_D_R
5%
1/16W
MF-LF
402
200K
1%
1/20W
MF
201
Vout = 1.25V * (1 + Ra / Rb)
(CHGR_SGATE)
2
SOT-323
1
R7005
3
61
CHGR_DCIN_D_R
20
1
2
R7021
(CHGR_DCIN)
10
1
5%
1/16W
MF-LF
402
2
ACIN pin threshold is 3.2V, +/- 50mV
1
Divider sets ACIN threshold at 13.55V
Sparkitecture impedance is set by R6912 in 15 " MBP
2
C7002
1UF
R7002
61
2
GND_CHGR_AGND
VDD
12
0
SMC_RESET_L
1
130K
5%
1/16W
MF-LF
402
IN
44
BI
70
1%
1/16W
MF-LF
2 402
44
IN
3
10
4
40.2K
1%
1/16W
MF-LF
2 402
1
R7015
94
330K
94
5%
1/16W
MF-LF
2 402
1
CHGR_ICOMP
CHGR_VCOMP
CHGR_VNEG
CHGR_CSO_P
CHGR_CSO_N
5
7
8
18
17
C7050
1UF
2
C7015
1
0.5%
1W
MF-LF
0612
1
2
1
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=18.5V
CRITICAL
1
20%
2 35V
TANT-POLY
CASE-D2-SM
0.1UF
2
2
C7030
CRITICAL
1
10UF
C7021
10%
25V
X5R
402
SGATE
AGATE
CSIP
CSIN
2
61
26
1
28 94
27 94
CHGR_DCIN
BOOT
UGATE
PHASE
25
23
CHGR_BOOT
CHGR_UGATE
CHGR_PHASE
21
4
1
C7031
CRITICAL
1
10UF
20%
2 35V
TANT-POLY
CASE-D2-SM
C7032
CRITICAL
1
10UF
20%
2 35V
TANT-POLY
CASE-D2-SM
C7033
10UF
20%
2 35V
TANT-POLY
CASE-D2-SM
CRITICAL
1
CRITICAL
1
C7034
BGATE
AMON
36V/V BMON
(OD) ACOK
20V/V
MIN_LINE_WIDTH=0.6 mm
15
14
GATE_NODE=TRUE
CRITICAL
CRITICAL
L7030
1
2
MIN_NECK_WIDTH=0.2 mm
1
2
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
SWITCH_NODE=TRUE
DIDT=TRUE
1
2
=PPBUS_G3H
152S1466
CRITICAL
F7041
OUT
46
OUT
46
OUT
42 45
8AMP-32V-0.006OHM
1
PPVBAT_G3H_CHGR_REG
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.6V
1
5
OMIT_TABLE
CRITICAL
1
C7040
RJK0305DPB
20%
16V
POLY-TANT
CASE-D2E-SM
2
10%
50V
X7R-CERM
0402
CRITICAL
LFPAK-HF
C7045
2
0603
0.001UF
68UF
CRITICAL
353S2392
4
R7050
CRITICAL
Q7055
SI7137DP
1%
1W
MF
0612
SO-8
(GND)
2.2
1
2
(CHGR_CSO_N)
R7052
0
1
2
10%
50V
CERM
0402
C7056
1
0.1UF
2
10%
16V
X7R-CERM
0402
C7057
1
0.01UF
2
10%
16V
X7R-CERM
0402
PPVBAT_G3H_CONN
7 60
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.6V
2
MF-LF
402
CHGR_CSO_R_N
1/16W
MF-LF
402
(PPVBAT_G3H_CHGR_R)
(CHGR_BGATE)
CHGR_ICOMP_RC
C7042
C7011
0.068UF
2
1
CHGR_CSO_R_P
1/16W
96
5%
(PPVBAT_G3H_CHGR_R)
1
96
5%
470PF
2
C7055
10%
25V
X5R
603-1
R7051
D
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=12.6V
1UF
(CHGR_CSO_P)
C7016
S
3
5
2
G
SM
PLACE_NEAR=U7000.29:1mm
PLACE_NEAR=U7000.22:1mm
B
TO/FROM BATTERY
4
3
PPVBAT_G3H_CHGR_R
3
2
1
4
1
2
2
XW7000
1
8 60
0603
CHGR_VNEG_R
1
C
PIME173T-SM
DIDT=TRUE
MIN_NECK_WIDTH=0.2 mm
2
2
10%
50V
X7R-CERM
0402
8AMP-32V-0.006OHM
1
1%
1/16W
MF-LF
402
C7037
0.001UF
2
TO SYSTEM
F7040
4.7UH-20%-14.5A-9MOHM
3
DIDT=TRUE
Q7035
3.01K
1
f = 400 kHz
S
2
R7016 1
10%
35V
2 X5R
603
LFPAK-SM
10%
10V
CERM
402
PLACE_NEAR=U7000.25:2mm
DIDT=TRUE
GATE_NODE=TRUE
CHGR_BGATE
CHGR_AMON
CHGR_BMON
=CHGR_ACOK
16
9
C7025
R7042
5%
1/16W
MF-LF
2 402
C7036
(L7030 limit)
RJK0332DPB-01
1
0
1
1UF
10%
35V
2 X5R
603
20%
2 35V
TANT-POLY
CASE-D2-SM
0.005
B
CRITICAL
C7035
1UF
10UF
Max Current = 8A
Q7030
G
0.22UF
2
CHGR_LGATE
24
CRITICAL
D
CHGR_SGATE
CHGR_AGATE
CHGR_CSI_P
CHGR_CSI_N
220PF
10%
50V
X7R-CERM
0402
3
5
DCIN
MIN_LINE_WIDTH=0.6 mm
29
CHGR_VCOMP_R
10%
16V
X5R
402
2
LGATE
ICOMP
VCOMP
VNEG
CSOP
CSON
(AGND)
R7011
ACIN
11
CHGR_ACIN
1
VHST
CRITICAL
SMB_RST_N
SCL
U7000
TQFN
SDA
VFRQ
CELL
13
0.020
VDDP
6
CHGR_RST_L
=SMBUS_CHGR_SCL
=SMBUS_CHGR_SDA
CHGR_VFRQ
CHGR_CELL
2
R7020
20
5%
1/16W
MF-LF
402
10%
25V
X5R
402
1
0.1UF
10%
10V
X5R
402
100K
2
C7022
1
1UF
R7000
IN
C7001
ISL6259
R7010
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5.1V
PGND
1%
1/16W
MF-LF
402 2
10
CHGR_CSI_R_N
5%
1/16W
MF-LF
402
PP5V1_CHGR_VDDP
22
10%
10V
X5R
402
1K
96
4 2
CHGR_CSI_R_P
PPDCIN_G3H_CHGR
61
5%
1/16W
MF-LF
402
19
R7012 1
1
1
CRITICAL
96
R7022
1
2
THRM_PAD
C
4.7
1
NO STUFF
1
10%
10V
X5R-CERM
0402
R7001
PP5V1_CHGR_VDD
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.1 mm
VOLTAGE=5.1V
=PP3V42_G3H_CHGR
C7020
0.047UF
30mA max load
70 8
2
5%
1/16W
MF-LF
402
10%
16V
X7R-CERM
0402
1
2
2
0.01UF
10%
10V
X5R-CERM
0402
1
C7000
1UF
10%
10V
X5R
402-1
C7005
1
C7026
0.22UF
1
NO STUFF
CRITICAL
0.001UF
10%
50V
X5R-CERM 2
0603-1
61
10%
50V
X7R-CERM
0402
R7055
2
0.001
1%
1W
MF
0612
GND_CHGR_AGND
MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V
2
4
A
1
3
SYNC_MASTER=D2_KEPLER
SYNC_DATE=01/13/2012
PAGE TITLE
PBus Supply & Battery Charger
DRAWING NUMBER
Apple Inc.
051-9589
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
4.18.0
BRANCH
PAGE
70 OF 132
SHEET
61 OF 99
1
A
8
7
6
5
4
3
2
1
D
D
8
8
=PPVIN_S0_VCCSAS0
=PP5V_S0_VCCSAS0
PLACE_NEAR=Q7100.2:1.5mm
VCCSAS0_BOOT_RC
R7101 1
1
C7101
2
20%
10V
X5R
603
1
R7130
2
5%
1/10W
MF-LF
603
20
19
VCC
PVCC
IN
CPU_VCCSASENSE
1
CPU_VCCSASENSE_DIV
2
1%
1/16W
MF-LF
402
10
FB
7
SREF
VCCSAS0_VO
12
VCCSAS0_OCSET
11
14
41.2K
1
1.62K
OUT
VCCSAS0_RTN_DIV
C7103
10%
16V
X5R-X7R-CERM
0402
2
1
2
R7150
1
B
1
1
C7106
10PF
5%
50V
2 C0G-CERM
0402
R7154
8
1%
1/16W
MF-LF
2 402
R7152
1%
1/16W
MF-LF
2 402
1
C7105
IN
5%
50V
2 C0G-CERM
0402
5%
25V
NP0-C0G
402
C
R7140
CRITICAL
0.001
1%
1W
MF-1
0612
PPVCCSA_S0_REG_R
2
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
PIMB053T-SM
=PPVCCSA_S0_REG
2
4
3
8 99
1
6A Max Output
SET1
VID0
5
VID1
f = 300 kHz
3 4 5
(ENDIAN SWAP)
96 45
PGND
R7141
VCCSAS0_CS_P
96 45
1
VCCSAS0_CS_N
1.5K
CPU_VCCSA_VID & lt; 1 & gt;
CPU_VCCSA_VID & lt; 0 & gt;
C7140
1000PF
2
1
5%
25V
NP0-C0G
402
VCCSAS0_SET_R
10PF
1000PF
152S1302
1%
1/16W
MF-LF
402 2
89 13
C7122
SET0
9
GND
IN
2
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
GATE_NODE=TRUE
DIDT=TRUE
2
89 13
2
1.0UH-7A
2
1%
1/16W
MF-LF
402
1
4.64K
4.64K
82.5K
10%
16V
X5R
603
1/16W
MF-LF
402
2
1
6
VCCSAS0_DRVL
R7103 1
0
C7102
5%
2.2UF
1
L7100
7
RTN
R7148
1%
1/16W
MF-LF
2 402
10%
16V
X7R-CERM
0402
CRITICAL
HWSON
1
VCCSAS0_LL
FSEL
1
52.3K
1
0.1UF
CRITICAL
RJK0222DNS
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
SWITCH_NODE=TRUE
DIDT=TRUE
6
1
0.022UF
1
LGATE
1
2
C7121
1
Q7100
13
VCCSAS0_FSEL
SM
16
20%
25V
X5R-CERM
0603
376S0944
VCCSAS0_DRVH
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
GATE_NODE=TRUE
DIDT=TRUE
VCCSAS0_SET1
1%
1/16W
MF-LF
402
XW7101
UGATE
17
C7120
10UF
10%
10V
CERM
402
2
VCCSAS0_SET0
2
2
4
VO
3
VCCSAS0_RTN
70
18
1
PGOOD
R7147
1%
1/16W
MF-LF
2 402
2
CRITICAL
2
OCSET
PVCCSA_PGOOD
1
R7153
CRITICAL
BOOT
PHASE
EN
0.22UF
2
89 13
IN
15
VCCSAS0_SREF
R7151
1.62K
UTQFN
=PVCCSA_EN
C7130
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
DIDT=TRUE
ISL95870AH
70
20%
25V
X5R-CERM
0603
VCCSAS0_VBST
U7100
C
1
0
PP5V_S0_VCCSAS0_VCC
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V
C7119
10UF
10UF
2.2
5%
1/16W
MF-LF
402
CRITICAL
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
DIDT=TRUE
R7149
499K
(VCCSAS0_OCSET)
1%
1/16W
MF-LF
2 402
B
1
R7142
1.5K
1%
1/16W
MF-LF
2 402
1
OCP = R7141 x 8.5uA / R7140
OCP = 8.5A
(VCCSAS0_VO)
XW7100
SM
VCCSAS0_AGND
1
2
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V
PLACE_NEAR=U7100.3:1mm
INTEL TABLE:
VID1
VID0
Voltage
fb = (R7151+R7152)/R7152 = 1.349 and Vref = 0.5;
VID1=1, VIC0=1:
Vout & lt; 1,1 & gt; = Vref x fb;
0
0
0.9V
1
0
0.8V
0
1
0.725V
1
1
0.675V
VID1=0, VID0=1:
Vout & lt; 0,1 & gt; = Vref x (1+R7147 / (R7148 + R7149 )) x fb
VID1=1, VID0=0
Vout & lt; 1,0 & gt; = Vref x (1+ (R7147 + R7148) / R7149 )) x fb
VID1=0, VID0=0
Vout & lt; 0,0 & gt; = Vref x (1+ (R7147 / (R7148 + R7149 // R7150 )) x fb
A
SYNC_MASTER=D2_KEPLER
SYNC_DATE=01/13/2012
PAGE TITLE
System Agent Supply
DRAWING NUMBER
Apple Inc.
051-9589
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
4.18.0
BRANCH
PAGE
71 OF 132
SHEET
62 OF 99
1
A
8
7
6
5
4
2
3
1
D
D
=PP5V_S4_REG
1
C7242
68UF
20%
16V
POLY-TANT
CASE-D2E-SM
1
2
C7241
1
2
2
0.001UF
10%
25V
X5R
603-1
10%
50V
X7R-CERM
0402
2
C7200
1UF
10%
25V
X5R
603-1
1
=PP5V_S4_REG
150UF
20%
2 6.3V
POLY-TANT
CASE-B2-SM
C7252
1
20%
6.3V
POLY-TANT
CASE-D3L-SM
2
CRITICAL
C7250
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
DIDT=TRUE
1
20%
10V
X5R
805
2
2
XW7222
SM
1
P5VS4_VFB1_R
2
XW7220
SM
R7220
40.2K
2
1%
1/16W
MF-LF
402
1
2
GATE_NODE=TRUE
SWITCH_NODE=TRUE
GATE_NODE=TRUE
1
C7299
10%
50V
X7R-CERM
0402
R7256 1
2
3.24K
70
1%
1/16W
MF-LF
402
SM
1
IN
70
VREF2
VREG3
VBST2
26
2.2UF
OUT
9
10
=P5VS4_EN
P5VS4_PGOOD
4
5
24
25
DRVL2
=P5VS5_EN
27
CSP2
CSN2
MODE
VFB1
COMP1
RF
VFB2
COMP2
EN1
PGOOD1
EN2
PGOOD2
1%
1/16W
MF-LF
402
1
IN
2
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
P5VS4_CSP1_R
70
17
3
16
15
21
20
P3V3S5_DRVH
GATE_NODE=TRUE
2
C7283
0.001UF
10%
50V
X7R-CERM
0402
2
Q7260
2 WPAK2
1.0UH-22A
2
1
10%
50V
X7R-CERM
0402
NO STUFF
R7298 1
10
3
4
5%
1/10W
MF-LF
603
5
70
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
DIDT=TRUE
NO STUFF
1
249K
1%
1/16W
MF-LF
402
R7246
1
1.43K
1%
1/16W
MF-LF
402
2
2
1
10K
1%
1/16W
MF-LF
402
C7298
0.001UF
2
R7239 1
2
P3V3S5_SNUBR
2
10%
16V
X7R-CERM
0402
R7206 1
10%
50V
X7R-CERM
0402
R7216
2
3.83K
2
2
P3V3S5_COMP2_R
C7290
1
XW7260
1%
1/16W
MF-LF
402
SM
1
2
5%
50V
C0G-CERM
0402
R7221
1
1
C7236
20%
6.3V
X5R
603
2
2
1
1
4700PF
10%
100V
2 CERM
402
10%
100V
CERM 2
402
(P5VP3V3_VREF2)
20%
6.3V
POLY-TANT
CASE-D3L-SM
2
XW7262
SM
1
P3V3S5_VFB2_R
2
XW7261
SM
1
R7260 1
23.2K
1%
1/16W
MF-LF
402
P3V3S5_CSP2_R
C7238
4700PF
C7292
330UF
PLACE_NEAR=U7200.28:1MM
1
C
150UF
CRITICAL
6
1
OUT
20%
6.3V 2
POLY-TANT
CASE-B2-SM
10UF
0.1UF
70
C7293 1
7
C7288
IN
1
2
C7272
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
1%
1/16W
MF-LF
402
CRITICAL
PCMC063T-SM
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
R7238
F = 400 KHZ
L7260
1
GATE_NODE=TRUE
=P3V3S5_EN
P3V3S5_PGOOD
10A MAX OUTPUT
CRITICAL
RJK0214DPA
8
VOUT = 3.3V
P3V3S5_TG
P3V3S5_RF
P3V3S5_VFB2
P3V3S5_COMP2
XW7200
SM
P5VS4_COMP1_R
1
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
DIDT=TRUE
GATE_NODE=TRUE
SWITCH_NODE=TRUE
P3V3S5_CSP2
P3V3S5_CSN2
2
2
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
P3V3S5_DRVL
1
2
10%
25V
X5R
603-1
0.001UF
2
5%
1/16W
MF-LF
402
12.1K
2
10%
50V
X7R
603-1
0
P3V3S5_LL
12.1K
10K
2
C7264
R7263
THRM_PAD
R7236 1
R7237
18
1
1UF
152S0754
CRITICAL
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
P3V3S5_VBST
DIDT=TRUE
CSP1
CSN1
GND
20%
10V
X5R-CERM
402
DIDT=TRUE
SW2
C7281
=PP3V3_S5_REG
1
DRVH2
1
1
13
22
29
23
2
8
2
10K
2
7
11
3.92K
XW7221
2
DIDT=TRUE
P5VS4_VFB1
P5VS4_COMP1
R7247
1
12
2
C7203
0.1UF
EN
DRVL1
2
10%
16V
X7R-CERM
0402
2
2
DIDT=TRUE
P5VS4_CSP1
P5VS4_CSN1
1
0.0033UF
DRVH1
SW1
30
P5VS4_DRVL
150PF
1
1
32
0.1UF
NO STUFF
10%
10V
CERM
402
DIDT=TRUE
C7218
P5VS4_SNUBR
1
0.22UF
DIDT=TRUE
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
DIDT=TRUE
VBST1
DIDT=TRUE
P5VS4_LL
C7237
B
31
DIDT=TRUE
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
PGND
SKIPSEL1
CRITICAL
SKIPSEL2
U7201
OCSEL
1
QFN
P5VS4_VBST
P5VS4_DRVH
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
BG 5
5%
1/10W
MF-LF
603
5%
1/16W
MF-LF
402
19
14
TGR 4
R7299
1
2
6
P5VP3V3_SKIPSEL
1
P5VS4_TG
NO STUFF
1
2
1
TG 3
R7244 1
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
DIDT=TRUE
6 VSW
7
8
P5VS4_VSW
10UF
330UF
SON5X6
10%
50V
X7R
603-1
9
20%
6.3V 2
POLY-TANT
CASE-B2-SM
CRITICAL
10%
50V
X7R-CERM
0402
PLACE_NEAR=L7220.2:3MM
150UF
1 VIN
PLACE_NEAR=L7220.1:3MM
CRITICAL
C7254 1
2
CSD58872Q5D
0.001UF
2
0.1UF
Q7220
PCMB103T-1R0MS
C7271
C7224
5%
1/20W
MF
201 2
20%
16V
POLY-TANT
CASE-D2E-SM
1
68UF
20%
16V
POLY-TANT
CASE-D2E-SM
20%
6.3V
X5R
603
33
1.0UH-21A-0.006OHM
1
PLACE_NEAR=L7220.1:3MM
C
C7253
CRITICAL
0
5%
1/20W
MF
201 2
VREG5
L7220
CRITICAL
NOSTUFF
1
1
TPS51980
F = 400 KHZ
R72001
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
CRITICAL
VIN
152S0688
C7282
68UF
10UF
C7201
0
28
1
R72011
V5SW
SKIP_5V3V3:AUDIBLE
OMIT_TABLE
CRITICAL
1
C7205
2
SKIP_5V3V3:INAUDIBLE
11A MAX OUTPUT
C7280
2
P5VP3V3_VREF2
VOUT = 5.0V
8
VOUT = 5V
100MA MAX OUTPUT
1
P5VP3V3_VREG3
63 8
OMIT_TABLE
CRITICAL
=PP5V_S5_LDO
C7270
1UF
68UF
20%
16V
POLY-TANT
CASE-D2E-SM
1
PLACE_NEAR=L7260.2:3MM
C7240
OMIT_TABLE
CRITICAL
2
OMIT_TABLE
CRITICAL
PLACE_NEAR=L7260.2:3MM
63 8
=PPVIN_S5_P5VP3V3
PLACE_NEAR=L7260.1:3MM
8
2
C7239
47PF
2
5%
50V
CERM
402
B
R7261 1
10K
(P5VP3V3_VREF2)
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
2
GND_5V3V3_AGND
MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=0V
A
SYNC_MASTER=D2_KEPLER
SYNC_DATE=01/13/2012
PAGE TITLE
5V / 3.3V Power Supply
DRAWING NUMBER
Apple Inc.
051-9589
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
4.18.0
BRANCH
PAGE
72 OF 132
SHEET
63 OF 99
1
SIZE
D
A
8
7
6
5
D
4
3
2
1
D
DDR3 (1V5R1V35 S3) REGULATOR
8
=PPVIN_S3_DDRREG
OMIT_TABLE
CRITICAL
C7330
OMIT_TABLE
CRITICAL
1
C7331
8
8
20%
16V 2
POLY-TANT
CASE-D2E-SM
=PPVIN_S0_DDRREG_LDO
=PP5V_S3_DDRREG
C7301
1
1
C7332
1
C7333
1UF
68UF
68UF
20%
16V 2
POLY-TANT
CASE-D2E-SM
2
1
0.001UF
10%
25V
X5R
603-1
10%
50V
X7R-CERM
0402
2
C7334
1UF
2
10%
25V
X5R
603-1
1
10UF
C7300
20%
10V
X5R
603
1
R7330
2
10UF
1
1
(DDRREG_DRVH)
MIN_LINE_WIDTH=0.6 mm
2
C
2
5%
1/16W
MF-LF
402
MIN_NECK_WIDTH=0.17 mm
2
20%
10V
X5R
603
VLDOIN
DDRREG_DRVH_R
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.17 mm
0.1UF
70
=DDRVTT_EN
=DDRREG_EN
IN
IN
(VTT Enable)
DDRREG_1V8_VREF
OMIT_TABLE
1
C7315
R7315
1
6
8
33 DDRREG_FB
U7300
S3
S5
TPS51916
2
2
DDRREG_MODE
1%
1/16W
MF-LF
402
DDRREG_TRIP
19
18
15
DDRREG_VBST
14
DDRREG_DRVH
13
1
MIN_LINE_WIDTH=0.6 mm
DDRREG_LL
GATE_NODE=TRUE
CSD58872Q5D
3 TG
10%
50V
X7R
603-1
DIDT=TRUE
SWITCH_NODE=TRUE
Q7330
2
DIDT=TRUE
VREF
CRITICAL
REFIN
MODE
TRIP
DRVL
PGOOD
VDDQSNS
VTT
VTTSNS
11
DDRREG_DRVL
20
DDRREG_PGOOD
9
0.68UH-18A-3.3MOHM
4 TGR
DDRREG_VDDQSNS
(DDRREG_LL)
GATE_NODE=TRUE
3
MIN_LINE_WIDTH=0.6 mm
DIDT=TRUE
88
OUT
MIN_NECK_WIDTH=0.17 mm
1
XW7360
8 =PPVTT_S0_DDR_LDO
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.17 mm
PGND
2
PLACE_NEAR=C7361.1:3mm
2
=PPVTT_S3_DDR_BUF 8 33
C7340
20%
2V
TANT
CASE-B4-SM
1
100K
1%
1/16W
MF-LF
402 2
2
1%
1/16W
MF-LF
402
C7316
0.01UF
2
1
10%
16V
X7R-CERM
0402
200K
DDRREG_P1V35_L
2
Q7319
SSM3K15FV
R7317
1%
1/16W
MF-LF
402
4
R7316
VTT THRM
GND PAD
C7360
1
20%
6.3V
X5R
603
1
R7318
61.9K
2
C7360, C7361 close
2
XW7300
D 3
SM
SOD-VESM-HF
NOSTUFF
1
C7350
1
2
2
1
1
2
2
20%
6.3V
X5R
603
10%
50V
X7R-CERM
0402
10UF
270UF
20%
2V
TANT
CASE-B4-SM
C7345
2
XW7301
20%
6.3V
X5R
603
SM
1
PLACE_NEAR=C7340.1:1MM
PLACE_NEAR=C3101.1:3mm
to memory
(DDRREG_VDDQSNS)
MIN_LINE_WIDTH=0.2 mm
0.22UF
10%
10V
CERM
402
C7361
10UF
PLACE_NEAR=C3101.1:1mm
1%
1/16W
MF-LF
2 402
1
10UF
21
150K
10
R7319
1
7
PGND GND
OMIT_TABLE
1
C7341
C7346
0.001UF
CRITICAL
5
10mA max load
NOSTUFF
1
8
Vout = 1.5V
18A max output
(Q7335 limit)
f = 400 kHz
270UF
DIDT=TRUE
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.17 mm
1
=PPDDR_S3_REG
CRITICAL
1
SWITCH_NODE=TRUE
5 BG
(DDRREG_DRVL)
SM
1
2
PCMB103T
152S0905
DDRREG_VSW
DDRREG_VTTSNS
VTTREF
CRITICAL
VSW 6
7
8
SON5X6
VIN 1
L7330
QFN
20.0K
0.1UF
10%
16V
X7R-CERM
0402
17
16
(VDDQ/VTTREF Enable)
VBST
DRVH
SW
9
27 9
V5IN
C
CRITICAL
C7325
MIN_NECK_WIDTH=0.17 mm
12
MIN_NECK_WIDTH=0.17 mm
2
PLACE_NEAR=U7300.7:1mm
GND_DDRREG_SGND
1
G
B
S 2
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.17 mm
VOLTAGE=0V
MEM_VDD_SEL_1V5_L
IN
B
18
PART NUMBER
QTY
DESCRIPTION
REFERENCE DES
CRITICAL
BOM OPTION
114S0343
1
RES,MTL FILM,1/16W,20.0K,1,0402,SMD,LF
R7315
PPDDR:1V5
114S0342
1
RES,MTL FILM,1/16W,19.6K,1,0402,SMD,LF
R7315
PPDDR:1V35
114S0411
1
RES,MTL FILM,1/16W,100K,1,0402,SMD,LF
R7316
PPDDR:1V5
114S0389
1
RES,MTL FILM,1/16W,57.6K,1,0402,SMD,LF
R7316
PPDDR:1V35
A
SYNC_MASTER=D2_KEPLER
SYNC_DATE=01/13/2012
PAGE TITLE
1V5R1V35V DDR3 SUPPLY
DRAWING NUMBER
Apple Inc.
051-9589
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
4.18.0
BRANCH
PAGE
73 OF 132
SHEET
64 OF 99
1
A
8
7
6
5
4
3
D
=PP5V_S0_CPUIMVP
2
1
D
8 66
R7401
10
1
PP5V_S0_CPUIMVP_VCC
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=5V
8
2
5%
1/16W
MF-LF
402
=PPVCCIO_S0_CPUIMVP
=PPVIN_S0_CPUIMVP
1
C7401
R74791
1
R7480
54.9
1
2
2
2.2UF
20%
10V
X6S-CERM
0402
2
1%
1/20W
MF
2 201
29
19
VDDB
VCC 46
PLACE_NEAR=U7400.24:2mm
PLACE_NEAR=U7400.15:2mm
PLACE_NEAR=U7400.16:2mm
VDDA
PLACE_NEAR=U7400.18:2mm
1
QFN
66
OUT
CPUIMVP_AXG_PWM2 13
DRVPWMB
TONB 1
OUT
CPUIMVP_PWM3
37
DRVPWMA
TONA 48
CPUIMVP_TONA
IN
CPUIMVP_ISUM3P
CPU_PROCHOT_L
45
4
CSPA3
VRHOT*
66 65
89 42 41 11
OUT
70
OUT
88
OUT
24
CPUIMVP_PGOOD
CPUIMVP_AXG_PGOOD 12
70
IN
CPUIMVP_VR_ON
47
CPU_VIDSOUT
CPU_VIDSCLK
CPU_VIDALERT_L
21
23
22
VDIO
CLK
ALERT*
100KOHM
100KOHM
0402
2
1
R7463
1
R7461
200K
0402
2
1
R7465
2
137K
CPUIMVP_FBB
1%
1/20W
MF
201
1%
1/20W
MF
201
2
2
66
66
OUT
66
10%
16V
X5R-X7R-CERM NO STUFF
0201
2
IN
46 66 97
IN
66
IN
66
IN
66
C
CPUIMVP_ISNS3_P
1
2
5%
1/20W
MF
201
R7409
40.2K2
OUT
1%
1/20W
MF
201
66
SIGNAL_MODEL=EMPTY
65
CPUIMVP_ISUM3P
NO STUFF
C7418
XW7400
1
C7419
NO STUFF
NO STUFF
1
C7414
1
C7415
1
C7416
65 66
NO STUFF
NO STUFF
1
NO STUFF
1
C7417
C7410
100PF
1
2
100PF
100PF
100PF
100PF
100PF
100PF
5%
25V
NP0-CERM
0201
SM
2
1
66
66
300
SIGNAL_MODEL=EMPTY
R7410
2
66
OUT
46 66 97
1%
1/20W
MF
201
66
OUT
IN
CPUIMVP_ISUMGN
1
66
OUT
NO STUFF
1
137K
1%
1/20W
MF
201
CPUIMVP_ISUM_R
1
PGNDB
AGND
R7467
2
C7409
OUT
2
1
17
2
30
2
CRITICAL
R7469
11
9
10
6
THRM
PAD
PGNDA
1%
1/20W
MF
201
1
470PF
CPUIMVP_BOOT1G
CPUIMVP_UGATE1G
CPUIMVP_PHASE1G
CPUIMVP_LGATE1G
300
SIGNAL_MODEL=EMPTY
R7408
150PF
66
NO STUFF
OUT
CPUIMVP_ISNS2_P
CPUIMVP_ISUMG2P
C7408
65
OUT
46 66 97
1%
1/20W
MF
201
10%
25V
X7R-CERM
0201
14
16
15
18
CSPBAVE
301K
1%
1/20W
MF
201
1
CRITICAL
B
301K
1%
1/20W
MF
201
8
49
200K
1%
1/20W
MF
201
2
1
R7460
GNDSB
2
R7462
GNDSA
1%
1/20W
MF
201
R7464
5
20
2
5.76K
1
2
5.76K
1
66
OUT
IN
R7407
1
OUT
CPUIMVP_ISUM
CPUIMVP_ISUMN
CPUIMVP_FBA
CPUIMVP_ISNS1_P
SIGNAL_MODEL=EMPTY
66
OUT
CPUIMVP_ISUM2P
CPUIMVP_BOOT2
CPUIMVP_UGATE2
CPUIMVP_PHASE2
CPUIMVP_LGATE2
IMAXA
IMAXB
66
OUT
44
34
32
33
31
NO STUFF
1
OUT
BSTB
DHB
LXB
DLB
SR
35
36
7
R7466
OUT
CSPA2
BSTA2
DHA2
LXA2
DLA2
THERMA
THERMB
38
CPUIMVP_IMAXA
CPUIMVP_IMAXB
1
27
26
28
42
182K 2
1%
1/20W
MF
201
66
2
1%
1/20W
MF
201
R7402
1
CPUIMVP_BOOT1
CPUIMVP_UGATE1
CPUIMVP_PHASE1
CPUIMVP_LGATE1
CPUIMVP_ISUM1P
CSPB2
CSPB1
CSNB
FBB
39
40
CPUIMVP_SLEW
R7468
25
CSPAAVE 41
66
CSNA 43
FBA 3
EN
BI
CPUIMVP_NTC
CPUIMVP_NTCG
1
BSTA1
DHA1
LXA1
DLA1
CSPA1
CRITICAL
POKA
POKB
89 13
IN
1
1%
1/20W
MF
201
CPUIMVP_TONB
66
OUT
300
182K 2
CPUIMVP_ISUMG1P
U7400
C
SIGNAL_MODEL=EMPTY
R7406
R7403
MAX15119GTM
89 13
20%
10V
X6S-CERM
0402
130
1%
1/20W
MF
201 2
89 13
8 66
C7403
2.2UF
1
2.2UF
20%
10V
X6S-CERM
0402
C7402
5%
25V
NP0-CERM
0201
5%
25V
NP0-CERM
0201
5%
25V
NP0-CERM
0201
5%
25V
NP0-CERM
0201
5%
25V
NP0-CERM
0201
5%
25V
NP0-CERM
0201
2
2
2
2
2
2
B
GND_CPUIMVP_SGND
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V
PLACE_NEAR=Q7510.1:7mm
PLACE_NEAR=Q7550.1:6mm
C7473
1
C7440
100PF
1000PF
2
SIGNAL_MODEL=EMPTY
66
IN
CPUIMVP_ISUMG_AVEP
1
1
10%
16V
X7R-CERM
0201
1
R7440
CPU_AXG_SENSE_R
10
1
IN
13 89
R7412
1%
1/20W
MF
201
C7441
10%
16V
X7R-CERM
0201
SIGNAL_MODEL=EMPTY
CPU_AXG_SENSE_N
2
1000PF
2
65
12.1K
CPUIMVP_FBA
1
1
NO STUFF
C7442
NO STUFF
1
C7443
10
2
2
CPU_VCCSENSE_N
IN
2
13 89
10
C7422
1%
1/20W
MF
201
2
CPU_VCCSENSE_P
IN
13 89
CPU_AXG_SENSE_P
IN
13 89
1
1000PF
1000PF
R7422
10%
16V
X7R-CERM
0201
16.2K
SIGNAL_MODEL=EMPTY
R7413
1
1%
1/20W
MF
SIGNAL_MODEL=EMPTY 201
10%
16V
X7R-CERM
0201
2
10%
16V
X7R-CERM
0201
CPUIMVP_FBA_R
1000PF
2
C7412
1000PF
5%
25V
NP0-CERM
0201
1%
1/20W
MF
201
R7441
CPU_VCCSENSE_R
1
SIGNAL_MODEL=EMPTY
2
65
CPUIMVP_FBB
1
2
10%
16V
X7R-CERM
0201
2
CPUIMVP_FBB_R
R7423
10
1
1%
1/20W
MF
201
SIGNAL_MODEL=EMPTY
A
2
1%
1/20W
MF
201
SYNC_MASTER=D2_SEAN
SYNC_DATE=03/05/2012
PAGE TITLE
CPU IMVP7 & AXG VCore Regulator
DRAWING NUMBER
Apple Inc.
051-9589
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
4.18.0
BRANCH
PAGE
74 OF 132
SHEET
65 OF 99
1
A
8
7
6
5
2
IRF6802SDTRPBF
2
20%
16V
X6S-CERM
0603
2
DIRECTFET-SA
L7510
1
5%
1/16W
MF-LF
402 2
R7512
2.2
CPUIMVP_UGATE1
IN
97 65 46
DIDT=TRUE
G
4
SWITCH_NODE=TRUE
DIRECTFET_S3C
CPUIMVP_LGATE1
376S1011
S
DIDT=TRUE
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
2
GATE_NODE=TRUE
8
66
R7521
0
20%
16V
POLY-TANT
CASE-D2E-SM
2
2
2
20%
16V
X6S-CERM
0603
DIRECTFET-SA
1
2
R7514
10
65
1%
1W
MF
0612
IN
IN
65
IN
DIDT=TRUE
DIDT=TRUE
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
65 66
10%
50V
X7R-CERM
0402
1
3
5
6
2
65
C7581
330PF
97 65 46
4
G
CPUIMVP_LGATE2
IN
DIDT=TRUE
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
GATE_NODE=TRUE
D
8 66
1
1%
1/20W
MF
201 2
2
R7524
10
1%
1/20W
MF
201
CPUIMVP_ISUMN
65 66
NOSTUFF
1
DIRECTFET_S3C
10%
16V
X7R-CERM
0201
C7522
0.001UF
376S1011
1
10%
50V
X7R-CERM
0402
2
2
C7582
330PF
10%
16V
X7R-CERM
0201
CPUIMVP_ISUM2P
CPUIMVP_ISUM1P
65
OMIT_TABLE
CRITICAL
649136PBF
S1
PHASE 3
D
376S1014
C
1
5
R7547
2
10K
VDD
5%
1/16W
MF-LF
402
2
2
68UF
20%
16V
POLY-TANT
CASE-D2E-SM
20%
16V
POLY-TANT
CASE-D2E-SM
2
20%
16V
X6S-CERM
0603
2
20%
16V
X6S-CERM
0603
2
R7531
3.3
U7541
IN
66
2
CPUIMVP_SKIP
6
TQFN
PWN
BST
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM
CRITICAL
DH
SKIP*
8
LX
4
GATE_NODE=TRUE
D
CPUIMVP_PHASE3
THRM
PAD
DIDT=TRUE
3
97 65 46
G
4
CPUIMVP_LGATE3
R7533
46.4
Q7535
1
1%
1/20W
MF
201 2
376S1011
2
1
10%
50V
X7R-CERM
0402
1
10%
16V
X7R-CERM
0201
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM
DIDT=TRUE
IN
D
S
20%
16V
POLY-TANT
CASE-D2E-SM
CPUIMVP_PHASE1G
DIDT=TRUE
CPUIMVP_LGATE1G
NOSTUFF
CRITICAL
D
1
Q7551
2
G
DIRECTFET_S3C
376S1011
152S1538
R7552
2.2
2
S
3
5
6
1
5
R7540
10K
2
VDD
5%
1/16W
MF-LF
402
C7552
0.001UF
10%
50V
X7R-CERM
0402
66
CPUIMVP_SKIP
2
C7559
0.001UF
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
6
TQFN
PWN
BST
1
DH
8
LX
D
4
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
9
3
THRM
PAD
=PPVCORE_S0_AXG_REG
R7553
46.4
1%
1/20W
MF
201
1
2
CPUIMVP_ISNS1G_N
1
2
R7554
10
7
G
65 66
CRITICAL
1
Q7561
5%
1/16W
MF-LF
402 2
2
2
10%
16V
CERM
402
CPUIMVP_ISNS2G_P
2
NOSTUFF
CPUIMVP_ISNS1G_P
376S1011
46 66 96
2
C7587
0.001UF
10%
50V
X7R-CERM
0402
R7561
46.4
2
C7566
0.001UF
10%
50V
X7R-CERM
0402
R7563
1%
1/20W
MF
201 2
CPUIMVP_ISUMGN
1
65 66
C7567
330PF
10%
16V
X7R-CERM
0201
CPUIMVP_ISUMG2P
CPUIMVP_ISUMG_AVEP
10%
16V
X7R-CERM
0201
46 97
1%
1/20W
MF
201
2
1%
1/20W
MF
2 201
8 45 66
R7562
10
1
1%
1/20W
MF
201 2
200
1
65
65
1
R7566
CPUIMVP_ISUMG1P
0
NOSTUFF
65
5%
1/20W
MF
1
R7565
DIDT=TRUE
0
DIDT=TRUE
DIDT=TRUE
10%
16V
X7R-CERM
0201
DIDT=TRUE
5
4
CPUIMVP_ISUMGN
3
DRAWING NUMBER
NOSTUFF
1
1000PF
GATE_NODE=TRUE
SYNC_DATE=03/05/2012
CPU IMVP7 & AXG VCore Output
CPUIMVP_ISUMG_AVE_RP
C7568
SWITCH_NODE=TRUE
SYNC_MASTER=D2_SEAN
PAGE TITLE
2 201
5%
1/20W
MF
201 2
GATE_NODE=TRUE
6
1
1
DIRECTFET_S3C
C7584
330PF
10%
50V
X7R-CERM
0402
CPUIMVP_ISNS2G_N
DIDT=TRUE
200
C7530
0.22UF
2
1
C7565
0.001UF
4
CPUIMVP_AXG2_SNUB
DIDT=TRUE
2
1
=PPVCORE_S0_AXG_REG
2
5%
1/10W
MF-LF
2 603
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.25 MM
1
1
MIN_LINE_WIDTH=0.6 MM 3
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
R7587
2.2
R7564
CPUIMVP_ISUMGN
10%
16V
X6S-CERM
0402
B
1%
1W
MF
0612
PPVCORE_S0_AXG2_L
2
NOSTUFF 152S1538
1
CPUIMVP_BOOT2G_RC
20%
16V
X6S-CERM
0603
C7564
1UF
0.00075
649135PBF
4
2
1
C7563
10UF
R7560
PIMS103T-SM
D
1%
1/20W
MF
201
2
L7560
3
96 46
DIDT=TRUE
R7535
3.3
2
20%
16V
X6S-CERM
0603
0.36UH-20%-36A-0.00108OHM
CPUIMVP_LGATE2G
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
20%
16V
POLY-TANT
CASE-D2E-SM
1
CPUIMVP_PHASE2G
MIN_LINE_WIDTH=1.5 MM
MIN_NECK_WIDTH=0.2 MM
68UF
CRITICAL
1
C7562
10UF
CRITICAL
DIRECTFET-SA
8 45 66
66 65
8
C7561
20%
16V
POLY-TANT
CASE-D2E-SM
THESE TWO CAPS ARE FOR EMC
NOSTUFF
CRITICAL
1
CRITICAL
IRF6802SDTRPBF
CPUIMVP_UGATE2G
7
DL
SKIP*
GND
C7560
97 46
CPUIMVP_BOOT2G
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM
CRITICAL
4
CPUIMVP_ISNS1G_P
96 66 46
1
NOSTUFF
CRITICAL
1
CRITICAL
Q7550
376S1010
10%
50V
X7R-CERM
0402
1
1
10%
16V
X6S-CERM
0402
U7542
2
2
C7540
1UF
MAX17491
IN
10%
50V
X7R-CERM
0402
S
2
65
2
1
C7558
0.001UF
S
1%
1W
MF
0612
PPVCORE_S0_AXG1_L
5%
1/10W
MF-LF
603
NOSTUFF
=PP5V_S0_CPUIMVP
CPUIMVP_AXG_PWM2
10%
16V
X6S-CERM
0402
1 G
CPUIMVP_AXG1_SNUB
2
1
C7557
1UF
0.00075
PIMS103T-SM
DIDT=TRUE
GATE_NODE=TRUE
1
A
2
L7550
649135PBF
1
20%
16V
X6S-CERM
0603
0.36UH-20%-36A-0.00108OHM
4
66 65 8
2
1
C7556
10UF
CRITICAL
SWITCH_NODE=TRUE
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
1
R7550
1
2
8
7
IN
20%
16V
X6S-CERM
0603
CRITICAL
1
65
2
C7555
10UF
CRITICAL
4
DIDT=TRUE
GATE_NODE=TRUE
MIN_LINE_WIDTH=1.5 MM
MIN_NECK_WIDTH=0.2 MM
1
C7554
68UF
DIRECTFET-SA
2
CPUIMVP_UGATE1G
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
1
IRF6802SDTRPBF
2 G
2
CRITICAL
5
6
7
8
10%
16V
CERM
402
2
THESE TWO CAPS ARE FOR EMC
NOSTUFF
CRITICAL
Q7550
NC
NC
65
IN
OMIT_TABLE
CRITICAL
3
65
OMIT_TABLE
1
2
8
7
CPUIMVP_BOOT1G
65
1
3
5
6
IN
OMIT_TABLE
CRITICAL
20%
2 16V
TANT
SM
C7583
330PF
3
5
6
65
376S1010
15UF
20%
2 16V
TANT
SM
65 66
C7576
C7532
0.001UF
68UF
1
CRITICAL
1
C7573
15UF
CPUIMVP_ISUMN
DIDT=TRUE
NOSTUFF
1
(B SIZE)
CRITICAL
CPUIMVP_BOOT1G_R
C7551
0.22UF
20%
2 16V
TANT
SM
20%
16V
POLY-TANT
CASE-D2E-SM
8 66
1%
1/20W
MF
201
2
AXG PHASE 2
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM
DIDT=TRUE
2
C7578
15UF
68UF
20%
2 16V
TANT
SM
20%
16V
POLY-TANT
CASE-D2E-SM
CRITICAL
1
C7575
R7534
10
CPUIMVP_ISUM3P
NC
NC
B
5%
1/16W
MF-LF
402
2
CRITICAL
1
15UF
68UF
20%
16V
POLY-TANT
CASE-D2E-SM
C7574
CPUIMVP_ISNS3_N
97 46
1
R7582
46.4
CPUIMVP_PH3_SNUB
CRITICAL
R7556
2
CRITICAL
1
C7572
1
1%
1/20W
MF
201 2
DIRECTFET_S3C
DIDT=TRUE
GATE_NODE=TRUE
CPUIMVP_ISNS3_P
5%
1/10W
MF-LF
603 2
=PPVIN_S0_CPUAXG
0
68UF
2
OMIT_TABLE
CRITICAL
1
C7571
4
AXG PHASE 1
1
1
20%
16V
POLY-TANT
CASE-D2E-SM
2
=PPVCORE_S0_CPU_REG
2
2
8
OMIT_TABLE
CRITICAL
C7570
68UF
10%
50V
X7R-CERM
0402
2
OMIT_TABLE
CRITICAL
1
C
1
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=1.25V
1
649135PBF
SWITCH_NODE=TRUE
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
9
3
R7532
2.2
DIDT=TRUE
MIN_LINE_WIDTH=1.5 MM
MIN_NECK_WIDTH=0.2 MM
PIMS103T-SM
NOSTUFF
CPUIMVP_UGATE3
7
DL
PPVCORE_S0_CPU_PH3
2
152S1538
DIDT=TRUE
DIDT=TRUE
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
GND
2
10%
50V
X7R-CERM
0402
C7539
0.001UF
SWITCH_NODE=TRUE
CPUIMVP_BOOT3
1
1
MIN_LINE_WIDTH=1.5 MM
MIN_NECK_WIDTH=0.2 MM
10%
16V
CERM
402
1
2
8
7
CPUIMVP_PWM3
2
1%
1W
MF
0612
0.36UH-20%-36A-0.00108OHM
C7531
0.22UF
10%
16V
X6S-CERM 2
0402
1
C7538
0.001UF
0.00075
1
1
1
C7537
1UF
R7530
CRITICAL
L7530
CPUIMVP_PHASE3_L
10%
16V
X6S-CERM
0402
OMIT_TABLE
1
C7536
10UF
CRITICAL
S
DIDT=TRUE
C7541
1UF
5%
1/16W
MF-LF
402 2
MAX17491
65
C7534
CRITICAL
1
C7535
10UF
6
G
3
S
2
C7533
CRITICAL
1
CPUIMVP_BOOT3_RC
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.25 MM
1
CRITICAL
1
68UF
1
THESE TWO CAPS ARE FOR EMC
OMIT_TABLE
CRITICAL
1
5
4
=PP5V_S0_CPUIMVP
65
Additonal Input Bulk Caps (D SIZE)
Q7530
66 65 8
10%
50V
X7R-CERM
0402
2
CPUIMVP_ISNS2_N
97 46
1
DIDT=TRUE
649135PBF
SWITCH_NODE=TRUE
2
C7529
0.001UF
4
CPUIMVP_ISNS2_P
CPUIMVP_PH2_SNUB
Q7525
DIDT=TRUE
10%
50V
X7R-CERM
0402
=PPVCORE_S0_CPU_REG
2
3
R7523
46.4
CRITICAL
D
GATE_NODE=TRUE
CPUIMVP_PHASE2
MIN_LINE_WIDTH=1.5 MM
MIN_NECK_WIDTH=0.2 MM
C7512
0.001UF
1
1
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=1.25V
152S1538
CPUIMVP_UGATE2
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM
CPUIMVP_ISUMN
2 PPVCORE_S0_CPU_PH2
5%
1/10W
MF-LF
603 2
CPUIMVP_BOOT2
65
1%
1/20W
MF
201
R7522
2.2
1
C7528
0.001UF
R7520
PIMS103T-SM
NOSTUFF
10%
16V
CERM
402
2
2
1
10%
16V
X6S-CERM
0402
0.00075
L7520
C7521
0.22UF
20%
16V
X6S-CERM
0603
C7527
1UF
CRITICAL
1
1
1
C7526
10UF
2
CRITICAL
1
5%
1/16W
MF-LF
402 2
CPUIMVP_ISNS1_N
97 46
1
NOSTUFF
1
=PPVCORE_S0_CPU_REG
4
DIDT=TRUE
649135PBF
68UF
CRITICAL
1
C7525
10UF
0.36UH-20%-36A-0.00108OHM
1%
1/20W
MF
201 2
CPUIMVP_PH1_SNUB
Q7515
C7524
20%
16V
POLY-TANT
CASE-D2E-SM
IRF6802SDTRPBF
S
DIDT=TRUE
2
CPUIMVP_ISNS1_P
Q7510
D
2 G
3
R7513
46.4
CRITICAL
D
DIDT=TRUE
GATE_NODE=TRUE
MIN_LINE_WIDTH=1.5 MM
MIN_NECK_WIDTH=0.2 MM
IN
1
5%
1/10W
MF-LF
603 2
CPUIMVP_PHASE1
IN
152S1538
1
2
8
7
DIDT=TRUE
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
65
10%
16V
CERM
402
PHASE 2
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.25 MM
1
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=1.25V
PIMS103T-SM
NOSTUFF
CPUIMVP_BOOT1
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM
65
2
C7511
0.22UF
2
C7523
CRITICAL
1
68UF
CRITICAL
376S1010
THESE TWO CAPS ARE FOR EMC
NOSTUFF
CRITICAL
1
CPUIMVP_BOOT2_RC
1%
1W
MF
0612
2 PPVCORE_S0_CPU_PH1
1
1
NC
NC
R7511
0
2
10%
50V
X7R-CERM
0402
0.00075
0.36UH-20%-36A-0.00108OHM
D
2
10%
50V
X7R-CERM
0402
1
C7519
0.001UF
R7510
CRITICAL
4
DIDT=TRUE
2
10%
16V
X6S-CERM
0402
1
C7518
0.001UF
CRITICAL
S
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.25 MM
20%
16V
X6S-CERM
0603
1
C7517
1UF
7
8
20%
16V
POLY-TANT
CASE-D2E-SM
OMIT_TABLE
CRITICAL
1
C7516
10UF
1
2
8
7
1 G
68UF
20%
16V
POLY-TANT
CASE-D2E-SM
OMIT_TABLE
CRITICAL
1
C7515
10UF
3
Q7510
D
C7514
68UF
THESE TWO CAPS ARE FOR EMC
NOSTUFF
CRITICAL
1
CPUIMVP_BOOT1_RC
65
1
3
5
6
5
6
PHASE 1
C7513
CRITICAL
376S1010
NOSTUFF
CRITICAL
1
NC
NC
CRITICAL
S
OMIT_TABLE
OMIT_TABLE
1
IN
2
3
=PPVIN_S0_CPUIMVP
65 8
65
4
1
Apple Inc.
C7569
330PF
051-9589
R
16V
2 X7R-CERM
0201
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
2
D
4.18.0
10%
2
SIZE
REVISION
BRANCH
PAGE
75 OF 132
SHEET
66 OF 99
1
A
8
7
6
5
4
3
2
1
D
D
CPU VCCIO (1V0R1V05 S0) REGULATOR
PART NUMBER
QTY
DESCRIPTION
REFERENCE DES
CRITICAL
BOM OPTION
114S0260
2
RES,MTL FILM,1/16W,2.74K,1,0402,SMD,LF
R7605,R7645
PPCPUVCCIO:SNB
114S0264
2
RES,MTL FILM,1/16W,3.01K,1,0402,SMD,LF
R7605,R7645
PPCPUVCCIO:IVB
8
8
=PPVIN_S0_CPUVCCIOS0
=PP5V_S0_CPUVCCIOS0
CPUVCCIOS0_BOOT_RC
R76011
1
5%
1/16W
MF-LF
402 2
R76301
3.01K
R7644
& lt; Ra & gt;
2
UTQFN
=CPUVCCIOS0_EN
IN
& lt; Ra & gt;
3
CPUVCCIOS0_FB
70
6
FB
4
SREF
CRITICAL
BOOT
12
UGATE
11
10
2.74K
1%
1/16W
MF-LF
402
2
& lt; Rb & gt;
B
2
PGOOD
9
2
C7602
1
& lt; Rb & gt;
C7604
1
1
10PF
5%
50V
C0G-CERM
0402
C7605
1
2
2
CRITICAL
0.001
1%
1W
MF-1
0612
0.82UH-20%-13A-0.0067OHM
1
2
PPCPUVCCIO_S0_REG_R
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.0V
152S1238
=PPCPUVCCIO_S0_REG
1
2
3
4
CRITICAL
C7649
C7623
R7603
20%
2V
TANT
CASE-B4-SM
1
1000PF
5%
25V
NP0-C0G
402
5
2
2
1
9A MAX OUTPUT
f = 300 kHz
270UF
PLACE_NEAR=L7630.2:1.5mm
4
8
VOUT = 1.05V
FSEL
2
2
CRITICAL
1
PGND
C7648
270UF
20%
2 2V
TANT
CASE-B4-SM
5%
1/16W
MF-LF
402
96 45
10%
16V
X7R-CERM
0402
2
R7640
L7630
1
1
R7641
XW7600
1
CPUVCCIOS0_CS_N
B
1.87K
SM
CPUVCCIOS0_AGND
CPUVCCIOS0_CS_P
96 45
0.047UF
5%
50V
C0G-CERM
0402
C
CRITICAL
CRITICAL
POWERPAK-6X3.7
C7603
10PF
5%
25V
NP0-C0G
402
0
2.2UF
10%
16V
X5R
603
1000PF
6
RTN
5
GND
1%
1/16W
MF-LF
402
2
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
GATE_NODE=TRUE
DIDT=TRUE
R7645
1
2
C7622
Q7630
IHLP2525CZ-SM
CPUVCCIOS0_DRVL
CPUVCCIOS0_FSEL
2.74K
1
16
1
20%
16V
POLY-TANT
CASE-D2E-SM
SIZ710DT
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
SWITCH_NODE=TRUE
DIDT=TRUE
VO
1
R7605 1
1
68UF
20%
16V 2
POLY-TANT
CASE-D2E-SM
8
OCSET
CPUVCCIOS0_PGOOD
OMIT_TABLE
7
CPUVCCIOS0_LL
7
LGATE
15
3
CPUVCCIOS0_DRVH
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
GATE_NODE=TRUE
DIDT=TRUE
8
CPUVCCIOS0_RTN
OMIT_TABLE
C7621
68UF
10%
25V
X5R
402
376S0959
CPUVCCIOS0_VO
OUT
2
OMIT_TABLE
CRITICAL
1
PLACE_NEAR=Q7630.1:1.5mm
2
CPUVCCIOS0_OCSET
70
C7620
10%
16V
X5R
402
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
DIDT=TRUE
PHASE
EN
2
CPUVCCIOS0_VBST
ISL95870
1%
1/16W
MF-LF
402
CPUVCCIOS0_SREF
2
PVCC
U7600
3.01K
C7630
1UF
0
VCC
1
C7625
1UF
1
5%
1/10W
MF-LF
603 2
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V
Vout = 0.5V * (1 + Ra / Rb)
R7604 1
1
14
CPU_VCCIOSENSE_N
1%
1/16W
MF-LF
402
20%
10V
X5R
603
PP5V_S0_CPUVCCIOS0_VCC
CPU_VCCIOSENSE_P
89 13
2
13
89 13
OMIT_TABLE
CRITICAL
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
DIDT=TRUE
10UF
2.2
C
C7601
1%
1/16W
MF-LF
402 2
2
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V
C7640
1000PF
2
PLACE_NEAR=U7600.1:1mm
1
5%
25V
NP0-C0G
402
1
R7642
1.87K
1%
1/16W
MF-LF
2 402
(CPUVCCIOS0_OCSET)
(CPUVCCIOS0_VO)
OCP = R7641 x 8.5uA / R7640
OCP = 10.3A
A
SYNC_MASTER=D2_KEPLER
SYNC_DATE=01/13/2012
PAGE TITLE
CPU VCCIO (1V0R1V05 S0) POWER SUPPLY
DRAWING NUMBER
Apple Inc.
051-9589
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
4.18.0
BRANCH
PAGE
76 OF 132
SHEET
67 OF 99
1
A
8
7
6
5
4
3
2
1
1.8V S0 Regulator
8
=PP3V3_S5_P1V2P1V8
PART NUMBER
22UF
20%
6.3V
X6S-CERM 2
0805
2
QTY
3
353S3739
DESCRIPTION
REFERENCE DES
IC,ISL8014A,SYNC BUCK REG,4A 1MHZ,QFN16
1
VDD
5%
25V
NP0-C0G
402
1
C7720
1000PF
VIN
C7724
1
2
CRITICAL
1
U7720
CRITICAL
152S1302
L7720
OMIT_TABLE
1.0UH-7A
U7720
PIMB053T-SM
=PP1V8_S0_REG
ISL8014A
D
70
IN
=P1V8S0_EN
5
P1V8S0_PGOOD
QFN
EN
OUT
PG
SYNCH
P1V8S0_SW
14
LX
LX
CRITICAL
7
4
70
1
1
THRM_PAD
NC
R7720
NC
NC
NC
6
13
2
113K
1%
1/16W
MF-LF
402
C7721
22UF
1
C7723
47PF
1
Max Current = 4A
Freq = 1 MHz
20%
6.3V
2 X6S-CERM
0805
5%
50V
CERM
402
1.05V SUS LDO
2
17
PGND
12
11
SGND
9
P1V8S0_FB
16
D
Vout = 1.794V
CRITICAL
CRITICAL
8
8
2
SWITCH_NODE=TRUE
DIDT=TRUE
15
VFB
10
BOM OPTION
& lt; Ra & gt;
Panther Point-M requires JTAG pull-ups to be powered at 1.05V in Sus.
Pull-ups (3) must be 51 ohms to support XDP (not required in production).
70mA is required to support pull-ups. Alternative is strong voltage
dividers (200/100) to 3.3V Sus, which burns 100mW in all S-states.
CRITICAL
R7721 1
C7722 1
90.9K
CRITICAL
XDP_PCH
22UF
1%
1/16W
MF-LF
402 2
20%
6.3V
X6S-CERM 2
0805
U7740
& lt; Rb & gt;
TPS720105
SON
=PP3V3_SUS_P1V05SUSLDO
8
4
IN
3
EN
OUT
GND
1
1UF
10%
6.3V
CERM
402
C
5
2
8
2
Vout = 1.05V
1
NC
XDP_PCH
C7740
=PP1V05_SUS_LDO
BIAS
6
Vout = 0.8V * (1 + Ra / Rb)
THRM
PAD
Max Current = 0.35A
NC
XDP_PCH
1
C7741
2.2UF
7
2
10%
6.3V
X5R
402
C
1.5V S0 Regulator
8
=PP3V3_S5_P1V5S0
CRITICAL
1
1
C7750
22UF
VIN
20%
6.3V
U7710
2
CRITICAL
CERM
805
ISL8009B
L7770
2.2UH-3A
DFN
70
2
=P1V5S0_EN
IN
EN
CRITICAL
LX
8
OUT
3
P1V5S0_PGOOD
POR
VFB
SKIP
RSI
2
Vout = 1.508V
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
SWITCH_NODE=TRUE
DIDT=TRUE
6
4
70
PCMB042T-IHLP1616BZ
5
GND
152S0691
1
C7776
1
5%
50V
CERM
402
9
353S2535
Max Current = 1.5A
R7780
100K
47PF
THRM_PAD
7
=PP1V5_S0_REG 8
1
1V5_S0_SW
Freq = 1.6MHZ
1%
1/16W
2
MF-LF
CRITICAL
402
2
& lt; Ra & gt;
1V5_S0_FB
1
C7771
22UF
20%
6.3V
1
2
R7781
CERM
805
113K
1%
1/16W
MF-LF
402
2
& lt; Rb & gt;
B
B
Vout = 0.8V * (1 + Ra / Rb)
1.5V S0 LDO (RIO)
P1V5S0:REG
=PP5V_S0_P1V5_LDO
P1V5S0:LDO
8
R7735
R77331
1
100
P1V5S0:LDO
R7730
C7731
1
2
IN0
IN1
5
1
mm
MIN_NECK_WIDTH=0.15 mm
VOLTAGE=1.5V
EN
OUT0
OUT1
9
10
20%
6.3V 2
X5R
0201-MUR
FB
8
TPS74701
P1V5S0_LDO_SS
P1V5S0:LDO
P1V5S0:LDO
1
1.0UF
20%
6.3V 2
X5R
0201-MUR
1
SON
1%
1/20W
MF
201 2
SS
PG
P1V5S0_LDO_FB
& lt; Ra & gt;
P1V5S0:LDO
3
R77371
2.2NF
10%
10V
2 X5R-CERM
0201
0
2
5%
1/16W
MF-LF
402
R77361
8
Vout = 1.563V
Max Current = 0.5A
Over 1.5V to compensate for flex loss
P1V5S0:LDO
1
C7732
4.7UF
20%
4V
2 X5R-1
402
4.42K
1%
1/20W
MF
201 2
GND THRML_PAD
C7733
6
C7730
7
1
P1V5S0:LDO
4.22K
U7730
1.0UF
A
CRITICAL
PP1V5_S0_LDO
P1V5S0:LDO MIN_LINE_WIDTH=0.6
BIAS
PP1V8_S0_P1V5_LDO
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.8V
P1V5S0:LDO
=PP1V5_S0_RIO_LDO
R7734
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V
0
5%
1/16W
MF-LF
402 2
2
P1V5S0:LDO
PP5V_S0_P1V5_LDO_BIAS
1
4
=PP1V8_S0_P1V5_LDO
5%
1/20W
MF
201 2
11
8
0
5%
1/16W
MF-LF
402
& lt; Rb & gt;
SYNC_MASTER=D2_KEPLER
Misc Power Supplies
Vout = 0.8V * (1 + Ra / Rb)
P1V5S0:LDO
DRAWING NUMBER
Apple Inc.
R77381
100K
5%
1/20W
MF
201 2
8
7
SYNC_DATE=01/13/2012
PAGE TITLE
051-9589
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
P1V5S0_LDO_PGOOD
6
5
4
3
2
SIZE
D
REVISION
4.18.0
BRANCH
PAGE
77 OF 132
SHEET
68 OF 99
1
A
8
7
6
5
4
3
2
1
R7803
0
376S0945
CRITICAL
3.3V SUS FET
CRITICAL
Q7820
SIA427DJ
NOSTUFF
SC70-6L
7
=PP3V3_S5_P3V3SUSFET
4
8
D
D
0.033UF
220K
10%
16V
5%
1/16W
SOT563
2
X5R
MF-LF
70
IN
3.3V SUS FET
402
402
MOSFET
SiA427
CHANNEL
C7800
2
P-TYPE 8V/5V
5
0.01UF
70
G
S
1
1
P3V3S3_S4
2
1
1
=P3V3S4_EN
RDS(ON)
10%
10%
100? mA (EDP)
16V
X7R-CERM
0402
26 mOhm @1.8V
LOADING
5%
1/16W
26 mOhm @1.8V
LOADING
5%
1/16W
MF-LF
2
P-TYPE 8V/5V
RDS(ON)
2
4
=P3V3SUS_EN
IN
1
P3V3SUS_SS
2
402
P3V3S4_EN_L
SiA427
CHANNEL
0.01UF
12K
P3V3SUS_EN_L
D
MOSFET
C7820
2
R7820
47K
S
2
X5R
MF-LF
3.3V S4 FET
R7800
G
10%
16V
1/16W
SOT563
402
402
0.033UF
100K
SSM6N15FEAPE
1
G
6
SSM6N15FEAPE
2
8
1
C7821
3
D
3
1
5%
C7809
1
R7802
R7822
G
8
3
1
D
S
4
=PP3V3_S4_FET
Q7802
Q7802
=PP3V3_SUS_FET
7
SC70-6L
=PP3V3_S4_P3V3S4FET
8
D
Q7800
SIA427DJ
S
3.3V S4 FET
2
5%
1/16W
MF-LF
402
1
1
0.7? A (EDP)
16V
MF-LF
X7R-CERM
402
0402
5V SUS FET
5V_SUS FET INPUT FILTER
CRITICAL
CRITICAL
Q7840
Q7810
SIA413DJ
R7843
SC70-6L
C7843
MF-LF
1
C7811
0.033UF
100K
10%
16V
5%
1/16W
SOT563
X5R
MF-LF
402
1
PLACE_NEAR=Q7840.4:5mm
G
R7812
6
IN
G
S
402
P3V3S3_EN_L
1
D
3
1
0.033UF
220K
SOD-VESM-HF
10%
16V
5%
MOSFET
C7810
2
X5R
1
P3V3S3_SS
2
CHANNEL
P-TYPE 8V/5V
RDS(ON)
2
26 mOhm @1.8V
1
70
5%
10%
G
S
P5VSUS_EN_L
1
1
P5VSUS_SS
2
2
RDS(ON)
10%
402
LOADING
0402
X7R-CERM
29 mOhm @4.5V
2 mA (EDP)
16V
402
16V
X7R-CERM
LOADING
5%
1/16W
MF-LF
MF-LF
P-TYPE 12V
2
=P5VSUS_EN
IN
SiA413
CHANNEL
0.01UF
3.3K
1
1/16W
MOSFET
C7840
R7840
0.01UF
8
5V SUS FET
402
2
SiA427
=PP5V_SUS_FET
1
C7841
402
47K
2
SSM3K15FV
2
402
R7842
MF-LF
2
=P3V3S3_EN
X5R-CERM
3.3V S3 FET
Q7842
1/16W
2
R7810
70
20%
10V
3
D
Q7812
SSM6N15FEAPE
1
2.2UF
402
4
1/16W
8
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.1 MM
VOLTAGE=5V
NO STUFF
D
PP5V_S5_P5VSUSFET_R
G
1
=PP3V3_S3_FET
7
2
5%
D
4
S
7
=PP3V3_S3_P3V3S3FET
8
0
1
8 =PP5V_S5_P5VSUSFET
S
SC70-6L
1
SIA427DJ
3
3.3V S3 FET
0402
3 A (EDP)
CRITICAL
Q7850
5V S3 FET
3.3V S0 FET
CRITICAL
Q7830
SIA427DJ
C
SC70-6L
C
SI7615DN
7
PWRPK-1212-8
=PP5V_S3_FET
=PP3V3_S0_P3V3S0FET
=PP3V3_S0_FET
8
SSM6N15FEAPE
1/16W
SOT563
X5R
MF-LF
402
2
R7832
402
MOSFET
R7850
70
G
S
P5VS3_EN_L
1
1
P5VS3_SS
2
D
1
C7831
47K
3
MOSFET
2
X5R
402
402
C7830
2
R7830
RDS(ON)
10%
3 A (EDP)
5
0402
5.5 mOhm @4.5V
LOADING
P3V3S0_EN_L
16V
X7R-CERM
402
RDS(ON)
0.01UF
5.6 A (EDP)
33K
26 mOhm @1.8V
LOADING
5%
1/16W
MF-LF
P-TYPE 20V/12V
16V
MF-LF
SOT563
SI7615DN
CHANNEL
10%
5%
1/16W
SSM6N15FEAPE
2
1
0.033UF
1
=P5VS3_EN
IN
P-TYPE 8V/5V
0.01UF
47K
2
Q7812
SiA427
CHANNEL
C7850
2
3.3V S0 FET
1
5V S3 FET
5
1
10%
16V
5%
G
C7851
0.033UF
100K
4
1
G
R7852
6
3
D
Q7852
2
D
8
S
8
3
1
D
4
S
=PP5V_S4_P5VS3FET
8
70 39
IN
=P3V3S0_EN
G
S
1
1
P3V3S0_SS
2
4
2
5%
10%
1/16W
16V
MF-LF
X7R-CERM
402
0402
1.5V S3/S0 FET
CRITICAL
8
8
3.3V S0 GPU FET
=PPVIN_S3_P1V5S3RS0_FET
Q7870
=PP5V_S5_P1V5S3RS0FET
SIA427DJ
SC70-6L
=PP3V3_GPU_P3V3GPUFET
3.3V S0 GPU FET
MOSFET
U7801
P1V5CPU_EN
IN
2
TDFN
ON
D
3
5
G
7
S
SHDN*
1UF
RDS(ON)
1
P1V5S3RS0FET_GATE
2
4
10%
6.3V
X6S-CERM 2
0402
1/16W
MF-LF
4
2
G
1
2
3
LOADING
2
0.11A (EDP)
B
10%
1/16W
SSM3K15FV
XW7805
1
P3V3GPU_SS
2
5%
Q7872
8
26 mOhm @1.8V
0.01UF
1K
1
P-TYPE 8V/5V
RDS(ON)
C7870
R7870
P3V3GPU_EN_L
S
SiA427
CHANNEL
2
PWRPK-1212-8-HF
5%
1/16W
MF-LF
402
THRM
PAD
GND
402
5 A (EDP)
MOSFET
D
MF-LF
16V
402
3
X7R-CERM
0402
SOD-VESM-HF
SM
9
10V
X5R
6 mOhm @4.5V
LOADING
SI7108DN
1
0.33UF
402
0
6
PG
10%
C7871
1
5%
Q7801
R7801
P1V5S3RS0FET_GATE_R
NO STUFF
C7802 1
R7872
CRITICAL
D
CRITICAL
B
N-TYPE
51K
SLG5AP020
27
SI7108DN
CHANNEL
APN 376S0651
5
402
G
VCC
2
8 88
3
CERM
=PP3V3_S0GPU_FET
1
20%
10V
4
0.1UF
1
8
D
1.5V S3/S0 FET
7
1
S
C7801
PP1V5_S3RS0_FET
1
2
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.5V
P1V5S3RS0_RAMP_DONE
OUT
=PP1V5_S3RS0_FET_ISNS
8
88
NC_ISNS_P1V5R1V35_CPUDDRN
OUT
IN
=P3V3GPU_EN
1
G
S
7 98
NC_ISNS_P1V5R1V35_CPUDDRP
88
OUT
7 98
2
CRITICAL
Q7860
SI7615DN
5.0V S0 FET
PWRPK-1212-8
=PP5V_S0_FET
S
8
3.3V S0 GPU MISC FET
=PP5V_S4_P5VS0FET
C7861
220K
SC70-6L
=PP3V3_S0GPU_MISC_FET
7
=PP3V3_GPU_MISC_P3V3GPUMISCFET
1
8
1
D
S
4
402
R7880
P3V3GPU_MISC_EN_L
Q7882
1
P-TYPE 8V/5V
2
P3V3GPU_MISC_SS
1
2
RDS(ON)
SSM3K15FV
LOADING
402
Q7865
26 mOhm @1.8V
0.5A (EDP)
D
2
1
10%
16V
X7R-CERM
3
SOD-VESM-HF
SYNC_MASTER=D2_KEPLER
16V
402
SYNC_DATE=01/13/2012
PAGE TITLE
10%
MF-LF
Power FETs
X7R-CERM
0402
SOD-VESM-HF
P5V0S0_SS
0402
D
5%
1/16W
3
5 A (EDP)
20V/12V
0.01UF
2
1/16W
0.01UF
1K
SSM3K15FV
1
MF-LF
C7880
2
A
P5V0S0_EN_L
SiA427
3
1/16W
LOADING
C7860
R7860
5%
10%
6.3V
X6S-CERM 2
0402
MF-LF
MOSFET
CHANNEL
0.47UF
5%
5.5 MOHM @4.5V
2
402
2
10K
1
G
C7881
1
X5R
402
P-TYPE
RDS(ON)
16V
MF-LF
SI7615DN
CHANNEL
0.033UF
MOSFET
10%
3.3V S0 MISC GPU FET
51K
1
5%
1/16W
R7882
G
R7862
4
SIA427DJ
8
5.0V S0 FET
1
Q7880
5
2
8
D
3
CRITICAL
1
70
IN
G
S
DRAWING NUMBER
2
=P5VS0_EN
Apple Inc.
051-9589
R
88
IN
G
S
NOTICE OF PROPRIETARY PROPERTY:
2
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
D
4.18.0
=P3V3GPU_MISC_EN
1
SIZE
REVISION
BRANCH
PAGE
78 OF 132
SHEET
69 OF 99
1
A
5
4
3
2
S5 Rail Enables & PGOOD
State
SMC_ADAPTER_EN
SMC_PM_G2_ENABLE
SMC_S4_WAKESRC_EN
PM_SUS_EN
PM_SLP_S5_L
PM_SLP_S4_L
X
1
0
1
0
1
0
toggle 3Hz
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
0
0
0
0
1
1
1
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
Deep Sleep (dS4AC)
R7940
Deep Sleep (dS4)
100
42 41
SMC_PM_G2_EN
IN
1
2
P3V3S5_EN
=P3V3S5_EN
OUT
MAKE_BASE=TRUE
MAKE_BASE=TRUE
5%
1/16W
MF-LF
402
63
Deep Sleep (dS5AC)
Deep Sleep (dS5)
Battery Off (G3HotAC)
1
PLACE_NEAR=U7201.21:7mm
D
C7942
Battery Off (G3Hot)
2
8
=PP3V42_G3H_PWRCTL
PLACE_NEAR=U7300.16:6mm
1
C7970
6
20%
10V
CERM
402
41 18
IN
2
S5_PWRGD
4
R7975
OUT
MAKE_BASE=TRUE
OUT
OUT
OUT
=TBTBPWRSW_EN
0
2
OUT
CPUIMVP_VR_ON
OUT
42 41
10%
6.3V
2
CERM-X5R
402
10%
6.3V
2
402
10%
6.3V
CERM-X5R
402
C7975
10%
6.3V
CERM-X5R
PM_SLP_S3_R_L
IN
R7987
2
R7978
100 2
1
R7981
2
33K
5%
1/16W
MF-LF
402
1
5%
1/16W
MF-LF
402
R7985
2
5%
1/16W
MF-LF
402
1
PLACE_NEAR=U7100.15:6mm
R7988
20K
20K
1
PLACE_NEAR=U7600.3:6mm
39 69
=PBUSVSENS_EN
OUT
45
=TBT_S0_EN
5.1K
5%
1/16W
MF-LF
402
69
OUT
OUT
84 85
R7986
10K
5%
1/16W
MF-LF
402
OUT
=P3V3S0_EN
2
1
5%
1/16W
MF-LF
402
PLACE_NEAR=U7720.5:6mm
PLACE_NEAR=U7760.4:6mm
P1V8S0_EN
=P1V8S0_EN
OUT
68
MAKE_BASE=TRUE
U7940
CHGR VFRQ Generation
74AUP1G3208
SOT891
1
8
61
A
=PP3V42_G3H_CHGR
P1V5S0_EN
=P1V5S0_EN
OUT
68
=PCHVCCIOS0_EN
OUT
87
=CPUVCCIOS0_EN
OUT
67
=PVCCSA_EN
OUT
62
MAKE_BASE=TRUE
PCHVCCIOS0_EN
MAKE_BASE=TRUE
B
2
3
Y
45 PM_SUS_EN
OUT
69
=P3V3SUS_EN
C
OUT
69
5%
1/16W
MF-LF
402
2
SSM3K15FV
8
1%
1/16W
MF-LF
402
1%
1/16W
MF-LF
402
VMON_Q2_BASE
2
7
2
NC
70 8
5%
1/16W
MF-LF
402
SENSE
4
Sus_PGOOD_CT
TPS3808G33DBVRG4
SOT23-6
CT
MR*
8
=PP3V3_SUS_CNTRL
8 70
25 8
R7933
G
R7957
1
2
100
5%
1/16W
MF-LF
402
Thresholds:
VDD:
2.734V-3.010V
V2MON: 2.815V-3.099V
V3MON: 0.572V-0.630V
V4MON: 0.572V-0.630V
5%
1/16W
MF-LF
402
C7931
U7930 RESET*
1
R7950
1
PM_RSMRST_L
3
S0PGOOD_ISL
1
10K
2
1%
1/16W
MF-LF
402
R7972
20%
10V
X7R-CERM 2
0402
OUT
18
SUS_PGOOD_MR_L
CKPLUS_WAIVE=UNCONNECTED_PINS
8
70 41 24
IN
ALL_SYS_PWRGD
1
IN
CPUIMVP_PGOOD
2
2
1%
1/16W
MF-LF
402
65
S0PGOOD_ISL
1
6
1%
1/16W
MF-LF
402
R7971
S0PGOOD_ISL
1
R7973
1%
2
1/16W
MF-LF
402
15.0K
2
OMIT_TABLE
8
P1V05_VID_VMON
1
10K
1%
1/16W
MF-LF
402
IN
62
MR*
1
CRITICAL
GND
RST*
8
IN
PCHVCCIOS0_PGOOD
1
SMC_DELAYED_PWRGD
1
OUT
18 24 41
OUT
18
PM_PCH_PWROK
OUT
18 25
5%
1/16W
MF-LF
402
0
2
MAKE_BASE=TRUE
2
PART NUMBER
QTY
DESCRIPTION
REFERENCE DES
CRITICAL
5%
1/16W
MF-LF
402
BOM OPTION
1
RES,MTL FILM,1/16W,10K,1,0402,SMD,LF
R7971
PPDDR:1V5
1
RES,MTL FILM,1/16W,12.4K,1,0402,SMD,LF
R7971
PPDDR:1V35
PM_WLAN_EN_L
3
D
NC
2
S
2
Q7920
D 6
R7963
2
2
OUT
24 41 70
42 41 18
IN
SMC_ADAPTER_EN
G
Q7920
S 1
1
2
70 41 38 27 18 7
IN
PM_SLP_S3_L
G
Apple Inc.
S 4
5%
1/16W
MF-LF
402
4
3
051-9589
NOTICE OF PROPRIETARY PROPERTY:
2
SIZE
D
REVISION
R
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
5
SYNC_DATE=01/13/2012
Power Control 1/ENABLE
DRAWING NUMBER
5
ALL_SYS_PWRGD
6
19 24 34
PAGE TITLE
SOT563
5%
1/16W
MF-LF
402 2
R7962
353S2310
D 3
SSM6N15FEAPE
0
SOT563
100
IN
SYNC_MASTER=D2_KEPLER
NO STUFF
R79291
SSM6N15FEAPE
G 1
AP_PWR_EN
AC_EN_L
5%
1/16W
MF-LF
402
S0PGOOD_ISL
330
34
SSM3K15FV
SOD-VESM-HF
100
1
OUT
Q7925
" WLAN " = ( " S3 " & & " AP_PWR_EN " & & ( " AC " || " S0 " ))
NOTE: S3 term is guaranteed by S3 pull-up
on open-drain AP_PWR_EN signal.
5%
1/16W
MF-LF
402
ALL_SYS_PWRGD_R
7
PM_PCH_SYS_PWROK
2
CKPLUS_WAIVE=UNCONNECTED_PINS
2
PVCCSA_PGOOD
THRM_PAD
2
1K
PM_PCH_APWROK
1
4
R7964
5%
1/16W
MF-LF
402
(IPU)
SYS_PWROK_R
08
B
4
PLACE_NEAR=U1800.p12:7mm
5%
1/16W
MF-LF
402
R7969
87
TDFN
3 V2MON
5 V3MON
6 V4MON
4
15.0K
U7950 Y
08
3
B
R7949
A
2
1
ISL88042IRTEZ
P1V5_DIV_VMON
5
100
2
R7961
B
74LVC2G08GT
SOT833
8
PM_S0_PGOOD
U7950 Y 7
2
CPUVCCIOS0_PGOOD
U7960
P5V_DIV_VMON
74LVC2G08GT
SOT833
A
100
1
P5VS4_PGOOD
S0PGOOD_ISL
VDD
6.04K
9
R7970
IN
20%
10V
CERM
402
2
R7966
0.1UF
7
S0PGOOD_ISL
1
6.04K
1%
1/16W
MF-LF
402
=PP1V05_S0_VMON
67
2
R7960
70 8
0.1UF
2
114S0323
5%
1/16W
MF-LF
402
C7960 1
C7950
2
PM_RSMRST_L goes to U1800.C21
114S0315
1
=PP3V3_S0_VMON
S0PGOOD_ISL
S0PGOOD_ISL
1
1
1
1K
5%
1/16W
MF-LF
402
42 41 37
2
P1V8S0_PGOOD
=PP5V_S0_VMON
70 8
2
PCH S0 PWRGD
20%
50V
CERM
402
100
100
IN
402
R7968
1
P1V5S0_PGOOD
R7965
63
CERM-X5R
R7948
5%
1/16W
MF-LF
402
IN
10%
2 6.3V
X6S-CERM
0402
10%
6.3V
NO STUFF
P1V5S0_PGOOD from U7710
68
2
C7986
0.47UF
0.47UF
10%
6.3V
CERM-X5R
402
=PP3V3_S0_PWRCTL
S0 Rail PGOOD Circuitry
IN
2
CERM-X5R
402
=PP3V3_S5_PCHPWRGD
=PP3V3_S0_SB_PM
R7967 1
68
10%
6.3V
PLACE_NEAR=U7720.5:6mm
1
C7988
88 8
2
(ISL Version in development)
70 8
S
0.001UF
1
2
1
1UF
0.47UF
10%
6.3V
CERM-X5R
C7985
VFRQ Low: Fix Frequency
10K
=PP1V5_S3RS0_VMON
2
PLACE_NEAR=U7710.2:6mm
PLACE_NEAR=U7760.4:6mm
1
C7981
VFRQ High: Variable Frequency
100K
2
353S2809
S0PGD_BJT_GND_R
Worst-Case Thresholds:
Q2: 0.XXXV
Q3: 0.640V
3.3V w/Divider: 2.345V
Q4: 0.660V
8
0.47UF
3
GND
VMON_Q4_BASE
2
2
5%
1/16W
MF-LF
402
5
=PP3V3_SUS_CNTRL
Q4
3
1K
5%
1/20W
MF
2 201
1
VDD
R7955
1
=PP1V05_S0_VMON
20%
10V
CERM
402
CRITICAL
Q3
CRITICAL
1
70 8
D
PLACE_NEAR=U7600.3:6mm
1
C7987
C
0.1uF
U7930 Sense input
threhold is 3.07V
8
NC
VMON_Q3_BASE
2
5%
1/16W
MF-LF
402
B
ASMCC0179
DFN2015H4-8
1K
PP1V5_S3RS0
Q2
C7930
No stuff C7931, 12ms
Min delay time
6
Q1
R7954
1
Could stuff to satisfy
PCH power down timing t235
0
PLACE_NEAR=U7930.6:2.3mm
1
=PP1V5_S3RS0_VMON
1
R7930
=PP3V3_S5_PWRCTL
70 8
Q7950
5
1%
1/16W
MF-LF
402
70 8
1
5%
1/16W
MF-LF
402
R7952
PLACE_NEAR=U7100.15:6mm
61
402
NOSTUFF
7.15K
2
3.3V SUS Detect
4
1
OUT
SOD-VESM-HF
5%
1/16W
MF-LF
402
24 41 70
R7953
VMON_3V3_DIV
1
ALL_SYS_PWRGD
2
S0PGD_C
1K
MAKE_BASE=TRUE
R7917
0 2
1
150K
R7951
15.0K
2
NO STUFF
1
6
1
PVCCSA_EN
CHGR_VFRQ
=PP3V3_S0_VMON
R7956
MAKE_BASE=TRUE
Q7931
S0 Rail PGOOD (BJT Version)
=PP3V3_S5_VMON
CPUVCCIOS0_EN
100K
GND
70 8
R7931
=P5VSUS_EN
MAKE_BASE=TRUE
6
PM_SLP_SUS_L
IN
4
1
18
D
C7914
0.47UF
CERM-X5R
VCC
2
PM_SLP_SUS_L:100K pull down on PCH page
A
2
CERM-X5R
0.47UF
(PM_SLP_S3_R_L)
PM_SLP_S3_L:100K pull down in PCH page
5
SMC_BATLOW_L
IN
2
1
SMC_BATLOW_L:100K pull up on SMC page
C
10%
6.3V
C7913
=P5VS0_EN
PM_SLP_S3_L
20%
10V
CERM
402
65
1
85
=PP3V3_S5_PWRCTL
PLACE_NEAR=U7400.7:5mm
64
MAKE_BASE=TRUE
70 41 38 27 18 7
5%
1/16W
MF-LF
402
0.47UF
1
S0 ENABLE
PLACE_NEAR=U7940.1:2.3mm
1
C7912
1
402
3.3V/5.0V Sus ENABLE
ALL_SYS_PWRGD
1
NO STUFF
84
5%
1/16W
MF-LF
402
0.1uF
C7910
1
NO STUFF
0.47UF
R7915
0 2
1
C7940
63
OUT
2
69
=TBTAPWRSW_EN
R7974
=P5VS4_EN
NO STUFF
0.47UF
NOSTUFF
MAKE_BASE=TRUE
70 8
P5VS4_EN
3
SMC_S4_WAKESRC_EN
CPUVCORE ENABLE
2
49
=P3V3S4_EN
IN
69
OUT
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NO STUFF
=P5VS4_TPAD_EN
5
42 41
69
OUT
=DDRREG_EN
P5V3V3_S4_EN
NC
70 41 24
0
MAKE_BASE=TRUE
NC
SMC-- & gt; PM_DSW_PWRGD
41
49
OUT
=P3V3S3_EN
DDRREG_EN
402
1
P3V3S5_PGOOD
OUT
=P5VS3_EN
SOT891
S5_PWRGD (old name RSMRST_PWRGD)-- & gt; SMC
63
TPAD_VBUS_EN
74LVC1G32
2
PM_SLP_S5_L
2
PLACE_NEAR=Q7842.2:6MM
MAKE_BASE=TRUE
U7970
PM_SLP_S5_L:100K pull down on PCH page
0.1uF
100K
5%
1/16W
MF-LF
402
1
PLACE_NEAR=Q7812.2:6mm
5%
1/20W
MF
201
P3V3S3_EN
5%
1/20W
MF
201
PLACE_NEAR=U7940.1:2.3mm
R7941
5%
1/16W
MF-LF
402
1
P5VS3_EN
NO STUFF
PLACE_NEAR=U7201.20:7mm
R7914
3.3K
MAKE_BASE=TRUE
3.3V S4 ENABLE
=PP3V3_S5_PWRCTL
R7913
2
5%
1/16W
MF-LF
402
1
402
1
70 8
R7912
2
5%
1/16W
MF-LF
1
0.0033UF
10%
50V
X7R-CERM
0402
R7911
5.1K
2
PLACE_NEAR=U5701.4:6MM
2
PM_SLP_S4_L:100K pull down in PCH page
1
=P5VS5_EN
OUT
PM_SLP_S4_L
IN
0
Sleep (S3)
63
41 40 38 34 27 18 7
PM_SLP_S3_L
Run (S0)
Sleep (S3AC)
1
5V, 3.3V, DDR S3 ENABLE
Mobile System Power State Table
2
6
1
7
0
8
4.18.0
BRANCH
PAGE
79 OF 132
SHEET
70 OF 99
1
A
8
7
6
5
4
3
2
1
OMIT_TABLE
Page Notes
U8000
Power aliases required by this page:
NV-GK107
- =PP3V3_GPU_VDD33
BGA
(1 OF 10)
89 88 71
89 88 71
PEG_R2D_P & lt; 0 & gt;
PEG_R2D_N & lt; 0 & gt;
AN12
AM12
PEX_RX0
PEX_RX0*
PEX_TX0 AK14
PEX_TX0* AJ14
PEG_D2R_C_P & lt; 0 & gt;
PEG_D2R_C_N & lt; 0 & gt;
PEG_R2D_P & lt; 1 & gt;
PEG_R2D_N & lt; 1 & gt;
AN14
AM14
PEX_RX1
PEX_RX1*
PEX_TX1 AH14
PEX_TX1* AG14
PEG_D2R_C_P & lt; 1 & gt;
PEG_D2R_C_N & lt; 1 & gt;
PEG_R2D_P & lt; 2 & gt;
PEG_R2D_N & lt; 2 & gt;
AP14
AP15
PEX_RX2
PEX_RX2*
PEX_TX2 AK15
PEX_TX2* AJ15
PEG_D2R_C_P & lt; 2 & gt;
PEG_D2R_C_N & lt; 2 & gt;
PEG_R2D_P & lt; 3 & gt;
PEG_R2D_N & lt; 3 & gt;
AN15
AM15
PEX_RX3
PEX_RX3*
PEX_TX3 AL16
PEX_TX3* AK16
PEG_D2R_C_P & lt; 3 & gt;
PEG_D2R_C_N & lt; 3 & gt;
PEG_R2D_P & lt; 4 & gt;
PEG_R2D_N & lt; 4 & gt;
AN17
PEX_RX4
PEX_RX4*
PEX_TX4 AK17
PEX_TX4* AJ17
PEG_D2R_C_P & lt; 4 & gt;
PEG_D2R_C_N & lt; 4 & gt;
PEG_R2D_P & lt; 5 & gt;
PEG_R2D_N & lt; 5 & gt;
AP17
PEX_RX5
PEX_RX5*
PEX_TX5 AH17
PEX_TX5* AG17
PEG_D2R_C_P & lt; 5 & gt;
PEG_D2R_C_N & lt; 5 & gt;
PEG_R2D_P & lt; 6 & gt;
PEG_R2D_N & lt; 6 & gt;
AN18
PEX_RX6
PEX_RX6*
PEX_TX6 AK18
PEX_TX6* AJ18
PEG_D2R_C_P & lt; 6 & gt;
PEG_D2R_C_N & lt; 6 & gt;
PEG_R2D_P & lt; 7 & gt;
PEG_R2D_N & lt; 7 & gt;
AN20
AM20
PEX_RX7
PEX_RX7*
PEX_TX7 AL19
PEX_TX7* AK19
PEG_D2R_C_P & lt; 7 & gt;
PEG_D2R_C_N & lt; 7 & gt;
AP20
AP21
PEX_RX8
PEX_RX8*
PEX_TX8 AK20
PEX_TX8* AJ20
NC
NC
AN21
AM21
PEX_RX9
PEX_RX9*
PEX_TX9 AH20
PEX_TX9* AG20
NC
NC
71 89
71 89
Signal aliases required by this page:
(NONE)
BOM options provided by this page:
89 71
(NONE)
89 71
71 89
71 89
D
D
IN
PEG_R2D_C_P & lt; 0 & gt;
89 9
IN
PEG_R2D_C_N & lt; 0 & gt;
89 9
IN
PEG_R2D_C_P & lt; 1 & gt;
89 9
PEG_R2D_C_N & lt; 1 & gt;
IN
PEG_R2D_C_P & lt; 2 & gt;
IN
PEG_R2D_C_N & lt; 2 & gt;
89 9
IN
PEG_R2D_C_P & lt; 3 & gt;
PEG_R2D_C_N & lt; 3 & gt;
89 9
IN
PEG_R2D_C_P & lt; 4 & gt;
IN
PEG_R2D_C_N & lt; 4 & gt;
IN
PEG_R2D_C_P & lt; 5 & gt;
1
PEG_R2D_N & lt; 0 & gt;
2
IN
PEG_R2D_C_P & lt; 6 & gt;
C8024
0.22UF
1
C8025
0.22UF
C8026
0.22UF
C8027
0.22UF
C8028
0.22UF
C8029
0.22UF
C8030
0.22UF
PEG_R2D_C_P & lt; 7 & gt;
2
1
89 71
PEG_R2D_P & lt; 2 & gt;
2
71 89
89 71
PEG_R2D_N & lt; 2 & gt;
2
89 88 71
PEG_R2D_P & lt; 3 & gt;
71 88 89
20% 6.3V X6S-CERM 0201
1
2
89 88 71
PEG_R2D_N & lt; 3 & gt;
2
89 71
PEG_R2D_P & lt; 4 & gt;
71 89
20% 6.3V X6S-CERM 0201
1
2
89 71
PEG_R2D_N & lt; 4 & gt;
2
89 88 71
PEG_R2D_P & lt; 5 & gt;
0.22UF 1
GND_VOID=TRUE
71 88 89
20% 6.3V X6S-CERM 0201
20% 6.3V X6S-CERM 0201
C8031
C8032
0.22UF
1
2
89 88 71
PEG_R2D_N & lt; 5 & gt;
2
PEG_R2D_P & lt; 6 & gt;
0.22UF 1
GND_VOID=TRUE
0.22UF
1
2
PEG_R2D_N & lt; 6 & gt;
2
0.22UF 1
GND_VOID=TRUE
PEG_R2D_P & lt; 7 & gt;
2
71 89
71 89
71 89
AM18
71 89
71 89
71 89
C
71 89
NC
NC
71 89
NC
NC
71 88 89
20% 6.3V X6S-CERM 0201
C8035
AP18
71 89
20% 6.3V X6S-CERM 0201
C8034
71 89
71 88 89
20% 6.3V X6S-CERM 0201
C8033
AM17
71 89
20% 6.3V X6S-CERM 0201
1
71 89
71 88 89
20% 6.3V X6S-CERM 0201
1
71 89
71 89
20% 6.3V X6S-CERM 0201
1
71 89
71 89
20% 6.3V X6S-CERM 0201
GND_VOID=TRUE
PEG_R2D_C_N & lt; 7 & gt;
89 88 71
PEG_R2D_N & lt; 1 & gt;
GND_VOID=TRUE
PEG_R2D_C_N & lt; 6 & gt;
89 88 71
71 89
20% 6.3V X6S-CERM 0201
2
71 89
71 88 89
PEG_R2D_P & lt; 1 & gt;
GND_VOID=TRUE
89 9
89 71
20% 6.3V X6S-CERM 0201
GND_VOID=TRUE
PEG_R2D_C_N & lt; 5 & gt;
IN
2
0.22UF 1
GND_VOID=TRUE
GND_VOID=TRUE
IN
89 9
0.22UF
C8023
GND_VOID=TRUE
89 9
IN
C8022
71 88 89
20% 6.3V X6S-CERM 0201
GND_VOID=TRUE
IN
89 9
1
GND_VOID=TRUE
89 9
IN
0.22UF
89 71
PEG_R2D_P & lt; 0 & gt;
20% 6.3V X6S-CERM 0201
GND_VOID=TRUE
89 9
89 9
C8021
2
GND_VOID=TRUE
89 9
C
1
GND_VOID=TRUE
IN
89 9
0.22UF
GND_VOID=TRUE
89 9
89 9
C8020
PEG_R2D_N & lt; 7 & gt;
=PP3V3_GPU_VDD33
79 78 77 8
71 88 89
20% 6.3V X6S-CERM 0201
NC
NC
AN23
AM23
PEX_RX10
PEX_RX10*
1
PEX_TX10 AK21
PEX_TX10* AJ21
R8001
NC
NC
10K
1%
1/20W
MF
2 201
NC
NC
NC
NC
NC
NC
B
89 71
89 71
PEG_D2R_C_P & lt; 0 & gt;
PEG_D2R_C_N & lt; 0 & gt;
C8055 0.22UF 1
GND_VOID=TRUE
C8056 0.22UF 1
PEG_D2R_C_P & lt; 1 & gt;
89 71
PEG_D2R_C_N & lt; 1 & gt;
C8057
0.22UF
PEG_D2R_P & lt; 0 & gt;
2
PEG_D2R_N & lt; 0 & gt;
20% 6.3V X6S-CERM 0201
GND_VOID=TRUE
89 71
2
20% 6.3V X6S-CERM 0201
1
2
PEG_D2R_P & lt; 1 & gt;
20% 6.3V X6S-CERM 0201
GND_VOID=TRUE
0.22UF 1
GND_VOID=TRUE
C8058
2
PEG_D2R_N & lt; 1 & gt;
20% 6.3V X6S-CERM 0201
OUT
9 88 89
OUT
9 89
AN24
AM24
AN26
AM26
PEX_CLKREQ_L_R
PEX_RX11
PEX_RX11*
PEX_TX11 AL22
PEX_TX11* AK22
NC
NC
PEX_RX12
PEX_RX12*
PEX_TX12 AK23
PEX_TX12* AJ23
NC
NC
PEX_RX13
PEX_RX13*
PEX_TX13 AH23
PEX_TX13* AG23
NC
NC
PEX_RX14
PEX_RX14*
PEX_TX14 AK24
PEX_TX14* AJ24
NC
NC
PEX_RX15
PEX_RX15*
PEX_TX15 AL25
PEX_TX15* AK25
NC
NC
78 71
B
9 89
OUT
AP24
9 88 89
OUT
AP23
NC
NC
NC
NC
AP26
AP27
AN27
AM27
NOSTUFF
R8002
1
89 71
89 71
89 71
PEG_D2R_C_P & lt; 2 & gt;
PEG_D2R_C_N & lt; 2 & gt;
PEG_D2R_C_P & lt; 3 & gt;
0.22UF 1
GND_VOID=TRUE
C8060 0.22UF 1
GND_VOID=TRUE
C8059
C8061
0.22UF
PEG_D2R_C_N & lt; 3 & gt;
89 71
PEG_D2R_C_P & lt; 4 & gt;
0.22UF 1
GND_VOID=TRUE
0.22UF
1
A
PEG_D2R_C_N & lt; 4 & gt;
89 71
PEG_D2R_C_P & lt; 5 & gt;
C8064
0.22UF
0.22UF
89 71
89 71
89 71
C8066
0.22UF
1
C8067
0.22UF
PEG_D2R_C_N & lt; 6 & gt;
0.22UF
PEG_D2R_C_P & lt; 7 & gt;
89 71
PEG_D2R_C_N & lt; 7 & gt;
C8069
0.22UF
1
0.22UF
GND_VOID=TRUE
8
PEG_D2R_N & lt; 3 & gt;
20% 6.3V X6S-CERM 0201
OUT
9 89
IN
92 17
9 89
IN
78 9
IN
1
0
GPU_RESET_R_L
2
MF 5% 1/20W
78 71
OUT
9 89
OUT
PEG_D2R_P & lt; 4 & gt;
201
R8005
PEX_TERMP AP29
1
201
AK12
PEX_CLKREQ_L_R
9 89
OUT
PEX_RST*
PEX_TSTCLK_O_N
PEX_CLKREQ*
AJ11
PEX_WAKE*
GPU_PEX_TERMP
2.49K
2
1%
1/20W
MF
9 89
OUT
AJ12
95
92
2
1%
1/20W
MF
9 88 89
OUT
PEX_REFCLK
PEX_REFCLK*
PEX_TSTCLK_OUT AJ26
PEX_TSTCLK_OUT* AK26
9 88 89
OUT
OUT
AL13
AK13
200
R8000
9 89
NC
2
2
PEG_D2R_N & lt; 4 & gt;
2
PEG_D2R_P & lt; 5 & gt;
2
PEG_D2R_N & lt; 5 & gt;
2
PEG_D2R_P & lt; 6 & gt;
20% 6.3V X6S-CERM 0201
1
2
PEG_D2R_N & lt; 6 & gt;
20% 6.3V X6S-CERM 0201
PEX_SVDD_3V3 AG12
201
79
SYNC_DATE=01/13/2012
PAGE TITLE
KEPLER PCI-E
DRAWING NUMBER
Apple Inc.
OUT
9 89
2
PEG_D2R_P & lt; 7 & gt;
20% 6.3V X6S-CERM 0201
OUT
9 88 89
1
2
PEG_D2R_N & lt; 7 & gt;
20% 6.3V X6S-CERM 0201
OUT
9 88 89
7
051-9589
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
6
5
4
3
2
SIZE
D
REVISION
R
NOTICE OF PROPRIETARY PROPERTY:
1
GND_VOID=TRUE
C8070
OUT
PEG_CLK100M_P
PEG_CLK100M_N
PEX_TSTCLK_O_P
SYNC_MASTER=D2_KEPLER
GND_VOID=TRUE
89 71
2
20% 6.3V X6S-CERM 0201
GND_VOID=TRUE
C8068
PEG_D2R_P & lt; 3 & gt;
20% 6.3V X6S-CERM 0201
1
GND_VOID=TRUE
PEG_D2R_C_P & lt; 6 & gt;
2
20% 6.3V X6S-CERM 0201
GND_VOID=TRUE
PEG_D2R_C_N & lt; 5 & gt;
95 92
9 89
PP3V3_GPU_PEX_PLL_HVDD
1
GND_VOID=TRUE
C8065
PEG_D2R_N & lt; 2 & gt;
20% 6.3V X6S-CERM 0201
GND_VOID=TRUE
89 71
OUT
92 17
2
20% 6.3V X6S-CERM 0201
20% 6.3V X6S-CERM 0201
C8062
C8063
PEG_D2R_P & lt; 2 & gt;
20% 6.3V X6S-CERM 0201
GPU_RESET_L
1
GND_VOID=TRUE
89 71
2
4.18.0
BRANCH
PAGE
80 OF 132
SHEET
71 OF 99
1
A
8
7
6
5
4
3
2
1
Page Notes
OMIT_TABLE
Power aliases required by this page:
U8000
=PPVCORE_GPU
NV-GK107
79 72 8
- =PPVCORE_GPU
- =PP1V35_GPU_FBVDDQ
=PPVCORE_GPU
8 72 79
BGA
(10 OF 10)
AA12
AA14
AA16
AA19
AA21
AA23
AB13
AB15
AB17
AB18
AB20
AB22
AC12
AC14
AC16
AC19
AC21
AC23
M12
M14
M16
M19
M21
M23
N13
N15
N17
N18
N20
N22
P12
P14
P16
P19
P21
P23
R13
R15
R17
R18
R20
R22
T12
T14
T16
T19
T21
T23
U13
U15
U17
U18
U20
U22
V13
V15
OMIT_TABLE
U8000
=PP1V35_GPU_FBVDDQ
=PP1V35_GPU_FBVDDQ
NV-GK107
76 75 72 8
8 72 75 76
BGA
(7 OF 10)
D
AA27
AA30
AB27
AB33
AC27
AD27
AE27
AF27
AG27
B13
B16
B19
E13
E16
E19
H10
H11
H12
H13
H14
H15
H16
FBVDDQ
FBVDDQ
H18
H19
H20
H21
H22
H23
H24
H8
H9
L27
M27
N27
P27
R27
T27
T30
T33
V27
W27
W30
W33
Y27
C
VDD
VDD
XVDD
V17
V18
V20
V22
W12
W14
W16
W19
W21
W23
Y13
Y15
Y17
Y18
Y20
Y22
U1
U2
U3
U4
U5
U6
U7
U8
V1
V2
V3
V4
V5
V6
V7
V8
W2
W3
W4
W5
W7
W8
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
Signal aliases required by this page:
(NONE)
D
BOM options provided by this page:
(NONE)
=PPVCORE_GPU
79 72 8
EDP = 30 A
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NOSTUFF
CRITICAL
NOSTUFF
1
C8161
1
47UF
20%
2 4V
X6S
0805
C8145
20UF
20%
2V
2 X6T-CERM
0402
1
C8168
10UF
20%
4V
2 X6S-CERM
0402-1
1
22UF
20%
2 4V
X6S-CERM
0603
CRITICAL
1
C8198
NOSTUFF
CRITICAL
C8146
20UF
20%
2V
2 X6T-CERM
0402
1
C8169
10UF
20%
4V
2 X6S-CERM
0402-1
CRITICAL
1
22UF
20%
2 4V
X6S-CERM
0603
CRITICAL
1
C8199
C8147
20UF
20%
2V
2 X6T-CERM
0402
1
C8170
10UF
20%
4V
2 X6S-CERM
0402-1
CRITICAL
1
20UF
20%
2 2V
X6T-CERM
0402
CRITICAL
1
C8162
C8148
20UF
20%
2V
2 X6T-CERM
0402
1
C8171
10UF
20%
4V
2 X6S-CERM
0402-1
CRITICAL
1
20UF
20%
2 2V
X6T-CERM
0402
1
C8149
20UF
20%
2V
2 X6T-CERM
0402
1
C8172
10UF
20%
4V
2 X6S-CERM
0402-1
C8164
C8150
20UF
20%
2V
2 X6T-CERM
0402
1
C8173
10UF
20%
4V
2 X6S-CERM
0402-1
C8165
1
20UF
20%
2 2V
X6T-CERM
0402
NOSTUFF
CRITICAL
1
NOSTUFF
CRITICAL
CRITICAL
1
20UF
20%
2 2V
X6T-CERM
0402
NOSTUFF
CRITICAL
CRITICAL
1
C8163
C8178
1
10UF
20%
2 4V
X6S-CERM
0402-1
B
C8179
1
10UF
C8180
1
10UF
C8181
1
10UF
C8184
1
10UF
C8185
20%
2 4V
X6S-CERM
0402-1
20%
2 4V
X6S-CERM
0402-1
20%
2 4V
X6S-CERM
0402-1
20%
2 4V
X6S-CERM
0402-1
1
1
1
1
1
C8183
1
20UF
20%
2 2V
X6T-CERM
0402
C8166
10UF
20%
2 4V
X6S-CERM
0402-1
1
C8167
10UF
20%
2 4V
X6S-CERM
0402-1
NOSTUFF
CRITICAL
1
C8151
20UF
20%
2V
2 X6T-CERM
0402
1
C8174
10UF
20%
4V
2 X6S-CERM
0402-1
1
10UF
20%
2 4V
X6S-CERM
0402-1
NOSTUFF
CRITICAL
1
20UF
20%
2 2V
X6T-CERM
0402
C
1
C8186
C8175
10UF
20%
4V
2 X6S-CERM
0402-1
CRITICAL
1
C8182
1
10UF
20%
4V
2 X6S-CERM
0402-1
CRITICAL
1
C8187
C8176
1
10UF
20%
4V
2 X6S-CERM
0402-1
CRITICAL
1
CRITICAL
1
C8188
1UF
1UF
1UF
2
20%
4V
CERM-X6S
0201
2
20%
4V
CERM-X6S
0201
20%
4V
CERM-X6S
0201
1
C8196
1
2
C8177
C8189
1UF
20%
2 4V
CERM-X6S
0201
B
CRITICAL
1
C8190
1UF
2
=PP1V35_GPU_FBVDDQ
GPU FB DE-COUPLING
20%
4V
CERM-X6S
0201
C8191
0.1UF
2
10%
6.3V
X6S
0201
C8192
0.1UF
2
10%
6.3V
X6S
0201
C8193
0.1UF
2
C8194
0.1UF
10%
6.3V
X6S
0201
2
10%
6.3V
X6S
0201
C8195
0.1UF
2
10%
6.3V
X6S
0201
1000PF
2
10%
16V
X7R-CERM
0201
C8197
1000PF
2
10%
16V
X7R-CERM
0201
76 75 72 8
EDP = 6500 MA
1
C8125
1
C8126
1
C8127
1
C8128
1
C8101
1
1
C8102
C8103
20UF
2
20UF
20UF
20UF
10UF
10UF
20%
2V
X6T-CERM
0402
20%
2V
X6T-CERM
0402
20%
2V
X6T-CERM
0402
20%
4V
X6S-CERM
0402-1
20%
4V
X6S-CERM
0402-1
20%
4V
X6S-CERM
0402-1
1
10UF
20%
2V
X6T-CERM
0402
2
2
2
2
2
2
C8104
GPU VCORE DE-COUPLING
10UF
2
20%
4V
X6S-CERM
0402-1
NOTE: ATLEAST 2 GND VIAS & 2 POWER VIAS PER CAP
1
C8105
1
4.7UF
2
20%
6.3V
X6S
0402
C8106
1
4.7UF
2
20%
6.3V
X6S
0402
C8107
1
4.7UF
2
20%
6.3V
X6S
0402
C8108
1
4.7UF
2
20%
6.3V
X6S
0402
C8109
1
4.7UF
2
20%
6.3V
X6S
0402
C8110
1
4.7UF
2
20%
6.3V
X6S
0402
C8111
1
1UF
1
C8112
1UF
2
20%
4V
CERM-X6S
0201
2
1
C8123
1
C8113
1
1UF
20%
4V
CERM-X6S
0201
2
20%
4V
CERM-X6S
0201
C8114
1UF
2
20%
4V
CERM-X6S
0201
A
SYNC_MASTER=D2_SEAN
1
C8115
1
0.1UF
2
10%
6.3V
X6S
0201
C8118
1
0.1UF
2
10%
6.3V
X6S
0201
C8119
1
0.1UF
2
10%
6.3V
X6S
0201
C8120
1
0.1UF
2
10%
6.3V
X6S
0201
C8121
1
0.1UF
2
10%
6.3V
X6S
0201
C8122
0.1UF
2
10%
6.3V
X6S
0201
0.1UF
2
10%
6.3V
X6S
0201
KEPLER CORE/FB POWER
0.1UF
2
SYNC_DATE=03/05/2012
PAGE TITLE
C8124
10%
6.3V
X6S
0201
DRAWING NUMBER
Apple Inc.
051-9589
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
4.18.0
BRANCH
PAGE
81 OF 132
SHEET
72 OF 99
1
A
8
7
6
5
4
3
2
1
Page Notes
NOTE:GDDR5 MODE H MAPPING
FB_A0_RESET_L
95 75 73
FB_A1_RESET_L
95 75 73
Power aliases required by this page:
- =PP1V35_GPU_S0_FB
- =PP1V05_GPU_PEX_IOVDD
OMIT_TABLE
1
BI
95 75
D
BI
95 75
BI
95 75
BI
95 75
BI
95 75
BI
95 75
BI
95 75
BI
95 75
BI
95 75
BI
95 75
BI
95 75
BI
95 75
BI
95 75
BI
95 75
BI
95 75
BI
95 75
BI
95 75
BI
95 75
BI
95 75
BI
95 75
BI
95 75
BI
95 75
BI
95 75
BI
95 75
BI
95 75
BI
95 75
BI
95 75
C
BI
95 75
BI
95 75
95 75
BI
BI
95 75
BI
95 75
BI
95 75
BI
95 75
BI
95 75
BI
95 75
BI
95 75
BI
95 75
95 75
BI
BI
95 75
BI
95 75
BI
95 75
BI
95 75
BI
95 75
BI
95 75
95 75
BI
BI
95 75
BI
95 75
BI
95 75
BI
95 75
BI
95 75
BI
95 75
BI
95 75
BI
95 75
BI
95 75
BI
95 75
B
BI
95 75
BI
95 75
BI
95 75
BI
95 75
BI
95 75
BI
95 75
BI
95 75
BI
95 75
OUT
95 75
OUT
95 75
OUT
95 75
OUT
95 75
OUT
95 75
OUT
95 75
OUT
95 75
OUT
L28
M29
FB_A0_DQ & lt; 0 & gt;
FB_A0_DQ & lt; 1 & gt;
FB_A0_DQ & lt; 2 & gt;
FB_A0_DQ & lt; 3 & gt;
FB_A0_DQ & lt; 4 & gt;
FB_A0_DQ & lt; 5 & gt;
FB_A0_DQ & lt; 6 & gt;
FB_A0_DQ & lt; 7 & gt;
FB_A0_DQ & lt; 8 & gt;
FB_A0_DQ & lt; 9 & gt;
FB_A0_DQ & lt; 10 & gt;
FB_A0_DQ & lt; 11 & gt;
FB_A0_DQ & lt; 12 & gt;
FB_A0_DQ & lt; 13 & gt;
FB_A0_DQ & lt; 14 & gt;
FB_A0_DQ & lt; 15 & gt;
FB_A0_DQ & lt; 16 & gt;
FB_A0_DQ & lt; 17 & gt;
FB_A0_DQ & lt; 18 & gt;
FB_A0_DQ & lt; 19 & gt;
FB_A0_DQ & lt; 20 & gt;
FB_A0_DQ & lt; 21 & gt;
FB_A0_DQ & lt; 22 & gt;
FB_A0_DQ & lt; 23 & gt;
FB_A0_DQ & lt; 24 & gt;
FB_A0_DQ & lt; 25 & gt;
FB_A0_DQ & lt; 26 & gt;
FB_A0_DQ & lt; 27 & gt;
FB_A0_DQ & lt; 28 & gt;
FB_A0_DQ & lt; 29 & gt;
FB_A0_DQ & lt; 30 & gt;
FB_A0_DQ & lt; 31 & gt;
FB_A1_DQ & lt; 0 & gt;
FB_A1_DQ & lt; 1 & gt;
FB_A1_DQ & lt; 2 & gt;
FB_A1_DQ & lt; 3 & gt;
FB_A1_DQ & lt; 4 & gt;
FB_A1_DQ & lt; 5 & gt;
FB_A1_DQ & lt; 6 & gt;
FB_A1_DQ & lt; 7 & gt;
FB_A1_DQ & lt; 8 & gt;
FB_A1_DQ & lt; 9 & gt;
FB_A1_DQ & lt; 10 & gt;
FB_A1_DQ & lt; 11 & gt;
FB_A1_DQ & lt; 12 & gt;
FB_A1_DQ & lt; 13 & gt;
FB_A1_DQ & lt; 14 & gt;
FB_A1_DQ & lt; 15 & gt;
FB_A1_DQ & lt; 16 & gt;
FB_A1_DQ & lt; 17 & gt;
FB_A1_DQ & lt; 18 & gt;
FB_A1_DQ & lt; 19 & gt;
FB_A1_DQ & lt; 20 & gt;
FB_A1_DQ & lt; 21 & gt;
FB_A1_DQ & lt; 22 & gt;
FB_A1_DQ & lt; 23 & gt;
FB_A1_DQ & lt; 24 & gt;
FB_A1_DQ & lt; 25 & gt;
FB_A1_DQ & lt; 26 & gt;
FB_A1_DQ & lt; 27 & gt;
FB_A1_DQ & lt; 28 & gt;
FB_A1_DQ & lt; 29 & gt;
FB_A1_DQ & lt; 30 & gt;
FB_A1_DQ & lt; 31 & gt;
L29
M28
N31
P29
R29
P28
J28
H29
J29
H28
G29
E31
E32
F30
C34
D32
B33
C33
F33
F32
H33
H32
P34
P32
P31
P33
L31
L34
L32
L33
AG28
AF29
AG29
AF28
AD30
AD29
AC29
AD28
AJ29
AK29
AJ30
AK28
AM29
AM31
AN29
AM30
AN31
AN32
AP30
AP32
AM33
AL31
AK33
AK32
AD34
AD32
AC30
AD33
AF31
AG34
AG32
AG33
K31
FB_A0_WCLK_P & lt; 0 & gt;
FB_A0_WCLK_N & lt; 0 & gt;
L30
H34
FB_A0_WCLK_P & lt; 1 & gt;
FB_A0_WCLK_N & lt; 1 & gt;
J34
FB_A1_WCLK_P & lt; 0 & gt;
FB_A1_WCLK_N & lt; 0 & gt;
AG30
FB_A1_WCLK_P & lt; 1 & gt;
FB_A1_WCLK_N & lt; 1 & gt;
AJ34
AK34
AG31
(3 OF 10)
MEM INTERFACE A
FBA_D0
FBA_CMD0 U30
FBA_D1
FBA_CMD1 T31
FBA_D2
FBA_CMD2 U29
FBA_D3
FBA_CMD3 R34
FBA_CMD4 R33
FBA_D4
FBA_D5
FBA_CMD5 U32
FBA_CMD6 U33
FBA_D6
FBA_D7
FBA_CMD7 U28
FBA_CMD8 V28
FBA_D8
FBA_D9
FBA_CMD9 V29
FBA_D10
FBA_CMD10 V30
FBA_CMD11 U34
FBA_D11
FBA_CMD12 U31
FBA_D12
FBA_D13
FBA_CMD13 V34
FBA_CMD14 V33
FBA_D14
FBA_CMD15 Y32
FBA_D15
FBA_CMD16 AA31
FBA_D16
FBA_CMD17 AA29
FBA_D17
FBA_CMD18 AA28
FBA_D18
FBA_CMD19 AC34
FBA_D19
FBA_CMD20 AC33
FBA_D20
FBA_CMD21 AA32
FBA_D21
FBA_CMD22 AA33
FBA_D22
FBA_CMD23 Y28
FBA_D23
FBA_CMD24 Y29
FBA_D24
FBA_CMD25 W31
FBA_D25
FBA_CMD26 Y30
FBA_D26
FBA_CMD27 AA34
FBA_D27
FBA_CMD28 Y31
FBA_D28
FBA_CMD29 Y34
FBA_D29
FBA_CMD30 Y33
FBA_D30
FBA_CMD31 V31
FBA_D31
FBA_D32
FBA_CLK0 R30
FBA_D33
FBA_CLK0* R31
FBA_D34
FBA_CLK1 AB31
FBA_D35
FBA_CLK1* AC31
FBA_D36
FBA_D37
FBA_DQM0 P30
FBA_D38
FBA_DQM1 F31
FBA_D39
FBA_DQM2 F34
FBA_D40
FBA_DQM3 M32
FBA_D41
FBA_DQM4 AD31
FBA_D42
FBA_DQM5 AL29
FBA_D43
FBA_DQM6 AM32
FBA_D44
FBA_DQM7 AF34
FBA_D45
FBA_D46
FBA_DQS_RN0 M30
FBA_D47
FBA_DQS_RN1 H30
FBA_D48
FBA_DQS_RN2 E34
FBA_D49
FBA_DQS_RN3 M34
FBA_D50
FBA_DQS_RN4 AF30
FBA_D51
FBA_DQS_RN5 AK31
FBA_D52
FBA_DQS_RN6 AM34
FBA_D53
FBA_DQS_RN7 AF32
FBA_D54
FBA_D55
FBA_DQS_WP0 M31
FBA_D56
FBA_DQS_WP1 G31
FBA_D57
FBA_DQS_WP2 E33
FBA_D58
FBA_DQS_WP3 M33
FBA_D59
FBA_DQS_WP4 AE31
FBA_D60
FBA_DQS_WP5 AK30
FBA_D61
FBA_DQS_WP6 AN33
FBA_D62
FBA_DQS_WP7 AF33
FBA_D63
FB_DLL_AVDD K27
FBA_WCK01
FBA_PLL_AVDD U27
FBA_WCK01*
FBA_DEBUG R28
FBA_WCK23
FBA_DEBUG AC28
FBA_WCK23*
FB_CAL_PD_VDDQ J27
FBA_WCK45
FB_CAL_PU_GND H27
FBA_WCK45*
FB_CAL_TERM_GND H25
FBA_WCK67
FB_CLAMP E1 82
FBA_WCK67*
J30
NC
NC
NC
NC
NC
NC
A
NC
NC
J31
FBA_WCKB01
FBA_WCKB01*
J32
J33
FBA_WCKB23
FBA_WCKB23*
AH31
FBA_CMD_RFU R32
FBA_CMD_RFU AC32
2
FB_A0_CS_L
FB_A0_A & lt; 3 & gt;
FB_A0_A & lt; 2 & gt;
FB_A0_A & lt; 4 & gt;
FB_A0_A & lt; 5 & gt;
FB_A0_WE_L
FB_A0_A & lt; 7 & gt;
FB_A0_A & lt; 6 & gt;
FB_A0_ABI_L
FB_A0_A & lt; 8 & gt;
FB_A0_A & lt; 0 & gt;
FB_A0_A & lt; 1 & gt;
FB_A0_RAS_L
FB_A0_RESET_L
FB_A0_CKE_L
FB_A0_CAS_L
FB_A1_CS_L
FB_A1_A & lt; 3 & gt;
FB_A1_A & lt; 2 & gt;
FB_A1_A & lt; 4 & gt;
FB_A1_A & lt; 5 & gt;
FB_A1_WE_L
FB_A1_A & lt; 7 & gt;
FB_A1_A & lt; 6 & gt;
FB_A1_ABI_L
FB_A1_A & lt; 8 & gt;
FB_A1_A & lt; 0 & gt;
FB_A1_A & lt; 1 & gt;
FB_A1_RAS_L
FB_A1_RESET_L
FB_A1_CKE_L
FB_A1_CAS_L
AJ32
AJ33
FB_GND_SENSE F2
OUT
10K
OMIT_TABLE
1%
1/20W
MF
201
1%
1/20W
MF
201
U8000
2
NV-GK107
75 95
OUT
75 95
95 76
BI
OUT
75 95
95 76
BI
OUT
75 95
95 76
BI
75 95
OUT
FB_A0_CKE_L
75 95
FB_A1_CKE_L
73 75 95
73 75 95
75 95
OUT
OUT
1
2
10K
1%
1/20W
MF
201
1%
1/20W
MF
201
2
BI
95 76
BI
95 76
BI
75 95
95 76
BI
OUT
75 95
95 76
BI
OUT
73 75 95
95 76
BI
OUT
73 75 95
95 76
BI
OUT
75 95
95 76
BI
OUT
75 95
95 76
BI
OUT
75 95
95 76
BI
OUT
75 95
95 76
BI
OUT
75 95
OUT
75 95
OUT
75 95
OUT
75 95
OUT
75 95
OUT
75 95
OUT
75 95
OUT
75 95
OUT
75 95
OUT
75 95
OUT
73 75 95
OUT
OUT
OUT
95 76
R8258
1%
1/20W
MF
201
BI
95 76
PLACE_NEAR=U8000.H26:8.4MM
1.33K
BI
95 76
1 NOSTUFF
BI
95 76
8 73
BI
95 76
=PP1V35_GPU_S0_FB
BI
95 76
BI
95 76
BI
95 76
BI
95 76
BI
95 76
2
BI
C8260
95 76
BI
0.1UF
95 76
BI
PLACE_NEAR=U8000.H26:8.4MM
FB_VREF
NOSTUFF
1
1
1.33K
75 95
73
NOSTUFF
R8259
73 75 95
1%
1/20W
MF
201
10%
6.3V
X6S
0201
BI
BI
BI
95 76
OUT
BI
BI
75 95
75 95
2
95 76
95 76
75 95
OUT
2
95 76
95 76
OUT
OUT
PLACE_NEAR=U8000.H26:8.4MM
75 95
95 76
BI
75 95
BI
BI
95 76
FB_A0_DBI_L & lt; 0 & gt;
FB_A0_DBI_L & lt; 1 & gt;
FB_A0_DBI_L & lt; 2 & gt;
FB_A0_DBI_L & lt; 3 & gt;
FB_A1_DBI_L & lt; 0 & gt;
FB_A1_DBI_L & lt; 1 & gt;
FB_A1_DBI_L & lt; 2 & gt;
FB_A1_DBI_L & lt; 3 & gt;
BI
75 95
FB VREF GEN (TEST ONLY)
75 95
BI
75 95
BI
BI
75 95
BI
BI
95 76
BI
95 76
75 95
95 76
BI
95 76
BI
95 76
BI
95 76
95 76
BI
75 95
BI
BI
95 76
BI
BI
75 95
95 76
NC
NC
NC
NC
NC
NC
NC
NC
BI
95 76
BI
95 76
BI
95 76
BI
95 76
BI
95 76
BI
95 76
BI
95 76
BI
95 76
BI
75 95
75 95
8 73
75 95
IN
=PP1V35_GPU_S0_FB
75 95
IN
IN
1
R8203
60.4
75 95
IN
75 95
1%
1/20W
MF
2 201
73
1
R8202
95 76
60.4
1%
1/20W
MF
2 201
BI
95 76
BI
R8270
95 76
BI
100
95 76
BI
95 76
BI
1
5%
1/20W
MF
2 201
73
GPU_FBA_DEBUG0
GPU_FBA_DEBUG1
FB_CAL_PD_VDDQ 73
FB_CAL_PU_GND
73
FB_CAL_TERM_GND 1
BI
95 76
IN
PP1V05_GPU_FB_DLL_AVDD
PP1V05_GPU_FB_PLL_AVDD
BI
95 76
75 95
IN
BI
95 76
75 95
BI
95 76
IN
BI
95 76
IN
BI
95 76
FB_A0_EDC & lt; 0 & gt;
FB_A0_EDC & lt; 1 & gt;
FB_A0_EDC & lt; 2 & gt;
FB_A0_EDC & lt; 3 & gt;
FB_A1_EDC & lt; 0 & gt;
FB_A1_EDC & lt; 1 & gt;
FB_A1_EDC & lt; 2 & gt;
FB_A1_EDC & lt; 3 & gt;
95 76
OUT
95 76
OUT
95 76
R8201 PLACE_NEAR=U8000.H25:8.4MM
95 76
OUT
OUT
10K
MF 1%
95 76
OUT
95 76
1
G9
FB_B0_DQ & lt; 0 & gt;
FB_B0_DQ & lt; 1 & gt;
FB_B0_DQ & lt; 2 & gt;
FB_B0_DQ & lt; 3 & gt;
FB_B0_DQ & lt; 4 & gt;
FB_B0_DQ & lt; 5 & gt;
FB_B0_DQ & lt; 6 & gt;
FB_B0_DQ & lt; 7 & gt;
FB_B0_DQ & lt; 8 & gt;
FB_B0_DQ & lt; 9 & gt;
FB_B0_DQ & lt; 10 & gt;
FB_B0_DQ & lt; 11 & gt;
FB_B0_DQ & lt; 12 & gt;
FB_B0_DQ & lt; 13 & gt;
FB_B0_DQ & lt; 14 & gt;
FB_B0_DQ & lt; 15 & gt;
FB_B0_DQ & lt; 16 & gt;
FB_B0_DQ & lt; 17 & gt;
FB_B0_DQ & lt; 18 & gt;
FB_B0_DQ & lt; 19 & gt;
FB_B0_DQ & lt; 20 & gt;
FB_B0_DQ & lt; 21 & gt;
FB_B0_DQ & lt; 22 & gt;
FB_B0_DQ & lt; 23 & gt;
FB_B0_DQ & lt; 24 & gt;
FB_B0_DQ & lt; 25 & gt;
FB_B0_DQ & lt; 26 & gt;
FB_B0_DQ & lt; 27 & gt;
FB_B0_DQ & lt; 28 & gt;
FB_B0_DQ & lt; 29 & gt;
FB_B0_DQ & lt; 30 & gt;
FB_B0_DQ & lt; 31 & gt;
FB_B1_DQ & lt; 0 & gt;
FB_B1_DQ & lt; 1 & gt;
FB_B1_DQ & lt; 2 & gt;
FB_B1_DQ & lt; 3 & gt;
FB_B1_DQ & lt; 4 & gt;
FB_B1_DQ & lt; 5 & gt;
FB_B1_DQ & lt; 6 & gt;
FB_B1_DQ & lt; 7 & gt;
FB_B1_DQ & lt; 8 & gt;
FB_B1_DQ & lt; 9 & gt;
FB_B1_DQ & lt; 10 & gt;
FB_B1_DQ & lt; 11 & gt;
FB_B1_DQ & lt; 12 & gt;
FB_B1_DQ & lt; 13 & gt;
FB_B1_DQ & lt; 14 & gt;
FB_B1_DQ & lt; 15 & gt;
FB_B1_DQ & lt; 16 & gt;
FB_B1_DQ & lt; 17 & gt;
FB_B1_DQ & lt; 18 & gt;
FB_B1_DQ & lt; 19 & gt;
FB_B1_DQ & lt; 20 & gt;
FB_B1_DQ & lt; 21 & gt;
FB_B1_DQ & lt; 22 & gt;
FB_B1_DQ & lt; 23 & gt;
FB_B1_DQ & lt; 24 & gt;
FB_B1_DQ & lt; 25 & gt;
FB_B1_DQ & lt; 26 & gt;
FB_B1_DQ & lt; 27 & gt;
FB_B1_DQ & lt; 28 & gt;
FB_B1_DQ & lt; 29 & gt;
FB_B1_DQ & lt; 30 & gt;
FB_B1_DQ & lt; 31 & gt;
E9
G8
F9
F11
G11
F12
G12
G6
F5
E6
F6
F4
G4
E2
F3
C2
D4
D3
C1
B3
C4
B5
C5
A11
C11
D11
B11
D8
A8
C8
B8
F24
G23
E24
G24
D21
E21
G21
F21
G27
D27
G26
E27
E29
F29
E30
D30
A32
C31
C32
B32
D29
A29
C29
B29
B21
C23
A21
C21
B24
C24
B26
C26
FB_B0_WCLK_P & lt; 0 & gt;
FB_B0_WCLK_N & lt; 0 & gt;
F8
FB_B0_WCLK_P & lt; 1 & gt;
FB_B0_WCLK_N & lt; 1 & gt;
A5
A6
E8
2
60.4
FB_CLAMP
NC
NC
OUT
95 76
OUT
1% 1/20W MF 201
R8261
2
1/20W 201
95 76
GPU_FBVDDQ_SENSE
OUT
74 97
GPU_FBGND_SENSE
OUT
74 97
R8271
FB_CAL_PU_GND
100
=PP1V35_GPU_S0_FB
8 73
1
R8204
1
R8205
40.2
1%
1/20W
MF
201
D24
FB_B1_WCLK_P & lt; 1 & gt;
FB_B1_WCLK_N & lt; 1 & gt;
B27
D25
C27
NC
NC
5%
1/20W
MF
2 201
NC
NC
NC
NC
(NONE)
(4 OF 10)
MEM INTRERFACE B
FBB_D0
FBB_CMD0
FBB_CMD1
FBB_D1
FBB_D2
FBB_CMD2
FBB_D3
FBB_CMD3
FBB_CMD4
FBB_D4
FBB_CMD5
FBB_D5
FBB_CMD6
FBB_D6
FBB_CMD7
FBB_D7
FBB_CMD8
FBB_D8
FBB_CMD9
FBB_D9
FBB_CMD10
FBB_D10
FBB_D11
FBB_CMD11
FBB_CMD12
FBB_D12
FBB_CMD13
FBB_D13
FBB_CMD14
FBB_D14
FBB_D15
FBB_CMD15
FBB_CMD16
FBB_D16
FBB_D17
FBB_CMD17
FBB_D18
FBB_CMD18
FBB_D19
FBB_CMD19
FBB_D20
FBB_CMD20
FBB_D21
FBB_CMD21
FBB_D22
FBB_CMD22
FBB_D23
FBB_CMD23
FBB_D24
FBB_CMD24
FBB_D25
FBB_CMD25
FBB_D26
FBB_CMD26
FBB_D27
FBB_CMD27
FBB_D28
FBB_CMD28
FBB_D29
FBB_CMD29
FBB_D30
FBB_CMD30
FBB_D31
FBB_CMD31
FBB_D32
FBB_CLK0
FBB_D33
FBB_CLK0*
FBB_D34
FBB_CLK1
FBB_D35
FBB_CLK1*
FBB_D36
FBB_D37
FBB_DQM0
FBB_D38
FBB_DQM1
FBB_D39
FBB_DQM2
FBB_D40
FBB_DQM3
FBB_D41
FBB_DQM4
FBB_D42
FBB_DQM5
FBB_D43
FBB_DQM6
FBB_D44
FBB_DQM7
FBB_D45
FBB_D46
FBB_DQS_RN0
FBB_D47
FBB_DQS_RN1
FBB_D48
FBB_DQS_RN2
FBB_D49
FBB_DQS_RN3
FBB_D50
FBB_DQS_RN4
FBB_D51
FBB_DQS_RN5
FBB_D52
FBB_DQS_RN6
FBB_D53
FBB_DQS_RN7
FBB_D54
FBB_D55
FBB_DQS_WP0
FBB_D56
FBB_DQS_WP1
FBB_D57
FBB_DQS_WP2
FBB_D58
FBB_DQS_WP3
FBB_D59
FBB_DQS_WP4
FBB_D60
FBB_DQS_WP5
FBB_D61
FBB_DQS_WP6
FBB_D62
FBB_DQS_WP7
FBB_D63
FBB_WCK01
FBB_WCK01*
FBB_WCK23
FBB_WCK23*
FBB_WCK45
FBB_WCK45*
FBB_WCK67
FBB_WCK67*
D6
D7
B6
FB_B0_CLK_P
FB_B0_CLK_N
FB_B1_CLK_P
FB_B1_CLK_N
E11
E3
A3
C9
F23
F27
C30
A24
PLACE_NEAR=U8000.H27:8.4MM
2
2
76 95
OUT
76 95
OUT
76 95
OUT
76 95
OUT
76 95
OUT
76 95
OUT
76 95
OUT
76 95
OUT
76 95
OUT
76 95
OUT
76 95
OUT
76 95
OUT
76 95
OUT
73 76 95
OUT
73 76 95
OUT
76 95
OUT
76 95
OUT
76 95 79 73 8
OUT
76 95
OUT
76 95
OUT
76 95
OUT
76 95
OUT
76 95
OUT
76 95
OUT
76 95
OUT
76 95
OUT
76 95
OUT
D
L8201
FERR-220-OHM-2A
8
73
79
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
=PP1V05_GPU_PEX_IOVDD
1
1
1
C8201
20%
4V
CERM-X6S
0201
2
A23
FBB_PLL_AVDD H17
FBB_DEBUG0 G14
FBB_DEBUG1 G20
FB_VREF H26
FBB_CMD_RFU0 C12
FBB_CMD_RFU1 C20
73
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
=PP1V05_GPU_PEX_IOVDD
1
PP1V05_GPU_FB_DLL_AVDD
1
1
C8208
C8204
20UF
2
10%
6.3V
X6S
0201
C
76 95
OUT
73 76 95
OUT
76 95
OUT
76 95
OUT
76 95
OUT
76 95
OUT
76 95
95 76 73
FB_B0_RESET_L
95 76 73
FB_B1_RESET_L
1
1
R8254
R8255
10K
BI
76 95
BI
76 95
BI
76 95
BI
76 95
BI
76 95
BI
1%
1/20W
MF
2 201
76 95
BI
10K
1%
1/20W
MF
201
76 95
BI
76 95
2
73 76 95
IN
73 76 95
FB_B0_CKE_L
FB_B1_CKE_L
1
R8257
10K
1%
1/20W
MF
201
1%
1/20W
MF
2 201
76 95
IN
76 95
IN
76 95
IN
76 95
IN
76 95
IN
76 95
IN
76 95
IN
76 95
MEM VREFC & VREFD SWITCH
FB_SW_LEG
76 75
OUT
PP1V05_GPU_FB_PLL_AVDD
GPU_FBB_DEBUG0
GPU_FBB_DEBUG1
FB_VREF
Q8265
3
73
1
C8206
1
1UF
73
2
NC
NC
FBB_WCKB67
FBB_WCKB67*
D
SSM3K15FV
SOD-VESM-HF
73
C8207
0.1UF
20%
4V
CERM-X6S
0201
2
10%
6.3V
X6S
0201
2
S
G 1
GPU_ALT_VREF
IN
A27
=PP1V35_GPU_S0_FB
78
8 73
SYNC_MASTER=D2_SEAN
SYNC_DATE=03/05/2012
PAGE TITLE
KEPLER FRAME BUFFER I/F
1
R8206
1
DRAWING NUMBER
R8207
60.4
73
60.4
1%
1/20W
MF
201
1%
1/20W
MF
201
2
Apple Inc.
73
GPU_FBB_DEBUG1
4
3
051-9589
2
SIZE
D
REVISION
R
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
GPU_FBB_DEBUG0
5
2
76 95
NOTICE OF PROPRIETARY PROPERTY:
6
C8205
0.1UF
20%
4V
CERM-X6S
0201
2
B
73
7
1
1UF
20%
2V
X6T-CERM
0402
73 76 95
2
2
8
73
2
0603
CRITICAL
ESR = 0.05OHM
10K
PLACE_NEAR=U8000.J27:8.4MM
FB_CAL_PD_VDDQ
10%
6.3V
X6S
0201
L8202
FERR-220-OHM-2A
OUT
FB_B0_EDC & lt; 0 & gt;
FB_B0_EDC & lt; 1 & gt;
FB_B0_EDC & lt; 2 & gt;
FB_B0_EDC & lt; 3 & gt;
FB_B1_EDC & lt; 0 & gt;
FB_B1_EDC & lt; 1 & gt;
FB_B1_EDC & lt; 2 & gt;
FB_B1_EDC & lt; 3 & gt;
E28
B30
0.1UF
2
FB PLL & DLL VDD
R8256
E23
73
C8203
1UF
20%
2V
X6T-CERM
0402
2
NC
NC
NC
NC
NC
NC
NC
NC
D10
D5
C3
B9
1
C8202
20UF
1
D9
E4
B2
A9
D22
D28
A30
B23
PP1V05_GPU_FB_PLL_AVDD
2
0603
CRITICAL
ESR = 0.05OHM
OUT
FB_B0_DBI_L & lt; 0 & gt;
FB_B0_DBI_L & lt; 1 & gt;
FB_B0_DBI_L & lt; 2 & gt;
FB_B0_DBI_L & lt; 3 & gt;
FB_B1_DBI_L & lt; 0 & gt;
FB_B1_DBI_L & lt; 1 & gt;
FB_B1_DBI_L & lt; 2 & gt;
FB_B1_DBI_L & lt; 3 & gt;
FBB_WCKB45
FBB_WCKB45*
A26
D12
E12
E20
F20
OUT
FBB_WCKB23
FBB_WCKB23*
F26
E26
E17
FB_B0_CS_L
FB_B0_A & lt; 3 & gt;
FB_B0_A & lt; 2 & gt;
FB_B0_A & lt; 4 & gt;
FB_B0_A & lt; 5 & gt;
FB_B0_WE_L
FB_B0_A & lt; 7 & gt;
FB_B0_A & lt; 6 & gt;
FB_B0_ABI_L
FB_B0_A & lt; 8 & gt;
FB_B0_A & lt; 0 & gt;
FB_B0_A & lt; 1 & gt;
FB_B0_RAS_L
FB_B0_RESET_L
FB_B0_CKE_L
FB_B0_CAS_L
FB_B1_CS_L
FB_B1_A & lt; 3 & gt;
FB_B1_A & lt; 2 & gt;
FB_B1_A & lt; 4 & gt;
FB_B1_A & lt; 5 & gt;
FB_B1_WE_L
FB_B1_A & lt; 7 & gt;
FB_B1_A & lt; 6 & gt;
FB_B1_ABI_L
FB_B1_A & lt; 8 & gt;
FB_B1_A & lt; 0 & gt;
FB_B1_A & lt; 1 & gt;
FB_B1_RAS_L
FB_B1_RESET_L
FB_B1_CKE_L
FB_B1_CAS_L
FBB_WCKB01
FBB_WCKB01*
C6
D13
E14
F14
A12
B12
C14
B14
G15
F15
E15
D15
A14
D14
A15
B15
C17
D18
E18
F18
A20
B20
C18
B18
G18
G17
F17
D16
A18
D17
A17
B17
40.2
1%
1/20W
MF
201
OUT
FB_B1_WCLK_P & lt; 0 & gt;
FB_B1_WCLK_N & lt; 0 & gt;
NC
NC
1
73
BI
95 76
PLACE CLOSE TO BGA
FBA_WCKB67
FBA_WCKB67*
BI
95 76
R8253
10K
75 95
BI
95 76
1
R8252
75 95
OUT
95 76
75 95
OUT
BOM options provided by this page:
BGA
75 95
OUT
Signal aliases required by this page:
(NONE)
OUT
FB_A0_CLK_P
FB_A0_CLK_N
FB_A1_CLK_P
FB_A1_CLK_N
FBA_WCKB45
FBA_WCKB45*
AJ31
FB_VDDQ_SENSE F1
R8251
10K
BGA
95 75
1
R8250
U8000
NV-GK107
4.18.0
BRANCH
PAGE
82 OF 132
SHEET
73 OF 99
1
A
8
7
6
5
4
74 8
74 8
GPUFB_BOOT_RC
1
5%
1/16W
MF-LF
402
C8371
2
20%
10V
X6S-CERM
0603
1.62K2
GPU_FBVDDQ_SENSE
1%
1/20W
MF
201
VOLTAGE=1.35V
19
20
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
DIDT=TRUE
7
GPUFB_VO
GPUFB_OCSET
301K
1%
1/20W
MF
2 201
R8353
1.62K2
IN
88
4
13
GPUFB_FSEL
2
R8368
1
R8350
0
1
C
C8376
10PF
1%
1/20W
MF
2 201
2
R8389
GPUFB_DRVH
1
2
7 POWERPAK-6X3.7
3
0.002
1
1
2
PP1V5R1V35_GPU_REG_R 1
MIN_LINE_WIDTH=0.6 mm
3
MIN_NECK_WIDTH=0.2 mm
8
PCMC063T-SM
1
R8352
1
4.64K
C8361
4
RTN
5
XW8352
5%
25V
NP0-C0G
402
2
10%
16V
X6S-CERM
0603
1/20W
MF
201
C8365
2
PLACE_NEAR=L8360.2:3MM
1
270UF
20%
2V 2
TANT
CASE-B4-SM
20%
2V 2
TANT
CASE-B4-SM
PLACE_NEAR=L8360.2:3MM
GPUFB_CS_N
99 96
XW8351
2
SM
GPUFB_GPU_OCSET_R
1
R83711
GPUFB_GPU_VO_R
4.75K
1%
1/20W
MF
201 2
PGND
C8370
1000PF
2
1
10%
16V
X7R-CERM
0201
2
C
1
R8372
4.75K
1%
1/20W
MF
2 201
IN
GPUFB_SET_R
5%
50V
2 COG-CERM
0201-1
C8363
270UF
SM
GND
2
CRITICAL
C8360 1
1
1000PF
GPUFB_CS_P
FSEL
5 VID1
78
10PF
1%
1/20W
MF
2 201
CRITICAL
PLACE_NEAR=L8360.2:1.5MM
6
99 96
8
2
4
VOLTAGE=1.05V
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
GATE_NODE=TRUE
DIDT=TRUE
PGOOD
=PP1V5R1V35_GPU_REG
1%
1W
MF
0612
CRITICAL
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
GATE_NODE=TRUE
DIDT=TRUE
GPUFB_LL
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
SWITCH_NODE=TRUE
DIDT=TRUE
R8380
Q8360
CRITICAL
SIZ710DT
L8360
0.68UH-25A-5.5MOHM
1
5%
1/16W
MF-LF
402
CRITICAL
5%
1/20W
MF
201
NOSTUFF
4.64K
GPUFB_DRVH_R
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
GATE_NODE=TRUE
DIDT=TRUE
D
376S0959
6 VID0
R8363 1
0
5%
C8372
2.2UF
2
5%
2 50V
COG-CERM
0201-1
VOUT = 1.5V / 1.35V
13A MAX OUTPUT
9 SET1
NOSTUFF
1%
1/20W
MF
2 201
R8354
2
8 SET0
1
150K
1
10%
25V
X5R
603-1
10%
16V
X7R-CERM
0402
GPUFB_DRVL
3
10%
16V
X7R-CERM
0402
2
1UF
5%
25V
NP0-C0G
402
1
0.01UF
NOSTUFF
LGATE 1
GPUFB_SET0
1
PHASE 16
SREF
GPUFB_SET1
C8373
1
14
GPUFB_RTN_DIV
1%
1/20W
MF
201
VOLTAGE=0V
UGATE 17
11 OCSET
GPUFB_PGOOD
OUT
1
BOOT 18
12 VO
R8367
73
97
CRITICAL
GPUFB_SREF
1
GPU_FBGND_SENSE
UTQFN
10 FB
GPUFB_SENSE_DIV
1
2
GPU FB SUPPLY
C8362
1000PF
2
IN
0.1UF
1
C8358
20%
16V 2
POLY-TANT
CASE-D2E-SM
C8355
GPUFB_VBST
ISL95870AH
97 73
PLACE_NEAR=Q8360.1:1.5MM
1
1
F = 500 KHZ
PVCC
15 EN
=P1V35FB_EN
1
R83591
5%
1/16W
MF-LF
402 2
U8350
IN
C8356
0
VCC
D
CRITICAL
68UF
2
PP5V_S0GPU_P1V35_GPU
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V
OMIT_TABLE
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
DIDT=TRUE
10UF
2.2
88
1
=PP5V_S0GPU_P1V0P1V35_GPU
R8351 1
R8381
2
3
=PPVIN_S0GPU_P1V5P1V0
FBVDD_ALTVO
GPIO(16) VID1
VID0
FBVDD
1
R8349
0
1%
1/20W
MF
2 201
0
1.5V
1
27K
0
1.35V
XW8350
SM
GPUFB_AGND
1
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V
74 8
97 79
P1V05_GPU_PEX_IOVDD_SNS_P
74 8
2
PLACE_NEAR=U8350.1:1mm
=PPVIN_S0GPU_P1V5P1V0
=PP5V_S0GPU_P1V0P1V35_GPU
IN
OMIT_TABLE
CRITICAL
VOLTAGE=1.05V
1
R8301
1
5%
1/16W
MF-LF
402 2
P1V05_GPU_PEX_IOVDD_SNS_N
IN
R83251
14
13
VCC
3.01K
1%
1/16W
MF-LF
402
R8305
2
2
=P1V05_GPU_EN
88
3
IN
& lt; Ra & gt;
6
P1V05_GPU_FB
P1V05_GPU_SREF
4
P1V05_GPU_VO
8
7
P1V05_GPU_OCSET
88
9
P1V05_S0GPU_PGOOD
OUT
P1V05_GPU_RTN
1
2.74K
1%
1/16W
MF-LF
402
P1V05_GPU_FSEL
R8307
1
10PF
2
& lt; Rb & gt;
5%
50V
C0G-CERM
0402
2
2
1
1%
1/16W
MF-LF
402
& lt; Rb & gt;
B
Q8310
C8302
1
10%
16V
X5R
603
C8305
10PF
2
5%
50V
C0G-CERM
0402
1
12
11
SREF
PHASE
10
VO
LGATE
P1V05_GPU_VBST
P1V05_GPU_DRVH_R
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
DIDT=TRUE
CSD58873Q3D
Q3D
R8346
1 1
2
15
P1V05_GPU_LL
DIDT=TRUE
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
GATE_NODE=TRUE
5%
1/16W
MF-LF
402
CRITICAL
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
GATE_NODE=TRUE
DIDT=TRUE
3
0.003
TG
L8310
TGR
VSW
OCSET
1
P1V05_GPU_DRVL
RTN
5
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
GATE_NODE=TRUE
DIDT=TRUE
FSEL
GND
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
SWITCH_NODE=TRUE
DIDT=TRUE
A
2
PGND
BG
2
2
1
3
P1V05_S0GPU_REG_R
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
IHLP2525CZ-SM1
=PP1V05_S0GPU_REG
C8310 1
98 96
XW8302
C8309
P1V05_GPU_CS_P
98 96
1
1000PF
5%
25V
NP0-C0G
402
P1V05_GPU_CS_N
2
2
270UF
20%
2V 2
TANT
CASE-B4-SM
PLACE_NEAR=L8310.2:3MM
VOUT = 1.05V
5.3A MAX OUTPUT
F = 500 KHZ
PLACE_NEAR=L8310.2:1.5MM
SM
XW8301
2
5%
1/20W
MF
201
1
SM
P1V05_GPU_OCSET_R
1
C8303
R83211
10%
16V
X7R-CERM
0402
1%
1/20W
MF
201 2
SM
P1V05_GPU_AGND
1
P1V05_GPU_VO_R
2.74K
XW8300
2
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V
C8320
SYNC_MASTER=D2_SEAN
1000PF
2
10%
16V
X7R-CERM
0201
PLACE_NEAR=U8310.1:1mm
DRAWING NUMBER
1
R8322
Apple Inc.
2.74K
1%
1/20W
MF
2 201
6
5
4
3
051-9589
NOTICE OF PROPRIETARY PROPERTY:
2
SIZE
D
REVISION
R
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
7
SYNC_DATE=03/05/2012
PAGE TITLE
1
1V05 GPU / 1V35 FB POWER SUPPLY
Vout = 0.5V * (1 + Ra / Rb)
8
8
2
4
CRITICAL
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
SWITCH_NODE=TRUE
DIDT=TRUE
0.047UF
2
1%
1W
MF
0612
2.2UH-14A
6
7
8
P1V05_GPU_LL_FET
PGOOD
R8303
R8345
CRITICAL
P1V05_GPU_DRVH
4
CRITICAL
VIN 1
0
2.2UF
1
BOOT
UGATE
FB
NOSTUFF
2.74K
C8304
5
CRITICAL
1
R8306 1
2
UTQFN
EN
GPU 1V05 SUPPLY
10%
25V
X5R
603-1
376S1038
ISL95870
1%
1/16W
MF-LF
402
2
10%
16V
X7R-CERM
0402
2
U8310
3.01K
& lt; Ra & gt;
PVCC
C8312
1UF
5%
25V
NP0-C0G
402
9
1
1000PF
16
R8304
1
1
C8308
0.1UF
2.2
5%
1/16W
MF-LF
402 2
2
C8345
1
PP5V_S0GPU_P1V05_GPU
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V
B
20%
16V 2
POLY-TANT
CASE-D2E-SM
PGND
VOLTAGE=0V
2
1
68UF
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
DIDT=TRUE
20%
10V
X5R
603
PLACE_NEAR=Q8310.1:1.5MM
1
C8307
P1V05_GPU_BOOT_RC
10UF
2.2
97 79
C8301
4.18.0
BRANCH
PAGE
83 OF 132
SHEET
74 OF 99
1
A
8
7
6
5
4
2
3
1
Page Notes
(NONE)
95 73
IN
95 73
BOM options provided by this page:
IN
95 73
IN
95 73
IN
PLACE_NEAR=U8400.J11:8.4MM
CK TERMINATION - A0
95 73
1%
1/20W
MF
201
1
PLACE_NEAR=U8400.J12:8.4MM
IN
95 73
R8401
R8402
FB_A0_CLK_P 40.2 FBA0_CK_MID 40.2
FB_A0_CLK_N
1
2
1
2
IN
95 73
73 75 95
95 73
1%
1/20W
MF
201
IN
IN
95 73
IN
95 75 73
IN
95 75 73
10%
10V
2 X7R-CERM
0201PLACE_NEAR=U8400.J11:8.4MM
IN
95 73
IN
95 73
IN
95 73
IN
95 73
IN
1
1%
1/20W
MF
201 2
R84041
120
1%
1/20W
MF
201
95 73
R84031
120
1%
1/20W
MF
201 2
2
IN
95 73
IN
95 73
BI
95 73
BI
95 73
BI
95 73
CK TERMINATION - A1
BI
PLACE_NEAR=U8450.J11:8.4MM
95 73
C
95
73
75
R8451
R8452
40.2 2 FBA1_CK_MID1 40.2 2
PLACE_NEAR=U8450.J12:8.4MM
1
73
75
95
1%
1/20W
MF
201
IN
95 73
FB_A1_CLK_N
FB_A1_CLK_P
1
1%
1/20W
MF
201
H11
K10
K11
H10
FB_A0_A & lt; 2 & gt;
FB_A0_A & lt; 5 & gt;
FB_A0_A & lt; 4 & gt;
FB_A0_A & lt; 3 & gt;
K4
H5
H4
K5
J3
FB_A0_A & lt; 7 & gt;
FB_A0_A & lt; 1 & gt;
FB_A0_A & lt; 0 & gt;
FB_A0_A & lt; 6 & gt;
FB_A0_CKE_L
BA0/A2
BA1/A5
BA2/A4
BA3/A3
IN
95 73
IN
95 73
IN
J12
J11
G12
L12
L3
G3
J13
J1
J10
J2
FB_A0_CLK_P
FB_A0_CLK_N
FB_A0_CS_L
FB_A0_WE_L
FB_A0_CAS_L
FB_A0_RAS_L
FB_A0_ZQ
FB_A0_MF
FB_A0_SEN
FB_A0_RESET_L
A8/A7
A9/A1
A10/A0
A11/A6
CKE*
CK
CK*
CS*
WE*
CAS*
RAS*
ZQ
MF (MF=0)
SEN
RESET*
J4 ABI*
FB_A0_ABI_L
C2
C13
R13
R2
FB_A0_EDC & lt; 0 & gt;
FB_A0_EDC & lt; 1 & gt;
FB_A0_EDC & lt; 2 & gt;
FB_A0_EDC & lt; 3 & gt;
EDC0
EDC1
EDC2
EDC3
D4 WCK01
D5 WCK01*
FB_A0_WCLK_P & lt; 0 & gt;
FB_A0_WCLK_N & lt; 0 & gt;
P4 WCK23
P5 WCK23*
FB_A0_WCLK_P & lt; 1 & gt;
FB_A0_WCLK_N & lt; 1 & gt;
C8491
0.01UF
10%
10V PLACE_NEAR=U8450.J11:8.4MM
2 X7R-CERM
0201
D2
D13
P13
P2
DBI0*
DBI1*
DBI2*
DBI3*
(1 OF 2)
OMIT_TABLE
C8490
0.01UF
R8400
120
BGA
H5GQ1H24AFR-T2C
BGA
H5GQ1H24AFR-T2C
Signal aliases required by this page:
75 73
95
32MX32-1.25GHZ-MFL
32MX32-1.25GHZ-MFL
- =PP1V5R1V35_S0_FB_VDD
D
U8450
U8400
Power aliases required by this page:
A4
A2
B4
B2
E4
E2
F4
F2
A11
A13
B11
B13
E11
E13
F11
F13
U11
U13
T11
T13
N11
N13
M11
M13
U4
U2
T4
T2
N4
N2
M4
M2
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
U8400
32MX32-1.25GHZ-MFL
A5
J5
U5
NC
BGA
H5GQ1H24AFR-T2C
72 8
76 75
1
C8400
4.7UF
20%
2 6.3V
X6S
0402
1
C8403
4.7UF
20%
2 6.3V
X6S
0402
1
B
20%
4V
2 CERM-X6S
0201
1
C8418
0.1UF
10%
2 6.3V
X6S
0201
1
1
C8422
0.1UF
10%
2 6.3V
X6S
0201
C8404
4.7UF
20%
2 6.3V
X6S
0402
C8407
1UF
20%
4V
2 CERM-X6S
0201
C8411
1UF
20%
4V
2 CERM-X6S
0201
1
C8414
1UF
C8401
4.7UF
20%
2 6.3V
X6S
0402
1
C8410
1UF
20%
4V
2 CERM-X6S
0201
1
1
1
C8406
1UF
20%
4V
2 CERM-X6S
0201
1
A
C5
C10
D11
G1
G4
G11
G14
L1
L4
L11
L14
P11
R5
R10
=PP1V35_GPU_FBVDDQ
C8415
1UF
20%
4V
2 CERM-X6S
0201
1
C8419
0.1UF
10%
2 6.3V
X6S
0201
1
C8423
0.1UF
10%
2 6.3V
X6S
0201
1
C8402
4.7UF
20%
6.3V
2 X6S
0402
1
C8405
4.7UF
20%
6.3V
2 X6S
0402
1
C8408
1UF
20%
2 4V
CERM-X6S
0201
1
C8412
1UF
20%
2 4V
CERM-X6S
0201
1
C8416
0.1UF
10%
6.3V
2 X6S
0201
1
C8420
0.1UF
10%
6.3V
2 X6S
0201
1
C8424
0.1UF
10%
6.3V
2 X6S
0201
75
75
8
1
C8409
1UF
20%
2 4V
CERM-X6S
0201
1
C8413
1UF
20%
2 4V
CERM-X6S
0201
1
C8417
0.1UF
10%
6.3V
2 X6S
0201
1
C8421
0.1UF
10%
6.3V
2 X6S
0201
1
C8425
0.1UF
10%
6.3V
2 X6S
0201
FB_A0_VREFC
FB_A0_VREFD
(2 OF 2)
VDD
B1
B3
B12
B14
D1
D3
D12
D14
E5
E10
F1
F3
F12
F14
G2
G13
H3
H12
K3
K12
L2
L13
M1
M3
M12
M14
N5
N10
P1
P3
P12
P14
T1
T3
T12
T14
FB_A0_DQ & lt; 0 & gt;
FB_A0_DQ & lt; 1 & gt;
FB_A0_DQ & lt; 2 & gt;
FB_A0_DQ & lt; 3 & gt;
FB_A0_DQ & lt; 4 & gt;
FB_A0_DQ & lt; 5 & gt;
FB_A0_DQ & lt; 6 & gt;
FB_A0_DQ & lt; 7 & gt;
FB_A0_DQ & lt; 8 & gt;
FB_A0_DQ & lt; 9 & gt;
FB_A0_DQ & lt; 10 & gt;
FB_A0_DQ & lt; 11 & gt;
FB_A0_DQ & lt; 12 & gt;
FB_A0_DQ & lt; 13 & gt;
FB_A0_DQ & lt; 14 & gt;
FB_A0_DQ & lt; 15 & gt;
FB_A0_DQ & lt; 16 & gt;
FB_A0_DQ & lt; 17 & gt;
FB_A0_DQ & lt; 18 & gt;
FB_A0_DQ & lt; 19 & gt;
FB_A0_DQ & lt; 20 & gt;
FB_A0_DQ & lt; 21 & gt;
FB_A0_DQ & lt; 22 & gt;
FB_A0_DQ & lt; 23 & gt;
FB_A0_DQ & lt; 24 & gt;
FB_A0_DQ & lt; 25 & gt;
FB_A0_DQ & lt; 26 & gt;
FB_A0_DQ & lt; 27 & gt;
FB_A0_DQ & lt; 28 & gt;
FB_A0_DQ & lt; 29 & gt;
FB_A0_DQ & lt; 30 & gt;
FB_A0_DQ & lt; 31 & gt;
VSSQ
95 73
FB_A0_VREFC
BI
73 95
BI
73 95
BI
73 95
95 73
R8431
1.33K
1%
1/20W
MF
2 201
1
R8434
931
1%
1/20W
MF
2 201
95 73
BI
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
1
R8454
120
73 95
BI
1%
1/20W
MF
201 2
73 95
BI
R84501
120
1%
1/20W
MF
201 2
1%
1/20W
MF
201
95 73
2
IN
BI
95 73
BI
73 95
BI
BI
73 95
BI
BI
95 73
BI
95 73
95 73
73 95
BI
BI
73 95
BI
73 95
BI
73 95
J12
J11
G12
L12
L3
G3
J13
J1
J10
J2
FB_A1_CLK_P
FB_A1_CLK_N
FB_A1_CS_L
FB_A1_WE_L
FB_A1_CAS_L
FB_A1_RAS_L
FB_A1_ZQ
FB_A1_MF
FB_A1_SEN
FB_A1_RESET_L
CK
CK*
CS*
WE*
CAS*
RAS*
ZQ
MF (MF=0)
SEN
RESET*
J4 ABI*
FB_A1_ABI_L
C2
C13
R13
R2
FB_A1_EDC & lt; 0 & gt;
FB_A1_EDC & lt; 1 & gt;
FB_A1_EDC & lt; 2 & gt;
FB_A1_EDC & lt; 3 & gt;
EDC0
EDC1
EDC2
EDC3
95 73
BI
73 95
BI
IN
73 95
BI
IN
95 73
73 95
95 73
BI
IN
P4 WCK23
P5 WCK23*
FB_A1_WCLK_P & lt; 1 & gt;
FB_A1_WCLK_N & lt; 1 & gt;
73 95
BI
IN
95 73
D4 WCK01
D5 WCK01*
FB_A1_WCLK_P & lt; 0 & gt;
FB_A1_WCLK_N & lt; 0 & gt;
D2
D13
P13
P2
FB_A1_DBI_L & lt; 0 & gt;
FB_A1_DBI_L & lt; 1 & gt;
FB_A1_DBI_L & lt; 2 & gt;
FB_A1_DBI_L & lt; 3 & gt;
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
A8/A7
A9/A1
A10/A0
A11/A6
CKE*
73 95
A4
A2
B4
B2
E4
E2
F4
F2
A11
A13
B11
B13
E11
E13
F11
F13
U11
U13
T11
T13
N11
N13
M11
M13
U4
U2
T4
T2
N4
N2
M4
M2
FB_A1_DQ & lt; 0 & gt;
FB_A1_DQ & lt; 1 & gt;
FB_A1_DQ & lt; 2 & gt;
FB_A1_DQ & lt; 3 & gt;
FB_A1_DQ & lt; 4 & gt;
FB_A1_DQ & lt; 5 & gt;
FB_A1_DQ & lt; 6 & gt;
FB_A1_DQ & lt; 7 & gt;
FB_A1_DQ & lt; 8 & gt;
FB_A1_DQ & lt; 9 & gt;
FB_A1_DQ & lt; 10 & gt;
FB_A1_DQ & lt; 11 & gt;
FB_A1_DQ & lt; 12 & gt;
FB_A1_DQ & lt; 13 & gt;
FB_A1_DQ & lt; 14 & gt;
FB_A1_DQ & lt; 15 & gt;
FB_A1_DQ & lt; 16 & gt;
FB_A1_DQ & lt; 17 & gt;
FB_A1_DQ & lt; 18 & gt;
FB_A1_DQ & lt; 19 & gt;
FB_A1_DQ & lt; 20 & gt;
FB_A1_DQ & lt; 21 & gt;
FB_A1_DQ & lt; 22 & gt;
FB_A1_DQ & lt; 23 & gt;
FB_A1_DQ & lt; 24 & gt;
FB_A1_DQ & lt; 25 & gt;
FB_A1_DQ & lt; 26 & gt;
FB_A1_DQ & lt; 27 & gt;
FB_A1_DQ & lt; 28 & gt;
FB_A1_DQ & lt; 29 & gt;
FB_A1_DQ & lt; 30 & gt;
FB_A1_DQ & lt; 31 & gt;
73 95
73 95
73 75 76
C5
C10
D11
G1
G4
G11
G14
L1
L4
L11
L14
P11
R5
R10
C8450
4.7UF
C8453
4.7UF
1
C8451
4.7UF
20%
6.3V
2 X6S
0402
1
C8454
4.7UF
20%
6.3V
2 X6S
0402
1
C8452
4.7UF
20%
2 6.3V
X6S
0402
1
C8455
4.7UF
20%
2 6.3V
X6S
0402
C8456
1UF
1
C8457
1UF
1
C8458
1UF
1
C8459
1UF
20%
4V
2 CERM-X6S
0201
20%
2 4V
CERM-X6S
0201
20%
4V
2 CERM-X6S
0201
20%
4V
2 CERM-X6S
0201
1
1
1
1
C8460
1UF
C8464
1UF
20%
4V
2 CERM-X6S
0201
1R8432
C8461
1UF
20%
2 4V
CERM-X6S
0201
C8462
1UF
20%
4V
2 CERM-X6S
0201
C8463
1UF
20%
4V
2 CERM-X6S
0201
1
C8465
1UF
20%
2 4V
CERM-X6S
0201
1
C8466
0.1UF
10%
2 6.3V
X6S
0201
1
C8467
0.1UF
10%
2 6.3V
X6S
0201
549
1%
1/20W
MF
2 201
1
C8468
0.1UF
10%
2 6.3V
X6S
0201
1
R8433
1.33K
1%
1/20W
10%
MF
25V
2 X7R-CERM 2 201
0201
NC
BGA
H5GQ1H24AFR-T2C
=PP1V35_GPU_FBVDDQ
1
PLACE_NEAR=U8400.U10:8.4MM
1
C8469
0.1UF
10%
6.3V
2 X6S
0201
1
C8470
0.1UF
10%
2 6.3V
X6S
0201
1
C8471
0.1UF
10%
2 6.3V
X6S
0201
PLACE_NEAR=U8400.U10:8.4MM
1
R8435
931
1%
1/20W
MF
2 201
1
FB_SW_LEGIN
PLACE_NEAR=U8400.A10:8.4MM
73 75
76
C8472
0.1UF
10%
2 6.3V
X6S
0201
1
C8473
0.1UF
10%
6.3V
2 X6S
0201
1
C8474
0.1UF
10%
2 6.3V
X6S
0201
1
C8475
0.1UF
10%
2 6.3V
X6S
0201
PLACE_NEAR=U8400.U10:8.4MM
PLACE_NEAR=U8400.U10:8.4MM
75
75
6
IN
73 95
1
10%
25V
2 X7R-CERM
0201
95 73
R84531
120
76 75 72 8
C8433
820PF
IN
73 95
=PP1V35_GPU_FBVDDQ
1
IN
95 73
73 95
20%
4V
2 CERM-X6S
0201
C8432
820PF
IN
DBI0*
DBI1*
DBI2*
DBI3*
(1 OF 2)
(2 OF 2)
VDD
VSS
B5
B10
D10
G5
G10
H1
H14
K1
K14
L5
L10
P10
T5
T10
A5
J5
U5
76 75 72 8
5
FB_A1_VREFC
FB_A1_VREFD
4
B1
B3
B12
B14
D1
D3
D12
D14
E5
E10
F1
F3
F12
F14
G2
G13
H3
H12
K3
K12
L2
L13
M1
M3
M12
M14
N5
N10
P1
P3
P12
P14
T1
T3
T12
T14
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
D
C
NC
FB_A1_A & lt; 8 & gt;
IN
73 95
NC
=PP1V35_GPU_FBVDDQ
1
R8480
549
1%
1/20W
MF
2 201
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.1 mm
PLACE_NEAR=U8450.J14:8.4MM
FB_A1_VREFC
75
PLACE_NEAR=U8450.J14:8.4MM
1
PLACE_NEAR=U8450.J14:8.4MM
1
R8481
1.33K
C8481
820PF
1%
1/20W
MF
2 201
10%
25V
2 X7R-CERM
0201
OMIT_TABLE
PLACE CLOSE TO U8400
1
IN
95 73
73 95
BI
IN
95 73
K4
H5
H4
K5
J3
FB_A1_A & lt; 7 & gt;
FB_A1_A & lt; 1 & gt;
FB_A1_A & lt; 0 & gt;
FB_A1_A & lt; 6 & gt;
FB_A1_CKE_L
BA0/A2
BA1/A5
BA2/A4
BA3/A3
OMIT_TABLE
73 95
BI
IN
95 75 73
BI
IN
95 75 73
20%
2 6.3V
X6S
0402
PLACE_NEAR=U8400.J14:8.4MM
1
FB_A0_VREFD
IN
73 95
1
75
IN
95 73
BI
PLACE_NEAR=U8400.J14:8.4MM
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.1 mm
IN
95 73
73 95
20%
2 6.3V
X6S
0402
1%
1/20W
MF
2 201
75
10%
2 25V
X7R-CERM
0201
IN
95 73
73 95
BI
NC
FB_SW_LEGIN
VDDQ
73 95
BI
IN
R8430
549PLACE_NEAR=U8400.J14:8.4MM
C8431
820PF
IN
H11
K10
K11
H10
FB_A1_A & lt; 2 & gt;
FB_A1_A & lt; 5 & gt;
FB_A1_A & lt; 4 & gt;
FB_A1_A & lt; 3 & gt;
32MX32-1.25GHZ-MFL
FB_A0_A & lt; 8 & gt;
PLACE_NEAR=U8400.J14:8.4MM
A1
A3
A12
A14
C1
C3
C4
C11
C12
C14
E1
E3
E12
E14
F5
F10
H2
H13
K2
K13
M5
M10
N1
N3
N12
N14
R1
R3
R4
R11
R12
R14
U1
U3
U12
U14
BI
NC
1
1
IN
95 73
73 95
1
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.1 mm
IN
95 73
73 95
BI
IN
95 73
73 95
BI
U8450
76 75 72 8
76 75 72 8
95 73
BI
=PP1V35_GPU_FBVDDQ
OMIT_TABLE
J14 VREFC
A10
U10 VREFD
7
VSS
B5
B10
D10
G5
G10
H1
H14
K1
K14
L5
L10
P10
T5
T10
FB_A0_DBI_L & lt; 0 & gt;
FB_A0_DBI_L & lt; 1 & gt;
FB_A0_DBI_L & lt; 2 & gt;
FB_A0_DBI_L & lt; 3 & gt;
1
R8484
931
1%
1/20W
MF
2 201
FB_SW_LEGIN
73 75 76
B
PLACE_NEAR=U8450.J14:8.4MM
VDDQ
VSSQ
J14 VREFC
A10
U10 VREFD
3
A1
A3
A12
A14
C1
C3
C4
C11
C12
C14
E1
E3
E12
E14
F5
F10
H2
H13
K2
K13
M5
M10
N1
N3
N12
N14
R1
R3
R4
R11
R12
R14
U1
U3
U12
U14
PLACE CLOSE TO U8450
=PP1V35_GPU_FBVDDQ
76 75 72 8
PLACE_NEAR=U8450.U10:8.4MM
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.1 mm
1R8482
549
1%
1/20W
MF
2 201
FB_A1_VREFD
75
PLACE_NEAR=U8450.U10:8.4MM
PLACE_NEAR=U8450.A10:8.4MM
1
1
1
C8482
820PF
10%
2 25V
X7R-CERM
0201
C8483
820PF
R8483
1.33K
1%
1/20W
10%
MF
25V
2 X7R-CERM 2 201
0201
PLACE_NEAR=U8450.U10:8.4MM
1
R8485
931
1%
1/20W
MF
2 201
FB_SW_LEG
IN
73 75 76
PLACE_NEAR=U8450.U10:8.4MM
SYNC_MASTER=D2_SEAN
SYNC_DATE=03/05/2012
PAGE TITLE
GDDR5 Frame Buffer A
DRAWING NUMBER
Apple Inc.
051-9589
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
2
SIZE
D
REVISION
4.18.0
BRANCH
PAGE
84 OF 132
SHEET
75 OF 99
1
A
8
7
6
5
4
3
2
1
Page Notes
(NONE)
95 73
IN
95 73
(NONE)
IN
95 73
IN
95 73
CK TERMINATION - B0
PLACE_NEAR=U8500.J11:8.4MM
R8501
R8502
FB_B0_CLK_P 40.2 FBB0_CK_MID 40.2
FB_B0_CLK_N
1
2
1
2
1%
1/20W
MF
201
1
PLACE_NEAR=U8500.J12:8.4MM
IN
95 73
IN
95 73
IN
95 73
73 76 95
95 73
1%
1/20W
MF
201
IN
IN
95 73
C8590
0.01UF
IN
95 76 73
IN
95 76 73
10%
10V
2 X7R-CERM
0201PLACE_NEAR=U8500.J11:8.4MM
IN
95 73
IN
95 73
IN
95 73
IN
95 73
IN
1
R8500
120
1%
1/20W
MF
201 2
R85041
120
1%
1/20W
MF
201
95 73
R85031
120
1%
1/20W
MF
201 2
2
IN
95 73
IN
95 73
BI
95 73
BI
95 73
BI
95 73
C
95
73
76
CK TERMINATION - B1
PLACE_NEAR=U8550.J11:8.4MM
R8551
R8552
FB_B1_CLK_P 40.2 FBB1_CK_MID 40.2
FB_B1_CLK_N
1
2
1
2
1%
1/20W
MF
201
BGA
H5GQ1H24AFR-T2C
BGA
H5GQ1H24AFR-T2C
BOM options provided by this page:
76 73
95
32MX32-1.25GHZ-MFL
32MX32-1.25GHZ-MFL
Signal aliases required by this page:
D
U8550
U8500
Power aliases required by this page:
- =PP1V5R1V35_S0_FB_VDD
1
PLACE_NEAR=U8550.J12:8.4MM
95 73
IN
95 73
73
76
95
1%
1/20W
MF
201
BI
IN
95 73
IN
95 73
IN
H11
K10
K11
H10
FB_B0_A & lt; 2 & gt;
FB_B0_A & lt; 5 & gt;
FB_B0_A & lt; 4 & gt;
FB_B0_A & lt; 3 & gt;
K4
H5
H4
K5
J3
FB_B0_A & lt; 7 & gt;
FB_B0_A & lt; 1 & gt;
FB_B0_A & lt; 0 & gt;
FB_B0_A & lt; 6 & gt;
FB_B0_CKE_L
J12
J11
G12
L12
L3
G3
J13
J1
J10
J2
FB_B0_CLK_P
FB_B0_CLK_N
FB_B0_CS_L
FB_B0_WE_L
FB_B0_CAS_L
FB_B0_RAS_L
FB_B0_ZQ
FB_B0_MF
FB_B0_SEN
FB_B0_RESET_L
BA0/A2
BA1/A5
BA2/A4
BA3/A3
A8/A7
A9/A1
A10/A0
A11/A6
CKE*
OMIT_TABLE
CK
CK*
CS*
WE*
CAS*
RAS*
ZQ
MF (MF=0)
SEN
RESET*
J4 ABI*
FB_B0_ABI_L
C2
C13
R13
R2
FB_B0_EDC & lt; 0 & gt;
FB_B0_EDC & lt; 1 & gt;
FB_B0_EDC & lt; 2 & gt;
FB_B0_EDC & lt; 3 & gt;
EDC0
EDC1
EDC2
EDC3
D4 WCK01
D5 WCK01*
FB_B0_WCLK_P & lt; 0 & gt;
FB_B0_WCLK_N & lt; 0 & gt;
P4 WCK23
P5 WCK23*
FB_B0_WCLK_P & lt; 1 & gt;
FB_B0_WCLK_N & lt; 1 & gt;
C8591
0.01UF
10%
2 10V
X7R-CERM
0201 PLACE_NEAR=U8550.J11:8.4MM
D2
D13
P13
P2
DBI0*
DBI1*
DBI2*
DBI3*
(1 OF 2)
A4
A2
B4
B2
E4
E2
F4
F2
A11
A13
B11
B13
E11
E13
F11
F13
U11
U13
T11
T13
N11
N13
M11
M13
U4
U2
T4
T2
N4
N2
M4
M2
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
U8500
32MX32-1.25GHZ-MFL
A5
J5
U5
NC
BGA
H5GQ1H24AFR-T2C
72 8
76 75
1
C8500
4.7UF
20%
6.3V
2 X6S
0402
1
C8503
4.7UF
20%
6.3V
2 X6S
0402
1
B
C8514
1UF
20%
2 4V
CERM-X6S
0201
1
C8518
0.1UF
10%
6.3V
2 X6S
0201
1
C8522
0.1UF
10%
6.3V
2 X6S
0201
C8501
4.7UF
20%
2 6.3V
X6S
0402
1
C8504
4.7UF
20%
6.3V
2 X6S
0402
C8507
1UF
20%
4V
2 CERM-X6S
0201
1
C8510
1UF
20%
2 4V
CERM-X6S
0201
1
1
1
C8506
1UF
20%
2 4V
CERM-X6S
0201
1
A
C5
C10
D11
G1
G4
G11
G14
L1
L4
L11
L14
P11
R5
R10
=PP1V35_GPU_FBVDDQ
C8511
1UF
20%
4V
2 CERM-X6S
0201
1
C8515
1UF
20%
4V
2 CERM-X6S
0201
1
C8519
0.1UF
10%
2 6.3V
X6S
0201
1
C8523
0.1UF
10%
2 6.3V
X6S
0201
1
C8502
4.7UF
20%
2 6.3V
X6S
0402
1
C8505
4.7UF
20%
6.3V
2 X6S
0402
1
C8508
1UF
20%
4V
2 CERM-X6S
0201
1
C8512
1UF
20%
4V
2 CERM-X6S
0201
1
C8516
0.1UF
10%
6.3V
2 X6S
0201
1
C8520
0.1UF
10%
6.3V
2 X6S
0201
1
C8524
0.1UF
10%
6.3V
2 X6S
0201
76
76
8
1
C8509
1UF
20%
2 4V
CERM-X6S
0201
1
C8513
1UF
20%
2 4V
CERM-X6S
0201
1
C8517
0.1UF
10%
6.3V
2 X6S
0201
1
C8521
0.1UF
10%
6.3V
2 X6S
0201
1
C8525
0.1UF
10%
6.3V
2 X6S
0201
FB_B0_VREFC
FB_B0_VREFD
(2 OF 2)
VDD
B1
B3
B12
B14
D1
D3
D12
D14
E5
E10
F1
F3
F12
F14
G2
G13
H3
H12
K3
K12
L2
L13
M1
M3
M12
M14
N5
N10
P1
P3
P12
P14
T1
T3
T12
T14
OMIT_TABLE
FB_B0_DQ & lt; 0 & gt;
FB_B0_DQ & lt; 1 & gt;
FB_B0_DQ & lt; 2 & gt;
FB_B0_DQ & lt; 3 & gt;
FB_B0_DQ & lt; 4 & gt;
FB_B0_DQ & lt; 5 & gt;
FB_B0_DQ & lt; 6 & gt;
FB_B0_DQ & lt; 7 & gt;
FB_B0_DQ & lt; 8 & gt;
FB_B0_DQ & lt; 9 & gt;
FB_B0_DQ & lt; 10 & gt;
FB_B0_DQ & lt; 11 & gt;
FB_B0_DQ & lt; 12 & gt;
FB_B0_DQ & lt; 13 & gt;
FB_B0_DQ & lt; 14 & gt;
FB_B0_DQ & lt; 15 & gt;
FB_B0_DQ & lt; 16 & gt;
FB_B0_DQ & lt; 17 & gt;
FB_B0_DQ & lt; 18 & gt;
FB_B0_DQ & lt; 19 & gt;
FB_B0_DQ & lt; 20 & gt;
FB_B0_DQ & lt; 21 & gt;
FB_B0_DQ & lt; 22 & gt;
FB_B0_DQ & lt; 23 & gt;
FB_B0_DQ & lt; 24 & gt;
FB_B0_DQ & lt; 25 & gt;
FB_B0_DQ & lt; 26 & gt;
FB_B0_DQ & lt; 27 & gt;
FB_B0_DQ & lt; 28 & gt;
FB_B0_DQ & lt; 29 & gt;
FB_B0_DQ & lt; 30 & gt;
FB_B0_DQ & lt; 31 & gt;
76 75 72 8
VSSQ
BI
73 95
95 73
1
95 76 73
R8531
1.33K
95 73
1%
1/20W
MF
2 201
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
1
R8554
120
73 95
BI
1%
1/20W
MF
201 2
73 95
BI
R85501
120
95 73
R85531
120
1%
1/20W
MF
201 2
IN
73 95
1%
1/20W
MF
201
95 73
2
IN
BI
95 73
BI
73 95
BI
BI
73 95
BI
BI
95 73
BI
95 73
95 73
73 95
BI
BI
73 95
BI
73 95
BI
73 95
K4
H5
H4
K5
J3
FB_B1_A & lt; 7 & gt;
FB_B1_A & lt; 1 & gt;
FB_B1_A & lt; 0 & gt;
FB_B1_A & lt; 6 & gt;
FB_B1_CKE_L
BA0/A2
BA1/A5
BA2/A4
BA3/A3
95 73
BI
73 95
BI
IN
73 95
BI
IN
95 73
73 95
95 73
BI
OMIT_TABLE
J12
J11
G12
L12
L3
G3
J13
J1
J10
J2
FB_B1_CLK_P
FB_B1_CLK_N
FB_B1_CS_L
FB_B1_WE_L
FB_B1_CAS_L
FB_B1_RAS_L
FB_B1_ZQ
FB_B1_MF
FB_B1_SEN
FB_B1_RESET_L
CK
CK*
CS*
WE*
CAS*
RAS*
ZQ
MF (MF=0)
SEN
RESET*
J4 ABI*
FB_B1_ABI_L
C2
C13
R13
R2
FB_B1_EDC & lt; 0 & gt;
FB_B1_EDC & lt; 1 & gt;
FB_B1_EDC & lt; 2 & gt;
FB_B1_EDC & lt; 3 & gt;
EDC0
EDC1
EDC2
EDC3
IN
D4 WCK01
D5 WCK01*
FB_B1_WCLK_P & lt; 0 & gt;
FB_B1_WCLK_N & lt; 0 & gt;
P4 WCK23
P5 WCK23*
FB_B1_WCLK_P & lt; 1 & gt;
FB_B1_WCLK_N & lt; 1 & gt;
73 95
BI
IN
95 73
DBI0*
DBI1*
DBI2*
DBI3*
(1 OF 2)
A8/A7
A9/A1
A10/A0
A11/A6
CKE*
73 95
D2
D13
P13
P2
FB_B1_DBI_L & lt; 0 & gt;
FB_B1_DBI_L & lt; 1 & gt;
FB_B1_DBI_L & lt; 2 & gt;
FB_B1_DBI_L & lt; 3 & gt;
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
A4
A2
B4
B2
E4
E2
F4
F2
A11
A13
B11
B13
E11
E13
F11
F13
U11
U13
T11
T13
N11
N13
M11
M13
U4
U2
T4
T2
N4
N2
M4
M2
FB_B1_DQ & lt; 0 & gt;
FB_B1_DQ & lt; 1 & gt;
FB_B1_DQ & lt; 2 & gt;
FB_B1_DQ & lt; 3 & gt;
FB_B1_DQ & lt; 4 & gt;
FB_B1_DQ & lt; 5 & gt;
FB_B1_DQ & lt; 6 & gt;
FB_B1_DQ & lt; 7 & gt;
FB_B1_DQ & lt; 8 & gt;
FB_B1_DQ & lt; 9 & gt;
FB_B1_DQ & lt; 10 & gt;
FB_B1_DQ & lt; 11 & gt;
FB_B1_DQ & lt; 12 & gt;
FB_B1_DQ & lt; 13 & gt;
FB_B1_DQ & lt; 14 & gt;
FB_B1_DQ & lt; 15 & gt;
FB_B1_DQ & lt; 16 & gt;
FB_B1_DQ & lt; 17 & gt;
FB_B1_DQ & lt; 18 & gt;
FB_B1_DQ & lt; 19 & gt;
FB_B1_DQ & lt; 20 & gt;
FB_B1_DQ & lt; 21 & gt;
FB_B1_DQ & lt; 22 & gt;
FB_B1_DQ & lt; 23 & gt;
FB_B1_DQ & lt; 24 & gt;
FB_B1_DQ & lt; 25 & gt;
FB_B1_DQ & lt; 26 & gt;
FB_B1_DQ & lt; 27 & gt;
FB_B1_DQ & lt; 28 & gt;
FB_B1_DQ & lt; 29 & gt;
FB_B1_DQ & lt; 30 & gt;
FB_B1_DQ & lt; 31 & gt;
73 95
73 95
C5
C10
D11
G1
G4
G11
G14
L1
L4
L11
L14
P11
R5
R10
=PP1V35_GPU_FBVDDQ
C8550
4.7UF
C8553
4.7UF
1
C8551
4.7UF
20%
2 6.3V
X6S
0402
1
C8554
4.7UF
20%
2 6.3V
X6S
0402
1
C8552
4.7UF
20%
2 6.3V
X6S
0402
1
C8555
4.7UF
20%
2 6.3V
X6S
0402
1
IN
73 75 76
C8556
1UF
1
C8557
1UF
1
C8558
1UF
1
C8559
1UF
20%
4V
2 CERM-X6S
0201
20%
4V
2 CERM-X6S
0201
20%
4V
2 CERM-X6S
0201
20%
4V
2 CERM-X6S
0201
1
1
1
C8560
1UF
20%
2 4V
CERM-X6S
0201
1
R8532
549
R8533
1.33K
1%
1/20W
10%
MF
25V
2 X7R-CERM 2 201
0201
(2 OF 2)
VDD
VSS
B5
B10
D10
G5
G10
H1
H14
K1
K14
L5
L10
P10
T5
T10
A5
J5
U5
C8561
1UF
20%
4V
2 CERM-X6S
0201
C8562
1UF
20%
4V
2 CERM-X6S
0201
C8563
1UF
20%
4V
2 CERM-X6S
0201
1
C8564
1UF
1
C8565
1UF
1
C8566
0.1UF
1
C8567
0.1UF
20%
2 4V
CERM-X6S
0201
20%
4V
2 CERM-X6S
0201
10%
6.3V
2 X6S
0201
10%
6.3V
2 X6S
0201
1
1
1
1
1
R8535
931
C8568
0.1UF
10%
2 6.3V
X6S
0201
1%
1/20W
MF
2 201
FB_SW_LEG
IN
PLACE_NEAR=U8500.U10:8.4MM
PLACE_NEAR=U8500.A10:8.4MM
C8569
0.1UF
10%
6.3V
2 X6S
0201
C8570
0.1UF
10%
6.3V
2 X6S
0201
10%
6.3V
2 X6S
0201
73 75 76
1
C8572
0.1UF
10%
2 6.3V
X6S
0201
1
C8573
0.1UF
10%
6.3V
2 X6S
0201
1
C8574
0.1UF
10%
6.3V
2 X6S
0201
76
76
5
C8571
0.1UF
1
C8575
0.1UF
10%
6.3V
2 X6S
0201
FB_B1_VREFC
FB_B1_VREFD
4
B1
B3
B12
B14
D1
D3
D12
D14
E5
E10
F1
F3
F12
F14
G2
G13
H3
H12
K3
K12
L2
L13
M1
M3
M12
M14
N5
N10
P1
P3
P12
P14
T1
T3
T12
T14
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
BI
73 95
D
C
NC
FB_B1_A & lt; 8 & gt;
73 95
IN
NC
76 75 72 8
=PP1V35_GPU_FBVDDQ
PLACE_NEAR=U8550.J14:8.4MM
1
R8580
549
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.1 mm
1%
1/20W
MF
2 201
FB_B1_VREFC
76
PLACE_NEAR=U8550.J14:8.4MM
PLACE_NEAR=U8550.J14:8.4MM
1
PLACE_NEAR=U8550.J14:8.4MM
1
C8581
820PF
10%
2 25V
X7R-CERM
0201
OMIT_TABLE
1%
1/20W
MF
2 201
PLACE_NEAR=U8500.J14:8.4MM
1
NC
BGA
H5GQ1H24AFR-T2C
PLACE_NEAR=U8500.U10:8.4MM
6
IN
73 95
R8534
931
1%
1/20W
MF
2 201
PLACE_NEAR=U8500.U10:8.4MM
IN
95 73
BI
PLACE_NEAR=U8500.U10:8.4MM
10%
25V
2 X7R-CERM
0201
IN
73 95
1
=PP1V35_GPU_FBVDDQ
C8533
820PF
IN
95 73
BI
20%
6.3V
2 X6S
0402
76 75 72 8
1
IN
95 73
73 95
1
C8532
820PF
IN
73 95
BI
IN
95 76 73
BI
PLACE CLOSE TO U8500
1
IN
73 95
1
PLACE_NEAR=U8500.J14:8.4MM
FB_B0_VREFD
IN
95 73
BI
20%
2 6.3V
X6S
0402
FB_B0_VREFC
76
IN
95 73
76
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.1 mm
IN
95 73
73 95
1
1%
1/20W
MF
2 201
PLACE_NEAR=U8500.J14:8.4MM
VDDQ
95 73
73 95
BI
NC
R8530
549
C8531
820PF
IN
73 95
BI
IN
1
10%
25V
2 X7R-CERM
0201
A1
A3
A12
A14
C1
C3
C4
C11
C12
C14
E1
E3
E12
E14
F5
F10
H2
H13
K2
K13
M5
M10
N1
N3
N12
N14
R1
R3
R4
R11
R12
R14
U1
U3
U12
U14
BI
PLACE_NEAR=U8500.J14:8.4MM
1
IN
95 73
73 95
H11
K10
K11
H10
FB_B1_A & lt; 2 & gt;
FB_B1_A & lt; 5 & gt;
FB_B1_A & lt; 4 & gt;
FB_B1_A & lt; 3 & gt;
32MX32-1.25GHZ-MFL
FB_B0_A & lt; 8 & gt;
=PP1V35_GPU_FBVDDQ
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.1 mm
IN
95 73
73 95
BI
IN
95 73
73 95
BI
NC
76 75 72 8
B5
B10
D10
G5
G10
H1
H14
K1
K14
L5
L10
P10
T5
T10
95 73
BI
U8550
FB_SW_LEG
J14 VREFC
A10
U10 VREFD
7
VSS
FB_B0_DBI_L & lt; 0 & gt;
FB_B0_DBI_L & lt; 1 & gt;
FB_B0_DBI_L & lt; 2 & gt;
FB_B0_DBI_L & lt; 3 & gt;
R8581
1.33K
1%
1/20W
MF
2 201
1
R8584
931
1%
1/20W
MF
2 201
FB_SW_LEG
VDDQ
VSSQ
J14 VREFC
A10
VREFD
U10
3
A1
A3
A12
A14
C1
C3
C4
C11
C12
C14
E1
E3
E12
E14
F5
F10
H2
H13
K2
K13
M5
M10
N1
N3
N12
N14
R1
R3
R4
R11
R12
R14
U1
U3
U12
U14
IN
73 75 76
B
PLACE CLOSE TO U8550
=PP1V35_GPU_FBVDDQ
76 75 72 8
MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.1 mm
PLACE_NEAR=U8550.U10:8.4MM
1
R8582
549
1%
1/20W
MF
2 201
FB_B1_VREFD
76
PLACE_NEAR=U8550.U10:8.4MM
1
1
PLACE_NEAR=U8550.A10:8.4MM
C8582
820PF
10%
2 25V
X7R-CERM
0201
1
C8583
820PF
R8583
1.33K
1%
1/20W
10%
MF
25V
2 X7R-CERM 2 201
0201
PLACE_NEAR=U8550.U10:8.4MM
1
R8585
931
1%
1/20W
MF
2 201
FB_SW_LEG
PLACE_NEAR=U8550.U10:8.4MM
SYNC_MASTER=D2_SEAN
IN
73 75 76
SYNC_DATE=03/05/2012
PAGE TITLE
GDDR5 Frame Buffer B
DRAWING NUMBER
Apple Inc.
051-9589
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
2
SIZE
D
REVISION
4.18.0
BRANCH
PAGE
85 OF 132
SHEET
76 OF 99
1
A
8
7
6
5
4
PP1V8_GPU_IFPA_IOVDD
PD FOR AUX CHANNELS (FOR NVIDIA)
95 82 77
PP3V3_GPU_IFPB_IOVDD
2
DISABLE PHY A & B FOR 15 " MBP
GPU_TESTMODE
PP1V05_GPU_IFPAB_PLLVDD
77
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.8V
DP_INT_EG_AUX_P
DP_INT_EG_AUX_N
95 82 77
3
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
1
1
R8601
R8602
Power aliases required by this page:
1
R8603
R8608
10K
100K
100K
1%
1/20W
MF
201
1%
1/20W
MF
201
77
1
R8617
R8618
100K
1%
1/20W
MF
201
77
100K
1%
1/20W
MF
201
77
PP1V05_GPU_IFPAB_PLLVDD AH8
AJ8
R8628
77
100K
100K
77
PP3V3_GPU_IFPX_PLLVDD
IFPC_RSET
AF7
AF8
1%
1/20W
MF
201
1%
1/20W
MF
201
PP3V3_GPU_IFPX_PLLVDD
IFPD_RSET
AG7
AN2
PP3V3_GPU_IFPX_PLLVDD
IFPEF_RSET
AB8
AD6
NO STUFF
1
R8627
2
77
NO STUFF
2
2
NC
1
2
77
=PP3V3_GPU_VDD33
79 78 77 71 8
77
1
77
1
R8623
R8624
4.7K
2
1%
1/20W
MF
201
77
4.7K
1%
1/20W
MF
201
2
83
OUT
83
BI
R4
R5
DPA_EG_DDC_CLK
DPA_EG_DDC_DATA
R2
R3
GPU_SSC_SMB_CLK
GPU_SSC_SMB_DAT
C
CRITICAL
78
L8604
78
330-OHM-1.2A
=PP3V3_GPU_IFPX_PLLVDD
1
OUT
PP3V3_GPU_IFPX_PLLVDD
2
BI
1
C8610
1
10UF
IFPX PLLVDD
2
1
C8611
20%
10V
X6S-CERM
0603
2
C8612
20%
16V
2 X6S-CERM
0201
10%
25V
X6S-CERM
0402
83
83
PLACE BELOW GPU NEAR DISPLAY SECTION
1
C8613
1
C8619
1
C8615
4.7UF
1UF
1UF
20%
10V
X6S-CERM
0603
10%
6.3V
X6S-CERM
0603
10%
25V
X6S-CERM
0402
10%
25V
X6S-CERM
0402
2
2
2
1
0.1UF
10UF
2
C8617
1
C8616
OUT
BI
DDC MAPPING
--------------------I2CA - & gt; IFPE
I2CB - & gt; IFPF
I2CC - & gt; SSC CLK GEN
C8618
0.1UF
20%
16V
2 X6S-CERM
0201
R7
R6
DPB_EG_DDC_CLK
DPB_EG_DDC_DATA
20%
16V
2 X6S-CERM
0201
I2CB_SCL
I2CB_SDA
B
=PP1V05_GPU_IFPCD_IOVDD
1
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
2
PP1V05_GPU_IFPCD_IOVDD
1
1
C8625
C8626
4.7UF
IFP CD IOVDD
2
C8627
0.1UF
1UF
20%
6.3V
X6S
0402
20%
16V
2 X6S-CERM
0201
20%
4V
CERM-X6S
0201
2
1
1
C8655
1
C8656
1UF
20%
4V
X6S-CERM
0402-1
20%
4V
CERM-X6S
0201
2
C8628
C8657
20%
16V
2 X6S-CERM
0201
1
DAC_AVDD
20%
16V
2 X6S-CERM
0201
1%
1/20W
MF
2
1%
1/20W
MF
201
2
1
C8629
1%
1/20W
MF
1%
1/20W
MF
GPU_OSC_27M_XTAL_BUFFOUT_R
IFP EF IOVDD
2
A
20%
4V
X6S-CERM
0402-1
20%
4V
CERM-X6S
0201
2
77 95
PLACE_NEAR=U8000.J4:8.4MM
PLACE_NEAR=U8000.H1:8.4MM
1
R8611
R8612
10K
SSM6N37FEAPE
SOT563
Q8600
2
HDMI_EG_DDC_CLK
10K
1%
1/20W
MF
201
1%
1/20W
MF
2 201
7 38
OUT
OMIT_TABLE
77
DDC 3.3V/5V LEVEL TRANSLATOR
HDMI_EG_DDC_CLK_Q
HDMI_EG_DDC_DATA_Q
HDMI_EG_DATA_C_P & lt; 2 & gt;
HDMI_EG_DATA_C_N & lt; 2 & gt;
HDMI_EG_DATA_C_P & lt; 1 & gt;
HDMI_EG_DATA_C_N & lt; 1 & gt;
HDMI_EG_DATA_C_P & lt; 0 & gt;
HDMI_EG_DATA_C_N & lt; 0 & gt;
HDMI_EG_CLK_C_P
HDMI_EG_CLK_C_N
U8000
NV-GK107
OUT
OUT
OUT
95
7
38
7
38
95
OUT
7
38 95
OUT
(6 OF 10)
J8
K8
L8
M8
SOT563
Q8600
HDMI_EG_DDC_DATA
=PP3V3_GPU_VDD33
78 77 71 8
79
BI 7 38
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
7 38 95
GPU_ROM_CS_L
GPU_ROM_SCLK
GPU_ROM_SI
GPU_ROM_SO
ROM_CS*
ROM_SCLK
ROM_SI
ROM_SO
MULTI_STRAP_REF
J1
MULTI_STRAP_REF0_GND
7 38 95
78
OUT
OUT
7 38 95
78
OUT
78
BI
BI
IN
78
OUT
77 82 95
PLACE_NEAR=U8000.J1:5MM
R8609
77 82 95
OUT
OUT
1
82 95
40.2K
82 95
OUT
OUT
82 95
OUT
82 95
OUT
OUT
AK11
TESTMODE
82 95
82 95
GPU_TESTMODE
82 95
OUT
2
0.1%
1/20W
MF
0201
82 95
VDD33
H6
H4
H5
H7
OUT
DP_INT_EG_ML_P & lt; 0 & gt;
DP_INT_EG_ML_N & lt; 0 & gt;
DP_INT_EG_ML_P & lt; 1 & gt;
DP_INT_EG_ML_N & lt; 1 & gt;
DP_INT_EG_ML_P & lt; 2 & gt;
DP_INT_EG_ML_N & lt; 2 & gt;
DP_INT_EG_ML_P & lt; 3 & gt;
DP_INT_EG_ML_N & lt; 3 & gt;
=PP3V3_GPU_MISC
77 8
SSM6N37FEAPE
7 38 95
OUT
DP_INT_EG_AUX_P
DP_INT_EG_AUX_N
BGA
Note: PP3v3_GPU_MISC and pp3v3_GPU_VDD33 have to be isolated from each other
95
38
7
77
79 77
PP1V05_GPU_SP_PLLVDD
BI
77 83 95
BI
77 83 95
95 78
95 78
OUT
AD8
PLLVDD
PP1V05_GPU_VID_PLLVDD
AD7
VID_PLLVDD
7 35 95
OUT
H3
H2
XTAL_IN
XTAL_OUT
J4
GPU_OSC_27M_XTALIN
GPU_OSC_27M_XTALOUT
OUT
7 35 95
OUT
GPU_OSC_27M_SSIN
7 35 95
OUT
95 77
IN
78
IN
78
IN
78
IN
78
IN
7 35 95
OUT
7 35 95
OUT
7 35 95
BI
77 83 95
BI
H1
J2
J7
J6
J5
J3
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST*
XTAL_SSIN
GPU_MLS_STRAP0
GPU_MLS_STRAP1
GPU_MLS_STRAP2
GPU_MLS_STRAP3
GPU_MLS_STRAP4
7 35 95
OUT
GPU_OSC_27M_XTAL_BUFFOUT_R
77
GPU_GPIO_0
GPU_GPIO_1
GPU_GPIO_2
GPU_GPIO_3
GPU_GPIO_4
GPU_GPIO_5
GPU_GPIO_6
GPU_GPIO_7
GPU_GPIO_8
GPU_GPIO_9
GPU_GPIO_10
GPU_GPIO_11
GPU_GPIO_12
GPU_GPIO_13
GPU_GPIO_14
GPU_GPIO_15
GPU_GPIO_16
GPU_GPIO_17
GPU_GPIO_18
GPU_GPIO_19
GPU_GPIO_20
GPU_GPIO_21
AM10
AM11
AP12
AP11
AN11
GPU_JTAG_TCK
IN
GPU_JTAG_TDI
IN
GPU_JTAG_TDO
OUT
GPU_JTAG_TMS
IN
GPU_JTAG_TRST_L IN
BI
OUT
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
THERMDP K3
THERMDN K4
BI
7 35 95
OUT
7 35 95
OUT
7 35 95
78
BI
78
BI
78
BI
78
BI
78
BI
78
BI
78
BI
78
BI
78
BI
78
BI
78
BI
78
BI
78
BI
78
BI
78
BI
78
78
78
78
78
78
IN
B
47 96
OUT
47 96
GPU PLL VDD
L8607
FERR-220-OHM-2A
79 8
=PP1V05_GPU_PEX_PLLVDD
AG10
DACA_VDD
NC
NC
AP9
AP8
DACA_VREF
DACA_RSET
DACA_RED AK9
DACA_GREEN AL10
DACA_BLUE AL9
1
MIN_LINE_WIDTH=0.41 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
2
DACA_HSYNC AM9
DACA_VSYNC AN9
CRITICAL
ESR = 0.05OHM
NC
NC
NC
1
C8651
1
C8652
20UF
2
NC
NC
PP1V05_GPU_PLLVDD
77
1UF
20%
2V
X6T-CERM
0402
20%
4V
CERM-X6S
0201
2
1
C8653
0.1UF
20%
16V
2 X6S-CERM
0201
1
C8654
0.1UF
20%
16V
2 X6S-CERM
0201
GPU 3V3 VDD
=PP3V3_GPU_VDD33
PP1V05_GPU_IFPEF_IOVDD
77
C8631
20%
16V
2 X6S-CERM
0201
1
C8632
CEC L3
0.1UF
C8640
1
10UF
NC
2
20%
16V
2 X6S-CERM
0201
20%
10V
X6S-CERM
0603
C8641
1
1UF
2
10%
25V
X6S-CERM
0402
C8642
1
10%
25V
X6S-CERM
0402
C8643
0.1UF
1UF
2
20%
16V
2 X6S-CERM
0201
1
C8644
0.1UF
20%
2 16V
X6S-CERM
0201
SYNC_MASTER=D2_SEAN
=PP3V3_GPU_MISC
SYNC_DATE=03/05/2012
PAGE TITLE
77 8
KEPLER EDP/DP/GPIO
DRAWING NUMBER
1
1
C8633
1
4.7UF
2
8
20%
6.3V
X6S
0402
C8634
1
4.7UF
2
20%
6.3V
X6S
0402
C8635
1
1UF
2
20%
4V
CERM-X6S
0201
7
C8636
1UF
2
C
7 35 95
OUT
78
BI
GPU_TDIODE_P
GPU_TDIODE_N
7 35 95
OUT
78
7 35 95
OUT
78
BI
7 35 95
OUT
78
BI
7 35 95
OUT
IN
78
BI
77 83 95
78
78
BI
XTAL_OUTBUFF
7 35 95
OUT
IN
SP_PLLVDD
PP1V05_GPU_PLLVDD
77
77
AE8
P6
M3
L6
P5
P7
L7
M7
N8
M1
M2
L1
M5
N3
M4
N4
P2
R8
M6
R1
P3
P4
P1
79 78 77 71 8
0.1UF
1UF
GPU_OSC_27M_SSIN
77
1
79 78 77 71 8
77
AM1
AM2
AM3
AM4
AL3
AL4
AK4
AK5
77
2 201
=PP3V3_GPU_VDD33
AK1
AJ1
AJ3
AJ2
AH3
AH4
AG5
AG4
PP1V05_GPU_VID_PLLVDD
MAKE_BASE=TRUE
2 201
1
C8630
10UF
PP1V05_GPU_SP_PLLVDD
R8626
1
1
1%
1/20W
MF
2 201
1
0603
CRITICAL
ESR = 0.05OHM
1K
0603
0.1UF
L8606
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
R8607
1K
4.7K
2 201
NC
NC
NC
NC
NC
NC
NC
NC
C8658
10K
1
4.7K
DP_TBTSNK1_ML_C_P & lt; 0 & gt;
DP_TBTSNK1_ML_C_N & lt; 0 & gt;
DP_TBTSNK1_ML_C_P & lt; 1 & gt;
DP_TBTSNK1_ML_C_N & lt; 1 & gt;
DP_TBTSNK1_ML_C_P & lt; 2 & gt;
DP_TBTSNK1_ML_C_N & lt; 2 & gt;
DP_TBTSNK1_ML_C_P & lt; 3 & gt;
DP_TBTSNK1_ML_C_N & lt; 3 & gt;
IFPF_L0
IFPF_L0*
IFPF_L1
IFPF_L1*
IFPF_L2
IFPF_L2*
IFPF_L3
IFPF_L3*
R8600
=PP1V05_GPU_IFPEF_IOVDD
R8625
AE3
AE4
AF4
AF5
AD4
AD5
AG1
AF1
0.1UF
R8606
1%
1/20W
MF
201
- D2:YES
79 77
1
DP_TBTSNK1_EG_AUXCH_P
DP_TBTSNK1_EG_AUXCH_N
1
FERR-220-OHM-2A
2
DP_TBTSNK0_ML_C_P & lt; 0 & gt;
DP_TBTSNK0_ML_C_N & lt; 0 & gt;
DP_TBTSNK0_ML_C_P & lt; 1 & gt;
DP_TBTSNK0_ML_C_N & lt; 1 & gt;
DP_TBTSNK0_ML_C_P & lt; 2 & gt;
DP_TBTSNK0_ML_C_N & lt; 2 & gt;
DP_TBTSNK0_ML_C_P & lt; 3 & gt;
DP_TBTSNK0_ML_C_N & lt; 3 & gt;
20%
16V
2 X6S-CERM
0201
0.1UF
10UF
2
1
1
1
1K
IFPF_AUX_I2CZ_SCL AF3
IFPF_AUX_I2CZ_SDA* AF2
0603
CRITICAL
ESR = 0.05OHM
PLACE_NEAR=U8000.AD6:5MM
1
R8621
=PP3V3_GPU_VDD33
79
71 8
78 77
AD2
AD3
AD1
AC1
AC2
AC3
AC4
AC5
77
D
BOM options provided by this page:
77
- J31:YES
DP_TBTSNK0_EG_AUXCH_P
DP_TBTSNK0_EG_AUXCH_N
IFPE_L0
IFPE_L0*
IFPE_L1
IFPE_L1*
IFPE_L2
IFPE_L2*
IFPE_L3
IFPE_L3*
IFPEF_RSET
77
PLACE_NEAR=U8000.AN2:5MM
IFPE_AUX_I2CY_SCL AB3
IFPE_AUX_I2CY_SDA* AB4
L8605
FERR-220-OHM-2A
IFPD_L0
IFPD_L0*
IFPD_L1
IFPD_L1*
IFPD_L2
IFPD_L2*
IFPD_L3
IFPD_L3*
IFPD_RSET
77
1
NC
NC
IFPD_AUX_I2CX_SCL AK3
IFPD_AUX_I2CX_SDA* AK2
0.1UF
1UF
AG3
AG2
NC
NC
NC
NC
NC
NC
NC
NC
77
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
0603
1
T4
T3
GPU_SMB_CLK
GPU_SMB_DAT
IFPC_AUX_I2CW_SCL
IFPC_AUX_I2CW_SDA*
I2CC_SCL
IFPC_L0
I2CC_SDA
IFPC_L0*
IFPC_L1
IFPC_L1*
IFPC_L2
IFPC_L2*
I2CS_SCL
I2CS_SDA
IFPC_L3
IFPC_L3*
IFPC_RSET
PLACE_NEAR=U8000.AF8:5MM
D
1
77
NC
NC
3
77
(NONE)
PD FOR RSET
D
77
77
HDMI_EG_DDC_CLK_Q
HDMI_EG_DDC_DATA_Q
- =PP1V05_GPU_DPLL
Signal aliases required by this page:
(5 OF 10)
IFPA_IOVDD
IFPA_TXC AM6
IFPB_IOVDD
IFPA_TXC* AN6
IFPC_IOVDD
IFPA_TXD0 AP3
IFPD_IOVDD
IFPA_TXD0* AN3
IFPE_IOVDD
IFPA_TXD1 AN5
IFPF_IOVDD
IFPA_TXD1* AM5
IFPAB_PLLVDD
IFPA_TXD2 AL6
IFPAB_RSET
IFPA_TXD2* AK6
IFPA_TXD3 AJ6
IFPC_PLLVDD
IFPA_TXD3* AH6
IFPC_RSET
IFPB_TXC AJ9
IFPD_PLLVDD
IFPB_TXC* AH9
IFPD_RSET
IFPB_TXD4 AP6
IFPEF_PLLVDD
IFPB_TXD4* AP5
IFPEF_RSET
IFPB_TXD5 AM7
IFPB_TXD5* AL7
IFPB_TXD6 AN8
I2CA_SCL
IFPB_TXD6* AM8
I2CA_SDA
IFPB_TXD7 AK8
IFPB_TXD7* AL8
6
DP_TBTSNK1_EG_AUXCH_P
DP_TBTSNK1_EG_AUXCH_N
95 83 77
AG8
AG9
AF6
AG6
AC7
AC8
5
PP1V8_GPU_IFPA_IOVDD
PP3V3_GPU_IFPB_IOVDD
PP1V05_GPU_IFPCD_IOVDD
PP1V05_GPU_IFPCD_IOVDD
PP1V05_GPU_IFPEF_IOVDD
PP1V05_GPU_IFPEF_IOVDD
77
G
2
2
- =PP1V05_GPU_IFPEF_IOVDD
- =PP3V3_GPU_VDD33
- =PP3V3_GPU_IFPX_PLLVDD
S
2
100K
1%
1/20W
MF
83 77
95
201
2
BGA
R8616
1%
1/20W
MF
201
2
U8000
1
100K
D
2
- =PP1V05_GPU_IFPCD_IOVDD
- =PP1V8_GPU_IFPA_IOVDD
- =PP1V8_GPU_DPLL
NV-GK107
4
R8615
2
1%
1/20W
MF
201
2
77 83 95
2
1
R8613
- =PP3V3_GPU_IFPB_IOVDD
10K
1%
1/20W
MF
201
G
77 83 95
10K
1%
1/20W
MF
201
S
DP_TBTSNK0_EG_AUXCH_P
DP_TBTSNK0_EG_AUXCH_N
1
R8614
10K
1%
1/20W
MF
201
OMIT_TABLE
CRITICAL
1
1
Page Notes
77
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
1
1
20%
4V
CERM-X6S
0201
1
C8637
0.1UF
20%
16V
2 X6S-CERM
0201
1
C8645
1
C8646
4.7UF
C8638
2
0.1UF
20%
16V
2 X6S-CERM
0201
4.7UF
20%
6.3V
X6S
0402
20%
6.3V
X6S
0402
2
1
C8649
0.1UF
20%
16V
2 X6S-CERM
0201
1
C8650
Apple Inc.
0.1UF
20%
16V
2 X6S-CERM
0201
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
6
5
4
3
051-9589
2
SIZE
D
REVISION
4.18.0
BRANCH
PAGE
86 OF 132
SHEET
77 OF 99
1
A
8
7
6
5
4
2
3
1
GPU internal Temp isolation
Unused signals
=PP3V3_GPU_VDD33
Native Func
GFXIMVP_PSI_R_L
GPU_GPIO_3
GP
77
EG_LCD_PWR_EN
GPU_GPIO_14
GPU_GPIO_15
GP
77
GP
80
77
GPU_GPIO_16
77
GPU_GPIO_17
GP
78 82
GP
77
GPU_GPIO_2
77
80
GPU_GPIO_1
GP
77
GFXIMVP_VID & lt; 4 & gt;
GP
80
GPU_GPIO_0
GP
77
DP_EXTA_CA_DET_EG
DP_EXTB_CA_DET_EG
GPU_SMB_DAT
1
BI
GPU_GPIO_4
GPU_GPIO_5
GP
77
GPU_GPIO_6
GP
GFXIMVP_VID & lt; 2 & gt;
GPU_GPIO_7
GP
77
FB_CLAMP_TOGGLE_REQ_L
GPU_GPIO_8
GP
77
EG_BKLT_EN
78 82
77
GPU_GPIO_18
GPU_GPIO_19
GP
NC_GPU_GPIO_20_RSVD
NC_GPU_GPIO_21_RSVD
DP_TBTSNK0_HPD_EG
80
77
82
77
GPU_GPIO_20
77
GPU_GPIO_21
GP
78 82
Note: PU to non GPU_S0 3v3 source
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NOSTUFF
NO_TEST=TRUE
MAKE_BASE=TRUE
=PP3V3_GPU_VDD33
NO_TEST=TRUE
GPU_GPIO_12
77
GPU_GPIO_13
5%
1/20W
MF
201 2
D
FB_CLAMP_TOGGLE_REQ_L
82 78
SOT563
78
73
MAKE_BASE=TRUE
77
GFXIMVP_VID & lt; 0 & gt;
GPU_SMB_CLK
OUT
4
80
D
77
1
10K
5%
1/20W
MF
201 2
5% 1/20W MF 201
GPU_ALT_VREF
GP
2
10K
5%
1/20W
MF
201
GPU_SMB_CLK_R
3
GPU_GPIO_11
2
10K
G
1
S
GPU_GPIO_10
77
=PP3V3_S0_DPMUX_UC
82 35 8
SSM6N37FEAPE
R8754 10K
78
MAKE_BASE=TRUE
77
NOSTUFF
R87511 R87581
R8753
Q8702
79 78 77 71 8
MAKE_BASE=TRUE
SMC_GFX_THROTTLE_R_L
GPU_JTAG_TRST_L
GC6 SUPPORT
5% 1/20W MF 201
5
80
SMC_GFX_OVERTEMP_R_L
GP
77
44
MAKE_BASE=TRUE
GP
MAKE_BASE=TRUE
77
BI
R8780
0 2
1
82
DP_TBTSNK1_HPD_EG
MAKE_BASE=TRUE
GP
GPU_SMB_DAT_R
NOSTUFF
MAKE_BASE=TRUE
GFXIMVP_VID & lt; 1 & gt;
77
GPU_JTAG_TMS
82
GP
MAKE_BASE=TRUE
GPU_GPIO_9
D
77
6
74 78
DP_INT_EG_HPD
MAKE_BASE=TRUE
GP
77
GPU_JTAG_TDO
TP_GPU_JTAG_TDO
MAKE_BASE=TRUE
77
MAKE_BASE=TRUE
MAKE_BASE=TRUE
D
SOT563
MAKE_BASE=TRUE
FBVDD_ALTVO
MAKE_BASE=TRUE
77
2
5% 1/20W MF 201
82
77
GPU_JTAG_TDI
TP_GPU_JTAG_TDI
MAKE_BASE=TRUE
S
MAKE_BASE=TRUE
77
1
MAKE_BASE=TRUE
GFXIMVP_VID & lt; 3 & gt;
GPU_JTAG_TCK
MAKE_BASE=TRUE
SSM6N37FEAPE
G
MAKE_BASE=TRUE
R8755 10K
82
TP_GPU_JTAG_TCK
Q8702
79 78 77 71 8
GPIOs
2
GPIOs
Native Func
IN
44
MAKE_BASE=TRUE
HDMI_EG_HPD
GP
82
MAKE_BASE=TRUE
GP
GFXIMVP_VID & lt; 5 & gt;
80
MAKE_BASE=TRUE
71
GP
PEX_CLKREQ_L_R
R8795
0
1
5%
PART NUMBER
QTY
1
EG_CLKREQ_IN_L
2
1/20W
MF
OUT
201
DESCRIPTION
R8781
0 2
9 82
5% 1/20W MF 201
NOSTUFF
REFERENCE DES
CRITICAL
BOM OPTION
Die Rev
Strap
118S0013
1
RES, 10KOHM, 0201
R8711
FB_2G_SAMSUNG
D-DIE
0x1
118S0414
1
RES,5.1KOHM, 0201
R8711
FB_2G_HYNIX_M_DIE
M-DIE
0x0
118S0230
1
RES,MF,24.9KOHM,1,1/20W,0201
R8711
FB_2G_HYNIX_A_DIE
A-DIE
0x4
CONFIG STRAPS - MLPS
=PP3V3_GPU_VDD33
=PP3V3_GPU_VDD33
77 71 8
79 78
79 78 77 71 8
NOSTUFF
1
1
R8700
R8708
45.3K
3.24K
1%
1%
1/20W
MF
1/20W
2
MF
201
2 201
OUT
C
77
OUT
GPU_MLS_STRAP0
77
C
GPU_MLS_STRAP4
1
1
R8701
R8709
5.62K
2
Straps for GK107. GF108 support has been removed.
GPU GC6 ROM
45.3K
1%
1/20W
MF
201
1%
1/20W
2
79 78 77 71 8
=PP3V3_GPU_VDD33
MF
201
GPU_ROM:YES
NOSTUFF
GPU_ROM_SI
77
78
=PP3V3_GPU_VDD33
33
GPU_ROM:YES
79 78 77 71 8
NOSTUFF
R8710
3.24K
GPU_ROM_SI_R
3.24K
1%
1/20W
MF
201
1%
1/20W
MF
201
2
OUT
R8726
GPU_ROM_SO
77
78
77
OUT
77 78
1
33
1
GPU_ROM:YES
GPU_ROM_SO_R
2
5%
1/20W
MF
201
GPU_ROM_SI
GPU_MLS_STRAP1
USON
SCLK
MX25L1005CMI-12G
CRITICAL
CS*
2 SO
WP*
HOLD*
5 SI
THRM
PAD
9
1
R8703
R8711
45.3K
R8724
6
GPU_ROM_SCLK_R
MF
201
2
GPU_ROM_SCLK
33
1
2
77 78
201 5%1/20W MF
1
GPU_ROM_CS_L_R
3
1
NO STUFF
GND
4
GPU_ROM:YES
R8725
GPU_ROM_WP_L
7
1
33
5%
1/20W
MF
201
2
GPU_ROM_CS_L
77
GPU_ROM:YES
R8722
0
1%
1/20W
MF
201
1/20W
10%
6.3V
X6S
0201
2
25.5K
1%
2
2
1MBIT
1
R8702
2
U8701
NOSTUFF
1
2
VCC
5%
1/20W
MF
201
=PP3V3_GPU_VDD33
77 71 8
79 78
5%
1/20W
MF
201
C8721
0.1UF
0
5%
1/20W
MF
201
OMIT_TABLE 8
2
1
R8721 1
10K
1
GPU_ROM:YES
GPU_ROM:YES
R8720 1
R8723
2
5%
1/20W
MF
201
GPU XTAL 27 MHZ
GPU_OSC_27M_XTALIN
GPU_OSC_27M_XTALOUT
OMIT_TABLE
CRITICAL
STRAP NOTES:
=PP3V3_GPU_VDD33
CURRENTLY STUFFED FOR GF108a/GK107-GTX
STUFF R8704 FOR THICK DIE
STUFF R8705 FOR THIN DIE
=PP3V3_GPU_VDD33
77 71 8
79 78
79 78 77 71 8
NOSTUFF
1
1
R8704
2
10K
1%
1/20W
MF
201
1%
1/20W
MF
201
2
79 78 77 71 8
42 41 8
=PP3V3_GPU_VDD33
79 78 77 71 8
OUT
77
OUT
GPU_MLS_STRAP2
1
10K
1%
1/20W
MF
2 201
2
5%
1/20W
MF
201
1%
1/20W
MF
201
0
79 78 77 71 8
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.1 MM
PP3V3_GPU_OVERTEMP
R8796 1
10K
5%
1/20W
MF
201
U8702
5%
1/20W
MF
201
2
SOT891
2
78
1
R8797 1
10K
2
D 3
5%
25V
NP0-C0G-CERM
0201
=PP3V3_GPU_VDD33
5%
1/20W
MF
2 201
4
=PP3V3_GPU_VDD33
C8701
18PF
2
R8757
6 74LVC1G08
=PP3V3_GPU_VDD33
1
5%
25V
NP0-C0G-CERM
0201
NOSTUFF
SMC_GFX_OVERTEMP_Q
Q8701
SSM3K15FV
4
1
5%
1/20W
MF
201 2
R87521
10K
C8700
18PF
2
0
R8713
30K
1
=PP3V3_GPU_VDD33
=PP3V3_S5_SMC
GPU_ROM_SO
R8705
08
OUT
2
NO STUFF
SMC_GFX_OVERTEMP_R_L
R8798
0
1
2
SMC_GFX_THROTTLE_R_L
R8799
0
1
2
SMC_GFX_OVERTEMP
5%
78
41
42
78
SMC_GFX_OVERTEMP
1/20W
MF
OUT
201
SMC_GFX_THROTTLE_L
5%
1/20W
MF
201
1
A
24.9K
OUT
R8707
5.62K
1%
1/20W
MF
2 201
G
S 2
NC
NO STUFF
R87921
77
GPU_MLS_STRAP3
1
1
1%
1/20W
MF
2 201
1%
1/20W
MF
201
OUT
GPU_ROM_SCLK
NOSTUFF
R87931
10K
78
SMC_GFX_OVERTEMP_R_L
10K
5%
1/20W
MF
201
77 78
5%
1/20W
MF
201
2
R87941
R87901
10K
2
10K
5%
1/20W
MF
201
5%
1/20W
MF
201
2
R8791
5%
1/20W
MF
201
OUT
78 82
OUT
74 78
SYNC_MASTER=D2_SEAN
KEPLER GPIOS,CLK & STRAPS
DRAWING NUMBER
Apple Inc.
2
R8715
NOTICE OF PROPRIETARY PROPERTY:
GPU_RESET_L
IN
7
051-9589
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
6
5
4
3
2
SIZE
D
REVISION
R
34.8K
1%
1/20W
MF
2 201
SYNC_DATE=03/05/2012
PAGE TITLE
10K
2
78 82
1
NOSTUFF
8
NOSTUFF1
OUT
FBVDD_ALTVO
R8714
20K
2
EG_LCD_PWR_EN
3
1
R8706
41
NC
5
SOD-VESM-HF
79 78 77 71 8
41 42 78
BI
EG_BKLT_EN
77 71 8
79 78
B
3
2
R87561
77 78
NOSTUFF
1
1
77 95
27MHZ-30PPM-18PF-60OHM
GPU overtemp masking
R8712
15K
77 95
IN
Y8700
2.50X2.00MM-SM
NC
NC
B
OUT
4.18.0
BRANCH
PAGE
87 OF 132
SHEET
78 OF 99
1
A
8
7
6
5
4
3
2
1
Page Notes
Power aliases required by this page:
L8804
OMIT_TABLE
FERR-220-OHM-2A
U8000
=PP1V05_GPU_PEX_IOVDD
NV-GK107
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
D
72 8
P8
AC6
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
AJ28
AJ4
AJ5
AL11
C15
D19
D20
D23
D26
H31
T8
V32
AG22
AG24
2
SM
1
AH21
1
C8830
1
C8831
1
C8832
C8833
4.7UF
1UF
1UF
20%
2V
X6T-CERM
0402
20%
6.3V
X6S
0402
20%
4V
CERM-X6S
0201
20%
4V
CERM-X6S
0201
2
2
2
1
C8834
0.1UF
20%
16V
2 X6S-CERM
0201
1
C8835
0.1UF
20%
16V
2 X6S-CERM
0201
1
C8836
0.1UF
20%
16V
2 X6S-CERM
0201
AG11
A2
A33
AA13
AA15
AA17
AA18
AA20
AA22
AB12
AB14
AB16
AB19
AB2
AB21
AB23
AB28
AB30
AB32
AB5
AB7
AC13
AC15
AC17
AC18
AC20
AC22
AE2
AE28
AE30
AE32
AE33
AE5
AE7
AH10
AH13
AH16
AH19
AH2
AH22
AH24
AH28
AH29
AH30
AH32
AH33
AH5
AH7
AJ7
AK10
AH15
AH18
AH26
AH27
AJ27
AK27
AL27
AM28
AN28
R8803
0
1
C8826
1
C8827
4.7UF
20%
6.3V
X6S
0402
20%
6.3V
X6S
0402
2
C8828
8 77 79
0.1UF
1UF
2
=PP1V05_GPU_PEX_PLLVDD
2
5%
1/10W
MF-LF
1 C8829 603
20%
4V
CERM-X6S
0201
10%
2 6.3V
X6S
0201
XW8802
SM
1
2
GND_GPU_PEX_PLLVDD
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=0V
VDD_SENSE
PEX_PLLVDD AG26
MIN_LINE_WIDTH=0.8 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
GND_SENSE
PEX_PLL_HVDD AH12
1
C8822
4.7UF
1
R8800
100
2
10K
5%
1/20W
MF
2 201
R8802
PP3V3_GPU_PEX_PLL_HVDD
71
1%
1/20W
MF
2 201
C8823
1
4.7UF
20%
6.3V
X6S
0402
2
20%
6.3V
X6S
0402
0
1
BUFRST*
1
R8811
C8824
1UF
2
20%
4V
CERM-X6S
0201
1
=PP3V3_GPU_VDD33
2
8 71 77 78
5%
1/16W
MF-LF
402
C8825
0.1UF
10%
6.3V
2 X6S
0201
XW8803
SM
1
GND_GPU_PEX_PLL_HVDD
XW8804
2
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=0V
PLACE XW8800 & XW8804 CLOSE TO C8803
SM
1
P1V05_GPU_PEX_IOVDD_SNS_P
2
74 97
OUT
PLACE_NEAR=C8803.1:2MM
=PP1V05_GPU_PEX_IOVDD
B
EDP = 2000 MA
79 73 8
1
1
C8803
20UF
2
C8804
1
20UF
20%
2V
X6T-CERM
0402
2
20%
2V
X6T-CERM
0402
1
C8805
4.7UF
2
(9 OF 10)
(8 OF 10)
AG18
AG25
GPUVCORE_SENSE_P
1
BGA
BGA
2
GPU_BUFRSTN L2
U8000
NV-GK107
NV-GK107
AG16
GND_OPT
GND_OPT
GPUVCORE_SENSE_N
OMIT_TABLE
OMIT_TABLE
1
C8800
1
20UF
20%
6.3V
X6S
0402
D
(NONE)
U8000
4.7UF
OUT
Signal aliases required by this page:
(NONE)
GND_GPU_SP_PLLVDD
AG13
AG15
PP1V05_GPU_PEX_PLLVDD
L5
0.1UF
20%
16V
2 X6S-CERM
0201
8 73 79
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
1
97 80
C8837
BOM options provided by this page:
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=0V
5%
1/20W
MF
2 201
L4
1
2
AH25
100
W32
1
XW8801
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
C16
77
0603
CRITICAL
ESR = 0.05OHM
20UF
R8810
OUT
2
- =PP3V3_GPU_VDD33
- =PP1V05_GPU_PEX_IOVDD
- =PP1V05_GPU_PEX_PLLVDD
PP1V05_GPU_SP_PLLVDD
=PP1V05_GPU_PEX_IOVDD
=PPVCORE_GPU
C
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=1.05V
AG19
AG21
1
97 80
1
77
79
8 73 79
BGA
(2 OF 10)
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
=PP1V05_GPU_PEX_PLLVDD
8
GPU SP PLLVDD
2
20%
2V
X6T-CERM
0402
C8801
1
20UF
C8802
4.7UF
2
20%
2V
X6T-CERM
0402
2
1
C8813
1
20%
6.3V
X6S
0402
GND
C7
D2
D31
D33
E10
E22
E25
E5
E7
F28
F7
G10
G13
G16
G19
G2
G22
G25
G28
G3
G30
G32
G33
G5
G7
K2
K28
K30
K32
K33
K5
K7
M13
M15
M17
M18
M20
M22
N12
N14
N16
N19
N2
N21
N23
N28
N30
N32
N33
N5
AK7
AL12
AL14
AL15
AL17
AL18
AL2
AL20
AL21
AL23
AL24
AL26
AL28
AL30
AL32
AL33
AL5
AM13
AM16
AM19
AM22
AM25
AN1
AN10
AN13
AN16
AN19
AN22
AN25
AN30
AN34
AN4
AN7
AP2
AP33
B1
B10
B22
B25
B28
B31
B34
B4
B7
C10
C13
C19
C22
C25
C28
GND
N7
P13
P15
P17
P18
P20
P22
R12
R14
R16
R19
R21
R23
T13
T15
T17
T18
T2
T20
T22
T28
T32
T5
T7
U12
U14
U16
U19
U21
U23
V12
V14
V16
V19
V21
V23
W13
W15
W17
W18
W20
W22
W28
Y12
Y14
Y16
Y19
Y21
Y23
AH11
C
B
XW8800
SM
1
2
P1V05_GPU_PEX_IOVDD_SNS_N
OUT
74 97
PLACE_NEAR=C8803.2:2MM
1
C8815
1
C8816
1
C8817
1
C8818
PEX IOVDD & PEX IOVDDQ
1
C8812
2
1
C8814
10UF
1UF
0.1UF
100PF
10UF
1UF
0.1UF
20%
4V
X6S-CERM
0402-1
20%
4V
CERM-X6S
0201
10%
6.3V
X6S
0201
5%
25V
NP0-CERM
0201
20%
4V
X6S-CERM
0402-1
20%
4V
CERM-X6S
0201
10%
6.3V
X6S
0201
2
2
2
2
2
2
C8821
100PF
2
5%
25V
NP0-CERM
0201
A
SYNC_MASTER=D2_SEAN
SYNC_DATE=03/05/2012
PAGE TITLE
1
1
C8809
1
C8810
1
C8811
1
C8819
10UF
2
1UF
0.1UF
20%
4V
CERM-X6S
0201
10%
6.3V
X6S
0201
5%
25V
NP0-CERM
0201
2
2
2
C8806
1
C8807
1
2
1
C8808
10UF
100PF
20%
4V
X6S-CERM
0402-1
1UF
0.1UF
20%
4V
X6S-CERM
0402-1
20%
4V
CERM-X6S
0201
10%
6.3V
X6S
0201
2
2
KEPLER PEX PWR/GNDS
C8820
DRAWING NUMBER
100PF
2
5%
25V
NP0-CERM
0201
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
051-9589
3
2
SIZE
D
REVISION
4.18.0
BRANCH
PAGE
88 OF 132
SHEET
79 OF 99
1
A
8
7
6
80 8
5
4
2
3
=PPVIN_S0_GFXIMVP
C8928
OMIT_TABLE
CRITICAL
1
C8927 1
1
0.001UF
R8900
10%
50V
X7R-CERM 2
0402
1
5%
1/20W
MF
2 201
1UF
10%
25V
X6S-CERM 2
0402
R8901
1
1
2
5%
1/20W
MF
201
GFXIMVP_BOOT2_R
10
1
R8930
PP5V_S0_GFXIMVP_VDD
PLACE_NEAR=Q8900.17:1mm
1
1
1
1UF
NCNC
C8900
D
4
U8900
80 78
IN
80 78
IN
80 78
IN
GFXIMVP_DPSLP_EN
IN
80 78
5%
50V
NP0-C0G-CERM 2
0201
1%
1/20W
MF
201 2
GFXIMVP_PSI_L
80 78
22PF
8.06K
GFXIMVP_VID & lt; 0 & gt;
GFXIMVP_VID & lt; 1 & gt;
GFXIMVP_VID & lt; 2 & gt;
GFXIMVP_VID & lt; 3 & gt;
GFXIMVP_VID & lt; 4 & gt;
GFXIMVP_VID & lt; 5 & gt;
GFXIMVP_VID & lt; 6 & gt;
80
C8918
R89131
1
10%
16V
2 X7R-CERM
0201
IN
80 78
IN
1
R8916
49.9
SIGNAL_MODEL=EMPTY
1
R8915
1%
1/20W
MF
2 201
88
1
1%
1/20W
MF
201 2
NOSTUFF
IN
97 79
GPUVCORE_SENSE_P
IN
97 79
GFXIMVP_ISEN2
BOOT1 19
GFXIMVP_BOOT1
1%
1/20W
MF
2 201
C8915
GFXIMVP_FB_GND_R
1
1000PF
NOSTUFF
10%
16V
X7R-CERM 2
0201
C8941
5600PF
3
5
6
NCNC
D
OUT
GFXIMVP6_IMON
4
SWITCH_NODE=TRUE
1
C8914
1
PLACE_NEAR=Q8961.3:1mm
MIN_LINE_WIDTH=0.6MM
XW8931
NC MIN_NECK_WIDTH=0.2MM
VOLTAGE=0V
ISEN1 11
ISUM+ 15
2
R8912
1000PF
10%
2 16V
X7R-CERM
0201
C8913
2
PLACE_NEAR=U8900.41:1mm
C8912
1%
1/20W
MF
201
1
0.1UF
1
10%
6.3V
X6S 2
0201
10%
2 6.3V
X6S
0201
1%
1/20W
MF
201 2
10%
10V
2 CERM
201
PPVCORE_S0_GFX_PH1
PIMB063T-SM
80 97
1%
1W
MF
0612
97
1
3
GFXIMVP_ISNS1_P
2
4
97 80
GFXIMVP_ISNS1_N
CRITICAL
Q8961
1
1
1%
1/20W
MF
201 2
1
1%
1/20W
MF
201 2
R8961 R8963
10K
DIRECTFET_S3C
376S1011
R8964
1K
1.00
1%
1/20W
MF
2 201
GFXIMVP_ISUMN
GFXIMVP_ISUMP
80
80
C8966
1
0.22UF
R89621
1
1%
1/20W
MF
201 2
C8910
10%
2 10V
CERM
201
R8910
NOSTUFF
XW8900
0.1UF
10K
2
2
GFXIMVP_ISUMN
80
B
C8911
1
1
10%
6.3V
2 X6S
0201
0.1UF
1.15K2
1%
1/20W
MF
201
GND_GFXIMVP_AGND
80 97
NOSTUFF
R8911
GFXIMVP_ISUMP_C
20%
6.3V
X6S-CERM
0201
GFXIMVP_ISNS2_N
5600PF
GFXIMVP_ISUMN_R
1.24K2
1
SM
80
10K
1
SIGNAL_MODEL=EMPTY
80
R8999
GFXIMVP_ISUMP
14
270UF
0.00075
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.05V
GFXIMVP_ISEN1
ISUM-
C8964
20%
2V
2 TANT
CASE-B2-SM
20%
2 2V
TANT
CASE-B2-SM
2
GFXIMVP_ISNS1_N
8 80
SM
GFXIMVP_VSSP1
THRM
PAD
1
G
GATE_NODE=TRUE
VSSP1 22
18 IMON
270UF
20%
6.3V
X6S-CERM
0201
GFXIMVP_LGATE1
12 VSEN
1
C8963
C
649135PBF
GFXIMVP_PHASE1
9 FB2
8 FB
SIGNAL_MODEL=EMPTY
SIGNAL_MODEL=EMPTY
SIGNAL_MODEL=EMPTY
R8960
13 RTN
45
49.9
1
GATE_NODE=TRUE
PHASE1 21
LGATE1B 24
1
1%
1/20W
MF
2 201
1
CRITICAL
L8960
1
GFXIMVP_UGATE1
7 COMP
20%
2 2V
TANT
CASE-B2-SM
IRF6802SDTRPBF
0.2UH-20%-24A-0.003OHM
5%
1/10W
MF-LF
2 603
38 VR_ON
GPUVCORE_SENSE_N
10%
16V
CERM 2
402
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=0V
UGATE1 20
80
R8917
1
ISEN2 10
LGATE1A 23
270UF
Q8930
0
6 VW
C8962
DIRECTFET-SA
0.22UF
GFXIMVP_VSSP2
39 DPRSLPVR
CKPLUS_WAIVE=PdifPr_badTerm
1
B
LGATE2 26
VSSP2 27
1.00
S
C8965 1
GFXIMVP_LGATE2
VID0
VID1
VID2
VID3
VID4
VID5
VID6
GFXIMVP_FB2
GFXIMVP_FB
3300PF
10%
10V
2 X7R
201
1 G
GFXIMVP_BOOT1_R
GFXIMVP_COMP
C8940
D
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
DIDT=TRUE
GATE_NODE=TRUE
GFXIMVP_VW
GFXIMVP_FB_SNS_R
=PPVIN_S0_GFXIMVP
SWITCH_NODE=TRUE
2 PSI*
=GPUVCORE_EN
IN
SIGNAL_MODEL=EMPTY
301
31
32
33
34
35
36
37
R8934
1
CRITICAL
10K
1%
1/20W
MF
201 2
GFXIMVP_PHASE2
80
NOSTUFF
GFXIMVP_COMP_R
1
20%
2V
2 TANT
CASE-B2-SM
CRITICAL
0.22UF
R89321
GFXIMVP_UGATE2
PHASE2 28
80
1%
1/20W
MF
2 201
270UF
1
1K
C8961
CRITICAL
C8931
4
C8919
1000PF
5.11K
10%
16V
2 X7R-CERM
0201
1%
1/20W
MF
201 2
10K
1
2
8
7
330PF
10%
50V
X7R-CERM 2
0201
1%
1/20W
MF
201 2
=PPVCORE_S0_GFX_REG
5
6
UGATE2 29
4 VR_TT*
40 CLK_EN*
1
GFXIMVP_ISNS2_N
3
5
6
R8914
1
R8931 R8933
1
GATE_NODE=TRUE
1 PGOOD
1
20%
16V 2
TANT
SM
GFXIMVP_BOOT2
GFXIMVP_VR_TT_L
41
560PF
C8917
CRITICAL
GFXIMVP_ISUMN
GFXIMVP_ISUMP
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
DIDT=TRUE
BOOT2 30
GPUVCORE_PGOOD
OUT
80
1
5 NTC
15UF
8
97 80
1
376S1011
S
88
C
TQFN
3 RBIAS 353S3679
GFXIMVP_NTC
1%
1/20W
MF
201
10%
25V
X6S-CERM 2
0402
25A max per phase
1
3
GFXIMVP_ISNS2_P
ISL62882C
GFXIMVP_RBIAS
30.1K
2
1
1
97
Line Width & DIDT
on all DIDT nets
VDD VCCP VIN
R8918
C8916
2
2
4
PIMB063T-SM
SM
17
16
1%
1/20W
MF
201
25
XW8930
1%
1W
MF
0612
PPVCORE_S0_GFX_PH2
DIRECTFET_S3C
S
PLACE_NEAR=Q8931.3:1mm
R8940
147K 2
1
2
Q8931
G
(GND_GFXIMVP_AGND)
10%
25V
X6S-CERM 2
0402
C8925 1
1UF
R8998
649135PBF
10%
25V
2 X7R
0402
C8924 1
0.00075
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.05V
CRITICAL
0.22UF
10%
25V
X6S-CERM 2
0402
CRITICAL
C8923 1
1UF
68UF
D
CRITICAL
L8930
0.2UH-20%-24A-0.003OHM
0
PLACE_NEAR=Q8900.16:1mm
C8901
10%
16V
CERM 2
402
5%
1/10W
MF-LF
2 603
C8922
DIRECTFET-SA
0.22UF
PPVIN_S0_GFXIMVP_R
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=5V
68UF
OMIT_TABLE
CRITICAL
1
20%
20%
20%
20%
16V
16V
16V
16V
POLY-TANT 2
POLY-TANT 2
POLY-TANT 2
POLY-TANT 2
CASE-D2E-SM
CASE-D2E-SM
CASE-D2E-SM
CASE-D2E-SM
S
C8930 1
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=12.8V
C8921
IRF6802SDTRPBF
3
C8902
68UF
OMIT_TABLE
CRITICAL
1
Q8930
D
2 G
1
2
8
7
D
1
PLACE_NEAR=Q8900.25:1mm
C8920
68UF
7
8
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
DIDT=TRUE
=PP5V_S0_GFXIMVP
OMIT_TABLE
CRITICAL
1
C8926
0.001UF
10%
50V
X7R-CERM 2
0402
8
1
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=0V
80 8
GPU VCORE VID STRAPS
DEFAULT = 0.9 V
=PP3V3_S0_GFX3V3BIAS
NOSTUFF
1
NOSTUFF
1
NOSTUFF
1
80 78
80 78
A
80 78
80 78
80 78
80
1%
1/20W
MF
201 2
1
R8946 R8947
10K
1%
1/20W
MF
201 2
80 78
10K
NOSTUFF
1
R8943 R8944 R8945
10K
Stuff option for GPIO control
NOSTUFF
10K
1%
1/20W
MF
201 2
10K
1%
1/20W
MF
201 2
1%
1/20W
MF
201 2
1
R8981 = PSI Control
R8982 = VID6 control (old connection)
R8982 = DPSLP Control
1
R8948 R8949
10K
10K
1%
1/20W
MF
201 2
1%
1/20W
MF
201 2
80 8
=PP3V3_S0_GFX3V3BIAS
NOSTUFF
R8970 1R8971
499
R8981
1
GFXIMVP_VID & lt; 0 & gt;
GFXIMVP_VID & lt; 1 & gt;
GFXIMVP_VID & lt; 2 & gt;
GFXIMVP_VID & lt; 3 & gt;
GFXIMVP_VID & lt; 4 & gt;
GFXIMVP_VID & lt; 5 & gt;
GFXIMVP_VID & lt; 6 & gt;
0
2
GFXIMVP_PSI_L
1%
1/20W
MF
2 201
80
5%
1/20W
MF
201
80
NOSTUFF
78
NOSTUFF
IN
GFXIMVP_PSI_R_L
80
R8982
80
1
NOSTUFF
10K
10K
10K
10K
10K
10K
1%
1/20W
MF
201 2
1%
1/20W
MF
201 2
1%
1/20W
MF
201 2
1%
1/20W
MF
201 2
1%
1/20W
MF
201 2
1%
1/20W
MF
201 2
2
1%
1/20W
MF
201 2
R8974
100K
5%
1/20W
MF
2 201
7
6
5
SYNC_DATE=03/05/2012
PAGE TITLE
GFX IMVP VCore Regulator
NOSTUFF
1
R8972
100K
2
GFXIMVP_DPSLP_EN
5%
1/20W
MF
2 201
80
DRAWING NUMBER
1
R8973
Apple Inc.
100K
5%
1/20W
MF
2 201
5%
1/20W
MF
201
8
Do not config
PSI_L = HIGH & DPSLP_EN = HIGH
80
R8983
0
5%
1/20W
MF
2 201
1
SYNC_MASTER=D2_SEAN
GFXIMVP_VID & lt; 6 & gt;
NOSTUFF
1
100K
GFXIMVP_VR_TT_L
GFXIMVP_PSI_L
GFXIMVP_DPSLP_EN
5%
1/20W
MF
201
R89501 R89511 R89521 R89531 R89541 R89551 R89561
10K
0
NOSTUFF
1
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
4
3
051-9589
2
SIZE
D
REVISION
4.18.0
BRANCH
PAGE
89 OF 132
SHEET
80 OF 99
1
A
8
7
6
5
4
3
2
1
D
D
LCD PANEL INTERFACE (eDP)
CRITICAL
J9000
20525-130E-01
F-RT-SM
31
1
PPVOUT_S0_LCDBKLT
99 86 7
NC
2
3
86 7
LED_RETURN_6
LED_RETURN_5
86 7
LED_RETURN_4
5
LED_RETURN_3
LED_RETURN_2
6
86 7
86 7
LED_RETURN_1
8
LCD_HPD_CONN
LCD_FSS
10
86 7
86 7
0
82
OUT
82 7
R9000
LCD_HPD
BI
95 82
DP_INT_AUX_C_P
C9028
1
BI
95 82
DP_INT_AUX_C_N
C9029
MF
IN
DP_INT_ML_C_P & lt; 0 & gt;
C9020
IN
DP_INT_ML_C_N & lt; 0 & gt;
C9021
IN
95 82
1
DP_INT_ML_C_P & lt; 1 & gt;
C9022
1
95 82
IN
DP_INT_ML_C_N & lt; 1 & gt;
C9023
2
10%
X5R-CERM
1
2
10%
X5R-CERM
0.1UF
LCD_PWR_EN
2
10%
X5R-CERM
0.1UF
95 82
1
2
10%
X5R-CERM
0.1UF
95 81 7
16V
0201
95 81 7
95 82
10K
IN
DP_INT_ML_C_P & lt; 2 & gt;
C9024
1
95 82
IN
DP_INT_ML_C_N & lt; 2 & gt;
C9025
1
IN
DP_INT_ML_C_P & lt; 3 & gt;
C9026
1
IN
DP_INT_ML_C_N & lt; 3 & gt;
C9027
1
0.1UF
CRITICAL
2
10%
X5R-CERM
0.1UF
95 82
2
10%
X5R-CERM
0.1UF
95 82
2
10%
X5R-CERM
0.1UF
95 DP_INT_ML_F_P & lt; 0 & gt;
16V
0201
95 DP_INT_ML_F_N & lt; 0 & gt;
16V
0201
95 DP_INT_ML_F_P & lt; 1 & gt;
16V
0201
95 DP_INT_ML_F_N & lt; 1 & gt;
16V
0201
2
10%
X5R-CERM
95 81 7
=PP5V_S0_LCD
2
95 81 7
3
B
VIN_2
GND
C9009
1
4
VOUT_2
PP5VR3V3_SW_LCD_ISNS
5
VOUT_1
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=5V
THRM
PAD
1
C9011
1
C9012
0.1UF
7
2
10UF
10%
16V
2 X7R-CERM
0402
6
DP_INT_ML_N & lt; 1 & gt;
95 81 7
DP_INT_ML_P & lt; 2 & gt;
95 81 7
DP_INT_ML_N & lt; 2 & gt;
21
FL9001
23
2
24
25
15OHM-100MA-8.5GHZ
DLP0NS
SYM_VER-2
4
3
26
27
CRITICAL
FL9002
28
1
2
29
30
15OHM-100MA-8.5GHZ
DLP0NS
SYM_VER-2
4
3
95 81 7
95 81 7
33
DP_INT_ML_P & lt; 3 & gt;
DP_INT_ML_N & lt; 3 & gt;
CRITICAL
34
FL9003
1
35
2
36
37
20%
6.3V
X5R
603
2
1
39
FERR-220-OHM
PP5VR3V3_SW_LCD_UF
2
38
L9000
1
NC_ISNS_LCD_PANELP
OUT
OUT
7 98
7
98
7
1
0.001UF
10%
50V
X7R-CERM
0402
2
C9000 1
2
SM
BP9000
R9011
1
8
=PP3V3_S0_LCD
1
DP_INT_ML_P & lt; 0 & gt;
SIGNAL_MODEL=EMPTY
SM
BP9001
BEAD-PROBE
1M
95 81 7
1
R9003
DP_INT_ML_P & lt; 1 & gt;
SIGNAL_MODEL=EMPTY
R9013
1
BP9003
95 81 7
DP_INT_AUX_P
95 81 7
R9015
1
1M
5%
1/20W
MF
2 201
R9002
SIGNAL_MODEL=EMPTY
1M
1
DP_INT_ML_P & lt; 2 & gt;
SM
95 81 7
DP_INT_ML_N & lt; 2 & gt;
SIGNAL_MODEL=EMPTY
95 81 7
1
DP_INT_ML_P & lt; 3 & gt;
SIGNAL_MODEL=EMPTY
BP9007
SM
95 81 7
DP_INT_ML_N & lt; 3 & gt;
1M
5%
1/20W
MF
201
DRAWING NUMBER
Apple Inc.
7
6
5
4
051-9589
NOTICE OF PROPRIETARY PROPERTY:
R9018
1
1M
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
2
3
2
SIZE
D
REVISION
R
5%
1/20W
MF
201
8
SYNC_DATE=01/13/2012
eDP Display Connector
2
2
1
BEAD-PROBE
R9017
1
1M
5%
1/20W
MF
201
BP9006
SM
SYNC_MASTER=D2_KEPLER
PAGE TITLE
R9016
1
BEAD-PROBE
2
2
5%
1/20W
MF
201
BP9005
BEAD-PROBE
5%
1/20W
MF
2 201
1M
1M
5%
1/20W
MF
201
BP9004
1
R9001
1
R9014
1
BEAD-PROBE
SM
95 81 7
2
5%
1/20W
MF
201
DP_INT_ML_N & lt; 1 & gt;
SIGNAL_MODEL=EMPTY
2
5%
1/20W
MF
201
1
SM
DP_INT_AUX_N
1M
1
SM
95 81 7
BEAD-PROBE
95 81 7
A
1M
1
BP9002
BEAD-PROBE
5%
1/20W
MF
2 201
1
R9012
DP_INT_ML_N & lt; 0 & gt;
SIGNAL_MODEL=EMPTY
1M
LCD_HPD_CONN
2
5%
1/20W
MF
201
1
LCD Panel HPD & AUX strapping
B
518S0829
1000PF
10%
100V 2
X7R
603-1
BEAD-PROBE
95 81 7
32
1
C9002
0.1UF
10%
16V
X7R-CERM
0402
41
PP5VR3V3_SW_LCD
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=5V
0805
C9001
NC_ISNS_LCD_PANELN
40
2
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=5V
SIGNAL_MODEL=EMPTY
81 7
22
CRITICAL
1
C
19
20
15OHM-100MA-8.5GHZ
DLP0NS
SYM_VER-2
4
3
XW9020
0.1UF
10%
16V
X7R-CERM
0402
DP_INT_ML_P & lt; 1 & gt;
95 81 7
2
CRITICAL
MFET-2X2-8IN
VIN_1
DP_INT_ML_N & lt; 0 & gt;
17
18
1
95 DP_INT_ML_F_N & lt; 2 & gt;
16V
0201
95 DP_INT_ML_F_N & lt; 3 & gt;
16V
0201
16
DP_INT_ML_P & lt; 0 & gt;
FL9000
95 DP_INT_ML_F_P & lt; 2 & gt;
16V
0201
95 DP_INT_ML_F_P & lt; 3 & gt;
16V
0201
15
95 81 7
CRITICAL
SM
8
12
14
15OHM-100MA-8.5GHZ
DLP0NS
SYM_VER-2
4
3
FPF1009
ON
11
DP_INT_AUX_P
DP_INT_AUX_N
13
U9000
1
9
16V
0201
1
5%
1/16W
MF-LF
402 2
201
7
2
10%
X5R-CERM
0.1UF
R9010
1/20W
2
10%
X5R-CERM
1
0.1UF
IN
81 7
5%
0.1UF
82
2
OUT
95 82
C
1
4
4.18.0
BRANCH
PAGE
90 OF 132
SHEET
81 OF 99
1
A
5
4
3
83 8
DPMUX_UC_MD2
2
=PP3V3_S0_DPMUX
82
1
Q9190
DP 2:1 ANALOG MUX
SSM3K15FV
73
OUT
92 43 41 17 7
BI
92 43 41 17 7
BI
92 43 41 17 7
BI
92 43 41 17 7
BI
92 43 41 17 7
IN
82 25
IN
25
IN
81 7
IN
82
C
82 9
82 9
OUT
IN
TP_DPMUX_UC_P40
TP_DPMUX_UC_P41
TP_DPMUX_UC_P42
LCD_FSS
LCD_MUX_SEL
TP_DPMUX_UC_P45
TP_DPMUX_UC_P46
TP_DPMUX_UC_P47
D4
A5
B4
A1
C2
B2
C1
C3
DPMUX_UC_TX
DPMUX_UC_RX
TP_DPMUX_UC_P52
G2
F3
E4
P40/TMI0/TCMCYI0
P41/TMO0/TCMCKI0/TCMMCI0
P42/TCMCYI1
P43/TMI1/TCMCKI1/TCMMCI1
P44/TMO1/PWMU2B/TCMCYI2
P45/PWMU3B/TCMCKI2/TCMMCI2
P46/PWMU4B
P47/PWMU5B
A7
B6
C7
D5
A6
B5
C6
TP_DPMUX_UC_P80
TP_DPMUX_UC_P81
TP_DPMUX_UC_P82
TP_DPMUX_UC_P83
DPMUX_UC_BOOT_TX
DPMUX_UC_BOOT_RX
TP_LCD_IRQ
P90/IRQ2*
P91/IRQ1*
P92/IRQ0*
P93/IRQ12*
P94/IRQ13*
P95/IRQ14*
P96/EXCL
P97/SDA0/IRQ15*
J4
G3
H2
G1
H4
G4
F4
F1
DP_TBTPA_HPD_BUF
DP_TBTPB_HPD_BUF
DP_TBTSNK0_HPD
DP_TBTSNK1_HPD
DP_A_CA_DET_BUF
DP_B_CA_DET_BUF
TP_DPMUX_UC_P96
TBT_DDC_XBAR_EN_L
82
0
8
1
=PP3V3_S3_DPMUX_UC
R9100
82
82
82 78 35 8
82
20
OUT
82
82
82
82
78
82 78
OUT
82 78
OUT
78
OUT
78
OUT
78
OUT
82 78
OUT
B
82 81
OUT
86 82
OUT
82
86 82
OUT
83
OUT
PU OFFPAGE
9
OUT
9
OUT
82 10
OUT
TP_DPA_EG_HPD
TP_DPB_EG_HPD
DP_TBTSNK0_HPD_EG
DP_TBTSNK1_HPD_EG
DP_EXTA_CA_DET_EG
DP_EXTB_CA_DET_EG
HDMI_EG_HPD
DP_INT_EG_HPD
G11
LCD_PWR_EN
G13
LCD_BKLT_EN
F12
TP_DPMUX_UC_PC2
H13
TP_DPMUX_UC_PC3
G10
LCD_MUX_EN
G12
TP_LCD_MUX_REQ
H11
LCD_BKLT_PWM
DP_DDC_MUX_CROSSBAR_LJ13
M10
TP_DPA_IG_HPD
N9
TP_DPB_IG_HPD
K10
DP_TBTSNK0_HPD_IG
L8
DP_TBTSNK1_HPD_IG
TP_DP_EXTA_CA_DET_IG M9
TP_DP_EXTB_CA_DET_IG N8
K9
TP_HDMI_IG_HPD
L7
DP_INT_IG_HPD
C9102
1
0.1UF
IN
35
20%
10V
X7R-CERM
0402
2
M8
N7
K8
K7
K6
N6
M7
L6
=I2C_DPMUX_A_SDA
=I2C_DPMUX_A_SCL
DPMUX_UC_UNUSED
DPMUX_UC_UNUSED
DPMUX_UC_UNUSED
DPMUX_LRESET_L
HDMI_HPD_BUF
LCD_HPD
PC6/TIOCA2/WUE14*
PC7/TIOCB2/TCLKD/WUE15*
E2
F2
A4
B3
IG_LCD_PWR_EN
IG_BKLT_EN
DPMUX_UC_PECI
DPMUX_UC_PEVREF
K5
N5
M6
L5
M5
N4
L4
M4
2
0.1UF
20%
10V
X7R-CERM
0402
2
20%
10V
X7R-CERM
0402
95 77
IN
35
95 77
IN
35
R9102
IN
35
IN
82
IN
82
IN
R9151
0
1
35
0
2
U9100
D3
1
82
C9141
95 77
C9105
IN
IN
IN
95 77
BI
95 77
BI
B8
D8
D9
2
DOUT_0+ B2
DOUT_0- B1
E8
E9
F9
2
NC
NC
10K
5%
25V
NPO
0201
NC
MD1 D1
MD2 H1
DPMUX_UC_MD1
DPMUX_UC_MD2
DPMUX_UC_NMI
DP_INT_ML_C_P & lt; 1 & gt;
DP_INT_ML_C_N & lt; 1 & gt;
OUT
81 95
OUT
81 95
DP_INT_ML_C_P & lt; 2 & gt;
DP_INT_ML_C_N & lt; 2 & gt;
OUT
81 95
OUT
81 95
B9
DOUT_3+ F2
DOUT_3- F1
DP_INT_ML_C_P & lt; 3 & gt;
DP_INT_ML_C_N & lt; 3 & gt;
OUT
81 95
OUT
81 95
H5
DIN2_0+
DIN2_0-
AUX+ H2
AUX- H1
DP_INT_AUX_C_P
DP_INT_AUX_C_N
81 95
BI
81 95
R9162
J5
DDC_CLK2
DDC_DAT2
H3
HPDIN J1
100K
DPMUX_HPD_PD
1
C
2
HPD_2
1%
1/20W MF
201
82
82
LCD_MUX_SEL
A1
GPU_SEL
82
82
LCD_MUX_EN
B7
XSD*
NC
DDC_AUX_SEL C2
82
DPMUX UC PULL-DOWNS
82
82
DPMUX UC PULL-UPS
82
82 78 35 8
82
EG_LCD_PWR_EN
EG_BKLT_EN
PM_ALL_GPU_PGOOD
EG_CLKREQ_IN_L
GPU_PGOOD4
GPU_PGOOD3
GPU_PGOOD2
GPU_PGOOD1
IN
78
IN
78
IN
9 78
IN
88
IN
88
IN
88
10K
1
DPMUX_UC_TRST_L
R9111
10K
1
DPMUX_UC_MD1
R9112
10K
1
10K
1
DPMUX_UC_CLK32K
R9114
10K
1
1/20W
MF
201
1/20W
MF
201
88 82
88 82
2
82
2
44
82
R9115
DPMUX_UC_TCK
10K
R9116
DPMUX_UC_TDI
10K
1
1
1/20W
MF
201
5%
1/20W
MF
201
5%
BI
5%
82
1/20W
MF
201
88 82
82 81
2
86 82
2
1/20W
MF
201
1/20W
MF
201
R9117
10K
1
2
DPMUX_UC_TMS
R9118
10K
1
2
EG_CLKREQ_OUT_L
R9119
100K
1
PU on PCH Page
2 NOSTUFF
IN
25 82
IN
82
IN
82 9
81
1/20W
MF
100K
1
1/20W
MF
R9127
10K
10K
1
MF
201
1/20W
MF
201
1/20W
MF
201
1/20W
MF
201
2
1
2
1
2
PD on LCD Page
2 NOSTUFF
5%
1/20W
1
1
MF
10K
1
R9129
10K
1
2
MF
201
1/20W
MF
201
MF
201
MF
201
2
DPMUX_UC_NMI
1/20W
NOSTUFF
1/20W
MF
82
DPMUX_UC_MD1
R9130
10K
1
2
NOSTUFF
5%
201
82
2
DPMUX_UC_MD2
R9131
10K
1
2
1/20W
1/20W
NOSTUFF
5%
9
82 9
18 9
82 78
42 38 7
HDMI_HPD_L
IN
6 74LVC1G00GF
SOT891
2 A
U9110
18 9
4
HDMI_HPD_BUF 82
82 78
1 B
NC
J9100
5
1909782
82 10
DPA_IG_HPD
DP_TBTSNK0_HPD_EG
DPB_IG_HPD
DP_TBTSNK1_HPD_EG
DP_INT_IG_HPD
3
NC
M-RT-SM
EG_RESET_L
82 78
DP_INT_EG_HPD
R9135
R9136
R9137
R9138
R9139
R9145
R9146
10K
100K
100K
100K
100K
100K
100K
100K
201
1/20W
MF
201
1/20W
MF
201
1/20W
MF
201
1/20W
MF
201
1/20W
MF
201
1/20W
MF
201
1/20W
MF
201
5%
8 35 78 82
R9134
201
5%
=PP3V3_S0_DPMUX_UC
82
DPMUX_UC_UNUSED
10K
MF
5%
82
R9133
1/20W
5%
82
DPMUX_UC_PEVREF
1
201
5%
82
HDMI HPD INVERSION & ISOLATION
10K
MF
5%
9
IN
R9132
1/20W
5%
IN
DPMUX_UC_PECI
MF
5%
82
1/20W
5%
82
B
201
2
R9128
201
5%
R9140
LCD_BKLT_EN
R9126
10K
201
1/20W
2
LCD_BKLT_PWM
201
5%
DPMUX_UC_RESET_L
LCD_PWR_EN
R9125
10K
201
MF
5%
5%
82
EG_RAIL5_EN
R9124
10K
1
82
DPMUX_UC_TDO
82
82
EG_RAIL4_EN
R9123
10K
86 82
82
82
EG_RAIL3_EN
R9122
MF
1/20W
5%
5%
44
EG_RAIL2_EN
1/20W
5%
5%
OUT
NOSTUFF
2
5%
88 82
5%
R9113
2
1
5%
201
5%
DPMUX_UC_MD2
1
10K
5%
MF
2
82
10K
R9121
5%
1/20W
2
82
R9120
5%
5%
82
DPMUX_UC_RESET_L
EG_RAIL1_EN
5%
88 82
2
88
IN
R9110
DPMUX_UC_NMI
88
IN
82
82
=PP3V3_S0_DPMUX_UC
5%
PD0/AN8
PD1/AN9
PD2/AN10
PD3/AN11
PD4/SSO
PD5/SSI
PD6/SSCK
PD7/SCS
PH0/IRQ6*
PH1/EXIRQ7*
PECI
PEVREF
BI
82
OMIT_TABLE
NC E5
81 95
DAUX2+
DAUX2-
MDCKN C4
SYM 3 OF 3
81 95
OUT
DIN2_3+
DIN2_3-
H6
J6
OUT
DIN2_2+
DIN2_2-
F8
DP_INT_ML_C_P & lt; 0 & gt;
DP_INT_ML_C_N & lt; 0 & gt;
DOUT_1+ D2
DOUT_1- D1
DIN2_1+
DIN2_1-
0.47UF
10%
6.3V
X6S-CERM
0402
D
DOUT_2+ E2
DOUT_2- E1
DP_INT_EG_AUX_P
DP_INT_EG_AUX_N
IN
95 77
1
NMI E3
5%
1/20W
MF
201 2
15PF
2
XTAL
EXTAL
DPMUX:HOCO
DPMUX:XTAL R91501
3
4
NC
NC
5%
25V
NPO
0201
RES*
A3
A2
DPMUX_UC_XTAL
DPMUX_UC_EXTAL
20MHZ-30PPM-12PF-50OHM
2
HPD_1
R4F2113NLG
2
TLP-145V
1
J2
DP_INT_EG_ML_P & lt; 3 & gt;
DP_INT_EG_ML_N & lt; 3 & gt;
IN
95 77
5%
1/16W
MF-LF
402
DPMUX:XTAL
J8
DDC_CLK1
DDC_DAT1
20%
10V
X7R-CERM
0402
U9150
DP_INT_EG_ML_P & lt; 2 & gt;
DP_INT_EG_ML_N & lt; 2 & gt;
IN
95 77
1
H8
A6
0.1UF
2
DIN1_1+
DIN1_1- CBTL06142EEE
TFBGA
DIN1_2+
DIN1_2CRITICAL
DP_INT_EG_ML_P & lt; 1 & gt;
DP_INT_EG_ML_N & lt; 1 & gt;
IN
95 77
NOSTUFF
DPMUX_LRESET_L
DAUX1+
DAUX1-
A5
DIN1_0+
DIN1_0-
DP_INT_EG_ML_P & lt; 0 & gt;
DP_INT_EG_ML_N & lt; 0 & gt;
IN
2
DPMUX_UC_RESET_L
Y9100
DPMUX_UC_CLK32K
DPMUX_UC_TCK
DPMUX_UC_TDI
DPMUX_UC_TDO
DPMUX_UC_TMS
DPMUX_UC_TRST_L
1
DPMUX_UC_VCL
82 25
H9
J9
NC
9
2.50X2.00MM-SM
K1
J3
K2
J1
K4
H3
C9103
1
0.1UF
20%
10V
X7R-CERM
0402
2
IN
82
DIN1_3+
DIN1_3-
C9104
95 77
DPMUX:XTAL
U9100
1
9
15PF
B8
C9
B9
A10
C10
B10
C11
A11
C9101
1
0.1UF
OUT
A9
NC
NC
PP3V3_S0_DPMUX_UC_R
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=3.3V
5%
1/20W
MF
201
PA0/KIN8*/SDA1 R4F2113NLG
PE0/EXEXCL
PA1/KIN9*/SCL1
TLP-145V
PE1/ETCK
PA2/KIN10*/PS2AC SYM 2 OF 3
PE2/ETDI
PA3/KIN11*/PS2AD
PE3/ETDO
PE4/ETMS
PA4/KIN12*/PS2BC OMIT_TABLE
PA5/KIN13*/PS2BD
PE5/ETRST*
PA6/KIN14*/PS2CC
PF0/IRQ8*/PWMU0A
PA7/KIN15*/PS2CD
PF1/IRQ9*/PWMU1A
PB0/LSMI*
PF2/IRQ10*/TMOY
PB1/LSCI
PF3/IRQ11*/TMOX
PB2/RI*/PWMU0B
PF4/PWMU2A/EXDSR
PB3/DCD*/PWMU1B
PF5/PWMU3A/EXDTR
PF6/PWMU4A/EXCTS
PB4/DSR*/FSIDO
PB5/DTR*/FSIDI
PF7/PWMU5A/EXRTS
PB6/CTS*/FSICK
PG0/EXIRQ8*/TMIX/SDAA
PB7/RTS*/FSISS
PG1/EXIRQ9*/TMIY/SCLA
PG2/EXIRQ10*/SDAB
PC0/TIOCA0/WUE8*
PG3/EXIRQ11*/SCLB
PC1/TIOCB0/WUE9*
PC2/TIOCC0/TCLKA/WUE10* PG4/EXIRQ12*/SDAC
PC3/TIOCD0/TCLKB/WUE11* PG5/EXIRQ13*/SCLC
PG6/EXIRQ14*/SDAD
PC4/TIOCA1/WUE12*
PC5/TIOCB1/TCLKC/WUE13* PG7/EXIRQ15*/SCLD
BI
A8
A4
0.1UF
20%
10V
X7R-CERM
0402
CONNECT I2C TO LCD BKLT IC
N3
N1
M3
M2
N2
L1
K3
L2
82
C9100
P50/FTXD
P51/FRXD
P52/SCL0
=I2C_DPMUX_UC_SDA
=I2C_DPMUX_UC_SCL
DPMUX_UC_IRQ
DPMUX_UC_UNUSED
DPMUX_UC_UNUSED
DPMUX_UC_UNUSED
DPMUX_UC_UNUSED
FB_CLAMP_TOGGLE_REQ_L
2
5%
1/16W
MF-LF
402
82
1
OUT
0
=PP3V3_S0_DPMUX_UC 1
C9140
BI
BI
89 10
PP3V3_S3_DPMUX_UC_R
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=3.3V
5%
1/16W
MF-LF
402
82
DPMUX:XTAL
44
2
82
DPMUX_UC_XTAL_R
44
IN
89 10
R9101
82
VDD A2
VDD J4
P80/PME*
P81/GA20
P82/CLKRUN*
P83/LPCPD*
P84/IRQ3*/TXD1
P85/IRQ4*/RXD1
P86/IRQ5*/SCK1
A9 P30/LAD0
D9 P31/LAD1
C8 P32/LAD2
B7 P33/LAD3
A8 P34/LFRAM*
D8 P35/LRESET*
D7 P36/LCLK
D6 P37/SERIRQ
LPC_AD & lt; 0 & gt;
LPC_AD & lt; 1 & gt;
LPC_AD & lt; 2 & gt;
LPC_AD & lt; 3 & gt;
LPC_FRAME_L
DPMUX_LRESET_L
LPC_CLK33M_DPMUX_UC
TP_DPMUX_UC_P37
IN
89 10
DP_INT_IG_AUX_P
DP_INT_IG_AUX_N
IN
89 10
2
C9151
GND
GND
GND
GND
GND
GND
OUT
89 10
B6
DP_INT_IG_ML_P & lt; 3 & gt;
DP_INT_IG_ML_N & lt; 3 & gt;
IN
83
B5
DP_INT_IG_ML_P & lt; 2 & gt;
DP_INT_IG_ML_N & lt; 2 & gt;
IN
89 10
OUT
IN
89 10
83
B4
DP_INT_IG_ML_P & lt; 1 & gt;
DP_INT_IG_ML_N & lt; 1 & gt;
IN
89 10
DPMUX_UC_MD1
82
OUT
DP_INT_IG_ML_P & lt; 0 & gt;
DP_INT_IG_ML_N & lt; 0 & gt;
IN
89 10
S 2
C8
82 9
89 10
G
1
B3
OUT
83
VBAT J2
OUT
82 9
83
OUT
AVSS
OUT
88 82
DPMUX_UC_UNUSED
DPMUX_UC_UNUSED
DPMUX_UC_UNUSED
DPMUX_UC_UNUSED
DPMUX_UC_UNUSED
DPMUX_UC_UNUSED
DPMUX_UC_UNUSED
DPMUX_UC_UNUSED
OUT
VCL E1
88 82
N10
M11
L10
N11
N12
M13
N13
L12
DP_EXTA_MUX_EN
DP_EXTA_MUX_SEL_EG
TP_DPMUX_UC_P62
TP_DPMUX_UC_P63
DP_EXTB_MUX_EN
DP_EXTB_MUX_SEL_EG
TP_DPMUX_UC_P66
TP_DPMUX_UC_P67
AVREF L11
OUT
P70/AN0
P71/AN1
P72/AN2
P73/AN3
P74/AN4
P75/AN5
P76/AN6
P77/AN7
P20
P21
P22
P23
P24
P25
P26
P27
L13
K12
K11
J12
K13
J10
J11
H12
1
20%
10V
X7R-CERM
0402
L9
OUT
EG_RAIL1_EN
EG_RAIL2_EN
EG_RAIL3_EN
EG_RAIL4_EN
EG_RAIL5_EN
EG_CLKREQ_OUT_L
EG_RESET_L
FB_CLAMP
OMIT_TABLE
P60/KIN0*
P61/KIN1*
P62/KIN2*
P63/KIN3*
P64/KIN4*
P65/KIN5*
P66/KIN6*
P67/IRQ7*/KIN7*
VCC B1
VCC M1
VCC H10
88 82
OUT
TLP-145V
SYM 1 OF 3
VSS
VSS
VSS
VSS
VSS
88 82
R4F2113NLG
D2
L3
F10
C5
B11
88 82
D13
E11
D12
F11
E13
E12
F13
E10
P10/WUE0*
P11/WUE1*
P12/WUE2*
P13/WUE3*
P14/WUE4*
P15/WUE5*
P16/WUE6*
P17/WUE7*
AVCC M12
D
U9100
B12
A13
A12
B13
D11
C13
C12
D10
C9150
0.1UF
D 3
SOD-VESM-HF
TP_DPMUX_UC_P10
TP_DPMUX_UC_P11
TP_DPMUX_UC_P12
TP_DPMUX_UC_P13
TP_DPMUX_UC_P14
TP_DPMUX_UC_P15
TP_DPMUX_UC_P16
TP_DPMUX_UC_P17
1
G2
6
H7
7
G8
H4
8
1/20W
MF
201
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
7
CA_DET ISOLATION
DPMUX_DEBUG
3
=PP3V3_S0_DPMUX_UC
R9160
6
6
IN
5
S
D
TBT_A_CONFIG1_BUF
3
84 35
100K
1
Q9110
5%
1/20W
MF
201
DP_A_CA_DET_BUF
DRAWING NUMBER
R9161
2
SSM6N37FEAPE
SOT563
OUT
82
85 35
4
Q9110
SSM6N37FEAPE
SOT563
G 5
1
8
7
SYNC_DATE=03/05/2012
PAGE TITLE
=PP3V3_S0_DPMUX_UC
eDP Mux
5
8
SYNC_MASTER=D2_SEAN
82 78 35 8
DPMUX UC DEBUG HEADER
4
IN
TBT_B_CONFIG1_BUF
G 2
4
82 78 35 8
S
DPMUX_UC_MD1
2
100K
Apple Inc.
2
5%
1/20W
MF
201
DP_B_CA_DET_BUF
1
82
82 9
1
D
PP3V3_S0_DPMUX_UC_R
DPMUX_UC_TX
DPMUX_UC_RX
DPMUX_UC_RESET_L
82
82 9
6
82
A
3
051-9589
R
NOTICE OF PROPRIETARY PROPERTY:
OUT
82
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
2
SIZE
D
REVISION
4.18.0
BRANCH
PAGE
91 OF 132
SHEET
82 OF 99
1
A
8
7
6
5
4
3
2
1
D
D
DP A & DP B AUX MUX
1
C9200
R9220 R9230
0.1UF
20%
10V
1
2 X7R-CERM
470K
0402
VCC 13
1%
1/20W
MF
2 201
1
R9240 R9250
1
470K
1%
1/20W
MF
2 201
470K
1%
1/20W
MF
2 201
20%
10V
2 X7R-CERM
470K
R92101
10K
5%
1/16W
MF-LF
402 2
DP_EXTA_MUX_EN
95 35 7
BI
95 35 7
BI
DP_TBTSNK0_AUXCH_C_P
DP_TBTSNK0_AUXCH_C_N
16
1
2
TS3DS10224
ENA
QFN
83 82
OUTA1+ 20
OUTA1- 19
BI
3
4
77 95
84
BI
DPA_IG_AUX_CH_P
DPA_IG_AUX_CH_N
BI
IN
DP_TBTSNK1_EG_AUXCH_P
DP_TBTSNK1_EG_AUXCH_N
BI
77 95
85
OUT
BI
77 95
85
BI
DPB_IG_AUX_CH_P
DPB_IG_AUX_CH_N
BI
18 95
DP_EXTB_MUX_SEL_EG
IN
SAO 15
SAI
BI
GND
5
SBO 11
BI
IN
10
DP_EXTB_MUX_EN
3
4
82
IN
DP_DDC_MUX_CROSSBAR_L
IN
DPA_IG_DDC_CLK
DPA_IG_DDC_DATA
IN
DP_EXTA_MUX_SEL_EG
IN
1%
1/20W
MF
2 201
82 83
OUTB1+ 6
OUTB1- 7
DPB_EG_DDC_CLK
DPB_EG_DDC_DATA
IN
77
DPB_IG_DDC_CLK
DPB_IG_DDC_DATA
IN
DP_EXTB_MUX_SEL_EG
IN
SAO 15
SAI
BI
BI
77
77
C
18
18
ENB
INB+
INB-
18 95
82 83
DPA_EG_DDC_CLK
DPA_EG_DDC_DATA
OUTB0+ 8
OUTB0- 9
14
DP_TBTPB_DDC_CLK
DP_TBTPB_DDC_DATA
470K
1%
1/20W
MF
2 201
OUTA1+ 20
OUTA1- 19
INA+
INA-
18 95
82 83
83 82
12 SBI
1
470K
1%
1/20W
MF
2 201
OUTA0+ 18
OUTA0- 17
ENB
INB+
INB-
470K
QFN
18 95
DP_EXTA_MUX_SEL_EG
1
2
DP_TBTPA_DDC_CLK
DP_TBTPA_DDC_DATA
12 SBI
GND
95 35 7
10
BI
470K
1
TS3DS10224
ENA
5
DP_EXTB_MUX_EN
DP_TBTSNK1_AUXCH_C_P
DP_TBTSNK1_AUXCH_C_N
OUT
THRM
PAD
IN
BI
84
R9253 R9254
1
U9210
16
DP_EXTA_MUX_EN
21
83 82
95 35 7
77 95
OUTB0+ 8
OUTB0- 9
14
BI
OUTB1+ 6
OUTB1- 7
C
DP_TBTSNK0_EG_AUXCH_P
DP_TBTSNK0_EG_AUXCH_N
OUTA0+ 18
OUTA0- 17
INA+
INA-
IN
R9251 R9252
1
1%
1/20W
MF
2 201
THRM
PAD
IN
0402
1%
1/20W
MF
2 201
U9200
83 82
C9210
0.1UF
1
SBO 11
BI
BI
77
18
18
82 83
21
1
VCC 13
82 8
DP A & DP B DDC MUX
=PP3V3_S0_DPMUX
MUX TRUTH TABLE
SAI/SBI
0
0
0
0
1
1
1
1
B
SAO
0
0
1
1
0
0
1
1
SBO | INA
0
1
0
1
0
1
0
1
OUTB0
OUTB1
OUTB0
OUTB1
OUTA0
OUTA0
OUTA1
OUTA1
INB
OUTA0
OUTA0
OUTA1
OUTA1
OUTB0
OUTB1
OUTB0
OUTB1
B
A
SYNC_MASTER=D2_SEAN
SYNC_DATE=03/05/2012
PAGE TITLE
eDP Muxed Graphics Support
DRAWING NUMBER
Apple Inc.
051-9589
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
4.18.0
BRANCH
PAGE
92 OF 132
SHEET
83 OF 99
1
A
6
5
4
3
84
C9420
1
2
C9481
2
22UF
20%
6.3V
X5R-CERM-1
603
2
0.1UF
Min
1030mA
830mA
830mA
V3P3OUT
12
4.7UF
10%
2 25V
X5R-CERM
0603
C9410
C9485
CRITICAL
0.1UF
10%
16V
X5R-CERM
0201
CD3210A0RGP
2
QFN
16
70
IN
=TBTAPWRSW_EN
37 35
IN
TBT_A_HV_EN
RSVD
5
BI
ISET_V3P3
1
1
1
C9486
2
2
2
93 35
93 35
DP_TBTPA_ML_C_P & lt; 1 & gt;
DP_TBTPA_ML_C_N & lt; 1 & gt;
IN
IN
1
84
TBTAPWRSW_ISET_V3P3
10
IN
=TBT_S0_EN
ISET_S3
S0
6.3V
0201
21
4
3
1
R9411
22.6K
1
22.6K
1%
1/20W
MF
201 2
TBTHV:P15V
Single-fault protection
requires two R’s per HV
ISET_Sx with CD3210.
Single R on ISET_V3P3 OK.
22.6K
1%
1/20W
MF
2 201
& lt; RHVS3 & gt;
& lt; RHVS0 & gt;
L9400
REFERENCE DES
CRITICAL
BOM OPTION
RES,MTL FILM,1/20W,17.8K,1,0201,SMD,LF
R9410,R9413
RES,MTL FILM,1/20W,17.8K,1,0201,SMD,LF
R9411,R9414
2
C9400
TBTHV:P12V
10%
50V
X7R-CERM
0402
1
2
(Both C’s)
GND_VOID=TRUE
4V
201
1
1
93
6.3V
0201
2
2
470K
1
93 35 7
OUT
93 35 7
OUT
0.47UF
C9477
5%
MF
R9479
470K
1
1/20W
201
2
5%
MF
1
20%
CERM-X5R-1
HPDOUT
HPD
17
1
R9428
5%
1/20W
MF
2 201
0.01UF
10%
25V
X5R-CERM 2
0201
DP Dir
(0-18.9V)
TBT Dir
93 7
TBT: TX_0
1/20W
201
MDP-D2
F-RT-TH GND0
HPD
ML_LANE0P
CONFIG1
ML_LANE0N
CONFIG2
GND1
GND2
ML_LANE3P ML_LANE1P
ML_LANE1N
ML_LANE3N
GND3
GND4
ML_LANE2P
AUX_CHP
ML_LANE2N
AUX_CHN
RETURN
DP_PWR
GND_VOID=TRUE
(Both C’s)
C9470
TBT_A_R2D_P & lt; 0 & gt;
TBT_A_R2D_N & lt; 0 & gt;
TBTACONN_7_C
C9471
1
1
10%
25V
X5R-CERM 2
0201
2
TBT_A_D2R_C_P & lt; 1 & gt;
TBT_A_D2R_C_N & lt; 1 & gt;
A
K
BAR90-02LRH
D9499
TSLP-2-7
A
93
K
BAR90-02LRH
4V
201
93
TBT_A_D2R1_AUXDDC_P
TBT_A_D2R1_AUXDDC_N
IN
20%
X5R
7 35 93
IN
7 35 93
6.3V
0201
1
R9470
R9471
470K
5%
1/20W
MF
201
2
5%
1/20W
MF
201
DP_A_LSX_ML_P & lt; 1 & gt;
DP_A_LSX_ML_N & lt; 1 & gt;
84 93
B
84 93
TBT: LSX_R2P/P2R (P/N)
GND_VOID=TRUE
(Both C’s)
C9472
93 7
93 7
514-0803
1
2
20%
X5R
0.22UF
TBT_A_R2D_P & lt; 1 & gt;
TBT_A_R2D_N & lt; 1 & gt;
C9473
1
6.3V
0201
TBT_A_R2D_C_P & lt; 1 & gt;
TBT_A_R2D_C_N & lt; 1 & gt;
IN
20%
X5R
0.22UF
7 35 93
IN
2
7 35 93
6.3V
0201
TBT: TX_1
GND_VOID=TRUE
TSLP-2-7
1
2
GND_VOID=TRUE
1
R9472
470K
650NH-5%-0.430MA-0.52OHM
DP_A_AUXCH_DDC_P
DP_A_AUXCH_DDC_N
TBT_A_R2D_C_P & lt; 0 & gt;
TBT_A_R2D_C_N & lt; 0 & gt;
GND_VOID=TRUE
(0-18.9V)
SHIELD PINS
(Both D’s)
D9498
6.3V
0201
2
470K
0.01UF
PORT B
GND_VOID=TRUE
1
GND_VOID=TRUE
GND_VOID=TRUE
C9406
2
20%
X5R
0.22UF
MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=18.9V
B1
B3
B5
B7
B9
B11
B13
B15
B17
B19
1
0.22UF
L9498
93 84
84
100K
CRITICAL
93 84
TBT_A_HPD
GND THMPAD
For J9400 TBT SMT pads
(3, 5, 17 & 19):
S22
S21
S20
S19
S18
S17
2
4V
201
84 93
C9405 1
SIGNAL_MODEL=TBTPIN
GND_VOID=TRUE
2
84 93
GND_VOID=TRUE
CRITICAL
5%
1/20W
MF
201
2
DP_A_LSX_ML_P & lt; 1 & gt;
DP_A_LSX_ML_N & lt; 1 & gt;
20
DP_PD
1
2
R9499
2.2K
GND_VOID=TRUE
20%
CERM-X5R-1
1
0.47UF
2
12
5%
1/20W
MF
201
B2
B4
B6
B8
B10
B12
B14
B16
B18
B20
2
DP_TBTPA_ML_P & lt; 3 & gt;
DP_TBTPA_ML_N & lt; 3 & gt;
5%
1/20W
MF
201
(Both C’s)
19
TBT: LSX_A_R2P/P2R (P/N)
1M
DP Dir
SIGNAL_MODEL=EMPTY
TBT_A_BIAS
GND_VOID=TRUE
LSTX
LSRX
5%
1/20W
MF
201 2
J9400
2.2K
TBT_A_D2R_P & lt; 1 & gt;
TBT_A_D2R_N & lt; 1 & gt;
TBT Dir
5%
1/20W
MF
201
TBT: Unused
6.3V
0201
R9498 1
1
10%
50V
X7R-CERM
0402
2
20%
X5R
0.22UF
C9476
12
R9426
GND
R9495
2
20%
X5R
93
84
6
DP_TBTPA_HPD
SHIELD PINS
R9478
1
0.22UF
DPMLO+
DPMLO-
84
2
1K
SIGNAL_MODEL=EMPTY
C9479
13
TBT_A_DP_PWRDN
GND_VOID=TRUE
1
1K
B
IN
OUT
S16
S15
S14
S13
S12
93 7
2
5%
1/20W
MF
201
IN
10
93 7
20%
CERM-X5R-1
C9478
IN
C 6
TBT_A_D2R_C_P & lt; 0 & gt;
TBT_A_D2R_C_N & lt; 0 & gt;
93 7
4V
201
R9494
DP_TBTPA_ML_C_P & lt; 3 & gt;
DP_TBTPA_ML_C_N & lt; 3 & gt;
C9401
2
1
TBT_A_CONFIG1_RC
MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=18.9V
1
MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=18V
0.01UF
GND_VOID=TRUE
0.47UF
18
R9401
1
20%
CERM-X5R-1
CA_DET
TBTACONN_1_C
TBTACONN_20_RC
2
Max
1170mA (12W minimum)
C9475
14
PP3V3RHV_SW_TBTAPWR
0.01UF
1
TBT_A_LSTX
TBT_A_LSRX_UNBUF
MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=15V
0603
TBTHV:P12V
2
0.47UF
35
FERR-120-OHM-3A
2
C9474
84 93
Thunderbolt Connector A
CRITICAL
ILIM = 40000 / RISET
118S0145
TBT_A_D2R_P & lt; 0 & gt;
TBT_A_D2R_N & lt; 0 & gt;
CA_DETOUT
DP+
DP-
B 1
10%
16V
2 X5R-CERM
0201
& lt; RV3P3 & gt;
118S0145
Min
1090mA
C9460
0.1UF
1
1
Nominal
IHVS0/S3 1120mA
16
11
A 3
Y = B
84 93
C
R9414
1%
1/20W
MF
201 2
DESCRIPTION
OUT
1%
1/20W
MF
2 201
DP_A_AUXCH_DDC_N
DP_A_AUXCH_DDC_P
22
TBT: RX_1 Bias Sink
DP_TBTPA_ML_P & lt; 1 & gt;
DP_TBTPA_ML_N & lt; 1 & gt;
35
4 Y
TBT_A_LSRX
23
1
22.6K
QTY
D
10%
16V
X5R-CERM
0201
TBTHV:P15V
R94131
For 12V systems:
35
R9412
36.5K
1%
1/20W
MF
2 201
TBTAPWRSW_ISET_S3_R
TBTAPWRSW_ISET_S0_R
C
5
AUXIOAUXIO+
DDC_DAT
DDC_CLK
VCC
TBTHV:P15V
R94101
12V: See
below
4
35
SOT891 5
TBTHV:P15V
AUXAUX+
8
2
20%
X5R
U9460
TBTAPWRSW_ISET_S3
9
THRM
PAD
13
2
1
GND
PART NUMBER
93
PP3V3_SW_TBTAPWR
TBTAPWRSW_ISET_S0
AUXIO_EN
7
TBT_A_CONFIG1_BUF
OUT
CRITICAL
ISET_S0
HV_EN
17
IN
6.3V
0201
74AUP1T97
85 70
BI
93
1
24
2
20%
X5R
0.22UF
C9433
0.22UF
8
83
82 35
10%
25V
X5R
402
C9432
0.1UF
20%
6.3V
CERM-X5R
0402
2
DP_TBTPA_AUXCH_N
DP_TBTPA_AUXCH_P
DP_TBTPA_DDC_DATA
DP_TBTPA_DDC_CLK
93
83
C9411
1
10UF
84
C9425
0.1UF
BIASOUT
DP_AUXIO_EN
IN
2
10%
16V
X5R-CERM
0201
0.1UF
BIASIN
2
93
C9431
1
2
10%
16V
X5R-CERM
0201
0.1UF
15
RSVD
EN
11
1
0.1UF
U9410
10%
25V
X5R
402
93 35
C9430
DP_TBTPA_AUXCH_C_N
DP_TBTPA_AUXCH_C_P
BI
MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=15V
VHV
1
93 35
PPHV_SW_TBTAPWR
14
OUT
84
MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=3.3V
18
V3P3
TBT_A_BIAS
VOLTAGE=3.3V
HVQFN
1
TBT_A_CIO_SEL
IN
85 25
6
C9415
2
CBTL05023
SIGNAL_MODEL=TBT_MUX
35
PP3V3_SW_TBTAPWR
7
93 35
5%
1/20W
MF
201
U9420
Max
1200mA
930mA (assumes 15V, 12W minimum)
930mA (assumes 3S, 9-12.6V, 7.5-11.7W)
10%
16V
X5R-CERM
0201
=PPHV_SW_TBTAPWRSW
1
IN
100K
25
1
18.9V Max
93 35
2
5%
1/20W
MF
201
9
Nominal
IV3P3 1100mA
IHVS0
890mA
IHVS3
890mA
20
OUT
10K
VDD
CRITICAL
19
93 35 7
2
R9429 1
R9427
21
C9480
1
100UF
20%
6.3V
POLY-TANT
CASE-B2-SM
OUT
1
=PP3V3_S4_TBTAPWRSW
C9487
93 35 7
10%
16V
X5R-CERM
0201
1
0.1UF
10%
16V
X5R-CERM
0201
2
CRITICAL
8
C9421
1
0.1UF
V3P3 must be S4 to support
wake from Thunderbolt devices.
D
1
PP3V3_SW_TBTAPWR
3.3V/HV Power MUX
8
2
3
7
15
8
1
GND_VOID=TRUE
2
R9473
470K
5%
1/20W
MF
201
2
5%
1/20W
MF
201
0603
SIGNAL_MODEL=EMPTY
C9498
1
1
30PF
5%
50V
C0G-NP0
0402
CRITICAL
C9499
2
2
470k R’s for ESD protection
on AC-coupled signals.
L9499
30PF
650NH-5%-0.430MA-0.52OHM
5%
50V
C0G-NP0
0402
2
1
0603
GND_VOID=TRUE
SIGNAL_MODEL=EMPTY
A
84
TBT_A_HPD
84
TBT_A_CONFIG1_RC
SYNC_MASTER=D2_KEPLER
35
OUT
C9402
0.01UF
TBT_A_CONFIG2_RC
R9452
1
1
1M
5%
1/20W
MF
201
8
7
R9451
1M
2
2
5%
1/20W
MF
201
1
C9494
1
1
330PF
10%
16V
X7R-CERM
0201
C9495
2
10%
16V
X7R-CERM
0201
6
10%
16V
X5R-CERM
0201
2
Thunderbolt Connector A
DRAWING NUMBER
Apple Inc.
100K
330PF
2
R9441
2
SYNC_DATE=01/13/2012
PAGE TITLE
DP Source must pull
down HPD input with
greater than or equal
to 100K (DPv1.1a).
1
051-9589
R
Sink HPD range:
High: 2.0 - 5.0V
Low: 0 - 0.8V
5%
1/20W
MF
201
5
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
4
3
2
SIZE
D
REVISION
4.18.0
BRANCH
PAGE
94 OF 132
SHEET
84 OF 99
1
A
6
5
4
3
85
C9620
1
2
C9681
2
22UF
20%
6.3V
X5R-CERM-1
603
2
0.1UF
Min
1030mA
830mA
830mA
V3P3OUT
4.7UF
10%
2 25V
X5R-CERM
0603
C9685
CRITICAL
0.1UF
10%
16V
X5R-CERM
0201
CD3210A0RGP
2
QFN
16
70
IN
=TBTBPWRSW_EN
37 35
IN
TBT_B_HV_EN
RSVD
5
BI
ISET_V3P3
1
1
C9686
1
2
2
C9632
93 35
DP_TBTPB_ML_C_P & lt; 1 & gt;
DP_TBTPB_ML_C_N & lt; 1 & gt;
IN
IN
1
85
TBTBPWRSW_ISET_V3P3
10
IN
=TBT_S0_EN
ISET_S3
S0
6.3V
0201
21
4
3
1
R9611
22.6K
1
22.6K
1%
1/20W
MF
201 2
TBTHV:P15V
35
R9612
& lt; RV3P3 & gt;
Single-fault protection
requires two R’s per HV
ISET_Sx with CD3210.
Single R on ISET_V3P3 OK.
22.6K
1%
1/20W
MF
2 201
& lt; RHVS3 & gt;
& lt; RHVS0 & gt;
REFERENCE DES
CRITICAL
RES,MTL FILM,1/20W,17.8K,1,0201,SMD,LF
R9610,R9613
L9600
118S0145
2
RES,MTL FILM,1/20W,17.8K,1,0201,SMD,LF
R9611,R9614
TBTHV:P12V
10%
50V
X7R-CERM
0402
TBTBCONN_20_RC
2
1
93 7
4V
201
93 7
2
20%
CERM-X5R-1
GND_VOID=TRUE
4V
201
1
1
93
6.3V
0201
2
2
470K
1
OUT
OUT
0.47UF
C9677
5%
MF
R9679
470K
1
1/20W
201
2
5%
MF
1
12
HPDOUT
HPD
17
1
85
R9628
100K
5%
1/20W
MF
2 201
1
For J9600 TBT SMT pads
(3, 5, 17 & 19):
GND_VOID=TRUE
DP Dir
(Both C’s)
(0-18.9V)
TBT Dir
C9670
TBT_B_R2D_P & lt; 0 & gt;
93 7 TBT_B_R2D_N & lt; 0 & gt;
TBTBCONN_7_C
1/20W
201
2
MDP-D2
F-RT-TH GND0
HPD
ML_LANE0P
CONFIG1
ML_LANE0N
CONFIG2
GND1
GND2
ML_LANE3P ML_LANE1P
ML_LANE1N
ML_LANE3N
GND3
GND4
ML_LANE2P
AUX_CHP
ML_LANE2N
AUX_CHN
RETURN
DP_PWR
C9606 1
10%
25V
X5R-CERM 2
0201
D9698
A
K
BAR90-02LRH
D9699
TSLP-2-7
A
93
K
BAR90-02LRH
4V
201
93
TBT_B_D2R1_AUXDDC_P
TBT_B_D2R1_AUXDDC_N
1
2
6.3V
0201
TBT_B_R2D_C_P & lt; 0 & gt;
TBT_B_R2D_C_N & lt; 0 & gt;
IN
20%
X5R
7 35 93
IN
2
7 35 93
6.3V
0201
GND_VOID=TRUE
1
R9670
470K
R9671
470K
5%
1/20W
MF
201
2
5%
1/20W
MF
201
(0-18.9V)
DP_B_LSX_ML_P & lt; 1 & gt;
DP_B_LSX_ML_N & lt; 1 & gt;
85 93
B
85 93
TBT: LSX_R2P/P2R (P/N)
GND_VOID=TRUE
(Both C’s)
C9672
93 7
93 7
514-0803
1
2
20%
X5R
0.22UF
TBT_B_R2D_P & lt; 1 & gt;
TBT_B_R2D_N & lt; 1 & gt;
C9673
1
6.3V
0201
TBT_B_R2D_C_P & lt; 1 & gt;
TBT_B_R2D_C_N & lt; 1 & gt;
IN
20%
X5R
0.22UF
7 35 93
IN
2
7 35 93
6.3V
0201
TBT: TX_1
GND_VOID=TRUE
TSLP-2-7
1
2
GND_VOID=TRUE
1
R9672
470K
650NH-5%-0.430MA-0.52OHM
DP_B_AUXCH_DDC_P
DP_B_AUXCH_DDC_N
1
0.22UF
0.01UF
A1
A3
A5
A7
A9
A11
A13
A15
A17
A19
2
20%
X5R
GND_VOID=TRUE
SHIELD PINS
(Both D’s)
GND_VOID=TRUE
TBT_B_D2R_C_P & lt; 1 & gt;
TBT_B_D2R_C_N & lt; 1 & gt;
4V
201
MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=18.9V
GND_VOID=TRUE
C9671
PORT A
SIGNAL_MODEL=TBTPIN
GND_VOID=TRUE
2
TBT: TX_0
1
0.22UF
L9698
93 85
TBT_B_HPD
GND THMPAD
CRITICAL
93 85
85 93
DP_PD
1
2
5%
1/20W
MF
201
CRITICAL
5%
1/20W
MF
201
2
20%
CERM-X5R-1
85 93
TBT: LSX_A_R2P/P2R (P/N)
10%
25V
X5R-CERM 2
0201
R9699
2.2K
GND_VOID=TRUE
20%
CERM-X5R-1
1
0.47UF
20
TBTBCONN_1_C
S11
S10
S9
S8
S7
S6
GND_VOID=TRUE
93 35 7
DP_B_LSX_ML_P & lt; 1 & gt;
DP_B_LSX_ML_N & lt; 1 & gt;
85
0.01UF
A2
A4
A6
A8
A10
A12
A14
A16
A18
A20
2
DP_TBTPB_ML_P & lt; 3 & gt;
DP_TBTPB_ML_N & lt; 3 & gt;
5%
1/20W
MF
201
(Both C’s)
93 35 7
19
C9605
DP Dir
SIGNAL_MODEL=EMPTY
TBT_B_BIAS
2
DPMLO+
DPMLO-
LSTX
LSRX
1M
J9400
2.2K
TBT_B_D2R_P & lt; 1 & gt;
TBT_B_D2R_N & lt; 1 & gt;
TBT Dir
5%
1/20W
MF
201
TBT: Unused
6.3V
0201
R9698 1
1
10%
50V
X7R-CERM
0402
2
20%
X5R
0.22UF
C9676
TBT_B_CONFIG1_RC
5%
1/20W
MF
201 2
GND
R9695
2
20%
X5R
93
85
R9626
SHIELD PINS
R9678
1
0.22UF
C9679
18
2
1K
SIGNAL_MODEL=EMPTY
B
12
GND_VOID=TRUE
1
1K
IN
DP_TBTPB_HPD
C 6
TBT_B_D2R_C_P & lt; 0 & gt;
TBT_B_D2R_C_N & lt; 0 & gt;
5%
1/20W
MF
201
C9678
6
TBT_B_DP_PWRDN
S5
S4
S3
S2
S1
1
CA_DET
93 7
20%
CERM-X5R-1
85 93
MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=18.9V
GND_VOID=TRUE
1
MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=18V
0.01UF
2
R9694
DP_TBTPB_ML_C_P & lt; 3 & gt;
DP_TBTPB_ML_C_N & lt; 3 & gt;
C9601
2
0.47UF
IN
OUT
13
PP3V3RHV_SW_TBTBPWR
0.01UF
(Both C’s)
C9675
IN
R9601
GND_VOID=TRUE
0.47UF
14
10
MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=15V
1
Max
1170mA (12W minimum)
1
2
0603
C9600
TBTHV:P12V
C9674
TBT_B_LSTX
TBT_B_LSRX_UNBUF
FERR-120-OHM-3A
BOM OPTION
2
TBT_B_D2R_P & lt; 0 & gt;
TBT_B_D2R_N & lt; 0 & gt;
35
Thunderbolt Connector B
CRITICAL
ILIM = 40000 / RISET
118S0145
Min
1090mA
CA_DETOUT
DP+
DP-
B 1
10%
16V
2 X5R-CERM
0201
1
Nominal
IHVS0/S3 1120mA
C9660
0.1UF
1
85 93
C
R9614
1%
1/20W
MF
201 2
DESCRIPTION
16
11
A 3
Y = B
1%
1/20W
MF
2 201
DP_B_AUXCH_DDC_N
DP_B_AUXCH_DDC_P
22
TBT: RX_1 Bias Sink
DP_TBTPB_ML_P & lt; 1 & gt;
DP_TBTPB_ML_N & lt; 1 & gt;
35
4 Y
TBT_B_LSRX
23
1
22.6K
QTY
D
10%
16V
X5R-CERM
0201
TBTHV:P15V
R96131
PART NUMBER
OUT
36.5K
1%
1/20W
MF
2 201
TBTBPWRSW_ISET_S3_R
TBTBPWRSW_ISET_S0_R
C
5
AUXIOAUXIO+
DDC_DAT
DDC_CLK
VCC
TBTHV:P15V
R96101
12V: See
below
4
35
SOT891 5
TBTHV:P15V
AUXAUX+
8
2
20%
X5R
U9660
TBTBPWRSW_ISET_S3
9
THRM
PAD
13
2
1
GND
For 12V systems:
93
PP3V3_SW_TBTBPWR
TBTBPWRSW_ISET_S0
AUXIO_EN
7
TBT_B_CONFIG1_BUF
OUT
CRITICAL
ISET_S0
HV_EN
17
IN
6.3V
0201
74AUP1T97
84 70
BI
93
1
24
2
20%
X5R
0.22UF
C9633
0.22UF
8
83
82 35
93 35
2
DP_TBTPB_AUXCH_N
DP_TBTPB_AUXCH_P
DP_TBTPB_DDC_DATA
DP_TBTPB_DDC_CLK
93
83
10%
25V
X5R
402
2
85
C9625
0.1UF
BIASOUT
DP_AUXIO_EN
IN
2
10%
16V
X5R-CERM
0201
0.1UF
BIASIN
2
93
C9631
0.1UF
20%
6.3V
CERM-X5R
0402
1
2
C9611
1
10UF
TBT_B_BIAS
VOLTAGE=3.3V
CBTL05023
1
TBT_B_CIO_SEL
IN
10%
16V
X5R-CERM
0201
0.1UF
15
RSVD
EN
11
1
0.1UF
U9610
10%
25V
X5R
402
93 35
C9630
DP_TBTPB_AUXCH_C_N
DP_TBTPB_AUXCH_C_P
BI
MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=15V
VHV
1
93 35
PPHV_SW_TBTBPWR
14
OUT
85
MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=3.3V
18
V3P3
12
C9610
2
HVQFN
35
84 25
6
C9615
SIGNAL_MODEL=TBT_MUX
PP3V3_SW_TBTBPWR
7
93 35
5%
1/20W
MF
201
U9620
Max
1200mA
930mA (assumes 15V, 12W minimum)
930mA (assumes 3S, 9-12.6V, 7.5-11.7W)
10%
16V
X5R-CERM
0201
=PPHV_SW_TBTBPWRSW
1
IN
100K
25
1
18V Max
93 35
2
5%
1/20W
MF
201
9
Nominal
IV3P3 1100mA
IHVS0
890mA
IHVS3
890mA
20
OUT
10K
VDD
CRITICAL
19
93 35 7
2
R9629 1
R9627
21
C9680
1
100UF
20%
6.3V
POLY-TANT
CASE-B2-SM
OUT
1
=PP3V3_S4_TBTBPWRSW
C9687
93 35 7
10%
16V
X5R-CERM
0201
1
0.1UF
10%
16V
X5R-CERM
0201
2
CRITICAL
8
C9621
1
0.1UF
V3P3 must be S4 to support
wake from Thunderbolt devices.
D
1
PP3V3_SW_TBTBPWR
3.3V/HV Power MUX
8
2
3
7
15
8
1
GND_VOID=TRUE
2
R9673
470K
5%
1/20W
MF
201
2
5%
1/20W
MF
201
0603
SIGNAL_MODEL=EMPTY
C9698
1
1
30PF
5%
50V
C0G-NP0
0402
CRITICAL
C9699
2
2
470k R’s for ESD protection
on AC-coupled signals.
L9699
30PF
650NH-5%-0.430MA-0.52OHM
5%
50V
C0G-NP0
0402
2
1
0603
GND_VOID=TRUE
SIGNAL_MODEL=EMPTY
A
85
TBT_B_HPD
85
TBT_B_CONFIG1_RC
SYNC_MASTER=D2_KEPLER
35
OUT
C9602
0.01UF
TBT_B_CONFIG2_RC
R9652
1
1
1M
5%
1/20W
MF
201
8
7
R9651
1M
2
2
5%
1/20W
MF
201
1
C9694
1
1
330PF
10%
16V
X7R-CERM
0201
C9695
2
10%
16V
X7R-CERM
0201
6
10%
16V
X5R-CERM
0201
2
Thunderbolt Connector B
DRAWING NUMBER
Apple Inc.
100K
330PF
2
R9641
2
SYNC_DATE=01/13/2012
PAGE TITLE
DP Source must pull
down HPD input with
greater than or equal
to 100K (DPv1.1a).
1
051-9589
R
Sink HPD range:
High: 2.0 - 5.0V
Low: 0 - 0.8V
5%
1/20W
MF
201
5
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
4
3
2
SIZE
D
REVISION
4.18.0
BRANCH
PAGE
96 OF 132
SHEET
85 OF 99
1
A
8
7
6
5
4
3
2
1
PPBUS S0 LCDBkLT FET
MOSFET
43 mOhm @4.5V
LOADING
Q9706
P-TYPE
RDS(ON)
CRITICAL
FDC638APZ
CHANNEL
0.715 A (EDP)
FDC638APZ_SBMS001
SSOT6-HF
PPBUS_SW_LCDBKLT_PWR
5
1 2
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.6V
603-HF
C9782
1
R9788
BOTTOM
99
THERE IS A SENSE RESISTOR BETWEEN
PPBUS_SW_LCDBKLT_PWR
AND PPBUS_SW_BKL
ON THE SENSOR PAGE
NEED VALUE CHANGES FOR 55V AND 96 LEDS !!!
0.1UF
301K
10%
16V
X7R-CERM 2
0402
1%
1/16W
MF-LF
2 402
=PP5V_S0_BKL
8
LCDBKLT_EN_DIV
*L9710, Q9701, D9701, C9715-C9719 SHOULD ALL BE PLACED NEAR EACH OTHER.
1
R9789
PLACE_NEAR=L9710.2:3MM
CRITICAL
147K
C9715, C9716 SHOULD BE PLACED IN T-BONE. SAME FOR C9718,C9719
CRITICAL
L9710
1%
1/16W
MF-LF
2 402
PPBUS_S0_LCDBKLT_PWR
86 8
PLACE_NEAR=L9710.1:5MM
LCDBKLT_EN_L
2
SOT563
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM
C9713
1
C9712
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=50V
DEM8030C-SM
152S1527
10%
25V
X5R
805
10%
25V
X5R
402
2
C9715, C9716 SHOULD BE PLACED ON TOP SIDE. PLACE C9718,C9719 ON BOTTOM SIDE
D9701
POWERDI-123
A
PLACE_NEAR=D9701.2:5MM
K
CRITICAL
DFLS2100
SWITCH_NODE=TRUE
0.1UF
10UF
D 3
SSM6N15FEAPE
22UH-20%-2.4A-0.105OHM
VOLTAGE=12.6V
1
2
PPBUS_S0_LCDBKLT_PWR_SW
PLACE_NEAR=L9710.1:3MM
CRITICAL
1
Q9707
D
1
3
8
4
D
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.6V
6
F9700
3AMP-32V-467
2
=PPBUS_S0_LCDBKLT 1
PPBUS_S0_LCDBKLT_FUSED
C9715
1
1
2.2UF
10%
100V
X7R-CERM
1210
PPBUS_S0_LCDBKLT_PWR_SW SHOULD BE KEPT AS SHORT AS POSSIBLE
2
PLACE_NEAR=D9701.2:5MM
CRITICAL
C9716
CRITICAL
1
2.2UF
2
10%
100V
X7R-CERM
1210
C9718
1
2.2UF
2
PPVOUT_S0_LCDBKLT
C9719
1
2.2UF
10%
100V
X7R-CERM
1210
2
7 81 99
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=55V
CRITICAL
C9717
1000PF
10%
100V
X7R-CERM
1210
10%
100V
X7R-CERM
0603
2
PLACE_NEAR=R9708.1:5MM
5 G
82
S 4
LCD_BKLT_EN
IN
PLACE_NEAR=D9701.2:3MM
LCDBKLT_DISABLE
PLACE_NEAR=D9701.2:3MM
8
Q9707
=PP3V3_S0_BKL_VDDIO
D 6
SSM6N15FEAPE
PLACE_NEAR=U9701.8:3MM
SOT563
R9708 1
PLACE_NEAR=U9701.22:5MM
PLACE_NEAR=U9701.22:3MM 1
C
2 G
25
0.01UF
S 1
2
BKLT_PLT_RST_L
IN
C9714
1
C9710
1
1UF
10%
16V
X7R-CERM
0402
2
PLACE_NEAR=L9710.2:3MM
C9711
10%
25V
X5R
603-1
2
1%
1/16W
MF-LF
402
10%
16V
X7R-CERM
0402
C
63.4K
5
0.1UF
CRITICAL
2
Q9701
BKL_FET_CNTL
SI7812DN
4
PWRPK-1212-8
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
R9709 1
59.0K
VDDIO
2
1%
1/16W
MF-LF
402
3
23
8
22
1
2
VIN
VLDO
U9701
GD
BKL_FSET
5
FSET
BKL_FLT
20
BKL_ISET
FILTER
LP8545SQX-EXTJ
LLP
6
SW
24
FB
21
BKL_FB
OUT1
12
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
BKL_SW
R9717
2
0
BKL_ISEN4
MF-LF
301K
PWM
7
FAULT
4
EN
R9715
1
100K
(EEPROM should set EN_I_RES=1)
1
R9714
1%
1/16W
MF-LF
402 2
R9704
1
0
5%
1/16W
MF-LF
402
LCD_BKLT_PWM SHOULD BE KEPT AWAY FROM BOOST CIRCUIT
R9765
10K
1%
1/16W
MF-LF
402
15.4K
LCD_BKLT_PWM
17
OUT6
18
19
10.2
2
I_LED=23.96MA
I_LED=369/Riset
BKL_VSYNC_R
R9716
1%
1/16W
MF-LF
402
NO STUFF
1
1
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
2
LED_RETURN_2
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
R9755
10K
THRM
PAD
2
(APN: 353S3376)
PWM RES = 9+3
10.2
2
OUT
7 81
OUT
7 81
B
LED_RETURN_3
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
0.1%
1/16W
TF
402
5%
1/16W
MF-LF
402
D_BKL:DEV
R9720
PLACE_NEAR=U9701.16:10MM
10.2
1
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
2
LED_RETURN_4
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
0.1%
1/16W
TF
402
FPWM=19.2KHZ
details in spec
OUT
7 81
D_BKL:DEV
R9721
PLACE_NEAR=U9701.17:10MM
2
1
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
C9704
10.2
2
LED_RETURN_5
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
0.1%
1/16W
TF
402
XW9710
5%
50V
C0G-CERM
0402
7 81
R9719
1
33PF
2
OUT
D_BKL:DEV
PLACE_NEAR=U9701.14:10MM
1
12.7K
2
5%
1/16W
MF-LF
402
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
0.1%
1/16W
TF
402
BKL_ISEN6
VSYNC
CRITICAL
LED_RETURN_1
R9718
1
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
BKL_ISEN5
OUT5
2
D_BKL:DEV
PLACE_NEAR=U9701.13:10MM
402
2
1
1%
1/16W
MF-LF
402
2
TP_BKL_FAULT
1/16W
2
1
IN
16
LVDS_BKL_PWM_RC
2
PPBUS_S0_LCDBKLT_PWR
82
OUT4
BKLT_EN
1
5%
B
SDA
402
R9731
86 8
BKL_ISEN3
11
10.2
0.1%
1/16W
TF
402
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
BKL_ISEN2
14
25
R9757
13
OUT3
GND_L
=I2C_BKL_1_SDA
MF-LF
OUT2
SCLK
GND_SW
44
1/16W
ISET
15
5%
3
GND_S
1
9
0
1
R9753
10
BKL_SDA
=I2C_BKL_1_SCL
1
BKL_ISEN1
BKL_SCL
R9753 AND R9757 NEED TO BE 402 PACK FOR LAB ACCESS
44
D_BKL:DEV
PLACE_NEAR=U9701.12:10MM
OUT
7 81
SM
BKL_SGND
1
2
D_BKL:DEV
R9722
PLACE_NEAR=U9701.9:10MM
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=0V
PLACE_NEAR=U9701.18:10MM
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
PLACE XW9710 AWAY FROM U9701.1 AND U9701.15
ADD VIAS IN TPAD OF U9701
PART NUMBER
A
116S0004
QTY
DESCRIPTION
6
RES, 0OHM, 0402
10.2
1
2
LED_RETURN_6
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm
0.1%
1/16W
TF
402
REFERENCE DES
R9717,R9718,R9719,R9720,R9721,R9722
CRITICAL
OUT
7 81
BOM OPTION
D_BKL:PROD
SYNC_MASTER=D2_KEPLER
SYNC_DATE=01/13/2012
PAGE TITLE
LCD Backlight Driver (LP8545)
DRAWING NUMBER
Apple Inc.
051-9589
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
4.18.0
BRANCH
PAGE
97 OF 132
SHEET
86 OF 99
1
A
8
7
6
5
4
3
2
1
D
D
PCH VCCIO (1.05V S0) REGULATOR
8
8
=PPVIN_S0_PCHVCCIOS0
=PP5V_S0_PCHVCCIOS0
XW9801
PCHVCCIOS0_BOOT_RC
SM
87 8
=PPPCHVCCIO_S0_REG
1
2
97
R98011
PCH_VCCIOSENSE_P
1
5%
1/16W
MF-LF
402 2
PCH_VCCIOSENSE_N
R98301
Vout = 0.5V * (1 + Ra / Rb)
R9804 1
1
3.01K
1%
1/16W
MF-LF
402
R9844
3.01K
& lt; Ra & gt;
2
UTQFN
=PCHVCCIOS0_EN
IN
& lt; Ra & gt;
3
PCHVCCIOS0_FB
70
6
FB
4
SREF
CRITICAL
PCHVCCIOS0_VO
8
VO
PCHVCCIOS0_OCSET
7
2
C9822
1000PF
5%
25V
NP0-C0G
402
C
PLACE_NEAR=Q9830.1:1.5mm
376S0953
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
DIDT=TRUE
BOOT
12
UGATE
11
PHASE
EN
2
20%
16V
POLY-TANT
CASE-D2E-SM
10%
16V
X5R
402
PCHVCCIOS0_VBST
ISL95870
PCHVCCIOS0_SREF
2
PVCC
U9800
1%
1/16W
MF-LF
402
1UF
1
68UF
20%
16V 2
POLY-TANT
CASE-D2E-SM
C9830
1
2
C9821
68UF
1
0
VCC
PLACE_NEAR=U1800.BJ6:1MM
OMIT_TABLE
CRITICAL
1
14
97
C9820
5%
1/10W
MF-LF
603 2
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V
SM
2
20%
10V
X5R
603
PP5V_S0_PCHVCCIOS0_VCC
XW9802
1
2
13
C
OMIT_TABLE
CRITICAL
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
DIDT=TRUE
10UF
2.2
PLACE_NEAR=U1800.BJ8:1MM
C9801
10
CRITICAL
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
GATE_NODE=TRUE
DIDT=TRUE
CRITICAL
Q9830
PCHVCCIOS0_DRVH
RJK0214DPA
R9840
CRITICAL
WPAK2
1
L9830
0.001
1%
1W
MF-1
0612
0.68UH-20%-23A-0.0034OHM
7
PCHVCCIOS0_LL
1
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
SWITCH_NODE=TRUE
DIDT=TRUE
2
PIMB103T
OCSET
LGATE
15
2
152S1651
PPPCHVCCIO_S0_REG_R
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
=PPPCHVCCIO_S0_REG
2
1
4
3
CRITICAL
C9849
6
PCHVCCIOS0_PGOOD
9
PGOOD
PCHVCCIOS0_RTN
OUT
2
RTN
PCHVCCIOS0_DRVL
FSEL
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
GATE_NODE=TRUE
DIDT=TRUE
C9823
20%
2V
TANT
CASE-B4-SM
1
1000PF
1%
1/16W
MF-LF
402
2
2
5
GND
2.74K
& lt; Rb & gt;
B
PCHVCCIOS0_FSEL
R9845
1
1%
1/16W
MF-LF
402
C9802
1
& lt; Rb & gt;
C9804
1
1
10PF
5%
50V
C0G-CERM
0402
C9805
1
2
2
2
20%
2 2V
TANT
CASE-B4-SM
5%
1/16W
MF-LF
402
99 97
10%
16V
X7R-CERM
0402
2
1
R9841
XW9800
1
PCHVCCIOS0_CS_N
B
2.0K
SM
PCHVCCIOS0_AGND
PCHVCCIOS0_CS_P
99 97
0.047UF
5%
50V
C0G-CERM
0402
C9848
270UF
C9803
10PF
2
R9803
2
CRITICAL
1
0
2.2UF
10%
16V
X5R
603
PGND
12A MAX OUTPUT
f = 300 kHz
2
16
1
2.74K
1
R9805 1
5%
25V
NP0-C0G
402
3 4 5
1
270UF
PLACE_NEAR=L9830.2:1.5mm
70
8 87
Vout = 1.05V
1%
1/16W
MF-LF
402 2
2
MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V
C9840
1000PF
2
PLACE_NEAR=U9800.1:1mm
1
5%
25V
NP0-C0G
402
1
R9842
2.0K
1%
1/16W
MF-LF
2 402
(PCHVCCIOS0_OCSET)
(PCHVCCIOS0_VO)
OCP = R9841 x 8.5uA / R9840
OCP = 14.4A
A
SYNC_MASTER=D2_KEPLER
SYNC_DATE=01/13/2012
PAGE TITLE
PCH VCCIO (1.05V) POWER SUPPLY
DRAWING NUMBER
Apple Inc.
051-9589
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
4.18.0
BRANCH
PAGE
98 OF 132
SHEET
87 OF 99
1
A
8
7
6
5
4
2
3
1
EXT GPU PWRGD Pullup
=PP3V3_S0_PWRCTL
88 70 8
Unused PGOOD signal
GPU Rail Sequencing
1
R9900
R9901
100K
KEPLER GPU REQUIRES RAILS TO COME
up in the following order:
1) GPU_3.3V
2
2) IFPX IOVDD - 1.8V
D
1
100K
5%
1/20W
MF
201
5%
1/20W
MF
201
2
1
R9902
100K
5%
1/20W
MF
2 201
88 70 8
D
=PP3V3_S0_PWRCTL
3) GPUVCORE
NO STUFF
4) FBVDDQ/GDDR5 1.35V
5) PEXVDD/Q
R9991
OR IFPY IOVDD - 1.05V
=P3V3GPU_MISC_EN
OUT
OUT
69
EG_RAIL1_EN
P3V3GPU_EN
69 8
82
EG_RAIL2_EN
P1V8GPU_EN
82
EG_RAIL3_EN
82
EG_RAIL5_EN
OUT
74
OUT
P1V05_S0GPU_EN
GPUVCORE_PGOOD
GPU_PGOOD3
OUT
82
IN
GPUFB_PGOOD
OUT
82
IN
OUT
82
2
CPUIMVP_AXG_PGOOD
=P1V35FB_EN
MAKE_BASE=TRUE
82
82
IN
74
80
OUT
P1V35GPUFB_EN
82
OUT
5%
1/16W
MF-LF
402
MAKE_BASE=TRUE
TP_DDRREG_PGOOD
=GPUVCORE_EN
MAKE_BASE=TRUE
EG_RAIL4_EN
OUT
GPU_PGOOD2
8
OUT
GPUVCORE_EN
GPU_PGOOD1
=PP1V8_GPU_FET
74
=P1V8GPU_EN
MAKE_BASE=TRUE
=PP3V3_S0GPU_FET
IN
80
=P3V3GPU_EN
MAKE_BASE=TRUE
IN
8
82
1
10K
69
GPU_PGOOD4
MAKE_BASE=TRUE
P1V05_S0GPU_PGOOD
TP_P1V5S3RS0_RAMP_DONE
PM_ALL_GPU_PGOOD
MAKE_BASE=TRUE
IN
65
DDRREG_PGOOD
IN
64
P1V5S3RS0_RAMP_DONE
IN
69
MAKE_BASE=TRUE
MAKE_BASE=TRUE
74
NOTE: NO PU ON 3V3 AND 1V8 PGOODS SINCE THEY ARE SYNTHETIC.
=P1V05_GPU_EN
MAKE_BASE=TRUE
NOTE 2: CHECK IF 1V8 IS READ AS LOGIC HIGH BY GMUX
NOTE: 1V8 MAY NOT BE REQUIRED FOR KEPLER IF THERE IS NO LVDS
C
C
PEG_R2D_P & lt; 5 & gt;
PEG_R2D_P & lt; 0 & gt;
71 89
71 89
1
1
R9910
R9915
82
82
5%
1/20W
MF
2 201
5%
1/20W
MF
2 201
NOSTUFF
NOSTUFF
PEG_R2D_N & lt; 0 & gt;
PEG_R2D_N & lt; 5 & gt;
71 89
71 89
PEG_R2D_P & lt; 7 & gt;
PEG_R2D_P & lt; 3 & gt;
71 89
71 89
1
1
R9913
R9917
82
82
5%
1/20W
MF
2 201
5%
1/20W
MF
2 201
NOSTUFF
NOSTUFF
PEG_R2D_N & lt; 3 & gt;
PEG_R2D_N & lt; 7 & gt;
71 89
71 89
PLACE R9910 - R9917 CLOSE TO U8000
B
B
PCIE TEST STRUCTURES (FOR LAB USE)
PEG_D2R_P & lt; 4 & gt;
PEG_D2R_P & lt; 0 & gt;
9 71 89
9 71 89
1
R9924
1
R9920
82
82
5%
1/20W
MF
2 201
5%
1/20W
MF
2 201
NOSTUFF
NOSTUFF
PEG_D2R_N & lt; 0 & gt;
PEG_D2R_N & lt; 4 & gt;
9 71 89
9 71 89
PEG_D2R_P & lt; 7 & gt;
9 71 89
1
R9927
82
5%
1/20W
MF
2 201
A
NOSTUFF
SYNC_MASTER=D2_KEPLER
PEG_D2R_N & lt; 7 & gt;
SYNC_DATE=01/13/2012
PAGE TITLE
9 71 89
Power Sequencing EG/PCH S0
PLACE R9920 - R9927 CLOSE TO U1000
DRAWING NUMBER
Apple Inc.
051-9589
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
4.18.0
BRANCH
PAGE
99 OF 132
SHEET
88 OF 99
1
A
8
7
6
5
CPU Signal Constraints
4
2
3
1
CPU Net Properties
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
CPU_50S
*
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
NET_TYPE
DIFFPAIR NECK GAP
=STANDARD
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
SPACING
TABLE_PHYSICAL_RULE_ITEM
DMI_S2N
PCIE_85D
PCIE
DMI_S2N
PCIE_85D
PCIE
DMI_N2S
PCIE_85D
PCIE
DMI_N2S
PCIE_85D
PCIE
FDI_DATA
PCIE_85D
PCIE
TABLE_PHYSICAL_RULE_ITEM
CPU_55S
*
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
TABLE_PHYSICAL_RULE_ITEM
CPU_27P4S
*
=27P4_OHM_SE
=27P4_OHM_SE
=27P4_OHM_SE
=27P4_OHM_SE
7 MIL
7 MIL
NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target impedance.
DMI_S2N_P & lt; 3:0 & gt;
DMI_S2N_N & lt; 3:0 & gt;
DMI_N2S_P & lt; 3:0 & gt;
DMI_N2S_N & lt; 3:0 & gt;
FDI_DATA_P & lt; 7:0 & gt;
FDI_DATA_N & lt; 7:0 & gt;
FDI_FSYNC & lt; 1..0 & gt;
10 18
10 18
10 18
10 18
9 10
FDI_DATA
CPU_AGTL
*
20 MIL
CPU_VID
=2:1_SPACING
DMI_CLK100M_CPU_P
11 17
I126
CLK_PCIE
DMI_CLK100M_CPU_N
11 17
DP_INT_ML
DP_85D
DISPLAYPORT
DP_INT_ML
DP_85D
DISPLAYPORT
DP_INT_IG_ML_P & lt; 3:0 & gt;
DP_INT_IG_ML_N & lt; 3:0 & gt;
DP_INT_AUX
DP_85D
DISPLAYPORT
DP_INT_AUX
DP_85D
DISPLAYPORT
I132
TOP,BOTTOM
=2x_DIELECTRIC
CPU_EDP_COMP
CPU_27P4S
CPU_COMP
CPU_PEG_COMP
CPU_27P4S
CPU_COMP
CPU_CFG
CPU_50S
CPU_ITP
CLK_PCIE_90D
CLK_PCIE
CLK_PCIE_90D
CLK_PCIE
XDP_CLK_PCH
CLK_PCIE_90D
CLK_PCIE
XDP_CLK_PCH
CLK_PCIE_90D
CLK_PCIE
DPLL_REF_CLK120M
CLK_PCIE_90D
CLK_PCIE
CLK_PCIE
?
*
0.457 MM
?
TABLE_SPACING_RULE_ITEM
?
*
CLK_PCIE
CLK_PCIE_90D
WEIGHT
TABLE_SPACING_RULE_ITEM
CPU_ITP
CLK_PCIE_90D
DMI_CLK100M
I131
LINE-TO-LINE SPACING
9 10
9 10
9 10
D
10 18
TABLE_SPACING_RULE_ITEM
?
CPU_COMP
DMI_CLK100M
I128
LAYER
TABLE_SPACING_RULE_ITEM
?
8 MIL
I125
XDP_CLK_CPU
*
CPU_AGTL
I127
SPACING_RULE_SET
TABLE_SPACING_RULE_ITEM
CPU_8MIL
CPU_50S
FDI_LSYNC & lt; 1..0 & gt;
FDI_INT
XDP_CLK_CPU
=STANDARD
CPU_AGTL
I133
D
*
PCIE
CPU_AGTL
CPU_50S
TABLE_SPACING_RULE_HEAD
WEIGHT
TABLE_SPACING_RULE_ITEM
CPU_AGTL
PCIE_85D
CPU_50S
I130
LINE-TO-LINE SPACING
FDI_LSYNC
I129
LAYER
FDI_FSYNC
FDI_INT
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
?
CPU_VREF
*
12 MIL
?
TABLE_SPACING_RULE_ITEM
10 82
10 82
TABLE_SPACING_RULE_ITEM
CPU_VCCSENSE
*
25 MIL
?
Most CPU signals with impedance requirements are 50-ohm single-ended.
Some signals require 27.4-ohm single-ended impedance.
SOURCE: IVB PLATFORM DG , Tables 205-207
PCI-Express
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM
PCIE_85D
*
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
I138
TABLE_PHYSICAL_RULE_ITEM
CLK_PCIE_90D
*
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
CPU_50S
CPU_ITP
XDP_TCK
CPU_50S
CPU_ITP
CPU_50S
CPU_ITP
CPU_50S
CPU_ITP
CPU_50S
CPU_ITP
I134
XDP_BDRESET_L
CPU_50S
CPU_ITP
I135
XDP_PRDY_L
CPU_50S
CPU_ITP
I136
XDP_PREQ_L
CPU_50S
CPU_ITP
CPU_CATERR_L
CPU_50S
CPU_AGTL
CPU_PROC_SEL_L
CPU_50S
CPU_AGTL
CPU_PECI
CPU_50S
CPU_VID
CPU_PROCHOT_L
CPU_50S
CPU_AGTL
XDP_CPU_PWRGD
CPU_50S
CPU_ITP
PM_THRMTRIP_L
CPU_50S
CPU_8MIL
I139
TABLE_SPACING_RULE_HEAD
WEIGHT
15 MIL
XDP_TMS
XDP_BPM
LINE-TO-LINE SPACING
?
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
15 MIL
?
TABLE_SPACING_RULE_ITEM
*
CPU_ITP
XDP_BPM_L
LAYER
PCIE
CPU_ITP
CPU_50S
XDP_TRST_L
SPACING_RULE_SET
CLK_PCIE_90D
CPU_50S
XDP_TDO
TABLE_SPACING_RULE_HEAD
DPLL_REF_CLK120M
XDP_TDI
=90_OHM_DIFF
TABLE_SPACING_RULE_ITEM
PCIE
TOP,BOTTOM
TABLE_SPACING_RULE_ITEM
CLK_PCIE
*
20 MIL
?
C
I115
PEG
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
PEG_80D
*
=80_OHM_DIFF
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
PM_SYNC
I150
CPU_50S
CPU_AGTL
PM_MEM_PWRGD
TABLE_PHYSICAL_RULE_ITEM
CPU_50S
CPU_AGTL
CPU_PWRGD
CPU_50S
CPU_AGTL
CPU_SM_RCOMP
DP_INT_IG_AUX_P
DP_INT_IG_AUX_N
CPU_EDP_COMP
CPU_PEG_COMP
CPU_CFG & lt; 17..0 & gt;
ITPCPU_CLK100M_P
ITPCPU_CLK100M_N
ITPXDP_CLK100M_P
ITPXDP_CLK100M_N
DPLL_REF_CLKP
DPLL_REF_CLKN
XDP_CPU_TDI
XDP_CPU_TDO
XDP_CPU_TMS
XDP_CPU_TCK
XDP_CPU_TRST_L
XDP_BPM_L & lt; 3..0 & gt;
XDP_BPM_L & lt; 7..4 & gt;
XDP_DBRESET_L
XDP_CPU_PRDY_L
XDP_CPU_PREQ_L
CPU_CATERR_L
CPU_PROC_SEL_L
CPU_PECI
CPU_PROCHOT_L
XDP_CPU_PWRGD
PM_THRMTRIP_L
PM_SYNC
PM_MEM_PWRGD
CPU_PWRGD
CPU_SM_RCOMP & lt; 2..0 & gt;
10 82
10 82
10
10
10 24
11 17
11 17
17 24
17 24
9 11
9 11
11 24
11 24
11 24
11 24
11 24
11 24
11 24
11 24 25
11 24
C
11 24
11 41
11 20
11 20 42
11 41 42 65
24
11 20 42
11 18
11 18 27
11 20 24
CPU_27P4S
CPU_COMP
CPU_50S
CPU_VID
CPU_VIDSOUT
13 65
CPU_50S
CPU_VID
CPU_VIDSCLK
13 65
CPU_50S
11
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_ITEM
PEG_RXRX
*
=4X_DIELECTRIC
?
PEG_TXTX
*
=4X_DIELECTRIC
?
CPU_VID
CPU_VIDALERT_L
CPU_55S
CPU_VID
CPU_VCCSA_VID & lt; 1..0 & gt;
CPU_VCCSENSE
CPU_27P4S
CPU_VCCSENSE
CPU_VCCSENSE
CPU_27P4S
CPU_VCCSENSE
CPU_VCCSENSE_P
CPU_VCCSENSE_N
CPU_VCCSENSE
CPU_27P4S
CPU_VCCSENSE
CPU_VCCIOSENSE_P
13 67
CPU_VCCSENSE
CPU_27P4S
CPU_VCCSENSE
CPU_VCCIOSENSE_N
13 67
CPU_VCCSENSE
CPU_27P4S
CPU_VCCSENSE
CPU_AXG_SENSE_P
13 65
CPU_VCCSENSE
CPU_27P4S
CPU_VCCSENSE
CPU_AXG_SENSE_N
I120
CPU_VCCSENSE
CPU_27P4S
CPU_VCCSENSE
CPU_VCC_VALSENSE_P
13
I121
CPU_VCCSENSE
CPU_27P4S
CPU_VCCSENSE
CPU_VCC_VALSENSE_N
13
I122
CPU_VCCSENSE
CPU_27P4S
CPU_VCCSENSE
I123
CPU_VCCSENSE
CPU_27P4S
CPU_VCCSENSE
CPU_AXG_VALSENSE_N
13
I137
CPU_VCCSASENSE
CPU_50S
CPU_AGTL
CPU_VCCSASENSE
13 62
PPCPU_MEM_VREFDQ_A
PPCPU_MEM_VREFDQ_B
13 65
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
PEG_TXRX
*
=10X_DIELECTRIC
?
13 62
13 65
13 65
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM
PEG_D2R
PEG_D2R
*
PEG_RXRX
PEG_R2D
PEG_R2D
*
PEG_TXTX
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
PEG_D2R
PEG_R2D
*
PEG_TXRX
B
I140
CPU_MEM_VREF
CPU_VREF
I141
CPU_MEM_VREF
CPU_VREF
I144
CPU_MEM_VREF
CPU_VREF
I145
CPU_MEM_VREF
CPU_VREF
I146
CPU_MEM_VREF
CPU_VREF
I147
CPU_MEM_VREF
CPU_VREF
I148
XDP_CLK_ITP
CLK_PCIE_90D
CLK_PCIE
I149
XDP_CLK_ITP
CLK_PCIE_90D
CLK_PCIE
PEG_80D
PEG_R2D
PEG_80D
PEG_D2R
PEG_R2D
PEG_80D
PEG_R2D
PEG_R2D
PEG_80D
PEG_R2D
PEG_80D
PEG_D2R
PEG_80D
PEG_D2R
PEG_80D
A
PEG_D2R
PEG_80D
PEG_D2R
CPU_AXG_VALSENSE_P
PP0V75_S3_MEM_VREFDQ_A
PP0V75_S3_MEM_VREFDQ_B
PP0V75_S3_MEM_VREFCA_A
PP0V75_S3_MEM_VREFCA_B
XDP_CPU_CLK100M_P
XDP_CPU_CLK100M_N
PEG_R2D_P & lt; 7..0 & gt;
PEG_R2D_N & lt; 7..0 & gt;
PEG_R2D_C_P & lt; 7..0 & gt;
PEG_R2D_C_N & lt; 7..0 & gt;
PEG_D2R_P & lt; 7..0 & gt;
PEG_D2R_N & lt; 7..0 & gt;
PEG_D2R_C_P & lt; 7..0 & gt;
PEG_D2R_C_N & lt; 7..0 & gt;
13 65
13
B
10 33
10 33
28 29 33
30 31 33
28 29 33
30 31 33
24
24
71 88
71 88
9 71
9 71
9 71 88
9 71 88
71
71
SYNC_MASTER=D2_KEPLER
SYNC_DATE=01/13/2012
PAGE TITLE
CPU Constraints
DRAWING NUMBER
Apple Inc.
051-9589
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
4.18.0
BRANCH
PAGE
100 OF 132
SHEET
89 OF 99
1
A
8
7
6
5
Memory Bus Constraints
4
3
2
1
Memory Net Properties
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
MEM_37S
*
=37_OHM_SE
=37_OHM_SE
=37_OHM_SE
=37_OHM_SE
=STANDARD
=STANDARD
MEM_40S
*
=40_OHM_SE
=40_OHM_SE
=40_OHM_SE
=40_OHM_SE
=STANDARD
=STANDARD
ELECTRICAL_CONSTRAINT_SET
NET_TYPE
SPACING
PHYSICAL
TABLE_PHYSICAL_RULE_ITEM
MEM_A_CLK
MEM_A_CLK
MEM_72D
MEM_72D
MEM_CLK
MEM_CLK
MEM_A_CLK_P & lt; 5..0 & gt;
MEM_A_CLK_N & lt; 5..0 & gt;
MEM_A_CNTL
MEM_A_CNTL
MEM_A_CNTL1
MEM_A_CNTL
MEM_37S
MEM_37S
MEM_37S
MEM_37S
MEM_CTRL
MEM_CTRL
MEM_CTRL
MEM_CTRL
MEM_A_CKE & lt; 3..0 & gt;
MEM_A_CS_L & lt; 3..2 & gt;
MEM_A_CS_L & lt; 1 & gt;
MEM_A_CS_L & lt; 0 & gt;
MEM_A_CNTL
MEM_A_CNTL1
MEM_A_CNTL
MEM_A_CMD
MEM_A_CMD
MEM_A_CMD
MEM_A_CMD
MEM_A_CMD
MEM_37S
MEM_37S
MEM_37S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_CTRL
MEM_CTRL
MEM_CTRL
MEM_CMD
MEM_CMD
MEM_CMD
MEM_CMD
MEM_CMD
MEM_A_ODT & lt; 3..2 & gt;
MEM_A_ODT & lt; 1 & gt;
MEM_A_ODT & lt; 0 & gt;
MEM_A_A & lt; 15..0 & gt;
MEM_A_BA & lt; 2..0 & gt;
MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L
MEM_A_DQ_BYTE0
MEM_A_DQ_BYTE1
MEM_A_DQ_BYTE2
MEM_A_DQ_BYTE3
MEM_A_DQ_BYTE4
MEM_A_DQ_BYTE5
MEM_A_DQ_BYTE6
MEM_A_DQ_BYTE7
MEM_50S
MEM_50S
MEM_50S
MEM_50S
MEM_50S
MEM_50S
MEM_50S
MEM_50S
MEM_A_DQ_BYTE0
MEM_A_DQ_BYTE1
MEM_A_DQ_BYTE2
MEM_A_DQ_BYTE3
MEM_A_DQ_BYTE4
MEM_A_DQ_BYTE5
MEM_A_DQ_BYTE6
MEM_A_DQ_BYTE7
MEM_A_DQ & lt; 7..0 & gt;
MEM_A_DQ & lt; 15..8 & gt;
MEM_A_DQ & lt; 23..16 & gt;
MEM_A_DQ & lt; 31..24 & gt;
MEM_A_DQ & lt; 39..32 & gt;
MEM_A_DQ & lt; 47..40 & gt;
MEM_A_DQ & lt; 55..48 & gt;
MEM_A_DQ & lt; 63..56 & gt;
MEM_A_DQS0
MEM_A_DQS0
MEM_A_DQS1
MEM_A_DQS1
MEM_A_DQS2
MEM_A_DQS2
MEM_A_DQS3
MEM_A_DQS3
MEM_A_DQS4
MEM_A_DQS4
MEM_A_DQS5
MEM_A_DQS5
MEM_A_DQS6
MEM_A_DQS6
MEM_A_DQS7
MEM_A_DQS7
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_A_DQS_P & lt; 0 & gt;
MEM_A_DQS_N & lt; 0 & gt;
MEM_A_DQS_P & lt; 1 & gt;
MEM_A_DQS_N & lt; 1 & gt;
MEM_A_DQS_P & lt; 2 & gt;
MEM_A_DQS_N & lt; 2 & gt;
MEM_A_DQS_P & lt; 3 & gt;
MEM_A_DQS_N & lt; 3 & gt;
MEM_A_DQS_P & lt; 4 & gt;
MEM_A_DQS_N & lt; 4 & gt;
MEM_A_DQS_P & lt; 5 & gt;
MEM_A_DQS_N & lt; 5 & gt;
MEM_A_DQS_P & lt; 6 & gt;
MEM_A_DQS_N & lt; 6 & gt;
MEM_A_DQS_P & lt; 7 & gt;
MEM_A_DQS_N & lt; 7 & gt;
MEM_B_CLK
MEM_B_CLK
MEM_72D
MEM_72D
MEM_CLK
MEM_CLK
MEM_B_CLK_P & lt; 5..0 & gt;
MEM_B_CLK_N & lt; 5..0 & gt;
MEM_B_CNTL
MEM_37S
MEM_CTRL
MEM_B_CKE & lt; 3..2 & gt;
I111
MEM_B_CNTL1
MEM_B_CNTL0
MEM_37S
MEM_37S
MEM_CTRL
MEM_CTRL
MEM_B_CKE & lt; 1 & gt;
MEM_B_CKE & lt; 0 & gt;
I109
MEM_B_CNTL
MEM_B_CNTL
MEM_B_CNTL0
MEM_37S
MEM_37S
MEM_37S
MEM_CTRL
MEM_CTRL
MEM_CTRL
MEM_B_CS_L & lt; 3..0 & gt;
MEM_B_ODT & lt; 3..1 & gt;
MEM_B_ODT & lt; 0 & gt;
MEM_B_CMD
MEM_B_CMD6
MEM_B_CMD
MEM_B_CMD
MEM_B_CMD
MEM_B_CMD
MEM_B_CMD
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_CMD
MEM_CMD
MEM_CMD
MEM_CMD
MEM_CMD
MEM_CMD
MEM_CMD
MEM_B_A & lt; 15..7 & gt;
MEM_B_A & lt; 6 & gt;
MEM_B_A & lt; 5..0 & gt;
MEM_B_BA & lt; 2..0 & gt;
MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L
MEM_B_DQ_BYTE0
MEM_B_DQ_BYTE1
MEM_B_DQ_BYTE2
MEM_B_DQ_BYTE3
MEM_B_DQ_BYTE4
MEM_B_DQ_BYTE5
MEM_B_DQ_BYTE6
MEM_B_DQ_BYTE7
MEM_50S
MEM_50S
MEM_50S
MEM_50S
MEM_50S
MEM_50S
MEM_50S
MEM_50S
MEM_B_DQ_BYTE0
MEM_B_DQ_BYTE1
MEM_B_DQ_BYTE2
MEM_B_DQ_BYTE3
MEM_B_DQ_BYTE4
MEM_B_DQ_BYTE5
MEM_B_DQ_BYTE6
MEM_B_DQ_BYTE7
MEM_B_DQ & lt; 7..0 & gt;
MEM_B_DQ & lt; 15..8 & gt;
MEM_B_DQ & lt; 23..16 & gt;
MEM_B_DQ & lt; 31..24 & gt;
MEM_B_DQ & lt; 39..32 & gt;
MEM_B_DQ & lt; 47..40 & gt;
MEM_B_DQ & lt; 55..48 & gt;
MEM_B_DQ & lt; 63..56 & gt;
MEM_B_DQS0
MEM_B_DQS0
MEM_B_DQS1
MEM_B_DQS1
MEM_B_DQS2
MEM_B_DQS2
MEM_B_DQS3
MEM_B_DQS3
MEM_B_DQS4
MEM_B_DQS4
MEM_B_DQS5
MEM_B_DQS5
MEM_B_DQS6
MEM_B_DQS6
MEM_B_DQS7
MEM_B_DQS7
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_85D
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_B_DQS_P & lt; 0 & gt;
MEM_B_DQS_N & lt; 0 & gt;
MEM_B_DQS_P & lt; 1 & gt;
MEM_B_DQS_N & lt; 1 & gt;
MEM_B_DQS_P & lt; 2 & gt;
MEM_B_DQS_N & lt; 2 & gt;
MEM_B_DQS_P & lt; 3 & gt;
MEM_B_DQS_N & lt; 3 & gt;
MEM_B_DQS_P & lt; 4 & gt;
MEM_B_DQS_N & lt; 4 & gt;
MEM_B_DQS_P & lt; 5 & gt;
MEM_B_DQS_N & lt; 5 & gt;
MEM_B_DQS_P & lt; 6 & gt;
MEM_B_DQS_N & lt; 6 & gt;
MEM_B_DQS_P & lt; 7 & gt;
MEM_B_DQS_N & lt; 7 & gt;
TABLE_PHYSICAL_RULE_ITEM
12 28 29 32
12 28 29 32
TABLE_PHYSICAL_RULE_ITEM
MEM_72D
*
=72_OHM_DIFF
=72_OHM_DIFF
=72_OHM_DIFF
=72_OHM_DIFF
=72_OHM_DIFF
=72_OHM_DIFF
MEM_50S
*
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
TABLE_PHYSICAL_RULE_ITEM
I101
TABLE_PHYSICAL_RULE_ITEM
MEM_85D
D
*
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
I102
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
=4:1_SPACING
?
I103
TABLE_SPACING_RULE_ITEM
MEM_CLK2MEM
*
I104
TABLE_SPACING_RULE_ITEM
MEM_CTRL2CTRL
*
=3:1_SPACING
?
MEM_CTRL2MEM
*
=2.5:1_SPACING
?
MEM_CMD2CMD
*
=1.5:1_SPACING
?
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
12 28 29 32
12 29 32
12 28 32
D
12 29 32
12 28 32
12 28 29 32
12 28 29 32
12 28 29 32
12 28 29 32
12 28 29 32
TABLE_SPACING_RULE_ITEM
MEM_CMD2MEM
*
=3:1_SPACING
?
MEM_DATA2DATA
*
=1.5:1_SPACING
?
MEM_DATA2MEM
*
=3:1_SPACING
?
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
MEM_DQS2MEM
*
=3:1_SPACING
?
MEM_2OTHER
*
25 MILS
?
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
MEM_DQBL2BL
*
16 MILS
?
MEM_DQCH2CH
*
25 MILS
I105
?
TABLE_SPACING_RULE_ITEM
I106
Memory Bus Spacing Group Assignments
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CLK
MEM_*
*
MEM_CLK2MEM
SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CMD
MEM_*
*
MEM_CMD2MEM
MEM_CMD
MEM_CMD
*
MEM_CMD2CMD
TABLE_SPACING_ASSIGNMENT_ITEM
C
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_CTRL
MEM_*
*
MEM_CTRL2MEM
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_*_DQ_BYTE*
MEM_*
*
MEM_DATA2MEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CTRL
MEM_CTRL
*
MEM_CTRL2CTRL
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_*_DQ_BYTE*
=SAME
*
MEM_DATA2DATA
MEM_A_DQ_BYTE*
MEM_A_DQ_BYTE*
*
MEM_DQBL2BL
TABLE_SPACING_ASSIGNMENT_ITEM
12 28 29
12 28 29
12 28 29
12 28 29
12 28 29
12 28 29
12 28 29
12 28 29
12 28 29
12 28 29
12 28 29
12 28 29
12 28 29
12 28 29
12 28 29
12 28 29
12 28 29
12 28 29
C
12 28 29
12 28 29
12 28 29
12 28 29
12 28 29
12 28 29
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_B_DQ_BYTE*
MEM_B_DQ_BYTE*
*
MEM_DQBL2BL
MEM_A_DQ_BYTE*
MEM_B_DQ_BYTE*
*
MEM_DQCH2CH
TABLE_SPACING_ASSIGNMENT_ITEM
MEM_DQS
MEM_*
*
MEM_DQS2MEM
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_*
*
*
MEM_2OTHER
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
I110
DDR3 (Memory Down):
DQ signals should be matched within 0.508mm of associated DQS pair
.
DQS intra-pair matching should be within 0.127mm, no inter-pair matching requirement.
DQS to clock matching should be within [CLK-139.73mm] and [CLK-30.48mm].
CLK intra-pair matching should be within 0.127mm, inter-pair matching should be within 0.508mm.
CONTROL signals should be matched within [CLK-2.54mm] to [CLK+0mm] of CLK pairs.
A/BA/CMD signals should be matched within [CLK-2.54mm] to [CLK+2.54mm] of CLK pairs.
DQ/DQS/A/BA/cmd signal spacing is 4x dielectric, CLK is 5x dielectric.
Maximum length of any signal from die pad to first DRAM device is 139.7mm max, to last DRAM device is 194.31mm max.
I108
I107
SOURCE: Chief River SFF Platform DG, Rev 0.7 (#460452), Section 2.6.3
B
A
12 30 31 32
12 30 31 32
12 31 32
12 30 32
12 30 31 32
12 31 32
12 30 32
12 30 31 32
12 30 31 32
12 30 31 32
B
12 30 31 32
12 30 31 32
12 30 31 32
12 30 31 32
12 30 31
12 30 31
12 30 31
12 30 31
12 30 31
12 30 31
12 30 31
12 30 31
12 30 31
12 30 31
12 30 31
12 30 31
12 30 31
12 30 31
12 30 31
12 30 31
12 30 31
12 30 31
12 30 31
12 30 31
12 30 31
12 30 31
12 30 31
SYNC_MASTER=D2_KEPLER
SYNC_DATE=01/13/2012
PAGE TITLE
Memory Constraints
12 30 31
DRAWING NUMBER
Apple Inc.
051-9589
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
4.18.0
BRANCH
PAGE
101 OF 132
SHEET
90 OF 99
1
A
8
7
6
5
Digital Video Signal Constraints
4
3
2
1
PCH Net Properties
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
NET_TYPE
TABLE_PHYSICAL_RULE_ITEM
PCH_DP_90D
*
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
LVDS_85D
*
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
LAYER
PHYSICAL
SPACING
=90_OHM_DIFF
SPACING_RULE_SET
ELECTRICAL_CONSTRAINT_SET
=90_OHM_DIFF
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_HEAD
LINE-TO-LINE SPACING
TABLE_SPACING_RULE_HEAD
WEIGHT
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_ITEM
PCH_DISPLAYPORT
=4:1_SPACING
TABLE_SPACING_RULE_ITEM
?
PCH_DISPLAYPORT
TOP,BOTTOM
=4:1_SPACING
?
LVDS
TOP,BOTTOM
=4:1_SPACING
?
LVDS_IG_A_CLK_P
LVDS_IG_A_CLK_N
LVDS_IG_A_DATA_P & lt; 2..0 & gt;
LVDS_IG_A_DATA_N & lt; 2..0 & gt;
LVDS_IG_A_DATA_P & lt; 3 & gt;
LVDS_IG_A_DATA_N & lt; 3 & gt;
LVDS
LVDS
LVDS
LVDS_85D
LVDS
LVDS_85D
LVDS
LVDS_85D
LVDS
LVDS_85D
LVDS
LVDS_IG_B_DATA
LVDS_85D
LVDS
SATA_HDD_R2D
SATA_90D
SATA
SATA_90D
SATA
SATA_90D
SATA
SATA_90D
SATA
SATA_90D
SATA
SATA_90D
SATA
SATA_90D
SATA
SATA_90D
SATA
SATA_90D
SATA
SATA_90D
SATA
SATA_90D
SATA
SATA_90D
SATA
LVDS_IG_B_DATA_P & lt; 2..0 & gt;
LVDS_IG_B_DATA_N & lt; 2..0 & gt;
SATA_HDD_R2D_C_P
SATA_HDD_R2D_C_N
SATA_HDD_D2R_P
SATA_HDD_D2R_N
SATA_SSD_D2R_MUX_OUT_P
SATA_SSD_D2R_MUX_OUT_N
SATA_SSD_R2D_MUX_IN_P
SATA_SSD_R2D_MUX_IN_N
SATA_SSD_D2R_P
SATA_SSD_D2R_N
SATA_SSD_R2D_P
SATA_SSD_R2D_N
SATA_90D
SATA
SATA_HDD_R2D_UF_P
SATA_90D
SATA
SATA_HDD_R2D_UF_N
SATA_90D
SATA
SATA_90D
SATA
SATA_90D
SATA
SATA_90D
SATA
SATA_90D
SATA
SATA_90D
TABLE_SPACING_RULE_ITEM
?
LVDS_85D
LVDS_IG_B_DATA
=4:1_SPACING
LVDS_85D
LVDS_IG_A_DATA3
D
ISL3,ISL4,ISL9,ISL10
LVDS_85D
LVDS_IG_A_DATA3
LVDS
LVDS_IG_A_CLK
LVDS_IG_A_DATA
TABLE_SPACING_RULE_ITEM
LVDS_IG_A_CLK
LVDS_IG_A_DATA
ISL3,ISL4,ISL9,ISL10
SATA
SATA_90D
SATA
SOURCE: HR PLATFORM DESIGN GUIDE, TABLES 191,193
SATA Interface Constraints
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
SATA_90D
*
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
TABLE_PHYSICAL_RULE_ITEM
SATA_HDD_D2R
TABLE_PHYSICAL_RULE_ITEM
SATA_37SE
*
=37_OHM_SE
=37_OHM_SE
=37_OHM_SE
=37_OHM_SE
=37_OHM_SE
=37_OHM_SE
SATA_HDD_D2R
TABLE_PHYSICAL_RULE_ITEM
SATA_50SE
*
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
SATA_HDD_R2D
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
=5:1_SPACING
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
?
LAYER
LINE-TO-LINE SPACING
WEIGHT
=5:1_SPACING
?
TABLE_SPACING_RULE_ITEM
SATA
ISL3,ISL4,ISL9,ISL10
I232
I233
TABLE_SPACING_RULE_ITEM
SATA
TOP,BOTTOM
SATA_HDD_D2R
I234
SATA_HDD_R2D
TABLE_SPACING_RULE_ITEM
SATA_ICOMP
*
15 MIL
I235
?
I218
SATA_HDD_R2D
I219
9 18
9 18
9 18
D
9 18
9 18
9 18
9 18
9 18
17 39
17 39
17 39
17 39
39
39
39
39
39
39
39
39
SOURCE: HR PLATFORM DESIGN GUIDE, TABLES 191,193
SATA_90D
SATA
SATA_ODD_R2D_C_P
SATA_ODD_R2D_C_N
SATA_ODD_R2D_P
SATA_ODD_R2D_N
SATA_ODD_D2R_P
SATA_ODD_D2R_N
SATA_ODD_D2R_UF_P
SATA_ODD_D2R_UF_N
PCH_SATA3_ICOMP
SATA_50SE
SATA_ICOMP
PCH_SATA3COMP
17
PCH_SATA_ICOMP
SATA_37SE
SATA_ICOMP
PCH_SATAICOMP
17
USB_HUB1_UP
USB_85D
USB
USB_85D
USB
USB_85D
USB
USB_85D
USB
USB_85D
USB
USB_85D
USB
USB_85D
USB
USB_85D
USB
USB_85D
USB
USB_85D
USB
USB_85D
USB
USB_85D
USB
USB_85D
USB
USB_85D
USB
USB_85D
USB
USB_85D
USB
USB_85D
USB
USB_85D
USB
USB_85D
USB
USB_85D
USB
USB_85D
USB
USB_85D
USB
USB_IR
USB_85D
USB
USB_85D
USB
PCH_USB_RBIAS
PCH_USB_RBIAS
USB_RBIAS
USB_T29A
USB_85D
USB
USB_85D
USB
USB_85D
USB
USB_85D
USB
USB_85D
USB
USB_85D
USB
USB_85D
USB
USB_85D
USB
USB_85D
USB3
USB_85D
USB3
USB_85D
USB3
USB_85D
USB3
USB_85D
USB3
USB_85D
USB3
USB_85D
USB3
USB_85D
USB3
USB_85D
USB3
USB_85D
USB3
USB_85D
USB3
USB_85D
USB3
USB_EXTB_XHCI_P
USB_EXTB_XHCI_N
USB_EXTB_EHCI_P
USB_EXTB_EHCI_N
USB_HUB_UP_P
USB_HUB_UP_N
USB_EXTA_P
USB_EXTA_N
USB_EXTB_P
USB_EXTB_N
USB_EXTC_P
USB_EXTC_N
USB_CAMERA_CONN_P
USB_CAMERA_CONN_N
USB_BT_P
USB_BT_N
USB_BT_CONN_P
USB_BT_CONN_N
USB_BT_WAKE_P
USB_BT_WAKE_N
USB_TPAD_P
USB_TPAD_N
USB_SMC_P
USB_SMC_N
PCH_USB_RBIAS
USB_EXTD_XHCI_P
USB_EXTD_XHCI_N
USB_EXTA_MUXED_P
USB_EXTA_MUXED_N
USB_CAMERA_P
USB_CAMERA_N
USB_LT1_P
USB_LT1_N
USB3_EXTB_TX_P
USB3_EXTB_TX_N
USB3_EXTB_RX_P
USB3_EXTB_RX_N
USB3_EXTC_TX_P
USB3_EXTC_TX_N
USB3_EXTC_RX_P
USB3_EXTC_RX_N
USB3_EXTA_TX_P
USB3_EXTA_TX_N
USB3_EXTA_RX_P
USB3_EXTA_RX_N
SATA_ODD_R2D
SATA_ODD_R2D
C
SATA_ODD_D2R
SATA_ODD_D2R
USB 2.0 Interface Constraints
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
I213
DIFFPAIR NECK GAP
9 17
9 17
C
9 17
9 17
TABLE_PHYSICAL_RULE_ITEM
PCH_USB_RBIAS
*
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
I236
TABLE_PHYSICAL_RULE_ITEM
USB_85D
*
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
I237
USB_HUB1_UP
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
=4:1_SPACING
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
?
LAYER
LINE-TO-LINE SPACING
WEIGHT
=4:1_SPACING
?
USB_HUB2_UP
TABLE_SPACING_RULE_ITEM
USB
ISL3,ISL4,ISL9,ISL10
TABLE_SPACING_RULE_ITEM
USB
TOP,BOTTOM
TABLE_SPACING_RULE_ITEM
USB_RBIAS
*
15 MIL
USB_EXTA
?
USB_EXTB
USB_EXTC
SOURCE: HR PLATFORM DESIGN GUIDE, TABLES 191,193
USB_CAMERA
USB_BT
USB_BT
USB 3.0 INTERFACE CONSTRAINTS
I260
TABLE_SPACING_RULE_HEAD
B
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_ITEM
USB3
ISL3,ISL4,ISL9,ISL10
=5:1_SPACING
I259
TABLE_SPACING_RULE_HEAD
WEIGHT
USB_BT
USB_TPAD
TABLE_SPACING_RULE_ITEM
?
USB3
TOP,BOTTOM
=5:1_SPACING
?
SOURCE: CR SFF PLATFORM DESIGN GUIDE V0.7, TABLE 4-211, 1X1+
I238
I239
I245
System Clock Signal Constraints
I244
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
=55_OHM_SE
=55_OHM_SE
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
I247
DIFFPAIR NECK GAP
*
=55_OHM_SE
=55_OHM_SE
=STANDARD
USB_CAMERA
I246
TABLE_PHYSICAL_RULE_ITEM
CLK_SLOW_55S
USB_EXTA
=STANDARD
I248
USB_EXTA
TABLE_PHYSICAL_RULE_ITEM
CLK_25M_55S
*
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
I249
=STANDARD
I220
I221
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
USB3_EXTB_TX
WEIGHT
I222
USB3_EXTB_RX
TABLE_SPACING_RULE_ITEM
CLK_SLOW
*
=2x_DIELECTRIC
I223
?
I224
TABLE_SPACING_RULE_ITEM
CLK_25M
*
=5x_DIELECTRIC
?
NOTE: 25MHz system clocks very sensitive to noise.
USB3_EXTC_TX
I225
I226
USB3_EXTC_RX
I227
I230
USB3_EXTA_TX
I229
I228
USB3_EXTA_RX
I231
A
19 26
19 26
19 26
19 26
19 26
19 26
19 40
19 40
7 26 38
7 26 38
9 19
9 19
7 34
7 34
9 34
9 34
7 34
7 34
34
34
9 49
9 41
9 41
19
19 26
19 26
40
40
19 34
19 34
40
40
19 38
19 38
7 19 38
7 19 38
9 19
9 19
9 19
9 19
19 40
19 40
19 40
19 40
Clock Net Properties
ELECTRICAL_CONSTRAINT_SET
B
9 49
SYNC_MASTER=D2_KEPLER
SYNC_DATE=01/13/2012
PAGE TITLE
NET_TYPE
PHYSICAL
SPACING
PCH Constraints 1
DRAWING NUMBER
I256
I255
SYSCLK_CLK32K_RTC
SYSCLK_CLK25M_SB
I254
I253
SYSCLK_CLK25M_ENET
I252
I251
SYSCLK_CLK25M_TBT
I250
8
7
6
5
4
CLK_SLOW_55S
CLK_25M_55S
CLK_25M_55S
CLK_25M_55S
CLK_25M_55S
CLK_25M_55S
CLK_25M_55S
CLK_SLOW
CLK_25M
CLK_25M
CLK_25M
CLK_25M
CLK_25M
CLK_25M
SYSCLK_CLK32K_RTC
SYSCLK_CLK25M_SB
SYSCLK_CLK25M_SB_R
SYSCLK_CLK25M_ENET
SYSCLK_CLK25M_ENET_R
SYSCLK_CLK25M_TBT
SYSCLK_CLK25M_TBT_R
3
17 25
Apple Inc.
R
17 25
17
25 35
35
051-9589
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
2
SIZE
D
REVISION
4.18.0
BRANCH
PAGE
102 OF 132
SHEET
91 OF 99
1
A
8
7
6
5
LPC Bus Constraints
4
2
3
1
PCH Net Properties
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
NET_TYPE
TABLE_PHYSICAL_RULE_ITEM
LPC_50S
*
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
CLK_LPC_50S
*
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
ELECTRICAL_CONSTRAINT_SET
=STANDARD
PHYSICAL
SPACING
=STANDARD
TABLE_PHYSICAL_RULE_ITEM
LPC_AD & lt; 3..0 & gt;
LPC_FRAME_L
LPC_RESET_L
LPC_AD
LPC_RESET_L
PCH_LPC_CLK0
CLK_LPC
CLK_LPC
CLK_LPC
SMB_50S
SMB
SMB_50S
SMB
SMBUS_PCH_0_CLK
SMB_50S
SMB
SMBUS_PCH_0_DATA
SMB_50S
SMB
SMBUS_PCH_1_CLK
SMB_50S
SMB
SMBUS_PCH_1_DATA
SMB_50S
SMB
HDA_BIT_CLK
HDA_50S
HDA
HDA_50S
HDA
HDA_50S
HDA
HDA_50S
HDA
HDA_50S
HDA
HDA_50S
HDA
HDA_50S
HDA
HDA_50S
HDA
HDA_50S
HDA
HDA_50S
HDA
SPI_55S
SPI
SPI_55S
SPI
SPI_55S
SPI
SPI_55S
SPI
SPI_MISO
SPI_55S
SPI
SPI_CS0
SPI_55S
SPI
SPI_55S
SPI
PCIE_85D
PCIE
PCIE_85D
PCIE
PCIE_85D
PCIE
PCIE_85D
PCIE
PCIE_85D
PCIE
PCIE_85D
PCIE
PCIE_85D
PCIE
PCIE_85D
PCIE
PCIE_85D
PCIE
PCIE_85D
PCIE
PCIE_85D
PCIE
PCIE_85D
PCIE
PCIE_85D
PCIE
PCIE_85D
6 MIL
CLK_LPC_50S
SMBUS_PCH_DATA
*
LPC
PCIE
PCIE_85D
PCIE
PCIE_85D
PCIE
PCIE_85D
PCIE
PCIE_85D
PCIE
?
TABLE_SPACING_RULE_ITEM
CLK_LPC
*
8 MIL
?
D
SMBus Interface Constraints
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
*
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
DIFFPAIR NECK GAP
=STANDARD
HDA_BIT_CLK
HDA_BIT_CLK_R
HDA_SYNC
HDA_SYNC_R
HDA_RST_R_L
HDA_RST_L
HDA_SDIN0
AUD_SDI_R
HDA_SDOUT
HDA_SDOUT_R
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_ITEM
SMB
*
=2x_DIELECTRIC
HDA_SYNC
?
HDA_RST_L
HD Audio Interface Constraints
HDA_SDIN0
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
HDA_SDOUT
TABLE_PHYSICAL_RULE_ITEM
HDA_50S
*
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
LPC_CLK33M_SMC_R
LPC_CLK33M_SMC
LPC_CLK33M_LPCPLUS
SMBUS_PCH_CLK
SMBUS_PCH_DATA
SML_PCH_0_CLK
SML_PCH_0_DATA
SML_PCH_1_CLK
SML_PCH_1_DATA
TABLE_PHYSICAL_RULE_ITEM
SMB_50S
7 17 41 43 82
7 17 41 43 82
25
WEIGHT
TABLE_SPACING_RULE_ITEM
LPC
LPC_50S
CLK_LPC_50S
LINE-TO-LINE SPACING
LPC
SMBUS_PCH_CLK
LAYER
LPC_50S
CLK_LPC_50S
SPACING_RULE_SET
LPC
LPC_FRAME_L
TABLE_SPACING_RULE_HEAD
LPC_50S
19 25
25 41
7 25 43
D
17 44
17 44
17 44
17 44
17 44
17 44
17 53
17
17 53
17
17
17 53
17 53
53
17 53
17 25
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
=2x_DIELECTRIC
?
SPI_CLK
SPI_CLK_R
SPI_CLK
SPI_MOSI_R
SPI_MOSI
SPI_MISO
SPI_CS0_R_L
SPI_CS0_L
TABLE_SPACING_RULE_ITEM
HDA
*
SPI_MOSI
SIO Signal Constraints
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
17 43
43
17 43
43
17 43
17 43
43
TABLE_PHYSICAL_RULE_ITEM
*
SPACING_RULE_SET
C
CLK_SLOW_55S
LAYER
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
TABLE_SPACING_RULE_HEAD
LINE-TO-LINE SPACING
PCIE_ENET_R2D
WEIGHT
TABLE_SPACING_RULE_ITEM
CLK_SLOW
*
8 MIL
?
PCIE_ENET_D2R
SPI Interface Constraints
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM
SPI_55S
*
SPACING_RULE_SET
LAYER
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
PCIE_AP_R2D
TABLE_SPACING_RULE_HEAD
LINE-TO-LINE SPACING
PCIE_AP_D2R
WEIGHT
PCIE_ENET_R2D_P
PCIE_ENET_R2D_N
PCIE_ENET_R2D_C_P
PCIE_ENET_R2D_C_N
PCIE_ENET_D2R_P
PCIE_ENET_D2R_N
PCIE_ENET_D2R_C_P
PCIE_ENET_D2R_C_N
PCIE_AP_R2D_P
PCIE_AP_R2D_N
PCIE_AP_R2D_C_P
PCIE_AP_R2D_C_N
PCIE_AP_D2R_P
PCIE_AP_D2R_N
C
7 17 38
7 17 38
7 17 38
7 17 38
7 34
7 34
17 34
17 34
17 34
17 34
TABLE_SPACING_RULE_ITEM
SPI
*
8 MIL
?
I275
PCIE_AP_D2R
I276
I278
PCIE_AP_D2R
I277
PCIE_TBT_D2R
PCIE_85D
PCIE
PCIE_85D
PCIE
PCIE_85D
PCIE
PCIE_85D
PCIE
PCIE_85D
PCIE
PCIE_85D
PCIE
PCIE_85D
PCIE
PCIE_85D
PCIE
PCIE_85D
PCIE
PCIE_85D
PCIE
PCIE_85D
PCIE
PCIE_85D
PCIE
CLK_PCIE_90D
CLK_PCIE
CLK_PCIE_90D
CLK_PCIE
CLK_PCIE_90D
CLK_PCIE
CLK_PCIE_90D
CLK_PCIE
CLK_PCIE_90D
CLK_PCIE
CLK_PCIE_90D
CLK_PCIE
CLK_PCIE_90D
CLK_PCIE
I259
CLK_PCIE_90D
CLK_PCIE
I258
CPU_50S
CLK_PCIE
I260
CPU_50S
CLK_PCIE
1:1_DIFFPAIR
CLK_PCIE
1:1_DIFFPAIR
CLK_PCIE
CLK_PCIE_90D
CLK_PCIE
CLK_PCIE_90D
CLK_PCIE
CLK_PCIE_90D
CLK_PCIE
CLK_PCIE_90D
CLK_PCIE
CLK_PCIE_90D
CLK_PCIE
CLK_PCIE_90D
CLK_PCIE
CLK_PCIE_90D
CLK_PCIE
CLK_PCIE_90D
CLK_PCIE
CLK_PCIE_90D
CLK_PCIE
CLK_PCIE_90D
CLK_PCIE
CLK_PCIE_90D
CLK_PCIE
CLK_PCIE_90D
CLK_PCIE
PCIE_TBT_R2D
PCIE_TBT_D2R
PCIE_TBT_R2D
B
I271
PCIE_TBT_D2R
I273
I274
PCIE_TBT_R2D
I272
I253
PCIE_CLK100M
I254
I262
PCIE_CLK100M_TBT_
I261
I255
I257
I256
I279
PCIE_CLK100M_TBT_
PCIE_CLK100M
I280
PCIE_CLK100M
PCIE_CLK100M_ENET
PCIE_CLK100M_AP
PCIE_CLK100M_FW
A
I281
PCIE_CLK100M_FW
I282
PCIE_CLK100M_EXCARD
I263
PCIE
PCIE_TBT_R2D
PCIE_85D
PCIE
PCIE_TBT_D2R
PCIE_85D
PCIE
I268
PCIE_TBT_D2R
PCIE_85D
PCIE
I270
PCIE_TBT_D2R
PCIE_85D
PCIE
I269
5
PCIE
PCIE_85D
I266
6
PCIE
PCIE_85D
PCIE_TBT_R2D
I267
7
PCIE_85D
PCIE_TBT_R2D
I265
8
PCIE_TBT_R2D
I264
PCIE_TBT_D2R
PCIE_85D
PCIE
4
PCIE_AP_D2R_PI_P
PCIE_AP_D2R_PI_N
PCIE_AP_R2D_PI_P
PCIE_AP_R2D_PI_N
PCIE_SSD_D2R_MUX_OUT_P
PCIE_SSD_D2R_MUX_OUT_N
PCIE_SSD_R2D_C_P & lt; 1..0 & gt;
PCIE_SSD_R2D_C_N & lt; 1..0 & gt;
PCIE_SSD_D2R_P & lt; 1..0 & gt;
PCIE_SSD_D2R_N & lt; 1..0 & gt;
PCIE_SSD_R2D_MUX_IN_P
PCIE_SSD_R2D_MUX_IN_N
PCIE_SSD_D2R_C_P & lt; 1 & gt;
PCIE_SSD_D2R_C_N & lt; 1 & gt;
PCIE_SSD_R2D_P & lt; 1 & gt;
PCIE_SSD_R2D_N & lt; 1 & gt;
PCIE_CLK100M_PCH_P
PCIE_CLK100M_PCH_N
PCIE_CLK100M_TBT_P
PCIE_CLK100M_TBT_N
PCH_CLK96M_DOT_P
PCH_CLK96M_DOT_N
PCH_CLK100M_SATA_P
PCH_CLK100M_SATA_N
PCH_CLK14P3M_REFCLK
PCH_CLK33M_PCIIN
PEX_TSTCLK_O_P
PEX_TSTCLK_O_N
PEG_CLK100M_P
PEG_CLK100M_N
PCIE_CLK100M_ENET_P
PCIE_CLK100M_ENET_N
PCIE_CLK100M_AP_P
PCIE_CLK100M_AP_N
PCIE_CLK100M_FW_P
PCIE_CLK100M_FW_N
PCIE_CLK100M_SSD_P
PCIE_CLK100M_SSD_N
PCIE_CLK100M_EXCARD_P
PCIE_CLK100M_EXCARD_N
PCIE_TBT_R2D_C_P & lt; 3..0 & gt;
PCIE_TBT_R2D_C_N & lt; 3..0 & gt;
PCIE_TBT_R2D_P & lt; 3..0 & gt;
PCIE_TBT_R2D_N & lt; 3..0 & gt;
PCIE_TBT_D2R_P & lt; 3..0 & gt;
PCIE_TBT_D2R_N & lt; 3..0 & gt;
PCIE_TBT_D2R_C_P & lt; 3..0 & gt;
PCIE_TBT_D2R_C_N & lt; 3..0 & gt;
3
7 34
7 34
34
34
39
39
9 39
9 39
9 39
9 39
39
B
39
39
39
39
39
17
17
17 35
17 35
17
17
17
17
17
17 25
71 95
71 95
17 71
17 71
7 17 38
7 17 38
17 34
17 34
9 17
9 17
17 39
17 39
9 17
SYNC_MASTER=D2_KEPLER
SYNC_DATE=01/13/2012
PAGE TITLE
PCH Constraints 2
9 17
DRAWING NUMBER
9 35
9 35
Apple Inc.
35
051-9589
R
9 35
35
35
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
2
D
4.18.0
35
9 35
SIZE
REVISION
BRANCH
PAGE
103 OF 132
SHEET
92 OF 99
1
A
8
7
6
5
DisplayPort Signal Constraints
4
3
NET_TYPE
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
SPACING
Thunderbolt SPI Signal Constraints
TBT_A_R2D
TBTDP_85D
TBTDP
TBT_A_R2D
TBTDP_85D
TBTDP
TBTDP_85D
TBTDP
TBTDP_85D
TBTDP
DP_TBTPA_ML
DP_85D
DISPLAYPORT
DP_TBTPA_ML
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
TBTDP_85D
TBTDP
TBTDP_85D
TBTDP
TBT_A_D2R
TBTDP_85D
TBTDP
TBT_A_D2R
TBTDP_85D
TBTDP
TBT_A_AUXCH
DP_85D
DISPLAYPORT
TBT_A_AUXCH
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
TABLE_PHYSICAL_RULE_HEAD
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM
TBT_SPI_55S
*
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
=2x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
TBT_SPI
D
*
1
Thunderbolt/DP Net Properties
NOTE: DisplayPort Physical/Spacing Constraints provided by Chipset or GPU page.
PHYSICAL_RULE_SET
2
Thunderbolt/DP Connector Signal Constraints
TBT_A_R2D_C_P & lt; 1..0 & gt;
TBT_A_R2D_C_N & lt; 1..0 & gt;
TBT_A_R2D_P & lt; 1..0 & gt;
TBT_A_R2D_N & lt; 1..0 & gt;
DP_TBTPA_ML_C_P & lt; 3..1:2 & gt;
DP_TBTPA_ML_C_N & lt; 3..1:2 & gt;
DP_TBTPA_ML_P & lt; 3..1:2 & gt;
DP_TBTPA_ML_N & lt; 3..1:2 & gt;
DP_A_LSX_ML_P & lt; 1 & gt;
DP_A_LSX_ML_N & lt; 1 & gt;
7 35 84
7 35 84
7 84
7 84
35 84
35 84
84
D
84
84
84
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TBTDP_80D
*
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TBTDP_85D
*
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
TBT_A_D2R_C_P & lt; 1..0 & gt;
TBT_A_D2R_C_N & lt; 1..0 & gt;
TBT_A_D2R_P & lt; 1..0 & gt;
TBT_A_D2R_N & lt; 1..0 & gt;
7 84
7 84
7 35 84
7 35 84
TABLE_PHYSICAL_RULE_ITEM
TBTDP_100D
*
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_ITEM
TBTDP
*
=5x_DIELECTRIC
TABLE_SPACING_RULE_ITEM
?
TBTDP
TOP,BOTTOM
=7x_DIELECTRIC
?
DP_85D
DISPLAYPORT
TBTDP_85D
TBTDP
TBTDP_85D
TBTDP
TBT_B_R2D
TBTDP_85D
TBTDP
TBT_B_R2D
TBTDP_85D
TBTDP
TBTDP_85D
TBTDP
TBTDP_85D
TBTDP
DP_TBTPB_ML
DP_85D
DISPLAYPORT
DP_TBTPB_ML
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
TBTDP_85D
TBTDP
TBTDP_85D
TBTDP
TBT_B_D2R
TBTDP_85D
TBTDP
TBT_B_D2R
TBTDP_85D
TBTDP
TBT_B_AUXCH
DP_85D
DISPLAYPORT
TBT_B_AUXCH
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
NOTE: Thunderbolt high-speed nets are NOT directly assigned to TBTDP_*D physical rules.
TABLE_PHYSICAL_ASSIGNMENT symbols must be used to create the assignments.
Proper differential impedance depends on mDP connector used.
For 514-0637: R2D nets (SMT pins) = 80D, D2R nets (TH pins) = 100D
SOURCE: Bill Cornelius’s Thunderbolt Routing Notes
C
DP_85D
DISPLAYPORT
TBTDP_85D
TBTDP
TBTDP_85D
TBT_B_D2R
TBTDP
DP_TBTPA_AUXCH_C_P
DP_TBTPA_AUXCH_C_N
DP_TBTPA_AUXCH_P
DP_TBTPA_AUXCH_N
DP_A_AUXCH_DDC_P
DP_A_AUXCH_DDC_N
TBT_A_D2R1_AUXDDC_P
TBT_A_D2R1_AUXDDC_N
TBT_B_R2D_C_P & lt; 1..0 & gt;
TBT_B_R2D_C_N & lt; 1..0 & gt;
TBT_B_R2D_P & lt; 1..0 & gt;
TBT_B_R2D_N & lt; 1..0 & gt;
DP_TBTPB_ML_C_P & lt; 3..1:2 & gt;
DP_TBTPB_ML_C_N & lt; 3..1:2 & gt;
DP_TBTPB_ML_P & lt; 3..1:2 & gt;
DP_TBTPB_ML_N & lt; 3..1:2 & gt;
DP_B_LSX_ML_P & lt; 1 & gt;
DP_B_LSX_ML_N & lt; 1 & gt;
TBT_B_D2R_C_P & lt; 1..0 & gt;
TBT_B_D2R_C_N & lt; 1..0 & gt;
TBT_B_D2R_P & lt; 1..0 & gt;
TBT_B_D2R_N & lt; 1..0 & gt;
DP_TBTPB_AUXCH_C_P
DP_TBTPB_AUXCH_C_N
DP_TBTPB_AUXCH_P
DP_TBTPB_AUXCH_N
DP_B_AUXCH_DDC_P
DP_B_AUXCH_DDC_N
TBT_B_D2R1_AUXDDC_P
TBT_B_D2R1_AUXDDC_N
35 84
35 84
84
84
84
84
84
84
7 35 85
7 35 85
7 85
7 85
35 85
35 85
85
85
85
C
85
7 85
Only used on dual-port hosts.
7 85
7 35 85
7 35 85
35 85
35 85
85
85
85
85
85
85
Thunderbolt IC Net Properties
NET_TYPE
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
SPACING
DP_85D
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
TBT_SPI_CLK
TBT_SPI_55S
TBT_SPI
TBT_SPI_MOSI
TBT_SPI_55S
TBT_SPI
TBT_SPI_MISO
TBT_SPI_55S
TBT_SPI
TBT_SPI_CS_L
B
DISPLAYPORT
TBT_SPI_55S
TBT_SPI
DP_TBTSRC_ML_C_P & lt; 3..0 & gt;
DP_TBTSRC_ML_C_N & lt; 3..0 & gt;
DP_TBTSRC_AUXCH_C_P
DP_TBTSRC_AUXCH_C_N
TBT_SPI_CLK
TBT_SPI_MOSI
TBT_SPI_MISO
TBT_SPI_CS_L
A
Only used on hosts supporting Thunderbolt video-in
35
35
B
35
35
SYNC_MASTER=D2_KEPLER
SYNC_DATE=01/13/2012
PAGE TITLE
Thunderbolt Constraints
DRAWING NUMBER
Apple Inc.
051-9589
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
4.18.0
BRANCH
PAGE
105 OF 132
SHEET
93 OF 99
1
A
8
7
6
5
4
3
2
1
SMC SMBus Net Properties
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
1TO1_DIFFPAIR
*
=STANDARD
=STANDARD
=STANDARD
=STANDARD
0.1 MM
NET_TYPE
DIFFPAIR NECK GAP
0.1 MM
ELECTRICAL_CONSTRAINT_SET
SPACING
PHYSICAL
TABLE_PHYSICAL_RULE_ITEM
SMBUS_SMC_2_S3_SCL
SMB
SMBUS_SMC_2_S3_SDA
SMB_50S
SMB
SMBUS_SMC_1_S0_SCL
SMB_50S
SMB
SMBUS_SMC_1_S0_SDA
SMB_50S
SMB
SMBUS_SMC_0_S0_SCL
SMB_50S
SMB
SMBUS_SMC_0_S0_SDA
SMB_50S
SMB
SMBUS_SMC_5_SCL
SMB_50S
SMB
SMBUS_SMC_5_SDA
SMB_50S
SMB
SMBUS_SMC_3_SCL
SMB_50S
SMB
SMBUS_SMC_3_SDA
D
SMB_50S
SMB_50S
SMB
SMBUS_SMC_2_S3_SCL
SMBUS_SMC_2_S3_SDA
SMBUS_SMC_1_S0_SCL
SMBUS_SMC_1_S0_SDA
SMBUS_SMC_0_S0_SCL
SMBUS_SMC_0_S0_SDA
SMBUS_SMC_5_SCL
SMBUS_SMC_5_SDA
SMBUS_SMC_3_SCL
SMBUS_SMC_3_SDA
7 41 44
7 41 44
41 44
41 44
41 44
41 44
D
41 44
41 44
SMBus Charger Net Properties
NET_TYPE
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
CHGR_CSI
1TO1_DIFFPAIR
1TO1_DIFFPAIR
CHGR_CSO
1TO1_DIFFPAIR
1TO1_DIFFPAIR
SPACING
CHGR_CSI_P
CHGR_CSI_N
61
61
CHGR_CSO_P
CHGR_CSO_N
61
61
C
C
B
B
A
SYNC_MASTER=D2_KEPLER
SYNC_DATE=01/13/2012
PAGE TITLE
SMC Constraints
DRAWING NUMBER
Apple Inc.
051-9589
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
3
2
SIZE
D
REVISION
4.18.0
BRANCH
PAGE
106 OF 132
SHEET
94 OF 99
1
A
8
7
6
5
GDDR5 Frame Buffer Signal Constraints
4
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
3
GDDR5 FB A Net Properties
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
2
NET_TYPE
DIFFPAIR NECK GAP
ELECTRICAL_CONSTRAINT_SET
1
GDDR5 FB B Net Properties
PHYSICAL
NET_TYPE
ELECTRICAL_CONSTRAINT_SET
SPACING
PHYSICAL
SPACING
TABLE_PHYSICAL_RULE_ITEM
GDDR5_45R50SE
*
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
12.7 MM
=STANDARD
I453
TABLE_PHYSICAL_RULE_ITEM
GDDR5_45SE
*
=45_OHM_SE
=45_OHM_SE
=45_OHM_SE
=STANDARD
=45_OHM_SE
=STANDARD
I454
TABLE_PHYSICAL_RULE_ITEM
GDDR5_80D
*
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
=80_OHM_DIFF
I452
=80_OHM_DIFF
I451
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_ITEM
GDDR5_CLK
*
=5x_DIELECTRIC
D
*
=3x_DIELECTRIC
?
GDDR5_CLK
TOP,BOTTOM
*
=3x_DIELECTRIC
*
=5x_DIELECTRIC
I447
TABLE_SPACING_RULE_ITEM
?
GDDR5_CMD
TOP,BOTTOM
?
=4x_DIELECTRIC
I446
TABLE_SPACING_RULE_ITEM
?
GDDR5_DATA
TOP,BOTTOM
I445
?
=5x_DIELECTRIC
TABLE_SPACING_RULE_ITEM
GDDR5_EDC
I449
?
=5x_DIELECTRIC
TABLE_SPACING_RULE_ITEM
GDDR5_DATA
I448
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
GDDR5_CMD
I450
TABLE_SPACING_RULE_HEAD
WEIGHT
I444
TABLE_SPACING_RULE_ITEM
?
GDDR5_EDC
TOP,BOTTOM
?
=5x_DIELECTRIC
I442
I443
Digital Video Signal Constraints
I440
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
I441
DIFFPAIR NECK GAP
I439
TABLE_PHYSICAL_RULE_ITEM
DP_85D
*
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
=85_OHM_DIFF
I437
TABLE_PHYSICAL_RULE_ITEM
HDMI_90D
*
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
=90_OHM_DIFF
I438
=90_OHM_DIFF
I435
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
DISPLAYPORT
*
=3x_DIELECTRIC
TABLE_SPACING_RULE_HEAD
?
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
DISPLAYPORT
TOP,BOTTOM
=4x_DIELECTRIC
?
TABLE_SPACING_RULE_ITEM
*
=3x_DIELECTRIC
I402
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
HDMI
I436
I400
I401
TABLE_SPACING_RULE_ITEM
?
HDMI
TOP,BOTTOM
=4x_DIELECTRIC
?
I398
I399
DisplayPort/TMDS intra-pair matching should be 0.127mm.
DIsplayPort AUX CH intra-pair matching should be 0.127mm.
Inter-pair matching should be within 2.54cm.
I397
Max Length 241.3mm.
I395
Max length 330.2mm.
I396
MAX LENGTH OF DISPLAYPORT/TMDS TRACES: 13 INCHES.
I394
SOURCE: Calpella SFF DG Rev 1.5 (407364) and Family GPU DG-04202-001-v04.
I392
I393
I390
I391
I389
I388
C
I387
I385
I386
I384
I383
I382
I380
I381
I379
I378
I377
I376
I375
I374
I373
I372
I371
FB_A0_CLK
FB_A0_CLK
FB_A1_CLK
FB_A1_CLK
FB_A0_CMD
FB_A1_CMD
FB_A0_CMD
FB_A1_CMD
FB_A0_CMD
FB_A1_CMD
FB_A0_CMD
FB_A1_CMD
FB_A0_CMD
FB_A1_CMD
FB_A0_CMD_R
FB_A1_CMD_R
FB_A0_CMD
FB_A1_CMD
FB_A0_EDC0
FB_A0_EDC1
FB_A0_EDC2
FB_A0_EDC3
FB_A1_EDC0
FB_A1_EDC1
FB_A1_EDC2
FB_A1_EDC3
FB_A0_DBI_L0
FB_A0_DBI_L1
FB_A0_DBI_L2
FB_A0_DBI_L3
FB_A1_DBI_L0
FB_A1_DBI_L1
FB_A1_DBI_L2
FB_A1_DBI_L3
FB_A0_WCLK0
FB_A0_WCLK0
FB_A0_WCLK1
FB_A0_WCLK1
FB_A1_WCLK0
FB_A1_WCLK0
FB_A1_WCLK1
FB_A1_WCLK1
FB_A0_DQ_BYTE0
FB_A0_DQ_BYTE1
FB_A0_DQ_BYTE2
FB_A0_DQ_BYTE3
FB_A1_DQ_BYTE0
FB_A1_DQ_BYTE1
FB_A1_DQ_BYTE2
FB_A1_DQ_BYTE3
FB_A0_CMD_R
FB_A1_CMD_R
GDDR5_80D
GDDR5_80D
GDDR5_80D
GDDR5_80D
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_80D
GDDR5_80D
GDDR5_80D
GDDR5_80D
GDDR5_80D
GDDR5_80D
GDDR5_80D
GDDR5_80D
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_CLK
GDDR5_CLK
GDDR5_CLK
GDDR5_CLK
GDDR5_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_EDC
GDDR5_EDC
GDDR5_EDC
GDDR5_EDC
GDDR5_EDC
GDDR5_EDC
GDDR5_EDC
GDDR5_EDC
GDDR5_DATA
GDDR5_DATA
GDDR5_DATA
GDDR5_DATA
GDDR5_DATA
GDDR5_DATA
GDDR5_DATA
GDDR5_DATA
GDDR5_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_DATA
GDDR5_DATA
GDDR5_DATA
GDDR5_DATA
GDDR5_DATA
GDDR5_DATA
GDDR5_DATA
GDDR5_DATA
GDDR5_CMD
GDDR5_CMD
FB_A0_CLK_P
FB_A0_CLK_N
FB_A1_CLK_P
FB_A1_CLK_N
FB_A0_A & lt; 8..0 & gt;
FB_A1_A & lt; 8..0 & gt;
FB_A0_ABI_L
FB_A1_ABI_L
FB_A0_RAS_L
FB_A1_RAS_L
FB_A0_CAS_L
FB_A1_CAS_L
FB_A0_WE_L
FB_A1_WE_L
FB_A0_CKE_L
FB_A1_CKE_L
FB_A0_CS_L
FB_A1_CS_L
FB_A0_EDC & lt; 0 & gt;
FB_A0_EDC & lt; 1 & gt;
FB_A0_EDC & lt; 2 & gt;
FB_A0_EDC & lt; 3 & gt;
FB_A1_EDC & lt; 0 & gt;
FB_A1_EDC & lt; 1 & gt;
FB_A1_EDC & lt; 2 & gt;
FB_A1_EDC & lt; 3 & gt;
FB_A0_DBI_L & lt; 0 & gt;
FB_A0_DBI_L & lt; 1 & gt;
FB_A0_DBI_L & lt; 2 & gt;
FB_A0_DBI_L & lt; 3 & gt;
FB_A1_DBI_L & lt; 0 & gt;
FB_A1_DBI_L & lt; 1 & gt;
FB_A1_DBI_L & lt; 2 & gt;
FB_A1_DBI_L & lt; 3 & gt;
FB_A0_WCLK_P & lt; 0 & gt;
FB_A0_WCLK_N & lt; 0 & gt;
FB_A0_WCLK_P & lt; 1 & gt;
FB_A0_WCLK_N & lt; 1 & gt;
FB_A1_WCLK_P & lt; 0 & gt;
FB_A1_WCLK_N & lt; 0 & gt;
FB_A1_WCLK_P & lt; 1 & gt;
FB_A1_WCLK_N & lt; 1 & gt;
FB_A0_DQ & lt; 7..0 & gt;
FB_A0_DQ & lt; 15..8 & gt;
FB_A0_DQ & lt; 23..16 & gt;
FB_A0_DQ & lt; 31..24 & gt;
FB_A1_DQ & lt; 7..0 & gt;
FB_A1_DQ & lt; 15..8 & gt;
FB_A1_DQ & lt; 23..16 & gt;
FB_A1_DQ & lt; 31..24 & gt;
FB_A0_RESET_L
FB_A1_RESET_L
73 75
73 75
I474
73 75
I472
73 75
I470
73 75
I471
73 75
FB_B0_CLK
FB_B0_CLK
FB_B1_CLK
FB_B1_CLK
FB_B0_CMD
FB_B1_CMD
FB_B0_CMD
FB_B1_CMD
FB_B0_CMD
FB_B1_CMD
FB_B0_CMD
FB_B1_CMD
FB_B0_CMD
FB_B1_CMD
FB_B0_CMD_R
FB_B1_CMD_R
FB_B0_CMD
FB_B1_CMD
FB_B0_EDC0
FB_B0_EDC1
FB_B0_EDC2
FB_B0_EDC3
FB_B1_EDC0
FB_B1_EDC1
FB_B1_EDC2
FB_B1_EDC3
FB_B0_DBI_L0
FB_B0_DBI_L1
FB_B0_DBI_L2
FB_B0_DBI_L3
FB_B1_DBI_L0
FB_B1_DBI_L1
FB_B1_DBI_L2
FB_B1_DBI_L3
FB_B0_WCLK0
FB_B0_WCLK0
FB_B0_WCLK1
FB_B0_WCLK1
FB_B1_WCLK0
FB_B1_WCLK0
FB_B1_WCLK1
FB_B1_WCLK1
FB_B0_DQ_BYTE0
FB_B0_DQ_BYTE1
FB_B0_DQ_BYTE2
FB_B0_DQ_BYTE3
FB_B1_DQ_BYTE0
FB_B1_DQ_BYTE1
FB_B1_DQ_BYTE2
FB_B1_DQ_BYTE3
FB_B0_CMD_R
FB_B1_CMD_R
I473
I468
73 75
I469
73 75
I467
73 75
I466
73 75
I465
73 75
I464
73 75
I463
73 75
I462
73 75
I460
73 75
I461
73 75
I459
73 75
I457
73 75
I458
73 75
I455
73 75
I456
73 75
I434
73 75
I433
73 75
I432
73 75
I430
73 75
I431
73 75
I429
73 75
I428
73 75
I427
73 75
I426
73 75
I424
73 75
I425
73 75
I423
73 75
I422
73 75
I421
73 75
I420
73 75
I419
73 75
I418
73 75
I417
73 75
I416
73 75
I414
73 75
I415
73 75
I412
73 75
I413
73 75
I411
73 75
I410
73 75
I409
73 75
I408
73 75
I407
73 75
I406
73 75
I404
73 75
I405
73 75
I403
GDDR5_80D
GDDR5_80D
GDDR5_80D
GDDR5_80D
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_80D
GDDR5_80D
GDDR5_80D
GDDR5_80D
GDDR5_80D
GDDR5_80D
GDDR5_80D
GDDR5_80D
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_45SE
GDDR5_CLK
GDDR5_CLK
GDDR5_CLK
GDDR5_CLK
GDDR5_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_EDC
GDDR5_EDC
GDDR5_EDC
GDDR5_EDC
GDDR5_EDC
GDDR5_EDC
GDDR5_EDC
GDDR5_EDC
GDDR5_DATA
GDDR5_DATA
GDDR5_DATA
GDDR5_DATA
GDDR5_DATA
GDDR5_DATA
GDDR5_DATA
GDDR5_DATA
GDDR5_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_CMD
GDDR5_DATA
GDDR5_DATA
GDDR5_DATA
GDDR5_DATA
GDDR5_DATA
GDDR5_DATA
GDDR5_DATA
GDDR5_DATA
GDDR5_CMD
GDDR5_CMD
FB_B0_CLK_P
FB_B0_CLK_N
FB_B1_CLK_P
FB_B1_CLK_N
FB_B0_A & lt; 8..0 & gt;
FB_B1_A & lt; 8..0 & gt;
FB_B0_ABI_L
FB_B1_ABI_L
FB_B0_RAS_L
FB_B1_RAS_L
FB_B0_CAS_L
FB_B1_CAS_L
FB_B0_WE_L
FB_B1_WE_L
FB_B0_CKE_L
FB_B1_CKE_L
FB_B0_CS_L
FB_B1_CS_L
FB_B0_EDC & lt; 0 & gt;
FB_B0_EDC & lt; 1 & gt;
FB_B0_EDC & lt; 2 & gt;
FB_B0_EDC & lt; 3 & gt;
FB_B1_EDC & lt; 0 & gt;
FB_B1_EDC & lt; 1 & gt;
FB_B1_EDC & lt; 2 & gt;
FB_B1_EDC & lt; 3 & gt;
FB_B0_DBI_L & lt; 0 & gt;
FB_B0_DBI_L & lt; 1 & gt;
FB_B0_DBI_L & lt; 2 & gt;
FB_B0_DBI_L & lt; 3 & gt;
FB_B1_DBI_L & lt; 0 & gt;
FB_B1_DBI_L & lt; 1 & gt;
FB_B1_DBI_L & lt; 2 & gt;
FB_B1_DBI_L & lt; 3 & gt;
FB_B0_WCLK_P & lt; 0 & gt;
FB_B0_WCLK_N & lt; 0 & gt;
FB_B0_WCLK_P & lt; 1 & gt;
FB_B0_WCLK_N & lt; 1 & gt;
FB_B1_WCLK_P & lt; 0 & gt;
FB_B1_WCLK_N & lt; 0 & gt;
FB_B1_WCLK_P & lt; 1 & gt;
FB_B1_WCLK_N & lt; 1 & gt;
FB_B0_DQ & lt; 7..0 & gt;
FB_B0_DQ & lt; 15..8 & gt;
FB_B0_DQ & lt; 23..16 & gt;
FB_B0_DQ & lt; 31..24 & gt;
FB_B1_DQ & lt; 7..0 & gt;
FB_B1_DQ & lt; 15..8 & gt;
FB_B1_DQ & lt; 23..16 & gt;
FB_B1_DQ & lt; 31..24 & gt;
FB_B0_RESET_L
FB_B1_RESET_L
73 76
73 76
73 76
73 76
73 76
73 76
73 76
73 76
D
73 76
73 76
73 76
73 76
73 76
73 76
73 76
73 76
73 76
73 76
73 76
73 76
73 76
73 76
73 76
73 76
73 76
73 76
73 76
73 76
73 76
73 76
73 76
73 76
73 76
73 76
73 76
C
73 76
73 76
73 76
73 76
73 76
73 76
73 76
73 76
73 76
73 76
73 76
73 76
73 76
73 76
73 76
73 76
73 76
MUXGFX & DP AUX MUX NET PROPERTIES
NET_TYPE
ELECTRICAL_CONSTRAINT_SET
DP_INT_ML
PHYSICAL
SPACING
DP_85D
DP_85D
B
I347
DP_INT_AUXCH
I336
I338
I337
I339
DP_INT_AUXCH
A
7
6
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DP_85D
DISPLAYPORT
DISPLAYPORT
DP_85D
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DP_85D
DISPLAYPORT
DISPLAYPORT
DP_85D
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_85D
DISPLAYPORT
DP_85D
5
DISPLAYPORT
DP_85D
DP_INT_ML
DP_85D
DP_85D
TBT_B_AUXCH
DP_INT_ML
I366
8
DP_85D
DP_85D
TBT_A_AUXCH
I362
I365
DISPLAYPORT
DP_85D
I361
I360
DISPLAYPORT
DP_85D
DP_INT_ML
I358
I359
DISPLAYPORT
DP_85D
DP_85D
I364
I357
DISPLAYPORT
DP_85D
DP_INT_ML
I356
I363
DP_85D
DP_85D
TBT_B_AUXCH
I354
I355
DISPLAYPORT
DP_85D
TBT_A_AUXCH
I352
I353
DISPLAYPORT
DP_85D
I340
I351
DISPLAYPORT
DP_85D
DP_INT_AUXCH
DISPLAYPORT
DP_85D
I335
DISPLAYPORT
DP_85D
DP_INT_AUXCH
DISPLAYPORT
DP_85D
I334
DISPLAYPORT
DP_85D
DP_INT_AUXCH
DISPLAYPORT
DP_85D
DP_INT_ML
DISPLAYPORT
DP_85D
DP_85D
I346
I333
DISPLAYPORT
DP_85D
DP_INT_ML
I344
I345
DP_85D
DP_85D
DP_INT_ML
I342
I343
DISPLAYPORT
DP_85D
DP_INT_AUXCH
I350
I341
DISPLAYPORT
DP_85D
I348
I349
DISPLAYPORT
DP_85D
DP_85D
DP_INT_AUXCH
DISPLAYPORT
DISPLAYPORT
DP_INT_ML_C_P & lt; 3..0 & gt;
DP_INT_ML_C_N & lt; 3..0 & gt;
DP_INT_AUX_C_P
DP_INT_AUX_C_N
DP_INT_AUX_P
DP_INT_AUX_N
DP_INT_EG_AUX_P
DP_INT_EG_AUX_N
DP_INT_ML_P & lt; 3..0 & gt;
DP_INT_ML_N & lt; 3..0 & gt;
DP_INT_ML_F_P & lt; 3..0 & gt;
DP_INT_ML_F_N & lt; 3..0 & gt;
DP_INT_EG_ML_P & lt; 3..0 & gt;
DP_INT_EG_ML_N & lt; 3..0 & gt;
DPA_IG_AUX_CH_P
DPA_IG_AUX_CH_N
DPB_IG_AUX_CH_P
DPB_IG_AUX_CH_N
DP_TBTSNK0_EG_AUXCH_P
DP_TBTSNK0_EG_AUXCH_N
DP_TBTSNK1_EG_AUXCH_P
DP_TBTSNK1_EG_AUXCH_N
DP_TBTSNK0_AUXCH_C_P
DP_TBTSNK0_AUXCH_C_N
DP_TBTSNK1_AUXCH_C_P
DP_TBTSNK1_AUXCH_C_N
DP_TBTSNK0_ML_C_P & lt; 3..0 & gt;
DP_TBTSNK0_ML_C_N & lt; 3..0 & gt;
DP_TBTSNK1_ML_C_P & lt; 3..0 & gt;
DP_TBTSNK1_ML_C_N & lt; 3..0 & gt;
DP_TBTSNK0_AUXCH_P
DP_TBTSNK0_AUXCH_N
DP_TBTSNK1_AUXCH_P
DP_TBTSNK1_AUXCH_N
DP_TBTSNK0_ML_P & lt; 3..0 & gt;
DP_TBTSNK0_ML_N & lt; 3..0 & gt;
DP_TBTSNK1_ML_P & lt; 3..0 & gt;
DP_TBTSNK1_ML_N & lt; 3..0 & gt;
4
81 82
Kepler Net Properties
81 82
81 82
NET_TYPE
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
B
SPACING
81 82
GPU_CLK27M
CLK_SLOW_55S
GPU_CLK27M
CLK_SLOW_55S
CLK_SLOW
GPU_CLK27M
CLK_SLOW_55S
CLK_SLOW
GPU_CLK27M
CLK_SLOW_55S
GPU_OSC_27M_XTALIN
GPU_OSC_27M_XTALOUT
GPU_OSC_27M_XTAL_BUFFOUT
GPU_OSC_27M_SSIN
CLK_SLOW
CLK_SLOW
7 81
7 81
77 82
77 78
77 78
77
77 82
7 81
7 81
81
81
77 82
77 82
18 83
18 83
18 83
PEX_TSTCLK_O_P
PEX_TSTCLK_O_N
1:1_DIFFPAIR
18 83
1:1_DIFFPAIR
71 92
71 92
77 83
77 83
HDMI_DATA
HDMI_90D
HDMI_90D
HDMI
HDMI_90D
HDMI
HDMI_90D
HDMI_EG_DATA_C_P & lt; 2..0 & gt;
HDMI_EG_DATA_C_N & lt; 2..0 & gt;
HDMI_EG_CLK_C_P
HDMI_EG_CLK_C_N
HDMI
HDMI
77 83
77 83
HDMI_CLK
7 35 83
7 38 77
7 38 77
7 38 77
7 38 77
7 35 83
7 35 83
7 35 83
7 35 77
7 35 77
7 35 77
SYNC_MASTER=D2_KEPLER
7 35 77
SYNC_DATE=01/13/2012
PAGE TITLE
7 35
GPU (Kepler) CONSTRAINTS
7 35
DRAWING NUMBER
7 35
7 35
Apple Inc.
7 35
051-9589
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
7 35
3
2
D
4.18.0
7 35
7 35
SIZE
REVISION
BRANCH
PAGE
107 OF 132
SHEET
95 OF 99
1
A
8
7
6
5
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
ALLOW ROUTE
ON LAYER?
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
4
3
D2 Specific Net Properties
2
1
D2 Specific Net Properties
NET_TYPE
NET_TYPE
TABLE_PHYSICAL_RULE_ITEM
SENSE_1TO1_55S
*
=55_OHM_SE
=1:1_DIFFPAIR
=55_OHM_SE
=55_OHM_SE
=1:1_DIFFPAIR
=1:1_DIFFPAIR
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
SPACING
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
SPACING
TABLE_PHYSICAL_RULE_ITEM
THERM_1TO1_55S
*
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=1:1_DIFFPAIR
SENSE_DIFFPAIR
CPUTHMSNS_D2_P
47
THERM
CPUTHMSNS_D2_N
THERM_1TO1_55S
THERM
DDR3THMSNS_D1_P
THERM_1TO1_55S
=1:1_DIFFPAIR
THERM
DDR3THMSNS_D1_N
THERM_1TO1_55S
THERM
THERM_1TO1_55S
=1:1_DIFFPAIR
TABLE_PHYSICAL_RULE_ITEM
DIFFPAIR
*
=1:1_DIFFPAIR
=1:1_DIFFPAIR
AUDIODIFF
*
=1:1_DIFFPAIR
0.1 MM
THERM_55S_CPUIMVPISNS1
*
=1:1_DIFFPAIR
=55_OHM_SE
=1:1_DIFFPAIR
=1:1_DIFFPAIR
0.1 MM
10 MM
0.1 MM
0.1 MM
=55_OHM_SE
=55_OHM_SE
0.2 MM
PCIE_CLK100M_AP
CLK_PCIE_90D
CLK_PCIE
47
CLK_PCIE_90D
CLK_PCIE
47
1TO1_DIFFPAIR
47
1TO1_DIFFPAIR
0.2 MM
SENSE_DIFFPAIR
TABLE_PHYSICAL_RULE_ITEM
PCIE_CLK100M_AP_CONN_P
PCIE_CLK100M_AP_CONN_N
CHGR_CSI_R_P
CHGR_CSI_R_N
CHGR_CSO_R_P
CHGR_CSO_R_N
7 34
7 34
61
61
GPUTHMSNS_D_P
47
THERM
GPUTHMSNS_D_N
47
THERM
GPU_TDIODE_P
47 77
(USB_EXTA)
USB_85D
USB
USB2_EXTA_MUXED_P
THERM
GPU_TDIODE_N
47 77
(USB_EXTA)
USB_85D
USB
USB2_EXTA_MUXED_N
SENSE_1TO1_55S
SENSE
VCCSAS0_CS_P
45 62
(USB_EXTA)
USB_85D
USB
SENSE
VCCSAS0_CS_N
45 62
(USB_EXTA)
USB_85D
USB
USB2_LT1_P
USB2_LT1_N
SENSE_1TO1_55S
SENSE
VCCSAISNS_R_P
45
USB_85D
USB
CONN_USB2_BT_P
SENSE_1TO1_55S
SENSE
VCCSAISNS_R_N
45
USB_85D
USB
SENSE_1TO1_55S
SENSE
ISNS_1V5_MEM_R_P
45
USB_85D
USB
SENSE_1TO1_55S
SENSE
ISNS_1V5_MEM_R_N
45
USB_85D
USB
SENSE_1TO1_55S
SENSE
CPUVCCIOS0_CS_P
45 67
AUDIODIFF
AUDIO
SPKRAMP_LIN_P
SENSE_1TO1_55S
SENSE
CPUVCCIOS0_CS_N
45 67
AUDIODIFF
AUDIO
SPKRAMP_LIN_N
57
SENSE_1TO1_55S
SENSE
CPUVCCIOISNS_R_P
45
AUDIODIFF
AUDIO
SPKRAMP_RIN_P
57
SENSE_1TO1_55S
D
THERM
SENSE_1TO1_55S
SENSE
CPUVCCIOISNS_R_N
45
AUDIODIFF
AUDIO
SPKRAMP_RIN_N
57
SENSE_1TO1_55S
SENSE
GPUISENS_N
AUDIODIFF
AUDIO
SSM2375SL_P
SENSE_1TO1_55S
SENSE
GPUISENS_P
AUDIODIFF
AUDIO
SSM2375SL_N
SENSE_1TO1_55S
SENSE
ISNS_1V5_MEM_N
45
AUDIODIFF
AUDIO
SSM2375SR_P
SENSE_1TO1_55S
SENSE_DIFFPAIR
THERM_1TO1_55S
THERM_1TO1_55S
SENSE_DIFFPAIR
THERM_1TO1_55S
THERM_1TO1_55S
TABLE_PHYSICAL_RULE_ITEM
SENSE
ISNS_1V5_MEM_P
45
AUDIODIFF
AUDIO
SENSE_1TO1_55S
SENSE
ISNS_AIRPORT_N
96
1TO1_DIFFPAIR
1TO1_DIFFPAIR
61
61
D
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
TABLE_SPACING_RULE_ITEM
CPU_COMP
GND
*
GND_P2MM
TABLE_SPACING_RULE_ITEM
CPU_VCCSENSE
GND
*
GND_P2MM
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
SENSE_DIFFPAIR
WEIGHT
TABLE_SPACING_ASSIGNMENT_ITEM
SENSE
*
=2:1_SPACING
?
THERM
*
=2:1_SPACING
?
AUDIO
*
=2:1_SPACING
?
SENSE_DIFFPAIR
TABLE_SPACING_ASSIGNMENT_ITEM
SENSE_DIFFPAIR
CONN_USB2_BT_N
USB_LT2_P
USB_LT2_N
TABLE_SPACING_RULE_ITEM
SENSE_DIFFPAIR
SENSE_DIFFPAIR
AUDIO_DIFFPAIR
AUDIO_DIFFPAIR
57
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
=STANDARD
?
SENSE_DIFFPAIR
TABLE_SPACING_RULE_ITEM
GND
*
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
I367
SENSE_DIFFPAIR
AUDIO_DIFFPAIR
I368
SPACING_RULE_SET
AUDIO_DIFFPAIR
TABLE_SPACING_ASSIGNMENT_ITEM
CLK_PCIE
GND
*
GND_P2MM
PCIE
GND
*
GND_P2MM
SATA
GND
*
GND_P2MM
TABLE_SPACING_ASSIGNMENT_ITEM
SENSE_DIFFPAIR
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
0.20 MM
1000
ISNS_AIRPORT_N
ISNS_AIRPORT_P
ISNS_AIRPORT_P
USB
GND
PWR_P2MM
*
0.20 MM
CLK_PCIE
SB_POWER
*
PWR_P2MM
SENSE_1TO1_55S
SENSE
ISNS_AIRPORT_R_N
NET_SPACING_TYPE2
AREA_TYPE
SENSE
ISNS_AIRPORT_R_P
SATA
SB_POWER
*
TABLE_SPACING_ASSIGNMENT_ITEM
GND
MEM_CLK
*
USB
SB_POWER
*
SENSE
ISNS_LCDBKLT_N
SENSE
ISNS_LCDBKLT_P
I390
GND_P2MM
I391
SENSE_1TO1_55S
SENSE
GPUFB_CS_P
74 99
GPUFB_CS_N
74 99
I360
GND
MEM_CTRL
SENSE_1TO1_55S
SENSE
ISNS_PP1V0_S0GPU_R_P
98
SENSE
ISNS_PP1V0_S0GPU_R_N
98
SENSE_1TO1_55S
SENSE
AUDIO
AUDIO
DIFFPAIR
AUDIO
AUDIO
DIFFPAIR
AUDIO
AUDIO
DIFFPAIR
AUDIO
AUDIO
DIFFPAIR
AUDIO
AUDIO
DIFFPAIR
AUDIO
DIFFPAIR
AUDIO
DIFFPAIR
AUDIO
DIFFPAIR
AUDIO
DIFFPAIR
AUDIO
DIFFPAIR
AUDIO
DIFFPAIR
AUDIO
DIFFPAIR
AUDIO
DIFFPAIR
AUDIO
DIFFPAIR
AUDIO
DIFFPAIR
AUDIO
DIFFPAIR
ISNS_PP1V8_S0GPU_P
SENSE_1TO1_55S
SENSE
ISNS_PP1V8_S0GPU_N
SENSE_1TO1_55S
SENSE
ISNS_PP1V8_S0GPU_R_P
SENSE
ISNS_PP1V8_S0GPU_R_N
SENSE_1TO1_55S
GND_P2MM
*
MEM_*_DQ_BYTE*
AUDIO
DIFFPAIR
DIFFPAIR
I359
SENSE_1TO1_55S
SENSE
P1V05_GPU_CS_P
74 98
SENSE_1TO1_55S
*
SENSE_DIFFPAIR
TABLE_SPACING_ASSIGNMENT_ITEM
GND
AUDIO
AUDIO
GND_P2MM
TABLE_SPACING_ASSIGNMENT_ITEM
C
AUDIO_DIFFPAIR
I392
SENSE
SENSE_1TO1_55S
*
DIFFPAIR
DIFFPAIR
AUDIO_DIFFPAIR
I389
SENSE_1TO1_55S
MEM_CMD
AUDIO
DIFFPAIR
AUDIO_DIFFPAIR
PWR_P2MM
TABLE_SPACING_ASSIGNMENT_ITEM
GND
AUDIO
DIFFPAIR
I387
I388
SENSE_DIFFPAIR
SENSE_1TO1_55S
SENSE_1TO1_55S
PWR_P2MM
DIFFPAIR
99
SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM
AUDIO
99
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
AUDIO_DIFFPAIR
I357
TABLE_SPACING_ASSIGNMENT_ITEM
1000
AUDIO
DIFFPAIR
I382
I358
SENSE_1TO1_55S
SENSE_DIFFPAIR
AUDIO
DIFFPAIR
96
GND_P2MM
*
TABLE_SPACING_RULE_ITEM
DIFFPAIR
96
SENSE
DIFFPAIR
96
SENSE
SENSE_1TO1_55S
SENSE_DIFFPAIR
TABLE_SPACING_ASSIGNMENT_ITEM
SSM2375SR_N
AUDIO
DIFFPAIR
SENSE
SENSE_1TO1_55S
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
*
GND_P2MM
AUDIO_DIFFPAIR
DIFFPAIR
DIFFPAIR
I381
SENSE_1TO1_55S
TABLE_SPACING_RULE_HEAD
AUDIO_DIFFPAIR
AUDIO_DIFFPAIR
TABLE_SPACING_ASSIGNMENT_HEAD
GND_P2MM
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
SENSE_DIFFPAIR
TABLE_SPACING_ASSIGNMENT_ITEM
GND
MEM_DQS
*
TABLE_SPACING_ASSIGNMENT_ITEM
GND_P2MM
LVDS
GND
*
SENSE_DIFFPAIR
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
MEM_40S
*
OVERRIDE
OVERRIDE
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
0.09 MM
100 MIL
OVERRIDE
OVERRIDE
AUDIO_DIFFPAIR
GND_P2MM
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
OVERRIDE
OVERRIDE
AUDIO_DIFFPAIR
SENSE
P1V05_GPU_CS_N
74 98
I393
SENSE_1TO1_55S
SENSE
ISNS_PP1V5_S0GPU_R_P
99
I394
SENSE_1TO1_55S
SENSE
ISNS_PP1V5_S0GPU_R_N
99
I396
SENSE_1TO1_55S
SENSE
CPUIMVP_ISNS1G_P
46 66
I395
46 66
TABLE_PHYSICAL_RULE_ITEM
OVERRIDE
OVERRIDE
SENSE_DIFFPAIR
TABLE_PHYSICAL_RULE_ITEM
MEM_72D
*
OVERRIDE
OVERRIDE
MEM_37S
*
OVERRIDE
OVERRIDE
0.09 MM
OVERRIDE
100 MIL
OVERRIDE
OVERRIDE
100 MIL
OVERRIDE
0.09 MM
OVERRIDE
OVERRIDE
SENSE_DIFFPAIR_42
OVERRIDE
OVERRIDE
SENSE_DIFFPAIR_42
SENSE_1TO1_55S
SENSE
CPUIMVP_ISNS1G_N
SENSE_DIFFPAIR
SENSE_1TO1_55S
SENSE
CPUIMVP_ISNS1G_R_P
SENSE
CPUIMVP_ISNS1G_R_N
SENSE
ISNS_HS_OTHER_P
46
I411
SENSE_1TO1_55S
SENSE
ISNS_HS_OTHER_N
46
I412
SENSE_1TO1_55S
SENSE
ISNS_HS_GPU_P
46
TABLE_PHYSICAL_RULE_ITEM
OVERRIDE
OVERRIDE
OVERRIDE
7 57 59
7 57 59
7 57 59
C
7 57 59
7 57 59
7 57 59
7 57 59
7 57 59
46
SENSE_1TO1_55S
AUDIO_DIFFPAIR
46
SENSE_1TO1_55S
AUDIO_DIFFPAIR
SPKRCONN_SL_OUT_P_R
SPKRCONN_SL_OUT_N_R
SPKRCONN_SL_OUT_P
SPKRCONN_SL_OUT_N
LSPKR_VSENSE_FILT_P
LSPKR_VSENSE_FILT_N
RSPKR_VSENSE_FILT_P
RSPKR_VSENSE_FILT_N
SPKRCONN_SR_OUT_P_R
SPKRCONN_SR_OUT_N_R
SPKRCONN_SR_OUT_P
SPKRCONN_SR_OUT_N
SPKRCONN_L_OUT_P
SPKRCONN_L_OUT_N
SPKRCONN_R_OUT_P
SPKRCONN_R_OUT_N
SPKRCONN_S_OUT_P
SPKRCONN_S_OUT_N
LSPKR_ISENSE_FILT_P
LSPKR_ISENSE_FILT_N
RSPKR_ISENSE_FILT_P
RSPKR_ISENSE_FILT_N
OVERRIDE
I409
AUDIO_DIFFPAIR
I410
RSUBIN_P
RSUBIN_N
57
57
TABLE_PHYSICAL_RULE_ITEM
MEM_85D
*
OVERRIDE
OVERRIDE
PCIE_85D
*
OVERRIDE
OVERRIDE
0.09 MM
OVERRIDE
OVERRIDE
OVERRIDE
0.09 MM
OVERRIDE
100 MIL
10 mm
OVERRIDE
SENSE_DIFFPAIR
OVERRIDE
OVERRIDE
TABLE_PHYSICAL_RULE_ITEM
OVERRIDE
OVERRIDE
OVERRIDE
0.1 MM
500 MIL
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
SENSE_DIFFPAIR
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
I414
SENSE_1TO1_55S
SENSE
ISNS_HS_GPU_N
SENSE
ISNS_HS_COMPUTING_P
46
SENSE
ISNS_HS_COMPUTING_N
AUDIO_DIFFPAIR
46
SENSE_1TO1_55S
SENSE_1TO1_55S
AUDIO_DIFFPAIR
46
TABLE_PHYSICAL_RULE_ITEM
USB_85D
TOP
OVERRIDE
OVERRIDE
SENSE_DIFFPAIR
I413
I415
AUDIO_DIFFPAIR
TABLE_PHYSICAL_RULE_ITEM
I416
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
OVERRIDE
CPUIMVP_ISNS_N
AUDIODIFF
AUDIO
ADC1_VSENSE_P
AUDIO
ADC1_VSENSE_N
AUDIODIFF
AUDIO
ADC2_VSENSE_P
AUDIO
ADC2_VSENSE_N
AUDIODIFF
AUDIO
ADC2_ISENSE_P
96
AUDIODIFF
AUDIO
ADC2_ISENSE_N
AUDIODIFF
AUDIO
ADC2_ISENSE_P
AUDIODIFF
AUDIO
ADC2_ISENSE_N
AUDIODIFF
AUDIO
SPKR_R_RSENSE_P
AUDIODIFF
AUDIO
SPKR_R_RSENSE_N
AUDIODIFF
AUDIO
SPKR_L_RSENSE_P
AUDIODIFF
AUDIO
SPKR_L_RSENSE_N
AUDIODIFF
AUDIO
AUD_LO1_L_P
53 57
AUDIODIFF
I345
AUDIO_DIFFPAIR
I346
B
I348
AUDIO_DIFFPAIR
I347
I350
AUDIO_DIFFPAIR
I349
I351
AUDIO_DIFFPAIR
I352
I353
AUDIO_DIFFPAIR
I354
I355
AUDIO_DIFFPAIR
I356
AUDIO_DIFFPAIR
AUDIO
AUD_LO1_L_N
53 57
AUDIODIFF
AUDIO
AUD_LO1_R_P
53 57
AUDIO
AUD_LO1_R_N
AUDIO_DIFFPAIR
53 57
AUDIODIFF
AUDIO
AUD_LO2_L_P
Graphics ,SATA Constraint Relaxations
AUDIO_DIFFPAIR
53 57
AUDIO
AUD_LO2_L_N
53 57
AUDIODIFF
AUDIO
AUD_LO2_R_P
53 57
AUDIO
AUD_LO2_R_N
53 57
AUDIODIFF
AUDIO
AUD_MIC_INL_P
53 58
53 58
Alternate diffpair width/gap through BGA fanout areas (95-ohm diff)
I417
AUDIO_DIFFPAIR
AUDIO_DIFFPAIR
AUDIODIFF
AUDIO
LSPKR_VSENSE_IN_P
I364
AUDIO_DIFFPAIR
AUDIODIFF
AUDIO
LSPKR_VSENSE_IN_N
I365
AUDIO_DIFFPAIR
AUDIODIFF
AUDIO
I366
AUDIO_DIFFPAIR
AUDIODIFF
AUDIO
RSPKR_VSENSE_IN_N
I371
AUDIO_DIFFPAIR
AUDIODIFF
AUDIO
LSPKR_ISENSE_RDIVIDE_P
96
I372
AUDIO_DIFFPAIR
AUDIODIFF
AUDIO
LSPKR_ISENSE_RDIVIDE_N
96
I376
AUDIO_DIFFPAIR
AUDIODIFF
AUDIO
RSPKR_ISENSE_RDIVIDE_P
AUDIODIFF
AUDIO
RSPKR_ISENSE_RDIVIDE_N
AUDIODIFF
AUDIO
LSPKR_VSENSE_RDIVIDE_P
AUDIODIFF
AUDIO
LSPKR_VSENSE_RDIVIDE_N
AUDIODIFF
AUDIO
RSPKR_VSENSE_RDIVIDE_P
AUDIODIFF
AUDIO
RSPKR_VSENSE_RDIVIDE_N
USB
USB_85D
AUDIO_DIFFPAIR
I344
I363
USB_85D
I343
57
SSM4321SR_P
SSM4321SR_N
SSM4321SL_P
SSM4321SL_N
46
AUDIODIFF
OVERRIDE
SENSE
AUDIODIFF
SENSE_DIFFPAIR
57
46
SENSE_1TO1_55S
100 MIL
CPUIMVP_ISNS_P
AUDIODIFF
0.23 MM
SENSE
AUDIODIFF
BOTTOM
SENSE_1TO1_55S
AUDIODIFF
CPU_27P4S
LSUBIN_P
LSUBIN_N
USB
96
I375
I378
AUDIO_DIFFPAIR
I379
I386
I385
AUDIO_DIFFPAIR
RSPKR_VSENSE_IN_P
B
NET_PHYSICAL_TYPE
AREA_TYPE
AUDIODIFF
AUDIO
AUD_SPKRAMP_LIN_P
AUDIO
AUD_SPKRAMP_LIN_N
AUD_SPKRAMP_RIN_P
PP3V3_S5
7 8
7 8
PP1V5_S3RS0_CPUDDR
8
57
AUDIO
26 49
57
AUDIODIFF
PP3V3_S0
SB_POWER
AUDIO
26 49
SB_POWER
AUDIODIFF
AUDIODIFF
I418
AUDIO_DIFFPAIR
AUDIO_DIFFPAIR
PHYSICAL_RULE_SET
AUD_MIC_INL_N
USB_TPAD_R_P
USB_TPAD_R_N
SB_POWER
TABLE_PHYSICAL_ASSIGNMENT_HEAD
57
TABLE_PHYSICAL_ASSIGNMENT_ITEM
LVDS_85D
BGA
LVDS_85D
DP_85D
BGA
100_DIFF_BGA
TABLE_PHYSICAL_ASSIGNMENT_ITEM
AUDIO_DIFFPAIR
TABLE_PHYSICAL_ASSIGNMENT_ITEM
SATA_90D
BGA
100_DIFF_BGA
AUDIODIFF
AUDIO
AUD_SPKRAMP_RIN_N
57
GND
CLK_PCIE_90D
BGA
AUD_SPKRAMP_LSUBIN_P
57
AUDIO
AUD_SPKRAMP_LSUBIN_N
57
AUDIODIFF
AUDIO
AUD_SPKRAMP_RSUBIN_P
57
AUDIO
AUD_SPKRAMP_RSUBIN_N
57
AUDIODIFF
AUDIO
LSPKR_INTIV_RSENSE_P
AUDIODIFF
AUDIO
LSPKR_INTIV_RSENSE_N
AUDIODIFF
AUDIO
RSPKR_INTIV_RSENSE_P
AUDIODIFF
AUDIO
RSPKR_INTIV_RSENSE_N
AUDIODIFF
AUDIO
LSPKR_INTIV_P
AUDIODIFF
AUDIO
LSPKR_INTIV_N
100_DIFF_BGA
I361
A
AUDIO
AUDIODIFF
AUDIO_DIFFPAIR
AUDIODIFF
AUDIODIFF
TABLE_PHYSICAL_ASSIGNMENT_ITEM
AUDIO_DIFFPAIR
I362
Memory Constraint Relaxations
I397
AUDIO_DIFFPAIR
I398
Allow 0.127 mm necks for & gt; 0.127 mm lines for ARD fanout.
I399
AUDIO_DIFFPAIR
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM
MEM_72D
BOTTOM
0.127 MM
6.35 MM
I400
I401
I403
TOP
0.1 MM
AUDIO_DIFFPAIR
I402
TABLE_PHYSICAL_RULE_ITEM
MEM_85D
I405
7
6
DRAWING NUMBER
Apple Inc.
AUDIODIFF
AUDIO
RSPKR_INTIV_P
AUDIO
RSPKR_INTIV_N
AUDIODIFF
AUDIO
ISNS_TBT_N
ISNS_TBT_P
99
AUDIODIFF
AUDIO
ISNS_TBT_R_N
99
AUDIO
ISNS_TBT_R_P
99
5
051-9589
SIZE
D
REVISION
99
AUDIO
AUDIODIFF
AUDIO_DIFFPAIR
I408
SYNC_DATE=03/15/2012
Project Specific Constraints
AUDIODIFF
AUDIO_DIFFPAIR
I406
I407
SYNC_MASTER=D2_CLEAN
PAGE TITLE
AUDIODIFF
AUDIO_DIFFPAIR
6.35 MM
I404
8
GND
4
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
3
2
4.18.0
BRANCH
PAGE
108 OF 132
SHEET
96 OF 99
1
A
8
7
6
5
4
3
2
1
15 " MBP BOARD-SPECIFIC SPACING & PHYSICAL CONSTRAINTS
TABLE_BOARD_INFO
BOARD LAYERS
BOARD AREAS
BOARD UNITS
(MIL or MM)
ALLEGRO
VERSION
TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM
NO_TYPE,BGA
MM
16.2
Stackup-Defined Spacing Rules
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM
DEFAULT
*
Y
=50_OHM_SE
=50_OHM_SE
10 MM
0 MM
0 MM
STANDARD
*
Y
=DEFAULT
=DEFAULT
10 MM
=DEFAULT
=DEFAULT
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
55_OHM_SE
TOP,BOTTOM
Y
0.090 MM
0.090 MM
Note: Outer dielectric is 0.058 mm nominal,
Inner dielectric is 0.053 mm nominal.
TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
*
*
BGA
P072_SPACE
TABLE_PHYSICAL_RULE_HEAD
D
LAYER
LINE-TO-LINE SPACING
WEIGHT
DEFAULT
*
0.1 MM
?
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
TABLE_SPACING_RULE_ITEM
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_PHYSICAL_RULE_ITEM
*
Y
0.076 MM
0.076 MM
=STANDARD
=STANDARD
=STANDARD
TABLE_SPACING_RULE_ITEM
1:1_SPACING
?
0.116 MM
?
TOP,BOTTOM
0.174 MM
?
4:1_SPACING
TOP,BOTTOM
0.232 MM
?
TOP,BOTTOM
0.290 MM
?
1:1_SPACING
ISL3,ISL4,ISL9,ISL10
0.053 MM
?
2:1_SPACING
ISL3,ISL4,ISL9,ISL10
0.106 MM
?
3:1_SPACING
ISL3,ISL4,ISL9,ISL10
0.159 MM
?
ISL3,ISL4,ISL9,ISL10
0.212 MM
?
5:1_SPACING
ISL3,ISL4,ISL9,ISL10
0.265 MM
?
1:1_SPACING ISL2,ISL5,ISL6,ISL7,ISL8,ISL11
0.101 MM
?
2:1_SPACING ISL2,ISL5,ISL6,ISL7,ISL8,ISL11
0.202 MM
?
3:1_SPACING ISL2,ISL5,ISL6,ISL7,ISL8,ISL11
0.303 MM
?
4:1_SPACING ISL2,ISL5,ISL6,ISL7,ISL8,ISL11
0.404 MM
?
5:1_SPACING ISL2,ISL5,ISL6,ISL7,ISL8,ISL11
?
=DEFAULT
0.058 MM
5:1_SPACING
*
TOP,BOTTOM
3:1_SPACING
TABLE_SPACING_RULE_ITEM
STANDARD
TOP,BOTTOM
2:1_SPACING
4:1_SPACING
55_OHM_SE
D
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
TABLE_PHYSICAL_RULE_ITEM
0.505 MM
?
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
BGA_P1MM
*
?
0.1 MM
DIFFPAIR NECK GAP
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
50_OHM_SE
TOP,BOTTOM
Y
0.090 MM
0.090 MM
50_OHM_SE
*
Y
0.070 MM
0.070 MM
BGA_P2MM
*
0.2 MM
?
P072_SPACE
*
0.071 MM
?
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
=STANDARD
=STANDARD
=STANDARD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
45_OHM_SE
TOP,BOTTOM
Y
0.116 MM
0.116 MM
15 " MBP Specific Net Properties
TABLE_SPACING_RULE_ITEM
NET_TYPE
TABLE_PHYSICAL_RULE_ITEM
45_OHM_SE
*
Y
0.085 MM
LAYER
ALLOW ROUTE
ON LAYER?
0.085 MM
=STANDARD
=STANDARD
=STANDARD
ELECTRICAL_CONSTRAINT_SET
PHYSICAL
SPACING
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
TABLE_PHYSICAL_RULE_ITEM
40_OHM_SE
TOP,BOTTOM
Y
0.145 MM
TABLE_SPACING_RULE_ITEM
DIFFPAIR NECK GAP
0.095 MM
I1
40_OHM_SE
*
Y
0.105 MM
0.090 MM
AUDIODIFF
AUDIO
AUDIODIFF
AUDIO
ADC1_ISENSE_N
SENSE_DIFFPAIR_42
THERM_55S_CPUIMVPISNS1
THERM
CPUIMVP_ISNS1_P
46 65 66
THERM_55S_CPUIMVPISNS1
THERM
CPUIMVP_ISNS1_N
46 66
THERM_1TO1_55S
THERM
CPUIMVP_ISNS2G_P
46 66
THERM_1TO1_55S
THERM
CPUIMVP_ISNS2G_N
46 66
THERM_1TO1_55S
THERM
CPUIMVP_ISNS2_P
46 65 66
THERM_1TO1_55S
THERM
CPUIMVP_ISNS2_N
46 66
THERM_55S_CPUIMVPISNS1
THERM
CPUIMVP_ISNS3_P
46 65 66
THERM_55S_CPUIMVPISNS1
TABLE_SPACING_RULE_ITEM
I2
TABLE_PHYSICAL_RULE_ITEM
=STANDARD
=STANDARD
I3
=STANDARD
I4
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
37_OHM_SE
TOP,BOTTOM
Y
0.165 MM
0.095 MM
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
I5
I7
TABLE_PHYSICAL_RULE_ITEM
37_OHM_SE
C
*
Y
0.120 MM
0.090 MM
=STANDARD
=STANDARD
=STANDARD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
SENSE_DIFFPAIR
SENSE_DIFFPAIR
THERM
CPUIMVP_ISNS3_N
46 66
THERM_1TO1_55S
THERM
CPUIMVP_ISUM_R_P
46
THERM_1TO1_55S
THERM
CPUIMVP_ISUM_R_N
46
THERM_1TO1_55S
THERM
CPUIMVP_ISUMG_R_P
46
THERM_1TO1_55S
THERM
CPUIMVP_ISUMG_R_N
46
THERM_1TO1_55S
THERM
GFXIMVP_ISNS1_P
80
THERM_1TO1_55S
THERM
GFXIMVP_ISNS1_N
80
THERM_1TO1_55S
THERM
GFXIMVP_ISNS2_P
80
THERM_1TO1_55S
THERM
GFXIMVP_ISNS2_N
80
THERM_1TO1_55S
THERM
ISNS_CPU_DDR_R_P
98
THERM_1TO1_55S
I10
THERM
ISNS_CPU_DDR_R_N
98
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
27P4_OHM_SE
TOP,BOTTOM
Y
0.265 MM
0.095 MM
27P4_OHM_SE
*
Y
0.190 MM
0.1 MM
I11
SENSE_DIFFPAIR
I12
I13
SENSE_DIFFPAIR
=STANDARD
I15
TABLE_PHYSICAL_RULE_HEAD
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
72_OHM_DIFF
*
N
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
72_OHM_DIFF
ISL3,ISL4,ISL9,ISL10
Y
0.124 MM
0.124 MM
0.200 MM
0.200 MM
72_OHM_DIFF
ISL2,ISL11
Y
0.124 MM
0.124 MM
0.200 MM
0.200 MM
72_OHM_DIFF
TOP,BOTTOM
Y
0.140 MM
0.140 MM
0.120 MM
0.120 MM
TABLE_PHYSICAL_RULE_ITEM
I17
SENSE_DIFFPAIR
SENSE_DIFFPAIR
TABLE_PHYSICAL_RULE_ITEM
I20
TABLE_PHYSICAL_RULE_ITEM
I21
I23
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
80_OHM_DIFF
*
N
=STANDARD
=STANDARD
=STANDARD
=STANDARD
=STANDARD
I26
I28
TABLE_PHYSICAL_RULE_ITEM
ISL3,ISL4,ISL9,ISL10
Y
0.096 MM
0.096 MM
0.126 MM
0.126 MM
80_OHM_DIFF
ISL2,ISL11
Y
0.096 MM
0.096 MM
0.126 MM
0.126 MM
80_OHM_DIFF
0.120 MM
0.160 MM
0.120 MM
0.160 MM
TOP,BOTTOM
Y
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
THERM_1TO1_55S
THERM
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
85_OHM_DIFF
*
N
=STANDARD
=STANDARD
=STANDARD
=STANDARD
3x_DIELECTRIC
TOP,BOTTOM
0.174 MM
?
4x_DIELECTRIC
TOP,BOTTOM
0.232 MM
?
TOP,BOTTOM
0.290 MM
?
1x_DIELECTRIC
ISL3,ISL4,ISL9,ISL10
0.053 MM
?
2x_DIELECTRIC
ISL3,ISL4,ISL9,ISL10
0.106 MM
?
3x_DIELECTRIC
ISL3,ISL4,ISL9,ISL10
0.159 MM
?
4x_DIELECTRIC
ISL3,ISL4,ISL9,ISL10
0.212 MM
?
5x_DIELECTRIC
ISL3,ISL4,ISL9,ISL10
0.265 MM
?
1X_DIELECTRIC
ISL2,ISL5,ISL6,ISL7,ISL8,ISL11
0.101 MM
?
2x_DIELECTRIC
ISL2,ISL5,ISL6,ISL7,ISL8,ISL11
0.202 MM
?
3x_DIELECTRIC
ISL2,ISL5,ISL6,ISL7,ISL8,ISL11
0.303 MM
?
4x_DIELECTRIC
ISL2,ISL5,ISL6,ISL7,ISL8,ISL11
0.404 MM
?
0.505 MM
?
TABLE_SPACING_RULE_ITEM
ISNS_P1V5R1V35_CPUDDR_P
THERM
ISNS_P1V5R1V35_CPUDDR_N
THERM_1TO1_55S
THERM
ISNS_SSD_P
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
39 99
ISNS_SSD_N
39 99
THERM_1TO1_55S
THERM
ISNS_SSD_R_P
99
THERM_1TO1_55S
THERM
ISNS_SSD_R_N
99
SENSE_DIFFPAIR
THERM_1TO1_55S
THERM
PCHVCCIOS0_CS_P
87 99
THERM_1TO1_55S
THERM
PCHVCCIOS0_CS_N
87 99
SENSE_DIFFPAIR
THERM_1TO1_55S
THERM
PCH_VCCIOSENSE_P
87
THERM_1TO1_55S
THERM
PCH_VCCIOSENSE_N
87
TABLE_SPACING_RULE_ITEM
SENSE_DIFFPAIR
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
=STANDARD
I31
TABLE_SPACING_RULE_ITEM
I67
SENSE_DIFFPAIR
40_OHM_SE
THERM
GPUVCORE_SENSE_P
79 80
I68
SENSE_DIFFPAIR
40_OHM_SE
THERM
GPUVCORE_SENSE_N
79 80
TABLE_PHYSICAL_RULE_HEAD
?
5x_DIELECTRIC
THERM
I29
I32
0.116 MM
ISNS_LCD_PANEL_N
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TOP,BOTTOM
TABLE_SPACING_RULE_ITEM
ISNS_LCD_PANEL_P
THERM
THERM_1TO1_55S
I27
I30
2x_DIELECTRIC
TABLE_SPACING_RULE_ITEM
SENSE_DIFFPAIR
I25
TABLE_PHYSICAL_RULE_ITEM
THERM
THERM_1TO1_55S
SENSE_DIFFPAIR
I24
TABLE_PHYSICAL_RULE_HEAD
?
TABLE_SPACING_RULE_ITEM
THERM_1TO1_55S
THERM_1TO1_55S
SENSE_DIFFPAIR
I22
TABLE_PHYSICAL_RULE_ITEM
WEIGHT
0.058 MM
TABLE_SPACING_RULE_ITEM
I18
I19
LINE-TO-LINE SPACING
TOP,BOTTOM
TABLE_SPACING_RULE_ITEM
SENSE_DIFFPAIR
I16
PHYSICAL_RULE_SET
LAYER
1x_DIELECTRIC
5x_DIELECTRIC
ISL2,ISL5,ISL6,ISL7,ISL8,ISL11
I14
=STANDARD
80_OHM_DIFF
C
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET
TABLE_PHYSICAL_RULE_ITEM
=STANDARD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
I8
I9
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
SENSE_DIFFPAIR
I6
TABLE_PHYSICAL_RULE_ITEM
ADC1_ISENSE_P
AUDIO_DIFFPAIR
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
B
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
85_OHM_DIFF
ISL3,ISL4,ISL9,ISL10
Y
0.089 MM
0.089 MM
0.180 MM
ISL2,ISL11
Y
0.089 MM
0.089 MM
0.180 MM
0.180 MM
85_OHM_DIFF
TOP,BOTTOM
Y
0.110 MM
0.110 MM
0.180 MM
0.180 MM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
74 79
74 79
THERM_1TO1_55S
THERM_1TO1_55S
THERM_1TO1_55S
THERM
P1V05_GPU_PEX_IOVDD_SNS_N
SENSE_DIFFPAIR
THERM_1TO1_55S
THERM
SPKRL_THMSNS_D2_P
THERM_1TO1_55S
THERM
SPKRL_THMSNS_D2_N
SENSE_DIFFPAIR
THERM_1TO1_55S
THERM
SPKR_THMSNS_D2_P
THERM_1TO1_55S
THERM
SPKR_THMSNS_D2_N
THERM_1TO1_55S
THERM
TBT_THERMD_P
47
THERM_1TO1_55S
THERM
TBT_THERMD_N
47
THERM_1TO1_55S
THERM
X29THMSNS_D2_P
THERM_1TO1_55S
THERM
X29THMSNS_D2_N
THERM_1TO1_55S
THERM
VDDCIS0_CS_P
I56
TABLE_PHYSICAL_RULE_HEAD
ALLOW ROUTE
ON LAYER?
73 74
P1V05_GPU_PEX_IOVDD_SNS_P
I53
I33
LAYER
GPU_FBGND_SENSE
THERM
THERM
TABLE_PHYSICAL_RULE_ITEM
PHYSICAL_RULE_SET
THERM
DIFFPAIR NECK GAP
I34
I35
TABLE_PHYSICAL_RULE_ITEM
90_OHM_DIFF
*
N
=STANDARD
=STANDARD
90_OHM_DIFF
ISL3,ISL4,ISL9,ISL10
Y
0.081 MM
=STANDARD
=STANDARD
I36
=STANDARD
0.200 MM
0.081 MM
0.200 MM
TABLE_PHYSICAL_RULE_ITEM
I37
90_OHM_DIFF
ISL2,ISL11
Y
0.081 MM
0.081 MM
0.200 MM
TOP,BOTTOM
Y
0.099 MM
0.090 MM
0.200 MM
I39
0.200 MM
90_OHM_DIFF
SENSE_DIFFPAIR
I38
TABLE_PHYSICAL_RULE_ITEM
0.200 MM
TABLE_PHYSICAL_RULE_ITEM
SENSE_DIFFPAIR
I40
I57
SENSE_DIFFPAIR
I58
SENSE_DIFFPAIR
THERM_1TO1_55S
THERM
VDDCIS0_CS_N
I59
SENSE_DIFFPAIR
THERM_1TO1_55S
THERM
GFXIMVP6_VSEN_P
I60
SENSE_DIFFPAIR
THERM_1TO1_55S
THERM
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM
100_OHM_DIFF
*
N
=STANDARD
=STANDARD
=STANDARD
=STANDARD
ISL3,ISL4,ISL9,ISL10
Y
0.065 MM
0.065 MM
0.200 MM
ISL2,ISL11
Y
0.065 MM
0.065 MM
0.200 MM
100_OHM_DIFF
TOP,BOTTOM
Y
0.079 MM
0.079 MM
0.200 MM
USB3
USB_85D
USB3
I44
USB_85D
USB3
I45
USB_85D
USB3
USB_85D
USB3
I47
USB_85D
USB3
I48
USB_85D
USB3
I49
USB_85D
USB3
I50
USB_85D
USB3
I70
USB_85D
USB3
I69
0.200 MM
USB_85D
USB_85D
USB3
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
100_DIFF_BGA
*
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
100_DIFF_BGA
ISL3,ISL4
Y
0.075 MM
0.075 MM
0.125 MM
0.125 MM
100_DIFF_BGA
ISL9,ISL10
Y
0.075 MM
0.075 MM
0.125 MM
0.125 MM
TABLE_PHYSICAL_RULE_ITEM
USB3_EXTA_TX_F_P
USB3_EXTA_TX_F_N
USB3_EXTA_RX_F_P
USB3_EXTA_RX_F_N
USB3_EXTA_TX_C_P
USB3_EXTA_TX_C_N
USB3_EXTB_TX_C_P
USB3_EXTB_TX_C_N
USB3_EXTB_RX_RC_P
USB3_EXTB_RX_RC_N
USB3_EXTA_RX_RC_P
USB3_EXTA_RX_RC_N
USB3
I43
0.200 MM
USB_85D
I42
0.200 MM
100_OHM_DIFF
I41
I46
100_OHM_DIFF
A
GFXIMVP6_VSEN_N
=STANDARD
TABLE_PHYSICAL_RULE_ITEM
B
73 74
THERM_1TO1_55S
I55
0.180 MM
85_OHM_DIFF
GPU_FBVDDQ_SENSE
I54
40
40
7 38
7 38
38
38
SYNC_MASTER=D2_KEPLER
40
SYNC_DATE=01/13/2012
PAGE TITLE
40
PCB Rule Definitions
NOTE: 100_DIFF_BGA is 100-ohms differential impedance on outer layers and 95-ohms on inner layers.
DRAWING NUMBER
Apple Inc.
051-9589
R
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE
ON LAYER?
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP
1:1_DIFFPAIR
*
Y
=STANDARD
=STANDARD
=STANDARD
0.1 MM
I61
P1V5_GPU_VSNS
P1V0S0_VSNS
CLK_25M
I62
CLK_25M
0.1 MM
TABLE_PHYSICAL_RULE_ITEM
8
7
6
5
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
4
3
2
SIZE
D
REVISION
4.18.0
BRANCH
PAGE
109 OF 132
SHEET
97 OF 99
1
A
8
7
6
5
4
3
2
1
GPU 1.0V CURRENT SENSE
SENSOR_NONPROD:Y
SENSOR_NONPROD:Y
=PP5V_S3_DEBUG_ISNS
RD003
SENSOR_NONPROD:Y
1
8
1 CD043
2
PP5V_S3_DEBUG_ADC_AVDD_FILT
20%
10V
X7R-CERM
0402
1
SENSOR_NONPROD:Y
1
SENSOR_NONPROD:Y
P1V05_GPU_CS_P
96 74
P1V05_GPU_CS_N
1
2
V+
4.53K
1V0_GPU_IOUT
2
1
V-
402
THRM
4
2
1
2
ADC_CH4
98
AVDD
SENSOR_NONPROD:Y
1 CD042
2
2 96 ISNS_PP1V0_S0GPU_R_N
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
22
NC
PLACE_NEAR=UD000.4:5MM
ADC_CH1
23
98
ADC_CH2
24
98
ADC_CH3
1
98
1%
ADC_CH4
2
98
SENSOR_NONPROD:Y
402
SENSOR_NONPROD:Y
1
RD042
RD043
1M
2
1M
SIGNAL_MODEL=EMPTY
1
1%
1/16W
MF-LF
402
20%
6.3V
X5R
603
D
DVDD
UD000
10%
16V
CERM
402
1/16W
MF-LF
10UF
2
SENSOR_NONPROD:Y
0.22UF
4.22K
SENSOR_NONPROD:Y
20%
10V
CERM
402
CD012
0.1UF
20%
6.3V
X5R
603
SENSOR_NONPROD:Y
1%
1/16W
MF-LF
402
9
RD041
10UF
20%
10V
CERM
402
2
8
RD044
1
1%
MF-LF
2
PLACE_NEAR=UD000. 3:5MM
1/16W
D
IG2C
OPA2333
1
CD002
0.1UF
DFN
3
96 ISNS_PP1V0_S0GPU_R_P
1
CD001
SENSOR_NONPROD:Y
5%
1/16W
MF-LF
402
21
96 74
8
4.22K
SENSOR_NONPROD:Y
12
RD040
MIN_NECK_WIDTH=0.25MM
VOLTAGE=5V
SENSOR_NONPROD:Y
1
CD007
=PP5V_S3_DEBUG_ADC_DVDD
2
MIN_LINE_WIDTH=0.3MM
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.25MM
VOLTAGE=5V
UD080
SENSOR_NONPROD:Y
10
PP5V_S3_DEBUG_ADC_DVDD_FILT
2
5%
1/16W
MF-LF
402
0.1UF
EDP Current: 2.846A
RD018
10
=PP5V_S3_DEBUG_ADC_AVDD
13
98 8
2
3
NC
NC
NC
1%
1/16W
MF-LF
402
SIGNAL_MODEL=EMPTY
4
5
GAIN: 237X
RD007
AD0
AD1
QFN
14
1
SDA
SCL
5%
1/16W
MF-LF
402
17
RD002
ADC_SCL
VREF
REFCOMP
8
=I2C_SMC_ADCS_SCL
2
IN
44
5%
1/16W
MF-LF
402
ADC_VREF
ADC_REFCOMP
SENSOR_NONPROD:Y
SENSOR_NONPROD:Y
THRM
PAD
1
SENSOR_NONPROD:Y
1
CD004
CD006
10UF
20%
10V
CERM
402
2
1
CD000
0.1UF
25
20
19
18
11
10
GND
9
44
PLACE_NEAR=U4900.E4:10mm
33
1
7
BI
SENSOR_NONPROD:Y
ADC_SDA
16
=I2C_SMC_ADCS_SDA
2
15
SENSOR_NONPROD:Y
COM
6
PLACE_NEAR=U4900.F1:10mm
33
LTC2309
2.2UF
20%
6.3V
X5R
603
2
20%
6.3V
CERM
402-LF
2
CPU DDR CURRENT SENSE
98 8
=PP5V_S3_DEBUG_ISNS
SENSOR_NONPROD:Y
1 CD082
C
C
0.1UF
20%
10V
CERM
402
2
SENSOR_NONPROD:Y
EDP CURRENT: 5.0A
SENSOR_NONPROD:Y
69 7
IN
NC_ISNS_P1V5R1V35_CPUDDRP
UD082
RD081
7.68K
1
1
97 ISNS_CPU_DDR_R_P
2
SC70-5
V+
1%
PLACE_NEAR=UD000.4:5MM
OPA333DCKG4
5
+
RD085
1/16W
IC3C
SENSOR_NONPROD:Y
4.53K
4
ISNS_CPU_DDR_IOUT
1
ADC_CH2
2
98
MF-LF
3
-
2
RD082
69 7
IN
NC_ISNS_P1V5R1V35_CPUDDRN
1%
1/16W
MF-LF
402
V-
402
1
0.22UF
7.68K
1
2
97
ISNS_CPU_DDR_R_N
Gain: 130x
SENSOR_NONPROD:Y
SENSOR_NONPROD:Y
CD081
2
1%
1/16W
20%
6.3V
X5R
402
PLACE_NEAR=UD000.4:5MM
MF-LF
402
SENSOR_NONPROD:Y
1
SENSOR_NONPROD:Y
RD083
RD084
1M
1M
1%
SIGNAL_MODEL=EMPTY
1
1/16W
2
MF-LF
SENSOR_NONPROD:Y
2
1%
402
1/16W
SIGNAL_MODEL=EMPTY
LD000
MF-LF
402
120OHM-0.3A
1
=PP5V_S0_RMC
2
PP5V_S0_RMC_FLT
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=5V
0402
SENSOR_NONPROD:Y
PLACE_NEAR=RD305.1:5MM
PLACE_NEAR=CD010.1:2MM
=PPVCORE_S0_CPU
2
1
B
1
PPVCORE_S0_RMC
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.1V
2
CD009
99 45 8
10UF
1UF
SM
IN
1
CD010
XWD000
45 15 13 8
LCD PANEL CURRENT SENSE
SENSOR_NONPROD:Y
CPU_VCORE_C
2
SENSOR_NONPROD:Y
20%
6.3V
CERM-X5R
0402
10.2
=PP1V05_S0_RMC
1
100
2
5%
1/16W
MF-LF
402
2
2
0.1%
1/16W
TF
402
PP1V05_S0_RMC_R
DD000
PLACE_NEAR=UD000.22:5MM
ILDC
UD070
RD071
INA214
81 7
IN
NC_ISNS_LCD_PANELN
5
81 7
SOD-523
A
B
20%
10V
CERM
402
SENSOR_NONPROD:Y
V+
EDP CURRENT: 1.0A
SENSOR_NONPROD:Y
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
CD070
0.1UF
RD009
1
RD000
8
1
SENSOR_NONPROD:Y
10%
16V
X5R
402
SENSOR_NONPROD:Y
=PP3V3_S0_ISNS
3
8
IN
NC_ISNS_LCD_PANELP
4
ININ+
SC70
6
OUT
LCD_DRV_IOUT
ADC_CH3
2
K
REF
SENSOR_NONPROD:Y
4.53K
1
98
1%
1/16W
MF-LF
402
1
BAT54XV2T1
GND
1
SENSOR_NONPROD:Y
2
SENSOR_NONPROD:Y
CD003
SENSOR_NONPROD:Y
RD011 1
1
1
11K
10UF
20%
6.3V
CERM-X5R
0402
SENSOR_NONPROD:Y
0.1%
1/16W
MF
402
2
SENSOR_NONPROD:Y
1
RD001
2
2
GAIN: 100X
0.1%
1/16W
MF
402
2
10%
16V
X7R-CERM
0402
1
3
SENSOR_NONPROD:Y
NO_TEST=TRUE
5
+
V+
RD005
2
10.2
1
2
RD004
A
0.1%
1/16W
MF
402
1
0.1UF
10%
16V
X7R-CERM
0402
SENSOR_NONPROD:Y
1
11K
SENSOR_NONPROD:Y
CD005
1
RD006
10%
16V
X7R-CERM
0402
UD002
SOD-523
COMP_CPU_VCORE_RMC
V-
4
CPU_VCORE_RMC_DIV
-
A
K
CPU_VCORE_RMCP
3
5
+
V+
SENSOR_NONPROD:Y
VCRP
OPA365
RD020
SOT23
BAT54XV2T1
1
VSNS_CPU_VCORE_RMC_OUT
4.53K
1
ADC_CH1
2
NO_TEST=TRUE
2
0.1%
1/16W
TF
402
CPU_VCORE_RMCN
NO_TEST=TRUE
1%
1/16W
MF-LF
402
V-
4
-
2
2
OUT
98
SENSOR_NONPROD:Y
1
1.00K
2
PLACE_NEAR=UD000.22:5MM
SENSOR_NONPROD:Y
DD001
SOT23
NO_TEST=TRUE
NO_TEST=TRUE
SENSOR_NONPROD:Y
SENSOR_NONPROD:Y
OPA365
1
CD018
20%
6.3V
X5R
402
0.1UF
SENSOR_NONPROD:Y
UD001
1V05_S0_RMC_DIV
2
SENSOR_NONPROD:Y
0.1UF
1.00K
CD071
0.22UF
CD008
CD020
0.22UF
0.1%
1/16W
MF
402
2
SIGNAL_MODEL=EMPTY
2
SYNC_MASTER=D2_SEAN
SENSOR_NONPROD:Y
RD021
RD008
DEBUG SENSORS AND ADC
1K
10
1
SYNC_DATE=03/05/2012
PAGE TITLE
SENSOR_NONPROD:Y
PLACE_NEAR=RD305.1:5MM
10%
10V
CERM
402
1
2
DRAWING NUMBER
2
1%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
Apple Inc.
R
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8
7
6
5
4
051-9589
3
2
SIZE
D
REVISION
4.18.0
BRANCH
PAGE
130 OF 132
SHEET
98 OF 99
1
A
8
7
6
5
4
3
LCD BKLT Current Sense
99 8
2
1
TBT (T29) CURRENT SENSE
=PP5V_S3_ISNS
1
CD200
0.1UF
2
SENSOR_NONPROD:Y
20%
10V
CERM
402
99 98 45 8
=PP3V3_S0_ISNS
1
3
EDP Current: 0.715A
8
SENSOR_NONPROD:Y
V+
=PPBUS_SW_BKL
UD200
2
D
7
INA214
NC_ISNS_LCDBKLTN
5
XWD200
SM
7
RD201
4
NC_ISNS_LCDBKLTP
IN-
OUT
SC70
IN+
REF
6
1
SMC_LCDBKLT_ISENSE
2
1
RD259
ISNS_TBT_P
931
1
1%
1W
MF
0612
2
CD201
0.22UF
20%
6.3V
X5R
402
GAIN: 100X
2
=PP1V05_S0_P1V05TBTFET
GND_SMC_AVSS
96
931
1
ISNS_TBT_N
UD250
1
V+
2
PLACE_NEAR=UD4900.A8:5MM
4.53K
4
1
ISNS_TBT_IOUT
2
GAIN: 1074.11X
ISNS_TBT_R_N
SMC_TBT_ISENSE
2
1%
1/16W
MF-LF
402
V-
-
SMC_ADC23
RD255
SC70-5
1 CD250
PLACE_NEAR=U4900.A8:5MM
2
20%
6.3V
X5R
402
GND_SMC_AVSS 41
RD253
1M
1
1%
1/20W
MF
2 201
42 45 46
99
RD254
1M
=PP3V3_S0_ISNS
42
0.22UF
1%
1/20W
MF
201
41 42 45 46 99
D
IHSC
OPA333DCKG4
5
+
3
1
SSD CURRENT SENSE
20%
10V
CERM
402
ISNS_TBT_R_P
RD252
1 3
PLACE_NEAR=U4900.G1:5MM
37 8
2
1%
1/20W
MF
201
2 4
0.001
SENSOR_NONPROD:Y
1
SENSOR_NONPROD:Y
96
CRITICAL
GND
PPBUS_SW_LCDBKLT_PWR
=PP1V05_S0_P1V05TBTFET_R
8
42
1%
1/16W
MF-LF
402
1
86
2
RD251
4.53K
LCDBKLT_IOUT
CD251
0.1UF
SENSE RESISTOR 0.001 OHM
EDP CURRENT: 3.0 A
IBLC
SMC_ADC17
PLACE_NEAR=U4900.G1:5MM
2
1%
1/20W
MF
201
1 CD258
0.1UF
Sense Resistor 0.005 Ohm
EDP CURRENT: 5A
97 39
2
RD260
7.68K
ISNS_SSD_P
1
97 ISNS_SSD_R_P
2
UD240
OPA333DCKG4
1%
1/16W
1
MF-LF
402
5
+
3
1
4.53K
ISNS_SSD_IOUT
-
2
99 8
SMC_SSD_ISENSE
2
1%
1/16W
MF-LF
402
GAIN: 130X
97 ISNS_SSD_R_N
2
1
V-
7.68K
ISNS_SSD_N
RD264
4
=PP5V_S3_ISNS
42
1 CD282
1 CD240
0.22UF
20%
6.3V
X5R
402
1%
C
GPU FB (1.35V/1.5V) CURRENT SENSE
IHDC
SMC_ADC6
PLACE_NEAR=U4900.A3:5MM
SC70-5
V+
RD261
97 39
20%
10V
CERM
402
2
1/16W
MF-LF
402
0.1UF
EDP Current: 7.8A
Rsense(R8380)=0.002 Ohm
PLACE_NEAR=U4900.A3:5MM
2
UD280
RD281
8
1
GND_SMC_AVSS
RD262
96 74
1
V+
C
SMC_ADC19
4.53K
1
P1V5_S0GPU_IOUT
1
SMC_GPU_P1V35_ISENSE
2
42
1/16W
2
V-
2
MF-LF
1%
1/16W
MF-LF
402
402
SIGNAL_MODEL=EMPTY
1%
1/16W
MF-LF
402
SIGNAL_MODEL=EMPTY
RD285
DFN
3
1%
1M
1
1%
1/16W
MF-LF
402
96 ISNS_PP1V5_S0GPU_R_P
2
IG3C
PLACE_NEAR=U4900.H2:5MM
OPA2333
7.68K
GPUFB_CS_P
RD263
1M
2
41 42 45 46 99
20%
10V
CERM
402
THRM
4
RD282
96 74
1
CD281
0.22UF
9
7.68K
GPUFB_CS_N
1
96
2
20%
6.3V
X5R
402
ISNS_PP1V5_S0GPU_R_N
Gain: 130x
2
1%
1/16W
PLACE_NEAR=U4900.H2:5MM
MF-LF
402
GND_SMC_AVSS 41
1
42 45 46 99
RD283
1M
1%
www.qdzbwx.com
=PP3V3_S3_ISNS
8
RD284
1M
X29 AIRPORT CURRENT SENSE
1
1/16W
1%
402
SIGNAL_MODEL=EMPTY
1/16W
SIGNAL_MODEL=EMPTY
MF-LF
SENSOR_NONPROD:Y
1
2
MF-LF
2
402
CD230
0.1UF
2
RD230
SENSOR_NONPROD:Y
2.61K
34
PP3V3_WLAN_R
7
NC_ISNS_AIRPORTP
1
2
96 ISNS_AIRPORT_R_P
UD230
OPA333DCKG4
1%
1/16W
1
MF-LF
2
402
5
+
V+
XWD235
SM
3
RD231
1
PP3V3_WLAN_F
7
NC_ISNS_AIRPORTN
B
1
2
RD234
4
IAPC
SMC_ADC22
4.53K
ISNS_AIRPORT_IOUT
1
2
SMC_X29_ISENSE
1%
1/16W
MF-LF
402
2
PCH VCORE CURRENT SENSE
42
SENSOR_NONPROD:Y
1 CD231
96 ISNS_AIRPORT_R_N
0.22UF
GAIN: 383X
SENSOR_NONPROD:Y
1%
SENSOR_NONPROD:Y
PLACE_NEAR=U4900.B8:5MM
SC70-5
V-
-
2.61K
34
20%
10V
CERM
402
SENSOR_NONPROD:Y
2
1/16W
MF-LF
402
20%
6.3V
X5R
402
=PP3V3_S0_ISNS
99 98 45 8
1
SENSOR_NONPROD:Y
1
RD232
RD233
1M
2
GND_SMC_AVSS
2
V+
41 42 45 46 99
EDP CURRENT:6.0A
SIGNAL_MODEL=EMPTY
1M
1
1%
1/16W
MF-LF
402
2
CD221
0.1UF
20%
10V
CERM
402
SENSOR_NONPROD:Y
MF-LF
97 87
402
5 IN-
PCHVCCIOS0_CS_N
IN
SENSOR_NONPROD:Y
97 87
6
OUT
CRITICAL
SC70
PCH_CORE_IOUT
1
4.53K
1%
1/16W
MF-LF
402
REF 1
SMC_PCH_CORE_ISENSE
2
1
CD222
0.22UF
PLACE_NEAR=U4900.A7:5MM
2
2 402
GND_SMC_AVSS
QTY
116S0114
DESCRIPTION
4
REFERENCE DES
RES,MTL FILM,100K,5,1/16W,0402,SMD,LF
CRITICAL
42
SENSOR_NONPROD:Y
20%
6.3V
X5R
GND
PART NUMBER
SMC_ADC21
RD223
INA210
4 IN+
PCHVCCIOS0_CS_P
IN
ISBC
SENSOR_NONPROD:Y
PLACE_NEAR=U4900.A7:5mm
UD220
SENSOR_NONPROD:Y
1%
1/16W
SIGNAL_MODEL=EMPTY
B
PLACE_NEAR=U4900.B8:5MM
3
Sense Resistor 0.005 Ohm
EDP Current: 1.06A
41 42 45 46 99
Gain:200x
BOM OPTION
SENSOR_NONPROD:N
CD201,CD222,CD231
LCD BKLT Voltage Sense
XWD250
CPU VCCSA VOLTAGE SENSE
SM
86 81 7
PLACE_NEAR=R7140.1:2MM
XWD245
A
=PPVCCSA_S0_REG
2
1
VCCSA_VSENSE_IN
1
4.53K
1
2
VC2C
SMC_ADC20
RD214
SM
62 8
PPVOUT_S0_LCDBKLT
SMC_CPU_SA_VSENSE
2
1%
1/16W
MF-LF
402
1
0.22UF
2
RD256
100K
42
1 CD211
PLACE_NEAR=U4900.7:5MM
VOUT_S0_LCDBKLT_XW
2
1%
1/16W
MF-LF
402
VOUT_S0_LCDBKLT_DIV
PLACE_NEAR=U4900.B7:5MM
20%
6.3V
X5R
402
1
RD257
RD258
1
4.53K
1%
1/16W
MF-LF
402
SMC_LCDBKLT_VSENSE
2
0.22UF
1%
402
7
6
5
4
DRAWING NUMBER
42
2
20%
6.3V
X5R
402
3
051-9589
PLACE_NEAR=U4900.G2:5MM
41 42 45 46 99
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
2
SIZE
D
REVISION
R
GND_SMC_AVSS
8
SMC12 SENSORS EXTENDED
1 CD252
1/16W
MF-LF
SYNC_DATE=01/13/2012
PAGE TITLE
Apple Inc.
4.64K
2
SYNC_MASTER=D2_KEPLER
VBLC
SMC_ADC16
PLACE_NEAR=U4900.G2:5MM
4.18.0
BRANCH
PAGE
132 OF 132
SHEET
99 OF 99
1
A