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Xmega serii 128A1 - Przykłady ATmela w C

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  • xMega_official_drivers_and_examples.rar
    • XMEGA IO Pins and External Interrupts.zip
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xMega_official_drivers_and_examples.rar > XMEGA Interrupts and the Programmable Multi-level Interrupt Controller.pdf

AVR1305: XMEGA Interrupts and the
Programmable Multi-level Interrupt Controller
Features
o 3 interrupt levels
o Round-robin scheduling for low-level interrupts
o Programmable priority for low-level interrupts

8-bit
Microcontrollers
Application Note

1 Introduction
Microcontrollers use interrupts to prioritize between the tasks and to ensure that
certain peripheral modules are serviced fast. Further, interrupts can be used to
reduce the power consumption of a microcontroller, so that the device is in low
power mode until a certain interrupt causing condition occurs.
The XMEGA(TM) Interrupt mechanisms and the Programmable Multi-level Interrupt
Controller (PMIC) are described in this application note. The application note also
offers a C code example that shows how the PMIC can be accessed.

Rev. 8043A-AVR-02/08

2 Theory of Operation
Most (peripheral) modules have status flags, or interrupt flags, that can trigger
execution of an interrupt. An interrupt is when a module signals to the AVR(R) CPU
that the flow of the program code execution should be interrupted and a specific
Interrupt Service Routine (ISR) program code should be executed. An interrupt is
generated if all of the following requirements are meet:
o
o
o
o

The condition that sets the interrupt flag is fulfilled.
The specific interrupt is enabled in the module.
The interrupt level is enabled in the Interrupt Controller.
Global interrupts are enabled for the CPU.

The execution order of interrupts is determined first by their Interrupt Level and then
their Interrupt Priority. Interrupt Level is specified individually for the Interrupts in the
module where they originate, while the Interrupt Priority is determined by their fixed
Interrupt Vector Address. Alternatively, for low-level interrupts, the Interrupt Priority
can be based on a Round-robin scheme controlled by the Interrupt Controller.
The Non-Maskable Interrupt (NMI) is a special interrupt that cannot be disabled, and
is used to for system critical interrupts. NMI is used for critical failures such as a
failure in the crystal oscillator.

2.1 Interrupt Level - enabling a module interrupt
When a peripheral module needs to use an interrupt, it sets the Interrupt Level of the
corresponding interrupt to something else than "off". An interrupt can be given one of
three levels: low, medium and high. The bits controlling the enabling and level of an
interrupt are typically located in the INTCTRL registers.
When having multiple interrupt levels one should understand that when executing an
interrupt with a given level it is interruptible by an interrupt with higher level. This
means that an interrupt with low interrupt level can be interrupted by an interrupt with
medium or high level. Evidently, nested interrupts can occur and one should take this
into considerations when assessing the stack depth required by the firmware.
Also, one has to consider protection of access to registers and variables that are
more than 8 bits wide. Since the AVR data bus is 8-bit wide and access to multi-byte
variables requires execution of more than one instruction, it is possible that an
interrupt can occur between accessing the first and the second byte of a 16-bit (or 32bit variable). If a 16-bit variable used in the main loop of the code is modified by an
interrupt, the variable can be corrupted. The same situation applies if an interrupt is
interrupted by another interrupt with higher level. Corruption can be avoided in
several ways: One method is to ensure that a variable that can be modified by ISRs is
accessed in an atomic operation. This can by achieved through global disabling of
interrupts while accessing the variable. Another method, which applies when
accessing 16-bit registers (or rather, two 8-bit registers that together represent a 16bit value), is to preserve and restore the temporary register that is used by hardware
when accessing these registers. This method can be relevant e.g. when accessing
the 16-bit timer registers. More information about temporary registers and 16-bit
access to registers can be found in the datasheet.

2

AVR1305
8043A-AVR-02/08

AVR1305
2.2 Non Maskable Interrupt (NMI)
The XMEGA A1 device has one NMI source, the Crystal Oscillator Failure NMI.
If a crystal is used as system clock, the clock from the crystal oscillator is monitored.
If for some reason the crystal clock stops (e.g. due to physical damage to the crystal)
an NMI is generated and the internal 2 MHz RC oscillator takes over as system clock.
Since an NMI interrupt by definition cannot be disabled, there is no available
mechanism to disable the NMI from software once enabled. The only way to disable
the NMI is to reset the MCU, which will bring back the initial state where the NMI is
disabled. Refer to application note AVR1003 covering the XMEGA Clock System for
more information about crystal failure detection and the clock system in general.

2.3 Enabling Interrupt Levels in PMIC
Each interrupt level can be enabled individually. This can e.g. be desired in cases
where atomic operations, like the above-mentioned examples of reading 16-bit
registers, should not block high level interrupts. Consider that only low level interrupts
writes to the variable that should be protected, there is no reason to block medium
and high level interrupts, since they do not affect the variable anyway. The HILVLEN,
MEDLVLEN and LOLVLEN bits in PMIC CTRL register enable the individual levels.
It is important to take into consideration that the Global Interrupt bit (I-bit in SREG) is
not cleared when entering an interrupt, as opposed to the single level interrupt system
in megaAVR(TM) microcontrollers. The PMIC contains the mechanism that ensures that
interrupts having same level cannot interrupt each other. Please refer to the
description of the PMIC STATUS register found in the datasheet for more information.

2.4 Global Enabling of Interrupts
Even if interrupt levels are enabled in both the module and the PMIC, no interrupts
are executed unless the Global Interrupt bit is set for the CPU. The assembly
instructions SEI and CLI respectively enable and disable the global interrupts (please
refer to the AVR instruction set for more information about these instructions).
When programming in C the enabling/disabling is typically done using inline assembly
or compiler specific intrinsic functions. Refer to your compiler reference guide to find
information about this.

2.5 Interrupt Vectors
Interrupt vectors are locations (addresses) in the program memory that are executed
when an interrupt is triggered. The memory location will typically hold a JMP (or
RJMP) instruction to the program memory address where the corresponding Interrupt
Service Routine (ISR) is located. The addresses of the individual interrupt vectors are
specified in the datasheet.
As a safety precaution it is recommended to not leave unused interrupt vectors
unprogrammed. Unprogrammed memory will contain illegal instruction opcode, and
the effect is undefined. "Filling" unused interrupt vectors with RETI instructions will
ensure that the consequence of executing an interrupt that has no ISR is less critical.
However, if employing this during development it may conceal the fact that an
undefined interrupt is executed. One should consider implementing a dummy ISR for
all unused interrupts during development and debugging, so that is possible to notice
this kind of bugs.
3
8043A-AVR-02/08

If you are using the boot section of the program memory to (re)program the
application section of the program memory while the interrupts should still operate, it
is necessary to move the interrupt vectors to the boot section. If the vectors are not
moved while the application section is being written an interrupt would cause the
execution of a program memory address that cannot be read (due to the write
process). Therefore, if interrupts are enabled while the application section of the
program memory is written to, one has to move the vectors to the boot section to
ensure that the interrupts executes correctly. The vectors are moved to the boot
section by setting the IVSEL bit in the PMIC CTRL register. More information about
bootloaders can be found in the application note AVR109 and AVR1316.

2.6 Interrupt Priority
The priority of interrupts is determined by their vector address (or vector number).
The vector address is fixed for a given device. The interrupt priority determines which
of two interrupts with same interrupt level that would be executed first if they occurring
at the same time.
The PMIC offers a Round-robin scheduling scheme for low-level interrupt, which is
enabled by setting the RREN bit in the PMIC CTRL register. When enabling the
Round-Robin priority scheme the CPU will update the INTPRI register automatically
so that it always holds the vector number of the interrupt that has been executed last.
The value in INTPRI defines which low-level interrupt has the lowest priority. In this
way the Round-Robin scheme ensures that no low-level interrupts are "starved", as
the priority changes continuously. In other words, the low-level interrupt last executed
will always get lowest priority to ensure that other low-level interrupts are also
serviced.
Note that the INTPRI register will not return to its default value (0x00), when disabling
the Round-robin scheme: it will contain the number of the last low-level interrupt
executed. If it is desired to return to the default priority order, one has to write 0x00 to
the INTPRI register after disabling the Round-Robin scheme. The value in the INTPRI
register will still affect the priority order of low-level interrupts even if the Round-Robin
scheme is not used.

2.7 Interrupt Flags
A number of status bits in the AVR modules are referred to as interrupt flags. These
interrupt flags provides information about a change of state in the module, e.g. that a
byte has been received on the SPI. Interrupt flags will be set even if the
corresponding interrupt is not enabled. This makes it possible to poll interrupt flags in
the firmware main loop. Polling can be preferred in some cases, but are often handled
by an ISR that are executed when the event occurs. One advantage of ISR handling
is that important modules can be given immediate attention by temporarily stopping
less important tasks. In the case where the interrupt controller has multiple interrupt
levels, "less important tasks" includes interrupt with lower level than the "important"
higher level interrupt. Another advantage is that the AVR can enter sleep mode, to
reduce power consumption, and wake up when interrupts occur. Please refer to the
datasheet to find out which interrupts that can wake the CPU from the different sleep
modes.
Interrupts can be cleared manually, typically by writing a logic one to the flag, or
automatically, when the interrupt vector is executed. Other interrupt flags are cleared
when certain registers are accessed, e.g. the USART data register. Another example

4

AVR1305
8043A-AVR-02/08

AVR1305
is the interrupt flag for EEPROM writing, which will generate interrupts continuously
while the EEPROM is not busy writing.
Further, some flags are not automatically cleared by execution the interrupt vector.
Please refer to the datasheet to for information about clearing the individual flags.

2.8 Interrupts versus Event System
Note that it is not always necessary to let the CPU handle interrupts. The XMEGA
Event System provides an alternate way to handle typical interrupt conditions in
hardware without CPU intervention. The Event System can e.g. start an ADC
conversion every time a timer overflow occurs. This offers unique timing
opportunities, which would not be possible to obtain if CPU intervention was required.
The Event System is described in application note AVR1303.

3 Driver Implementation
This application note includes a source code package with a basic driver
implemented in C. It is written for the IAR Embedded Workbench(R) compiler.
Note that this driver is written to be highly readable and as general example how to
use the peripheral module. If using the driver in an application it may be desirable to
copy relevant parts of the code to where it is needed, to reduce to number of function
calls. This will both speed up the code and reduce the code footprint.

3.1 Files
The source code package consists of three files:
o pmic_driver.c - driver source file
o pmic_driver.h - driver header file
o pmic_example.c - Example code using the driver
For a complete overview of the available driver interface functions and their use,
please refer to the source code documentation.

3.2 Doxygen documentation
All source code is prepared for automatic documentation generation using Doxygen.
Doxygen is a tool for generating documentation from source code by analyzing the
source code and using special keywords. For more details about Doxygen please visit
http://sourceforge.net/projects/doxygen. Precompiled Doxygen documentation is also
supplied with the source code accompanying this application note, available from the
index.html file in the source code folder.

5
8043A-AVR-02/08

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8043A-AVR-02/08


xMega_official_drivers_and_examples.rar > XMEGA Clock System.pdf

AVR1003: Using the XMEGA(TM) Clock System
Features
o
o
o
o
o
o
o
o

8-bit
Microcontrollers

Internal 32 kHz, 2 MHz, and 32 MHz oscillators
External crystal oscillator or clock input
Internal PLL with multiplication factor 1x to 31x
Safe clock source switching
External oscillator failure detection
1x to 2048x system clock prescaler option
Automatic runtime calibration of internal oscillators
Driver source code included

Application Note

1 Introduction
The XMEGA Clock System is a set of highly flexible modules that provides a large
portfolio of internal and external clock sources. An internal high-frequency PLL and
a flexible prescaler block provide a vast amount of possible clock source
configurations, both for the CPU and peripherals. An external oscillator failure
detector and optional automatic runtime calibration of internal oscillators reduce
external component count and help designing for accuracy and safety.
This application describes the XMEGA Clock System with detailed configuration
procedures and a ready-to-use software driver.
Figure 1-1. XMEGA Clock System Overview

Automatic
Calibration
reference

Internal
Clock
Sources
Prescaler
Block

External
Clock
Sources

CPU
Peripherals
...

Highfrequency
PLL

Rev. 8072E-AVR-11/09

2 Clock System Overview
The XMEGA Clock System provides a large portfolio of clock sources, both internal
and external. In addition, an internal PLL can be used to multiply selected clock
sources with a factor ranging from 1x to 31x.
In order to ease implementations, the default clock setting for the XMEGA is to start
up running from an internal 2 MHz factory-calibrated source. In this way, if the default
settings are sufficient, no external components or software configuration is required to
start executing code.
The following sections describe the various clock sources and the available
configuration options for using one of them as a main system clock.

2.1 Internal Clock Sources
There are five internal clock sources (including the internal PLL), ranging from an
ultra low-power 32 kHz RC oscillator to a 32 MHz factory-calibrated ring oscillator with
auto-calibration features. All but one can be used for the main system clock.
Any number of the internal sources can be enabled at any given time, even if none
are used for the main system clock. Also, some clock sources might even be used for
multiple purposes, such as the 32 kHz RC oscillator that can be used as a main
system clock and as a clock source for the Real-time Counter module at the same
time.
Some of the internal clock source can be used as a reference to the internal PLL in
order to generate even higher frequencies. The PLL is covered in Section 2.3.
2.1.1 Ultra Low-power 32 kHz RC Oscillator
The Ultra Low-power 32 kHz internal RC oscillator (ULP32K) is mainly used for
system purposes, such as startup delays, the Watchdog Timer and various internal
timings. It can be used for the Real-time Clock module, but is not available as a
system clock source. With a frequency accuracy of 30%, it is not intended as such
either.
The ULP oscillator can be used as a source for the Real-time Counter module. Refer
to the application note "AVR1314: Using the XMEGA Real-time Counter" for more
details.
The ULP oscillator is automatically enabled by hardware when it is needed.
2.1.2 Calibrated 32 kHz RC Oscillator
The 32.768 kHz internal RC oscillator (RC32K) is factory-calibrated to 32 kHz with an
accuracy of 1% at 3V and 25°C. The calibration value is stored in the calibration row
and is automatically loaded into the oscillator's calibration register (RC32KCAL) on
reset. This value is read and write accessible for the user, but the oscillator should not
be tuned outside recommended limits. Please refer to the electrical characteristics in
the device datasheet for details.
The RC32K oscillator can be used as a system clock source directly and also as a
source for the Real-time Counter module (actually the RC32K divided down to
1.024 kHz). Refer to the application note "AVR1314: Using the XMEGA Real-time
Counter" for more details.
2

AVR1003
8072E-AVR-11/09

AVR1003
The RC32K oscillator cannot be used as a source for the internal PLL.
Apart from being a system clock source alternative, the RC32K can also be used as a
reference for the auto-calibration feature of the 2 MHz and 32 MHz internal
oscillators. The two oscillators and the auto-calibration feature are covered in later
sections.
The Internal 32kHz RC Oscillator Enable bit (RC32KEN) in the Oscillator Control
register (OSC.CTRL) controls this oscillator, while the Internal 32kHz RC Oscillator
Ready bit (RC32KRDY) in the Oscillator Status register (OSC.STATUS) can be polled
to check if it is stable and ready to be used as a system clock source.
2.1.3 Calibrated 2 MHz RC Oscillator
The 2 MHz internal RC oscillator (RC2M) is factory-calibrated to 2 MHz with an
accuracy of 1% at 3V and 25°C. The calibration value is stored in the calibration row
and is automatically loaded into the oscillator's internal calibration register on reset.
The oscillator can be further tuned and calibrated using the auto-calibration feature
covered in Section 2.8.
The RC2M oscillator can be used as a system clock source directly or through the
internal PLL to generate even higher system frequencies. Note that when using the
PLL, the user is responsible for not exceeding recommended frequency limits for the
CPU and peripherals.
The Internal 2MHz RC Oscillator Enable bit (RC2MEN) in the Oscillator Control register
(OSC.CTRL) controls this oscillator, while the Internal 2MHz RC Oscillator Ready bit
(RC2MRDY) in the Oscillator Status register (OSC.STATUS) can be polled to check if it
is stable and ready to be used as a system clock source.
2.1.4 Calibrated 32 MHz Ring Oscillator
The 32 MHz internal ring oscillator (R32M) is factory-calibrated to 32 MHz with an
accuracy of 1% at 3V and 25°C. The calibration value is stored in the calibration row
and is automatically loaded into the oscillator's internal calibration register on reset.
The oscillator can be further tuned and calibrated using the auto-calibration feature
covered in Section 2.8.
The R32M oscillator can be used as a system clock source directly or through the
internal PLL to generate even higher system frequencies. Note that when using the
PLL, the user is responsible for not exceeding recommended frequency limits for the
CPU and peripherals.
The Internal 32MHz Ring Oscillator Enable bit (R32MEN) in the Oscillator Control
register (OSC.CTRL) controls this oscillator, while the Internal 32MHz Ring Oscillator
Ready bit (R32MRDY) in the Oscillator Status register (OSC.STATUS) can be polled to
check if it is stable and ready to be used as a system clock source.

2.2 External Clock Sources
There are several possible external clock sources, all sharing the XTAL1 and XTAL2
pins. Of course, this means that only one source can be enabled at any given time.
Hardware makes sure that no two external sources are enabled simultaneously.
Attempts to do so will be disregarded by the hardware.
An exception from this is the Real-time Counter Oscillator using the TOSC1 and
TOSC2 pins with an external watch crystal as a source to the Real-time Clock
module. The Real-time Counter Oscillator can be used as a system clock source
3
8072E-AVR-11/09

directly, but not the 1 kHz prescaled signal as this only goes to the RTC. Refer to the
application note "AVR1314: Using the XMEGA Real-time Counter" for more details on
the RTC.
2.2.1 Crystals and Resonators
The XTAL1 and XTAL2 pins are input and output, respectively, of an inverting
amplifier that serves as an on-chip oscillator using external crystals or resonators
from 0.4 MHz to 16 MHz. This Crystal Oscillator (XOSC) can be configured for one
the following options:
o
o
o
o
o

32.768 kHz watch crystal oscillator with a low-power option
0.4 - 2 MHz low-swing crystal or resonator oscillator
2 - 9 MHz low-swing crystal or resonator oscillator
9 - 12 MHz low-swing crystal or resonator oscillator
12 - 16 MHz low-swing crystal or resonator oscillator

Actually, this is implemented as two crystal oscillators, one for 32.768 kHz crystals
and one for high-frequency crystals.
When using external 32 kHz watch crystals, the 32kHz Crystal Oscillator Low-power
Mode bit (X32KLPM) in the External Oscillator Control register (OSC.XOSCCTRL)
enables low-power mode. This only applies to 32 kHz watch crystals and should only
be used with high quality crystals.
The External Oscillator Selection bitfield (XOSCSEL) in the External Oscillator Control
register (OSC.XOSCCTRL) selects the external oscillator type and start-up time.
The External Oscillator Enable bit (XOSCEN) in the Oscillator Control register
(OSC.CTRL) controls this oscillator, while the External Oscillator Ready bit (XOSCRDY)
in the Oscillator Status register (OSC.STATUS) can be polled to check if it is stable
and ready to be used as a system clock source.
The oscillator must be configured before enabling it and the configuration cannot be
changed without disabling it first. Hardware will disregard any attempts to change
configuration while it is enabled.
How to connect external crystals and the recommended capacitor values are
shown in Figure 2-1 and
Table 2-1 below.
Figure 2-1. Crystal Oscillator Connection
C2
XTAL2
C1
XTAL1

GND

4

AVR1003
8072E-AVR-11/09

AVR1003
Table 2-1. Recommended Capacitor Values
Frequency Range

Capacitor Value (C1 and C2)

0.4 - 2 MHz

100 pF

2 - 9 MHz

15 pF

9 - 12 MHz

15 pF

12 - 16 MHz

10 pF

Note that the crystal oscillator is a low-swing type oscillator, which means that the
XTAL pins cannot be used to provide a clock signal to other devices. Instead, one of
the Timer/Counter modules could be used to generate a clock signal for external
devices. Refer to the application note "AVR1306: Using the XMEGA Timer/Counters".
2.2.2 External Clock
If the hardware design provides an external clock signal, this can be connected to the
XTAL1 pin and the on-chip crystal oscillator can be disabled. External clock is one of
the possible selections in the External Oscillator Selection bitfield (XOSCSEL) in the
External Oscillator Control register (OSC.XOSCCTRL) and always use a startup time
of six clock cycles before being reported to be stable with the External Oscillator
Ready bit (XOSCRDY) in the Oscillator Status register (OSC.STATUS).
Figure 2-2 below shows how to connect an external clock signal. To ensure correct
operation, the clock frequency should not change more than 2% from one cycle to
another. If the clock frequency needs to change more rapidly, the XMEGA should be
kept in a reset state during the change.
Figure 2-2. External Clock Connection
NC

XTAL2

External
Clock
Signal

XTAL1

GND

2.3 High-frequency PLL Option
If higher frequencies are required, a built-in PLL can be used to multiply a clock
source by a factor from 1 to 31. The following clock sources can be used as input to
the PLL:
o Internal 2 MHz RC oscillator
o Internal 32 MHz ring oscillator divided internally by four
o External 0.4 - 16 MHz crystal oscillator
o External clock
The hardware will not allow using the external oscillator as a PLL source if it is
configured for 32 kHz operation. If the external clock is used as input, it must be
5
8072E-AVR-11/09

above 0.4 MHz. Please refer to the electrical characteristics for accurate minimum
values.
The correct procedure for enabling the PLL is as follows:
1. Select multiplication factor using the Multiplication Factor bitfield (PLLFAC) and
input clock source using the Clock Source bitfield (PLLSRC) in the PLL Control
Register (OSC.PLLCTRL).
2. Enable the PLL using the PLL Enable bit (PLLEN) in the Oscillator Control register
(OSC.CTRL).
3. Wait for the PLL to stabilize by checking the PLL Ready bit (PLLRDY) in the
Oscillator Status register (OSC.STATUS).
The user should make sure that the input clock source is stable before trying to
enable the PLL. When enabled, the PLL typically needs 64 reference cycles to
stabilize.
The PLL configuration cannot be changed without disabling it first. Hardware will
disregard any attempts to change the configuration while it is enabled.
The user is responsible for providing a minimum input clock frequency of 0.44 MHz to
the PLL and make sure that the output never exceeds 200 MHz. The minimum input
frequency requirement applies when using an external clock signal as input to the
PLL.

2.4 System Clock Selection and Prescalers
To provide flexible options for the main system clock, the XMEGA Clock System
contains a MUX that selects one of the clock sources or the PLL. It feeds the selected
clock through a highly configurable prescaler block that can divide the clock signal by
a factor from 1 to 2048 before it is routed to the CPU and peripherals. It can also
provide clock signals two and four times the CPU clock frequency for peripherals than
operate at a higher frequency than the CPU, for instance the EBI module that can
operate at twice the CPU frequency.
Figure 2-3 below illustrates the MUX and prescalers. The output from the MUX goes
through three prescaler stages. The first stage, prescaler A, can divide by a factor of
1 to 512. Then prescalers B and C can be configured to either pass the signal through
or divide by up to four combined. See datasheet for details on this restriction.
Prescaler C output is routed to the CPU and peripherals.
Figure 2-3. System Clock Selection and Prescalers
Clock Control Register

Clock Prescaler Control Register

Internal 32 kHz RC Osc.
Internal 2 MHz RC Osc.
Internal 32 MHz Ring Osc.

P rescaler A
1, 2, 4, ... , 512

Prescaler B
1, 2, 4

Prescaler C
1, 2

CPU and peripherals

External Clock or Crystal Osc.
Internal PLL

2x speed tolerant peripherals

4x speed tolerant peripherals

The default setup after a reset is to select the internal 2 MHz RC oscillator and pass
the clock signal undivided through all three prescalers. Prescaler A can be used to
6

AVR1003
8072E-AVR-11/09

AVR1003
lower the system frequency by a large factor in order to reduce power consumption,
while prescaler B and C is primarily intended to provide clock signals one, two, or four
times the CPU frequency to selected peripherals.
The prescaler settings can be changed safely at any time. The hardware will ensure a
glitch-free transition between frequencies. When changing clock sources, hardware
will prevent any attempts to change to an unstable clock source.
The procedure for changing system clock and prescalers is as follows:
1. Load the Protect IO Register signature (byte value 0xD8) into the Configuration
Change Protection register (CCP). This will automatically disable all interrupts for
the next four CPU instruction cycles.
2. Set the desired configuration for the prescaler or the system clock.
Note that writing the signature to the CCP register only leaves time for reconfiguring
either the prescaler or the system clock. Repeat the CCP write if both needs
reconfiguration. Study the example software for details.

2.5 Clock Configuration Locking
As a safety precaution, it is possible to lock the current Clock System configuration
until the next reset. If your application is going to run from one clock configuration, it
could be wise to protect that configuration from accidental changes.
The procedure for locking the configuration is as follows:
1. Set up the XMEGA Clock System to desired configuration
2. Load the Protect IO Register signature (byte value 0xD8) into the Configuration
Change Protection register (CCP). This will automatically disable all interrupts for
the next four CPU instruction cycles.
3. Set the Clock System Lock bit (LOCK) in the Clock System Lock register
(CLK.LOCK) to logic one.
4. The clock configuration is now locked until the next system reset.
If the External Oscillator Failure Detector is enabled, a failure will unlock the Clock
System configuration. See Section 2.7 below for details.

2.6 Sleep Modes and Clock Sources
All oscillators and clock generation will be disabled in Power-down and Power-save
sleep modes. The exception is if the Real-time Counter is enabled in Power-save
mode, which leaves the RTC clock source running. If the RTC is not used, Powerdown mode is recommended instead of Power-save mode. With these two sleep
modes, start-up delays behave as if the oscillators were disabled.
In Standby and Extended Standby sleep modes, the oscillators are kept running,
enabling the CPU to wake up without extensive delays.
In Idle mode, the oscillators are kept running and the CPU will wake up from sleep
without any delay.
Please refer to the device datasheet for details on sleep modes and wakeup
conditions.

7
8072E-AVR-11/09

2.7 External Oscillator Failure Detector
When using external crystals or external clock sources, there is always a slight
probability of the source failing. As a safety precaution, the XMEGA Clock System
has an External Oscillator Failure Detector that monitors the external clock source
and reacts if it stops.
If the external source is selected as the main system clock source and it fails, the
failure detector switches to the internal 2 MHz RC oscillator and issues a Nonmaskable Interrupt (NMI). Please refer to the application note "AVR1305: XMEGA
Interrupts and the Programmable Multilevel Interrupt Controller" for more details on
NMIs.
If the external source is enabled, but is not selected as the main system clock source,
the external source will only be disabled, but the NMI will still be issued.
The failure detector uses the ULP oscillator to monitor the external source, and reacts
if the frequency falls below 32 kHz. Note that the ULP accuracy is 30%, so it could be
possible to run below 32 kHz, but it is not recommended. 32 kHz operation is
guaranteed not to cause a failure detection.
The failure detector is not enabled by default. To avoid accidental enabling, a special
sequence is required to enable it. The procedure is as follows:
1. Load the Protect IO Register signature (byte value 0xD8) into the Configuration
Change Protection register (CCP). This will automatically disable all interrupts for
the next four CPU instruction cycles.
2. Set the Failure Detection Enable bit (XOSCFDEN) in the External Oscillator Failure
Detection register (OSC.XOSCFAIL) to logic one.
3. The failure detector is now enabled until the next system reset.
Since the failure detector issues a Non-maskable Interrupt if the external source fails
when used as the main system clock source, it is important to implement an interrupt
handler for this interrupt. Non-maskable interrupts cannot be disabled in any way,
hence the name "Non-maskable". Please study the example software for details.

2.8 Automatic Runtime Calibration of Internal Oscillators
The XMEGA Clock System provides two Digital Frequency-locked Loops (DFLLs),
one for the 2 MHz RC oscillator and one for the 32 MHz ring oscillator. The DFLLs
can be configured individually to use either the internal 32 kHz RC oscillator or an
external 32 kHz watch crystal as a reference for the calibration process.
Once enabled, a DFLL provides continuous calibration of its oscillator based on the
clock reference. When entering sleep mode, the current state is frozen and the
calibration loop continues from where it stopped when exiting from sleep mode again.
If a DFLL is disabled, the current calibration value for the oscillator will remain in
effect until the DFLL is enabled again and the calibration process continues.
The DFLL Control register (OSC.DFLLCTRL) contains two control bits, DFLL 32MHz
Calibration Reference Selection (R32MCREF) and DFLL 2MHz Calibration Reference
Selection (RC2MCREF), which select the clock reference for the DFLLs. A logic zero
selects the internal 32 kHz RC oscillator, while a logic one selects the external watch
crystal oscillator. Hardware will disregard any attempts to use an unstable clock
source.

8

AVR1003
8072E-AVR-11/09

AVR1003
The DFLLs themselves require a three-byte counter reference value in the
corresponding DFLL Counter registers (OSC.DFLLx.OSCCNTn). Correct counter
reference values are loaded automatically on reset and should not be changed by the
user.
The DFLLs also have a two-byte calibration register each (OSC.DFLLx.CALn), which
contains an enable bit and a calibration value, which is loaded automatically by
hardware on reset. The calibration value serves as a starting point for the calibration
loop and should not be changed by the user.
The correct procedure for enabling a DFLL is as follows:
1. Select internal or external clock reference with the DFLL's control bit in the DFLL
Control register (OSC.DFLLCTRL).
2. Set the DFLL Enable bit (ENABLE) in the DFLL's Control Register (DFLLx.CTRL)
to logic one to enable the DFLL.
3. The calibration process starts immediately.
There are no runtime calibration options for the internal 32 kHz RC oscillator, but if
required, it can be fine-tuned by changing its calibration register (RC32KCAL).
However, great care should be taken not to tune any oscillator outside recommended
operating limits.

3 Examples
This application note includes a source code package with a basic Clock System
driver implemented in C. It is written for the IAR Embedded Workbench(R) compiler.
Note that this Clock System driver is not intended for use with high-performance
code. It is designed as a library to get started with the XMEGA Clock System. For
timing and code space critical application development, you should access the Clock
System registers directly. Please refer to the driver source code and device datasheet
for more details.

3.1 Files
The source code package consists of three files:
o clksys_driver.c - Clock System driver source file
o clksys_driver.h - Clock System driver header file
o main.c - Example code using the driver
For a complete overview of the available driver interface functions and their use,
please refer to the source code documentation.

3.2 Doxygen Documentation
All source code is prepared for automatic documentation generation using Doxygen.
Doxygen is a tool for generating documentation from source code by analyzing the
source code and using special keywords. For more details about Doxygen please visit
http://www.doxygen.org. Precompiled Doxygen documentation is also supplied with
the source code accompanying this application note, available from the readme.html
file in the source code folder.

9
8072E-AVR-11/09

Disclaimer

Headquarters

International

Atmel Corporation
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San Jose, CA 95131
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Tel: 1(408) 441-0311
Fax: 1(408) 487-2600

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Fax: (81) 3-3523-7581

Technical Support
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Sales Contact
www.atmel.com/contacts

Product Contact
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Literature Request
www.atmel.com/literature

Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any
intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL'S TERMS AND
CONDITIONS OF SALE LOCATED ON ATMEL'S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED
OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY,
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(R)

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(C) 2009 Atmel Corporation. All rights reserved. Atmel , Atmel logo and combinations thereof, AVR , AVR logo and others, are the
registered trademarks, XMEGA(TM) and others are trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be
trademarks of others.

8072E-AVR-11/09


xMega_official_drivers_and_examples.rar > documentation.h

/* Doxygen documentation mainpage ********************************************/
/*! \mainpage
* \section intro Introduction
* This documents the firmware for the application note. \n
*
* \section compinfo Compilation Info
* This firmware was compiled with IAR Embedded Workbench 5.20.1 and WinAVR 20080411.\n
*
* To make the project in IAR EWAVR:\n
* Add the .c files (and .S90 files where applicable) for the given example to your
* project. Use device ATxmega128A1 and enable bit definitions in I/O include files,
* optimization low for debug target and high for release, output format: ubrof8 for
* Debug and intel_extended for Release, select Normal DLIB as library. \n
*
* To make the project in WinAVR:\n
* Add the .c files (and .S files where applicable) for the given example to your project.
* Use device ATxmega128A1, optimization low for debug target and high for release. \n
*
* \section deviceinfo Device Info
* All XMEGA devices with the targeted module can be used. The example is
* written for ATxmega128A1.
*
* \section contactinfo Contact Info
* For more info about Atmel AVR visit http://www.atmel.com/products/AVR/ \n
* For application notes visit
* http://www.atmel.com/dyn/products/app_notes.asp?family_id=607 \n
* Support mail: avr@atmel.com \n
*
* $Revision: 2773 $
* $Date: 2009-09-14 09:47:33 +0200 (ma, 14 sep 2009) $
*
* Copyright (c) 2008, Atmel Corporation All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of ATMEL may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL " AS IS " AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
* SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*****************************************************************************/


xMega_official_drivers_and_examples.rar > clksys_example.c

/* This file has been prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief XMEGA Clock System driver example source.
*
* This file contains an example application that demonstrates the Clock
* System driver. The recommended setup for this demonstration is to connect
* an external 2-9MHz crystal to the XTAL1/XTAL2 pins with proper decoupling.
*
*
* \par Application note:
* AVR1003: Using the XMEGA Clock System
*
* \par Documentation
* For comprehensive code documentation, supported compilers, compiler
* settings and supported devices see readme.html
*
* \author
* Atmel Corporation: http://www.atmel.com \n
* Support email: avr@atmel.com
*
* $Revision: 1569 $
* $Date: 2008-04-22 13:03:43 +0200 (ti, 22 apr 2008) $ \n
*
* Copyright (c) 2008, Atmel Corporation All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of ATMEL may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL " AS IS " AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
* SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*****************************************************************************/

#include " avr_compiler.h "
#include " clksys_driver.h "

/* The LED to use for visual feedback. */
#define LEDPORT PORTD
#define LEDMASK 0xFF

/* Which switches to listen to */
#define SWITCHPORT PORTC
#define SWITCHMASK 0xFF


/* Prototype function. */
void WaitForSwitches( void );


/*! \brief Example code that switch between different clocks
*
* This example code shows how to change between 5 different system clocks
* and how to prescale and divide the clocks to make use of dynamic
* clocking for the different parts on the device. When changes are
* made to the clocks, blocking functions are used to make sure the
* clocks are stable before they can be used.
*/
int main( void )
{
/* Set up user interface. */
LEDPORT.DIRSET = LEDMASK;
LEDPORT.OUTSET = LEDMASK;
SWITCHPORT.DIRCLR = SWITCHMASK;

/* Set up Timer/Counter 0 to work from CPUCLK/64, with period 10000 and
* enable overflow interrupt.
*/
TCC0.PER = 10000;
TCC0.CTRLA = ( TCC0.CTRLA & ~TC0_CLKSEL_gm ) | TC_CLKSEL_DIV64_gc;
TCC0.INTCTRLA = ( TCC0.INTCTRLA & ~TC0_OVFINTLVL_gm ) |
TC_OVFINTLVL_MED_gc;

/* Enable low interrupt level in PMIC and enable global interrupts. */
PMIC.CTRL |= PMIC_MEDLVLEN_bm;
sei();


/* This while loop run through and switch between the different
* system clock sources available.
*/
while(1) {

/* Wait for user input while the LEDs toggle. */
WaitForSwitches();


/* Enable internal 32 MHz ring oscillator and wait until it's
* stable. Divide clock by two with the prescaler C and set the
* 32 MHz ring oscillator as the main clock source. Wait for
* user input while the LEDs toggle.
*/
CLKSYS_Enable( OSC_RC32MEN_bm );
CLKSYS_Prescalers_Config( CLK_PSADIV_1_gc, CLK_PSBCDIV_1_2_gc );
do {} while ( CLKSYS_IsReady( OSC_RC32MRDY_bm ) == 0 );
CLKSYS_Main_ClockSource_Select( CLK_SCLKSEL_RC32M_gc );
WaitForSwitches( );


/* Enable for external 2-9 MHz crystal with quick startup time
* (256CLK). Check if it's stable and set the external
* oscillator as the main clock source. Wait for user input
* while the LEDs toggle.
*/
CLKSYS_XOSC_Config( OSC_FRQRANGE_2TO9_gc,
false,
OSC_XOSCSEL_EXTCLK_gc );
CLKSYS_Enable( OSC_XOSCEN_bm );
do {} while ( CLKSYS_IsReady( OSC_XOSCRDY_bm ) == 0 );
CLKSYS_Main_ClockSource_Select( CLK_SCLKSEL_XOSC_gc );
CLKSYS_Disable( OSC_RC32MEN_bm );
WaitForSwitches();


/* Divide Prescaler C by two and Prescaler C by two, and wait
* for user input.
*/
CLKSYS_Prescalers_Config( CLK_PSADIV_1_gc, CLK_PSBCDIV_2_2_gc );
WaitForSwitches();


/* Enable internal 32 kHz calibrated oscillator and check for
* it to be stable and set prescaler A, B and C to none. Set
* the 32 kHz oscillator as the main clock source. Wait for
* user input while the LEDs toggle.
*/
CLKSYS_Enable( OSC_RC32KEN_bm );
CLKSYS_Prescalers_Config( CLK_PSADIV_1_gc, CLK_PSBCDIV_1_1_gc );
do {} while ( CLKSYS_IsReady( OSC_RC32KRDY_bm ) == 0 );
CLKSYS_Main_ClockSource_Select( CLK_SCLKSEL_RC32K_gc );
CLKSYS_Disable( OSC_XOSCEN_bm );
WaitForSwitches();


/* Configure PLL with the 2 MHz RC oscillator as source and
* multiply by 30 to get 60 MHz PLL clock and enable it. Wait
* for it to be stable and set prescaler C to divide by two
* to set the CPU clock to 30 MHz. Disable unused clock and
* wait for user input.
*/
CLKSYS_PLL_Config( OSC_PLLSRC_RC2M_gc, 30 );
CLKSYS_Enable( OSC_PLLEN_bm );
CLKSYS_Prescalers_Config( CLK_PSADIV_1_gc, CLK_PSBCDIV_1_2_gc );
do {} while ( CLKSYS_IsReady( OSC_PLLRDY_bm ) == 0 );
CLKSYS_Main_ClockSource_Select( CLK_SCLKSEL_PLL_gc );
CLKSYS_Disable( OSC_XOSCEN_bm );
WaitForSwitches( );


/* Select 2 MHz RC oscillator as main clock source and diable
* unused clock.
*/
do {} while ( CLKSYS_IsReady( OSC_RC2MRDY_bm ) == 0 );
CLKSYS_Main_ClockSource_Select( CLK_SCLKSEL_RC2M_gc );
CLKSYS_Disable( OSC_PLLEN_bm );

}
}

/*! \brief This function waits for a button push and release before proceeding.
*/
void WaitForSwitches( void )
{
do {} while ( ( SWITCHPORT.IN & SWITCHMASK ) == SWITCHMASK );
delay_us( 1000 );
do {} while ( ( SWITCHPORT.IN & SWITCHMASK ) != SWITCHMASK );
delay_us( 1000 );
}


/*! Just toggle LED(s) when interrupt occurs. */
ISR(TCC0_OVF_vect)
{
LEDPORT.OUTTGL = LEDMASK;
}


xMega_official_drivers_and_examples.rar > avr_compiler.h

/* This file has been prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief This file implements some macros that makes the IAR C-compiler and
* avr-gcc work with the same code base for the AVR architecture.
*
* \par Documentation
* For comprehensive code documentation, supported compilers, compiler
* settings and supported devices see readme.html
*
* \author
* Atmel Corporation: http://www.atmel.com \n
* Support email: avr@atmel.com
*
* $Revision: 2772 $
* $Date: 2009-09-11 12:40:26 +0200 (fr, 11 sep 2009) $ \n
*
* Copyright (c) 2008, Atmel Corporation All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of ATMEL may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL " AS IS " AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
* SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/

#ifndef COMPILER_AVR_H
#define COMPILER_AVR_H

#ifndef F_CPU
/*! \brief Define default CPU frequency, if this is not already defined. */
#define F_CPU 2000000UL
#endif

#include & lt; stdint.h & gt;
#include & lt; stdbool.h & gt;
#include & lt; stdlib.h & gt;

/*! \brief This macro will protect the following code from interrupts. */
#define AVR_ENTER_CRITICAL_REGION( ) uint8_t volatile saved_sreg = SREG; \
cli();

/*! \brief This macro must always be used in conjunction with AVR_ENTER_CRITICAL_REGION
* so the interrupts are enabled again.
*/
#define AVR_LEAVE_CRITICAL_REGION( ) SREG = saved_sreg;

#if defined( __ICCAVR__ )

#include & lt; inavr.h & gt;
#include & lt; ioavr.h & gt;
#include & lt; intrinsics.h & gt;
#include & lt; pgmspace.h & gt;

#ifndef __HAS_ELPM__
#define _MEMATTR __flash
#else /* __HAS_ELPM__ */
#define _MEMATTR __farflash
#endif /* __HAS_ELPM__ */

/*! \brief Perform a delay of \c us microseconds.
*
* The macro F_CPU is supposed to be defined to a constant defining the CPU
* clock frequency (in Hertz).
*
* The maximal possible delay is 262.14 ms / F_CPU in MHz.
*
* \note For the IAR compiler, currently F_CPU must be a
* multiple of 1000000UL (1 MHz).
*/
#define delay_us( us ) ( __delay_cycles( ( F_CPU / 1000000UL ) * ( us ) ) )

/*! \brief Preprocessor magic.
*
* Some preprocessor magic to allow for a header file abstraction of
* interrupt service routine declarations for the IAR compiler. This
* requires the use of the C99 _Pragma() directive (rather than the
* old #pragma one that could not be used as a macro replacement), as
* well as two different levels of preprocessor concetanations in
* order to do both, assign the correct interrupt vector name, as well
* as construct a unique function name for the ISR.
*
* \note Do *NOT* try to reorder the macros below, as this will only
* work in the given order.
*/
#define PRAGMA(x) _Pragma( #x )
#define ISR(vec) PRAGMA( vector=vec ) __interrupt void handler_##vec(void)
#define sei( ) (__enable_interrupt( ))
#define cli( ) (__disable_interrupt( ))

/*! \brief Define the no operation macro. */
#define nop( ) (__no_operation())

/*! \brief Define the watchdog reset macro. */
#define watchdog_reset( ) (__watchdog_reset( ))


#define INLINE PRAGMA( inline=forced ) static

#define FLASH_DECLARE(x) _MEMATTR x
#define FLASH_STRING(x) ((_MEMATTR const char *)(x))
#define FLASH_STRING_T char const _MEMATTR *
#define FLASH_BYTE_ARRAY_T uint8_t const _MEMATTR *
#define PGM_READ_BYTE(x) *(x)
#define PGM_READ_WORD(x) *(x)

#define SHORTENUM /**/

#elif defined( __GNUC__ )

#include & lt; avr/io.h & gt;
#include & lt; avr/interrupt.h & gt;
#include & lt; avr/pgmspace.h & gt;
#include & lt; util/delay.h & gt;

/*! \brief Define the delay_us macro for GCC. */
#define delay_us( us ) (_delay_us( us ))

#define INLINE static inline

/*! \brief Define the no operation macro. */
#define nop() do { __asm__ __volatile__ ( " nop " ); } while (0)

#define MAIN_TASK_PROLOGUE int


#define MAIN_TASK_EPILOGUE() return -1;

#define SHORTENUM __attribute__ ((packed))

#else
#error Compiler not supported.
#endif

#endif


xMega_official_drivers_and_examples.rar > clksys_driver.h

/* This file has been prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief XMEGA Clock System driver header file.
*
* This file contains the function prototypes and enumerator definitions
* for various configuration parameters for the XMEGA Clock System driver.
*
* The driver is not intended for size and/or speed critical code, since
* most functions are just a few lines of code, and the function call
* overhead would decrease code performance. The driver is intended for
* rapid prototyping and documentation purposes for getting started with
* the XMEGA Clock System.
*
* For size and/or speed critical code, it is recommended to copy the
* function contents directly into your application instead of making
* a function call.
*
* \par Application note:
* AVR1003: Using the XMEGA Clock System
*
* \par Documentation
* For comprehensive code documentation, supported compilers, compiler
* settings and supported devices see readme.html
*
* \author
* Atmel Corporation: http://www.atmel.com \n
* Support email: avr@atmel.com
*
* $Revision: 1665 $
* $Date: 2008-06-05 09:21:50 +0200 (to, 05 jun 2008) $ \n
*
* Copyright (c) 2008, Atmel Corporation All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of ATMEL may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL " AS IS " AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
* SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*****************************************************************************/
#ifndef CLKSYS_DRIVER_H
#define CLKSYS_DRIVER_H

#include " avr_compiler.h "


/* Definitions of macros. */

/*! \brief This macro enables the selected oscillator.
*
* \note Note that the oscillator cannot be used as a main system clock
* source without being enabled and stable first. Check the ready flag
* before using the clock. The function CLKSYS_IsReady( _oscSel )
* can be used to check this.
*
* \param _oscSel Bitmask of selected clock. Can be one of the following
* OSC_RC2MEN_bm, OSC_RC32MEN_bm, OSC_RC32KEN_bm, OSC_XOSCEN_bm,
* OSC_PLLEN_bm.
*/
#define CLKSYS_Enable( _oscSel ) ( OSC.CTRL |= (_oscSel) )

/*! \brief This macro check if selected oscillator is ready.
*
* This macro will return non-zero if is is running, regardless if it is
* used as a main clock source or not.
*
* \param _oscSel Bitmask of selected clock. Can be one of the following
* OSC_RC2MEN_bm, OSC_RC32MEN_bm, OSC_RC32KEN_bm, OSC_XOSCEN_bm,
* OSC_PLLEN_bm.
*
* \return Non-zero if oscillator is ready and running.
*/
#define CLKSYS_IsReady( _oscSel ) ( OSC.STATUS & (_oscSel) )

/*! \brief This macro disables routing of clock signals to the Real-Time
* Counter (RTC).
*
* Disabling the RTC saves power if the RTC is not in use.
*/
#define CLKSYS_RTC_ClockSource_Disable() ( CLK.RTCCTRL & = ~CLK_RTCEN_bm )

/*! \brief This macro disables the automatic calibration of the selected
* internal oscillator.
*
* \param _clk Clock source calibration to disable, either DFLLRC2M or DFLLRC32M.
*/
#define CLKSYS_AutoCalibration_Disable( _clk ) ( (_clk).CTRL & = ~DFLL_ENABLE_bm )


/* Prototyping of function. Detailed information is found in source file. */
void CCPWrite( volatile uint8_t * address, uint8_t value );
void CLKSYS_XOSC_Config( OSC_FRQRANGE_t freqRange,
bool lowPower32kHz,
OSC_XOSCSEL_t xoscModeSelection );
void CLKSYS_PLL_Config( OSC_PLLSRC_t clockSource, uint8_t factor );
uint8_t CLKSYS_Disable( uint8_t oscSel );
void CLKSYS_Prescalers_Config( CLK_PSADIV_t PSAfactor,
CLK_PSBCDIV_t PSBCfactor );
uint8_t CLKSYS_Main_ClockSource_Select( CLK_SCLKSEL_t clockSource );
void CLKSYS_RTC_ClockSource_Enable( CLK_RTCSRC_t clockSource );
void CLKSYS_AutoCalibration_Enable( uint8_t clkSource, bool extReference );
void CLKSYS_XOSC_FailureDetection_Enable( void );
void CLKSYS_Configuration_Lock( void );


#endif


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documentation.h File Reference

Go to the source code of this file.






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clksys_example.c File Reference XMEGA Clock System driver example source.
More...

#include & quot; avr_compiler.h & quot;
#include & quot; clksys_driver.h & quot;



Include dependency graph for clksys_example.c:







Go to the source code of this file.

Defines
#define & nbsp; LEDMASK & nbsp; & nbsp; & nbsp;0xFF

#define & nbsp; LEDPORT & nbsp; & nbsp; & nbsp;PORTD

#define & nbsp; SWITCHMASK & nbsp; & nbsp; & nbsp;0xFF

#define & nbsp; SWITCHPORT & nbsp; & nbsp; & nbsp;PORTC

Functions
& nbsp; ISR (TCC0_OVF_vect)

int & nbsp; main (void)

& nbsp; Example code that switch between different clocks.
void & nbsp; WaitForSwitches (void)

& nbsp; This function waits for a button push and release before proceeding.

Detailed Description
XMEGA Clock System driver example source.

This file contains an example application that demonstrates the Clock System driver. The recommended setup for this demonstration is to connect an external 2-9MHz crystal to the XTAL1/XTAL2 pins with proper decoupling.
Application note: AVR1003: Using the XMEGA Clock System
Documentation For comprehensive code documentation, supported compilers, compiler settings and supported devices see readme.html
Author: Atmel Corporation: http://www.atmel.com
Support email: avr@atmel.com
Revision 1569
Date 2008-04-22 13:03:43 +0200 (ti, 22 apr 2008)


Copyright (c) 2008, Atmel Corporation All rights reserved.
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
3. The name of ATMEL may not be used to endorse or promote products derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY ATMEL " AS IS " AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Definition in file clksys_example.c .
Define Documentation





#define LEDMASK & nbsp; & nbsp; & nbsp;0xFF







Definition at line 57 of file clksys_example.c .

Referenced by ISR() , and main() .








#define LEDPORT & nbsp; & nbsp; & nbsp;PORTD







Definition at line 56 of file clksys_example.c .

Referenced by ISR() , and main() .








#define SWITCHMASK & nbsp; & nbsp; & nbsp;0xFF







Definition at line 61 of file clksys_example.c .

Referenced by main() , and WaitForSwitches() .








#define SWITCHPORT & nbsp; & nbsp; & nbsp;PORTC







Definition at line 60 of file clksys_example.c .

Referenced by main() , and WaitForSwitches() .



Function Documentation





ISR
(
TCC0_OVF_vect & nbsp;

& nbsp;) & nbsp;







Just toggle LED(s) when interrupt occurs.
Definition at line 189 of file clksys_example.c .

References LEDMASK , and LEDPORT .
00190 {
00191 LEDPORT .OUTTGL = LEDMASK ;
00192 }










int main
(
void & nbsp;

& nbsp;) & nbsp;







Example code that switch between different clocks.

This example code shows how to change between 5 different system clocks and how to prescale and divide the clocks to make use of dynamic clocking for the different parts on the device. When changes are made to the clocks, blocking functions are used to make sure the clocks are stable before they can be used.
Definition at line 76 of file clksys_example.c .

References CLKSYS_Disable() , CLKSYS_Enable , CLKSYS_IsReady , CLKSYS_Main_ClockSource_Select() , CLKSYS_PLL_Config() , CLKSYS_Prescalers_Config() , CLKSYS_XOSC_Config() , LEDMASK , LEDPORT , SWITCHMASK , SWITCHPORT , and WaitForSwitches() .
00077 {
00078 /* Set up user interface. */
00079 LEDPORT .DIRSET = LEDMASK ;
00080 LEDPORT .OUTSET = LEDMASK ;
00081 SWITCHPORT .DIRCLR = SWITCHMASK ;
00082
00083 /* Set up Timer/Counter 0 to work from CPUCLK/64, with period 10000 and
00084 * enable overflow interrupt.
00085 */
00086 TCC0.PER = 10000;
00087 TCC0.CTRLA = ( TCC0.CTRLA & amp; ~TC0_CLKSEL_gm ) | TC_CLKSEL_DIV64_gc;
00088 TCC0.INTCTRLA = ( TCC0.INTCTRLA & amp; ~TC0_OVFINTLVL_gm ) |
00089 TC_OVFINTLVL_MED_gc;
00090
00091 /* Enable low interrupt level in PMIC and enable global interrupts. */
00092 PMIC.CTRL |= PMIC_MEDLVLEN_bm;
00093 sei();
00094
00095
00096 /* This while loop run through and switch between the different
00097 * system clock sources available.
00098 */
00099 while (1) {
00100
00101 /* Wait for user input while the LEDs toggle. */
00102 WaitForSwitches ();
00103
00104
00105 /* Enable internal 32 MHz ring oscillator and wait until it's
00106 * stable. Divide clock by two with the prescaler C and set the
00107 * 32 MHz ring oscillator as the main clock source. Wait for
00108 * user input while the LEDs toggle.
00109 */
00110 CLKSYS_Enable ( OSC_RC32MEN_bm );
00111 CLKSYS_Prescalers_Config ( CLK_PSADIV_1_gc, CLK_PSBCDIV_1_2_gc );
00112 do {} while ( CLKSYS_IsReady ( OSC_RC32MRDY_bm ) == 0 );
00113 CLKSYS_Main_ClockSource_Select ( CLK_SCLKSEL_RC32M_gc );
00114 WaitForSwitches ( );
00115
00116
00117 /* Enable for external 2-9 MHz crystal with quick startup time
00118 * (256CLK). Check if it's stable and set the external
00119 * oscillator as the main clock source. Wait for user input
00120 * while the LEDs toggle.
00121 */
00122 CLKSYS_XOSC_Config ( OSC_FRQRANGE_2TO9_gc,
00123 false ,
00124 OSC_XOSCSEL_EXTCLK_gc );
00125 CLKSYS_Enable ( OSC_XOSCEN_bm );
00126 do {} while ( CLKSYS_IsReady ( OSC_XOSCRDY_bm ) == 0 );
00127 CLKSYS_Main_ClockSource_Select ( CLK_SCLKSEL_XOSC_gc );
00128 CLKSYS_Disable ( OSC_RC32MEN_bm );
00129 WaitForSwitches ();
00130
00131
00132 /* Divide Prescaler C by two and Prescaler C by two, and wait
00133 * for user input.
00134 */
00135 CLKSYS_Prescalers_Config ( CLK_PSADIV_1_gc, CLK_PSBCDIV_2_2_gc );
00136 WaitForSwitches ();
00137
00138
00139 /* Enable internal 32 kHz calibrated oscillator and check for
00140 * it to be stable and set prescaler A, B and C to none. Set
00141 * the 32 kHz oscillator as the main clock source. Wait for
00142 * user input while the LEDs toggle.
00143 */
00144 CLKSYS_Enable ( OSC_RC32KEN_bm );
00145 CLKSYS_Prescalers_Config ( CLK_PSADIV_1_gc, CLK_PSBCDIV_1_1_gc );
00146 do {} while ( CLKSYS_IsReady ( OSC_RC32KRDY_bm ) == 0 );
00147 CLKSYS_Main_ClockSource_Select ( CLK_SCLKSEL_RC32K_gc );
00148 CLKSYS_Disable ( OSC_XOSCEN_bm );
00149 WaitForSwitches ();
00150
00151
00152 /* Configure PLL with the 2 MHz RC oscillator as source and
00153 * multiply by 30 to get 60 MHz PLL clock and enable it. Wait
00154 * for it to be stable and set prescaler C to divide by two
00155 * to set the CPU clock to 30 MHz. Disable unused clock and
00156 * wait for user input.
00157 */
00158 CLKSYS_PLL_Config ( OSC_PLLSRC_RC2M_gc, 30 );
00159 CLKSYS_Enable ( OSC_PLLEN_bm );
00160 CLKSYS_Prescalers_Config ( CLK_PSADIV_1_gc, CLK_PSBCDIV_1_2_gc );
00161 do {} while ( CLKSYS_IsReady ( OSC_PLLRDY_bm ) == 0 );
00162 CLKSYS_Main_ClockSource_Select ( CLK_SCLKSEL_PLL_gc );
00163 CLKSYS_Disable ( OSC_XOSCEN_bm );
00164 WaitForSwitches ( );
00165
00166
00167 /* Select 2 MHz RC oscillator as main clock source and diable
00168 * unused clock.
00169 */
00170 do {} while ( CLKSYS_IsReady ( OSC_RC2MRDY_bm ) == 0 );
00171 CLKSYS_Main_ClockSource_Select ( CLK_SCLKSEL_RC2M_gc );
00172 CLKSYS_Disable ( OSC_PLLEN_bm );
00173
00174 }
00175 }





Here is the call graph for this function:













void WaitForSwitches
(
void & nbsp;

& nbsp;) & nbsp;







This function waits for a button push and release before proceeding.


Definition at line 179 of file clksys_example.c .

References SWITCHMASK , and SWITCHPORT .

Referenced by main() .
00180 {
00181 do {} while ( ( SWITCHPORT .IN & amp; SWITCHMASK ) == SWITCHMASK );
00182 delay_us( 1000 );
00183 do {} while ( ( SWITCHPORT .IN & amp; SWITCHMASK ) != SWITCHMASK );
00184 delay_us( 1000 );
00185 }









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Xmega Application Note







clksys_example.c Go to the documentation of this file. 00001 /* This file has been prepared for Doxygen automatic documentation generation.*/
00052 #include " avr_compiler.h "
00053 #include " clksys_driver.h "
00054
00055 /* The LED to use for visual feedback. */
00056 #define LEDPORT PORTD
00057 #define LEDMASK 0xFF
00058
00059 /* Which switches to listen to */
00060 #define SWITCHPORT PORTC
00061 #define SWITCHMASK 0xFF
00062
00063
00064 /* Prototype function. */
00065 void WaitForSwitches ( void );
00066
00067
00076 int main ( void )
00077 {
00078 /* Set up user interface. */
00079 LEDPORT .DIRSET = LEDMASK ;
00080 LEDPORT .OUTSET = LEDMASK ;
00081 SWITCHPORT .DIRCLR = SWITCHMASK ;
00082
00083 /* Set up Timer/Counter 0 to work from CPUCLK/64, with period 10000 and
00084 * enable overflow interrupt.
00085 */
00086 TCC0.PER = 10000;
00087 TCC0.CTRLA = ( TCC0.CTRLA & amp; ~TC0_CLKSEL_gm ) | TC_CLKSEL_DIV64_gc;
00088 TCC0.INTCTRLA = ( TCC0.INTCTRLA & amp; ~TC0_OVFINTLVL_gm ) |
00089 TC_OVFINTLVL_MED_gc;
00090
00091 /* Enable low interrupt level in PMIC and enable global interrupts. */
00092 PMIC.CTRL |= PMIC_MEDLVLEN_bm;
00093 sei();
00094
00095
00096 /* This while loop run through and switch between the different
00097 * system clock sources available.
00098 */
00099 while (1) {
00100
00101 /* Wait for user input while the LEDs toggle. */
00102 WaitForSwitches ();
00103
00104
00105 /* Enable internal 32 MHz ring oscillator and wait until it's
00106 * stable. Divide clock by two with the prescaler C and set the
00107 * 32 MHz ring oscillator as the main clock source. Wait for
00108 * user input while the LEDs toggle.
00109 */
00110 CLKSYS_Enable ( OSC_RC32MEN_bm );
00111 CLKSYS_Prescalers_Config ( CLK_PSADIV_1_gc, CLK_PSBCDIV_1_2_gc );
00112 do {} while ( CLKSYS_IsReady ( OSC_RC32MRDY_bm ) == 0 );
00113 CLKSYS_Main_ClockSource_Select ( CLK_SCLKSEL_RC32M_gc );
00114 WaitForSwitches ( );
00115
00116
00117 /* Enable for external 2-9 MHz crystal with quick startup time
00118 * (256CLK). Check if it's stable and set the external
00119 * oscillator as the main clock source. Wait for user input
00120 * while the LEDs toggle.
00121 */
00122 CLKSYS_XOSC_Config ( OSC_FRQRANGE_2TO9_gc,
00123 false ,
00124 OSC_XOSCSEL_EXTCLK_gc );
00125 CLKSYS_Enable ( OSC_XOSCEN_bm );
00126 do {} while ( CLKSYS_IsReady ( OSC_XOSCRDY_bm ) == 0 );
00127 CLKSYS_Main_ClockSource_Select ( CLK_SCLKSEL_XOSC_gc );
00128 CLKSYS_Disable ( OSC_RC32MEN_bm );
00129 WaitForSwitches ();
00130
00131
00132 /* Divide Prescaler C by two and Prescaler C by two, and wait
00133 * for user input.
00134 */
00135 CLKSYS_Prescalers_Config ( CLK_PSADIV_1_gc, CLK_PSBCDIV_2_2_gc );
00136 WaitForSwitches ();
00137
00138
00139 /* Enable internal 32 kHz calibrated oscillator and check for
00140 * it to be stable and set prescaler A, B and C to none. Set
00141 * the 32 kHz oscillator as the main clock source. Wait for
00142 * user input while the LEDs toggle.
00143 */
00144 CLKSYS_Enable ( OSC_RC32KEN_bm );
00145 CLKSYS_Prescalers_Config ( CLK_PSADIV_1_gc, CLK_PSBCDIV_1_1_gc );
00146 do {} while ( CLKSYS_IsReady ( OSC_RC32KRDY_bm ) == 0 );
00147 CLKSYS_Main_ClockSource_Select ( CLK_SCLKSEL_RC32K_gc );
00148 CLKSYS_Disable ( OSC_XOSCEN_bm );
00149 WaitForSwitches ();
00150
00151
00152 /* Configure PLL with the 2 MHz RC oscillator as source and
00153 * multiply by 30 to get 60 MHz PLL clock and enable it. Wait
00154 * for it to be stable and set prescaler C to divide by two
00155 * to set the CPU clock to 30 MHz. Disable unused clock and
00156 * wait for user input.
00157 */
00158 CLKSYS_PLL_Config ( OSC_PLLSRC_RC2M_gc, 30 );
00159 CLKSYS_Enable ( OSC_PLLEN_bm );
00160 CLKSYS_Prescalers_Config ( CLK_PSADIV_1_gc, CLK_PSBCDIV_1_2_gc );
00161 do {} while ( CLKSYS_IsReady ( OSC_PLLRDY_bm ) == 0 );
00162 CLKSYS_Main_ClockSource_Select ( CLK_SCLKSEL_PLL_gc );
00163 CLKSYS_Disable ( OSC_XOSCEN_bm );
00164 WaitForSwitches ( );
00165
00166
00167 /* Select 2 MHz RC oscillator as main clock source and diable
00168 * unused clock.
00169 */
00170 do {} while ( CLKSYS_IsReady ( OSC_RC2MRDY_bm ) == 0 );
00171 CLKSYS_Main_ClockSource_Select ( CLK_SCLKSEL_RC2M_gc );
00172 CLKSYS_Disable ( OSC_PLLEN_bm );
00173
00174 }
00175 }
00176
00179 void WaitForSwitches ( void )
00180 {
00181 do {} while ( ( SWITCHPORT .IN & amp; SWITCHMASK ) == SWITCHMASK );
00182 delay_us( 1000 );
00183 do {} while ( ( SWITCHPORT .IN & amp; SWITCHMASK ) != SWITCHMASK );
00184 delay_us( 1000 );
00185 }
00186
00187
00189 ISR (TCC0_OVF_vect)
00190 {
00191 LEDPORT .OUTTGL = LEDMASK ;
00192 }




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avr_compiler.h Go to the documentation of this file. 00001 /* This file has been prepared for Doxygen automatic documentation generation.*/
00045 #ifndef COMPILER_AVR_H
00046 #define COMPILER_AVR_H
00047
00048 #ifndef F_CPU
00049
00050 #define F_CPU 2000000UL
00051 #endif
00052
00053 #include & lt;stdint.h & gt;
00054 #include & lt;stdbool.h & gt;
00055 #include & lt;stdlib.h & gt;
00056
00058 #define AVR_ENTER_CRITICAL_REGION( ) uint8_t volatile saved_sreg = SREG; \
00059 cli();
00060
00064 #define AVR_LEAVE_CRITICAL_REGION( ) SREG = saved_sreg;
00065
00066 #if defined( __ICCAVR__ )
00067
00068 #include & lt;inavr.h & gt;
00069 #include & lt;ioavr.h & gt;
00070 #include & lt;intrinsics.h & gt;
00071 #include & lt;pgmspace.h & gt;
00072
00073 #ifndef __HAS_ELPM__
00074 #define _MEMATTR __flash
00075 #else /* __HAS_ELPM__ */
00076 #define _MEMATTR __farflash
00077 #endif /* __HAS_ELPM__ */
00078
00089 #define delay_us( us ) ( __delay_cycles( ( F_CPU / 1000000UL ) * ( us ) ) )
00090
00104 #define PRAGMA(x) _Pragma( #x )
00105 #define ISR(vec) PRAGMA( vector=vec ) __interrupt void handler_##vec(void)
00106 #define sei( ) (__enable_interrupt( ))
00107 #define cli( ) (__disable_interrupt( ))
00108
00110 #define nop( ) (__no_operation())
00111
00113 #define watchdog_reset( ) (__watchdog_reset( ))
00114
00115
00116 #define INLINE PRAGMA( inline=forced ) static
00117
00118 #define FLASH_DECLARE(x) _MEMATTR x
00119 #define FLASH_STRING(x) ((_MEMATTR const char *)(x))
00120 #define FLASH_STRING_T char const _MEMATTR *
00121 #define FLASH_BYTE_ARRAY_T uint8_t const _MEMATTR *
00122 #define PGM_READ_BYTE(x) *(x)
00123 #define PGM_READ_WORD(x) *(x)
00124
00125 #define SHORTENUM
00126
00127 #elif defined( __GNUC__ )
00128
00129 #include & lt;avr/io.h & gt;
00130 #include & lt;avr/interrupt.h & gt;
00131 #include & lt;avr/pgmspace.h & gt;
00132 #include & lt;util/delay.h & gt;
00133
00135 #define delay_us( us ) (_delay_us( us ))
00136
00137 #define INLINE static inline
00138
00140 #define nop() do { __asm__ __volatile__ ( " nop " ); } while (0)
00141
00142 #define MAIN_TASK_PROLOGUE int
00143
00144
00145 #define MAIN_TASK_EPILOGUE() return -1;
00146
00147 #define SHORTENUM __attribute__ ((packed))
00148
00149 #else
00150 #error Compiler not supported.
00151 #endif
00152
00153 #endif
00154




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All
Functions
Defines



& nbsp;


CCPWrite()
: clksys_driver.c
, clksys_driver.h
CLKSYS_AutoCalibration_Enable()
: clksys_driver.h
, clksys_driver.c
CLKSYS_Configuration_Lock()
: clksys_driver.c
, clksys_driver.h
CLKSYS_Disable()
: clksys_driver.h
, clksys_driver.c
CLKSYS_Main_ClockSource_Select()
: clksys_driver.c
, clksys_driver.h
CLKSYS_PLL_Config()
: clksys_driver.c
, clksys_driver.h
CLKSYS_Prescalers_Config()
: clksys_driver.c
, clksys_driver.h
CLKSYS_RTC_ClockSource_Enable()
: clksys_driver.c
, clksys_driver.h
CLKSYS_XOSC_Config()
: clksys_driver.h
, clksys_driver.c
CLKSYS_XOSC_FailureDetection_Enable()
: clksys_driver.h
, clksys_driver.c
ISR()
: clksys_example.c
main()
: clksys_example.c
WaitForSwitches()
: clksys_example.c





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Xmega Application Note








AVR1003 Using the XMEGA Clock System Documentation

Atmel AVR Application Notes
Introduction
This documents the firmware for the application note.

Compilation Info
This firmware was compiled with IAR Embedded Workbench 5.20.1 and WinAVR 20080411.

To make the project in IAR EWAVR:
Add the .c files (and .S90 files where applicable) for the given example to your project. Use device ATxmega128A1 and enable bit definitions in I/O include files, optimization low for debug target and high for release, output format: ubrof8 for Debug and intel_extended for Release, select Normal DLIB as library.

To make the project in WinAVR:
Add the .c files (and .S files where applicable) for the given example to your project. Use device ATxmega128A1, optimization low for debug target and high for release.

Device Info
All XMEGA devices with the targeted module can be used. The example is written for ATxmega128A1.
Contact Info
For more info about Atmel AVR visit http://www.atmel.com/products/AVR/
For application notes visit http://www.atmel.com/dyn/products/app_notes.asp?family_id=607
Support mail: avr@atmel.com

Revision 2773
Date 2009-09-14 09:47:33 +0200 (ma, 14 sep 2009)

Copyright (c) 2008, Atmel Corporation All rights reserved.
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
3. The name of ATMEL may not be used to endorse or promote products derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY ATMEL " AS IS " AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.



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Xmega Application Note








File List Here is a list of all files with brief descriptions:
avr_compiler.h [code] This file implements some macros that makes the IAR C-compiler and avr-gcc work with the same code base for the AVR architecture
clksys_driver.c [code] XMEGA Clock System driver source file
clksys_driver.h [code] XMEGA Clock System driver header file
clksys_example.c [code] XMEGA Clock System driver example source
documentation.h [code]





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Xmega Application Note









All
Functions
Defines




a
c
f
i
l
m
s
w



Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- a -
AVR_ENTER_CRITICAL_REGION
: avr_compiler.h
AVR_LEAVE_CRITICAL_REGION
: avr_compiler.h

- c -
CCPWrite()
: clksys_driver.c
, clksys_driver.h
CLKSYS_AutoCalibration_Disable
: clksys_driver.h
CLKSYS_AutoCalibration_Enable()
: clksys_driver.c
, clksys_driver.h
CLKSYS_Configuration_Lock()
: clksys_driver.c
, clksys_driver.h
CLKSYS_Disable()
: clksys_driver.c
, clksys_driver.h
CLKSYS_Enable
: clksys_driver.h
CLKSYS_IsReady
: clksys_driver.h
CLKSYS_Main_ClockSource_Select()
: clksys_driver.c
, clksys_driver.h
CLKSYS_PLL_Config()
: clksys_driver.h
, clksys_driver.c
CLKSYS_Prescalers_Config()
: clksys_driver.c
, clksys_driver.h
CLKSYS_RTC_ClockSource_Disable
: clksys_driver.h
CLKSYS_RTC_ClockSource_Enable()
: clksys_driver.h
, clksys_driver.c
CLKSYS_XOSC_Config()
: clksys_driver.h
, clksys_driver.c
CLKSYS_XOSC_FailureDetection_Enable()
: clksys_driver.h
, clksys_driver.c

- f -
F_CPU
: avr_compiler.h

- i -
ISR()
: clksys_example.c

- l -
LEDMASK
: clksys_example.c
LEDPORT
: clksys_example.c

- m -
main()
: clksys_example.c

- s -
SWITCHMASK
: clksys_example.c
SWITCHPORT
: clksys_example.c

- w -
WaitForSwitches()
: clksys_example.c





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avr_compiler.h File Reference This file implements some macros that makes the IAR C-compiler and avr-gcc work with the same code base for the AVR architecture.
More...

#include & lt;stdint.h & gt;
#include & lt;stdbool.h & gt;
#include & lt;stdlib.h & gt;



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This graph shows which files directly or indirectly include this file:







Go to the source code of this file.

Defines
#define & nbsp; AVR_ENTER_CRITICAL_REGION ()

& nbsp; This macro will protect the following code from interrupts.
#define & nbsp; AVR_LEAVE_CRITICAL_REGION () & nbsp; & nbsp; & nbsp;SREG = saved_sreg;

& nbsp; This macro must always be used in conjunction with AVR_ENTER_CRITICAL_REGION so the interrupts are enabled again.
#define & nbsp; F_CPU & nbsp; & nbsp; & nbsp;2000000UL

& nbsp; Define default CPU frequency, if this is not already defined.

Detailed Description
This file implements some macros that makes the IAR C-compiler and avr-gcc work with the same code base for the AVR architecture.

Documentation For comprehensive code documentation, supported compilers, compiler settings and supported devices see readme.html
Author: Atmel Corporation: http://www.atmel.com
Support email: avr@atmel.com
Revision 2772
Date 2009-09-11 12:40:26 +0200 (fr, 11 sep 2009)


Copyright (c) 2008, Atmel Corporation All rights reserved.
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
3. The name of ATMEL may not be used to endorse or promote products derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY ATMEL " AS IS " AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Definition in file avr_compiler.h .
Define Documentation





#define AVR_ENTER_CRITICAL_REGION
(
& nbsp;

& nbsp;) & nbsp;







Value: uint8_t volatile saved_sreg = SREG; \
cli();
This macro will protect the following code from interrupts.


Definition at line 58 of file avr_compiler.h .

Referenced by CCPWrite() .








#define AVR_LEAVE_CRITICAL_REGION
(
& nbsp;

& nbsp;) & nbsp;
& nbsp; & nbsp; & nbsp;SREG = saved_sreg;






This macro must always be used in conjunction with AVR_ENTER_CRITICAL_REGION so the interrupts are enabled again.


Definition at line 64 of file avr_compiler.h .

Referenced by CCPWrite() .








#define F_CPU & nbsp; & nbsp; & nbsp;2000000UL






Define default CPU frequency, if this is not already defined.


Definition at line 50 of file avr_compiler.h .







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clksys_driver.h File Reference XMEGA Clock System driver header file.
More...

#include & quot; avr_compiler.h & quot;



Include dependency graph for clksys_driver.h:








This graph shows which files directly or indirectly include this file:







Go to the source code of this file.

Defines
#define & nbsp; CLKSYS_AutoCalibration_Disable (_clk) & nbsp; & nbsp; & nbsp;( (_clk).CTRL & amp;= ~DFLL_ENABLE_bm )

& nbsp; This macro disables the automatic calibration of the selected internal oscillator.
#define & nbsp; CLKSYS_Enable (_oscSel) & nbsp; & nbsp; & nbsp;( OSC.CTRL |= (_oscSel) )

& nbsp; This macro enables the selected oscillator.
#define & nbsp; CLKSYS_IsReady (_oscSel) & nbsp; & nbsp; & nbsp;( OSC.STATUS & amp; (_oscSel) )

& nbsp; This macro check if selected oscillator is ready.
#define & nbsp; CLKSYS_RTC_ClockSource_Disable () & nbsp; & nbsp; & nbsp;( CLK.RTCCTRL & amp;= ~CLK_RTCEN_bm )

& nbsp; This macro disables routing of clock signals to the Real-Time Counter (RTC).
Functions
void & nbsp; CCPWrite (volatile uint8_t *address, uint8_t value)

& nbsp; CCP write helper function written in assembly.
void & nbsp; CLKSYS_AutoCalibration_Enable (uint8_t clkSource, bool extReference)

& nbsp; This function enables automatic calibration of the selected internal oscillator.
void & nbsp; CLKSYS_Configuration_Lock (void)

& nbsp; This function lock the entire clock system configuration.
uint8_t & nbsp; CLKSYS_Disable (uint8_t oscSel)

& nbsp; This function disables the selected oscillator.
uint8_t & nbsp; CLKSYS_Main_ClockSource_Select (CLK_SCLKSEL_t clockSource)

& nbsp; This function selects the main system clock source.
void & nbsp; CLKSYS_PLL_Config (OSC_PLLSRC_t clockSource, uint8_t factor)

& nbsp; This function configures the internal high-frequency PLL.
void & nbsp; CLKSYS_Prescalers_Config (CLK_PSADIV_t PSAfactor, CLK_PSBCDIV_t PSBCfactor)

& nbsp; This function changes the prescaler configuration.
void & nbsp; CLKSYS_RTC_ClockSource_Enable (CLK_RTCSRC_t clockSource)

& nbsp; This function selects a Real-Time Counter clock source.
void & nbsp; CLKSYS_XOSC_Config (OSC_FRQRANGE_t freqRange, bool lowPower32kHz, OSC_XOSCSEL_t xoscModeSelection)

& nbsp; This function configures the external oscillator.
void & nbsp; CLKSYS_XOSC_FailureDetection_Enable (void)

& nbsp; This function enables the External Oscillator Failure Detection (XOSCFD) feature.

Detailed Description
XMEGA Clock System driver header file.

This file contains the function prototypes and enumerator definitions for various configuration parameters for the XMEGA Clock System driver.
The driver is not intended for size and/or speed critical code, since most functions are just a few lines of code, and the function call overhead would decrease code performance. The driver is intended for rapid prototyping and documentation purposes for getting started with the XMEGA Clock System.
For size and/or speed critical code, it is recommended to copy the function contents directly into your application instead of making a function call.
Application note: AVR1003: Using the XMEGA Clock System
Documentation For comprehensive code documentation, supported compilers, compiler settings and supported devices see readme.html
Author: Atmel Corporation: http://www.atmel.com
Support email: avr@atmel.com
Revision 1665
Date 2008-06-05 09:21:50 +0200 (to, 05 jun 2008)


Copyright (c) 2008, Atmel Corporation All rights reserved.
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
3. The name of ATMEL may not be used to endorse or promote products derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY ATMEL " AS IS " AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Definition in file clksys_driver.h .
Define Documentation





#define CLKSYS_AutoCalibration_Disable
(
_clk & nbsp;

& nbsp;) & nbsp;
& nbsp; & nbsp; & nbsp;( (_clk).CTRL & amp;= ~DFLL_ENABLE_bm )






This macro disables the automatic calibration of the selected internal oscillator.

Parameters:

_clk & nbsp; Clock source calibration to disable, either DFLLRC2M or DFLLRC32M.



Definition at line 105 of file clksys_driver.h .








#define CLKSYS_Enable
(
_oscSel & nbsp;

& nbsp;) & nbsp;
& nbsp; & nbsp; & nbsp;( OSC.CTRL |= (_oscSel) )






This macro enables the selected oscillator.

Note: Note that the oscillator cannot be used as a main system clock source without being enabled and stable first. Check the ready flag before using the clock. The function CLKSYS_IsReady( _oscSel ) can be used to check this.
Parameters:

_oscSel & nbsp; Bitmask of selected clock. Can be one of the following OSC_RC2MEN_bm, OSC_RC32MEN_bm, OSC_RC32KEN_bm, OSC_XOSCEN_bm, OSC_PLLEN_bm.



Definition at line 78 of file clksys_driver.h .

Referenced by main() .








#define CLKSYS_IsReady
(
_oscSel & nbsp;

& nbsp;) & nbsp;
& nbsp; & nbsp; & nbsp;( OSC.STATUS & amp; (_oscSel) )






This macro check if selected oscillator is ready.

This macro will return non-zero if is is running, regardless if it is used as a main clock source or not.
Parameters:

_oscSel & nbsp; Bitmask of selected clock. Can be one of the following OSC_RC2MEN_bm, OSC_RC32MEN_bm, OSC_RC32KEN_bm, OSC_XOSCEN_bm, OSC_PLLEN_bm.


Returns: Non-zero if oscillator is ready and running.

Definition at line 91 of file clksys_driver.h .

Referenced by main() .








#define CLKSYS_RTC_ClockSource_Disable
(
& nbsp;

& nbsp;) & nbsp;
& nbsp; & nbsp; & nbsp;( CLK.RTCCTRL & amp;= ~CLK_RTCEN_bm )






This macro disables routing of clock signals to the Real-Time Counter (RTC).

Disabling the RTC saves power if the RTC is not in use.
Definition at line 98 of file clksys_driver.h .



Function Documentation





void CCPWrite
(
volatile uint8_t * & nbsp;
address ,




uint8_t & nbsp;
value & nbsp;



)







CCP write helper function written in assembly.

This function is written in assembly because of the timecritial operation of writing to the registers.
Parameters:

address & nbsp; A pointer to the address to write to.
value & nbsp; The value to put in to the register.



Definition at line 77 of file clksys_driver.c .

References AVR_ENTER_CRITICAL_REGION , and AVR_LEAVE_CRITICAL_REGION .

Referenced by CLKSYS_Configuration_Lock() , CLKSYS_Main_ClockSource_Select() , CLKSYS_Prescalers_Config() , and CLKSYS_XOSC_FailureDetection_Enable() .
00078 {
00079 #ifdef __ICCAVR__
00080
00081 // Store global interrupt setting in scratch register and disable interrupts.
00082 asm ( " in R1, 0x3F \n "
00083 " cli "
00084 );
00085
00086 // Move destination address pointer to Z pointer registers.
00087 asm ( " movw r30, r16 " );
00088 #ifdef RAMPZ
00089 asm ( " ldi R16, 0 \n "
00090 " out 0x3B, R16 "
00091 );
00092
00093 #endif
00094 asm ( " ldi r16, 0xD8 \n "
00095 " out 0x34, r16 \n "
00096 #if (__MEMORY_MODEL__ == 1)
00097 " st Z, r17 \n " );
00098 #elif (__MEMORY_MODEL__ == 2)
00099 " st Z, r18 \n " );
00100 #else /* (__MEMORY_MODEL__ == 3) || (__MEMORY_MODEL__ == 5) */
00101 " st Z, r19 \n " );
00102 #endif /* __MEMORY_MODEL__ */
00103
00104 // Restore global interrupt setting from scratch register.
00105 asm ( " out 0x3F, R1 " );
00106
00107 #elif defined __GNUC__
00108 AVR_ENTER_CRITICAL_REGION ( );
00109 volatile uint8_t * tmpAddr = address;
00110 #ifdef RAMPZ
00111 RAMPZ = 0;
00112 #endif
00113 asm volatile (
00114 " movw r30, %0 " " \n\t "
00115 " ldi r16, %2 " " \n\t "
00116 " out %3, r16 " " \n\t "
00117 " st Z, %1 " " \n\t "
00118 :
00119 : " r " (tmpAddr), " r " (value), " M " (CCP_IOREG_gc), " i " ( & amp;CCP)
00120 : " r16 " , " r30 " , " r31 "
00121 );
00122
00123 AVR_LEAVE_CRITICAL_REGION ( );
00124 #endif
00125 }










void CLKSYS_AutoCalibration_Enable
(
uint8_t & nbsp;
clkSource ,




bool & nbsp;
extReference & nbsp;



)







This function enables automatic calibration of the selected internal oscillator.

Either the internal 32kHz RC oscillator or an external 32kHz crystal can be used as a calibration reference. The user must make sure that the selected reference is ready and running.
Parameters:

clkSource & nbsp; Clock source to calibrate, either OSC_RC2MCREF_bm or OSC_RC32MCREF_bm.
extReference & nbsp; True if external crystal should be used as reference.



Definition at line 260 of file clksys_driver.c .
00261 {
00262 OSC.DFLLCTRL = ( OSC.DFLLCTRL & amp; ~clkSource ) |
00263 ( extReference ? clkSource : 0 );
00264 if (clkSource == OSC_RC2MCREF_bm) {
00265 DFLLRC2M.CTRL |= DFLL_ENABLE_bm;
00266 } else if (clkSource == OSC_RC32MCREF_bm) {
00267 DFLLRC32M.CTRL |= DFLL_ENABLE_bm;
00268 }
00269 }










void CLKSYS_Configuration_Lock
(
void & nbsp;

& nbsp;) & nbsp;







This function lock the entire clock system configuration.

This will lock the configuration until the next reset, or until the External Oscillator Failure Detections (XOSCFD) feature detects a failure and switches to internal 2MHz RC oscillator.
Definition at line 292 of file clksys_driver.c .

References CCPWrite() .
00293 {
00294 CCPWrite ( & amp;CLK.LOCK, CLK_LOCK_bm );
00295 }





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uint8_t CLKSYS_Disable
(
uint8_t & nbsp;
oscSel
& nbsp;) & nbsp;







This function disables the selected oscillator.

This function will disable the selected oscillator if possible. If it is currently used as a main system clock source, hardware will disregard the disable attempt, and this function will return zero. If it fails, change to another main system clock source and try again.
Parameters:

oscSel & nbsp; Bitmask of selected clock. Can be one of the following OSC_RC2MEN_bm, OSC_RC32MEN_bm, OSC_RC32KEN_bm, OSC_XOSCEN_bm, OSC_PLLEN_bm.


Returns: Non-zero if oscillator was disabled successfully.

Definition at line 187 of file clksys_driver.c .

Referenced by main() .
00188 {
00189 OSC.CTRL & amp;= ~oscSel;
00190 uint8_t clkEnabled = OSC.CTRL & amp; oscSel;
00191 return clkEnabled;
00192 }










uint8_t CLKSYS_Main_ClockSource_Select
(
CLK_SCLKSEL_t & nbsp;
clockSource
& nbsp;) & nbsp;







This function selects the main system clock source.

Hardware will disregard any attempts to select a clock source that is not enabled or not stable. If the change fails, make sure the source is ready and running and try again.
Parameters:

clockSource & nbsp; Clock source to use as input for the system clock prescaler block.


Returns: Non-zero if change was successful.

Definition at line 225 of file clksys_driver.c .

References CCPWrite() .

Referenced by main() .
00226 {
00227 uint8_t clkCtrl = ( CLK.CTRL & amp; ~CLK_SCLKSEL_gm ) | clockSource;
00228 CCPWrite ( & amp;CLK.CTRL, clkCtrl );
00229 clkCtrl = ( CLK.CTRL & amp; clockSource );
00230 return clkCtrl;
00231 }





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void CLKSYS_PLL_Config
(
OSC_PLLSRC_t & nbsp;
clockSource ,




uint8_t & nbsp;
factor & nbsp;



)







This function configures the internal high-frequency PLL.

Configuration of the internal high-frequency PLL to the correct values. It is used to define the input of the PLL and the factor of multiplication of the input clock source.
Note: Note that the oscillator cannot be used as a main system clock source without being enabled and stable first. Check the ready flag before using the clock. The macro CLKSYS_IsReady( _oscSel ) can be used to check this.
Parameters:

clockSource & nbsp; Reference clock source for the PLL, must be above 0.4MHz.
factor & nbsp; PLL multiplication factor, must be from 1 to 31, inclusive.



Definition at line 167 of file clksys_driver.c .

Referenced by main() .
00168 {
00169 factor & amp;= OSC_PLLFAC_gm;
00170 OSC.PLLCTRL = (uint8_t) clockSource | ( factor & lt; & lt; OSC_PLLFAC_gp );
00171 }










void CLKSYS_Prescalers_Config
(
CLK_PSADIV_t & nbsp;
PSAfactor ,




CLK_PSBCDIV_t & nbsp;
PSBCfactor & nbsp;



)







This function changes the prescaler configuration.

Change the configuration of the three system clock prescaler is one single operation. The user must make sure that the main CPU clock does not exceed recommended limits.
Parameters:

PSAfactor & nbsp; Prescaler A division factor, OFF or 2 to 512 in powers of two.
PSBCfactor & nbsp; Prescaler B and C division factor, in the combination of (1,1), (1,2), (4,1) or (2,2).



Definition at line 206 of file clksys_driver.c .

References CCPWrite() .

Referenced by main() .
00208 {
00209 uint8_t PSconfig = (uint8_t) PSAfactor | PSBCfactor;
00210 CCPWrite ( & amp;CLK.PSCTRL, PSconfig );
00211 }





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void CLKSYS_RTC_ClockSource_Enable
(
CLK_RTCSRC_t & nbsp;
clockSource
& nbsp;) & nbsp;







This function selects a Real-Time Counter clock source.

Selects the clock source for use by the Real-Time Counter (RTC) and enables clock signal routing to the RTC module.
Parameters:

clockSource & nbsp; Clock source to use for the RTC.



Definition at line 241 of file clksys_driver.c .
00242 {
00243 CLK.RTCCTRL = ( CLK.RTCCTRL & amp; ~CLK_RTCSRC_gm ) |
00244 clockSource |
00245 CLK_RTCEN_bm;
00246 }










void CLKSYS_XOSC_Config
(
OSC_FRQRANGE_t & nbsp;
freqRange ,




bool & nbsp;
lowPower32kHz ,




OSC_XOSCSEL_t & nbsp;
xoscModeSelection & nbsp;



)







This function configures the external oscillator.

Note: Note that the oscillator cannot be used as a main system clock source without being enabled and stable first. Check the ready flag before using the clock. The macro CLKSYS_IsReady( _oscSel ) can be used to check this.
Parameters:

freqRange & nbsp; Frequency range for high-frequency crystal, does not apply for external clock or 32kHz crystals.
lowPower32kHz & nbsp; True of high-quality watch crystals are used and low-power oscillator is desired.
xoscModeSelection & nbsp; Combined selection of oscillator type (or external clock) and startup times.



Definition at line 141 of file clksys_driver.c .

Referenced by main() .
00144 {
00145 OSC.XOSCCTRL = (uint8_t) freqRange |
00146 ( lowPower32kHz ? OSC_X32KLPM_bm : 0 ) |
00147 xoscModeSelection;
00148 }










void CLKSYS_XOSC_FailureDetection_Enable
(
void & nbsp;

& nbsp;) & nbsp;







This function enables the External Oscillator Failure Detection (XOSCFD) feature.

The feature will stay enabled until next reset. Note that the XOSCFD _will_ issue the XOSCF Non-maskable Interrupt (NMI) regardless of any interrupt priorities and settings. Therefore, make sure that a handler is implemented for the XOSCF NMI when you enable it.
Definition at line 280 of file clksys_driver.c .

References CCPWrite() .
00281 {
00282 CCPWrite ( & amp;OSC.XOSCFAIL, ( OSC_XOSCFDIF_bm | OSC_XOSCFDEN_bm ) );
00283 }





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clksys_driver.c File Reference XMEGA Clock System driver source file.
More...

#include & quot; clksys_driver.h & quot;



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Go to the source code of this file.

Functions
void & nbsp; CCPWrite (volatile uint8_t *address, uint8_t value)

& nbsp; CCP write helper function written in assembly.
void & nbsp; CLKSYS_AutoCalibration_Enable (uint8_t clkSource, bool extReference)

& nbsp; This function enables automatic calibration of the selected internal oscillator.
void & nbsp; CLKSYS_Configuration_Lock (void)

& nbsp; This function lock the entire clock system configuration.
uint8_t & nbsp; CLKSYS_Disable (uint8_t oscSel)

& nbsp; This function disables the selected oscillator.
uint8_t & nbsp; CLKSYS_Main_ClockSource_Select (CLK_SCLKSEL_t clockSource)

& nbsp; This function selects the main system clock source.
void & nbsp; CLKSYS_PLL_Config (OSC_PLLSRC_t clockSource, uint8_t factor)

& nbsp; This function configures the internal high-frequency PLL.
void & nbsp; CLKSYS_Prescalers_Config (CLK_PSADIV_t PSAfactor, CLK_PSBCDIV_t PSBCfactor)

& nbsp; This function changes the prescaler configuration.
void & nbsp; CLKSYS_RTC_ClockSource_Enable (CLK_RTCSRC_t clockSource)

& nbsp; This function selects a Real-Time Counter clock source.
void & nbsp; CLKSYS_XOSC_Config (OSC_FRQRANGE_t freqRange, bool lowPower32kHz, OSC_XOSCSEL_t xoscModeSelection)

& nbsp; This function configures the external oscillator.
void & nbsp; CLKSYS_XOSC_FailureDetection_Enable (void)

& nbsp; This function enables the External Oscillator Failure Detection (XOSCFD) feature.

Detailed Description
XMEGA Clock System driver source file.

This file contains the function implementations for the XMEGA Clock System driver.
The driver is not intended for size and/or speed critical code, since most functions are just a few lines of code, and the function call overhead would decrease code performance. The driver is intended for rapid prototyping and documentation purposes for getting started with the XMEGA Clock System.
For size and/or speed critical code, it is recommended to copy the function contents directly into your application instead of making a function call.
Several functions use the following construct: " some_register = ... | (some_parameter ? SOME_BIT_bm : 0) | ... " Although the use of the ternary operator ( if ? then : else ) is discouraged, in some occasions the operator makes it possible to write pretty clean and neat code. In this driver, the construct is used to set or not set a configuration bit based on a boolean input parameter, such as the " some_parameter " in the example above.
Application note: AVR1003: Using the XMEGA Clock System
Documentation For comprehensive code documentation, supported compilers, compiler settings and supported devices see readme.html
Author: Atmel Corporation: http://www.atmel.com
Support email: avr@atmel.com
Revision 2771
Date 2009-09-11 11:54:26 +0200 (fr, 11 sep 2009)


Copyright (c) 2008, Atmel Corporation All rights reserved.
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
3. The name of ATMEL may not be used to endorse or promote products derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY ATMEL " AS IS " AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Definition in file clksys_driver.c .
Function Documentation





void CCPWrite
(
volatile uint8_t * & nbsp;
address ,




uint8_t & nbsp;
value & nbsp;



)







CCP write helper function written in assembly.

This function is written in assembly because of the timecritial operation of writing to the registers.
Parameters:

address & nbsp; A pointer to the address to write to.
value & nbsp; The value to put in to the register.



Definition at line 77 of file clksys_driver.c .

References AVR_ENTER_CRITICAL_REGION , and AVR_LEAVE_CRITICAL_REGION .

Referenced by CLKSYS_Configuration_Lock() , CLKSYS_Main_ClockSource_Select() , CLKSYS_Prescalers_Config() , and CLKSYS_XOSC_FailureDetection_Enable() .
00078 {
00079 #ifdef __ICCAVR__
00080
00081 // Store global interrupt setting in scratch register and disable interrupts.
00082 asm ( " in R1, 0x3F \n "
00083 " cli "
00084 );
00085
00086 // Move destination address pointer to Z pointer registers.
00087 asm ( " movw r30, r16 " );
00088 #ifdef RAMPZ
00089 asm ( " ldi R16, 0 \n "
00090 " out 0x3B, R16 "
00091 );
00092
00093 #endif
00094 asm ( " ldi r16, 0xD8 \n "
00095 " out 0x34, r16 \n "
00096 #if (__MEMORY_MODEL__ == 1)
00097 " st Z, r17 \n " );
00098 #elif (__MEMORY_MODEL__ == 2)
00099 " st Z, r18 \n " );
00100 #else /* (__MEMORY_MODEL__ == 3) || (__MEMORY_MODEL__ == 5) */
00101 " st Z, r19 \n " );
00102 #endif /* __MEMORY_MODEL__ */
00103
00104 // Restore global interrupt setting from scratch register.
00105 asm ( " out 0x3F, R1 " );
00106
00107 #elif defined __GNUC__
00108 AVR_ENTER_CRITICAL_REGION ( );
00109 volatile uint8_t * tmpAddr = address;
00110 #ifdef RAMPZ
00111 RAMPZ = 0;
00112 #endif
00113 asm volatile (
00114 " movw r30, %0 " " \n\t "
00115 " ldi r16, %2 " " \n\t "
00116 " out %3, r16 " " \n\t "
00117 " st Z, %1 " " \n\t "
00118 :
00119 : " r " (tmpAddr), " r " (value), " M " (CCP_IOREG_gc), " i " ( & amp;CCP)
00120 : " r16 " , " r30 " , " r31 "
00121 );
00122
00123 AVR_LEAVE_CRITICAL_REGION ( );
00124 #endif
00125 }










void CLKSYS_AutoCalibration_Enable
(
uint8_t & nbsp;
clkSource ,




bool & nbsp;
extReference & nbsp;



)







This function enables automatic calibration of the selected internal oscillator.

Either the internal 32kHz RC oscillator or an external 32kHz crystal can be used as a calibration reference. The user must make sure that the selected reference is ready and running.
Parameters:

clkSource & nbsp; Clock source to calibrate, either OSC_RC2MCREF_bm or OSC_RC32MCREF_bm.
extReference & nbsp; True if external crystal should be used as reference.



Definition at line 260 of file clksys_driver.c .
00261 {
00262 OSC.DFLLCTRL = ( OSC.DFLLCTRL & amp; ~clkSource ) |
00263 ( extReference ? clkSource : 0 );
00264 if (clkSource == OSC_RC2MCREF_bm) {
00265 DFLLRC2M.CTRL |= DFLL_ENABLE_bm;
00266 } else if (clkSource == OSC_RC32MCREF_bm) {
00267 DFLLRC32M.CTRL |= DFLL_ENABLE_bm;
00268 }
00269 }










void CLKSYS_Configuration_Lock
(
void & nbsp;

& nbsp;) & nbsp;







This function lock the entire clock system configuration.

This will lock the configuration until the next reset, or until the External Oscillator Failure Detections (XOSCFD) feature detects a failure and switches to internal 2MHz RC oscillator.
Definition at line 292 of file clksys_driver.c .

References CCPWrite() .
00293 {
00294 CCPWrite ( & amp;CLK.LOCK, CLK_LOCK_bm );
00295 }





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uint8_t CLKSYS_Disable
(
uint8_t & nbsp;
oscSel
& nbsp;) & nbsp;







This function disables the selected oscillator.

This function will disable the selected oscillator if possible. If it is currently used as a main system clock source, hardware will disregard the disable attempt, and this function will return zero. If it fails, change to another main system clock source and try again.
Parameters:

oscSel & nbsp; Bitmask of selected clock. Can be one of the following OSC_RC2MEN_bm, OSC_RC32MEN_bm, OSC_RC32KEN_bm, OSC_XOSCEN_bm, OSC_PLLEN_bm.


Returns: Non-zero if oscillator was disabled successfully.

Definition at line 187 of file clksys_driver.c .

Referenced by main() .
00188 {
00189 OSC.CTRL & amp;= ~oscSel;
00190 uint8_t clkEnabled = OSC.CTRL & amp; oscSel;
00191 return clkEnabled;
00192 }










uint8_t CLKSYS_Main_ClockSource_Select
(
CLK_SCLKSEL_t & nbsp;
clockSource
& nbsp;) & nbsp;







This function selects the main system clock source.

Hardware will disregard any attempts to select a clock source that is not enabled or not stable. If the change fails, make sure the source is ready and running and try again.
Parameters:

clockSource & nbsp; Clock source to use as input for the system clock prescaler block.


Returns: Non-zero if change was successful.

Definition at line 225 of file clksys_driver.c .

References CCPWrite() .

Referenced by main() .
00226 {
00227 uint8_t clkCtrl = ( CLK.CTRL & amp; ~CLK_SCLKSEL_gm ) | clockSource;
00228 CCPWrite ( & amp;CLK.CTRL, clkCtrl );
00229 clkCtrl = ( CLK.CTRL & amp; clockSource );
00230 return clkCtrl;
00231 }





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void CLKSYS_PLL_Config
(
OSC_PLLSRC_t & nbsp;
clockSource ,




uint8_t & nbsp;
factor & nbsp;



)







This function configures the internal high-frequency PLL.

Configuration of the internal high-frequency PLL to the correct values. It is used to define the input of the PLL and the factor of multiplication of the input clock source.
Note: Note that the oscillator cannot be used as a main system clock source without being enabled and stable first. Check the ready flag before using the clock. The macro CLKSYS_IsReady( _oscSel ) can be used to check this.
Parameters:

clockSource & nbsp; Reference clock source for the PLL, must be above 0.4MHz.
factor & nbsp; PLL multiplication factor, must be from 1 to 31, inclusive.



Definition at line 167 of file clksys_driver.c .

Referenced by main() .
00168 {
00169 factor & amp;= OSC_PLLFAC_gm;
00170 OSC.PLLCTRL = (uint8_t) clockSource | ( factor & lt; & lt; OSC_PLLFAC_gp );
00171 }










void CLKSYS_Prescalers_Config
(
CLK_PSADIV_t & nbsp;
PSAfactor ,




CLK_PSBCDIV_t & nbsp;
PSBCfactor & nbsp;



)







This function changes the prescaler configuration.

Change the configuration of the three system clock prescaler is one single operation. The user must make sure that the main CPU clock does not exceed recommended limits.
Parameters:

PSAfactor & nbsp; Prescaler A division factor, OFF or 2 to 512 in powers of two.
PSBCfactor & nbsp; Prescaler B and C division factor, in the combination of (1,1), (1,2), (4,1) or (2,2).



Definition at line 206 of file clksys_driver.c .

References CCPWrite() .

Referenced by main() .
00208 {
00209 uint8_t PSconfig = (uint8_t) PSAfactor | PSBCfactor;
00210 CCPWrite ( & amp;CLK.PSCTRL, PSconfig );
00211 }





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void CLKSYS_RTC_ClockSource_Enable
(
CLK_RTCSRC_t & nbsp;
clockSource
& nbsp;) & nbsp;







This function selects a Real-Time Counter clock source.

Selects the clock source for use by the Real-Time Counter (RTC) and enables clock signal routing to the RTC module.
Parameters:

clockSource & nbsp; Clock source to use for the RTC.



Definition at line 241 of file clksys_driver.c .
00242 {
00243 CLK.RTCCTRL = ( CLK.RTCCTRL & amp; ~CLK_RTCSRC_gm ) |
00244 clockSource |
00245 CLK_RTCEN_bm;
00246 }










void CLKSYS_XOSC_Config
(
OSC_FRQRANGE_t & nbsp;
freqRange ,




bool & nbsp;
lowPower32kHz ,




OSC_XOSCSEL_t & nbsp;
xoscModeSelection & nbsp;



)







This function configures the external oscillator.

Note: Note that the oscillator cannot be used as a main system clock source without being enabled and stable first. Check the ready flag before using the clock. The macro CLKSYS_IsReady( _oscSel ) can be used to check this.
Parameters:

freqRange & nbsp; Frequency range for high-frequency crystal, does not apply for external clock or 32kHz crystals.
lowPower32kHz & nbsp; True of high-quality watch crystals are used and low-power oscillator is desired.
xoscModeSelection & nbsp; Combined selection of oscillator type (or external clock) and startup times.



Definition at line 141 of file clksys_driver.c .

Referenced by main() .
00144 {
00145 OSC.XOSCCTRL = (uint8_t) freqRange |
00146 ( lowPower32kHz ? OSC_X32KLPM_bm : 0 ) |
00147 xoscModeSelection;
00148 }










void CLKSYS_XOSC_FailureDetection_Enable
(
void & nbsp;

& nbsp;) & nbsp;







This function enables the External Oscillator Failure Detection (XOSCFD) feature.

The feature will stay enabled until next reset. Note that the XOSCFD _will_ issue the XOSCF Non-maskable Interrupt (NMI) regardless of any interrupt priorities and settings. Therefore, make sure that a handler is implemented for the XOSCF NMI when you enable it.
Definition at line 280 of file clksys_driver.c .

References CCPWrite() .
00281 {
00282 CCPWrite ( & amp;OSC.XOSCFAIL, ( OSC_XOSCFDIF_bm | OSC_XOSCFDEN_bm ) );
00283 }





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@DOC_TITLE@












Generated on Mon Sep 14 09:48:10 2009 for AVR1003 Using the XMEGA Clock System by 1.5.8


xMega_official_drivers_and_examples.rar > graph_legend.html

@DOC_TITLE@







Xmega Application Note








Graph Legend This page explains how to interpret the graphs that are generated by doxygen.
Consider the following example: /*! Invisible class because of truncation */
class Invisible { };

/*! Truncated class, inheritance relation is hidden */
class Truncated : public Invisible { };

/* Class not documented with doxygen comments */
class Undocumented { };

/*! Class that is inherited using public inheritance */
class PublicBase : public Truncated { };

/*! A template class */
template & lt; class T & gt; class Templ { };

/*! Class that is inherited using protected inheritance */
class ProtectedBase { };

/*! Class that is inherited using private inheritance */
class PrivateBase { };

/*! Class that is used by the Inherited class */
class Used { };

/*! Super class that inherits a number of other classes */
class Inherited : public PublicBase,
protected ProtectedBase,
private PrivateBase,
public Undocumented,
public Templ & lt;int & gt;
{
private :
Used *m_usedClass;
};
This will result in the following graph:




The boxes in the above graph have the following meaning:

A filled gray box represents the struct or class for which the graph is generated.

A box with a black border denotes a documented struct or class.

A box with a grey border denotes an undocumented struct or class.

A box with a red border denotes a documented struct or class forwhich not all inheritance/containment relations are shown. A graph is truncated if it does not fit within the specified boundaries.

The arrows have the following meaning:

A dark blue arrow is used to visualize a public inheritance relation between two classes.

A dark green arrow is used for protected inheritance.

A dark red arrow is used for private inheritance.

A purple dashed arrow is used if a class is contained or used by another class. The arrow is labeled with the variable(s) through which the pointed class or struct is accessible.

A yellow dashed arrow denotes a relation between a template instance and the template class it was instantiated from. The arrow is labeled with the template parameters of the instance.





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Generated on Mon Sep 14 09:48:10 2009 for AVR1003 Using the XMEGA Clock System by 1.5.8


xMega_official_drivers_and_examples.rar > a00007.html

@DOC_TITLE@







Xmega Application Note







clksys_driver.c Go to the documentation of this file. 00001 /* This file has been prepared for Doxygen automatic documentation generation.*/
00067 #include " clksys_driver.h "
00068
00077 void CCPWrite ( volatile uint8_t * address, uint8_t value )
00078 {
00079 #ifdef __ICCAVR__
00080
00081 // Store global interrupt setting in scratch register and disable interrupts.
00082 asm ( " in R1, 0x3F \n "
00083 " cli "
00084 );
00085
00086 // Move destination address pointer to Z pointer registers.
00087 asm ( " movw r30, r16 " );
00088 #ifdef RAMPZ
00089 asm ( " ldi R16, 0 \n "
00090 " out 0x3B, R16 "
00091 );
00092
00093 #endif
00094 asm ( " ldi r16, 0xD8 \n "
00095 " out 0x34, r16 \n "
00096 #if (__MEMORY_MODEL__ == 1)
00097 " st Z, r17 \n " );
00098 #elif (__MEMORY_MODEL__ == 2)
00099 " st Z, r18 \n " );
00100 #else /* (__MEMORY_MODEL__ == 3) || (__MEMORY_MODEL__ == 5) */
00101 " st Z, r19 \n " );
00102 #endif /* __MEMORY_MODEL__ */
00103
00104 // Restore global interrupt setting from scratch register.
00105 asm ( " out 0x3F, R1 " );
00106
00107 #elif defined __GNUC__
00108 AVR_ENTER_CRITICAL_REGION ( );
00109 volatile uint8_t * tmpAddr = address;
00110 #ifdef RAMPZ
00111 RAMPZ = 0;
00112 #endif
00113 asm volatile (
00114 " movw r30, %0 " " \n\t "
00115 " ldi r16, %2 " " \n\t "
00116 " out %3, r16 " " \n\t "
00117 " st Z, %1 " " \n\t "
00118 :
00119 : " r " (tmpAddr), " r " (value), " M " (CCP_IOREG_gc), " i " ( & amp;CCP)
00120 : " r16 " , " r30 " , " r31 "
00121 );
00122
00123 AVR_LEAVE_CRITICAL_REGION ( );
00124 #endif
00125 }
00126
00141 void CLKSYS_XOSC_Config ( OSC_FRQRANGE_t freqRange,
00142 bool lowPower32kHz,
00143 OSC_XOSCSEL_t xoscModeSelection )
00144 {
00145 OSC.XOSCCTRL = (uint8_t) freqRange |
00146 ( lowPower32kHz ? OSC_X32KLPM_bm : 0 ) |
00147 xoscModeSelection;
00148 }
00149
00150
00167 void CLKSYS_PLL_Config ( OSC_PLLSRC_t clockSource, uint8_t factor )
00168 {
00169 factor & amp;= OSC_PLLFAC_gm;
00170 OSC.PLLCTRL = (uint8_t) clockSource | ( factor & lt; & lt; OSC_PLLFAC_gp );
00171 }
00172
00173
00187 uint8_t CLKSYS_Disable ( uint8_t oscSel )
00188 {
00189 OSC.CTRL & amp;= ~oscSel;
00190 uint8_t clkEnabled = OSC.CTRL & amp; oscSel;
00191 return clkEnabled;
00192 }
00193
00194
00206 void CLKSYS_Prescalers_Config ( CLK_PSADIV_t PSAfactor,
00207 CLK_PSBCDIV_t PSBCfactor )
00208 {
00209 uint8_t PSconfig = (uint8_t) PSAfactor | PSBCfactor;
00210 CCPWrite ( & amp;CLK.PSCTRL, PSconfig );
00211 }
00212
00213
00225 uint8_t CLKSYS_Main_ClockSource_Select ( CLK_SCLKSEL_t clockSource )
00226 {
00227 uint8_t clkCtrl = ( CLK.CTRL & amp; ~CLK_SCLKSEL_gm ) | clockSource;
00228 CCPWrite ( & amp;CLK.CTRL, clkCtrl );
00229 clkCtrl = ( CLK.CTRL & amp; clockSource );
00230 return clkCtrl;
00231 }
00232
00233
00241 void CLKSYS_RTC_ClockSource_Enable ( CLK_RTCSRC_t clockSource )
00242 {
00243 CLK.RTCCTRL = ( CLK.RTCCTRL & amp; ~CLK_RTCSRC_gm ) |
00244 clockSource |
00245 CLK_RTCEN_bm;
00246 }
00247
00248
00260 void CLKSYS_AutoCalibration_Enable ( uint8_t clkSource, bool extReference )
00261 {
00262 OSC.DFLLCTRL = ( OSC.DFLLCTRL & amp; ~clkSource ) |
00263 ( extReference ? clkSource : 0 );
00264 if (clkSource == OSC_RC2MCREF_bm) {
00265 DFLLRC2M.CTRL |= DFLL_ENABLE_bm;
00266 } else if (clkSource == OSC_RC32MCREF_bm) {
00267 DFLLRC32M.CTRL |= DFLL_ENABLE_bm;
00268 }
00269 }
00270
00271
00280 void CLKSYS_XOSC_FailureDetection_Enable ( void )
00281 {
00282 CCPWrite ( & amp;OSC.XOSCFAIL, ( OSC_XOSCFDIF_bm | OSC_XOSCFDEN_bm ) );
00283 }
00284
00285
00292 void CLKSYS_Configuration_Lock ( void )
00293 {
00294 CCPWrite ( & amp;CLK.LOCK, CLK_LOCK_bm );
00295 }
00296




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xMega_official_drivers_and_examples.rar > a00009.html

@DOC_TITLE@







Xmega Application Note







clksys_driver.h Go to the documentation of this file. 00001 /* This file has been prepared for Doxygen automatic documentation generation.*/
00059 #ifndef CLKSYS_DRIVER_H
00060 #define CLKSYS_DRIVER_H
00061
00062 #include " avr_compiler.h "
00063
00064
00065 /* Definitions of macros. */
00066
00078 #define CLKSYS_Enable( _oscSel ) ( OSC.CTRL |= (_oscSel) )
00079
00091 #define CLKSYS_IsReady( _oscSel ) ( OSC.STATUS & amp; (_oscSel) )
00092
00098 #define CLKSYS_RTC_ClockSource_Disable() ( CLK.RTCCTRL & amp;= ~CLK_RTCEN_bm )
00099
00105 #define CLKSYS_AutoCalibration_Disable( _clk ) ( (_clk).CTRL & amp;= ~DFLL_ENABLE_bm )
00106
00107
00108 /* Prototyping of function. Detailed information is found in source file. */
00109 void CCPWrite ( volatile uint8_t * address, uint8_t value );
00110 void CLKSYS_XOSC_Config ( OSC_FRQRANGE_t freqRange,
00111 bool lowPower32kHz,
00112 OSC_XOSCSEL_t xoscModeSelection );
00113 void CLKSYS_PLL_Config ( OSC_PLLSRC_t clockSource, uint8_t factor );
00114 uint8_t CLKSYS_Disable ( uint8_t oscSel );
00115 void CLKSYS_Prescalers_Config ( CLK_PSADIV_t PSAfactor,
00116 CLK_PSBCDIV_t PSBCfactor );
00117 uint8_t CLKSYS_Main_ClockSource_Select ( CLK_SCLKSEL_t clockSource );
00118 void CLKSYS_RTC_ClockSource_Enable ( CLK_RTCSRC_t clockSource );
00119 void CLKSYS_AutoCalibration_Enable ( uint8_t clkSource, bool extReference );
00120 void CLKSYS_XOSC_FailureDetection_Enable ( void );
00121 void CLKSYS_Configuration_Lock ( void );
00122
00123
00124 #endif




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xMega_official_drivers_and_examples.rar > globals_defs.html

@DOC_TITLE@







Xmega Application Note









All
Functions
Defines



& nbsp;


AVR_ENTER_CRITICAL_REGION
: avr_compiler.h
AVR_LEAVE_CRITICAL_REGION
: avr_compiler.h
CLKSYS_AutoCalibration_Disable
: clksys_driver.h
CLKSYS_Enable
: clksys_driver.h
CLKSYS_IsReady
: clksys_driver.h
CLKSYS_RTC_ClockSource_Disable
: clksys_driver.h
F_CPU
: avr_compiler.h
LEDMASK
: clksys_example.c
LEDPORT
: clksys_example.c
SWITCHMASK
: clksys_example.c
SWITCHPORT
: clksys_example.c





@DOC_TITLE@












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xMega_official_drivers_and_examples.rar > tree.html

TreeView







AVR1003 Using the XMEGA Clock System

Main Page
File List

avr_compiler.h
clksys_driver.c
clksys_driver.h
clksys_example.c
documentation.h

Globals


xMega_official_drivers_and_examples.rar > clksys_driver.c

/* This file has been prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief XMEGA Clock System driver source file.
*
* This file contains the function implementations for the XMEGA Clock
* System driver.
*
* The driver is not intended for size and/or speed critical code, since
* most functions are just a few lines of code, and the function call
* overhead would decrease code performance. The driver is intended for
* rapid prototyping and documentation purposes for getting started with
* the XMEGA Clock System.
*
* For size and/or speed critical code, it is recommended to copy the
* function contents directly into your application instead of making
* a function call.
*
* Several functions use the following construct:
* " some_register = ... | (some_parameter ? SOME_BIT_bm : 0) | ... "
* Although the use of the ternary operator ( if ? then : else ) is
* discouraged, in some occasions the operator makes it possible to
* write pretty clean and neat code. In this driver, the construct is
* used to set or not set a configuration bit based on a boolean input
* parameter, such as the " some_parameter " in the example above.
*
* \par Application note:
* AVR1003: Using the XMEGA Clock System
*
* \par Documentation
* For comprehensive code documentation, supported compilers, compiler
* settings and supported devices see readme.html
*
* \author
* Atmel Corporation: http://www.atmel.com \n
* Support email: avr@atmel.com
*
* $Revision: 2771 $
* $Date: 2009-09-11 11:54:26 +0200 (fr, 11 sep 2009) $ \n
*
* Copyright (c) 2008, Atmel Corporation All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of ATMEL may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL " AS IS " AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
* SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*****************************************************************************/
#include " clksys_driver.h "

/*! \brief CCP write helper function written in assembly.
*
* This function is written in assembly because of the timecritial
* operation of writing to the registers.
*
* \param address A pointer to the address to write to.
* \param value The value to put in to the register.
*/
void CCPWrite( volatile uint8_t * address, uint8_t value )
{
#ifdef __ICCAVR__

// Store global interrupt setting in scratch register and disable interrupts.
asm( " in R1, 0x3F \n "
" cli "
);

// Move destination address pointer to Z pointer registers.
asm( " movw r30, r16 " );
#ifdef RAMPZ
asm( " ldi R16, 0 \n "
" out 0x3B, R16 "
);

#endif
asm( " ldi r16, 0xD8 \n "
" out 0x34, r16 \n "
#if (__MEMORY_MODEL__ == 1)
" st Z, r17 \n " );
#elif (__MEMORY_MODEL__ == 2)
" st Z, r18 \n " );
#else /* (__MEMORY_MODEL__ == 3) || (__MEMORY_MODEL__ == 5) */
" st Z, r19 \n " );
#endif /* __MEMORY_MODEL__ */

// Restore global interrupt setting from scratch register.
asm( " out 0x3F, R1 " );

#elif defined __GNUC__
AVR_ENTER_CRITICAL_REGION( );
volatile uint8_t * tmpAddr = address;
#ifdef RAMPZ
RAMPZ = 0;
#endif
asm volatile(
" movw r30, %0 " " \n\t "
" ldi r16, %2 " " \n\t "
" out %3, r16 " " \n\t "
" st Z, %1 " " \n\t "
:
: " r " (tmpAddr), " r " (value), " M " (CCP_IOREG_gc), " i " ( & CCP)
: " r16 " , " r30 " , " r31 "
);

AVR_LEAVE_CRITICAL_REGION( );
#endif
}

/*! \brief This function configures the external oscillator.
*
* \note Note that the oscillator cannot be used as a main system clock
* source without being enabled and stable first. Check the ready flag
* before using the clock. The macro CLKSYS_IsReady( _oscSel )
* can be used to check this.
*
* \param freqRange Frequency range for high-frequency crystal, does
* not apply for external clock or 32kHz crystals.
* \param lowPower32kHz True of high-quality watch crystals are used and
* low-power oscillator is desired.
* \param xoscModeSelection Combined selection of oscillator type (or
* external clock) and startup times.
*/
void CLKSYS_XOSC_Config( OSC_FRQRANGE_t freqRange,
bool lowPower32kHz,
OSC_XOSCSEL_t xoscModeSelection )
{
OSC.XOSCCTRL = (uint8_t) freqRange |
( lowPower32kHz ? OSC_X32KLPM_bm : 0 ) |
xoscModeSelection;
}


/*! \brief This function configures the internal high-frequency PLL.
*
* Configuration of the internal high-frequency PLL to the correct
* values. It is used to define the input of the PLL and the factor of
* multiplication of the input clock source.
*
* \note Note that the oscillator cannot be used as a main system clock
* source without being enabled and stable first. Check the ready flag
* before using the clock. The macro CLKSYS_IsReady( _oscSel )
* can be used to check this.
*
* \param clockSource Reference clock source for the PLL,
* must be above 0.4MHz.
* \param factor PLL multiplication factor, must be
* from 1 to 31, inclusive.
*/
void CLKSYS_PLL_Config( OSC_PLLSRC_t clockSource, uint8_t factor )
{
factor & = OSC_PLLFAC_gm;
OSC.PLLCTRL = (uint8_t) clockSource | ( factor & lt; & lt; OSC_PLLFAC_gp );
}


/*! \brief This function disables the selected oscillator.
*
* This function will disable the selected oscillator if possible.
* If it is currently used as a main system clock source, hardware will
* disregard the disable attempt, and this function will return zero.
* If it fails, change to another main system clock source and try again.
*
* \param oscSel Bitmask of selected clock. Can be one of the following
* OSC_RC2MEN_bm, OSC_RC32MEN_bm, OSC_RC32KEN_bm,
* OSC_XOSCEN_bm, OSC_PLLEN_bm.
*
* \return Non-zero if oscillator was disabled successfully.
*/
uint8_t CLKSYS_Disable( uint8_t oscSel )
{
OSC.CTRL & = ~oscSel;
uint8_t clkEnabled = OSC.CTRL & oscSel;
return clkEnabled;
}


/*! \brief This function changes the prescaler configuration.
*
* Change the configuration of the three system clock
* prescaler is one single operation. The user must make sure that
* the main CPU clock does not exceed recommended limits.
*
* \param PSAfactor Prescaler A division factor, OFF or 2 to 512 in
* powers of two.
* \param PSBCfactor Prescaler B and C division factor, in the combination
* of (1,1), (1,2), (4,1) or (2,2).
*/
void CLKSYS_Prescalers_Config( CLK_PSADIV_t PSAfactor,
CLK_PSBCDIV_t PSBCfactor )
{
uint8_t PSconfig = (uint8_t) PSAfactor | PSBCfactor;
CCPWrite( & CLK.PSCTRL, PSconfig );
}


/*! \brief This function selects the main system clock source.
*
* Hardware will disregard any attempts to select a clock source that is not
* enabled or not stable. If the change fails, make sure the source is ready
* and running and try again.
*
* \param clockSource Clock source to use as input for the system clock
* prescaler block.
*
* \return Non-zero if change was successful.
*/
uint8_t CLKSYS_Main_ClockSource_Select( CLK_SCLKSEL_t clockSource )
{
uint8_t clkCtrl = ( CLK.CTRL & ~CLK_SCLKSEL_gm ) | clockSource;
CCPWrite( & CLK.CTRL, clkCtrl );
clkCtrl = ( CLK.CTRL & clockSource );
return clkCtrl;
}


/*! \brief This function selects a Real-Time Counter clock source.
*
* Selects the clock source for use by the Real-Time Counter (RTC)
* and enables clock signal routing to the RTC module.
*
* \param clockSource Clock source to use for the RTC.
*/
void CLKSYS_RTC_ClockSource_Enable( CLK_RTCSRC_t clockSource )
{
CLK.RTCCTRL = ( CLK.RTCCTRL & ~CLK_RTCSRC_gm ) |
clockSource |
CLK_RTCEN_bm;
}


/*! \brief This function enables automatic calibration of the selected internal
* oscillator.
*
* Either the internal 32kHz RC oscillator or an external 32kHz
* crystal can be used as a calibration reference. The user must make sure
* that the selected reference is ready and running.
*
* \param clkSource Clock source to calibrate, either OSC_RC2MCREF_bm or
* OSC_RC32MCREF_bm.
* \param extReference True if external crystal should be used as reference.
*/
void CLKSYS_AutoCalibration_Enable( uint8_t clkSource, bool extReference )
{
OSC.DFLLCTRL = ( OSC.DFLLCTRL & ~clkSource ) |
( extReference ? clkSource : 0 );
if (clkSource == OSC_RC2MCREF_bm) {
DFLLRC2M.CTRL |= DFLL_ENABLE_bm;
} else if (clkSource == OSC_RC32MCREF_bm) {
DFLLRC32M.CTRL |= DFLL_ENABLE_bm;
}
}


/*! \brief This function enables the External Oscillator Failure Detection
* (XOSCFD) feature.
*
* The feature will stay enabled until next reset. Note that the
* XOSCFD _will_ issue the XOSCF Non-maskable Interrupt (NMI) regardless of
* any interrupt priorities and settings. Therefore, make sure that a handler
* is implemented for the XOSCF NMI when you enable it.
*/
void CLKSYS_XOSC_FailureDetection_Enable( void )
{
CCPWrite( & OSC.XOSCFAIL, ( OSC_XOSCFDIF_bm | OSC_XOSCFDEN_bm ) );
}


/*! \brief This function lock the entire clock system configuration.
*
* This will lock the configuration until the next reset, or until the
* External Oscillator Failure Detections (XOSCFD) feature detects a failure
* and switches to internal 2MHz RC oscillator.
*/
void CLKSYS_Configuration_Lock( void )
{
CCPWrite( & CLK.LOCK, CLK_LOCK_bm );
}


xMega_official_drivers_and_examples.rar > readme.html

Code Documentation Redirecting


xMega_official_drivers_and_examples.rar > XMEGA Real Time Counter.pdf

AVR1314: Using the XMEGA Real Time Counter
Features
o 16- bit RTC with programmable period and alarm.
o Clock source options
- Accurate Internal 32 kHz RC oscillator
- Ultra Low Power Internal 32 kHz RC oscillator
- External 32 kHz crystal oscillator.
o Optional division of 32 kHz clock to 1kHz to save power
o RTC clock prescaling factor between 1 and 1024.
- Timer tick between 31us and 1 second

8-bit
Microcontrollers
Application Note

1 Introduction
In many embedded systems a real time counter is used to keep track of time. This
can be to schedule application functions, like the duration of a washing cycle in a
washing machine. It can also be used to wake up the MCU from low power modes
on (ir)regular intervals The ability to use long time out periods reduces the battery
power consumption in applications like e.g. thermostats, wireless applications and
sensor/actuators.
This application note covers the use of the 16-bit Real Time Counter (RTC) in the
XMEGA(TM).

Rev. 8047A-AVR-02/08

2 Real time counter overview
The XMEGA RTC is a 16-bit timer with programmable period time and a single
compare channel.

2.1 Registers
The RTC count, period, and compare value are all 16-bit values. Since the data bus is
only 8-bit wide, two registers are used to represent a 16-bit value. The high byte is
referred to with an "H" suffix and low byte with an "L". Most C-compilers will handle
the 16-bit access automatically when symbolic names of the 16-bit registers are used.
It is also possible to access the high and low word individually. The 16-bit registers for
the RTC are CNT[H:L], PER[H:L], and CMP[H:L].

2.2 Interrupts
The RTC can generate two interrupts, an overflow interrupt, and one compare
interrupt. The overflow interrupt will have a fixed frequency, as long as the period
register (PER) is not changed: it can e.g. interrupt with 1 Hz interval - to update the
clock digit on an LCD. The compare register (COMP) offers a way to set a variable
timeout interrupt, without changing the period or reloading the timer's count registers
(CNT).

2.3 Clock sources
The RTC can be clocked from of three clock sources:
o Internal 32 kHz Ultra-Low Power (ULP) RC oscillator
o Internal 32kHz Calibrated RC oscillator (more accurate than the ULP RC, but
draws more current).
o An external 32.768kHz watch crystal oscillator (highly accurate).
To reduce the power consumption the clock system can divide the 32 kHz clock
sources to 1 kHz before providing it to the RTC module. An RTC clock cycle is
therefore either 1ms or 31us. The RTC clock must be enabled in the clock system
before the RTC can be used. Please refer to the application note AVR1003 and the
datasheet for details on the clock system.
The RTC module has an internal prescaling option. Prescaling factors up to 1024 are
available. The prescaler factor is controlled by the CTRL register.
The maximum timeout period and time resolution for the RTC is determined by the
RTC clock frequency. If a fast clock is used this gives a fine timer resolution, but at
the expense of fairly short timeout periods. If on the other hand the clock frequency is
increased, the timeout period can be quite long, but with lower resolution. A few
examples are given in the table below:

2

AVR1314
8047A-AVR-02/08

AVR1314
Table 2-1. RTC clock frequency, time resolution and timeout period
Scaled RTC clock

Timer tick resolution

Timeout period

32.768 kHz

31 us

2 sec.

1.024 kHz

1 ms

64 sec

1 Hz

1 sec

18 hours 12 min

This means that ultra low power battery applications can spend very long periods in
sleep mode. This reduces power consumption, as frequent wakeups only to update
the real time variables are not needed. The MCU only wakes up when processing is
required.

2.4 Clock domains - synchronized and unsynchronized RTC registers
Since the RTC is operating from a different clock than the CPU, it has another "clock
domain" than the CPU. When the CPU and RTC exchange information across the
clock domain boundary, synchronization between the two clock domains is required.
The synchronization is hardware controlled. When data is transferred from CPU into
RTC domain, the synchronization takes 3 clock cycles in the RTC clock domain. Note
that, when referring clock cycles in the RTC clock domain, it is the unscaled clock
input to the RTC module that it referred to. This is either 32 kHz or 1 kHz.
The synchronization from RTC to CPU domain is 3 CPU cycles. This means that
unless the CPU clock is very slow the duration of the synchronization in this direction
is negligible.
The four synchronized registers are CTRL, CNT, PER and COMP. Note that the PER
register does not have a separate synchronizer; the synchronization of PER is
triggered by synchronization of the CNT, CTRL or COMP registers.
Synchronization from CPU into RTC domain is triggered when writing the high byte of
the COUNT, COMP or PER registers. Writing the low bytes does not trigger
synchronization. When writing new values it is therefore relevant to access the
registers in correct order - write the low byte first and then the high byte. If the PER
register is updated, one of the other registers must also be updated to synchronize
PER value into RTC domain The mechanism is designed in this ways to ensure that
corresponding PER and COMP values can be loaded in the same RTC cycle, while
the RTC clock is running.
To monitor if synchronization is completed the SYNCBUSY flag in the STATUS
register can be inspected. The flag is set while synchronization is ongoing. Note that
once the synchronization of a register is triggered, this register cannot be written
again until the synchronization is completed. This applies to all four synchronized
registers. Writing to one register does not block access to other registers.

2.5 Special concerns for sleep mode
Due to synchronization it is impossible to wake up from sleep mode by RTC interrupts
more frequent than every 4 RTC clock cycles (unscaled clock). If for instance the
compare period is set to 3 RTC timer ticks (and the clock is not prescaled in the RTC
module), the synchronization will cause every second interrupt to be missed. If this
interrupt is used to wake up the part from sleep this would be observed as if the
wake-up from sleep occurs at half the expected frequency. This can be avoided by
selecting an appropriate time base for the RTC with a higher frequency.

3
8047A-AVR-02/08

2.6 Connecting the RTC to the Event System
It is possible for the RTC to generate events on overflow and compare match - for
details about the event system please refer to the datasheet and application note
AVR1001. If combined with the Timer/Counters, this can be used to form a 24 hour
timer: The RTC can generate an event every 60 seconds. The "minute-event" is used
as clock source to a Timer Counter, which in turn generates overflow event to the
event system after 60 minutes. The "hour-overflow" event is used at clock for another
Timer Counter, which keeps tracks of the hours.
Note that the event system is not operating in other sleep modes than Idle mode. Idle
and Extended Power Save are however quite similar in power consumption when
peripherals are not enabled.

2.7 Operation of the RTC in debugging mode
The RTC clock is blocked when breaking code execution in debugging mode. This
ensures that interrupts are not generated continuously when single stepping.
However, the timing of the RTC will be affected when single stepping the code as the
RTC clock source is asynchronous to the CPU clock.

3 Required methods of use
The following subsections describe the recommended procedures for initialization and
configuration of the RTC. All the procedures below assume that clock system is set
up to provide a clock for the RTC module.
3.1.1 Initialization (RTC not already running)
1. Write period value by writing to the PER register.
2. Write compare match and count values (COMP and CNT).
3. Set interrupt level for compare match and overflow interrupt.
4. Set clock prescaler selection in CTRL register.
3.1.2 Re-initialization (RTC running)
1. Stop RTC clock, by clearing prescaler.
2. Wait for BSY flag to clear.
3. Write period value by writing to the PER registers.
4. Write compare match and count values (COMP and CNT).
5. Set interrupt level for compare match and overflow interrupt.
6. Set prescaler setting in CTRL register.
3.1.3 Change RTC period
1. Wait for SYNCBUSY flag to clear.
2. Write period value by writing to the PER registers.
3. Write either CNT or COMP register.
3.1.4 Changing compare match or count value
1. Wait for SYNCBUSY flag to clear.
2. Write either CNT or COMP register.
4

AVR1314
8047A-AVR-02/08

AVR1314
3.1.5 Enter sleep mode
1. Wait for SYNCBUSY flag to clear.
2. Enter sleep mode.

4 Driver Implementation
This application note includes a source code package with a basic driver
implemented in C.
Note that this driver is written to be highly readable and as general example how to
use the peripheral module. If using the driver in an application it may be desirable to
copy relevant parts of the code to where it is needed, to reduce to number of function
calls. This will both speed up the code and reduce the code footprint.

4.1 Files
The source code package consists of three files:
o rtc_driver.c - driver source file
o rtc_driver.h - driver header file
o rtc_example.c - Example code using the driver
For an overview of the available driver interface functions and their use, please refer
to the source code documentation.

4.2 Doxygen documentation
All source code is prepared for automatic documentation generation using Doxygen.
Doxygen is a tool for generating documentation from source code by analyzing the
source code and using special keywords. For more details about Doxygen please visit
http://www.doxygen.org. Precompiled Doxygen documentation is also supplied with
the source code accompanying this application note, available from the readme.html
file in the source code folder.

5
8047A-AVR-02/08

Disclaimer

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8047A-AVR-02/08


xMega_official_drivers_and_examples.rar > XMEGA Self-programming.pdf

AVR1316: XMEGA Self-programming
Features
o
o
o
o
o
o
o
o
o
o

8-bit
Microcontrollers

Software Access to Non-volatile Memories
Read Calibration Byte
Read Fuse Bytes
Read and Write Lock Bits
Erase, Read, and Write User Signature Row
Erase, Read, and Write Application Section
Erase, Read, and Write Boot Section
CRC Generation for Application and Boot Section
Optimized Assembly Implementation
Driver Source Code Included

Application Note

1 Introduction
This application note contains descriptions of the basic functionality of the
XMEGA(TM) Self-programming feature and code examples to get up and running
quickly. A driver interface written in assembly with a C interface is included as well.
Figure 1-1 Self-programming Overview
User Signature

Flash Boot
Section

Flash Application
Section

Lock Bits

NVM
Interface
SPM
Instruction

Z-pointer (R31:R30)
(R1:R0)

Calibration Bytes

Fuses

Rev. 8070B-AVR-11/08

2 Module Overview
This section provides an overview of the functionality and basic configuration options
of the XMEGA Self-programming features.

2.1 The Non-volatile Memory Module
The XMEGA Flash memory, signature and calibration bytes, fuses and lock bits can
all be accessed using the Non-volatile Memory (NVM) module. The NVM module is
also used for access to EEPROM. Please refer to application note "AVR1315:
Accessing the XMEGA EEPROM" or the device datasheet for more details.
As the NVM module serves several purposes, it is important to check that the NVM
module is not busy with other operations (such as EEPROM update) before using it to
access Flash memory etc. The NVM Busy bit (NVMBUSY) in the NVM Status register
(STATUS) is set when the NVM module is busy.
Using the NVM module to perform Self-programming involves using NVM
Commands. There are commands for erasing, writing, reading etc. Several
commands require addresses or indexes to be set before issuing the command.
Some commands also return values.
There are three different command types, depending on memory and access type.
The command types are described in the next three sections. An overview of
commands and their use can be found in Section 2.5 below.
2.1.1 NVM Action-based Commands
NVM Action-based commands are instructions where the Command Execute bit
(CMDEX) in NVM Control Register A (CTRLA) has to be set in order to start an NVM
Action. The Command Execute bit has to be set after the required control registers
are set up. The NVM Action-based commands are used to access fuse bits, lock bits,
EEPROM and to calculate CRC for the Flash memory sections.
The exact procedure is as follows:
1. Load address or index into the Address registers (ADDRn) if required.
2. Load data into the Data registers (DATAn) if required.
3. Load the command code into the Command register (CMD).
4. Load the Protect IO Register signature (byte value 0xD8) into the Configuration
Change Protection register (CCP). This will automatically disable all interrupts for
the next four CPU instruction cycles.
5. Within the next four CPU instruction cycles, set the Command Execute bit (CMDEX)
in NVM Control Register A (CTRLA).
6. The operation is finished when the NVM Busy bit (NVMBUSY) is cleared.
7. Results from the operation will be available in the NVM Data registers (DATAn).
The following operations use NVM Action-based commands:
o
o
o
o
2

Reading fuse bytes
Writing lock bits
Generating CRC for Application Section
Generating CRC for Boot Section

AVR1316
8070B-AVR-11/08

AVR1316
2.1.2 LPM-based Commands
LPM-based commands are commands where the LPM instruction is used. The LPM
instruction is executed after the required control registers are set up. LPM-based
commands are used for reading Flash memories. In XMEGA devices, the application
code, calibration bytes, and signature bytes are located in Flash memory.
The exact procedure is as follows:
1. Load address or index into the Z pointer register (R31 and R30) if required.
2. Load the command code into the Command register (CMD).
3. Execute the LPM instruction.
4. The operation finishes immediately.
5. Results from the operation will be available in registers R0.
The following operations use LPM-based commands:
o Reading calibration bytes
o Reading user-accessible signature bytes
o Read Flash memory
2.1.3 SPM-based Commands
SPM-based commands are commands where the CPU executes the SPM instruction.
The SPM instruction is executed after the required control registers are set up. SPMbased commands are used for erasing and writing Flash memories. In XMEGA
devices, the application code, calibration bytes, and signature bytes are located in
Flash memory.
The exact procedure is as follows:
1. Load address or index into the Z pointer register (R31 and R30) if required.
2. Load data into registers R1 and R0 if required.
3. Load the command code into the Command register (CMD).
4. Load the Protect SPM Register signature (byte value 0x9D) into the Configuration
Change Protection register (CCP). This will automatically disable all interrupts for
the next four CPU instruction cycles.
5. Within the next four CPU instruction cycles, execute the SPM instruction.
6. The operation is finished when the NVM Busy bit (NVMBUSY) is cleared.
The following operations use SPM-based commands:
o
o
o
o
o
o

Erasing user signature row
Writing user signature row
Erasing Flash memory
Loading Flash page buffer
Writing Flash memory
Flushing Flash page buffer

3
8070B-AVR-11/08

2.2 Erasing and Writing Flash memory
There are two ways to update the Flash memory: atomic write and split operation.
With atomic write, Flash locations are erased and written in one operation. With split
operation, erasing and writing are separate operations.
When erasing Flash locations, all bits are set to logic one. A split write can then
program selected bits to logic zero. Split write operations cannot change a bit from
zero to one, as opposed to an atomic write that first erase to logic one and then writes
logic zeros to selected bits. This means that multiple writes to one location with
different values, without erases in between, eventually results in all locations being
logic zeros. This is similar to a logic AND operation between existing value and
written value.
An atomic write takes approximately twice the time of one erase or one write.
Therefore, split operation can be used to save time by erasing Flash locations in
advance, e.g. during initialization. For instance, if the application needs to store vital
data when a power drop is detected, a split write will take less time than an atomic
write.
Another useful application for the split operation is to increase Flash memory
endurance, especially for applications that update Flash locations frequently. By
implementing a scheme where Flash locations are not erased unless they have to,
the split operation feature will increase Flash endurance. This is similar to split and
atomic write for EEPROM. For more details, refer to the application note "AVR101:
High Endurance EEPROM Storage".
Different erase and write operations, together with bit values before and after the
operation, are illustrated in Figure 2-1 below. For simplicity, the figure shows byte
addresses although the Flash sections are word-addressable.
Figure 2-1. Atomic Write, Split Write and Erase Operations
0x57

0

1

0

1

0

1

1

1

Atomic write: 0xD0

0x57

0

1

0

1

0

1

1

1

Split write: 0xF0

0xD0

1

1

0

1

0

0

0

0

0x50

0

1

0

1

0

0

0

0

0x57

0

1

0

1

0

1

1

1

0xFF

1

1

1

1

1

1

1

1

1

0

0

0

0

Erase
0xFF

Split write: 0xF0
1

1

1

1

1

1

1

1

0xF0

1

1

1

2.3 The Temporary Page Buffer
The Flash memory is organized in pages, which in turn are word-addressable. Both
erase and write operations operate on pages. The page size depends on memory
size and is given in the device datasheet. Erase and write operations use a temporary
page buffer to store the individual words until the entire page is ready to be written to
Flash.

4

AVR1316
8070B-AVR-11/08

AVR1316
The Flash page buffer is very similar to the EEPROM page buffer, which is described
in application note "AVR1315: Accessing the XMEGA EEPROM". The difference is
that even if only a few words are loaded in the Flash page buffer, the entire page will
be updated when writing data, or the entire page will be erased when performing a
page erase. For the EEPROM page buffer, only the loaded buffer locations will be
affected when writing or erasing EEPROM pages. Please study the example code for
usage details.
A Flash page write actually consists of two operations: (1) loading the page buffer
with data and (2) writing data to a Flash page. When loading the page buffer, the
lower part of the Flash address is used to select a word in the page buffer, while the
upper part is ignored. When writing or erasing a page, the upper part of the address
selects the page while the lower part is ignored. As the Flash is word-addressable,
the LSB of the address is always ignored.
Once a word has been loaded into the buffer for the first time, the Flash Page Buffer
Active Loading bit (FLOAD) in the NVM Status register (STATUS) will be set. The bit
remains set until either the buffer is flushed or a page write is performed (atomic or
split write).
Note that each word location in the page buffer can only be written once before
flushing the buffer or writing a page.

2.4 Application and Boot Sections
The XMEGA Flash memory is divided into two sections, the Application Section and
the Boot Section. The Application Section stores ordinary application firmware, while
the Boot Section is most often used to store a bootloader application.
The Boot Section can also be used for ordinary application firmware. Since code that
executes SPM-based commands can only run from the Boot Section, the section is
most often used for bootloaders and/or parts of the application firmware that needs to
update Flash memory or run other SPM-based commands.
There are separate lock bits for the Application Section and the Boot Section, so that
read and/or write access to the two sections can be individually limited. Also, the
upper part of the Application Section has its own set of lock bits, independent from
the rest of the section. This upper section is called the Application Table Section,
since it is ideal for storing and maintaining larger tables in Flash memory.
A common scenario for using the Application Table Section is as follows:
o Store application firmware in the Application Section and lock it using
corresponding lock bits.
o Store and maintain larger tables in the Application Table Section, and leave it
unlocks in case it needs updates later.
o Store the parts of the application firmware that maintains the Flash tables (using
SPM-based commands) in the Boot Section and lock it using corresponding lock
bits.
Note that the size of the Application Table Section will always be equal to the size of
the Boot Section.
Figure 2-2 below shows an overview of the different Flash memory sections related to
each other.

5
8070B-AVR-11/08

Figure 2-2. Flash Memory Organization
Boot
Section

Boot
Section

No-Read-While-Write
Section (NRWW)

Application
Table Section

Entire
Flash
Memory

Application
Section

Application
Code Section

Read-While-Write
Section (RWW)

2.4.1 No-Read-While-Write Section
The entire Boot Section is referred to as a No-Read-While-Write Section (NRWW). It
is not possible to read from any location in Flash memory while the NRWW section is
being written to. Reading includes executing code and reading Flash data using LPMbased commands.
SPM-based commands can only be executed from the Boot Section. If a bootloader
application wants to update its own code, instruction execution is halted while the
Boot Section is being written.
2.4.2 Read-While-Write Section
The entire Application Section is referred to as a Read-While-Write Section (RWW).
This does not mean that it is possible to read from this section while it is being written
to. It means that it is possible to read and execute code from the Boot Section while
the Application Section is being updated.
This feature makes it possible to keep critical functions running while updating the
application firmware or Flash tables in the Application Table Section.
2.4.3 SPM Lock
Some applications update the application section after startup, and then leave it
untouched until the next reset or power cycle. As a safety precaution for this usage,
the NVM module can lock all further access to any SPM-based command.
The SPM Lock command requires a variant of the NVM Action-based command. The
exact procedure is as follows:
1. Load the Protect IO Register signature (byte value 0xD8) into the Configuration
Change Protection register (CCP). This will automatically disable all interrupts for
the next four CPU instruction cycles.
2. Within the next four CPU instruction cycles, set the SPM Lock bit (SPMLOCK) in
NVM Control Register B (CTRLB).
The example software contains an implementation of this functionality.
6

AVR1316
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AVR1316
2.4.4 Boot Reset Vector
Applications that use bootloader firmware to update the Application Section needs to
configure the XMEGA to start executing code in the Boot Section after power-up or
reset instead of the Application Section. A dedicated fuse bit is used to configure the
startup address to the first location (RESET interrupt vector) in the Boot Section
instead of the Application Section. Please refer to the device datasheet for fuse
settings and programming information.
2.4.5 Interrupt Vector Table Location
Some applications need to keep selected vital functions running even when the
Application Section is being updated. These functions are often interrupt-controlled
and need to be enabled and executable at all times during the update. When updating
the Application Section, no code can be running from it. The interrupt handler code
needs to be duplicated in the Boot Section and the interrupt vector table must be
relocated.
For details on how to move the interrupt table and information on interrupts in
general, please refer to the application note "AVR1305: XMEGA Interrupts and the
Programmable Multilevel Interrupt Controller".
2.4.6 Reducing Power Consumption
It is possible to configure the NVM module to disable the Flash section that is unused
at any given time (Application Section or Boot Section). This feature minimizes power
consumption in the application since there is no current consumption in the disabled
Flash section. By default, both sections are always enabled, but by setting the Flash
Power Reduction Enable bit (FPRM) in Control Register B (CTRLB), only the section
where code executes is enabled. If the execution flow moves from one section to
another, e.g. a function call, the CPU is halted for 6 clock cycles while one section is
enabled and the other is disabled.
The 6-cycle penalty also applies when an LPM operation accesses a disabled Flash
section.
Note that the Application Table Section is a part of the Application Section and will be
enabled when the Application Section is.

2.5 Command Summary
Table 2-1 below gives an overview of all NVM commands available for selfprogramming operations along with the symbolic name used in the source code. The
byte value of the command, its type, and a short description are also included. Please
study the example source code for more details.
Table 2-1. Relevant NVM Commands
Command

Code

Type

Description

NO_OPERATION

0x00

(LPM)

Read Flash byte from address Z into R0.

READ_USER_SIG_ROW

0x01

LPM

Read user signature byte at index Z into R0.

READ_CALIB_ROW

0x02

LPM

Read calibration byte at index Z into R0.

READ_FUSES

0x07

NVM

Read fuse byte at index ADDR0 into DATA0.

WRITE_LOCK_BITS

0x08

NVM

Write DATA0 to lock bits.

ERASE_USER_SIG_ROW

0x18

SPM

Erase user signature byte at index Z.

7
8070B-AVR-11/08

Command

Code

Type

Description

WRITE_USER_SIG_ROW

0x1A

SPM

Write R0 to user signature byte at index Z.

ERASE_APP

0x20

SPM

Erase entire Application Section.

ERASE_APP_PAGE

0x22

SPM

Erase application page at address Z, using
only the upper address bits.

LOAD_FLASH_BUFFER

0x23

SPM

Load word R1:R0 into page buffer at
address Z, using only the lower address
bits.

WRITE_APP_PAGE

0x24

SPM

Write page buffer to application page at
address Z, using only the upper address
bits.

ERASE_WRITE_APP_PAGE

0x25

SPM

Erase application page at address Z and
write page buffer to application page at
address Z, using only the upper address
bits.

ERASE_FLASH_BUFFER

0x26

SPM

Flush the page buffer.

ERASE_BOOT_PAGE

0x2A

SPM

Erase boot page at address Z, using only
the upper address bits.

WRITE_BOOT_PAGE

0x2C

SPM

Write page buffer to boot page at address
Z, using only the upper address bits.

ERASE_WRITE_BOOT_PAGE

0x2D

SPM

Erase boot page at address Z and write
page buffer to boot page at address Z,
using only the upper address bits.

APP_CRC

0x38

NVM

Generate CRC from Application Section
and store in DATA2:DATA1:DATA0.

BOOT_CRC

0x39

NVM

Generate CRC from Boot Section and store
in DATA2:DATA1:DATA0.

The algorithm details for the CRC generation can be found in the device datasheet.
2.5.1 Special Case: Reading Lock Bits
The lock bits are I/O-mapped into the NVM Lock Bits register (LOCKBITS), and can
be read directly without any NVM commands.

2.6 Interrupt Considerations
When using interrupts and self-programming operations in the same application, the
following should be considered:
o Take care not to corrupt the Flash page buffer contents. When loading the page
buffer, make sure that no interrupt handlers access the page buffer. If an interrupt
handler is used to access the page buffer, make sure that other parts of the
application do not access the buffer at the same time.
o Instead of continuously polling the NVM Busy flag (NVMBUSY) to detect when an
NVM operation is finished, it is possible to enable the SPM Interrupt by setting an
appropriate interrupt level with the SPM Interrupt Level bitfield (SPMLVL) in the
Interrupt Control register (INTCTRL). The corresponding interrupt handler will be
called whenever the NVM Busy flag (NVMBUSY) is not set. This can be used to
implement an interrupt-controlled Flash memory update. More details on interrupts
8

AVR1316
8070B-AVR-11/08

AVR1316
can be found in application note "AVR1305: XMEGA Interrupts and the
Programmable Multi-level Interrupt Controller".

3 Getting Started
This section walks you through the basic steps for getting up and running with the
XMEGA Self-programming. A few common scenarios are described in the sections
below. For further examples and details, please study the example software.

3.1 Full Application Section Update
A common scenario is for a Bootloader to get updated Flash data from serial
communication through a PC application. In the case of a full Application Section
update, the recommended procedure is as follows:
1. Erase entire application section with the SPM command ERASE_APP.
2. Wait for NVM Busy flag to be cleared.
3. Get one page worth of data over the communication channel.
4. Load the page buffer with the data using the SPM command LOAD_PAGE_BUFFER.
5. Use the SPM command WRITE_APP_PAGE to write the new data to the Flash
page.
6. Wait for NVM Busy flag to be cleared.
7. Repeat from step 2 until all pages are updated.

3.2 Update Selected Locations
Another common scenario is to update selected locations on Flash, for instance
constant tables or parameters stored in Flash memory, preferably in the Application
Table Section. The recommended procedure for such read-modify-write operations is
as follows:
1. Read the Flash page that contains the locations to be updated into an SRAM buffer
using plain LPM read operations (NO_OPERATION).
2. Updated selected locations in the SRAM buffer.
3. Load the page buffer with the data from the updated SRAM buffer using the SPM
command LOAD_PAGE_BUFFER.
4. Use the SPM command ERASE_WRITE_APP_PAGE to erase previous contents and
write the new data to the Flash page.
5. Wait for NVM Busy flag to be cleared.

4 Driver Implementation
This application note includes a source code package with a basic Self-programming
driver implemented in assembly with a C interface. Please refer to the driver source
code and device datasheet for more details.

4.1 Files
The source code package consists of three files:
o sp_driver.s/sp_driver.s90 - Self-programming driver source file
o sp_driver.h - Self-programming driver header file
9
8070B-AVR-11/08

o sp_example.c - Example code using the driver
For a complete overview of the available driver interface functions and their use,
please refer to the source code documentation.

4.2 Doxygen Documentation
All source code is prepared for automatic documentation generation using Doxygen.
Doxygen is a tool for generating documentation from source code by analyzing the
source code and using special keywords. For more details about Doxygen please visit
http://www.doxygen.org. Precompiled Doxygen documentation is also supplied with
the source code accompanying this application note, available from the readme.html
file in the source code folder.

10

AVR1316
8070B-AVR-11/08

Disclaimer

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8070B-AVR-11/08


xMega_official_drivers_and_examples.rar > dma_driver.c

/* This file has been prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief XMEGA DMA Controller driver source file.
*
* This file contains the function implementations for the XMEGA DMA driver.
*
* The driver is not intended for size and/or speed critical code, since
* most functions are just a few lines of code, and the function call
* overhead would decrease code performance. The driver is intended for
* rapid prototyping and documentation purposes for getting started with
* the XMEGA DMA module.
*
* For size and/or speed critical code, it is recommended to copy the
* function contents directly into your application instead of making
* a function call.
*
* \par Application note:
* AVR1304: Using the XMEGA DMA Controller
*
* \par Documentation
* For comprehensive code documentation, supported compilers, compiler
* settings and supported devices see readme.html
*
* \author
* Atmel Corporation: http://www.atmel.com \n
* Support email: avr@atmel.com
*
* $Revision: 2593 $
* $Date: 2009-07-17 15:22:29 +0200 (fr, 17 jul 2009) $ \n
*
* Copyright (c) 2008, Atmel Corporation All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of ATMEL may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL " AS IS " AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
* SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*****************************************************************************/

#include " dma_driver.h "


/*! \brief This function forces a software reset of the DMA module.
*
* All registers will be set to their default values. If the DMA
* module is enabled, it must and will be disabled before being reset.
* It will not be enabled afterwards.
*/
void DMA_Reset( void )
{
DMA.CTRL & = ~DMA_ENABLE_bm;
DMA.CTRL |= DMA_RESET_bm;
while (DMA.CTRL & DMA_RESET_bm); // Wait until reset is completed
}


/*! \brief This function configures the double buffering feature of the DMA.
*
* Channel pair 0/1 and/or channel pair 2/3 can
* be configured to operation in a chained mode. This means that
* once the first channel has completed its transfer, the second
* channel takes over automatically. It is important to setup the
* channel pair with equal block sizes, repeat modes etc.
*
* Do not change these settings after a transfer has started.
*
* \param dbufMode Double buffering mode.
*/
void DMA_ConfigDoubleBuffering( DMA_DBUFMODE_t dbufMode )
{
DMA.CTRL = ( DMA.CTRL & ~DMA_DBUFMODE_gm ) | dbufMode;
}


/*! \brief This function selects what priority scheme to use for the DMA channels.
*
* It decides what channels to schedule in a round-robin
* manner, which means that they take turns in acquiring the data bus
* for individual data transfers. Channels not included in the round-robin
* scheme will have fixed priorities, with channel 0 having highest priority.
*
* \note Do not change these settings after a transfer has started.
*
* \param priMode An enum selection the priority scheme to use.
*/
void DMA_SetPriority( DMA_PRIMODE_t priMode )
{
DMA.CTRL = ( DMA.CTRL & ~DMA_PRIMODE_gm ) | priMode;
}


/*! \brief This function checks if the channel has on-going transfers not
* finished yet.
*
* \param channel Channel to check.
*
* \return Non-zero if the selected channel have on-going transfers,
* zero otherwise.
*/
uint8_t DMA_CH_IsOngoing( volatile DMA_CH_t * channel )
{
uint8_t flagMask;
flagMask = channel- & gt; CTRLB & DMA_CH_CHBUSY_bm;
return flagMask;
}

/*! \brief This function checks if any channel have on-going transfers are not
* finished yet.
*
* \return Non-zero if any channel have on-going transfers, zero otherwise.
*/
uint8_t DMA_IsOngoing( void )
{
uint8_t flagMask;
flagMask = DMA.STATUS & 0xF0;
return flagMask;
}

/*! \brief This function check if the channel has transfers pending.
*
* This function checks if the channel selected have transfers that are
* pending, which means that a transfer has been requested by a trigger source
* or by a manual request, but the channel haven't yet started its transfer.
*
* \param channel Channel to check.
*
* \return Non-zero if the selected channel have pending transfers,
* zero otherwise.
*/
uint8_t DMA_CH_IsPending( volatile DMA_CH_t * channel )
{
uint8_t flagMask;
flagMask = channel- & gt; CTRLB & DMA_CH_CHPEND_bm;
return flagMask;
}


/*! \brief This function check if there are any transfers pending.
*
* This function checks if any channel have transfers that are pending,
* which means that a transfer has been requested by a trigger source
* or by a manual request, but the channels haven't yet started its transfer.
*
* \return Non-zero if the selected channel have pending transfers,
* zero otherwise.
*/
uint8_t DMA_IsPending( void )
{
uint8_t flagMask;
flagMask = DMA.STATUS & 0x0F;
return flagMask;
}

/*! \brief This function return the interrupt flag status of a channel.
*
* This function return the status the channels selected finishes an on-going
* transfer or encounters an error and aborts the transfer.
*
* \note Flags covered by the channel will NOT be cleared when this
* function exits.
*
* \param channel The channel to check.
*
* \return Relevant interrupt flags.
*/
uint8_t DMA_ReturnStatus_non_blocking( volatile DMA_CH_t * channel )
{
uint8_t relevantFlags;
relevantFlags = channel- & gt; CTRLB & (DMA_CH_ERRIF_bm | DMA_CH_TRNIF_bm);
return relevantFlags;
}


/*! \brief This function return the interrupt flag status of a channel.
*
* This function return the status of the channel selected either finishes
* an on-going transfer or encounters an error and aborts the transfer.
*
* \note Flags covered by the channel will be cleared when this
* function exits. However, it will return the flag status. This
* is a BLOCKING function, and will go into a dead-lock if the flags
* never get set.
*
* \param channel The channel to check.
*
* \return Relevant interrupt flags.
*/
uint8_t DMA_ReturnStatus_blocking( volatile DMA_CH_t * channel )
{
uint8_t flagMask;
uint8_t relevantFlags;

flagMask = DMA_CH_ERRIF_bm | DMA_CH_TRNIF_bm;

do {
relevantFlags = channel- & gt; CTRLB & flagMask;
} while (relevantFlags == 0x00);

channel- & gt; CTRLB = flagMask;
return relevantFlags;
}

/*! \brief This function enables one DMA channel sub module.
*
* \note A DMA channel will be automatically disabled
* when a transfer is finished.
*
* \param channel The channel to enable.
*/
void DMA_EnableChannel( volatile DMA_CH_t * channel )
{
channel- & gt; CTRLA |= DMA_CH_ENABLE_bm;
}


/*! \brief This function disables one DMA channel sub module.
*
* \note On-going transfers will be aborted and the error flag be set if a
* channel is disabled in the middle of a transfer.
*
* \param channel The channel to disable.
*/
void DMA_DisableChannel( volatile DMA_CH_t * channel )
{
channel- & gt; CTRLA & = ~DMA_CH_ENABLE_bm;
}


/*! \brief This function forces a software reset of the DMA channel sub module.
*
* All registers will be set to their default values. If the channel
* is enabled, it must and will be disabled before being reset.
* It will not be enabled afterwards.
*
* \param channel The channel to reset.
*/
void DMA_ResetChannel( volatile DMA_CH_t * channel )
{
channel- & gt; CTRLA & = ~DMA_CH_ENABLE_bm;
channel- & gt; CTRLA |= DMA_CH_RESET_bm;
channel- & gt; CTRLA & = ~DMA_CH_RESET_bm;
}


/*! \brief This function configures the interrupt levels for one DMA channel.
*
* \note The interrupt level parameter use the data type for channel 0,
* regardless of which channel is used. This is because we use the
* same function for all channel. This method relies upon channel
* bit fields to be located this way: CH3:CH2:CH1:CH0.
*
* \param channel The channel to configure.
* \param transferInt Transfer Complete Interrupt Level.
* \param errorInt Transfer Error Interrupt Level.
*/
void DMA_SetIntLevel( volatile DMA_CH_t * channel,
DMA_CH_TRNINTLVL_t transferInt,
DMA_CH_ERRINTLVL_t errorInt )
{
channel- & gt; CTRLB = (channel- & gt; CTRLB & ~(DMA_CH_ERRINTLVL_gm | DMA_CH_TRNINTLVL_gm)) |
transferInt | errorInt;
}


/*! \brief This function configures the necessary registers for a block transfer.
*
* \note The transfer must be manually triggered or a trigger source
* selected before the transfer starts. It is possible to reload the
* source and/or destination address after each data transfer, block
* transfer or only when the entire transfer is complete.
* Do not change these settings after a transfer has started.
*
* \param channel The channel to configure.
* \param srcAddr Source memory address.
* \param srcReload Source address reload mode.
* \param srcDirection Source address direction (fixed, increment, or decrement).
* \param destAddr Destination memory address.
* \param destReload Destination address reload mode.
* \param destDirection Destination address direction (fixed, increment, or decrement).
* \param blockSize Block size in number of bytes (0 = 64k).
* \param burstMode Number of bytes per data transfer (1, 2, 4, or 8 bytes).
* \param repeatCount Number of blocks, 0x00 if you want to repeat at infinitum.
* \param useRepeat True if reapeat should be used, false if not.
*/
void DMA_SetupBlock( volatile DMA_CH_t * channel,
const void * srcAddr,
DMA_CH_SRCRELOAD_t srcReload,
DMA_CH_SRCDIR_t srcDirection,
void * destAddr,
DMA_CH_DESTRELOAD_t destReload,
DMA_CH_DESTDIR_t destDirection,
uint16_t blockSize,
DMA_CH_BURSTLEN_t burstMode,
uint8_t repeatCount,
bool useRepeat )
{
channel- & gt; SRCADDR0 = (( (uint32_t) srcAddr) & gt; & gt; 0*8 ) & 0xFF;
channel- & gt; SRCADDR1 = (( (uint32_t) srcAddr) & gt; & gt; 1*8 ) & 0xFF;
channel- & gt; SRCADDR2 = (( (uint32_t) srcAddr) & gt; & gt; 2*8 ) & 0xFF;

channel- & gt; DESTADDR0 = (( (uint32_t) destAddr) & gt; & gt; 0*8 ) & 0xFF;
channel- & gt; DESTADDR1 = (( (uint32_t) destAddr) & gt; & gt; 1*8 ) & 0xFF;
channel- & gt; DESTADDR2 = (( (uint32_t) destAddr) & gt; & gt; 2*8 ) & 0xFF;

channel- & gt; ADDRCTRL = (uint8_t) srcReload | srcDirection |
destReload | destDirection;
channel- & gt; TRFCNT = blockSize;
channel- & gt; CTRLA = ( channel- & gt; CTRLA & ~( DMA_CH_BURSTLEN_gm | DMA_CH_REPEAT_bm ) ) |
burstMode | ( useRepeat ? DMA_CH_REPEAT_bm : 0);

if ( useRepeat ) {
channel- & gt; REPCNT = repeatCount;
}
}


/*! \brief This function enables single-shot transfer mode for a channel.
*
* In single-shot mode, one transfer trigger (manual or from a trigger source)
* only causes one single data transfer (1, 2, 4, or 8 byte). When not
* in single-shot mode, one transfer trigger causes one entire block transfer.
* Do not change this setting after a transfer has started.
*
* \param channel The channel to configure.
*/
void DMA_EnableSingleShot( volatile DMA_CH_t * channel )
{
channel- & gt; CTRLA |= DMA_CH_SINGLE_bm;
}


/*! \brief This function disables single-shot transfer mode for a channel.
*
* In single-shot mode, one transfer trigger (manual or from a trigger source)
* only causes one single data transfer (1, 2, 4, or 8 byte). When not
* in single-shot mode, one transfer trigger causes one entire block transfer.
*
* Do not change this setting after a transfer has started.
*
* \param channel The channel to configure.
*/
void DMA_DisableSingleShot( volatile DMA_CH_t * channel )
{
channel- & gt; CTRLA & = ~DMA_CH_SINGLE_bm;
}


/*! \brief This function sets the transfer trigger source for a channel.
*
* \note A manual transfer requests can be used even after setting a trigger
* source. Do not change this setting after a transfer has started.
*
* \param channel The channel to configure.
* \param trigger The trigger source ID.
*/
void DMA_SetTriggerSource( volatile DMA_CH_t * channel, uint8_t trigger )
{
channel- & gt; TRIGSRC = trigger;
}


/*! \brief This function sends a manual transfer request to the channel.
*
* The bit will automatically clear when transfer starts.
*
* \param channel The channel to request a transfer for.
*/
void DMA_StartTransfer( volatile DMA_CH_t * channel )
{
channel- & gt; CTRLA |= DMA_CH_TRFREQ_bm;
}


xMega_official_drivers_and_examples.rar > dma_example.c

/* This file has been prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief XMEGA DMA driver example source.
*
* This file contains an example application that demonstrates the DMA
* driver. It shows how to set up the DMA for a memory-to-memory block
* copy operation. Two functions are provided, one using single block
* transfer and one using repeated block transfer. Single block transfers
* supports up to 64k bytes, while repeated blocks supports up to 255
* blocks (16M - 64k bytes). Both functions are tested in the main()
* function.
*
* \par Application note:
* AVR1304: Using the XMEGA DMA Controller
*
* \par Documentation
* For comprehensive code documentation, supported compilers, compiler
* settings and supported devices see readme.html
*
* \author
* Atmel Corporation: http://www.atmel.com \n
* Support email: avr@atmel.com
*
* $Revision: 1569 $
* $Date: 2008-04-22 13:03:43 +0200 (ti, 22 apr 2008) $ \n
*
* Copyright (c) 2008, Atmel Corporation All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of ATMEL may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL " AS IS " AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
* SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*****************************************************************************/
#include " dma_driver.h "
#include " avr_compiler.h "

/*! Size of one memory block. */
#define MEM_BLOCK_SIZE (10)

/*! Memory block count. */
#define MEM_BLOCK_COUNT (10)

/*! Total block size. Note that MEM_BLOCK_SIZE * MEM_BLOCK_COUNT must not
* exceed 64k for this demo application.
*/
#define MEM_BLOCK ( MEM_BLOCK_SIZE * MEM_BLOCK_COUNT )

/*! Memory blocks A and B for testing. */
uint8_t memoryBlockA[MEM_BLOCK];
uint8_t memoryBlockB[MEM_BLOCK];

/*! Global declared status for interrupt routine. */
volatile bool gInterruptDone;
volatile bool gStatus;

/*! \brief Example demonstrating block memory copy.
*
* Block size 0 = 64k. Enable the DMA channel to use first and it will be
* disabled automatically. Setup channel for copying data, increasing
* addresses, no address pointer reload, with 8-byte bursts.
*
* \note This function DO NOT wait for a completion, and this must be handled
* by the program calling this function. In this example, an interrupt.
*
* \retval true if success.
* \retval false if failure.
*/
bool BlockMemCopy( const void * src,
void * dest,
uint16_t blockSize,
volatile DMA_CH_t * dmaChannel )
{
DMA_EnableChannel( dmaChannel );

DMA_SetupBlock( dmaChannel,
src,
DMA_CH_SRCRELOAD_NONE_gc,
DMA_CH_SRCDIR_INC_gc,
dest,
DMA_CH_DESTRELOAD_NONE_gc,
DMA_CH_DESTDIR_INC_gc,
blockSize,
DMA_CH_BURSTLEN_8BYTE_gc,
0,
false );

DMA_StartTransfer( dmaChannel );

return true;
}



/*! \brief Example of a repeated block memory copy operation.
*
* Block size 0 = 64k. Enable the DMA channel to use first and the channel
* will be disabled automatically. A parameter check to avoid illegal values.
* Setup channel for copying data, increasing addresses, no address pointer
* reload, with 8-byte bursts.
*
* \note This function wait until the transfer is complete and use a blocking
* function which also makes this function blocking, hence the function
* will dead-lock if the completion or error flag never get set.
*
* \retval true if success.
* \retval false if failure.
*/
bool MultiBlockMemCopy( const void * src, void * dest, uint16_t blockSize,
uint8_t repeatCount, volatile DMA_CH_t * dmaChannel )
{
uint8_t flags;

DMA_EnableChannel( dmaChannel );
DMA_SetupBlock( dmaChannel,
src,
DMA_CH_SRCRELOAD_NONE_gc,
DMA_CH_SRCDIR_INC_gc,
dest,
DMA_CH_DESTRELOAD_NONE_gc,
DMA_CH_DESTDIR_INC_gc,
blockSize,
DMA_CH_BURSTLEN_8BYTE_gc,
repeatCount,
true );

DMA_StartTransfer( dmaChannel );

/* Wait until the completion or error flag is set. The flags
* must be cleared manually.
*/
do {
flags = DMA_ReturnStatus_non_blocking( dmaChannel );
} while ( flags == 0);

dmaChannel- & gt; CTRLB |= ( flags );

/* Check if error flag is set. */
if ( ( flags & DMA_CH_ERRIF_bm ) != 0x00 ) {
return false;
} else {
return true;
}
}

/*! \brief Example code using two different methods of transfer.
*
* Example code using the two example functions to do a singe block memory
* copy and a multi block memory copy. The first test use a polling function
* to wait until the transfer completes or get an error. The second test use
* an interrupt to know when the transfer completes or get an error.
*/
void main( void )
{
uint32_t index;

volatile DMA_CH_t * Channel;
Channel = & DMA.CH0;

DMA_Enable();

/* Test 1: Copy using repeated blocks. */

/* Fill memory block A with example data. */
for ( index = 0; index & lt; MEM_BLOCK; ++index ) {
memoryBlockA[index] = ( (uint8_t) index & 0xff );
}

/* Copy data using channel 0. */
gStatus = MultiBlockMemCopy( memoryBlockA,
memoryBlockB,
MEM_BLOCK_SIZE,
MEM_BLOCK_COUNT,
Channel );

/* Compare memory blocks if status is true. */
if ( gStatus ) {
for ( index = 0; index & lt; MEM_BLOCK; ++index) {
if (memoryBlockA[index] != memoryBlockB[index]) {
gStatus = false;
break;
}
}
}


/* Test 2: Copy using single block mode and use interrupt. Perform
* second test only if first test succeeded.
*/
if ( gStatus ) {

/* Enable LO interrupt level for the complete transaction and
* error flag on DMA channel 0.
*/
DMA_SetIntLevel( Channel, DMA_CH_TRNINTLVL_LO_gc, DMA_CH_ERRINTLVL_LO_gc );
PMIC.CTRL |= PMIC_LOLVLEN_bm;
sei();

/* Fill memory block A with example data again. */
for ( index = 0; index & lt; MEM_BLOCK; ++index ) {
memoryBlockA[index] = 0xff - ( (uint8_t) index & 0xff );
}

/* Set intDone to false to know when it has been executed. */
gInterruptDone = false;

/* Copy data using channel 0. */
gStatus = BlockMemCopy( memoryBlockA,
memoryBlockB,
MEM_BLOCK,
Channel);

do {
/* Do something here while waiting for the
* interrupt routine to signal completion.
*/
} while ( gInterruptDone == false );

/* Compare memory blocks. */
if ( gStatus ) {
for ( index = 0; index & lt; MEM_BLOCK; ++index ) {
if (memoryBlockA[index] != memoryBlockB[index]) {
gStatus = false;
break;
}
}
}
}

if ( gStatus ) {
do {
/* Completed with success. */
} while (1);
} else {
do {
/* Completed with failure. */
} while (1);
}
}


/*! DMA CH0 Interrupt service routine. Clear interrupt flags after check. */
ISR(DMA_CH0_vect)
{
if (DMA.CH0.CTRLB & DMA_CH_ERRIF_bm) {
DMA.CH0.CTRLB |= DMA_CH_ERRIF_bm;
gStatus = false;
} else {
DMA.CH0.CTRLB |= DMA_CH_TRNIF_bm;
gStatus = true;
}
gInterruptDone = true;
}


xMega_official_drivers_and_examples.rar > documentation.h

/* Doxygen documentation mainpage ********************************************/
/*! \mainpage
* \section intro Introduction
* This documents the firmware for the application note. \n
*
* \section compinfo Compilation Info
* This firmware was compiled with IAR Embedded Workbench 5.30.0 and WinAVR 20090313.\n
*
* To make the project in IAR EWAVR:\n
* Add the .c files (and .S90 files where applicable) for the given example to your
* project. Use device ATxmega128A1 and enable bit definitions in I/O include files,
* optimization low for debug target and high for release, output format: ubrof8 for
* Debug and intel_extended for Release, select Normal DLIB as library. \n
*
* To make the project in WinAVR:\n
* Add the .c files (and .S files where applicable) for the given example to your project.
* Use device ATxmega128A1, optimization low for debug target and high for release. \n
*
* \section deviceinfo Device Info
* All XMEGA devices with the targeted module can be used. The example is
* written for ATxmega128A1.
*
* \section contactinfo Contact Info
* For more info about Atmel AVR visit http://www.atmel.com/products/AVR/ \n
* For application notes visit
* http://www.atmel.com/dyn/products/app_notes.asp?family_id=607 \n
* Support mail: avr@atmel.com \n
*
* $Revision: 2595 $
* $Date: 2009-07-17 17:03:49 +0200 (fr, 17 jul 2009) $
*
* Copyright (c) 2009, Atmel Corporation All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of ATMEL may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL " AS IS " AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
* SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*****************************************************************************/


xMega_official_drivers_and_examples.rar > avr_compiler.h

/* This file has been prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief This file implements some macros that makes the IAR C-compiler and
* avr-gcc work with the same code base for the AVR architecture.
*
* \par Documentation
* For comprehensive code documentation, supported compilers, compiler
* settings and supported devices see readme.html
*
* \author
* Atmel Corporation: http://www.atmel.com \n
* Support email: avr@atmel.com
*
* $Revision: 613 $
* $Date: 2006-04-07 14:40:07 +0200 (fr, 07 apr 2006) $ \n
*
* Copyright (c) 2008, Atmel Corporation All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of ATMEL may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL " AS IS " AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
* SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/

#ifndef COMPILER_AVR_H
#define COMPILER_AVR_H

#ifndef F_CPU
/*! \brief Define default CPU frequency, if this is not already defined. */
#define F_CPU 2000000UL
#endif

#include & lt; stdint.h & gt;
#include & lt; stdbool.h & gt;
#include & lt; stdlib.h & gt;

/*! \brief This macro will protect the following code from interrupts. */
#define AVR_ENTER_CRITICAL_REGION( ) uint8_t volatile saved_sreg = SREG; \
cli();

/*! \brief This macro must always be used in conjunction with AVR_ENTER_CRITICAL_REGION
* so the interrupts are enabled again.
*/
#define AVR_LEAVE_CRITICAL_REGION( ) SREG = saved_sreg;

#if defined( __ICCAVR__ )

#include & lt; inavr.h & gt;
#include & lt; ioavr.h & gt;
#include & lt; intrinsics.h & gt;
#include & lt; pgmspace.h & gt;

#ifndef __HAS_ELPM__
#define _MEMATTR __flash
#else /* __HAS_ELPM__ */
#define _MEMATTR __farflash
#endif /* __HAS_ELPM__ */

/*! \brief Perform a delay of \c us microseconds.
*
* The macro F_CPU is supposed to be defined to a constant defining the CPU
* clock frequency (in Hertz).
*
* The maximal possible delay is 262.14 ms / F_CPU in MHz.
*
* \note For the IAR compiler, currently F_CPU must be a
* multiple of 1000000UL (1 MHz).
*/
#define delay_us( us ) ( __delay_cycles( ( F_CPU / 1000000UL ) * ( us ) ) )

/*! \brief Preprocessor magic.
*
* Some preprocessor magic to allow for a header file abstraction of
* interrupt service routine declarations for the IAR compiler. This
* requires the use of the C99 _Pragma() directive (rather than the
* old #pragma one that could not be used as a macro replacement), as
* well as two different levels of preprocessor concetanations in
* order to do both, assign the correct interrupt vector name, as well
* as construct a unique function name for the ISR.
*
* \note Do *NOT* try to reorder the macros below, as this will only
* work in the given order.
*/
#define PRAGMA(x) _Pragma( #x )
#define ISR(vec) PRAGMA( vector=vec ) __interrupt void handler_##vec(void)
#define sei( ) (__enable_interrupt( ))
#define cli( ) (__disable_interrupt( ))

/*! \brief Define the no operation macro. */
#define nop( ) (__no_operation())

/*! \brief Define the watchdog reset macro. */
#define watchdog_reset( ) (__watchdog_reset( ))


#define INLINE PRAGMA( inline=forced ) static

#define FLASH_DECLARE(x) _MEMATTR x
#define FLASH_STRING(x) ((_MEMATTR const char *)(x))
#define FLASH_STRING_T char const _MEMATTR *
#define FLASH_BYTE_ARRAY_T uint8_t const _MEMATTR *
#define PGM_READ_BYTE(x) *(x)
#define PGM_READ_WORD(x) *(x)

#define SHORTENUM /**/

#elif defined( __GNUC__ )

#include & lt; avr/io.h & gt;
#include & lt; avr/interrupt.h & gt;
#include & lt; avr/pgmspace.h & gt;
#include & lt; util/delay.h & gt;

/*! \brief Define the delay_us macro for GCC. */
#define delay_us( us ) (_delay_us( us ))

#define INLINE static inline

/*! \brief Define the no operation macro. */
#define nop() do { __asm__ __volatile__ ( " nop " ); } while (0)

#define MAIN_TASK_PROLOGUE int


#define MAIN_TASK_EPILOGUE() return -1;

#define SHORTENUM __attribute__ ((packed))

#else
#error Compiler not supported.
#endif

#endif


xMega_official_drivers_and_examples.rar > dma__driver_8h.html

@DOC_TITLE@







Xmega Application Note








dma_driver.h File Reference XMEGA DMA Controller driver header file.
More...

#include & quot; avr_compiler.h & quot;



Include dependency graph for dma_driver.h:









This graph shows which files directly or indirectly include this file:









Go to the source code of this file.

Defines
#define & nbsp; DMA_Disable () & nbsp; & nbsp; & nbsp;( DMA.CTRL & amp;= ~DMA_ENABLE_bm )

& nbsp; This function disables the DMA module.
#define & nbsp; DMA_Enable () & nbsp; & nbsp; & nbsp;( DMA.CTRL |= DMA_ENABLE_bm )

& nbsp; This function enable the DMA module.
Functions
uint8_t & nbsp; DMA_CH_IsOngoing (volatile DMA_CH_t *channel)

& nbsp; This function checks if the channel has on-going transfers not finished yet.
uint8_t & nbsp; DMA_CH_IsPending (volatile DMA_CH_t *channel)

& nbsp; This function check if the channel has transfers pending.
void & nbsp; DMA_ConfigDoubleBuffering (DMA_DBUFMODE_t dbufMode)

& nbsp; This function configures the double buffering feature of the DMA.
void & nbsp; DMA_DisableChannel (volatile DMA_CH_t *channel)

& nbsp; This function disables one DMA channel sub module.
void & nbsp; DMA_DisableSingleShot (volatile DMA_CH_t *channel)

& nbsp; This function disables single-shot transfer mode for a channel.
void & nbsp; DMA_EnableChannel (volatile DMA_CH_t *channel)

& nbsp; This function enables one DMA channel sub module.
void & nbsp; DMA_EnableSingleShot (volatile DMA_CH_t *channel)

& nbsp; This function enables single-shot transfer mode for a channel.
uint8_t & nbsp; DMA_IsOngoing (void)

& nbsp; This function checks if any channel have on-going transfers are not finished yet.
uint8_t & nbsp; DMA_IsPending (void)

& nbsp; This function check if there are any transfers pending.
void & nbsp; DMA_Reset (void)

& nbsp; This function forces a software reset of the DMA module.
void & nbsp; DMA_ResetChannel (volatile DMA_CH_t *channel)

& nbsp; This function forces a software reset of the DMA channel sub module.
uint8_t & nbsp; DMA_ReturnStatus_blocking (volatile DMA_CH_t *channel)

& nbsp; This function return the interrupt flag status of a channel.
uint8_t & nbsp; DMA_ReturnStatus_non_blocking (volatile DMA_CH_t *channel)

& nbsp; This function return the interrupt flag status of a channel.
void & nbsp; DMA_SetIntLevel (volatile DMA_CH_t *channel, DMA_CH_TRNINTLVL_t transferInt, DMA_CH_ERRINTLVL_t errorInt)

& nbsp; This function configures the interrupt levels for one DMA channel.
void & nbsp; DMA_SetPriority (DMA_PRIMODE_t priMode)

& nbsp; This function selects what priority scheme to use for the DMA channels.
void & nbsp; DMA_SetTriggerSource (volatile DMA_CH_t *channel, uint8_t trigger)

& nbsp; This function sets the transfer trigger source for a channel.
void & nbsp; DMA_SetupBlock (volatile DMA_CH_t *channel, const void *srcAddr, DMA_CH_SRCRELOAD_t srcReload, DMA_CH_SRCDIR_t srcDirection, void *destAddr, DMA_CH_DESTRELOAD_t destReload, DMA_CH_DESTDIR_t destDirection, uint16_t blockSize, DMA_CH_BURSTLEN_t burstMode, uint8_t repeatCount, bool useRepeat)

& nbsp; This function configures the necessary registers for a block transfer.
void & nbsp; DMA_StartTransfer (volatile DMA_CH_t *channel)

& nbsp; This function sends a manual transfer request to the channel.

Detailed Description
XMEGA DMA Controller driver header file.

This file contains the function prototypes and enumerator definitions for various configuration parameters for the XMEGA DMA driver.
The driver is not intended for size and/or speed critical code, since most functions are just a few lines of code, and the function call overhead would decrease code performance. The driver is intended for rapid prototyping and documentation purposes for getting started with the XMEGA DMA module.
For size and/or speed critical code, it is recommended to copy the function contents directly into your application instead of making a function call.
Application note: AVR1304: Using the XMEGA DMA Controller
Documentation For comprehensive code documentation, supported compilers, compiler settings and supported devices see readme.html
Author: Atmel Corporation: http://www.atmel.com
Support email: avr@atmel.com
Revision 2593
Date 2009-07-17 15:22:29 +0200 (fr, 17 jul 2009)


Copyright (c) 2008, Atmel Corporation All rights reserved.
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
3. The name of ATMEL may not be used to endorse or promote products derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY ATMEL " AS IS " AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Definition in file dma_driver.h .
Define Documentation





#define DMA_Disable
(
& nbsp;

& nbsp;) & nbsp;
& nbsp; & nbsp; & nbsp;( DMA.CTRL & amp;= ~DMA_ENABLE_bm )






This function disables the DMA module.

Note: On-going transfers will be aborted.

Definition at line 76 of file dma_driver.h .








#define DMA_Enable
(
& nbsp;

& nbsp;) & nbsp;
& nbsp; & nbsp; & nbsp;( DMA.CTRL |= DMA_ENABLE_bm )






This function enable the DMA module.

Note: Each individual DMA channel must be enabled separately using the DMA_EnableChannel() function.

Definition at line 70 of file dma_driver.h .

Referenced by main() .



Function Documentation





uint8_t DMA_CH_IsOngoing
(
volatile DMA_CH_t * & nbsp;
channel
& nbsp;) & nbsp;







This function checks if the channel has on-going transfers not finished yet.

Parameters:

channel & nbsp; Channel to check.


Returns: Non-zero if the selected channel have on-going transfers, zero otherwise.

Definition at line 119 of file dma_driver.c .
00120 {
00121 uint8_t flagMask;
00122 flagMask = channel- & gt;CTRLB & amp; DMA_CH_CHBUSY_bm;
00123 return flagMask;
00124 }










uint8_t DMA_CH_IsPending
(
volatile DMA_CH_t * & nbsp;
channel
& nbsp;) & nbsp;







This function check if the channel has transfers pending.

This function checks if the channel selected have transfers that are pending, which means that a transfer has been requested by a trigger source or by a manual request, but the channel haven't yet started its transfer.
Parameters:

channel & nbsp; Channel to check.


Returns: Non-zero if the selected channel have pending transfers, zero otherwise.

Definition at line 149 of file dma_driver.c .
00150 {
00151 uint8_t flagMask;
00152 flagMask = channel- & gt;CTRLB & amp; DMA_CH_CHPEND_bm;
00153 return flagMask;
00154 }










void DMA_ConfigDoubleBuffering
(
DMA_DBUFMODE_t & nbsp;
dbufMode
& nbsp;) & nbsp;







This function configures the double buffering feature of the DMA.

Channel pair 0/1 and/or channel pair 2/3 can be configured to operation in a chained mode. This means that once the first channel has completed its transfer, the second channel takes over automatically. It is important to setup the channel pair with equal block sizes, repeat modes etc.
Do not change these settings after a transfer has started.
Parameters:

dbufMode & nbsp; Double buffering mode.



Definition at line 88 of file dma_driver.c .
00089 {
00090 DMA.CTRL = ( DMA.CTRL & amp; ~DMA_DBUFMODE_gm ) | dbufMode;
00091 }










void DMA_DisableChannel
(
volatile DMA_CH_t * & nbsp;
channel
& nbsp;) & nbsp;







This function disables one DMA channel sub module.

Note: On-going transfers will be aborted and the error flag be set if a channel is disabled in the middle of a transfer.
Parameters:

channel & nbsp; The channel to disable.



Definition at line 242 of file dma_driver.c .
00243 {
00244 channel- & gt;CTRLA & amp;= ~DMA_CH_ENABLE_bm;
00245 }










void DMA_DisableSingleShot
(
volatile DMA_CH_t * & nbsp;
channel
& nbsp;) & nbsp;







This function disables single-shot transfer mode for a channel.

In single-shot mode, one transfer trigger (manual or from a trigger source) only causes one single data transfer (1, 2, 4, or 8 byte). When not in single-shot mode, one transfer trigger causes one entire block transfer.
Do not change this setting after a transfer has started.
Parameters:

channel & nbsp; The channel to configure.



Definition at line 361 of file dma_driver.c .
00362 {
00363 channel- & gt;CTRLA & amp;= ~DMA_CH_SINGLE_bm;
00364 }










void DMA_EnableChannel
(
volatile DMA_CH_t * & nbsp;
channel
& nbsp;) & nbsp;







This function enables one DMA channel sub module.

Note: A DMA channel will be automatically disabled when a transfer is finished.
Parameters:

channel & nbsp; The channel to enable.



Definition at line 229 of file dma_driver.c .

Referenced by BlockMemCopy() , and MultiBlockMemCopy() .
00230 {
00231 channel- & gt;CTRLA |= DMA_CH_ENABLE_bm;
00232 }










void DMA_EnableSingleShot
(
volatile DMA_CH_t * & nbsp;
channel
& nbsp;) & nbsp;







This function enables single-shot transfer mode for a channel.

In single-shot mode, one transfer trigger (manual or from a trigger source) only causes one single data transfer (1, 2, 4, or 8 byte). When not in single-shot mode, one transfer trigger causes one entire block transfer. Do not change this setting after a transfer has started.
Parameters:

channel & nbsp; The channel to configure.



Definition at line 345 of file dma_driver.c .
00346 {
00347 channel- & gt;CTRLA |= DMA_CH_SINGLE_bm;
00348 }










uint8_t DMA_IsOngoing
(
void & nbsp;

& nbsp;) & nbsp;







This function checks if any channel have on-going transfers are not finished yet.

Returns: Non-zero if any channel have on-going transfers, zero otherwise.

Definition at line 131 of file dma_driver.c .
00132 {
00133 uint8_t flagMask;
00134 flagMask = DMA.STATUS & amp; 0xF0;
00135 return flagMask;
00136 }










uint8_t DMA_IsPending
(
void & nbsp;

& nbsp;) & nbsp;







This function check if there are any transfers pending.

This function checks if any channel have transfers that are pending, which means that a transfer has been requested by a trigger source or by a manual request, but the channels haven't yet started its transfer.
Returns: Non-zero if the selected channel have pending transfers, zero otherwise.

Definition at line 166 of file dma_driver.c .
00167 {
00168 uint8_t flagMask;
00169 flagMask = DMA.STATUS & amp; 0x0F;
00170 return flagMask;
00171 }










void DMA_Reset
(
void & nbsp;

& nbsp;) & nbsp;







This function forces a software reset of the DMA module.

Prototyping of functions.
All registers will be set to their default values. If the DMA module is enabled, it must and will be disabled before being reset. It will not be enabled afterwards.
Definition at line 68 of file dma_driver.c .
00069 {
00070 DMA.CTRL & amp;= ~DMA_ENABLE_bm;
00071 DMA.CTRL |= DMA_RESET_bm;
00072 while (DMA.CTRL & amp; DMA_RESET_bm); // Wait until reset is completed
00073 }










void DMA_ResetChannel
(
volatile DMA_CH_t * & nbsp;
channel
& nbsp;) & nbsp;







This function forces a software reset of the DMA channel sub module.

All registers will be set to their default values. If the channel is enabled, it must and will be disabled before being reset. It will not be enabled afterwards.
Parameters:

channel & nbsp; The channel to reset.



Definition at line 256 of file dma_driver.c .
00257 {
00258 channel- & gt;CTRLA & amp;= ~DMA_CH_ENABLE_bm;
00259 channel- & gt;CTRLA |= DMA_CH_RESET_bm;
00260 channel- & gt;CTRLA & amp;= ~DMA_CH_RESET_bm;
00261 }










uint8_t DMA_ReturnStatus_blocking
(
volatile DMA_CH_t * & nbsp;
channel
& nbsp;) & nbsp;







This function return the interrupt flag status of a channel.

This function return the status of the channel selected either finishes an on-going transfer or encounters an error and aborts the transfer.
Note: Flags covered by the channel will be cleared when this function exits. However, it will return the flag status. This is a BLOCKING function, and will go into a dead-lock if the flags never get set.
Parameters:

channel & nbsp; The channel to check.


Returns: Relevant interrupt flags.

Definition at line 207 of file dma_driver.c .
00208 {
00209 uint8_t flagMask;
00210 uint8_t relevantFlags;
00211
00212 flagMask = DMA_CH_ERRIF_bm | DMA_CH_TRNIF_bm;
00213
00214 do {
00215 relevantFlags = channel- & gt;CTRLB & amp; flagMask;
00216 } while (relevantFlags == 0x00);
00217
00218 channel- & gt;CTRLB = flagMask;
00219 return relevantFlags;
00220 }










uint8_t DMA_ReturnStatus_non_blocking
(
volatile DMA_CH_t * & nbsp;
channel
& nbsp;) & nbsp;







This function return the interrupt flag status of a channel.

This function return the status the channels selected finishes an on-going transfer or encounters an error and aborts the transfer.
Note: Flags covered by the channel will NOT be cleared when this function exits.
Parameters:

channel & nbsp; The channel to check.


Returns: Relevant interrupt flags.

Definition at line 185 of file dma_driver.c .

Referenced by MultiBlockMemCopy() .
00186 {
00187 uint8_t relevantFlags;
00188 relevantFlags = channel- & gt;CTRLB & amp; (DMA_CH_ERRIF_bm | DMA_CH_TRNIF_bm);
00189 return relevantFlags;
00190 }










void DMA_SetIntLevel
(
volatile DMA_CH_t * & nbsp;
channel ,




DMA_CH_TRNINTLVL_t & nbsp;
transferInt ,




DMA_CH_ERRINTLVL_t & nbsp;
errorInt & nbsp;



)







This function configures the interrupt levels for one DMA channel.

Note: The interrupt level parameter use the data type for channel 0, regardless of which channel is used. This is because we use the same function for all channel. This method relies upon channel bit fields to be located this way: CH3:CH2:CH1:CH0.
Parameters:

channel & nbsp; The channel to configure.
transferInt & nbsp; Transfer Complete Interrupt Level.
errorInt & nbsp; Transfer Error Interrupt Level.



Definition at line 275 of file dma_driver.c .

Referenced by main() .
00278 {
00279 channel- & gt;CTRLB = (channel- & gt;CTRLB & amp; ~(DMA_CH_ERRINTLVL_gm | DMA_CH_TRNINTLVL_gm)) |
00280 transferInt | errorInt;
00281 }










void DMA_SetPriority
(
DMA_PRIMODE_t & nbsp;
priMode
& nbsp;) & nbsp;







This function selects what priority scheme to use for the DMA channels.

It decides what channels to schedule in a round-robin manner, which means that they take turns in acquiring the data bus for individual data transfers. Channels not included in the round-robin scheme will have fixed priorities, with channel 0 having highest priority.
Note: Do not change these settings after a transfer has started.
Parameters:

priMode & nbsp; An enum selection the priority scheme to use.



Definition at line 105 of file dma_driver.c .
00106 {
00107 DMA.CTRL = ( DMA.CTRL & amp; ~DMA_PRIMODE_gm ) | priMode;
00108 }










void DMA_SetTriggerSource
(
volatile DMA_CH_t * & nbsp;
channel ,




uint8_t & nbsp;
trigger & nbsp;



)







This function sets the transfer trigger source for a channel.

Note: A manual transfer requests can be used even after setting a trigger source. Do not change this setting after a transfer has started.
Parameters:

channel & nbsp; The channel to configure.
trigger & nbsp; The trigger source ID.



Definition at line 375 of file dma_driver.c .
00376 {
00377 channel- & gt;TRIGSRC = trigger;
00378 }










void DMA_SetupBlock
(
volatile DMA_CH_t * & nbsp;
channel ,




const void * & nbsp;
srcAddr ,




DMA_CH_SRCRELOAD_t & nbsp;
srcReload ,




DMA_CH_SRCDIR_t & nbsp;
srcDirection ,




void * & nbsp;
destAddr ,




DMA_CH_DESTRELOAD_t & nbsp;
destReload ,




DMA_CH_DESTDIR_t & nbsp;
destDirection ,




uint16_t & nbsp;
blockSize ,




DMA_CH_BURSTLEN_t & nbsp;
burstMode ,




uint8_t & nbsp;
repeatCount ,




bool & nbsp;
useRepeat & nbsp;



)







This function configures the necessary registers for a block transfer.

Note: The transfer must be manually triggered or a trigger source selected before the transfer starts. It is possible to reload the source and/or destination address after each data transfer, block transfer or only when the entire transfer is complete. Do not change these settings after a transfer has started.
Parameters:

channel & nbsp; The channel to configure.
srcAddr & nbsp; Source memory address.
srcReload & nbsp; Source address reload mode.
srcDirection & nbsp; Source address direction (fixed, increment, or decrement).
destAddr & nbsp; Destination memory address.
destReload & nbsp; Destination address reload mode.
destDirection & nbsp; Destination address direction (fixed, increment, or decrement).
blockSize & nbsp; Block size in number of bytes (0 = 64k).
burstMode & nbsp; Number of bytes per data transfer (1, 2, 4, or 8 bytes).
repeatCount & nbsp; Number of blocks, 0x00 if you want to repeat at infinitum.
useRepeat & nbsp; True if reapeat should be used, false if not.



Definition at line 304 of file dma_driver.c .

Referenced by BlockMemCopy() , and MultiBlockMemCopy() .
00315 {
00316 channel- & gt;SRCADDR0 = (( (uint32_t) srcAddr) & gt; & gt; 0*8 ) & amp; 0xFF;
00317 channel- & gt;SRCADDR1 = (( (uint32_t) srcAddr) & gt; & gt; 1*8 ) & amp; 0xFF;
00318 channel- & gt;SRCADDR2 = (( (uint32_t) srcAddr) & gt; & gt; 2*8 ) & amp; 0xFF;
00319
00320 channel- & gt;DESTADDR0 = (( (uint32_t) destAddr) & gt; & gt; 0*8 ) & amp; 0xFF;
00321 channel- & gt;DESTADDR1 = (( (uint32_t) destAddr) & gt; & gt; 1*8 ) & amp; 0xFF;
00322 channel- & gt;DESTADDR2 = (( (uint32_t) destAddr) & gt; & gt; 2*8 ) & amp; 0xFF;
00323
00324 channel- & gt;ADDRCTRL = (uint8_t) srcReload | srcDirection |
00325 destReload | destDirection;
00326 channel- & gt;TRFCNT = blockSize;
00327 channel- & gt;CTRLA = ( channel- & gt;CTRLA & amp; ~( DMA_CH_BURSTLEN_gm | DMA_CH_REPEAT_bm ) ) |
00328 burstMode | ( useRepeat ? DMA_CH_REPEAT_bm : 0);
00329
00330 if ( useRepeat ) {
00331 channel- & gt;REPCNT = repeatCount;
00332 }
00333 }










void DMA_StartTransfer
(
volatile DMA_CH_t * & nbsp;
channel
& nbsp;) & nbsp;







This function sends a manual transfer request to the channel.

The bit will automatically clear when transfer starts.
Parameters:

channel & nbsp; The channel to request a transfer for.



Definition at line 387 of file dma_driver.c .

Referenced by BlockMemCopy() , and MultiBlockMemCopy() .
00388 {
00389 channel- & gt;CTRLA |= DMA_CH_TRFREQ_bm;
00390 }









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@DOC_TITLE@







Xmega Application Note







dma_example.c Go to the documentation of this file. 00001 /* This file has been prepared for Doxygen automatic documentation generation.*/
00054 #include " dma_driver.h "
00055 #include " avr_compiler.h "
00056
00058 #define MEM_BLOCK_SIZE (10)
00059
00061 #define MEM_BLOCK_COUNT (10)
00062
00066 #define MEM_BLOCK ( MEM_BLOCK_SIZE * MEM_BLOCK_COUNT )
00067
00069 uint8_t memoryBlockA [ MEM_BLOCK ];
00070 uint8_t memoryBlockB [ MEM_BLOCK ];
00071
00073 volatile bool gInterruptDone ;
00074 volatile bool gStatus ;
00075
00088 bool BlockMemCopy ( const void * src,
00089 void * dest,
00090 uint16_t blockSize,
00091 volatile DMA_CH_t * dmaChannel )
00092 {
00093 DMA_EnableChannel ( dmaChannel );
00094
00095 DMA_SetupBlock ( dmaChannel,
00096 src,
00097 DMA_CH_SRCRELOAD_NONE_gc,
00098 DMA_CH_SRCDIR_INC_gc,
00099 dest,
00100 DMA_CH_DESTRELOAD_NONE_gc,
00101 DMA_CH_DESTDIR_INC_gc,
00102 blockSize,
00103 DMA_CH_BURSTLEN_8BYTE_gc,
00104 0,
00105 false );
00106
00107 DMA_StartTransfer ( dmaChannel );
00108
00109 return true ;
00110 }
00111
00112
00113
00128 bool MultiBlockMemCopy ( const void * src, void * dest, uint16_t blockSize,
00129 uint8_t repeatCount, volatile DMA_CH_t * dmaChannel )
00130 {
00131 uint8_t flags;
00132
00133 DMA_EnableChannel ( dmaChannel );
00134 DMA_SetupBlock ( dmaChannel,
00135 src,
00136 DMA_CH_SRCRELOAD_NONE_gc,
00137 DMA_CH_SRCDIR_INC_gc,
00138 dest,
00139 DMA_CH_DESTRELOAD_NONE_gc,
00140 DMA_CH_DESTDIR_INC_gc,
00141 blockSize,
00142 DMA_CH_BURSTLEN_8BYTE_gc,
00143 repeatCount,
00144 true );
00145
00146 DMA_StartTransfer ( dmaChannel );
00147
00148 /* Wait until the completion or error flag is set. The flags
00149 * must be cleared manually.
00150 */
00151 do {
00152 flags = DMA_ReturnStatus_non_blocking ( dmaChannel );
00153 } while ( flags == 0);
00154
00155 dmaChannel- & gt;CTRLB |= ( flags );
00156
00157 /* Check if error flag is set. */
00158 if ( ( flags & amp; DMA_CH_ERRIF_bm ) != 0x00 ) {
00159 return false ;
00160 } else {
00161 return true ;
00162 }
00163 }
00164
00172 void main ( void )
00173 {
00174 uint32_t index;
00175
00176 volatile DMA_CH_t * Channel;
00177 Channel = & amp;DMA.CH0;
00178
00179 DMA_Enable ();
00180
00181 /* Test 1: Copy using repeated blocks. */
00182
00183 /* Fill memory block A with example data. */
00184 for ( index = 0; index & lt; MEM_BLOCK ; ++index ) {
00185 memoryBlockA [index] = ( (uint8_t) index & amp; 0xff );
00186 }
00187
00188 /* Copy data using channel 0. */
00189 gStatus = MultiBlockMemCopy ( memoryBlockA ,
00190 memoryBlockB ,
00191 MEM_BLOCK_SIZE ,
00192 MEM_BLOCK_COUNT ,
00193 Channel );
00194
00195 /* Compare memory blocks if status is true. */
00196 if ( gStatus ) {
00197 for ( index = 0; index & lt; MEM_BLOCK; ++index) {
00198 if ( memoryBlockA [index] != memoryBlockB [index]) {
00199 gStatus = false ;
00200 break ;
00201 }
00202 }
00203 }
00204
00205
00206 /* Test 2: Copy using single block mode and use interrupt. Perform
00207 * second test only if first test succeeded.
00208 */
00209 if ( gStatus ) {
00210
00211 /* Enable LO interrupt level for the complete transaction and
00212 * error flag on DMA channel 0.
00213 */
00214 DMA_SetIntLevel ( Channel, DMA_CH_TRNINTLVL_LO_gc, DMA_CH_ERRINTLVL_LO_gc );
00215 PMIC.CTRL |= PMIC_LOLVLEN_bm;
00216 sei();
00217
00218 /* Fill memory block A with example data again. */
00219 for ( index = 0; index & lt; MEM_BLOCK; ++index ) {
00220 memoryBlockA [index] = 0xff - ( (uint8_t) index & amp; 0xff );
00221 }
00222
00223 /* Set intDone to false to know when it has been executed. */
00224 gInterruptDone = false ;
00225
00226 /* Copy data using channel 0. */
00227 gStatus = BlockMemCopy ( memoryBlockA ,
00228 memoryBlockB ,
00229 MEM_BLOCK,
00230 Channel);
00231
00232 do {
00233 /* Do something here while waiting for the
00234 * interrupt routine to signal completion.
00235 */
00236 } while ( gInterruptDone == false );
00237
00238 /* Compare memory blocks. */
00239 if ( gStatus ) {
00240 for ( index = 0; index & lt; MEM_BLOCK; ++index ) {
00241 if ( memoryBlockA [index] != memoryBlockB [index]) {
00242 gStatus = false ;
00243 break ;
00244 }
00245 }
00246 }
00247 }
00248
00249 if ( gStatus ) {
00250 do {
00251 /* Completed with success. */
00252 } while (1);
00253 } else {
00254 do {
00255 /* Completed with failure. */
00256 } while (1);
00257 }
00258 }
00259
00260
00262 ISR (DMA_CH0_vect)
00263 {
00264 if (DMA.CH0.CTRLB & amp; DMA_CH_ERRIF_bm) {
00265 DMA.CH0.CTRLB |= DMA_CH_ERRIF_bm;
00266 gStatus = false ;
00267 } else {
00268 DMA.CH0.CTRLB |= DMA_CH_TRNIF_bm;
00269 gStatus = true ;
00270 }
00271 gInterruptDone = true ;
00272 }




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documentation.h Go to the documentation of this file. 00001 /* Doxygen documentation mainpage ********************************************/




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xMega_official_drivers_and_examples.rar > dma__driver_8c.html

@DOC_TITLE@







Xmega Application Note








dma_driver.c File Reference XMEGA DMA Controller driver source file.
More...

#include & quot; dma_driver.h & quot;



Include dependency graph for dma_driver.c:









Go to the source code of this file.

Functions
uint8_t & nbsp; DMA_CH_IsOngoing (volatile DMA_CH_t *channel)

& nbsp; This function checks if the channel has on-going transfers not finished yet.
uint8_t & nbsp; DMA_CH_IsPending (volatile DMA_CH_t *channel)

& nbsp; This function check if the channel has transfers pending.
void & nbsp; DMA_ConfigDoubleBuffering (DMA_DBUFMODE_t dbufMode)

& nbsp; This function configures the double buffering feature of the DMA.
void & nbsp; DMA_DisableChannel (volatile DMA_CH_t *channel)

& nbsp; This function disables one DMA channel sub module.
void & nbsp; DMA_DisableSingleShot (volatile DMA_CH_t *channel)

& nbsp; This function disables single-shot transfer mode for a channel.
void & nbsp; DMA_EnableChannel (volatile DMA_CH_t *channel)

& nbsp; This function enables one DMA channel sub module.
void & nbsp; DMA_EnableSingleShot (volatile DMA_CH_t *channel)

& nbsp; This function enables single-shot transfer mode for a channel.
uint8_t & nbsp; DMA_IsOngoing (void)

& nbsp; This function checks if any channel have on-going transfers are not finished yet.
uint8_t & nbsp; DMA_IsPending (void)

& nbsp; This function check if there are any transfers pending.
void & nbsp; DMA_Reset (void)

& nbsp; This function forces a software reset of the DMA module.
void & nbsp; DMA_ResetChannel (volatile DMA_CH_t *channel)

& nbsp; This function forces a software reset of the DMA channel sub module.
uint8_t & nbsp; DMA_ReturnStatus_blocking (volatile DMA_CH_t *channel)

& nbsp; This function return the interrupt flag status of a channel.
uint8_t & nbsp; DMA_ReturnStatus_non_blocking (volatile DMA_CH_t *channel)

& nbsp; This function return the interrupt flag status of a channel.
void & nbsp; DMA_SetIntLevel (volatile DMA_CH_t *channel, DMA_CH_TRNINTLVL_t transferInt, DMA_CH_ERRINTLVL_t errorInt)

& nbsp; This function configures the interrupt levels for one DMA channel.
void & nbsp; DMA_SetPriority (DMA_PRIMODE_t priMode)

& nbsp; This function selects what priority scheme to use for the DMA channels.
void & nbsp; DMA_SetTriggerSource (volatile DMA_CH_t *channel, uint8_t trigger)

& nbsp; This function sets the transfer trigger source for a channel.
void & nbsp; DMA_SetupBlock (volatile DMA_CH_t *channel, const void *srcAddr, DMA_CH_SRCRELOAD_t srcReload, DMA_CH_SRCDIR_t srcDirection, void *destAddr, DMA_CH_DESTRELOAD_t destReload, DMA_CH_DESTDIR_t destDirection, uint16_t blockSize, DMA_CH_BURSTLEN_t burstMode, uint8_t repeatCount, bool useRepeat)

& nbsp; This function configures the necessary registers for a block transfer.
void & nbsp; DMA_StartTransfer (volatile DMA_CH_t *channel)

& nbsp; This function sends a manual transfer request to the channel.

Detailed Description
XMEGA DMA Controller driver source file.

This file contains the function implementations for the XMEGA DMA driver.
The driver is not intended for size and/or speed critical code, since most functions are just a few lines of code, and the function call overhead would decrease code performance. The driver is intended for rapid prototyping and documentation purposes for getting started with the XMEGA DMA module.
For size and/or speed critical code, it is recommended to copy the function contents directly into your application instead of making a function call.
Application note: AVR1304: Using the XMEGA DMA Controller
Documentation For comprehensive code documentation, supported compilers, compiler settings and supported devices see readme.html
Author: Atmel Corporation: http://www.atmel.com
Support email: avr@atmel.com
Revision 2593
Date 2009-07-17 15:22:29 +0200 (fr, 17 jul 2009)


Copyright (c) 2008, Atmel Corporation All rights reserved.
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
3. The name of ATMEL may not be used to endorse or promote products derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY ATMEL " AS IS " AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Definition in file dma_driver.c .
Function Documentation





uint8_t DMA_CH_IsOngoing
(
volatile DMA_CH_t * & nbsp;
channel
& nbsp;) & nbsp;







This function checks if the channel has on-going transfers not finished yet.

Parameters:

channel & nbsp; Channel to check.


Returns: Non-zero if the selected channel have on-going transfers, zero otherwise.

Definition at line 119 of file dma_driver.c .
00120 {
00121 uint8_t flagMask;
00122 flagMask = channel- & gt;CTRLB & amp; DMA_CH_CHBUSY_bm;
00123 return flagMask;
00124 }










uint8_t DMA_CH_IsPending
(
volatile DMA_CH_t * & nbsp;
channel
& nbsp;) & nbsp;







This function check if the channel has transfers pending.

This function checks if the channel selected have transfers that are pending, which means that a transfer has been requested by a trigger source or by a manual request, but the channel haven't yet started its transfer.
Parameters:

channel & nbsp; Channel to check.


Returns: Non-zero if the selected channel have pending transfers, zero otherwise.

Definition at line 149 of file dma_driver.c .
00150 {
00151 uint8_t flagMask;
00152 flagMask = channel- & gt;CTRLB & amp; DMA_CH_CHPEND_bm;
00153 return flagMask;
00154 }










void DMA_ConfigDoubleBuffering
(
DMA_DBUFMODE_t & nbsp;
dbufMode
& nbsp;) & nbsp;







This function configures the double buffering feature of the DMA.

Channel pair 0/1 and/or channel pair 2/3 can be configured to operation in a chained mode. This means that once the first channel has completed its transfer, the second channel takes over automatically. It is important to setup the channel pair with equal block sizes, repeat modes etc.
Do not change these settings after a transfer has started.
Parameters:

dbufMode & nbsp; Double buffering mode.



Definition at line 88 of file dma_driver.c .
00089 {
00090 DMA.CTRL = ( DMA.CTRL & amp; ~DMA_DBUFMODE_gm ) | dbufMode;
00091 }










void DMA_DisableChannel
(
volatile DMA_CH_t * & nbsp;
channel
& nbsp;) & nbsp;







This function disables one DMA channel sub module.

Note: On-going transfers will be aborted and the error flag be set if a channel is disabled in the middle of a transfer.
Parameters:

channel & nbsp; The channel to disable.



Definition at line 242 of file dma_driver.c .
00243 {
00244 channel- & gt;CTRLA & amp;= ~DMA_CH_ENABLE_bm;
00245 }










void DMA_DisableSingleShot
(
volatile DMA_CH_t * & nbsp;
channel
& nbsp;) & nbsp;







This function disables single-shot transfer mode for a channel.

In single-shot mode, one transfer trigger (manual or from a trigger source) only causes one single data transfer (1, 2, 4, or 8 byte). When not in single-shot mode, one transfer trigger causes one entire block transfer.
Do not change this setting after a transfer has started.
Parameters:

channel & nbsp; The channel to configure.



Definition at line 361 of file dma_driver.c .
00362 {
00363 channel- & gt;CTRLA & amp;= ~DMA_CH_SINGLE_bm;
00364 }










void DMA_EnableChannel
(
volatile DMA_CH_t * & nbsp;
channel
& nbsp;) & nbsp;







This function enables one DMA channel sub module.

Note: A DMA channel will be automatically disabled when a transfer is finished.
Parameters:

channel & nbsp; The channel to enable.



Definition at line 229 of file dma_driver.c .

Referenced by BlockMemCopy() , and MultiBlockMemCopy() .
00230 {
00231 channel- & gt;CTRLA |= DMA_CH_ENABLE_bm;
00232 }










void DMA_EnableSingleShot
(
volatile DMA_CH_t * & nbsp;
channel
& nbsp;) & nbsp;







This function enables single-shot transfer mode for a channel.

In single-shot mode, one transfer trigger (manual or from a trigger source) only causes one single data transfer (1, 2, 4, or 8 byte). When not in single-shot mode, one transfer trigger causes one entire block transfer. Do not change this setting after a transfer has started.
Parameters:

channel & nbsp; The channel to configure.



Definition at line 345 of file dma_driver.c .
00346 {
00347 channel- & gt;CTRLA |= DMA_CH_SINGLE_bm;
00348 }










uint8_t DMA_IsOngoing
(
void & nbsp;

& nbsp;) & nbsp;







This function checks if any channel have on-going transfers are not finished yet.

Returns: Non-zero if any channel have on-going transfers, zero otherwise.

Definition at line 131 of file dma_driver.c .
00132 {
00133 uint8_t flagMask;
00134 flagMask = DMA.STATUS & amp; 0xF0;
00135 return flagMask;
00136 }










uint8_t DMA_IsPending
(
void & nbsp;

& nbsp;) & nbsp;







This function check if there are any transfers pending.

This function checks if any channel have transfers that are pending, which means that a transfer has been requested by a trigger source or by a manual request, but the channels haven't yet started its transfer.
Returns: Non-zero if the selected channel have pending transfers, zero otherwise.

Definition at line 166 of file dma_driver.c .
00167 {
00168 uint8_t flagMask;
00169 flagMask = DMA.STATUS & amp; 0x0F;
00170 return flagMask;
00171 }










void DMA_Reset
(
void & nbsp;

& nbsp;) & nbsp;







This function forces a software reset of the DMA module.

All registers will be set to their default values. If the DMA module is enabled, it must and will be disabled before being reset. It will not be enabled afterwards.
Definition at line 68 of file dma_driver.c .
00069 {
00070 DMA.CTRL & amp;= ~DMA_ENABLE_bm;
00071 DMA.CTRL |= DMA_RESET_bm;
00072 while (DMA.CTRL & amp; DMA_RESET_bm); // Wait until reset is completed
00073 }










void DMA_ResetChannel
(
volatile DMA_CH_t * & nbsp;
channel
& nbsp;) & nbsp;







This function forces a software reset of the DMA channel sub module.

All registers will be set to their default values. If the channel is enabled, it must and will be disabled before being reset. It will not be enabled afterwards.
Parameters:

channel & nbsp; The channel to reset.



Definition at line 256 of file dma_driver.c .
00257 {
00258 channel- & gt;CTRLA & amp;= ~DMA_CH_ENABLE_bm;
00259 channel- & gt;CTRLA |= DMA_CH_RESET_bm;
00260 channel- & gt;CTRLA & amp;= ~DMA_CH_RESET_bm;
00261 }










uint8_t DMA_ReturnStatus_blocking
(
volatile DMA_CH_t * & nbsp;
channel
& nbsp;) & nbsp;







This function return the interrupt flag status of a channel.

This function return the status of the channel selected either finishes an on-going transfer or encounters an error and aborts the transfer.
Note: Flags covered by the channel will be cleared when this function exits. However, it will return the flag status. This is a BLOCKING function, and will go into a dead-lock if the flags never get set.
Parameters:

channel & nbsp; The channel to check.


Returns: Relevant interrupt flags.

Definition at line 207 of file dma_driver.c .
00208 {
00209 uint8_t flagMask;
00210 uint8_t relevantFlags;
00211
00212 flagMask = DMA_CH_ERRIF_bm | DMA_CH_TRNIF_bm;
00213
00214 do {
00215 relevantFlags = channel- & gt;CTRLB & amp; flagMask;
00216 } while (relevantFlags == 0x00);
00217
00218 channel- & gt;CTRLB = flagMask;
00219 return relevantFlags;
00220 }










uint8_t DMA_ReturnStatus_non_blocking
(
volatile DMA_CH_t * & nbsp;
channel
& nbsp;) & nbsp;







This function return the interrupt flag status of a channel.

This function return the status the channels selected finishes an on-going transfer or encounters an error and aborts the transfer.
Note: Flags covered by the channel will NOT be cleared when this function exits.
Parameters:

channel & nbsp; The channel to check.


Returns: Relevant interrupt flags.

Definition at line 185 of file dma_driver.c .

Referenced by MultiBlockMemCopy() .
00186 {
00187 uint8_t relevantFlags;
00188 relevantFlags = channel- & gt;CTRLB & amp; (DMA_CH_ERRIF_bm | DMA_CH_TRNIF_bm);
00189 return relevantFlags;
00190 }










void DMA_SetIntLevel
(
volatile DMA_CH_t * & nbsp;
channel ,




DMA_CH_TRNINTLVL_t & nbsp;
transferInt ,




DMA_CH_ERRINTLVL_t & nbsp;
errorInt & nbsp;



)







This function configures the interrupt levels for one DMA channel.

Note: The interrupt level parameter use the data type for channel 0, regardless of which channel is used. This is because we use the same function for all channel. This method relies upon channel bit fields to be located this way: CH3:CH2:CH1:CH0.
Parameters:

channel & nbsp; The channel to configure.
transferInt & nbsp; Transfer Complete Interrupt Level.
errorInt & nbsp; Transfer Error Interrupt Level.



Definition at line 275 of file dma_driver.c .

Referenced by main() .
00278 {
00279 channel- & gt;CTRLB = (channel- & gt;CTRLB & amp; ~(DMA_CH_ERRINTLVL_gm | DMA_CH_TRNINTLVL_gm)) |
00280 transferInt | errorInt;
00281 }










void DMA_SetPriority
(
DMA_PRIMODE_t & nbsp;
priMode
& nbsp;) & nbsp;







This function selects what priority scheme to use for the DMA channels.

It decides what channels to schedule in a round-robin manner, which means that they take turns in acquiring the data bus for individual data transfers. Channels not included in the round-robin scheme will have fixed priorities, with channel 0 having highest priority.
Note: Do not change these settings after a transfer has started.
Parameters:

priMode & nbsp; An enum selection the priority scheme to use.



Definition at line 105 of file dma_driver.c .
00106 {
00107 DMA.CTRL = ( DMA.CTRL & amp; ~DMA_PRIMODE_gm ) | priMode;
00108 }










void DMA_SetTriggerSource
(
volatile DMA_CH_t * & nbsp;
channel ,




uint8_t & nbsp;
trigger & nbsp;



)







This function sets the transfer trigger source for a channel.

Note: A manual transfer requests can be used even after setting a trigger source. Do not change this setting after a transfer has started.
Parameters:

channel & nbsp; The channel to configure.
trigger & nbsp; The trigger source ID.



Definition at line 375 of file dma_driver.c .
00376 {
00377 channel- & gt;TRIGSRC = trigger;
00378 }










void DMA_SetupBlock
(
volatile DMA_CH_t * & nbsp;
channel ,




const void * & nbsp;
srcAddr ,




DMA_CH_SRCRELOAD_t & nbsp;
srcReload ,




DMA_CH_SRCDIR_t & nbsp;
srcDirection ,




void * & nbsp;
destAddr ,




DMA_CH_DESTRELOAD_t & nbsp;
destReload ,




DMA_CH_DESTDIR_t & nbsp;
destDirection ,




uint16_t & nbsp;
blockSize ,




DMA_CH_BURSTLEN_t & nbsp;
burstMode ,




uint8_t & nbsp;
repeatCount ,




bool & nbsp;
useRepeat & nbsp;



)







This function configures the necessary registers for a block transfer.

Note: The transfer must be manually triggered or a trigger source selected before the transfer starts. It is possible to reload the source and/or destination address after each data transfer, block transfer or only when the entire transfer is complete. Do not change these settings after a transfer has started.
Parameters:

channel & nbsp; The channel to configure.
srcAddr & nbsp; Source memory address.
srcReload & nbsp; Source address reload mode.
srcDirection & nbsp; Source address direction (fixed, increment, or decrement).
destAddr & nbsp; Destination memory address.
destReload & nbsp; Destination address reload mode.
destDirection & nbsp; Destination address direction (fixed, increment, or decrement).
blockSize & nbsp; Block size in number of bytes (0 = 64k).
burstMode & nbsp; Number of bytes per data transfer (1, 2, 4, or 8 bytes).
repeatCount & nbsp; Number of blocks, 0x00 if you want to repeat at infinitum.
useRepeat & nbsp; True if reapeat should be used, false if not.



Definition at line 304 of file dma_driver.c .

Referenced by BlockMemCopy() , and MultiBlockMemCopy() .
00315 {
00316 channel- & gt;SRCADDR0 = (( (uint32_t) srcAddr) & gt; & gt; 0*8 ) & amp; 0xFF;
00317 channel- & gt;SRCADDR1 = (( (uint32_t) srcAddr) & gt; & gt; 1*8 ) & amp; 0xFF;
00318 channel- & gt;SRCADDR2 = (( (uint32_t) srcAddr) & gt; & gt; 2*8 ) & amp; 0xFF;
00319
00320 channel- & gt;DESTADDR0 = (( (uint32_t) destAddr) & gt; & gt; 0*8 ) & amp; 0xFF;
00321 channel- & gt;DESTADDR1 = (( (uint32_t) destAddr) & gt; & gt; 1*8 ) & amp; 0xFF;
00322 channel- & gt;DESTADDR2 = (( (uint32_t) destAddr) & gt; & gt; 2*8 ) & amp; 0xFF;
00323
00324 channel- & gt;ADDRCTRL = (uint8_t) srcReload | srcDirection |
00325 destReload | destDirection;
00326 channel- & gt;TRFCNT = blockSize;
00327 channel- & gt;CTRLA = ( channel- & gt;CTRLA & amp; ~( DMA_CH_BURSTLEN_gm | DMA_CH_REPEAT_bm ) ) |
00328 burstMode | ( useRepeat ? DMA_CH_REPEAT_bm : 0);
00329
00330 if ( useRepeat ) {
00331 channel- & gt;REPCNT = repeatCount;
00332 }
00333 }










void DMA_StartTransfer
(
volatile DMA_CH_t * & nbsp;
channel
& nbsp;) & nbsp;







This function sends a manual transfer request to the channel.

The bit will automatically clear when transfer starts.
Parameters:

channel & nbsp; The channel to request a transfer for.



Definition at line 387 of file dma_driver.c .

Referenced by BlockMemCopy() , and MultiBlockMemCopy() .
00388 {
00389 channel- & gt;CTRLA |= DMA_CH_TRFREQ_bm;
00390 }









@DOC_TITLE@












Generated on Fri Jul 17 17:12:43 2009 for AVR1304 Using the XMEGA DMA Controller by 1.5.9


xMega_official_drivers_and_examples.rar > globals_func.html

@DOC_TITLE@







Xmega Application Note









All
Functions
Variables
Defines




b
d
i
m



& nbsp;

- b -
BlockMemCopy()
: dma_example.c

- d -
DMA_CH_IsOngoing()
: dma_driver.c
, dma_driver.h
DMA_CH_IsPending()
: dma_driver.h
, dma_driver.c
DMA_ConfigDoubleBuffering()
: dma_driver.c
, dma_driver.h
DMA_DisableChannel()
: dma_driver.h
, dma_driver.c
DMA_DisableSingleShot()
: dma_driver.c
, dma_driver.h
DMA_EnableChannel()
: dma_driver.c
, dma_driver.h
DMA_EnableSingleShot()
: dma_driver.c
, dma_driver.h
DMA_IsOngoing()
: dma_driver.h
, dma_driver.c
DMA_IsPending()
: dma_driver.c
, dma_driver.h
DMA_Reset()
: dma_driver.c
, dma_driver.h
DMA_ResetChannel()
: dma_driver.c
, dma_driver.h
DMA_ReturnStatus_blocking()
: dma_driver.c
, dma_driver.h
DMA_ReturnStatus_non_blocking()
: dma_driver.c
, dma_driver.h
DMA_SetIntLevel()
: dma_driver.c
, dma_driver.h
DMA_SetPriority()
: dma_driver.h
, dma_driver.c
DMA_SetTriggerSource()
: dma_driver.h
, dma_driver.c
DMA_SetupBlock()
: dma_driver.c
, dma_driver.h
DMA_StartTransfer()
: dma_driver.h
, dma_driver.c

- i -
ISR()
: dma_example.c

- m -
main()
: dma_example.c
MultiBlockMemCopy()
: dma_example.c





@DOC_TITLE@












Generated on Fri Jul 17 17:12:43 2009 for AVR1304 Using the XMEGA DMA Controller by 1.5.9


xMega_official_drivers_and_examples.rar > dma__driver_8h_source.html

@DOC_TITLE@







Xmega Application Note







dma_driver.h Go to the documentation of this file. 00001 /* This file has been prepared for Doxygen automatic documentation generation.*/
00059 #ifndef DMA_DRIVER_H
00060 #define DMA_DRIVER_H
00061
00062 #include " avr_compiler.h "
00063
00064
00070 #define DMA_Enable() ( DMA.CTRL |= DMA_ENABLE_bm )
00071
00076 #define DMA_Disable() ( DMA.CTRL & amp;= ~DMA_ENABLE_bm )
00077
00078
00079
00081 void DMA_Reset ( void );
00082 void DMA_ConfigDoubleBuffering ( DMA_DBUFMODE_t dbufMode );
00083 void DMA_SetPriority ( DMA_PRIMODE_t priMode );
00084 uint8_t DMA_CH_IsOngoing ( volatile DMA_CH_t * channel );
00085 uint8_t DMA_IsOngoing ( void );
00086 uint8_t DMA_CH_IsPending ( volatile DMA_CH_t * channel );
00087 uint8_t DMA_IsPending ( void );
00088 uint8_t DMA_ReturnStatus_non_blocking ( volatile DMA_CH_t * channel );
00089 uint8_t DMA_ReturnStatus_blocking ( volatile DMA_CH_t * channel );
00090 void DMA_EnableChannel ( volatile DMA_CH_t * channel );
00091 void DMA_DisableChannel ( volatile DMA_CH_t * channel );
00092 void DMA_ResetChannel ( volatile DMA_CH_t * channel );
00093 void DMA_SetIntLevel ( volatile DMA_CH_t * channel,
00094 DMA_CH_TRNINTLVL_t transferInt,
00095 DMA_CH_ERRINTLVL_t errorInt );
00096 void DMA_SetupBlock ( volatile DMA_CH_t * channel,
00097 const void * srcAddr,
00098 DMA_CH_SRCRELOAD_t srcReload,
00099 DMA_CH_SRCDIR_t srcDirection,
00100 void * destAddr,
00101 DMA_CH_DESTRELOAD_t destReload,
00102 DMA_CH_DESTDIR_t destDirection,
00103 uint16_t blockSize,
00104 DMA_CH_BURSTLEN_t burstMode,
00105 uint8_t repeatCount,
00106 bool useRepeat );
00107 void DMA_EnableSingleShot ( volatile DMA_CH_t * channel );
00108 void DMA_DisableSingleShot ( volatile DMA_CH_t * channel );
00109 void DMA_SetTriggerSource ( volatile DMA_CH_t * channel, uint8_t trigger );
00110 void DMA_StartTransfer ( volatile DMA_CH_t * channel );
00111
00112 #endif




@DOC_TITLE@












Generated on Fri Jul 17 17:12:43 2009 for AVR1304 Using the XMEGA DMA Controller by 1.5.9


xMega_official_drivers_and_examples.rar > avr__compiler_8h.html

@DOC_TITLE@







Xmega Application Note








avr_compiler.h File Reference This file implements some macros that makes the IAR C-compiler and avr-gcc work with the same code base for the AVR architecture.
More...

#include & lt;stdint.h & gt;
#include & lt;stdbool.h & gt;
#include & lt;stdlib.h & gt;



Include dependency graph for avr_compiler.h:






This graph shows which files directly or indirectly include this file:










Go to the source code of this file.

Defines
#define & nbsp; AVR_ENTER_CRITICAL_REGION ()

& nbsp; This macro will protect the following code from interrupts.
#define & nbsp; AVR_LEAVE_CRITICAL_REGION () & nbsp; & nbsp; & nbsp;SREG = saved_sreg;

& nbsp; This macro must always be used in conjunction with AVR_ENTER_CRITICAL_REGION so the interrupts are enabled again.
#define & nbsp; F_CPU & nbsp; & nbsp; & nbsp;2000000UL

& nbsp; Define default CPU frequency, if this is not already defined.

Detailed Description
This file implements some macros that makes the IAR C-compiler and avr-gcc work with the same code base for the AVR architecture.

Documentation For comprehensive code documentation, supported compilers, compiler settings and supported devices see readme.html
Author: Atmel Corporation: http://www.atmel.com
Support email: avr@atmel.com
Revision 613
Date 2006-04-07 14:40:07 +0200 (fr, 07 apr 2006)


Copyright (c) 2008, Atmel Corporation All rights reserved.
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
3. The name of ATMEL may not be used to endorse or promote products derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY ATMEL " AS IS " AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Definition in file avr_compiler.h .
Define Documentation





#define AVR_ENTER_CRITICAL_REGION
(
& nbsp;

& nbsp;) & nbsp;







Value: uint8_t volatile saved_sreg = SREG; \
cli();
This macro will protect the following code from interrupts.


Definition at line 58 of file avr_compiler.h .








#define AVR_LEAVE_CRITICAL_REGION
(
& nbsp;

& nbsp;) & nbsp;
& nbsp; & nbsp; & nbsp;SREG = saved_sreg;






This macro must always be used in conjunction with AVR_ENTER_CRITICAL_REGION so the interrupts are enabled again.


Definition at line 64 of file avr_compiler.h .








#define F_CPU & nbsp; & nbsp; & nbsp;2000000UL






Define default CPU frequency, if this is not already defined.


Definition at line 50 of file avr_compiler.h .







@DOC_TITLE@












Generated on Fri Jul 17 17:12:43 2009 for AVR1304 Using the XMEGA DMA Controller by 1.5.9


xMega_official_drivers_and_examples.rar > main.html

@DOC_TITLE@







Xmega Application Note








AVR1304 Using the XMEGA DMA Controller Documentation

Atmel AVR Application Notes
Introduction
This documents the firmware for the application note.

Compilation Info
This firmware was compiled with IAR Embedded Workbench 5.30.0 and WinAVR 20090313.

To make the project in IAR EWAVR:
Add the .c files (and .S90 files where applicable) for the given example to your project. Use device ATxmega128A1 and enable bit definitions in I/O include files, optimization low for debug target and high for release, output format: ubrof8 for Debug and intel_extended for Release, select Normal DLIB as library.

To make the project in WinAVR:
Add the .c files (and .S files where applicable) for the given example to your project. Use device ATxmega128A1, optimization low for debug target and high for release.

Device Info
All XMEGA devices with the targeted module can be used. The example is written for ATxmega128A1.
Contact Info
For more info about Atmel AVR visit http://www.atmel.com/products/AVR/
For application notes visit http://www.atmel.com/dyn/products/app_notes.asp?family_id=607
Support mail: avr@atmel.com

Revision 2595
Date 2009-07-17 17:03:49 +0200 (fr, 17 jul 2009)

Copyright (c) 2009, Atmel Corporation All rights reserved.
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
3. The name of ATMEL may not be used to endorse or promote products derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY ATMEL " AS IS " AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.



@DOC_TITLE@












Generated on Fri Jul 17 17:12:43 2009 for AVR1304 Using the XMEGA DMA Controller by 1.5.9


xMega_official_drivers_and_examples.rar > files.html

@DOC_TITLE@







Xmega Application Note








File List Here is a list of all files with brief descriptions:
avr_compiler.h [code] This file implements some macros that makes the IAR C-compiler and avr-gcc work with the same code base for the AVR architecture
dma_driver.c [code] XMEGA DMA Controller driver source file
dma_driver.h [code] XMEGA DMA Controller driver header file
dma_example.c [code] XMEGA DMA driver example source
documentation.h [code]





@DOC_TITLE@












Generated on Fri Jul 17 17:12:43 2009 for AVR1304 Using the XMEGA DMA Controller by 1.5.9


xMega_official_drivers_and_examples.rar > dma__example_8c.html

@DOC_TITLE@







Xmega Application Note








dma_example.c File Reference XMEGA DMA driver example source.
More...

#include & quot; dma_driver.h & quot;
#include & quot; avr_compiler.h & quot;



Include dependency graph for dma_example.c:









Go to the source code of this file.

Defines
#define & nbsp; MEM_BLOCK & nbsp; & nbsp; & nbsp;( MEM_BLOCK_SIZE * MEM_BLOCK_COUNT )

#define & nbsp; MEM_BLOCK_COUNT & nbsp; & nbsp; & nbsp;(10)

#define & nbsp; MEM_BLOCK_SIZE & nbsp; & nbsp; & nbsp;(10)

Functions
bool & nbsp; BlockMemCopy (const void *src, void *dest, uint16_t blockSize, volatile DMA_CH_t *dmaChannel)

& nbsp; Example demonstrating block memory copy.
& nbsp; ISR (DMA_CH0_vect)

void & nbsp; main (void)

& nbsp; Example code using two different methods of transfer.
bool & nbsp; MultiBlockMemCopy (const void *src, void *dest, uint16_t blockSize, uint8_t repeatCount, volatile DMA_CH_t *dmaChannel)

& nbsp; Example of a repeated block memory copy operation.
Variables
volatile bool & nbsp; gInterruptDone

volatile bool & nbsp; gStatus

uint8_t & nbsp; memoryBlockA [MEM_BLOCK]

uint8_t & nbsp; memoryBlockB [MEM_BLOCK]


Detailed Description
XMEGA DMA driver example source.

This file contains an example application that demonstrates the DMA driver. It shows how to set up the DMA for a memory-to-memory block copy operation. Two functions are provided, one using single block transfer and one using repeated block transfer. Single block transfers supports up to 64k bytes, while repeated blocks supports up to 255 blocks (16M - 64k bytes). Both functions are tested in the main() function.
Application note: AVR1304: Using the XMEGA DMA Controller
Documentation For comprehensive code documentation, supported compilers, compiler settings and supported devices see readme.html
Author: Atmel Corporation: http://www.atmel.com
Support email: avr@atmel.com
Revision 1569
Date 2008-04-22 13:03:43 +0200 (ti, 22 apr 2008)


Copyright (c) 2008, Atmel Corporation All rights reserved.
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
3. The name of ATMEL may not be used to endorse or promote products derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY ATMEL " AS IS " AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Definition in file dma_example.c .
Define Documentation





#define MEM_BLOCK & nbsp; & nbsp; & nbsp;( MEM_BLOCK_SIZE * MEM_BLOCK_COUNT )






Total block size. Note that MEM_BLOCK_SIZE * MEM_BLOCK_COUNT must not exceed 64k for this demo application.
Definition at line 66 of file dma_example.c .

Referenced by main() .








#define MEM_BLOCK_COUNT & nbsp; & nbsp; & nbsp;(10)






Memory block count.
Definition at line 61 of file dma_example.c .

Referenced by main() .








#define MEM_BLOCK_SIZE & nbsp; & nbsp; & nbsp;(10)






Size of one memory block.
Definition at line 58 of file dma_example.c .

Referenced by main() .



Function Documentation





bool BlockMemCopy
(
const void * & nbsp;
src ,




void * & nbsp;
dest ,




uint16_t & nbsp;
blockSize ,




volatile DMA_CH_t * & nbsp;
dmaChannel & nbsp;



)







Example demonstrating block memory copy.

Block size 0 = 64k. Enable the DMA channel to use first and it will be disabled automatically. Setup channel for copying data, increasing addresses, no address pointer reload, with 8-byte bursts.
Note: This function DO NOT wait for a completion, and this must be handled by the program calling this function. In this example, an interrupt.
Return values:

true & nbsp; if success.
false & nbsp; if failure.



Definition at line 88 of file dma_example.c .

References DMA_EnableChannel() , DMA_SetupBlock() , and DMA_StartTransfer() .

Referenced by main() .
00092 {
00093 DMA_EnableChannel ( dmaChannel );
00094
00095 DMA_SetupBlock ( dmaChannel,
00096 src,
00097 DMA_CH_SRCRELOAD_NONE_gc,
00098 DMA_CH_SRCDIR_INC_gc,
00099 dest,
00100 DMA_CH_DESTRELOAD_NONE_gc,
00101 DMA_CH_DESTDIR_INC_gc,
00102 blockSize,
00103 DMA_CH_BURSTLEN_8BYTE_gc,
00104 0,
00105 false );
00106
00107 DMA_StartTransfer ( dmaChannel );
00108
00109 return true ;
00110 }





Here is the call graph for this function:
















ISR
(
DMA_CH0_vect & nbsp;

& nbsp;) & nbsp;







DMA CH0 Interrupt service routine. Clear interrupt flags after check.
Definition at line 262 of file dma_example.c .

References gInterruptDone , and gStatus .
00263 {
00264 if (DMA.CH0.CTRLB & amp; DMA_CH_ERRIF_bm) {
00265 DMA.CH0.CTRLB |= DMA_CH_ERRIF_bm;
00266 gStatus = false ;
00267 } else {
00268 DMA.CH0.CTRLB |= DMA_CH_TRNIF_bm;
00269 gStatus = true ;
00270 }
00271 gInterruptDone = true ;
00272 }










void main
(
void & nbsp;

& nbsp;) & nbsp;







Example code using two different methods of transfer.

Example code using the two example functions to do a singe block memory copy and a multi block memory copy. The first test use a polling function to wait until the transfer completes or get an error. The second test use an interrupt to know when the transfer completes or get an error.
Definition at line 172 of file dma_example.c .

References BlockMemCopy() , DMA_Enable , DMA_SetIntLevel() , gInterruptDone , gStatus , MEM_BLOCK , MEM_BLOCK_COUNT , MEM_BLOCK_SIZE , memoryBlockA , memoryBlockB , and MultiBlockMemCopy() .
00173 {
00174 uint32_t index;
00175
00176 volatile DMA_CH_t * Channel;
00177 Channel = & amp;DMA.CH0;
00178
00179 DMA_Enable ();
00180
00181 /* Test 1: Copy using repeated blocks. */
00182
00183 /* Fill memory block A with example data. */
00184 for ( index = 0; index & lt; MEM_BLOCK ; ++index ) {
00185 memoryBlockA [index] = ( (uint8_t) index & amp; 0xff );
00186 }
00187
00188 /* Copy data using channel 0. */
00189 gStatus = MultiBlockMemCopy ( memoryBlockA ,
00190 memoryBlockB ,
00191 MEM_BLOCK_SIZE ,
00192 MEM_BLOCK_COUNT ,
00193 Channel );
00194
00195 /* Compare memory blocks if status is true. */
00196 if ( gStatus ) {
00197 for ( index = 0; index & lt; MEM_BLOCK; ++index) {
00198 if ( memoryBlockA [index] != memoryBlockB [index]) {
00199 gStatus = false ;
00200 break ;
00201 }
00202 }
00203 }
00204
00205
00206 /* Test 2: Copy using single block mode and use interrupt. Perform
00207 * second test only if first test succeeded.
00208 */
00209 if ( gStatus ) {
00210
00211 /* Enable LO interrupt level for the complete transaction and
00212 * error flag on DMA channel 0.
00213 */
00214 DMA_SetIntLevel ( Channel, DMA_CH_TRNINTLVL_LO_gc, DMA_CH_ERRINTLVL_LO_gc );
00215 PMIC.CTRL |= PMIC_LOLVLEN_bm;
00216 sei();
00217
00218 /* Fill memory block A with example data again. */
00219 for ( index = 0; index & lt; MEM_BLOCK; ++index ) {
00220 memoryBlockA [index] = 0xff - ( (uint8_t) index & amp; 0xff );
00221 }
00222
00223 /* Set intDone to false to know when it has been executed. */
00224 gInterruptDone = false ;
00225
00226 /* Copy data using channel 0. */
00227 gStatus = BlockMemCopy ( memoryBlockA ,
00228 memoryBlockB ,
00229 MEM_BLOCK,
00230 Channel);
00231
00232 do {
00233 /* Do something here while waiting for the
00234 * interrupt routine to signal completion.
00235 */
00236 } while ( gInterruptDone == false );
00237
00238 /* Compare memory blocks. */
00239 if ( gStatus ) {
00240 for ( index = 0; index & lt; MEM_BLOCK; ++index ) {
00241 if ( memoryBlockA [index] != memoryBlockB [index]) {
00242 gStatus = false ;
00243 break ;
00244 }
00245 }
00246 }
00247 }
00248
00249 if ( gStatus ) {
00250 do {
00251 /* Completed with success. */
00252 } while (1);
00253 } else {
00254 do {
00255 /* Completed with failure. */
00256 } while (1);
00257 }
00258 }





Here is the call graph for this function:




















bool MultiBlockMemCopy
(
const void * & nbsp;
src ,




void * & nbsp;
dest ,




uint16_t & nbsp;
blockSize ,




uint8_t & nbsp;
repeatCount ,




volatile DMA_CH_t * & nbsp;
dmaChannel & nbsp;



)







Example of a repeated block memory copy operation.

Block size 0 = 64k. Enable the DMA channel to use first and the channel will be disabled automatically. A parameter check to avoid illegal values. Setup channel for copying data, increasing addresses, no address pointer reload, with 8-byte bursts.
Note: This function wait until the transfer is complete and use a blocking function which also makes this function blocking, hence the function will dead-lock if the completion or error flag never get set.
Return values:

true & nbsp; if success.
false & nbsp; if failure.



Definition at line 128 of file dma_example.c .

References DMA_EnableChannel() , DMA_ReturnStatus_non_blocking() , DMA_SetupBlock() , and DMA_StartTransfer() .

Referenced by main() .
00130 {
00131 uint8_t flags;
00132
00133 DMA_EnableChannel ( dmaChannel );
00134 DMA_SetupBlock ( dmaChannel,
00135 src,
00136 DMA_CH_SRCRELOAD_NONE_gc,
00137 DMA_CH_SRCDIR_INC_gc,
00138 dest,
00139 DMA_CH_DESTRELOAD_NONE_gc,
00140 DMA_CH_DESTDIR_INC_gc,
00141 blockSize,
00142 DMA_CH_BURSTLEN_8BYTE_gc,
00143 repeatCount,
00144 true );
00145
00146 DMA_StartTransfer ( dmaChannel );
00147
00148 /* Wait until the completion or error flag is set. The flags
00149 * must be cleared manually.
00150 */
00151 do {
00152 flags = DMA_ReturnStatus_non_blocking ( dmaChannel );
00153 } while ( flags == 0);
00154
00155 dmaChannel- & gt;CTRLB |= ( flags );
00156
00157 /* Check if error flag is set. */
00158 if ( ( flags & amp; DMA_CH_ERRIF_bm ) != 0x00 ) {
00159 return false ;
00160 } else {
00161 return true ;
00162 }
00163 }





Here is the call graph for this function:












Variable Documentation





volatile bool gInterruptDone






Global declared status for interrupt routine.
Definition at line 73 of file dma_example.c .

Referenced by ISR() , and main() .








volatile bool gStatus







Definition at line 74 of file dma_example.c .

Referenced by ISR() , and main() .








uint8_t memoryBlockA [MEM_BLOCK]






Memory blocks A and B for testing.
Definition at line 69 of file dma_example.c .

Referenced by main() .








uint8_t memoryBlockB [MEM_BLOCK]







Definition at line 70 of file dma_example.c .

Referenced by main() .







@DOC_TITLE@












Generated on Fri Jul 17 17:12:43 2009 for AVR1304 Using the XMEGA DMA Controller by 1.5.9


xMega_official_drivers_and_examples.rar > globals.html

@DOC_TITLE@







Xmega Application Note









All
Functions
Variables
Defines




a
b
d
f
g
i
m



Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- a -
AVR_ENTER_CRITICAL_REGION
: avr_compiler.h
AVR_LEAVE_CRITICAL_REGION
: avr_compiler.h

- b -
BlockMemCopy()
: dma_example.c

- d -
DMA_CH_IsOngoing()
: dma_driver.c
, dma_driver.h
DMA_CH_IsPending()
: dma_driver.h
, dma_driver.c
DMA_ConfigDoubleBuffering()
: dma_driver.c
, dma_driver.h
DMA_Disable
: dma_driver.h
DMA_DisableChannel()
: dma_driver.c
, dma_driver.h
DMA_DisableSingleShot()
: dma_driver.c
, dma_driver.h
DMA_Enable
: dma_driver.h
DMA_EnableChannel()
: dma_driver.c
, dma_driver.h
DMA_EnableSingleShot()
: dma_driver.h
, dma_driver.c
DMA_IsOngoing()
: dma_driver.c
, dma_driver.h
DMA_IsPending()
: dma_driver.c
, dma_driver.h
DMA_Reset()
: dma_driver.c
, dma_driver.h
DMA_ResetChannel()
: dma_driver.c
, dma_driver.h
DMA_ReturnStatus_blocking()
: dma_driver.c
, dma_driver.h
DMA_ReturnStatus_non_blocking()
: dma_driver.c
, dma_driver.h
DMA_SetIntLevel()
: dma_driver.c
, dma_driver.h
DMA_SetPriority()
: dma_driver.h
, dma_driver.c
DMA_SetTriggerSource()
: dma_driver.h
, dma_driver.c
DMA_SetupBlock()
: dma_driver.c
, dma_driver.h
DMA_StartTransfer()
: dma_driver.h
, dma_driver.c

- f -
F_CPU
: avr_compiler.h

- g -
gInterruptDone
: dma_example.c
gStatus
: dma_example.c

- i -
ISR()
: dma_example.c

- m -
main()
: dma_example.c
MEM_BLOCK
: dma_example.c
MEM_BLOCK_COUNT
: dma_example.c
MEM_BLOCK_SIZE
: dma_example.c
memoryBlockA
: dma_example.c
memoryBlockB
: dma_example.c
MultiBlockMemCopy()
: dma_example.c





@DOC_TITLE@












Generated on Fri Jul 17 17:12:43 2009 for AVR1304 Using the XMEGA DMA Controller by 1.5.9


xMega_official_drivers_and_examples.rar > avr__compiler_8h_source.html

@DOC_TITLE@







Xmega Application Note







avr_compiler.h Go to the documentation of this file. 00001 /* This file has been prepared for Doxygen automatic documentation generation.*/
00045 #ifndef COMPILER_AVR_H
00046 #define COMPILER_AVR_H
00047
00048 #ifndef F_CPU
00049
00050 #define F_CPU 2000000UL
00051 #endif
00052
00053 #include & lt;stdint.h & gt;
00054 #include & lt;stdbool.h & gt;
00055 #include & lt;stdlib.h & gt;
00056
00058 #define AVR_ENTER_CRITICAL_REGION( ) uint8_t volatile saved_sreg = SREG; \
00059 cli();
00060
00064 #define AVR_LEAVE_CRITICAL_REGION( ) SREG = saved_sreg;
00065
00066 #if defined( __ICCAVR__ )
00067
00068 #include & lt;inavr.h & gt;
00069 #include & lt;ioavr.h & gt;
00070 #include & lt;intrinsics.h & gt;
00071 #include & lt;pgmspace.h & gt;
00072
00073 #ifndef __HAS_ELPM__
00074 #define _MEMATTR __flash
00075 #else /* __HAS_ELPM__ */
00076 #define _MEMATTR __farflash
00077 #endif /* __HAS_ELPM__ */
00078
00089 #define delay_us( us ) ( __delay_cycles( ( F_CPU / 1000000UL ) * ( us ) ) )
00090
00104 #define PRAGMA(x) _Pragma( #x )
00105 #define ISR(vec) PRAGMA( vector=vec ) __interrupt void handler_##vec(void)
00106 #define sei( ) (__enable_interrupt( ))
00107 #define cli( ) (__disable_interrupt( ))
00108
00110 #define nop( ) (__no_operation())
00111
00113 #define watchdog_reset( ) (__watchdog_reset( ))
00114
00115
00116 #define INLINE PRAGMA( inline=forced ) static
00117
00118 #define FLASH_DECLARE(x) _MEMATTR x
00119 #define FLASH_STRING(x) ((_MEMATTR const char *)(x))
00120 #define FLASH_STRING_T char const _MEMATTR *
00121 #define FLASH_BYTE_ARRAY_T uint8_t const _MEMATTR *
00122 #define PGM_READ_BYTE(x) *(x)
00123 #define PGM_READ_WORD(x) *(x)
00124
00125 #define SHORTENUM
00126
00127 #elif defined( __GNUC__ )
00128
00129 #include & lt;avr/io.h & gt;
00130 #include & lt;avr/interrupt.h & gt;
00131 #include & lt;avr/pgmspace.h & gt;
00132 #include & lt;util/delay.h & gt;
00133
00135 #define delay_us( us ) (_delay_us( us ))
00136
00137 #define INLINE static inline
00138
00140 #define nop() do { __asm__ __volatile__ ( " nop " ); } while (0)
00141
00142 #define MAIN_TASK_PROLOGUE int
00143
00144
00145 #define MAIN_TASK_EPILOGUE() return -1;
00146
00147 #define SHORTENUM __attribute__ ((packed))
00148
00149 #else
00150 #error Compiler not supported.
00151 #endif
00152
00153 #endif
00154




@DOC_TITLE@












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xMega_official_drivers_and_examples.rar > atmel-header.html

@DOC_TITLE@







Xmega Application Note


xMega_official_drivers_and_examples.rar > documentation_8h.html

@DOC_TITLE@







Xmega Application Note








documentation.h File Reference

Go to the source code of this file.






@DOC_TITLE@












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xMega_official_drivers_and_examples.rar > index.html

AVR1304 Using the XMEGA DMA Controller




Frames are disabled. Click here to go to the main page.


xMega_official_drivers_and_examples.rar > globals_vars.html

@DOC_TITLE@







Xmega Application Note









All
Functions
Variables
Defines



& nbsp;


gInterruptDone
: dma_example.c
gStatus
: dma_example.c
memoryBlockA
: dma_example.c
memoryBlockB
: dma_example.c





@DOC_TITLE@












Generated on Fri Jul 17 17:12:43 2009 for AVR1304 Using the XMEGA DMA Controller by 1.5.9


xMega_official_drivers_and_examples.rar > graph_legend.html

@DOC_TITLE@







Xmega Application Note








Graph Legend This page explains how to interpret the graphs that are generated by doxygen.
Consider the following example: /*! Invisible class because of truncation */
class Invisible { };

/*! Truncated class, inheritance relation is hidden */
class Truncated : public Invisible { };

/* Class not documented with doxygen comments */
class Undocumented { };

/*! Class that is inherited using public inheritance */
class PublicBase : public Truncated { };

/*! A template class */
template & lt; class T & gt; class Templ { };

/*! Class that is inherited using protected inheritance */
class ProtectedBase { };

/*! Class that is inherited using private inheritance */
class PrivateBase { };

/*! Class that is used by the Inherited class */
class Used { };

/*! Super class that inherits a number of other classes */
class Inherited : public PublicBase,
protected ProtectedBase,
private PrivateBase,
public Undocumented,
public Templ & lt;int & gt;
{
private :
Used *m_usedClass;
};
This will result in the following graph:




The boxes in the above graph have the following meaning:

A filled gray box represents the struct or class for which the graph is generated.

A box with a black border denotes a documented struct or class.

A box with a grey border denotes an undocumented struct or class.

A box with a red border denotes a documented struct or class forwhich not all inheritance/containment relations are shown. A graph is truncated if it does not fit within the specified boundaries.

The arrows have the following meaning:

A dark blue arrow is used to visualize a public inheritance relation between two classes.

A dark green arrow is used for protected inheritance.

A dark red arrow is used for private inheritance.

A purple dashed arrow is used if a class is contained or used by another class. The arrow is labeled with the variable(s) through which the pointed class or struct is accessible.

A yellow dashed arrow denotes a relation between a template instance and the template class it was instantiated from. The arrow is labeled with the template parameters of the instance.





@DOC_TITLE@












Generated on Fri Jul 17 17:12:43 2009 for AVR1304 Using the XMEGA DMA Controller by 1.5.9


xMega_official_drivers_and_examples.rar > globals_defs.html

@DOC_TITLE@







Xmega Application Note









All
Functions
Variables
Defines



& nbsp;


AVR_ENTER_CRITICAL_REGION
: avr_compiler.h
AVR_LEAVE_CRITICAL_REGION
: avr_compiler.h
DMA_Disable
: dma_driver.h
DMA_Enable
: dma_driver.h
F_CPU
: avr_compiler.h
MEM_BLOCK
: dma_example.c
MEM_BLOCK_COUNT
: dma_example.c
MEM_BLOCK_SIZE
: dma_example.c





@DOC_TITLE@












Generated on Fri Jul 17 17:12:43 2009 for AVR1304 Using the XMEGA DMA Controller by 1.5.9


xMega_official_drivers_and_examples.rar > dma__driver_8c_source.html

@DOC_TITLE@







Xmega Application Note







dma_driver.c Go to the documentation of this file. 00001 /* This file has been prepared for Doxygen automatic documentation generation.*/
00059 #include " dma_driver.h "
00060
00061
00068 void DMA_Reset ( void )
00069 {
00070 DMA.CTRL & amp;= ~DMA_ENABLE_bm;
00071 DMA.CTRL |= DMA_RESET_bm;
00072 while (DMA.CTRL & amp; DMA_RESET_bm); // Wait until reset is completed
00073 }
00074
00075
00088 void DMA_ConfigDoubleBuffering ( DMA_DBUFMODE_t dbufMode )
00089 {
00090 DMA.CTRL = ( DMA.CTRL & amp; ~DMA_DBUFMODE_gm ) | dbufMode;
00091 }
00092
00093
00105 void DMA_SetPriority ( DMA_PRIMODE_t priMode )
00106 {
00107 DMA.CTRL = ( DMA.CTRL & amp; ~DMA_PRIMODE_gm ) | priMode;
00108 }
00109
00110
00119 uint8_t DMA_CH_IsOngoing ( volatile DMA_CH_t * channel )
00120 {
00121 uint8_t flagMask;
00122 flagMask = channel- & gt;CTRLB & amp; DMA_CH_CHBUSY_bm;
00123 return flagMask;
00124 }
00125
00131 uint8_t DMA_IsOngoing ( void )
00132 {
00133 uint8_t flagMask;
00134 flagMask = DMA.STATUS & amp; 0xF0;
00135 return flagMask;
00136 }
00137
00149 uint8_t DMA_CH_IsPending ( volatile DMA_CH_t * channel )
00150 {
00151 uint8_t flagMask;
00152 flagMask = channel- & gt;CTRLB & amp; DMA_CH_CHPEND_bm;
00153 return flagMask;
00154 }
00155
00156
00166 uint8_t DMA_IsPending ( void )
00167 {
00168 uint8_t flagMask;
00169 flagMask = DMA.STATUS & amp; 0x0F;
00170 return flagMask;
00171 }
00172
00185 uint8_t DMA_ReturnStatus_non_blocking ( volatile DMA_CH_t * channel )
00186 {
00187 uint8_t relevantFlags;
00188 relevantFlags = channel- & gt;CTRLB & amp; (DMA_CH_ERRIF_bm | DMA_CH_TRNIF_bm);
00189 return relevantFlags;
00190 }
00191
00192
00207 uint8_t DMA_ReturnStatus_blocking ( volatile DMA_CH_t * channel )
00208 {
00209 uint8_t flagMask;
00210 uint8_t relevantFlags;
00211
00212 flagMask = DMA_CH_ERRIF_bm | DMA_CH_TRNIF_bm;
00213
00214 do {
00215 relevantFlags = channel- & gt;CTRLB & amp; flagMask;
00216 } while (relevantFlags == 0x00);
00217
00218 channel- & gt;CTRLB = flagMask;
00219 return relevantFlags;
00220 }
00221
00229 void DMA_EnableChannel ( volatile DMA_CH_t * channel )
00230 {
00231 channel- & gt;CTRLA |= DMA_CH_ENABLE_bm;
00232 }
00233
00234
00242 void DMA_DisableChannel ( volatile DMA_CH_t * channel )
00243 {
00244 channel- & gt;CTRLA & amp;= ~DMA_CH_ENABLE_bm;
00245 }
00246
00247
00256 void DMA_ResetChannel ( volatile DMA_CH_t * channel )
00257 {
00258 channel- & gt;CTRLA & amp;= ~DMA_CH_ENABLE_bm;
00259 channel- & gt;CTRLA |= DMA_CH_RESET_bm;
00260 channel- & gt;CTRLA & amp;= ~DMA_CH_RESET_bm;
00261 }
00262
00263
00275 void DMA_SetIntLevel ( volatile DMA_CH_t * channel,
00276 DMA_CH_TRNINTLVL_t transferInt,
00277 DMA_CH_ERRINTLVL_t errorInt )
00278 {
00279 channel- & gt;CTRLB = (channel- & gt;CTRLB & amp; ~(DMA_CH_ERRINTLVL_gm | DMA_CH_TRNINTLVL_gm)) |
00280 transferInt | errorInt;
00281 }
00282
00283
00304 void DMA_SetupBlock ( volatile DMA_CH_t * channel,
00305 const void * srcAddr,
00306 DMA_CH_SRCRELOAD_t srcReload,
00307 DMA_CH_SRCDIR_t srcDirection,
00308 void * destAddr,
00309 DMA_CH_DESTRELOAD_t destReload,
00310 DMA_CH_DESTDIR_t destDirection,
00311 uint16_t blockSize,
00312 DMA_CH_BURSTLEN_t burstMode,
00313 uint8_t repeatCount,
00314 bool useRepeat )
00315 {
00316 channel- & gt;SRCADDR0 = (( (uint32_t) srcAddr) & gt; & gt; 0*8 ) & amp; 0xFF;
00317 channel- & gt;SRCADDR1 = (( (uint32_t) srcAddr) & gt; & gt; 1*8 ) & amp; 0xFF;
00318 channel- & gt;SRCADDR2 = (( (uint32_t) srcAddr) & gt; & gt; 2*8 ) & amp; 0xFF;
00319
00320 channel- & gt;DESTADDR0 = (( (uint32_t) destAddr) & gt; & gt; 0*8 ) & amp; 0xFF;
00321 channel- & gt;DESTADDR1 = (( (uint32_t) destAddr) & gt; & gt; 1*8 ) & amp; 0xFF;
00322 channel- & gt;DESTADDR2 = (( (uint32_t) destAddr) & gt; & gt; 2*8 ) & amp; 0xFF;
00323
00324 channel- & gt;ADDRCTRL = (uint8_t) srcReload | srcDirection |
00325 destReload | destDirection;
00326 channel- & gt;TRFCNT = blockSize;
00327 channel- & gt;CTRLA = ( channel- & gt;CTRLA & amp; ~( DMA_CH_BURSTLEN_gm | DMA_CH_REPEAT_bm ) ) |
00328 burstMode | ( useRepeat ? DMA_CH_REPEAT_bm : 0);
00329
00330 if ( useRepeat ) {
00331 channel- & gt;REPCNT = repeatCount;
00332 }
00333 }
00334
00335
00345 void DMA_EnableSingleShot ( volatile DMA_CH_t * channel )
00346 {
00347 channel- & gt;CTRLA |= DMA_CH_SINGLE_bm;
00348 }
00349
00350
00361 void DMA_DisableSingleShot ( volatile DMA_CH_t * channel )
00362 {
00363 channel- & gt;CTRLA & amp;= ~DMA_CH_SINGLE_bm;
00364 }
00365
00366
00375 void DMA_SetTriggerSource ( volatile DMA_CH_t * channel, uint8_t trigger )
00376 {
00377 channel- & gt;TRIGSRC = trigger;
00378 }
00379
00380
00387 void DMA_StartTransfer ( volatile DMA_CH_t * channel )
00388 {
00389 channel- & gt;CTRLA |= DMA_CH_TRFREQ_bm;
00390 }




@DOC_TITLE@












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xMega_official_drivers_and_examples.rar > tree.html

TreeView







AVR1304 Using the XMEGA DMA Controller

Main Page
File List

avr_compiler.h
dma_driver.c
dma_driver.h
dma_example.c
documentation.h

Globals


xMega_official_drivers_and_examples.rar > readme.html

Code Documentation Redirecting


xMega_official_drivers_and_examples.rar > dma_driver.h

/* This file has been prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief XMEGA DMA Controller driver header file.
*
* This file contains the function prototypes and enumerator definitions
* for various configuration parameters for the XMEGA DMA driver.
*
* The driver is not intended for size and/or speed critical code, since
* most functions are just a few lines of code, and the function call
* overhead would decrease code performance. The driver is intended for
* rapid prototyping and documentation purposes for getting started with
* the XMEGA DMA module.
*
* For size and/or speed critical code, it is recommended to copy the
* function contents directly into your application instead of making
* a function call.
*
* \par Application note:
* AVR1304: Using the XMEGA DMA Controller
*
* \par Documentation
* For comprehensive code documentation, supported compilers, compiler
* settings and supported devices see readme.html
*
* \author
* Atmel Corporation: http://www.atmel.com \n
* Support email: avr@atmel.com
*
* $Revision: 2593 $
* $Date: 2009-07-17 15:22:29 +0200 (fr, 17 jul 2009) $ \n
*
* Copyright (c) 2008, Atmel Corporation All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of ATMEL may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL " AS IS " AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
* SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*****************************************************************************/
#ifndef DMA_DRIVER_H
#define DMA_DRIVER_H

#include " avr_compiler.h "


/*! \brief This function enable the DMA module.
*
* \note Each individual DMA channel must be enabled separately
* using the DMA_EnableChannel() function.
*/
#define DMA_Enable() ( DMA.CTRL |= DMA_ENABLE_bm )

/*! \brief This function disables the DMA module.
*
* \note On-going transfers will be aborted.
*/
#define DMA_Disable() ( DMA.CTRL & = ~DMA_ENABLE_bm )



/*! Prototyping of functions. */
void DMA_Reset( void );
void DMA_ConfigDoubleBuffering( DMA_DBUFMODE_t dbufMode );
void DMA_SetPriority( DMA_PRIMODE_t priMode );
uint8_t DMA_CH_IsOngoing( volatile DMA_CH_t * channel );
uint8_t DMA_IsOngoing( void );
uint8_t DMA_CH_IsPending( volatile DMA_CH_t * channel );
uint8_t DMA_IsPending( void );
uint8_t DMA_ReturnStatus_non_blocking( volatile DMA_CH_t * channel );
uint8_t DMA_ReturnStatus_blocking( volatile DMA_CH_t * channel );
void DMA_EnableChannel( volatile DMA_CH_t * channel );
void DMA_DisableChannel( volatile DMA_CH_t * channel );
void DMA_ResetChannel( volatile DMA_CH_t * channel );
void DMA_SetIntLevel( volatile DMA_CH_t * channel,
DMA_CH_TRNINTLVL_t transferInt,
DMA_CH_ERRINTLVL_t errorInt );
void DMA_SetupBlock( volatile DMA_CH_t * channel,
const void * srcAddr,
DMA_CH_SRCRELOAD_t srcReload,
DMA_CH_SRCDIR_t srcDirection,
void * destAddr,
DMA_CH_DESTRELOAD_t destReload,
DMA_CH_DESTDIR_t destDirection,
uint16_t blockSize,
DMA_CH_BURSTLEN_t burstMode,
uint8_t repeatCount,
bool useRepeat );
void DMA_EnableSingleShot( volatile DMA_CH_t * channel );
void DMA_DisableSingleShot( volatile DMA_CH_t * channel );
void DMA_SetTriggerSource( volatile DMA_CH_t * channel, uint8_t trigger );
void DMA_StartTransfer( volatile DMA_CH_t * channel );

#endif


xMega_official_drivers_and_examples.rar > XMEGA EEPROM.pdf

AVR1315: Accessing the XMEGA EEPROM
Features
o
o
o
o
o

8-bit
Microcontrollers

I/O-mapped access
Memory-mapped access
Split erase and write operations supported
Efficient page-oriented access
Driver source code included

Application Note

1 Introduction
This application note describes the basic functionality of the XMEGA(TM) EEPROM
with code examples to get up and running quickly. A driver interface written in C is
included as well.
Figure 1-1. EEPROM Overview

Data Space

External
Memory
Bus

Internal
SRAM
EEPROM
Memory
Memorymapped
EEPROM

NVM Control Registers

I/O
Registers

NVM
Interface

Rev. 8066A-AVR-04/08

2 EEPROM Overview
This section provides an overview of the functionality and basic configuration options
of the EEPROM. Section 3 then walks you through the basic steps to get you up and
running, with register descriptions and configuration details.

2.1 The Non-volatile Memory Controller
The XMEGA EEPROM is accessed through the Non-volatile Memory (NVM)
controller, which is also used for access to fuse and lock bits and for updating Flash
memory from software. Please refer to the application note "AVR1316: XMEGA
Bootloader" or the device datasheet for more details.
As the NVM controller not only serves the EEPROM memory, it is important to check
that the NVM controller is not busy with other operations (such as Flash memory
update) before using it to access EEPROM. The NVM Busy bit (NVMBUSY) in the
NVM Status register (STATUS) is set whenever the NVM controller is busy.
Using the NVM to access EEPROM involves using NVM Commands. There are
commands for erasing, writing, reading etc. The procedure for issuing a command is
as follows:
1. Wait for any previous NVM operations to finish.
2. Load necessary information into the Address registers (ADDRn) and/or the Data
registers (DATAn). This will be described in later sections.
3. Load the command code into the Command register (CMD).
4. Load the Protect IO Register signature (byte value 0xD8) into the Configuration
Change Protection register (CCP). This will automatically disable all interrupts for
the next four CPU instruction cycles.
5. Within the next four CPU instruction cycles, set the Command Execute bit
(CMDEX) in NVM Control Register A (CTRLA).
6. The operation is finished when the NVM Busy bit (NVMBUSY) is cleared.
The relevant command codes and their use are described in the following sections.
By setting the EEPROM Mapping Enable bit (EEMAPEN) in NVM Control Register B
(CTRLB), EEPROM access is mapped to data memory space instead of using the
NVM controller. However, one must still check that the NVM is not busy before
accessing EEPROM, as the NVM is used internally. Memory-mapped access is
covered in Section 3.2.

2.2 Erasing and Writing
There are two ways to update the EEPROM memory: atomic write and split operation.
With atomic write, EEPROM locations are erased and written in one operation. With
split operation, erasing and writing are separate operations.
When erasing the EEPROM locations, all bits are set to logic one. A split write can
then program selected bits to logic zero. Split write operations cannot change a bit
from zero to one, as opposed to an atomic write that first erase to logic one and then
writes logic zeros to selected bits. This means that multiple writes with different
values eventually results in all locations being logic zeros, if the locations are not
2

AVR1315
8066A-AVR-04/08

AVR1315
erased in between. This is similar to a logic AND operation between existing value
and written value.
An atomic write takes approximately twice the time of one erase or one write.
Therefore, split operation can be used to save time by erasing EEPROM locations in
advance, e.g. during initialization. For instance, if the application needs to store vital
data when a power drop is detected, a split write will take less time than an atomic
write.
Another useful application for the split operation is to increase EEPROM endurance,
especially for applications that update EEPROM locations frequently. By
implementing a scheme where EEPROM locations are not erased unless they have
to, the split operation feature can be used to increase EEPROM endurance. For more
details, refer to the application note "AVR101: High Endurance EEPROM Storage".
Different erase and write operations, together with byte values before and after the
operation, are illustrated in Figure 2-1 below.
Figure 2-1. Atomic Write, Split Write and Erase Operations
0x57

0

1

0

1

0

1

1

1

Atomic write: 0xD0

0x57

0

1

0

1

0

1

1

1

Split write: 0xF0

0xD0

1

1

0

1

0

0

0

0

0x50

0

1

0

1

0

0

0

0

0x57

0

1

0

1

0

1

1

1

0xFF

1

1

1

1

1

1

1

1

1

0

0

0

0

Erase
0xFF

Split write: 0xF0
1

1

1

1

1

1

1

1

0xF0

1

1

1

2.3 The Temporary Page Buffer
The EEPROM memory is organized in pages, and both erase and write operations
operate on pages. The page size depends on memory size and is given in the device
datasheet. Erase and write operations use a temporary page buffer, both to keep
track of which bytes in a page should be accessed and, for write operations the data
itself.
A write operation actually consists of two operations: (1) loading the page buffer with
data and (2) writing data to an EEPROM page. When loading the page buffer, the
lower part of the EEPROM address is used to select a byte in the page buffer, while
the upper part is ignored. When writing or erasing a page, the upper part of the
address selects the page, while the lower part is ignored.
Figure 2-2 below shows an example where one byte is loaded into the page buffer
and the buffer is written to an EEPROM page afterwards. The figure shows that the
buffer location that was loaded gets tagged so that the page buffer knows which byte
locations need to be written.
For a page erase operation, only the bytes that are tagged in the buffer will be erased
in EEPROM. Unless you plan to perform a write afterwards, the actual values in the
buffer do not matter.
3
8066A-AVR-04/08

Figure 2-2. Example Buffer Load and Page Write with a 32-byte Buffer
Load Page Buffer

EEPROM Address
Data
byte

0x0102

Page Buffer
0

1

2

29

30

31

Write Page

EEPROM Address

0x0102
Page Buffer
0

1

2

29

30

31

EEPROM Pages

7

8

9

10

11

Once a byte has been loaded into the buffer, the EEPROM Page Buffer Active
Loading bit (EELOAD) in the NVM Status register (STATUS) will be set. The bit
remains set until either the buffer is flushed or a page write is performed (atomic or
split write). To flush the page buffer, issue the EEPROM Flush Page Buffer command
(byte value 0x36) to the NVM controller. Erase and write commands are covered in
Section 3.1.
Note that if multiple bytes are loaded to the same buffer location, the resulting value is
a logical AND between existing data and the new data, similar to what happens
during page write operations.

2.4 DMA Considerations
When using DMA and EEPROM in the same application, it should be considered that
the DMA controller cannot access the EEPROM when the CPU is in any sleep mode.
An ongoing DMA transaction will be aborted if an access is attempted during sleep.
Please refer to the application note "AVR1304: Using the XMEGA DMA Controller" for
more information.

2.5 Interrupt Considerations
When using interrupts and EEPROM in the same application, the following should be
considered:
o Take care not to corrupt the EEPROM page buffer contents. When loading the
page buffer, make sure that no interrupt handlers access the page buffer. Or, if an
interrupt handler is used to access the page buffer, make sure that other parts of
the application do not access it at the same time.
o Instead of continuously polling the NVM Busy flag (NVMBUSY) to detect when an
NVM operation is finished, it is possible to enable the EEPROM Interrupt by
setting an appropriate interrupt level with the EEPROM Interrupt Level bitfield
4

AVR1315
8066A-AVR-04/08

AVR1315
(EELVL) in the Interrupt Control register (INTCTRL). The corresponding interrupt
handler will be called whenever the NVM Busy flag (NVMBUSY) is not set. For
instance, this can be used to implement an interrupt-controlled EEPROM update.
More details on interrupts can be found in application note "AVR1305: XMEGA
Interrupts and the Programmable Multi-level Interrupt Controller".

3 Getting Started
This section walks you through the basic steps for getting up and running with the
XMEGA EEPROM. The necessary registers are described along with relevant bit
settings.

3.1 I/O-mapped Access
I/O-mapped access means that all EEPROM access is done using I/O registers in the
NVM controller and issuing NVM commands.
3.1.1 Reading EEPROM
The steps to read an EEPROM location are as follows:
1. Wait for any previous NVM operations to finish.
2. Load the NVM Address registers (ADDRn) with the desired EEPROM byte
address.
3. Issue the EEPROM Read command (byte value 0x06) to the NVM controller.
4. The CPU will be halted two clock cycles and then data is available in NVM Data
Register 0 (DATA0). There is no need to wait for the NVM Busy bit to clear.
This operation is not supported if memory-mapped EEPROM access is enabled.
3.1.2 Loading EEPROM Page Buffer
The steps to load a byte into the temporary page buffer are as follows:
1. Wait for any previous NVM operations to finish.
2. Load the EEPROM Load Page Buffer command (byte value 0x33) into the NVM
Command register (CMD).
3. Load the NVM Address registers (ADDRn) with the desired EEPROM byte
address.
4. Load NVM Data Register 0 (DATA0) with the data byte. This automatically
triggers the buffer load operation. This is a command that does not require the
Command Execute bit (CMDEX) in NVM Control Register A (CTRLA) to be set.
The CPU will be halted for one clock cycle during this operation.
It is important that the write to the data register is done last, as this triggers the
operation itself. The order of the other steps is not important.
This operation is not supported if memory-mapped EEPROM access is enabled.
3.1.3 Atomic Write (Erase and Write) EEPROM Page
The steps to erase a page and write prepared page buffer data to the page is as
follows:
5
8066A-AVR-04/08

1. Wait for any previous NVM operations to finish.
2. Load the NVM Address registers (ADDRn) with an EEPROM address within the
page to be updated.
3. Issue the EEPROM Atomic Write command (byte value 0x35) to the NVM
controller.
4. The operation is finished when the NVM Busy bit is cleared.
Only the buffer locations that have been loaded will be updated in the EEPROM
page.
3.1.4 Erase EEPROM Page
The steps to erase a page without writing anything are as follows:
1. Wait for any previous NVM operations to finish.
2. Load the NVM Address registers (ADDRn) with an EEPROM address within the
page to be erased.
3. Issue the EEPROM Erase Page command (byte value 0x32) to the NVM
controller.
4. The operation is finished when the NVM Busy bit is cleared.
Only the buffer locations that have been loaded will be erased in the EEPROM page.
Therefore, dummy bytes should be loaded into every buffer location corresponding to
the bytes you want to erase from the EEPROM page.
3.1.5 Split Write (Write Only) EEPROM Page
The steps to write prepared page buffer data to an already erased page are as
follows:
1. Wait for any previous NVM operations to finish.
2. Load the NVM Address registers (ADDRn) with an EEPROM address within the
page to be updated.
3. Issue the EEPROM Split Write command (byte value 0x34) to the NVM
controller.
4. The operation is finished when the NVM Busy bit is cleared.
Only the buffer locations that have been loaded will be updated in the EEPROM
page.

3.2 Memory-mapped Access
Memory-mapped access means that EEPROM read and page buffer load operations
are mapped into data space. This means that EEPROM data can be read simply by
reading from a location in data memory. For the XMEGA A1 family, memory-mapped
EEPROM starts at address 0x1000.
Page buffer loading is also simply a matter of writing to data memory. However,
flushing the buffer and erasing and writing pages must still be done through the NVM
controller as for I/O-mapped access. Also, the NVM controller must not be busy when
accessing EEPROM.
6

AVR1315
8066A-AVR-04/08

AVR1315
The necessary steps to perform an atomic write using memory-mapped access are
as follows:
1. Wait for any pervious NVM operations to finish.
2. Load page buffer by writing directly to data space, while staying inside one
EEPROM page.
3. Load the NVM Address registers (ADDRn) with an EEPROM address within the
page to be updated.
4. Issue the EEPROM Atomic Write command (byte value 0x35) to the NVM
controller.
5. The operation is finished when the NVM Busy bit is cleared.
The procedure is similar for erase and split write operations. In short, reading data
and loading the page buffer is replaced by memory-mapped access. The rest is
similar to I/O-mapped access. Please refer to the code examples of this application
note for more details.

4 Driver Implementation
This application note includes a source code package with a basic EEPROM driver
implemented in C. It is written for the IAR Embedded Workbench(R) compiler.
Note that this EEPROM driver is not intended for use with high-performance code. It
is designed as a library to get started with the EEPROM. For timing and code space
critical application development, you should access the EEPROM (NVM) registers
directly. Please refer to the driver source code and device datasheet for more details.

4.1 Files
The source code package consists of three files:
o eeprom_driver.c - EEPROM driver source file
o eeprom_driver.h - EEPROM driver header file
o eeprom_example.c - Example code using the driver
For a complete overview of the available driver interface functions and their use,
please refer to the source code documentation.

4.2 Doxygen Documentation
All source code is prepared for automatic documentation generation using Doxygen.
Doxygen is a tool for generating documentation from source code by analyzing the
source code and using special keywords. For more details about Doxygen please visit
http://www.doxygen.org. Precompiled Doxygen documentation is also supplied with
the source code accompanying this application note, available from the readme.html
file in the source code folder.

7
8066A-AVR-04/08

Disclaimer

Headquarters

International

Atmel Corporation
2325 Orchard Parkway
San Jose, CA 95131
USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600

Atmel Asia
Room 1219
Chinachem Golden Plaza
77 Mody Road Tsimshatsui
East Kowloon
Hong Kong
Tel: (852) 2721-9778
Fax: (852) 2722-1369

Atmel Europe
Le Krebs
8, Rue Jean-Pierre Timbaud
BP 309
78054 Saint-Quentin-enYvelines Cedex
France
Tel: (33) 1-30-60-70-00
Fax: (33) 1-30-60-71-11

Atmel Japan
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
Tel: (81) 3-3523-3551
Fax: (81) 3-3523-7581

Technical Support
avr@atmel.com

Sales Contact
www.atmel.com/contacts

Product Contact
Web Site
www.atmel.com

Literature Request
www.atmel.com/literature

Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any
intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL'S TERMS AND
CONDITIONS OF SALE LOCATED ON ATMEL'S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED
OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS,
BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS
BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the
contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any
commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in,
automotive applications. Atmel's products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.

(C) 2008 Atmel Corporation. All rights reserved. Atmel(R), logo and combinations thereof, AVR(R) and others, are the registered trademarks or
trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.

8066A-AVR-04/08


xMega_official_drivers_and_examples.rar > XMEGA SPI.pdf

AVR1309: Using the XMEGA SPI
Features
o Introduction to SPI and the XMEGA(TM) SPI module
o Setup and use of the XMEGA SPI module
o Implementation of module drivers
Polled master
Interrupt controlled master
Polled slave
Interrupt controlled slave
o Code examples for interrupt controlled and polled drivers

8-bit
Microcontrollers
Application Note

1 Introduction
This application note describes how to set up and use the SPI module in the AVR(R)
XMEGA. Both interrupt controlled and polled C code drivers and examples are
included for master and slave applications.
Serial buses are more and more preferred over parallel. The wiring is simpler, and
as the efficiency of serial interfaces increases, the speed advantage of a parallel
transmission gets less important. Typical peripherals that use a serial interface are
converters (A/D and D/A), memories (RAM and EEPROM), real time clocks,
sensors and other controllers for LCD, CAN USB etc.
Figure 1-1. Basic SPI implementation

SCK
MASTER

MOSI
MISO

SLAVE

SS

Rev. 8057A-AVR-02/08

2 The SPI bus
The Serial Peripheral Interface (SPI) is mainly used in synchronous serial
transmissions in a master/slave relationship. The master initiates and controls the
transfer, while the slave responds.
SPI is a full duplex interface, and at a low cost enabling high-speed communication
between master and slave. SPI does not have a specific higher-level protocol, which
means there is almost no overhead. The drawback is that there is no
acknowledgement and flow control, and the master doesn't even have to be aware of
the slave's presence.

2.1 Data and control lines
The standard SPI configuration makes use of two control and two data lines. The data
lines are MOSI (Master Out, Slave In) and MISO (Master In, Slave Out), transferring
data in each direction. The control lines are SCK (SPI Clock) and SS (Slave Select). If
SS is used, the master selects a slave device by pulling this line low, and supplies the
clock signal. Data is now transferred in both directions simultaneously, and it is up to
a higher-level protocol to define the meaning of each byte.
Figure 2-1. Master/slave interconnection
MASTER

SLAVE
MSB

LSB

GPIO

MISO

SCK

SS

LSB

MOSI

SCK

SPI CLOCK GENERATOR

MISO

MOSI

8 BIT SHIFT REGISTER

MSB

SS

8 BIT SHIFT REGISTER

SHIFT
ENABLE

If multiple slaves exists and should be independently addressed, the master must
generate a SS signal for each slave. This is illustrated in Figure 2-2.

2

AVR1309
8057A-AVR-02/08

AVR1309
Figure 2-2. Multi slave implementation

SCK

SCK

MOSI

MOSI

MISO

MISO

SLAVE #1
MASTER
SS1

SS

SS2
SCK

SS3

MOSI
SLAVE #2
MISO
SS

SCK
MOSI
SLAVE #3
MISO
SS

2.2 Modes and configuration
There is no official specification for SPI communication, making flexibility of the
devices important. Clock polarity (CPOL) and clock phase (CPHA) determines the
data setup and sampling point, and must be configured the same for devices to
communicate.
Table 2-1. SPI modes
SPI mode

Configuration

Leading edge

Trailing edge

CPOL

CPHA

0

0

0

Rising

Sample

Falling

Setup

1

0

1

Rising

Setup

Falling

Sample

2

1

0

Falling

Sample

Rising

Setup

3

1

1

Falling

Setup

Rising

Sample

For more information about SPI modes and configuration, please see the XMEGA
SPI data sheet.

3
8057A-AVR-02/08

3 The XMEGA SPI module
The XMEGA SPI module is designed for high-speed data transfers between the
XMEGA and other SPI devices. The control bits allow flexible configuration to enable
a flawless connection.

3.1 Registers
The SPI module consists of the baud rate generator, status and control logic with
supporting registers listed in Table 3-1.
Table 3-1. SPI module registers.
Register name

C struct and element

SPI Control Register

SPIx.CTRL

SPI Interrupt Control Register

SPIx.INTCTRL

SPI Status Register

SPIx.STATUS

SPI Data Register

SPIx.DATA

All control bits with exception of the interrupt level bits, are located in CTRL. The two
interrupt level bits are found in INTCTRL, and the SPI interrupt and write collision
flags in STATUS.
The DATA register is a read/write register for data transfers. Reading the registers
returns the data currently in the SPI shift register, while writing will initiate a data
transmission. The system is single buffered in the transmit direction and double
buffered in the receive direction. As a result, new data must not be written to the
DATA register before the entire shift cycle is complete. To avoid losing data, a
received character must be read from DATA before the next character has been
completely shifted in.

3.2 The SS pin
In master mode the SS pin is fully configurable from software, and typically used as
one of these three options:
o

Input (interrupt) from other master(s) accessing the bus

o

Output SS signal to slave

o

General output

If the SPI module's SS pin is configured as input, the function is like the first option
above. This SS input function is controlled from the SPI module hardware, and the SS
pin must be held logic high to ensure master SPI operation. If pulled low by other
master(s) using the SPI bus, the SPI module will avoid bus contention by entering
slave mode and consequently not driving the SCK and MOSI lines. Entering slave
mode is signaled by setting the SPI interrupt flag, generating an interrupt if enabled.
Configuring the SS pin as output enables the two last typical options, both controlled
from software and not affecting the SPI module operation. The SS pin is no different
than any other GPIO pins when it is configured as an output.
Often, several slaves are connected to the same bus, while the application would
address one slave at a time. As illustrated in Figure 2-2, this can be done using
4

AVR1309
8057A-AVR-02/08

AVR1309
several GPIO pins, one for each slave or through some external logic reducing the
number of pins needed.

4 SPI driver
The driver included in this application note supports both polled and interruptcontrolled SPI operation for both master and slave. The driver is intended for rapid
prototyping and to get started with the XMEGA SPI module.

4.1 Files
The SPI driver source code consists of the following files:
o spi_driver.c - driver source file
o spi_driver.h - driver header file
For a complete overview of the available driver interface functions and their use,
please refer to the source code documentation.

5 Code examples
Two code examples are included that show how to use the SPI drivers for interruptdriven and polled operation. In both examples, SPIC is used as master, while SPID
serves as slave.

5.1 Files
The SPI code examples are contained in the following files:
o spi_interrupt_example.c
o spi_polled_example.c

- Example of interrupt-driven SPI operation
- Example of polled SPI operation

5.2 Interrupt-driven
The interrupt-driven code example uses the SPI driver to instantiate a master and a
slave. A data packet is then initialized and sent to the slave. When data is received at
the slave, an ISR increments the data before it is put back in the data register, ready
to be shifted back to the master. The master interrupt handler will transfer the number
of bytes contained in the data packet. When the complete flag for the data packet is
set, the master verifies that it has received the correct values.

5.3 Polled
The polled code example uses the SPI driver to instantiate a master and slave. The
example is split into two sections:
First, the master sends one byte at the time to the slave, the slave increments the
byte and puts it in the shift register. The master sends a dummy byte, in order to fetch
the byte from the slave. The master then verifies that it has received the correct
value.
In the second section, a data packet is initialized and sent to the slave. The slave
does not manipulate the data, which is shifted back to the slave as new bytes are
5
8057A-AVR-02/08

transferred. When the whole packet is sent, the master verifies that the received
bytes match the sent bytes (except for the last byte which is not shifted back to the
master).

6 Doxygen Documentation
All source code is prepared for automatic documentation generation using Doxygen.
Doxygen is a tool for generating documentation from source code by analyzing the
source code and using special keywords. For more details about Doxygen please visit
http://www.doxygen.org. Precompiled Doxygen documentation is also supplied with
the source code accompanying this application note, available from the readme.html
file in the source code folder.

6

AVR1309
8057A-AVR-02/08

Disclaimer

Headquarters

International

Atmel Corporation
2325 Orchard Parkway
San Jose, CA 95131
USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600

Atmel Asia
Room 1219
Chinachem Golden Plaza
77 Mody Road Tsimshatsui
East Kowloon
Hong Kong
Tel: (852) 2721-9778
Fax: (852) 2722-1369

Atmel Europe
Le Krebs
8, Rue Jean-Pierre Timbaud
BP 309
78054 Saint-Quentin-enYvelines Cedex
France
Tel: (33) 1-30-60-70-00
Fax: (33) 1-30-60-71-11

Atmel Japan
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
Tel: (81) 3-3523-3551
Fax: (81) 3-3523-7581

Technical Support
avr@atmel.com

Sales Contact
www.atmel.com/contacts

Product Contact
Web Site
www.atmel.com

Literature Request
www.atmel.com/literature

Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any
intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL'S TERMS AND
CONDITIONS OF SALE LOCATED ON ATMEL'S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED
OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
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8057A-AVR-02/08


xMega_official_drivers_and_examples.rar > iox128a1.h

/* Copyright (c) 2009 Atmel Corporation
All rights reserved.

Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:

* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.

* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.

* Neither the name of the copyright holders nor the names of
contributors may be used to endorse or promote products derived
from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS " AS IS "
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE. */

/* $Id: iox128a1.h,v 1.1.2.17 2009/12/29 22:41:04 arcanum Exp $ */

/* avr/iox128a1.h - definitions for ATxmega128A1 */

/* This file should only be included from & lt; avr/io.h & gt; , never directly. */

#ifndef _AVR_IO_H_
# error " Include & lt; avr/io.h & gt; instead of this file. "
#endif

#ifndef _AVR_IOXXX_H_
# define _AVR_IOXXX_H_ " iox128a1.h "
#else
# error " Attempt to include more than one & lt; avr/ioXXX.h & gt; file. "
#endif


#ifndef _AVR_ATxmega128A1_H_
#define _AVR_ATxmega128A1_H_ 1


/* Ungrouped common registers */
#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */
#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */
#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */
#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */
#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */
#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */
#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */
#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */
#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */
#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */
#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */
#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */
#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */
#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */
#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */
#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */

#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */
#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */
#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */
#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */
#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */
#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */
#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */
#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */
#define SREG _SFR_MEM8(0x003F) /* Status Register */


/* C Language Only */
#if !defined (__ASSEMBLER__)

#include & lt; stdint.h & gt;

typedef volatile uint8_t register8_t;
typedef volatile uint16_t register16_t;
typedef volatile uint32_t register32_t;


#ifdef _WORDREGISTER
#undef _WORDREGISTER
#endif
#define _WORDREGISTER(regname) \
__extension__ union \
{ \
register16_t regname; \
struct \
{ \
register8_t regname ## L; \
register8_t regname ## H; \
}; \
}

#ifdef _DWORDREGISTER
#undef _DWORDREGISTER
#endif
#define _DWORDREGISTER(regname) \
__extension__ union \
{ \
register32_t regname; \
struct \
{ \
register8_t regname ## 0; \
register8_t regname ## 1; \
register8_t regname ## 2; \
register8_t regname ## 3; \
}; \
}


/*
==========================================================================
IO Module Structures
==========================================================================
*/


/*
--------------------------------------------------------------------------
XOCD - On-Chip Debug System
--------------------------------------------------------------------------
*/

/* On-Chip Debug System */
typedef struct OCD_struct
{
register8_t OCDR0; /* OCD Register 0 */
register8_t OCDR1; /* OCD Register 1 */
} OCD_t;


/* CCP signatures */
typedef enum CCP_enum
{
CCP_SPM_gc = (0x9D & lt; & lt; 0), /* SPM Instruction Protection */
CCP_IOREG_gc = (0xD8 & lt; & lt; 0), /* IO Register Protection */
} CCP_t;


/*
--------------------------------------------------------------------------
CLK - Clock System
--------------------------------------------------------------------------
*/

/* Clock System */
typedef struct CLK_struct
{
register8_t CTRL; /* Control Register */
register8_t PSCTRL; /* Prescaler Control Register */
register8_t LOCK; /* Lock register */
register8_t RTCCTRL; /* RTC Control Register */
} CLK_t;

/*
--------------------------------------------------------------------------
CLK - Clock System
--------------------------------------------------------------------------
*/

/* Power Reduction */
typedef struct PR_struct
{
register8_t PRGEN; /* General Power Reduction */
register8_t PRPA; /* Power Reduction Port A */
register8_t PRPB; /* Power Reduction Port B */
register8_t PRPC; /* Power Reduction Port C */
register8_t PRPD; /* Power Reduction Port D */
register8_t PRPE; /* Power Reduction Port E */
register8_t PRPF; /* Power Reduction Port F */
} PR_t;

/* System Clock Selection */
typedef enum CLK_SCLKSEL_enum
{
CLK_SCLKSEL_RC2M_gc = (0x00 & lt; & lt; 0), /* Internal 2MHz RC Oscillator */
CLK_SCLKSEL_RC32M_gc = (0x01 & lt; & lt; 0), /* Internal 32MHz RC Oscillator */
CLK_SCLKSEL_RC32K_gc = (0x02 & lt; & lt; 0), /* Internal 32kHz RC Oscillator */
CLK_SCLKSEL_XOSC_gc = (0x03 & lt; & lt; 0), /* External Crystal Oscillator or Clock */
CLK_SCLKSEL_PLL_gc = (0x04 & lt; & lt; 0), /* Phase Locked Loop */
} CLK_SCLKSEL_t;

/* Prescaler A Division Factor */
typedef enum CLK_PSADIV_enum
{
CLK_PSADIV_1_gc = (0x00 & lt; & lt; 2), /* Divide by 1 */
CLK_PSADIV_2_gc = (0x01 & lt; & lt; 2), /* Divide by 2 */
CLK_PSADIV_4_gc = (0x03 & lt; & lt; 2), /* Divide by 4 */
CLK_PSADIV_8_gc = (0x05 & lt; & lt; 2), /* Divide by 8 */
CLK_PSADIV_16_gc = (0x07 & lt; & lt; 2), /* Divide by 16 */
CLK_PSADIV_32_gc = (0x09 & lt; & lt; 2), /* Divide by 32 */
CLK_PSADIV_64_gc = (0x0B & lt; & lt; 2), /* Divide by 64 */
CLK_PSADIV_128_gc = (0x0D & lt; & lt; 2), /* Divide by 128 */
CLK_PSADIV_256_gc = (0x0F & lt; & lt; 2), /* Divide by 256 */
CLK_PSADIV_512_gc = (0x11 & lt; & lt; 2), /* Divide by 512 */
} CLK_PSADIV_t;

/* Prescaler B and C Division Factor */
typedef enum CLK_PSBCDIV_enum
{
CLK_PSBCDIV_1_1_gc = (0x00 & lt; & lt; 0), /* Divide B by 1 and C by 1 */
CLK_PSBCDIV_1_2_gc = (0x01 & lt; & lt; 0), /* Divide B by 1 and C by 2 */
CLK_PSBCDIV_4_1_gc = (0x02 & lt; & lt; 0), /* Divide B by 4 and C by 1 */
CLK_PSBCDIV_2_2_gc = (0x03 & lt; & lt; 0), /* Divide B by 2 and C by 2 */
} CLK_PSBCDIV_t;

/* RTC Clock Source */
typedef enum CLK_RTCSRC_enum
{
CLK_RTCSRC_ULP_gc = (0x00 & lt; & lt; 1), /* 1kHz from internal 32kHz ULP */
CLK_RTCSRC_TOSC_gc = (0x01 & lt; & lt; 1), /* 1kHz from 32kHz crystal oscillator on TOSC */
CLK_RTCSRC_RCOSC_gc = (0x02 & lt; & lt; 1), /* 1kHz from internal 32kHz RC oscillator */
CLK_RTCSRC_TOSC32_gc = (0x05 & lt; & lt; 1), /* 32kHz from 32kHz crystal oscillator on TOSC */
} CLK_RTCSRC_t;


/*
--------------------------------------------------------------------------
SLEEP - Sleep Controller
--------------------------------------------------------------------------
*/

/* Sleep Controller */
typedef struct SLEEP_struct
{
register8_t CTRL; /* Control Register */
} SLEEP_t;

/* Sleep Mode */
typedef enum SLEEP_SMODE_enum
{
SLEEP_SMODE_IDLE_gc = (0x00 & lt; & lt; 1), /* Idle mode */
SLEEP_SMODE_PDOWN_gc = (0x02 & lt; & lt; 1), /* Power-down Mode */
SLEEP_SMODE_PSAVE_gc = (0x03 & lt; & lt; 1), /* Power-save Mode */
SLEEP_SMODE_STDBY_gc = (0x06 & lt; & lt; 1), /* Standby Mode */
SLEEP_SMODE_ESTDBY_gc = (0x07 & lt; & lt; 1), /* Extended Standby Mode */
} SLEEP_SMODE_t;


/*
--------------------------------------------------------------------------
OSC - Oscillator
--------------------------------------------------------------------------
*/

/* Oscillator */
typedef struct OSC_struct
{
register8_t CTRL; /* Control Register */
register8_t STATUS; /* Status Register */
register8_t XOSCCTRL; /* External Oscillator Control Register */
register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */
register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */
register8_t PLLCTRL; /* PLL Control REgister */
register8_t DFLLCTRL; /* DFLL Control Register */
} OSC_t;

/* Oscillator Frequency Range */
typedef enum OSC_FRQRANGE_enum
{
OSC_FRQRANGE_04TO2_gc = (0x00 & lt; & lt; 6), /* 0.4 - 2 MHz */
OSC_FRQRANGE_2TO9_gc = (0x01 & lt; & lt; 6), /* 2 - 9 MHz */
OSC_FRQRANGE_9TO12_gc = (0x02 & lt; & lt; 6), /* 9 - 12 MHz */
OSC_FRQRANGE_12TO16_gc = (0x03 & lt; & lt; 6), /* 12 - 16 MHz */
} OSC_FRQRANGE_t;

/* External Oscillator Selection and Startup Time */
typedef enum OSC_XOSCSEL_enum
{
OSC_XOSCSEL_EXTCLK_gc = (0x00 & lt; & lt; 0), /* External Clock - 6 CLK */
OSC_XOSCSEL_32KHz_gc = (0x02 & lt; & lt; 0), /* 32kHz TOSC - 32K CLK */
OSC_XOSCSEL_XTAL_256CLK_gc = (0x03 & lt; & lt; 0), /* 0.4-16MHz XTAL - 256 CLK */
OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07 & lt; & lt; 0), /* 0.4-16MHz XTAL - 1K CLK */
OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B & lt; & lt; 0), /* 0.4-16MHz XTAL - 16K CLK */
} OSC_XOSCSEL_t;

/* PLL Clock Source */
typedef enum OSC_PLLSRC_enum
{
OSC_PLLSRC_RC2M_gc = (0x00 & lt; & lt; 6), /* Internal 2MHz RC Oscillator */
OSC_PLLSRC_RC32M_gc = (0x02 & lt; & lt; 6), /* Internal 32MHz RC Oscillator */
OSC_PLLSRC_XOSC_gc = (0x03 & lt; & lt; 6), /* External Oscillator */
} OSC_PLLSRC_t;


/*
--------------------------------------------------------------------------
DFLL - DFLL
--------------------------------------------------------------------------
*/

/* DFLL */
typedef struct DFLL_struct
{
register8_t CTRL; /* Control Register */
register8_t reserved_0x01;
register8_t CALA; /* Calibration Register A */
register8_t CALB; /* Calibration Register B */
register8_t COMP0; /* Oscillator Compare Register 0 */
register8_t COMP1; /* Oscillator Compare Register 1 */
register8_t COMP2; /* Oscillator Compare Register 2 */
register8_t reserved_0x07;
} DFLL_t;


/*
--------------------------------------------------------------------------
RST - Reset
--------------------------------------------------------------------------
*/

/* Reset */
typedef struct RST_struct
{
register8_t STATUS; /* Status Register */
register8_t CTRL; /* Control Register */
} RST_t;


/*
--------------------------------------------------------------------------
WDT - Watch-Dog Timer
--------------------------------------------------------------------------
*/

/* Watch-Dog Timer */
typedef struct WDT_struct
{
register8_t CTRL; /* Control */
register8_t WINCTRL; /* Windowed Mode Control */
register8_t STATUS; /* Status */
} WDT_t;

/* Period setting */
typedef enum WDT_PER_enum
{
WDT_PER_8CLK_gc = (0x00 & lt; & lt; 2), /* 8 cycles (8ms @ 3.3V) */
WDT_PER_16CLK_gc = (0x01 & lt; & lt; 2), /* 16 cycles (16ms @ 3.3V) */
WDT_PER_32CLK_gc = (0x02 & lt; & lt; 2), /* 32 cycles (32ms @ 3.3V) */
WDT_PER_64CLK_gc = (0x03 & lt; & lt; 2), /* 64 cycles (64ms @ 3.3V) */
WDT_PER_128CLK_gc = (0x04 & lt; & lt; 2), /* 128 cycles (0.125s @ 3.3V) */
WDT_PER_256CLK_gc = (0x05 & lt; & lt; 2), /* 256 cycles (0.25s @ 3.3V) */
WDT_PER_512CLK_gc = (0x06 & lt; & lt; 2), /* 512 cycles (0.5s @ 3.3V) */
WDT_PER_1KCLK_gc = (0x07 & lt; & lt; 2), /* 1K cycles (1s @ 3.3V) */
WDT_PER_2KCLK_gc = (0x08 & lt; & lt; 2), /* 2K cycles (2s @ 3.3V) */
WDT_PER_4KCLK_gc = (0x09 & lt; & lt; 2), /* 4K cycles (4s @ 3.3V) */
WDT_PER_8KCLK_gc = (0x0A & lt; & lt; 2), /* 8K cycles (8s @ 3.3V) */
} WDT_PER_t;

/* Closed window period */
typedef enum WDT_WPER_enum
{
WDT_WPER_8CLK_gc = (0x00 & lt; & lt; 2), /* 8 cycles (8ms @ 3.3V) */
WDT_WPER_16CLK_gc = (0x01 & lt; & lt; 2), /* 16 cycles (16ms @ 3.3V) */
WDT_WPER_32CLK_gc = (0x02 & lt; & lt; 2), /* 32 cycles (32ms @ 3.3V) */
WDT_WPER_64CLK_gc = (0x03 & lt; & lt; 2), /* 64 cycles (64ms @ 3.3V) */
WDT_WPER_128CLK_gc = (0x04 & lt; & lt; 2), /* 128 cycles (0.125s @ 3.3V) */
WDT_WPER_256CLK_gc = (0x05 & lt; & lt; 2), /* 256 cycles (0.25s @ 3.3V) */
WDT_WPER_512CLK_gc = (0x06 & lt; & lt; 2), /* 512 cycles (0.5s @ 3.3V) */
WDT_WPER_1KCLK_gc = (0x07 & lt; & lt; 2), /* 1K cycles (1s @ 3.3V) */
WDT_WPER_2KCLK_gc = (0x08 & lt; & lt; 2), /* 2K cycles (2s @ 3.3V) */
WDT_WPER_4KCLK_gc = (0x09 & lt; & lt; 2), /* 4K cycles (4s @ 3.3V) */
WDT_WPER_8KCLK_gc = (0x0A & lt; & lt; 2), /* 8K cycles (8s @ 3.3V) */
} WDT_WPER_t;


/*
--------------------------------------------------------------------------
MCU - MCU Control
--------------------------------------------------------------------------
*/

/* MCU Control */
typedef struct MCU_struct
{
register8_t DEVID0; /* Device ID byte 0 */
register8_t DEVID1; /* Device ID byte 1 */
register8_t DEVID2; /* Device ID byte 2 */
register8_t REVID; /* Revision ID */
register8_t JTAGUID; /* JTAG User ID */
register8_t reserved_0x05;
register8_t MCUCR; /* MCU Control */
register8_t reserved_0x07;
register8_t EVSYSLOCK; /* Event System Lock */
register8_t AWEXLOCK; /* AWEX Lock */
register8_t reserved_0x0A;
register8_t reserved_0x0B;
} MCU_t;


/*
--------------------------------------------------------------------------
PMIC - Programmable Multi-level Interrupt Controller
--------------------------------------------------------------------------
*/

/* Programmable Multi-level Interrupt Controller */
typedef struct PMIC_struct
{
register8_t STATUS; /* Status Register */
register8_t INTPRI; /* Interrupt Priority */
register8_t CTRL; /* Control Register */
} PMIC_t;


/*
--------------------------------------------------------------------------
DMA - DMA Controller
--------------------------------------------------------------------------
*/

/* DMA Channel */
typedef struct DMA_CH_struct
{
register8_t CTRLA; /* Channel Control */
register8_t CTRLB; /* Channel Control */
register8_t ADDRCTRL; /* Address Control */
register8_t TRIGSRC; /* Channel Trigger Source */
_WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */
register8_t REPCNT; /* Channel Repeat Count */
register8_t reserved_0x07;
register8_t SRCADDR0; /* Channel Source Address 0 */
register8_t SRCADDR1; /* Channel Source Address 1 */
register8_t SRCADDR2; /* Channel Source Address 2 */
register8_t reserved_0x0B;
register8_t DESTADDR0; /* Channel Destination Address 0 */
register8_t DESTADDR1; /* Channel Destination Address 1 */
register8_t DESTADDR2; /* Channel Destination Address 2 */
register8_t reserved_0x0F;
} DMA_CH_t;

/*
--------------------------------------------------------------------------
DMA - DMA Controller
--------------------------------------------------------------------------
*/

/* DMA Controller */
typedef struct DMA_struct
{
register8_t CTRL; /* Control */
register8_t reserved_0x01;
register8_t reserved_0x02;
register8_t INTFLAGS; /* Transfer Interrupt Status */
register8_t STATUS; /* Status */
register8_t reserved_0x05;
_WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */
register8_t reserved_0x08;
register8_t reserved_0x09;
register8_t reserved_0x0A;
register8_t reserved_0x0B;
register8_t reserved_0x0C;
register8_t reserved_0x0D;
register8_t reserved_0x0E;
register8_t reserved_0x0F;
DMA_CH_t CH0; /* DMA Channel 0 */
DMA_CH_t CH1; /* DMA Channel 1 */
DMA_CH_t CH2; /* DMA Channel 2 */
DMA_CH_t CH3; /* DMA Channel 3 */
} DMA_t;

/* Burst mode */
typedef enum DMA_CH_BURSTLEN_enum
{
DMA_CH_BURSTLEN_1BYTE_gc = (0x00 & lt; & lt; 0), /* 1-byte burst mode */
DMA_CH_BURSTLEN_2BYTE_gc = (0x01 & lt; & lt; 0), /* 2-byte burst mode */
DMA_CH_BURSTLEN_4BYTE_gc = (0x02 & lt; & lt; 0), /* 4-byte burst mode */
DMA_CH_BURSTLEN_8BYTE_gc = (0x03 & lt; & lt; 0), /* 8-byte burst mode */
} DMA_CH_BURSTLEN_t;

/* Source address reload mode */
typedef enum DMA_CH_SRCRELOAD_enum
{
DMA_CH_SRCRELOAD_NONE_gc = (0x00 & lt; & lt; 6), /* No reload */
DMA_CH_SRCRELOAD_BLOCK_gc = (0x01 & lt; & lt; 6), /* Reload at end of block */
DMA_CH_SRCRELOAD_BURST_gc = (0x02 & lt; & lt; 6), /* Reload at end of burst */
DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03 & lt; & lt; 6), /* Reload at end of transaction */
} DMA_CH_SRCRELOAD_t;

/* Source addressing mode */
typedef enum DMA_CH_SRCDIR_enum
{
DMA_CH_SRCDIR_FIXED_gc = (0x00 & lt; & lt; 4), /* Fixed */
DMA_CH_SRCDIR_INC_gc = (0x01 & lt; & lt; 4), /* Increment */
DMA_CH_SRCDIR_DEC_gc = (0x02 & lt; & lt; 4), /* Decrement */
} DMA_CH_SRCDIR_t;

/* Destination adress reload mode */
typedef enum DMA_CH_DESTRELOAD_enum
{
DMA_CH_DESTRELOAD_NONE_gc = (0x00 & lt; & lt; 2), /* No reload */
DMA_CH_DESTRELOAD_BLOCK_gc = (0x01 & lt; & lt; 2), /* Reload at end of block */
DMA_CH_DESTRELOAD_BURST_gc = (0x02 & lt; & lt; 2), /* Reload at end of burst */
DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03 & lt; & lt; 2), /* Reload at end of transaction */
} DMA_CH_DESTRELOAD_t;

/* Destination adressing mode */
typedef enum DMA_CH_DESTDIR_enum
{
DMA_CH_DESTDIR_FIXED_gc = (0x00 & lt; & lt; 0), /* Fixed */
DMA_CH_DESTDIR_INC_gc = (0x01 & lt; & lt; 0), /* Increment */
DMA_CH_DESTDIR_DEC_gc = (0x02 & lt; & lt; 0), /* Decrement */
} DMA_CH_DESTDIR_t;

/* Transfer trigger source */
typedef enum DMA_CH_TRIGSRC_enum
{
DMA_CH_TRIGSRC_OFF_gc = (0x00 & lt; & lt; 0), /* Off software triggers only */
DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01 & lt; & lt; 0), /* Event System Channel 0 */
DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02 & lt; & lt; 0), /* Event System Channel 1 */
DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03 & lt; & lt; 0), /* Event System Channel 2 */
DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10 & lt; & lt; 0), /* ADCA Channel 0 */
DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11 & lt; & lt; 0), /* ADCA Channel 1 */
DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12 & lt; & lt; 0), /* ADCA Channel 2 */
DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13 & lt; & lt; 0), /* ADCA Channel 3 */
DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14 & lt; & lt; 0), /* ADCA Channel 0,1,2,3 combined */
DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15 & lt; & lt; 0), /* DACA Channel 0 */
DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16 & lt; & lt; 0), /* DACA Channel 1 */
DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20 & lt; & lt; 0), /* ADCB Channel 0 */
DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21 & lt; & lt; 0), /* ADCB Channel 1 */
DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22 & lt; & lt; 0), /* ADCB Channel 2 */
DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23 & lt; & lt; 0), /* ADCB Channel 3 */
DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24 & lt; & lt; 0), /* ADCB Channel 0,1,2,3 combined */
DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25 & lt; & lt; 0), /* DACB Channel 0 */
DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26 & lt; & lt; 0), /* DACB Channel 1 */
DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40 & lt; & lt; 0), /* Timer/Counter C0 Overflow */
DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41 & lt; & lt; 0), /* Timer/Counter C0 Error */
DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42 & lt; & lt; 0), /* Timer/Counter C0 Compare or Capture A */
DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43 & lt; & lt; 0), /* Timer/Counter C0 Compare or Capture B */
DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44 & lt; & lt; 0), /* Timer/Counter C0 Compare or Capture C */
DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45 & lt; & lt; 0), /* Timer/Counter C0 Compare or Capture D */
DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46 & lt; & lt; 0), /* Timer/Counter C1 Overflow */
DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47 & lt; & lt; 0), /* Timer/Counter C1 Error */
DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48 & lt; & lt; 0), /* Timer/Counter C1 Compare or Capture A */
DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49 & lt; & lt; 0), /* Timer/Counter C1 Compare or Capture B */
DMA_CH_TRIGSRC_SPIC_gc = (0x4A & lt; & lt; 0), /* SPI C Transfer Complete */
DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B & lt; & lt; 0), /* USART C0 Receive Complete */
DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C & lt; & lt; 0), /* USART C0 Data Register Empty */
DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E & lt; & lt; 0), /* USART C1 Receive Complete */
DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F & lt; & lt; 0), /* USART C1 Data Register Empty */
DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60 & lt; & lt; 0), /* Timer/Counter D0 Overflow */
DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61 & lt; & lt; 0), /* Timer/Counter D0 Error */
DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62 & lt; & lt; 0), /* Timer/Counter D0 Compare or Capture A */
DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63 & lt; & lt; 0), /* Timer/Counter D0 Compare or Capture B */
DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64 & lt; & lt; 0), /* Timer/Counter D0 Compare or Capture C */
DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65 & lt; & lt; 0), /* Timer/Counter D0 Compare or Capture D */
DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66 & lt; & lt; 0), /* Timer/Counter D1 Overflow */
DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67 & lt; & lt; 0), /* Timer/Counter D1 Error */
DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68 & lt; & lt; 0), /* Timer/Counter D1 Compare or Capture A */
DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69 & lt; & lt; 0), /* Timer/Counter D1 Compare or Capture B */
DMA_CH_TRIGSRC_SPID_gc = (0x6A & lt; & lt; 0), /* SPI D Transfer Complete */
DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B & lt; & lt; 0), /* USART D0 Receive Complete */
DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C & lt; & lt; 0), /* USART D0 Data Register Empty */
DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E & lt; & lt; 0), /* USART D1 Receive Complete */
DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F & lt; & lt; 0), /* USART D1 Data Register Empty */
DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80 & lt; & lt; 0), /* Timer/Counter E0 Overflow */
DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81 & lt; & lt; 0), /* Timer/Counter E0 Error */
DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82 & lt; & lt; 0), /* Timer/Counter E0 Compare or Capture A */
DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83 & lt; & lt; 0), /* Timer/Counter E0 Compare or Capture B */
DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84 & lt; & lt; 0), /* Timer/Counter E0 Compare or Capture C */
DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85 & lt; & lt; 0), /* Timer/Counter E0 Compare or Capture D */
DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86 & lt; & lt; 0), /* Timer/Counter E1 Overflow */
DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87 & lt; & lt; 0), /* Timer/Counter E1 Error */
DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88 & lt; & lt; 0), /* Timer/Counter E1 Compare or Capture A */
DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89 & lt; & lt; 0), /* Timer/Counter E1 Compare or Capture B */
DMA_CH_TRIGSRC_SPIE_gc = (0x8A & lt; & lt; 0), /* SPI E Transfer Complete */
DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B & lt; & lt; 0), /* USART E0 Receive Complete */
DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C & lt; & lt; 0), /* USART E0 Data Register Empty */
DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E & lt; & lt; 0), /* USART E1 Receive Complete */
DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F & lt; & lt; 0), /* USART E1 Data Register Empty */
DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0 & lt; & lt; 0), /* Timer/Counter F0 Overflow */
DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1 & lt; & lt; 0), /* Timer/Counter F0 Error */
DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2 & lt; & lt; 0), /* Timer/Counter F0 Compare or Capture A */
DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3 & lt; & lt; 0), /* Timer/Counter F0 Compare or Capture B */
DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4 & lt; & lt; 0), /* Timer/Counter F0 Compare or Capture C */
DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5 & lt; & lt; 0), /* Timer/Counter F0 Compare or Capture D */
DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6 & lt; & lt; 0), /* Timer/Counter F1 Overflow */
DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7 & lt; & lt; 0), /* Timer/Counter F1 Error */
DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8 & lt; & lt; 0), /* Timer/Counter F1 Compare or Capture A */
DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9 & lt; & lt; 0), /* Timer/Counter F1 Compare or Capture B */
DMA_CH_TRIGSRC_SPIF_gc = (0xAA & lt; & lt; 0), /* SPI F Transfer Complete */
DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB & lt; & lt; 0), /* USART F0 Receive Complete */
DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC & lt; & lt; 0), /* USART F0 Data Register Empty */
DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE & lt; & lt; 0), /* USART F1 Receive Complete */
DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF & lt; & lt; 0), /* USART F1 Data Register Empty */
} DMA_CH_TRIGSRC_t;

/* Double buffering mode */
typedef enum DMA_DBUFMODE_enum
{
DMA_DBUFMODE_DISABLED_gc = (0x00 & lt; & lt; 2), /* Double buffering disabled */
DMA_DBUFMODE_CH01_gc = (0x01 & lt; & lt; 2), /* Double buffering enabled on channel 0/1 */
DMA_DBUFMODE_CH23_gc = (0x02 & lt; & lt; 2), /* Double buffering enabled on channel 2/3 */
DMA_DBUFMODE_CH01CH23_gc = (0x03 & lt; & lt; 2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */
} DMA_DBUFMODE_t;

/* Priority mode */
typedef enum DMA_PRIMODE_enum
{
DMA_PRIMODE_RR0123_gc = (0x00 & lt; & lt; 0), /* Round Robin */
DMA_PRIMODE_CH0RR123_gc = (0x01 & lt; & lt; 0), /* Channel 0 & gt; Round Robin on channel 1/2/3 */
DMA_PRIMODE_CH01RR23_gc = (0x02 & lt; & lt; 0), /* Channel 0 & gt; channel 1 & gt; Round Robin on channel 2/3 */
DMA_PRIMODE_CH0123_gc = (0x03 & lt; & lt; 0), /* Channel 0 & gt; channel 1 & gt; channel 2 & gt; channel 3 */
} DMA_PRIMODE_t;

/* Interrupt level */
typedef enum DMA_CH_ERRINTLVL_enum
{
DMA_CH_ERRINTLVL_OFF_gc = (0x00 & lt; & lt; 2), /* Interrupt disabled */
DMA_CH_ERRINTLVL_LO_gc = (0x01 & lt; & lt; 2), /* Low level */
DMA_CH_ERRINTLVL_MED_gc = (0x02 & lt; & lt; 2), /* Medium level */
DMA_CH_ERRINTLVL_HI_gc = (0x03 & lt; & lt; 2), /* High level */
} DMA_CH_ERRINTLVL_t;

/* Interrupt level */
typedef enum DMA_CH_TRNINTLVL_enum
{
DMA_CH_TRNINTLVL_OFF_gc = (0x00 & lt; & lt; 0), /* Interrupt disabled */
DMA_CH_TRNINTLVL_LO_gc = (0x01 & lt; & lt; 0), /* Low level */
DMA_CH_TRNINTLVL_MED_gc = (0x02 & lt; & lt; 0), /* Medium level */
DMA_CH_TRNINTLVL_HI_gc = (0x03 & lt; & lt; 0), /* High level */
} DMA_CH_TRNINTLVL_t;


/*
--------------------------------------------------------------------------
EVSYS - Event System
--------------------------------------------------------------------------
*/

/* Event System */
typedef struct EVSYS_struct
{
register8_t CH0MUX; /* Event Channel 0 Multiplexer */
register8_t CH1MUX; /* Event Channel 1 Multiplexer */
register8_t CH2MUX; /* Event Channel 2 Multiplexer */
register8_t CH3MUX; /* Event Channel 3 Multiplexer */
register8_t CH4MUX; /* Event Channel 4 Multiplexer */
register8_t CH5MUX; /* Event Channel 5 Multiplexer */
register8_t CH6MUX; /* Event Channel 6 Multiplexer */
register8_t CH7MUX; /* Event Channel 7 Multiplexer */
register8_t CH0CTRL; /* Channel 0 Control Register */
register8_t CH1CTRL; /* Channel 1 Control Register */
register8_t CH2CTRL; /* Channel 2 Control Register */
register8_t CH3CTRL; /* Channel 3 Control Register */
register8_t CH4CTRL; /* Channel 4 Control Register */
register8_t CH5CTRL; /* Channel 5 Control Register */
register8_t CH6CTRL; /* Channel 6 Control Register */
register8_t CH7CTRL; /* Channel 7 Control Register */
register8_t STROBE; /* Event Strobe */
register8_t DATA; /* Event Data */
} EVSYS_t;

/* Quadrature Decoder Index Recognition Mode */
typedef enum EVSYS_QDIRM_enum
{
EVSYS_QDIRM_00_gc = (0x00 & lt; & lt; 5), /* QDPH0 = 0, QDPH90 = 0 */
EVSYS_QDIRM_01_gc = (0x01 & lt; & lt; 5), /* QDPH0 = 0, QDPH90 = 1 */
EVSYS_QDIRM_10_gc = (0x02 & lt; & lt; 5), /* QDPH0 = 1, QDPH90 = 0 */
EVSYS_QDIRM_11_gc = (0x03 & lt; & lt; 5), /* QDPH0 = 1, QDPH90 = 1 */
} EVSYS_QDIRM_t;

/* Digital filter coefficient */
typedef enum EVSYS_DIGFILT_enum
{
EVSYS_DIGFILT_1SAMPLE_gc = (0x00 & lt; & lt; 0), /* 1 SAMPLE */
EVSYS_DIGFILT_2SAMPLES_gc = (0x01 & lt; & lt; 0), /* 2 SAMPLES */
EVSYS_DIGFILT_3SAMPLES_gc = (0x02 & lt; & lt; 0), /* 3 SAMPLES */
EVSYS_DIGFILT_4SAMPLES_gc = (0x03 & lt; & lt; 0), /* 4 SAMPLES */
EVSYS_DIGFILT_5SAMPLES_gc = (0x04 & lt; & lt; 0), /* 5 SAMPLES */
EVSYS_DIGFILT_6SAMPLES_gc = (0x05 & lt; & lt; 0), /* 6 SAMPLES */
EVSYS_DIGFILT_7SAMPLES_gc = (0x06 & lt; & lt; 0), /* 7 SAMPLES */
EVSYS_DIGFILT_8SAMPLES_gc = (0x07 & lt; & lt; 0), /* 8 SAMPLES */
} EVSYS_DIGFILT_t;

/* Event Channel multiplexer input selection */
typedef enum EVSYS_CHMUX_enum
{
EVSYS_CHMUX_OFF_gc = (0x00 & lt; & lt; 0), /* Off */
EVSYS_CHMUX_RTC_OVF_gc = (0x08 & lt; & lt; 0), /* RTC Overflow */
EVSYS_CHMUX_RTC_CMP_gc = (0x09 & lt; & lt; 0), /* RTC Compare Match */
EVSYS_CHMUX_ACA_CH0_gc = (0x10 & lt; & lt; 0), /* Analog Comparator A Channel 0 */
EVSYS_CHMUX_ACA_CH1_gc = (0x11 & lt; & lt; 0), /* Analog Comparator A Channel 1 */
EVSYS_CHMUX_ACA_WIN_gc = (0x12 & lt; & lt; 0), /* Analog Comparator A Window */
EVSYS_CHMUX_ACB_CH0_gc = (0x13 & lt; & lt; 0), /* Analog Comparator B Channel 0 */
EVSYS_CHMUX_ACB_CH1_gc = (0x14 & lt; & lt; 0), /* Analog Comparator B Channel 1 */
EVSYS_CHMUX_ACB_WIN_gc = (0x15 & lt; & lt; 0), /* Analog Comparator B Window */
EVSYS_CHMUX_ADCA_CH0_gc = (0x20 & lt; & lt; 0), /* ADC A Channel 0 */
EVSYS_CHMUX_ADCA_CH1_gc = (0x21 & lt; & lt; 0), /* ADC A Channel 1 */
EVSYS_CHMUX_ADCA_CH2_gc = (0x22 & lt; & lt; 0), /* ADC A Channel 2 */
EVSYS_CHMUX_ADCA_CH3_gc = (0x23 & lt; & lt; 0), /* ADC A Channel 3 */
EVSYS_CHMUX_ADCB_CH0_gc = (0x24 & lt; & lt; 0), /* ADC B Channel 0 */
EVSYS_CHMUX_ADCB_CH1_gc = (0x25 & lt; & lt; 0), /* ADC B Channel 1 */
EVSYS_CHMUX_ADCB_CH2_gc = (0x26 & lt; & lt; 0), /* ADC B Channel 2 */
EVSYS_CHMUX_ADCB_CH3_gc = (0x27 & lt; & lt; 0), /* ADC B Channel 3 */
EVSYS_CHMUX_PORTA_PIN0_gc = (0x50 & lt; & lt; 0), /* Port A, Pin0 */
EVSYS_CHMUX_PORTA_PIN1_gc = (0x51 & lt; & lt; 0), /* Port A, Pin1 */
EVSYS_CHMUX_PORTA_PIN2_gc = (0x52 & lt; & lt; 0), /* Port A, Pin2 */
EVSYS_CHMUX_PORTA_PIN3_gc = (0x53 & lt; & lt; 0), /* Port A, Pin3 */
EVSYS_CHMUX_PORTA_PIN4_gc = (0x54 & lt; & lt; 0), /* Port A, Pin4 */
EVSYS_CHMUX_PORTA_PIN5_gc = (0x55 & lt; & lt; 0), /* Port A, Pin5 */
EVSYS_CHMUX_PORTA_PIN6_gc = (0x56 & lt; & lt; 0), /* Port A, Pin6 */
EVSYS_CHMUX_PORTA_PIN7_gc = (0x57 & lt; & lt; 0), /* Port A, Pin7 */
EVSYS_CHMUX_PORTB_PIN0_gc = (0x58 & lt; & lt; 0), /* Port B, Pin0 */
EVSYS_CHMUX_PORTB_PIN1_gc = (0x59 & lt; & lt; 0), /* Port B, Pin1 */
EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A & lt; & lt; 0), /* Port B, Pin2 */
EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B & lt; & lt; 0), /* Port B, Pin3 */
EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C & lt; & lt; 0), /* Port B, Pin4 */
EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D & lt; & lt; 0), /* Port B, Pin5 */
EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E & lt; & lt; 0), /* Port B, Pin6 */
EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F & lt; & lt; 0), /* Port B, Pin7 */
EVSYS_CHMUX_PORTC_PIN0_gc = (0x60 & lt; & lt; 0), /* Port C, Pin0 */
EVSYS_CHMUX_PORTC_PIN1_gc = (0x61 & lt; & lt; 0), /* Port C, Pin1 */
EVSYS_CHMUX_PORTC_PIN2_gc = (0x62 & lt; & lt; 0), /* Port C, Pin2 */
EVSYS_CHMUX_PORTC_PIN3_gc = (0x63 & lt; & lt; 0), /* Port C, Pin3 */
EVSYS_CHMUX_PORTC_PIN4_gc = (0x64 & lt; & lt; 0), /* Port C, Pin4 */
EVSYS_CHMUX_PORTC_PIN5_gc = (0x65 & lt; & lt; 0), /* Port C, Pin5 */
EVSYS_CHMUX_PORTC_PIN6_gc = (0x66 & lt; & lt; 0), /* Port C, Pin6 */
EVSYS_CHMUX_PORTC_PIN7_gc = (0x67 & lt; & lt; 0), /* Port C, Pin7 */
EVSYS_CHMUX_PORTD_PIN0_gc = (0x68 & lt; & lt; 0), /* Port D, Pin0 */
EVSYS_CHMUX_PORTD_PIN1_gc = (0x69 & lt; & lt; 0), /* Port D, Pin1 */
EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A & lt; & lt; 0), /* Port D, Pin2 */
EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B & lt; & lt; 0), /* Port D, Pin3 */
EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C & lt; & lt; 0), /* Port D, Pin4 */
EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D & lt; & lt; 0), /* Port D, Pin5 */
EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E & lt; & lt; 0), /* Port D, Pin6 */
EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F & lt; & lt; 0), /* Port D, Pin7 */
EVSYS_CHMUX_PORTE_PIN0_gc = (0x70 & lt; & lt; 0), /* Port E, Pin0 */
EVSYS_CHMUX_PORTE_PIN1_gc = (0x71 & lt; & lt; 0), /* Port E, Pin1 */
EVSYS_CHMUX_PORTE_PIN2_gc = (0x72 & lt; & lt; 0), /* Port E, Pin2 */
EVSYS_CHMUX_PORTE_PIN3_gc = (0x73 & lt; & lt; 0), /* Port E, Pin3 */
EVSYS_CHMUX_PORTE_PIN4_gc = (0x74 & lt; & lt; 0), /* Port E, Pin4 */
EVSYS_CHMUX_PORTE_PIN5_gc = (0x75 & lt; & lt; 0), /* Port E, Pin5 */
EVSYS_CHMUX_PORTE_PIN6_gc = (0x76 & lt; & lt; 0), /* Port E, Pin6 */
EVSYS_CHMUX_PORTE_PIN7_gc = (0x77 & lt; & lt; 0), /* Port E, Pin7 */
EVSYS_CHMUX_PORTF_PIN0_gc = (0x78 & lt; & lt; 0), /* Port F, Pin0 */
EVSYS_CHMUX_PORTF_PIN1_gc = (0x79 & lt; & lt; 0), /* Port F, Pin1 */
EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A & lt; & lt; 0), /* Port F, Pin2 */
EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B & lt; & lt; 0), /* Port F, Pin3 */
EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C & lt; & lt; 0), /* Port F, Pin4 */
EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D & lt; & lt; 0), /* Port F, Pin5 */
EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E & lt; & lt; 0), /* Port F, Pin6 */
EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F & lt; & lt; 0), /* Port F, Pin7 */
EVSYS_CHMUX_PRESCALER_1_gc = (0x80 & lt; & lt; 0), /* Prescaler, divide by 1 */
EVSYS_CHMUX_PRESCALER_2_gc = (0x81 & lt; & lt; 0), /* Prescaler, divide by 2 */
EVSYS_CHMUX_PRESCALER_4_gc = (0x82 & lt; & lt; 0), /* Prescaler, divide by 4 */
EVSYS_CHMUX_PRESCALER_8_gc = (0x83 & lt; & lt; 0), /* Prescaler, divide by 8 */
EVSYS_CHMUX_PRESCALER_16_gc = (0x84 & lt; & lt; 0), /* Prescaler, divide by 16 */
EVSYS_CHMUX_PRESCALER_32_gc = (0x85 & lt; & lt; 0), /* Prescaler, divide by 32 */
EVSYS_CHMUX_PRESCALER_64_gc = (0x86 & lt; & lt; 0), /* Prescaler, divide by 64 */
EVSYS_CHMUX_PRESCALER_128_gc = (0x87 & lt; & lt; 0), /* Prescaler, divide by 128 */
EVSYS_CHMUX_PRESCALER_256_gc = (0x88 & lt; & lt; 0), /* Prescaler, divide by 256 */
EVSYS_CHMUX_PRESCALER_512_gc = (0x89 & lt; & lt; 0), /* Prescaler, divide by 512 */
EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A & lt; & lt; 0), /* Prescaler, divide by 1024 */
EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B & lt; & lt; 0), /* Prescaler, divide by 2048 */
EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C & lt; & lt; 0), /* Prescaler, divide by 4096 */
EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D & lt; & lt; 0), /* Prescaler, divide by 8192 */
EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E & lt; & lt; 0), /* Prescaler, divide by 16384 */
EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F & lt; & lt; 0), /* Prescaler, divide by 32768 */
EVSYS_CHMUX_TCC0_OVF_gc = (0xC0 & lt; & lt; 0), /* Timer/Counter C0 Overflow */
EVSYS_CHMUX_TCC0_ERR_gc = (0xC1 & lt; & lt; 0), /* Timer/Counter C0 Error */
EVSYS_CHMUX_TCC0_CCA_gc = (0xC4 & lt; & lt; 0), /* Timer/Counter C0 Compare or Capture A */
EVSYS_CHMUX_TCC0_CCB_gc = (0xC5 & lt; & lt; 0), /* Timer/Counter C0 Compare or Capture B */
EVSYS_CHMUX_TCC0_CCC_gc = (0xC6 & lt; & lt; 0), /* Timer/Counter C0 Compare or Capture C */
EVSYS_CHMUX_TCC0_CCD_gc = (0xC7 & lt; & lt; 0), /* Timer/Counter C0 Compare or Capture D */
EVSYS_CHMUX_TCC1_OVF_gc = (0xC8 & lt; & lt; 0), /* Timer/Counter C1 Overflow */
EVSYS_CHMUX_TCC1_ERR_gc = (0xC9 & lt; & lt; 0), /* Timer/Counter C1 Error */
EVSYS_CHMUX_TCC1_CCA_gc = (0xCC & lt; & lt; 0), /* Timer/Counter C1 Compare or Capture A */
EVSYS_CHMUX_TCC1_CCB_gc = (0xCD & lt; & lt; 0), /* Timer/Counter C1 Compare or Capture B */
EVSYS_CHMUX_TCD0_OVF_gc = (0xD0 & lt; & lt; 0), /* Timer/Counter D0 Overflow */
EVSYS_CHMUX_TCD0_ERR_gc = (0xD1 & lt; & lt; 0), /* Timer/Counter D0 Error */
EVSYS_CHMUX_TCD0_CCA_gc = (0xD4 & lt; & lt; 0), /* Timer/Counter D0 Compare or Capture A */
EVSYS_CHMUX_TCD0_CCB_gc = (0xD5 & lt; & lt; 0), /* Timer/Counter D0 Compare or Capture B */
EVSYS_CHMUX_TCD0_CCC_gc = (0xD6 & lt; & lt; 0), /* Timer/Counter D0 Compare or Capture C */
EVSYS_CHMUX_TCD0_CCD_gc = (0xD7 & lt; & lt; 0), /* Timer/Counter D0 Compare or Capture D */
EVSYS_CHMUX_TCD1_OVF_gc = (0xD8 & lt; & lt; 0), /* Timer/Counter D1 Overflow */
EVSYS_CHMUX_TCD1_ERR_gc = (0xD9 & lt; & lt; 0), /* Timer/Counter D1 Error */
EVSYS_CHMUX_TCD1_CCA_gc = (0xDC & lt; & lt; 0), /* Timer/Counter D1 Compare or Capture A */
EVSYS_CHMUX_TCD1_CCB_gc = (0xDD & lt; & lt; 0), /* Timer/Counter D1 Compare or Capture B */
EVSYS_CHMUX_TCE0_OVF_gc = (0xE0 & lt; & lt; 0), /* Timer/Counter E0 Overflow */
EVSYS_CHMUX_TCE0_ERR_gc = (0xE1 & lt; & lt; 0), /* Timer/Counter E0 Error */
EVSYS_CHMUX_TCE0_CCA_gc = (0xE4 & lt; & lt; 0), /* Timer/Counter E0 Compare or Capture A */
EVSYS_CHMUX_TCE0_CCB_gc = (0xE5 & lt; & lt; 0), /* Timer/Counter E0 Compare or Capture B */
EVSYS_CHMUX_TCE0_CCC_gc = (0xE6 & lt; & lt; 0), /* Timer/Counter E0 Compare or Capture C */
EVSYS_CHMUX_TCE0_CCD_gc = (0xE7 & lt; & lt; 0), /* Timer/Counter E0 Compare or Capture D */
EVSYS_CHMUX_TCE1_OVF_gc = (0xE8 & lt; & lt; 0), /* Timer/Counter E1 Overflow */
EVSYS_CHMUX_TCE1_ERR_gc = (0xE9 & lt; & lt; 0), /* Timer/Counter E1 Error */
EVSYS_CHMUX_TCE1_CCA_gc = (0xEC & lt; & lt; 0), /* Timer/Counter E1 Compare or Capture A */
EVSYS_CHMUX_TCE1_CCB_gc = (0xED & lt; & lt; 0), /* Timer/Counter E1 Compare or Capture B */
EVSYS_CHMUX_TCF0_OVF_gc = (0xF0 & lt; & lt; 0), /* Timer/Counter F0 Overflow */
EVSYS_CHMUX_TCF0_ERR_gc = (0xF1 & lt; & lt; 0), /* Timer/Counter F0 Error */
EVSYS_CHMUX_TCF0_CCA_gc = (0xF4 & lt; & lt; 0), /* Timer/Counter F0 Compare or Capture A */
EVSYS_CHMUX_TCF0_CCB_gc = (0xF5 & lt; & lt; 0), /* Timer/Counter F0 Compare or Capture B */
EVSYS_CHMUX_TCF0_CCC_gc = (0xF6 & lt; & lt; 0), /* Timer/Counter F0 Compare or Capture C */
EVSYS_CHMUX_TCF0_CCD_gc = (0xF7 & lt; & lt; 0), /* Timer/Counter F0 Compare or Capture D */
EVSYS_CHMUX_TCF1_OVF_gc = (0xF8 & lt; & lt; 0), /* Timer/Counter F1 Overflow */
EVSYS_CHMUX_TCF1_ERR_gc = (0xF9 & lt; & lt; 0), /* Timer/Counter F1 Error */
EVSYS_CHMUX_TCF1_CCA_gc = (0xFC & lt; & lt; 0), /* Timer/Counter F1 Compare or Capture A */
EVSYS_CHMUX_TCF1_CCB_gc = (0xFD & lt; & lt; 0), /* Timer/Counter F1 Compare or Capture B */
} EVSYS_CHMUX_t;


/*
--------------------------------------------------------------------------
NVM - Non Volatile Memory Controller
--------------------------------------------------------------------------
*/

/* Non-volatile Memory Controller */
typedef struct NVM_struct
{
register8_t ADDR0; /* Address Register 0 */
register8_t ADDR1; /* Address Register 1 */
register8_t ADDR2; /* Address Register 2 */
register8_t reserved_0x03;
register8_t DATA0; /* Data Register 0 */
register8_t DATA1; /* Data Register 1 */
register8_t DATA2; /* Data Register 2 */
register8_t reserved_0x07;
register8_t reserved_0x08;
register8_t reserved_0x09;
register8_t CMD; /* Command */
register8_t CTRLA; /* Control Register A */
register8_t CTRLB; /* Control Register B */
register8_t INTCTRL; /* Interrupt Control */
register8_t reserved_0x0E;
register8_t STATUS; /* Status */
register8_t LOCKBITS; /* Lock Bits */
} NVM_t;

/*
--------------------------------------------------------------------------
NVM - Non Volatile Memory Controller
--------------------------------------------------------------------------
*/

/* Lock Bits */
typedef struct NVM_LOCKBITS_struct
{
register8_t LOCKBITS; /* Lock Bits */
} NVM_LOCKBITS_t;

/*
--------------------------------------------------------------------------
NVM - Non Volatile Memory Controller
--------------------------------------------------------------------------
*/

/* Fuses */
typedef struct NVM_FUSES_struct
{
register8_t FUSEBYTE0; /* JTAG User ID */
register8_t FUSEBYTE1; /* Watchdog Configuration */
register8_t FUSEBYTE2; /* Reset Configuration */
register8_t reserved_0x03;
register8_t FUSEBYTE4; /* Start-up Configuration */
register8_t FUSEBYTE5; /* EESAVE and BOD Level */
} NVM_FUSES_t;

/*
--------------------------------------------------------------------------
NVM - Non Volatile Memory Controller
--------------------------------------------------------------------------
*/

/* Production Signatures */
typedef struct NVM_PROD_SIGNATURES_struct
{
register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */
register8_t reserved_0x01;
register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */
register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */
register8_t reserved_0x04;
register8_t reserved_0x05;
register8_t reserved_0x06;
register8_t reserved_0x07;
register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */
register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */
register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */
register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */
register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */
register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */
register8_t reserved_0x0E;
register8_t reserved_0x0F;
register8_t WAFNUM; /* Wafer Number */
register8_t reserved_0x11;
register8_t COORDX0; /* Wafer Coordinate X Byte 0 */
register8_t COORDX1; /* Wafer Coordinate X Byte 1 */
register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */
register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */
register8_t reserved_0x16;
register8_t reserved_0x17;
register8_t reserved_0x18;
register8_t reserved_0x19;
register8_t reserved_0x1A;
register8_t reserved_0x1B;
register8_t reserved_0x1C;
register8_t reserved_0x1D;
register8_t reserved_0x1E;
register8_t reserved_0x1F;
register8_t ADCACAL0; /* ADCA Calibration Byte 0 */
register8_t ADCACAL1; /* ADCA Calibration Byte 1 */
register8_t reserved_0x22;
register8_t reserved_0x23;
register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */
register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */
register8_t reserved_0x26;
register8_t reserved_0x27;
register8_t reserved_0x28;
register8_t reserved_0x29;
register8_t reserved_0x2A;
register8_t reserved_0x2B;
register8_t reserved_0x2C;
register8_t reserved_0x2D;
register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */
register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */
register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */
register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */
register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */
register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */
register8_t reserved_0x34;
register8_t reserved_0x35;
register8_t reserved_0x36;
register8_t reserved_0x37;
register8_t reserved_0x38;
register8_t reserved_0x39;
register8_t reserved_0x3A;
register8_t reserved_0x3B;
register8_t reserved_0x3C;
register8_t reserved_0x3D;
register8_t reserved_0x3E;
} NVM_PROD_SIGNATURES_t;

/* NVM Command */
typedef enum NVM_CMD_enum
{
NVM_CMD_NO_OPERATION_gc = (0x00 & lt; & lt; 0), /* Noop/Ordinary LPM */
NVM_CMD_READ_CALIB_ROW_gc = (0x02 & lt; & lt; 0), /* Read calibration row */
NVM_CMD_READ_USER_SIG_ROW_gc = (0x01 & lt; & lt; 0), /* Read user signature row */
NVM_CMD_READ_EEPROM_gc = (0x06 & lt; & lt; 0), /* Read EEPROM */
NVM_CMD_READ_FUSES_gc = (0x07 & lt; & lt; 0), /* Read fuse byte */
NVM_CMD_WRITE_LOCK_BITS_gc = (0x08 & lt; & lt; 0), /* Write lock bits */
NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18 & lt; & lt; 0), /* Erase user signature row */
NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A & lt; & lt; 0), /* Write user signature row */
NVM_CMD_ERASE_APP_gc = (0x20 & lt; & lt; 0), /* Erase Application Section */
NVM_CMD_ERASE_APP_PAGE_gc = (0x22 & lt; & lt; 0), /* Erase Application Section page */
NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23 & lt; & lt; 0), /* Load Flash page buffer */
NVM_CMD_WRITE_APP_PAGE_gc = (0x24 & lt; & lt; 0), /* Write Application Section page */
NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25 & lt; & lt; 0), /* Erase-and-write Application Section page */
NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26 & lt; & lt; 0), /* Erase/flush Flash page buffer */
NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A & lt; & lt; 0), /* Erase Boot Section page */
NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C & lt; & lt; 0), /* Write Boot Section page */
NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D & lt; & lt; 0), /* Erase-and-write Boot Section page */
NVM_CMD_ERASE_EEPROM_gc = (0x30 & lt; & lt; 0), /* Erase EEPROM */
NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32 & lt; & lt; 0), /* Erase EEPROM page */
NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33 & lt; & lt; 0), /* Load EEPROM page buffer */
NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34 & lt; & lt; 0), /* Write EEPROM page */
NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35 & lt; & lt; 0), /* Erase-and-write EEPROM page */
NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36 & lt; & lt; 0), /* Erase/flush EEPROM page buffer */
NVM_CMD_APP_CRC_gc = (0x38 & lt; & lt; 0), /* Generate Application section CRC */
NVM_CMD_BOOT_CRC_gc = (0x39 & lt; & lt; 0), /* Generate Boot Section CRC */
NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A & lt; & lt; 0), /* Generate Flash Range CRC */
} NVM_CMD_t;

/* SPM ready interrupt level */
typedef enum NVM_SPMLVL_enum
{
NVM_SPMLVL_OFF_gc = (0x00 & lt; & lt; 2), /* Interrupt disabled */
NVM_SPMLVL_LO_gc = (0x01 & lt; & lt; 2), /* Low level */
NVM_SPMLVL_MED_gc = (0x02 & lt; & lt; 2), /* Medium level */
NVM_SPMLVL_HI_gc = (0x03 & lt; & lt; 2), /* High level */
} NVM_SPMLVL_t;

/* EEPROM ready interrupt level */
typedef enum NVM_EELVL_enum
{
NVM_EELVL_OFF_gc = (0x00 & lt; & lt; 0), /* Interrupt disabled */
NVM_EELVL_LO_gc = (0x01 & lt; & lt; 0), /* Low level */
NVM_EELVL_MED_gc = (0x02 & lt; & lt; 0), /* Medium level */
NVM_EELVL_HI_gc = (0x03 & lt; & lt; 0), /* High level */
} NVM_EELVL_t;

/* Boot lock bits - boot setcion */
typedef enum NVM_BLBB_enum
{
NVM_BLBB_NOLOCK_gc = (0x03 & lt; & lt; 6), /* No locks */
NVM_BLBB_WLOCK_gc = (0x02 & lt; & lt; 6), /* Write not allowed */
NVM_BLBB_RLOCK_gc = (0x01 & lt; & lt; 6), /* Read not allowed */
NVM_BLBB_RWLOCK_gc = (0x00 & lt; & lt; 6), /* Read and write not allowed */
} NVM_BLBB_t;

/* Boot lock bits - application section */
typedef enum NVM_BLBA_enum
{
NVM_BLBA_NOLOCK_gc = (0x03 & lt; & lt; 4), /* No locks */
NVM_BLBA_WLOCK_gc = (0x02 & lt; & lt; 4), /* Write not allowed */
NVM_BLBA_RLOCK_gc = (0x01 & lt; & lt; 4), /* Read not allowed */
NVM_BLBA_RWLOCK_gc = (0x00 & lt; & lt; 4), /* Read and write not allowed */
} NVM_BLBA_t;

/* Boot lock bits - application table section */
typedef enum NVM_BLBAT_enum
{
NVM_BLBAT_NOLOCK_gc = (0x03 & lt; & lt; 2), /* No locks */
NVM_BLBAT_WLOCK_gc = (0x02 & lt; & lt; 2), /* Write not allowed */
NVM_BLBAT_RLOCK_gc = (0x01 & lt; & lt; 2), /* Read not allowed */
NVM_BLBAT_RWLOCK_gc = (0x00 & lt; & lt; 2), /* Read and write not allowed */
} NVM_BLBAT_t;

/* Lock bits */
typedef enum NVM_LB_enum
{
NVM_LB_NOLOCK_gc = (0x03 & lt; & lt; 0), /* No locks */
NVM_LB_WLOCK_gc = (0x02 & lt; & lt; 0), /* Write not allowed */
NVM_LB_RWLOCK_gc = (0x00 & lt; & lt; 0), /* Read and write not allowed */
} NVM_LB_t;

/* Boot Loader Section Reset Vector */
typedef enum BOOTRST_enum
{
BOOTRST_BOOTLDR_gc = (0x00 & lt; & lt; 6), /* Boot Loader Reset */
BOOTRST_APPLICATION_gc = (0x01 & lt; & lt; 6), /* Application Reset */
} BOOTRST_t;

/* BOD operation */
typedef enum BOD_enum
{
BOD_INSAMPLEDMODE_gc = (0x01 & lt; & lt; 2), /* BOD enabled in sampled mode */
BOD_CONTINOUSLY_gc = (0x02 & lt; & lt; 2), /* BOD enabled continuously */
BOD_DISABLED_gc = (0x03 & lt; & lt; 2), /* BOD Disabled */
} BOD_t;

/* Watchdog (Window) Timeout Period */
typedef enum WD_enum
{
WD_8CLK_gc = (0x00 & lt; & lt; 4), /* 8 cycles (8ms @ 3.3V) */
WD_16CLK_gc = (0x01 & lt; & lt; 4), /* 16 cycles (16ms @ 3.3V) */
WD_32CLK_gc = (0x02 & lt; & lt; 4), /* 32 cycles (32ms @ 3.3V) */
WD_64CLK_gc = (0x03 & lt; & lt; 4), /* 64 cycles (64ms @ 3.3V) */
WD_128CLK_gc = (0x04 & lt; & lt; 4), /* 128 cycles (0.125s @ 3.3V) */
WD_256CLK_gc = (0x05 & lt; & lt; 4), /* 256 cycles (0.25s @ 3.3V) */
WD_512CLK_gc = (0x06 & lt; & lt; 4), /* 512 cycles (0.5s @ 3.3V) */
WD_1KCLK_gc = (0x07 & lt; & lt; 4), /* 1K cycles (1s @ 3.3V) */
WD_2KCLK_gc = (0x08 & lt; & lt; 4), /* 2K cycles (2s @ 3.3V) */
WD_4KCLK_gc = (0x09 & lt; & lt; 4), /* 4K cycles (4s @ 3.3V) */
WD_8KCLK_gc = (0x0A & lt; & lt; 4), /* 8K cycles (8s @ 3.3V) */
} WD_t;

/* Start-up Time */
typedef enum SUT_enum
{
SUT_0MS_gc = (0x03 & lt; & lt; 2), /* 0 ms */
SUT_4MS_gc = (0x01 & lt; & lt; 2), /* 4 ms */
SUT_64MS_gc = (0x00 & lt; & lt; 2), /* 64 ms */
} SUT_t;

/* Brown Out Detection Voltage Level */
typedef enum BODLVL_enum
{
BODLVL_1V6_gc = (0x07 & lt; & lt; 0), /* 1.6 V */
BODLVL_1V9_gc = (0x06 & lt; & lt; 0), /* 1.8 V */
BODLVL_2V1_gc = (0x05 & lt; & lt; 0), /* 2.0 V */
BODLVL_2V4_gc = (0x04 & lt; & lt; 0), /* 2.2 V */
BODLVL_2V6_gc = (0x03 & lt; & lt; 0), /* 2.4 V */
BODLVL_2V9_gc = (0x02 & lt; & lt; 0), /* 2.7 V */
BODLVL_3V2_gc = (0x01 & lt; & lt; 0), /* 2.9 V */
} BODLVL_t;


/*
--------------------------------------------------------------------------
AC - Analog Comparator
--------------------------------------------------------------------------
*/

/* Analog Comparator */
typedef struct AC_struct
{
register8_t AC0CTRL; /* Comparator 0 Control */
register8_t AC1CTRL; /* Comparator 1 Control */
register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */
register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */
register8_t CTRLA; /* Control Register A */
register8_t CTRLB; /* Control Register B */
register8_t WINCTRL; /* Window Mode Control */
register8_t STATUS; /* Status */
} AC_t;

/* Interrupt mode */
typedef enum AC_INTMODE_enum
{
AC_INTMODE_BOTHEDGES_gc = (0x00 & lt; & lt; 6), /* Interrupt on both edges */
AC_INTMODE_FALLING_gc = (0x02 & lt; & lt; 6), /* Interrupt on falling edge */
AC_INTMODE_RISING_gc = (0x03 & lt; & lt; 6), /* Interrupt on rising edge */
} AC_INTMODE_t;

/* Interrupt level */
typedef enum AC_INTLVL_enum
{
AC_INTLVL_OFF_gc = (0x00 & lt; & lt; 4), /* Interrupt disabled */
AC_INTLVL_LO_gc = (0x01 & lt; & lt; 4), /* Low level */
AC_INTLVL_MED_gc = (0x02 & lt; & lt; 4), /* Medium level */
AC_INTLVL_HI_gc = (0x03 & lt; & lt; 4), /* High level */
} AC_INTLVL_t;

/* Hysteresis mode selection */
typedef enum AC_HYSMODE_enum
{
AC_HYSMODE_NO_gc = (0x00 & lt; & lt; 1), /* No hysteresis */
AC_HYSMODE_SMALL_gc = (0x01 & lt; & lt; 1), /* Small hysteresis */
AC_HYSMODE_LARGE_gc = (0x02 & lt; & lt; 1), /* Large hysteresis */
} AC_HYSMODE_t;

/* Positive input multiplexer selection */
typedef enum AC_MUXPOS_enum
{
AC_MUXPOS_PIN0_gc = (0x00 & lt; & lt; 3), /* Pin 0 */
AC_MUXPOS_PIN1_gc = (0x01 & lt; & lt; 3), /* Pin 1 */
AC_MUXPOS_PIN2_gc = (0x02 & lt; & lt; 3), /* Pin 2 */
AC_MUXPOS_PIN3_gc = (0x03 & lt; & lt; 3), /* Pin 3 */
AC_MUXPOS_PIN4_gc = (0x04 & lt; & lt; 3), /* Pin 4 */
AC_MUXPOS_PIN5_gc = (0x05 & lt; & lt; 3), /* Pin 5 */
AC_MUXPOS_PIN6_gc = (0x06 & lt; & lt; 3), /* Pin 6 */
AC_MUXPOS_DAC_gc = (0x07 & lt; & lt; 3), /* DAC output */
} AC_MUXPOS_t;

/* Negative input multiplexer selection */
typedef enum AC_MUXNEG_enum
{
AC_MUXNEG_PIN0_gc = (0x00 & lt; & lt; 0), /* Pin 0 */
AC_MUXNEG_PIN1_gc = (0x01 & lt; & lt; 0), /* Pin 1 */
AC_MUXNEG_PIN3_gc = (0x02 & lt; & lt; 0), /* Pin 3 */
AC_MUXNEG_PIN5_gc = (0x03 & lt; & lt; 0), /* Pin 5 */
AC_MUXNEG_PIN7_gc = (0x04 & lt; & lt; 0), /* Pin 7 */
AC_MUXNEG_DAC_gc = (0x05 & lt; & lt; 0), /* DAC output */
AC_MUXNEG_BANDGAP_gc = (0x06 & lt; & lt; 0), /* Bandgap Reference */
AC_MUXNEG_SCALER_gc = (0x07 & lt; & lt; 0), /* Internal voltage scaler */
} AC_MUXNEG_t;

/* Windows interrupt mode */
typedef enum AC_WINTMODE_enum
{
AC_WINTMODE_ABOVE_gc = (0x00 & lt; & lt; 2), /* Interrupt on above window */
AC_WINTMODE_INSIDE_gc = (0x01 & lt; & lt; 2), /* Interrupt on inside window */
AC_WINTMODE_BELOW_gc = (0x02 & lt; & lt; 2), /* Interrupt on below window */
AC_WINTMODE_OUTSIDE_gc = (0x03 & lt; & lt; 2), /* Interrupt on outside window */
} AC_WINTMODE_t;

/* Window interrupt level */
typedef enum AC_WINTLVL_enum
{
AC_WINTLVL_OFF_gc = (0x00 & lt; & lt; 0), /* Interrupt disabled */
AC_WINTLVL_LO_gc = (0x01 & lt; & lt; 0), /* Low priority */
AC_WINTLVL_MED_gc = (0x02 & lt; & lt; 0), /* Medium priority */
AC_WINTLVL_HI_gc = (0x03 & lt; & lt; 0), /* High priority */
} AC_WINTLVL_t;

/* Window mode state */
typedef enum AC_WSTATE_enum
{
AC_WSTATE_ABOVE_gc = (0x00 & lt; & lt; 6), /* Signal above window */
AC_WSTATE_INSIDE_gc = (0x01 & lt; & lt; 6), /* Signal inside window */
AC_WSTATE_BELOW_gc = (0x02 & lt; & lt; 6), /* Signal below window */
} AC_WSTATE_t;


/*
--------------------------------------------------------------------------
ADC - Analog/Digital Converter
--------------------------------------------------------------------------
*/

/* ADC Channel */
typedef struct ADC_CH_struct
{
register8_t CTRL; /* Control Register */
register8_t MUXCTRL; /* MUX Control */
register8_t INTCTRL; /* Channel Interrupt Control */
register8_t INTFLAGS; /* Interrupt Flags */
_WORDREGISTER(RES); /* Channel Result */
register8_t reserved_0x6;
register8_t reserved_0x7;
} ADC_CH_t;

/*
--------------------------------------------------------------------------
ADC - Analog/Digital Converter
--------------------------------------------------------------------------
*/

/* Analog-to-Digital Converter */
typedef struct ADC_struct
{
register8_t CTRLA; /* Control Register A */
register8_t CTRLB; /* Control Register B */
register8_t REFCTRL; /* Reference Control */
register8_t EVCTRL; /* Event Control */
register8_t PRESCALER; /* Clock Prescaler */
register8_t CALCTRL; /* Calibration Control Register */
register8_t INTFLAGS; /* Interrupt Flags */
register8_t reserved_0x07;
register8_t reserved_0x08;
register8_t reserved_0x09;
register8_t reserved_0x0A;
register8_t reserved_0x0B;
_WORDREGISTER(CAL); /* Calibration Value */
register8_t reserved_0x0E;
register8_t reserved_0x0F;
_WORDREGISTER(CH0RES); /* Channel 0 Result */
_WORDREGISTER(CH1RES); /* Channel 1 Result */
_WORDREGISTER(CH2RES); /* Channel 2 Result */
_WORDREGISTER(CH3RES); /* Channel 3 Result */
_WORDREGISTER(CMP); /* Compare Value */
register8_t reserved_0x1A;
register8_t reserved_0x1B;
register8_t reserved_0x1C;
register8_t reserved_0x1D;
register8_t reserved_0x1E;
register8_t reserved_0x1F;
ADC_CH_t CH0; /* ADC Channel 0 */
ADC_CH_t CH1; /* ADC Channel 1 */
ADC_CH_t CH2; /* ADC Channel 2 */
ADC_CH_t CH3; /* ADC Channel 3 */
} ADC_t;

/* Positive input multiplexer selection */
typedef enum ADC_CH_MUXPOS_enum
{
ADC_CH_MUXPOS_PIN0_gc = (0x00 & lt; & lt; 3), /* Input pin 0 */
ADC_CH_MUXPOS_PIN1_gc = (0x01 & lt; & lt; 3), /* Input pin 1 */
ADC_CH_MUXPOS_PIN2_gc = (0x02 & lt; & lt; 3), /* Input pin 2 */
ADC_CH_MUXPOS_PIN3_gc = (0x03 & lt; & lt; 3), /* Input pin 3 */
ADC_CH_MUXPOS_PIN4_gc = (0x04 & lt; & lt; 3), /* Input pin 4 */
ADC_CH_MUXPOS_PIN5_gc = (0x05 & lt; & lt; 3), /* Input pin 5 */
ADC_CH_MUXPOS_PIN6_gc = (0x06 & lt; & lt; 3), /* Input pin 6 */
ADC_CH_MUXPOS_PIN7_gc = (0x07 & lt; & lt; 3), /* Input pin 7 */
} ADC_CH_MUXPOS_t;

/* Internal input multiplexer selections */
typedef enum ADC_CH_MUXINT_enum
{
ADC_CH_MUXINT_TEMP_gc = (0x00 & lt; & lt; 3), /* Temperature Reference */
ADC_CH_MUXINT_BANDGAP_gc = (0x01 & lt; & lt; 3), /* Bandgap Reference */
ADC_CH_MUXINT_SCALEDVCC_gc = (0x02 & lt; & lt; 3), /* 1/10 scaled VCC */
ADC_CH_MUXINT_DAC_gc = (0x03 & lt; & lt; 3), /* DAC output */
} ADC_CH_MUXINT_t;

/* Negative input multiplexer selection */
typedef enum ADC_CH_MUXNEG_enum
{
ADC_CH_MUXNEG_PIN0_gc = (0x00 & lt; & lt; 0), /* Input pin 0 */
ADC_CH_MUXNEG_PIN1_gc = (0x01 & lt; & lt; 0), /* Input pin 1 */
ADC_CH_MUXNEG_PIN2_gc = (0x02 & lt; & lt; 0), /* Input pin 2 */
ADC_CH_MUXNEG_PIN3_gc = (0x03 & lt; & lt; 0), /* Input pin 3 */
ADC_CH_MUXNEG_PIN4_gc = (0x04 & lt; & lt; 0), /* Input pin 4 */
ADC_CH_MUXNEG_PIN5_gc = (0x05 & lt; & lt; 0), /* Input pin 5 */
ADC_CH_MUXNEG_PIN6_gc = (0x06 & lt; & lt; 0), /* Input pin 6 */
ADC_CH_MUXNEG_PIN7_gc = (0x07 & lt; & lt; 0), /* Input pin 7 */
} ADC_CH_MUXNEG_t;

/* Input mode */
typedef enum ADC_CH_INPUTMODE_enum
{
ADC_CH_INPUTMODE_INTERNAL_gc = (0x00 & lt; & lt; 0), /* Internal inputs, no gain */
ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01 & lt; & lt; 0), /* Single-ended input, no gain */
ADC_CH_INPUTMODE_DIFF_gc = (0x02 & lt; & lt; 0), /* Differential input, no gain */
ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03 & lt; & lt; 0), /* Differential input, with gain */
} ADC_CH_INPUTMODE_t;

/* Gain factor */
typedef enum ADC_CH_GAIN_enum
{
ADC_CH_GAIN_1X_gc = (0x00 & lt; & lt; 2), /* 1x gain */
ADC_CH_GAIN_2X_gc = (0x01 & lt; & lt; 2), /* 2x gain */
ADC_CH_GAIN_4X_gc = (0x02 & lt; & lt; 2), /* 4x gain */
ADC_CH_GAIN_8X_gc = (0x03 & lt; & lt; 2), /* 8x gain */
ADC_CH_GAIN_16X_gc = (0x04 & lt; & lt; 2), /* 16x gain */
ADC_CH_GAIN_32X_gc = (0x05 & lt; & lt; 2), /* 32x gain */
ADC_CH_GAIN_64X_gc = (0x06 & lt; & lt; 2), /* 64x gain */
} ADC_CH_GAIN_t;

/* Conversion result resolution */
typedef enum ADC_RESOLUTION_enum
{
ADC_RESOLUTION_12BIT_gc = (0x00 & lt; & lt; 1), /* 12-bit right-adjusted result */
ADC_RESOLUTION_8BIT_gc = (0x02 & lt; & lt; 1), /* 8-bit right-adjusted result */
ADC_RESOLUTION_LEFT12BIT_gc = (0x03 & lt; & lt; 1), /* 12-bit left-adjusted result */
} ADC_RESOLUTION_t;

/* Voltage reference selection */
typedef enum ADC_REFSEL_enum
{
ADC_REFSEL_INT1V_gc = (0x00 & lt; & lt; 4), /* Internal 1V */
ADC_REFSEL_VCC_gc = (0x01 & lt; & lt; 4), /* Internal VCC / 1.6V */
ADC_REFSEL_AREFA_gc = (0x02 & lt; & lt; 4), /* External reference on PORT A */
ADC_REFSEL_AREFB_gc = (0x03 & lt; & lt; 4), /* External reference on PORT B */
} ADC_REFSEL_t;

/* Channel sweep selection */
typedef enum ADC_SWEEP_enum
{
ADC_SWEEP_0_gc = (0x00 & lt; & lt; 6), /* ADC Channel 0 */
ADC_SWEEP_01_gc = (0x01 & lt; & lt; 6), /* ADC Channel 0,1 */
ADC_SWEEP_012_gc = (0x02 & lt; & lt; 6), /* ADC Channel 0,1,2 */
ADC_SWEEP_0123_gc = (0x03 & lt; & lt; 6), /* ADC Channel 0,1,2,3 */
} ADC_SWEEP_t;

/* Event channel input selection */
typedef enum ADC_EVSEL_enum
{
ADC_EVSEL_0123_gc = (0x00 & lt; & lt; 3), /* Event Channel 0,1,2,3 */
ADC_EVSEL_1234_gc = (0x01 & lt; & lt; 3), /* Event Channel 1,2,3,4 */
ADC_EVSEL_2345_gc = (0x02 & lt; & lt; 3), /* Event Channel 2,3,4,5 */
ADC_EVSEL_3456_gc = (0x03 & lt; & lt; 3), /* Event Channel 3,4,5,6 */
ADC_EVSEL_4567_gc = (0x04 & lt; & lt; 3), /* Event Channel 4,5,6,7 */
ADC_EVSEL_567_gc = (0x05 & lt; & lt; 3), /* Event Channel 5,6,7 */
ADC_EVSEL_67_gc = (0x06 & lt; & lt; 3), /* Event Channel 6,7 */
ADC_EVSEL_7_gc = (0x07 & lt; & lt; 3), /* Event Channel 7 */
} ADC_EVSEL_t;

/* Event action selection */
typedef enum ADC_EVACT_enum
{
ADC_EVACT_NONE_gc = (0x00 & lt; & lt; 0), /* No event action */
ADC_EVACT_CH0_gc = (0x01 & lt; & lt; 0), /* First event triggers channel 0 */
ADC_EVACT_CH01_gc = (0x02 & lt; & lt; 0), /* First two events trigger channel 0,1 */
ADC_EVACT_CH012_gc = (0x03 & lt; & lt; 0), /* First three events trigger channel 0,1,2 */
ADC_EVACT_CH0123_gc = (0x04 & lt; & lt; 0), /* Events trigger channel 0,1,2,3 */
ADC_EVACT_SWEEP_gc = (0x05 & lt; & lt; 0), /* First event triggers sweep */
ADC_EVACT_SYNCHSWEEP_gc = (0x06 & lt; & lt; 0), /* First event triggers synchronized sweep */
} ADC_EVACT_t;

/* Interupt mode */
typedef enum ADC_CH_INTMODE_enum
{
ADC_CH_INTMODE_COMPLETE_gc = (0x00 & lt; & lt; 2), /* Interrupt on conversion complete */
ADC_CH_INTMODE_BELOW_gc = (0x01 & lt; & lt; 2), /* Interrupt on result below compare value */
ADC_CH_INTMODE_ABOVE_gc = (0x03 & lt; & lt; 2), /* Interrupt on result above compare value */
} ADC_CH_INTMODE_t;

/* Interrupt level */
typedef enum ADC_CH_INTLVL_enum
{
ADC_CH_INTLVL_OFF_gc = (0x00 & lt; & lt; 0), /* Interrupt disabled */
ADC_CH_INTLVL_LO_gc = (0x01 & lt; & lt; 0), /* Low level */
ADC_CH_INTLVL_MED_gc = (0x02 & lt; & lt; 0), /* Medium level */
ADC_CH_INTLVL_HI_gc = (0x03 & lt; & lt; 0), /* High level */
} ADC_CH_INTLVL_t;

/* DMA request selection */
typedef enum ADC_DMASEL_enum
{
ADC_DMASEL_OFF_gc = (0x00 & lt; & lt; 6), /* Combined DMA request OFF */
ADC_DMASEL_CH01_gc = (0x01 & lt; & lt; 6), /* ADC Channel 0 or 1 */
ADC_DMASEL_CH012_gc = (0x02 & lt; & lt; 6), /* ADC Channel 0 or 1 or 2 */
ADC_DMASEL_CH0123_gc = (0x03 & lt; & lt; 6), /* ADC Channel 0 or 1 or 2 or 3 */
} ADC_DMASEL_t;

/* Clock prescaler */
typedef enum ADC_PRESCALER_enum
{
ADC_PRESCALER_DIV4_gc = (0x00 & lt; & lt; 0), /* Divide clock by 4 */
ADC_PRESCALER_DIV8_gc = (0x01 & lt; & lt; 0), /* Divide clock by 8 */
ADC_PRESCALER_DIV16_gc = (0x02 & lt; & lt; 0), /* Divide clock by 16 */
ADC_PRESCALER_DIV32_gc = (0x03 & lt; & lt; 0), /* Divide clock by 32 */
ADC_PRESCALER_DIV64_gc = (0x04 & lt; & lt; 0), /* Divide clock by 64 */
ADC_PRESCALER_DIV128_gc = (0x05 & lt; & lt; 0), /* Divide clock by 128 */
ADC_PRESCALER_DIV256_gc = (0x06 & lt; & lt; 0), /* Divide clock by 256 */
ADC_PRESCALER_DIV512_gc = (0x07 & lt; & lt; 0), /* Divide clock by 512 */
} ADC_PRESCALER_t;


/*
--------------------------------------------------------------------------
DAC - Digital/Analog Converter
--------------------------------------------------------------------------
*/

/* Digital-to-Analog Converter */
typedef struct DAC_struct
{
register8_t CTRLA; /* Control Register A */
register8_t CTRLB; /* Control Register B */
register8_t CTRLC; /* Control Register C */
register8_t EVCTRL; /* Event Input Control */
register8_t TIMCTRL; /* Timing Control */
register8_t STATUS; /* Status */
register8_t reserved_0x06;
register8_t reserved_0x07;
register8_t GAINCAL; /* Gain Calibration */
register8_t OFFSETCAL; /* Offset Calibration */
register8_t reserved_0x0A;
register8_t reserved_0x0B;
register8_t reserved_0x0C;
register8_t reserved_0x0D;
register8_t reserved_0x0E;
register8_t reserved_0x0F;
register8_t reserved_0x10;
register8_t reserved_0x11;
register8_t reserved_0x12;
register8_t reserved_0x13;
register8_t reserved_0x14;
register8_t reserved_0x15;
register8_t reserved_0x16;
register8_t reserved_0x17;
_WORDREGISTER(CH0DATA); /* Channel 0 Data */
_WORDREGISTER(CH1DATA); /* Channel 1 Data */
} DAC_t;

/* Output channel selection */
typedef enum DAC_CHSEL_enum
{
DAC_CHSEL_SINGLE_gc = (0x00 & lt; & lt; 5), /* Single channel operation (Channel A only) */
DAC_CHSEL_DUAL_gc = (0x02 & lt; & lt; 5), /* Dual channel operation (S/H on both channels) */
} DAC_CHSEL_t;

/* Reference voltage selection */
typedef enum DAC_REFSEL_enum
{
DAC_REFSEL_INT1V_gc = (0x00 & lt; & lt; 3), /* Internal 1V */
DAC_REFSEL_AVCC_gc = (0x01 & lt; & lt; 3), /* Analog supply voltage */
DAC_REFSEL_AREFA_gc = (0x02 & lt; & lt; 3), /* External reference on AREF on PORTA */
DAC_REFSEL_AREFB_gc = (0x03 & lt; & lt; 3), /* External reference on AREF on PORTB */
} DAC_REFSEL_t;

/* Event channel selection */
typedef enum DAC_EVSEL_enum
{
DAC_EVSEL_0_gc = (0x00 & lt; & lt; 0), /* Event Channel 0 */
DAC_EVSEL_1_gc = (0x01 & lt; & lt; 0), /* Event Channel 1 */
DAC_EVSEL_2_gc = (0x02 & lt; & lt; 0), /* Event Channel 2 */
DAC_EVSEL_3_gc = (0x03 & lt; & lt; 0), /* Event Channel 3 */
DAC_EVSEL_4_gc = (0x04 & lt; & lt; 0), /* Event Channel 4 */
DAC_EVSEL_5_gc = (0x05 & lt; & lt; 0), /* Event Channel 5 */
DAC_EVSEL_6_gc = (0x06 & lt; & lt; 0), /* Event Channel 6 */
DAC_EVSEL_7_gc = (0x07 & lt; & lt; 0), /* Event Channel 7 */
} DAC_EVSEL_t;

/* Conversion interval */
typedef enum DAC_CONINTVAL_enum
{
DAC_CONINTVAL_1CLK_gc = (0x00 & lt; & lt; 4), /* 1 CLK / 2 CLK in S/H mode */
DAC_CONINTVAL_2CLK_gc = (0x01 & lt; & lt; 4), /* 2 CLK / 3 CLK in S/H mode */
DAC_CONINTVAL_4CLK_gc = (0x02 & lt; & lt; 4), /* 4 CLK / 6 CLK in S/H mode */
DAC_CONINTVAL_8CLK_gc = (0x03 & lt; & lt; 4), /* 8 CLK / 12 CLK in S/H mode */
DAC_CONINTVAL_16CLK_gc = (0x04 & lt; & lt; 4), /* 16 CLK / 24 CLK in S/H mode */
DAC_CONINTVAL_32CLK_gc = (0x05 & lt; & lt; 4), /* 32 CLK / 48 CLK in S/H mode */
DAC_CONINTVAL_64CLK_gc = (0x06 & lt; & lt; 4), /* 64 CLK / 96 CLK in S/H mode */
DAC_CONINTVAL_128CLK_gc = (0x07 & lt; & lt; 4), /* 128 CLK / 192 CLK in S/H mode */
} DAC_CONINTVAL_t;

/* Refresh rate */
typedef enum DAC_REFRESH_enum
{
DAC_REFRESH_16CLK_gc = (0x00 & lt; & lt; 0), /* 16 CLK */
DAC_REFRESH_32CLK_gc = (0x01 & lt; & lt; 0), /* 32 CLK */
DAC_REFRESH_64CLK_gc = (0x02 & lt; & lt; 0), /* 64 CLK */
DAC_REFRESH_128CLK_gc = (0x03 & lt; & lt; 0), /* 128 CLK */
DAC_REFRESH_256CLK_gc = (0x04 & lt; & lt; 0), /* 256 CLK */
DAC_REFRESH_512CLK_gc = (0x05 & lt; & lt; 0), /* 512 CLK */
DAC_REFRESH_1024CLK_gc = (0x06 & lt; & lt; 0), /* 1024 CLK */
DAC_REFRESH_2048CLK_gc = (0x07 & lt; & lt; 0), /* 2048 CLK */
DAC_REFRESH_4086CLK_gc = (0x08 & lt; & lt; 0), /* 4096 CLK */
DAC_REFRESH_8192CLK_gc = (0x09 & lt; & lt; 0), /* 8192 CLK */
DAC_REFRESH_16384CLK_gc = (0x0A & lt; & lt; 0), /* 16384 CLK */
DAC_REFRESH_32768CLK_gc = (0x0B & lt; & lt; 0), /* 32768 CLK */
DAC_REFRESH_65536CLK_gc = (0x0C & lt; & lt; 0), /* 65536 CLK */
DAC_REFRESH_OFF_gc = (0x0F & lt; & lt; 0), /* Auto refresh OFF */
} DAC_REFRESH_t;


/*
--------------------------------------------------------------------------
RTC - Real-Time Clounter
--------------------------------------------------------------------------
*/

/* Real-Time Counter */
typedef struct RTC_struct
{
register8_t CTRL; /* Control Register */
register8_t STATUS; /* Status Register */
register8_t INTCTRL; /* Interrupt Control Register */
register8_t INTFLAGS; /* Interrupt Flags */
register8_t TEMP; /* Temporary register */
register8_t reserved_0x05;
register8_t reserved_0x06;
register8_t reserved_0x07;
_WORDREGISTER(CNT); /* Count Register */
_WORDREGISTER(PER); /* Period Register */
_WORDREGISTER(COMP); /* Compare Register */
} RTC_t;

/* Prescaler Factor */
typedef enum RTC_PRESCALER_enum
{
RTC_PRESCALER_OFF_gc = (0x00 & lt; & lt; 0), /* RTC Off */
RTC_PRESCALER_DIV1_gc = (0x01 & lt; & lt; 0), /* RTC Clock */
RTC_PRESCALER_DIV2_gc = (0x02 & lt; & lt; 0), /* RTC Clock / 2 */
RTC_PRESCALER_DIV8_gc = (0x03 & lt; & lt; 0), /* RTC Clock / 8 */
RTC_PRESCALER_DIV16_gc = (0x04 & lt; & lt; 0), /* RTC Clock / 16 */
RTC_PRESCALER_DIV64_gc = (0x05 & lt; & lt; 0), /* RTC Clock / 64 */
RTC_PRESCALER_DIV256_gc = (0x06 & lt; & lt; 0), /* RTC Clock / 256 */
RTC_PRESCALER_DIV1024_gc = (0x07 & lt; & lt; 0), /* RTC Clock / 1024 */
} RTC_PRESCALER_t;

/* Compare Interrupt level */
typedef enum RTC_COMPINTLVL_enum
{
RTC_COMPINTLVL_OFF_gc = (0x00 & lt; & lt; 2), /* Interrupt Disabled */
RTC_COMPINTLVL_LO_gc = (0x01 & lt; & lt; 2), /* Low Level */
RTC_COMPINTLVL_MED_gc = (0x02 & lt; & lt; 2), /* Medium Level */
RTC_COMPINTLVL_HI_gc = (0x03 & lt; & lt; 2), /* High Level */
} RTC_COMPINTLVL_t;

/* Overflow Interrupt level */
typedef enum RTC_OVFINTLVL_enum
{
RTC_OVFINTLVL_OFF_gc = (0x00 & lt; & lt; 0), /* Interrupt Disabled */
RTC_OVFINTLVL_LO_gc = (0x01 & lt; & lt; 0), /* Low Level */
RTC_OVFINTLVL_MED_gc = (0x02 & lt; & lt; 0), /* Medium Level */
RTC_OVFINTLVL_HI_gc = (0x03 & lt; & lt; 0), /* High Level */
} RTC_OVFINTLVL_t;


/*
--------------------------------------------------------------------------
EBI - External Bus Interface
--------------------------------------------------------------------------
*/

/* EBI Chip Select Module */
typedef struct EBI_CS_struct
{
register8_t CTRLA; /* Chip Select Control Register A */
register8_t CTRLB; /* Chip Select Control Register B */
_WORDREGISTER(BASEADDR); /* Chip Select Base Address */
} EBI_CS_t;

/*
--------------------------------------------------------------------------
EBI - External Bus Interface
--------------------------------------------------------------------------
*/

/* External Bus Interface */
typedef struct EBI_struct
{
register8_t CTRL; /* Control */
register8_t SDRAMCTRLA; /* SDRAM Control Register A */
register8_t reserved_0x02;
register8_t reserved_0x03;
_WORDREGISTER(REFRESH); /* SDRAM Refresh Period */
_WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */
register8_t SDRAMCTRLB; /* SDRAM Control Register B */
register8_t SDRAMCTRLC; /* SDRAM Control Register C */
register8_t reserved_0x0A;
register8_t reserved_0x0B;
register8_t reserved_0x0C;
register8_t reserved_0x0D;
register8_t reserved_0x0E;
register8_t reserved_0x0F;
EBI_CS_t CS0; /* Chip Select 0 */
EBI_CS_t CS1; /* Chip Select 1 */
EBI_CS_t CS2; /* Chip Select 2 */
EBI_CS_t CS3; /* Chip Select 3 */
} EBI_t;

/* Chip Select adress space */
typedef enum EBI_CS_ASPACE_enum
{
EBI_CS_ASPACE_256B_gc = (0x00 & lt; & lt; 2), /* 256 bytes */
EBI_CS_ASPACE_512B_gc = (0x01 & lt; & lt; 2), /* 512 bytes */
EBI_CS_ASPACE_1KB_gc = (0x02 & lt; & lt; 2), /* 1K bytes */
EBI_CS_ASPACE_2KB_gc = (0x03 & lt; & lt; 2), /* 2K bytes */
EBI_CS_ASPACE_4KB_gc = (0x04 & lt; & lt; 2), /* 4K bytes */
EBI_CS_ASPACE_8KB_gc = (0x05 & lt; & lt; 2), /* 8K bytes */
EBI_CS_ASPACE_16KB_gc = (0x06 & lt; & lt; 2), /* 16K bytes */
EBI_CS_ASPACE_32KB_gc = (0x07 & lt; & lt; 2), /* 32K bytes */
EBI_CS_ASPACE_64KB_gc = (0x08 & lt; & lt; 2), /* 64K bytes */
EBI_CS_ASPACE_128KB_gc = (0x09 & lt; & lt; 2), /* 128K bytes */
EBI_CS_ASPACE_256KB_gc = (0x0A & lt; & lt; 2), /* 256K bytes */
EBI_CS_ASPACE_512KB_gc = (0x0B & lt; & lt; 2), /* 512K bytes */
EBI_CS_ASPACE_1MB_gc = (0x0C & lt; & lt; 2), /* 1M bytes */
EBI_CS_ASPACE_2MB_gc = (0x0D & lt; & lt; 2), /* 2M bytes */
EBI_CS_ASPACE_4MB_gc = (0x0E & lt; & lt; 2), /* 4M bytes */
EBI_CS_ASPACE_8MB_gc = (0x0F & lt; & lt; 2), /* 8M bytes */
EBI_CS_ASPACE_16M_gc = (0x10 & lt; & lt; 2), /* 16M bytes */
} EBI_CS_ASPACE_t;

/* */
typedef enum EBI_CS_SRWS_enum
{
EBI_CS_SRWS_0CLK_gc = (0x00 & lt; & lt; 0), /* 0 cycles */
EBI_CS_SRWS_1CLK_gc = (0x01 & lt; & lt; 0), /* 1 cycle */
EBI_CS_SRWS_2CLK_gc = (0x02 & lt; & lt; 0), /* 2 cycles */
EBI_CS_SRWS_3CLK_gc = (0x03 & lt; & lt; 0), /* 3 cycles */
EBI_CS_SRWS_4CLK_gc = (0x04 & lt; & lt; 0), /* 4 cycles */
EBI_CS_SRWS_5CLK_gc = (0x05 & lt; & lt; 0), /* 5 cycle */
EBI_CS_SRWS_6CLK_gc = (0x06 & lt; & lt; 0), /* 6 cycles */
EBI_CS_SRWS_7CLK_gc = (0x07 & lt; & lt; 0), /* 7 cycles */
} EBI_CS_SRWS_t;

/* Chip Select address mode */
typedef enum EBI_CS_MODE_enum
{
EBI_CS_MODE_DISABLED_gc = (0x00 & lt; & lt; 0), /* Chip Select Disabled */
EBI_CS_MODE_SRAM_gc = (0x01 & lt; & lt; 0), /* Chip Select in SRAM mode */
EBI_CS_MODE_LPC_gc = (0x02 & lt; & lt; 0), /* Chip Select in SRAM LPC mode */
EBI_CS_MODE_SDRAM_gc = (0x03 & lt; & lt; 0), /* Chip Select in SDRAM mode */
} EBI_CS_MODE_t;

/* Chip Select SDRAM mode */
typedef enum EBI_CS_SDMODE_enum
{
EBI_CS_SDMODE_NORMAL_gc = (0x00 & lt; & lt; 0), /* Normal mode */
EBI_CS_SDMODE_LOAD_gc = (0x01 & lt; & lt; 0), /* Load Mode Register command mode */
} EBI_CS_SDMODE_t;

/* */
typedef enum EBI_SDDATAW_enum
{
EBI_SDDATAW_4BIT_gc = (0x00 & lt; & lt; 6), /* 4-bit data bus */
EBI_SDDATAW_8BIT_gc = (0x01 & lt; & lt; 6), /* 8-bit data bus */
} EBI_SDDATAW_t;

/* */
typedef enum EBI_LPCMODE_enum
{
EBI_LPCMODE_ALE1_gc = (0x00 & lt; & lt; 4), /* Data muxed with addr byte 0 */
EBI_LPCMODE_ALE12_gc = (0x02 & lt; & lt; 4), /* Data muxed with addr byte 0 and 1 */
} EBI_LPCMODE_t;

/* */
typedef enum EBI_SRMODE_enum
{
EBI_SRMODE_ALE1_gc = (0x00 & lt; & lt; 2), /* Addr byte 0 muxed with 1 */
EBI_SRMODE_ALE2_gc = (0x01 & lt; & lt; 2), /* Addr byte 0 muxed with 2 */
EBI_SRMODE_ALE12_gc = (0x02 & lt; & lt; 2), /* Addr byte 0 muxed with 1 and 2 */
EBI_SRMODE_NOALE_gc = (0x03 & lt; & lt; 2), /* No addr muxing */
} EBI_SRMODE_t;

/* */
typedef enum EBI_IFMODE_enum
{
EBI_IFMODE_DISABLED_gc = (0x00 & lt; & lt; 0), /* EBI Disabled */
EBI_IFMODE_3PORT_gc = (0x01 & lt; & lt; 0), /* 3-port mode */
EBI_IFMODE_4PORT_gc = (0x02 & lt; & lt; 0), /* 4-port mode */
EBI_IFMODE_2PORT_gc = (0x03 & lt; & lt; 0), /* 2-port mode */
} EBI_IFMODE_t;

/* */
typedef enum EBI_SDCOL_enum
{
EBI_SDCOL_8BIT_gc = (0x00 & lt; & lt; 0), /* 8 column bits */
EBI_SDCOL_9BIT_gc = (0x01 & lt; & lt; 0), /* 9 column bits */
EBI_SDCOL_10BIT_gc = (0x02 & lt; & lt; 0), /* 10 column bits */
EBI_SDCOL_11BIT_gc = (0x03 & lt; & lt; 0), /* 11 column bits */
} EBI_SDCOL_t;

/* */
typedef enum EBI_MRDLY_enum
{
EBI_MRDLY_0CLK_gc = (0x00 & lt; & lt; 6), /* 0 cycles */
EBI_MRDLY_1CLK_gc = (0x01 & lt; & lt; 6), /* 1 cycle */
EBI_MRDLY_2CLK_gc = (0x02 & lt; & lt; 6), /* 2 cycles */
EBI_MRDLY_3CLK_gc = (0x03 & lt; & lt; 6), /* 3 cycles */
} EBI_MRDLY_t;

/* */
typedef enum EBI_ROWCYCDLY_enum
{
EBI_ROWCYCDLY_0CLK_gc = (0x00 & lt; & lt; 3), /* 0 cycles */
EBI_ROWCYCDLY_1CLK_gc = (0x01 & lt; & lt; 3), /* 1 cycle */
EBI_ROWCYCDLY_2CLK_gc = (0x02 & lt; & lt; 3), /* 2 cycles */
EBI_ROWCYCDLY_3CLK_gc = (0x03 & lt; & lt; 3), /* 3 cycles */
EBI_ROWCYCDLY_4CLK_gc = (0x04 & lt; & lt; 3), /* 4 cycles */
EBI_ROWCYCDLY_5CLK_gc = (0x05 & lt; & lt; 3), /* 5 cycle */
EBI_ROWCYCDLY_6CLK_gc = (0x06 & lt; & lt; 3), /* 6 cycles */
EBI_ROWCYCDLY_7CLK_gc = (0x07 & lt; & lt; 3), /* 7 cycles */
} EBI_ROWCYCDLY_t;

/* */
typedef enum EBI_RPDLY_enum
{
EBI_RPDLY_0CLK_gc = (0x00 & lt; & lt; 0), /* 0 cycles */
EBI_RPDLY_1CLK_gc = (0x01 & lt; & lt; 0), /* 1 cycle */
EBI_RPDLY_2CLK_gc = (0x02 & lt; & lt; 0), /* 2 cycles */
EBI_RPDLY_3CLK_gc = (0x03 & lt; & lt; 0), /* 3 cycles */
EBI_RPDLY_4CLK_gc = (0x04 & lt; & lt; 0), /* 4 cycles */
EBI_RPDLY_5CLK_gc = (0x05 & lt; & lt; 0), /* 5 cycle */
EBI_RPDLY_6CLK_gc = (0x06 & lt; & lt; 0), /* 6 cycles */
EBI_RPDLY_7CLK_gc = (0x07 & lt; & lt; 0), /* 7 cycles */
} EBI_RPDLY_t;

/* */
typedef enum EBI_WRDLY_enum
{
EBI_WRDLY_0CLK_gc = (0x00 & lt; & lt; 6), /* 0 cycles */
EBI_WRDLY_1CLK_gc = (0x01 & lt; & lt; 6), /* 1 cycle */
EBI_WRDLY_2CLK_gc = (0x02 & lt; & lt; 6), /* 2 cycles */
EBI_WRDLY_3CLK_gc = (0x03 & lt; & lt; 6), /* 3 cycles */
} EBI_WRDLY_t;

/* */
typedef enum EBI_ESRDLY_enum
{
EBI_ESRDLY_0CLK_gc = (0x00 & lt; & lt; 3), /* 0 cycles */
EBI_ESRDLY_1CLK_gc = (0x01 & lt; & lt; 3), /* 1 cycle */
EBI_ESRDLY_2CLK_gc = (0x02 & lt; & lt; 3), /* 2 cycles */
EBI_ESRDLY_3CLK_gc = (0x03 & lt; & lt; 3), /* 3 cycles */
EBI_ESRDLY_4CLK_gc = (0x04 & lt; & lt; 3), /* 4 cycles */
EBI_ESRDLY_5CLK_gc = (0x05 & lt; & lt; 3), /* 5 cycle */
EBI_ESRDLY_6CLK_gc = (0x06 & lt; & lt; 3), /* 6 cycles */
EBI_ESRDLY_7CLK_gc = (0x07 & lt; & lt; 3), /* 7 cycles */
} EBI_ESRDLY_t;

/* */
typedef enum EBI_ROWCOLDLY_enum
{
EBI_ROWCOLDLY_0CLK_gc = (0x00 & lt; & lt; 0), /* 0 cycles */
EBI_ROWCOLDLY_1CLK_gc = (0x01 & lt; & lt; 0), /* 1 cycle */
EBI_ROWCOLDLY_2CLK_gc = (0x02 & lt; & lt; 0), /* 2 cycles */
EBI_ROWCOLDLY_3CLK_gc = (0x03 & lt; & lt; 0), /* 3 cycles */
EBI_ROWCOLDLY_4CLK_gc = (0x04 & lt; & lt; 0), /* 4 cycles */
EBI_ROWCOLDLY_5CLK_gc = (0x05 & lt; & lt; 0), /* 5 cycle */
EBI_ROWCOLDLY_6CLK_gc = (0x06 & lt; & lt; 0), /* 6 cycles */
EBI_ROWCOLDLY_7CLK_gc = (0x07 & lt; & lt; 0), /* 7 cycles */
} EBI_ROWCOLDLY_t;


/*
--------------------------------------------------------------------------
TWI - Two-Wire Interface
--------------------------------------------------------------------------
*/

/* */
typedef struct TWI_MASTER_struct
{
register8_t CTRLA; /* Control Register A */
register8_t CTRLB; /* Control Register B */
register8_t CTRLC; /* Control Register C */
register8_t STATUS; /* Status Register */
register8_t BAUD; /* Baurd Rate Control Register */
register8_t ADDR; /* Address Register */
register8_t DATA; /* Data Register */
} TWI_MASTER_t;

/*
--------------------------------------------------------------------------
TWI - Two-Wire Interface
--------------------------------------------------------------------------
*/

/* */
typedef struct TWI_SLAVE_struct
{
register8_t CTRLA; /* Control Register A */
register8_t CTRLB; /* Control Register B */
register8_t STATUS; /* Status Register */
register8_t ADDR; /* Address Register */
register8_t DATA; /* Data Register */
register8_t ADDRMASK; /* Address Mask Register */
} TWI_SLAVE_t;

/*
--------------------------------------------------------------------------
TWI - Two-Wire Interface
--------------------------------------------------------------------------
*/

/* Two-Wire Interface */
typedef struct TWI_struct
{
register8_t CTRL; /* TWI Common Control Register */
TWI_MASTER_t MASTER; /* TWI master module */
TWI_SLAVE_t SLAVE; /* TWI slave module */
} TWI_t;

/* Master Interrupt Level */
typedef enum TWI_MASTER_INTLVL_enum
{
TWI_MASTER_INTLVL_OFF_gc = (0x00 & lt; & lt; 6), /* Interrupt Disabled */
TWI_MASTER_INTLVL_LO_gc = (0x01 & lt; & lt; 6), /* Low Level */
TWI_MASTER_INTLVL_MED_gc = (0x02 & lt; & lt; 6), /* Medium Level */
TWI_MASTER_INTLVL_HI_gc = (0x03 & lt; & lt; 6), /* High Level */
} TWI_MASTER_INTLVL_t;

/* Inactive Timeout */
typedef enum TWI_MASTER_TIMEOUT_enum
{
TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00 & lt; & lt; 2), /* Bus Timeout Disabled */
TWI_MASTER_TIMEOUT_50US_gc = (0x01 & lt; & lt; 2), /* 50 Microseconds */
TWI_MASTER_TIMEOUT_100US_gc = (0x02 & lt; & lt; 2), /* 100 Microseconds */
TWI_MASTER_TIMEOUT_200US_gc = (0x03 & lt; & lt; 2), /* 200 Microseconds */
} TWI_MASTER_TIMEOUT_t;

/* Master Command */
typedef enum TWI_MASTER_CMD_enum
{
TWI_MASTER_CMD_NOACT_gc = (0x00 & lt; & lt; 0), /* No Action */
TWI_MASTER_CMD_REPSTART_gc = (0x01 & lt; & lt; 0), /* Issue Repeated Start Condition */
TWI_MASTER_CMD_RECVTRANS_gc = (0x02 & lt; & lt; 0), /* Receive or Transmit Data */
TWI_MASTER_CMD_STOP_gc = (0x03 & lt; & lt; 0), /* Issue Stop Condition */
} TWI_MASTER_CMD_t;

/* Master Bus State */
typedef enum TWI_MASTER_BUSSTATE_enum
{
TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00 & lt; & lt; 0), /* Unknown Bus State */
TWI_MASTER_BUSSTATE_IDLE_gc = (0x01 & lt; & lt; 0), /* Bus is Idle */
TWI_MASTER_BUSSTATE_OWNER_gc = (0x02 & lt; & lt; 0), /* This Module Controls The Bus */
TWI_MASTER_BUSSTATE_BUSY_gc = (0x03 & lt; & lt; 0), /* The Bus is Busy */
} TWI_MASTER_BUSSTATE_t;

/* Slave Interrupt Level */
typedef enum TWI_SLAVE_INTLVL_enum
{
TWI_SLAVE_INTLVL_OFF_gc = (0x00 & lt; & lt; 6), /* Interrupt Disabled */
TWI_SLAVE_INTLVL_LO_gc = (0x01 & lt; & lt; 6), /* Low Level */
TWI_SLAVE_INTLVL_MED_gc = (0x02 & lt; & lt; 6), /* Medium Level */
TWI_SLAVE_INTLVL_HI_gc = (0x03 & lt; & lt; 6), /* High Level */
} TWI_SLAVE_INTLVL_t;

/* Slave Command */
typedef enum TWI_SLAVE_CMD_enum
{
TWI_SLAVE_CMD_NOACT_gc = (0x00 & lt; & lt; 0), /* No Action */
TWI_SLAVE_CMD_COMPTRANS_gc = (0x02 & lt; & lt; 0), /* Used To Complete a Transaction */
TWI_SLAVE_CMD_RESPONSE_gc = (0x03 & lt; & lt; 0), /* Used in Response to Address/Data Interrupt */
} TWI_SLAVE_CMD_t;


/*
--------------------------------------------------------------------------
PORT - Port Configuration
--------------------------------------------------------------------------
*/

/* I/O port Configuration */
typedef struct PORTCFG_struct
{
register8_t MPCMASK; /* Multi-pin Configuration Mask */
register8_t reserved_0x01;
register8_t VPCTRLA; /* Virtual Port Control Register A */
register8_t VPCTRLB; /* Virtual Port Control Register B */
register8_t CLKEVOUT; /* Clock and Event Out Register */
} PORTCFG_t;

/*
--------------------------------------------------------------------------
PORT - Port Configuration
--------------------------------------------------------------------------
*/

/* Virtual Port */
typedef struct VPORT_struct
{
register8_t DIR; /* I/O Port Data Direction */
register8_t OUT; /* I/O Port Output */
register8_t IN; /* I/O Port Input */
register8_t INTFLAGS; /* Interrupt Flag Register */
} VPORT_t;

/*
--------------------------------------------------------------------------
PORT - Port Configuration
--------------------------------------------------------------------------
*/

/* I/O Ports */
typedef struct PORT_struct
{
register8_t DIR; /* I/O Port Data Direction */
register8_t DIRSET; /* I/O Port Data Direction Set */
register8_t DIRCLR; /* I/O Port Data Direction Clear */
register8_t DIRTGL; /* I/O Port Data Direction Toggle */
register8_t OUT; /* I/O Port Output */
register8_t OUTSET; /* I/O Port Output Set */
register8_t OUTCLR; /* I/O Port Output Clear */
register8_t OUTTGL; /* I/O Port Output Toggle */
register8_t IN; /* I/O port Input */
register8_t INTCTRL; /* Interrupt Control Register */
register8_t INT0MASK; /* Port Interrupt 0 Mask */
register8_t INT1MASK; /* Port Interrupt 1 Mask */
register8_t INTFLAGS; /* Interrupt Flag Register */
register8_t reserved_0x0D;
register8_t reserved_0x0E;
register8_t reserved_0x0F;
register8_t PIN0CTRL; /* Pin 0 Control Register */
register8_t PIN1CTRL; /* Pin 1 Control Register */
register8_t PIN2CTRL; /* Pin 2 Control Register */
register8_t PIN3CTRL; /* Pin 3 Control Register */
register8_t PIN4CTRL; /* Pin 4 Control Register */
register8_t PIN5CTRL; /* Pin 5 Control Register */
register8_t PIN6CTRL; /* Pin 6 Control Register */
register8_t PIN7CTRL; /* Pin 7 Control Register */
} PORT_t;

/* Virtual Port 0 Mapping */
typedef enum PORTCFG_VP0MAP_enum
{
PORTCFG_VP0MAP_PORTA_gc = (0x00 & lt; & lt; 0), /* Mapped To PORTA */
PORTCFG_VP0MAP_PORTB_gc = (0x01 & lt; & lt; 0), /* Mapped To PORTB */
PORTCFG_VP0MAP_PORTC_gc = (0x02 & lt; & lt; 0), /* Mapped To PORTC */
PORTCFG_VP0MAP_PORTD_gc = (0x03 & lt; & lt; 0), /* Mapped To PORTD */
PORTCFG_VP0MAP_PORTE_gc = (0x04 & lt; & lt; 0), /* Mapped To PORTE */
PORTCFG_VP0MAP_PORTF_gc = (0x05 & lt; & lt; 0), /* Mapped To PORTF */
PORTCFG_VP0MAP_PORTG_gc = (0x06 & lt; & lt; 0), /* Mapped To PORTG */
PORTCFG_VP0MAP_PORTH_gc = (0x07 & lt; & lt; 0), /* Mapped To PORTH */
PORTCFG_VP0MAP_PORTJ_gc = (0x08 & lt; & lt; 0), /* Mapped To PORTJ */
PORTCFG_VP0MAP_PORTK_gc = (0x09 & lt; & lt; 0), /* Mapped To PORTK */
PORTCFG_VP0MAP_PORTL_gc = (0x0A & lt; & lt; 0), /* Mapped To PORTL */
PORTCFG_VP0MAP_PORTM_gc = (0x0B & lt; & lt; 0), /* Mapped To PORTM */
PORTCFG_VP0MAP_PORTN_gc = (0x0C & lt; & lt; 0), /* Mapped To PORTN */
PORTCFG_VP0MAP_PORTP_gc = (0x0D & lt; & lt; 0), /* Mapped To PORTP */
PORTCFG_VP0MAP_PORTQ_gc = (0x0E & lt; & lt; 0), /* Mapped To PORTQ */
PORTCFG_VP0MAP_PORTR_gc = (0x0F & lt; & lt; 0), /* Mapped To PORTR */
} PORTCFG_VP0MAP_t;

/* Virtual Port 1 Mapping */
typedef enum PORTCFG_VP1MAP_enum
{
PORTCFG_VP1MAP_PORTA_gc = (0x00 & lt; & lt; 4), /* Mapped To PORTA */
PORTCFG_VP1MAP_PORTB_gc = (0x01 & lt; & lt; 4), /* Mapped To PORTB */
PORTCFG_VP1MAP_PORTC_gc = (0x02 & lt; & lt; 4), /* Mapped To PORTC */
PORTCFG_VP1MAP_PORTD_gc = (0x03 & lt; & lt; 4), /* Mapped To PORTD */
PORTCFG_VP1MAP_PORTE_gc = (0x04 & lt; & lt; 4), /* Mapped To PORTE */
PORTCFG_VP1MAP_PORTF_gc = (0x05 & lt; & lt; 4), /* Mapped To PORTF */
PORTCFG_VP1MAP_PORTG_gc = (0x06 & lt; & lt; 4), /* Mapped To PORTG */
PORTCFG_VP1MAP_PORTH_gc = (0x07 & lt; & lt; 4), /* Mapped To PORTH */
PORTCFG_VP1MAP_PORTJ_gc = (0x08 & lt; & lt; 4), /* Mapped To PORTJ */
PORTCFG_VP1MAP_PORTK_gc = (0x09 & lt; & lt; 4), /* Mapped To PORTK */
PORTCFG_VP1MAP_PORTL_gc = (0x0A & lt; & lt; 4), /* Mapped To PORTL */
PORTCFG_VP1MAP_PORTM_gc = (0x0B & lt; & lt; 4), /* Mapped To PORTM */
PORTCFG_VP1MAP_PORTN_gc = (0x0C & lt; & lt; 4), /* Mapped To PORTN */
PORTCFG_VP1MAP_PORTP_gc = (0x0D & lt; & lt; 4), /* Mapped To PORTP */
PORTCFG_VP1MAP_PORTQ_gc = (0x0E & lt; & lt; 4), /* Mapped To PORTQ */
PORTCFG_VP1MAP_PORTR_gc = (0x0F & lt; & lt; 4), /* Mapped To PORTR */
} PORTCFG_VP1MAP_t;

/* Virtual Port 2 Mapping */
typedef enum PORTCFG_VP2MAP_enum
{
PORTCFG_VP2MAP_PORTA_gc = (0x00 & lt; & lt; 0), /* Mapped To PORTA */
PORTCFG_VP2MAP_PORTB_gc = (0x01 & lt; & lt; 0), /* Mapped To PORTB */
PORTCFG_VP2MAP_PORTC_gc = (0x02 & lt; & lt; 0), /* Mapped To PORTC */
PORTCFG_VP2MAP_PORTD_gc = (0x03 & lt; & lt; 0), /* Mapped To PORTD */
PORTCFG_VP2MAP_PORTE_gc = (0x04 & lt; & lt; 0), /* Mapped To PORTE */
PORTCFG_VP2MAP_PORTF_gc = (0x05 & lt; & lt; 0), /* Mapped To PORTF */
PORTCFG_VP2MAP_PORTG_gc = (0x06 & lt; & lt; 0), /* Mapped To PORTG */
PORTCFG_VP2MAP_PORTH_gc = (0x07 & lt; & lt; 0), /* Mapped To PORTH */
PORTCFG_VP2MAP_PORTJ_gc = (0x08 & lt; & lt; 0), /* Mapped To PORTJ */
PORTCFG_VP2MAP_PORTK_gc = (0x09 & lt; & lt; 0), /* Mapped To PORTK */
PORTCFG_VP2MAP_PORTL_gc = (0x0A & lt; & lt; 0), /* Mapped To PORTL */
PORTCFG_VP2MAP_PORTM_gc = (0x0B & lt; & lt; 0), /* Mapped To PORTM */
PORTCFG_VP2MAP_PORTN_gc = (0x0C & lt; & lt; 0), /* Mapped To PORTN */
PORTCFG_VP2MAP_PORTP_gc = (0x0D & lt; & lt; 0), /* Mapped To PORTP */
PORTCFG_VP2MAP_PORTQ_gc = (0x0E & lt; & lt; 0), /* Mapped To PORTQ */
PORTCFG_VP2MAP_PORTR_gc = (0x0F & lt; & lt; 0), /* Mapped To PORTR */
} PORTCFG_VP2MAP_t;

/* Virtual Port 3 Mapping */
typedef enum PORTCFG_VP3MAP_enum
{
PORTCFG_VP3MAP_PORTA_gc = (0x00 & lt; & lt; 4), /* Mapped To PORTA */
PORTCFG_VP3MAP_PORTB_gc = (0x01 & lt; & lt; 4), /* Mapped To PORTB */
PORTCFG_VP3MAP_PORTC_gc = (0x02 & lt; & lt; 4), /* Mapped To PORTC */
PORTCFG_VP3MAP_PORTD_gc = (0x03 & lt; & lt; 4), /* Mapped To PORTD */
PORTCFG_VP3MAP_PORTE_gc = (0x04 & lt; & lt; 4), /* Mapped To PORTE */
PORTCFG_VP3MAP_PORTF_gc = (0x05 & lt; & lt; 4), /* Mapped To PORTF */
PORTCFG_VP3MAP_PORTG_gc = (0x06 & lt; & lt; 4), /* Mapped To PORTG */
PORTCFG_VP3MAP_PORTH_gc = (0x07 & lt; & lt; 4), /* Mapped To PORTH */
PORTCFG_VP3MAP_PORTJ_gc = (0x08 & lt; & lt; 4), /* Mapped To PORTJ */
PORTCFG_VP3MAP_PORTK_gc = (0x09 & lt; & lt; 4), /* Mapped To PORTK */
PORTCFG_VP3MAP_PORTL_gc = (0x0A & lt; & lt; 4), /* Mapped To PORTL */
PORTCFG_VP3MAP_PORTM_gc = (0x0B & lt; & lt; 4), /* Mapped To PORTM */
PORTCFG_VP3MAP_PORTN_gc = (0x0C & lt; & lt; 4), /* Mapped To PORTN */
PORTCFG_VP3MAP_PORTP_gc = (0x0D & lt; & lt; 4), /* Mapped To PORTP */
PORTCFG_VP3MAP_PORTQ_gc = (0x0E & lt; & lt; 4), /* Mapped To PORTQ */
PORTCFG_VP3MAP_PORTR_gc = (0x0F & lt; & lt; 4), /* Mapped To PORTR */
} PORTCFG_VP3MAP_t;

/* Clock Output Port */
typedef enum PORTCFG_CLKOUT_enum
{
PORTCFG_CLKOUT_OFF_gc = (0x00 & lt; & lt; 0), /* Clock Output Disabled */
PORTCFG_CLKOUT_PC7_gc = (0x01 & lt; & lt; 0), /* Clock Output on Port C pin 7 */
PORTCFG_CLKOUT_PD7_gc = (0x02 & lt; & lt; 0), /* Clock Output on Port D pin 7 */
PORTCFG_CLKOUT_PE7_gc = (0x03 & lt; & lt; 0), /* Clock Output on Port E pin 7 */
} PORTCFG_CLKOUT_t;

/* Event Output Port */
typedef enum PORTCFG_EVOUT_enum
{
PORTCFG_EVOUT_OFF_gc = (0x00 & lt; & lt; 4), /* Event Output Disabled */
PORTCFG_EVOUT_PC7_gc = (0x01 & lt; & lt; 4), /* Event Channel 7 Output on Port C pin 7 */
PORTCFG_EVOUT_PD7_gc = (0x02 & lt; & lt; 4), /* Event Channel 7 Output on Port D pin 7 */
PORTCFG_EVOUT_PE7_gc = (0x03 & lt; & lt; 4), /* Event Channel 7 Output on Port E pin 7 */
} PORTCFG_EVOUT_t;

/* Port Interrupt 0 Level */
typedef enum PORT_INT0LVL_enum
{
PORT_INT0LVL_OFF_gc = (0x00 & lt; & lt; 0), /* Interrupt Disabled */
PORT_INT0LVL_LO_gc = (0x01 & lt; & lt; 0), /* Low Level */
PORT_INT0LVL_MED_gc = (0x02 & lt; & lt; 0), /* Medium Level */
PORT_INT0LVL_HI_gc = (0x03 & lt; & lt; 0), /* High Level */
} PORT_INT0LVL_t;

/* Port Interrupt 1 Level */
typedef enum PORT_INT1LVL_enum
{
PORT_INT1LVL_OFF_gc = (0x00 & lt; & lt; 2), /* Interrupt Disabled */
PORT_INT1LVL_LO_gc = (0x01 & lt; & lt; 2), /* Low Level */
PORT_INT1LVL_MED_gc = (0x02 & lt; & lt; 2), /* Medium Level */
PORT_INT1LVL_HI_gc = (0x03 & lt; & lt; 2), /* High Level */
} PORT_INT1LVL_t;

/* Output/Pull Configuration */
typedef enum PORT_OPC_enum
{
PORT_OPC_TOTEM_gc = (0x00 & lt; & lt; 3), /* Totempole */
PORT_OPC_BUSKEEPER_gc = (0x01 & lt; & lt; 3), /* Totempole w/ Bus keeper on Input and Output */
PORT_OPC_PULLDOWN_gc = (0x02 & lt; & lt; 3), /* Totempole w/ Pull-down on Input */
PORT_OPC_PULLUP_gc = (0x03 & lt; & lt; 3), /* Totempole w/ Pull-up on Input */
PORT_OPC_WIREDOR_gc = (0x04 & lt; & lt; 3), /* Wired OR */
PORT_OPC_WIREDAND_gc = (0x05 & lt; & lt; 3), /* Wired AND */
PORT_OPC_WIREDORPULL_gc = (0x06 & lt; & lt; 3), /* Wired OR w/ Pull-down */
PORT_OPC_WIREDANDPULL_gc = (0x07 & lt; & lt; 3), /* Wired AND w/ Pull-up */
} PORT_OPC_t;

/* Input/Sense Configuration */
typedef enum PORT_ISC_enum
{
PORT_ISC_BOTHEDGES_gc = (0x00 & lt; & lt; 0), /* Sense Both Edges */
PORT_ISC_RISING_gc = (0x01 & lt; & lt; 0), /* Sense Rising Edge */
PORT_ISC_FALLING_gc = (0x02 & lt; & lt; 0), /* Sense Falling Edge */
PORT_ISC_LEVEL_gc = (0x03 & lt; & lt; 0), /* Sense Level (Transparent For Events) */
PORT_ISC_INPUT_DISABLE_gc = (0x07 & lt; & lt; 0), /* Disable Digital Input Buffer */
} PORT_ISC_t;


/*
--------------------------------------------------------------------------
TC - 16-bit Timer/Counter With PWM
--------------------------------------------------------------------------
*/

/* 16-bit Timer/Counter 0 */
typedef struct TC0_struct
{
register8_t CTRLA; /* Control Register A */
register8_t CTRLB; /* Control Register B */
register8_t CTRLC; /* Control register C */
register8_t CTRLD; /* Control Register D */
register8_t CTRLE; /* Control Register E */
register8_t reserved_0x05;
register8_t INTCTRLA; /* Interrupt Control Register A */
register8_t INTCTRLB; /* Interrupt Control Register B */
register8_t CTRLFCLR; /* Control Register F Clear */
register8_t CTRLFSET; /* Control Register F Set */
register8_t CTRLGCLR; /* Control Register G Clear */
register8_t CTRLGSET; /* Control Register G Set */
register8_t INTFLAGS; /* Interrupt Flag Register */
register8_t reserved_0x0D;
register8_t reserved_0x0E;
register8_t TEMP; /* Temporary Register For 16-bit Access */
register8_t reserved_0x10;
register8_t reserved_0x11;
register8_t reserved_0x12;
register8_t reserved_0x13;
register8_t reserved_0x14;
register8_t reserved_0x15;
register8_t reserved_0x16;
register8_t reserved_0x17;
register8_t reserved_0x18;
register8_t reserved_0x19;
register8_t reserved_0x1A;
register8_t reserved_0x1B;
register8_t reserved_0x1C;
register8_t reserved_0x1D;
register8_t reserved_0x1E;
register8_t reserved_0x1F;
_WORDREGISTER(CNT); /* Count */
register8_t reserved_0x22;
register8_t reserved_0x23;
register8_t reserved_0x24;
register8_t reserved_0x25;
_WORDREGISTER(PER); /* Period */
_WORDREGISTER(CCA); /* Compare or Capture A */
_WORDREGISTER(CCB); /* Compare or Capture B */
_WORDREGISTER(CCC); /* Compare or Capture C */
_WORDREGISTER(CCD); /* Compare or Capture D */
register8_t reserved_0x30;
register8_t reserved_0x31;
register8_t reserved_0x32;
register8_t reserved_0x33;
register8_t reserved_0x34;
register8_t reserved_0x35;
_WORDREGISTER(PERBUF); /* Period Buffer */
_WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
_WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
_WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */
_WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */
} TC0_t;

/*
--------------------------------------------------------------------------
TC - 16-bit Timer/Counter With PWM
--------------------------------------------------------------------------
*/

/* 16-bit Timer/Counter 1 */
typedef struct TC1_struct
{
register8_t CTRLA; /* Control Register A */
register8_t CTRLB; /* Control Register B */
register8_t CTRLC; /* Control register C */
register8_t CTRLD; /* Control Register D */
register8_t CTRLE; /* Control Register E */
register8_t reserved_0x05;
register8_t INTCTRLA; /* Interrupt Control Register A */
register8_t INTCTRLB; /* Interrupt Control Register B */
register8_t CTRLFCLR; /* Control Register F Clear */
register8_t CTRLFSET; /* Control Register F Set */
register8_t CTRLGCLR; /* Control Register G Clear */
register8_t CTRLGSET; /* Control Register G Set */
register8_t INTFLAGS; /* Interrupt Flag Register */
register8_t reserved_0x0D;
register8_t reserved_0x0E;
register8_t TEMP; /* Temporary Register For 16-bit Access */
register8_t reserved_0x10;
register8_t reserved_0x11;
register8_t reserved_0x12;
register8_t reserved_0x13;
register8_t reserved_0x14;
register8_t reserved_0x15;
register8_t reserved_0x16;
register8_t reserved_0x17;
register8_t reserved_0x18;
register8_t reserved_0x19;
register8_t reserved_0x1A;
register8_t reserved_0x1B;
register8_t reserved_0x1C;
register8_t reserved_0x1D;
register8_t reserved_0x1E;
register8_t reserved_0x1F;
_WORDREGISTER(CNT); /* Count */
register8_t reserved_0x22;
register8_t reserved_0x23;
register8_t reserved_0x24;
register8_t reserved_0x25;
_WORDREGISTER(PER); /* Period */
_WORDREGISTER(CCA); /* Compare or Capture A */
_WORDREGISTER(CCB); /* Compare or Capture B */
register8_t reserved_0x2C;
register8_t reserved_0x2D;
register8_t reserved_0x2E;
register8_t reserved_0x2F;
register8_t reserved_0x30;
register8_t reserved_0x31;
register8_t reserved_0x32;
register8_t reserved_0x33;
register8_t reserved_0x34;
register8_t reserved_0x35;
_WORDREGISTER(PERBUF); /* Period Buffer */
_WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
_WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
} TC1_t;

/*
--------------------------------------------------------------------------
TC - 16-bit Timer/Counter With PWM
--------------------------------------------------------------------------
*/

/* Advanced Waveform Extension */
typedef struct AWEX_struct
{
register8_t CTRL; /* Control Register */
register8_t reserved_0x01;
register8_t FDEVMASK; /* Fault Detection Event Mask */
register8_t FDCTRL; /* Fault Detection Control Register */
register8_t STATUS; /* Status Register */
register8_t reserved_0x05;
register8_t DTBOTH; /* Dead Time Both Sides */
register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */
register8_t DTLS; /* Dead Time Low Side */
register8_t DTHS; /* Dead Time High Side */
register8_t DTLSBUF; /* Dead Time Low Side Buffer */
register8_t DTHSBUF; /* Dead Time High Side Buffer */
register8_t OUTOVEN; /* Output Override Enable */
} AWEX_t;

/*
--------------------------------------------------------------------------
TC - 16-bit Timer/Counter With PWM
--------------------------------------------------------------------------
*/

/* High-Resolution Extension */
typedef struct HIRES_struct
{
register8_t CTRL; /* Control Register */
} HIRES_t;

/* Clock Selection */
typedef enum TC_CLKSEL_enum
{
TC_CLKSEL_OFF_gc = (0x00 & lt; & lt; 0), /* Timer Off */
TC_CLKSEL_DIV1_gc = (0x01 & lt; & lt; 0), /* System Clock */
TC_CLKSEL_DIV2_gc = (0x02 & lt; & lt; 0), /* System Clock / 2 */
TC_CLKSEL_DIV4_gc = (0x03 & lt; & lt; 0), /* System Clock / 4 */
TC_CLKSEL_DIV8_gc = (0x04 & lt; & lt; 0), /* System Clock / 8 */
TC_CLKSEL_DIV64_gc = (0x05 & lt; & lt; 0), /* System Clock / 64 */
TC_CLKSEL_DIV256_gc = (0x06 & lt; & lt; 0), /* System Clock / 256 */
TC_CLKSEL_DIV1024_gc = (0x07 & lt; & lt; 0), /* System Clock / 1024 */
TC_CLKSEL_EVCH0_gc = (0x08 & lt; & lt; 0), /* Event Channel 0 */
TC_CLKSEL_EVCH1_gc = (0x09 & lt; & lt; 0), /* Event Channel 1 */
TC_CLKSEL_EVCH2_gc = (0x0A & lt; & lt; 0), /* Event Channel 2 */
TC_CLKSEL_EVCH3_gc = (0x0B & lt; & lt; 0), /* Event Channel 3 */
TC_CLKSEL_EVCH4_gc = (0x0C & lt; & lt; 0), /* Event Channel 4 */
TC_CLKSEL_EVCH5_gc = (0x0D & lt; & lt; 0), /* Event Channel 5 */
TC_CLKSEL_EVCH6_gc = (0x0E & lt; & lt; 0), /* Event Channel 6 */
TC_CLKSEL_EVCH7_gc = (0x0F & lt; & lt; 0), /* Event Channel 7 */
} TC_CLKSEL_t;

/* Waveform Generation Mode */
typedef enum TC_WGMODE_enum
{
TC_WGMODE_NORMAL_gc = (0x00 & lt; & lt; 0), /* Normal Mode */
TC_WGMODE_FRQ_gc = (0x01 & lt; & lt; 0), /* Frequency Generation Mode */
TC_WGMODE_SS_gc = (0x03 & lt; & lt; 0), /* Single Slope */
TC_WGMODE_DS_T_gc = (0x05 & lt; & lt; 0), /* Dual Slope, Update on TOP */
TC_WGMODE_DS_TB_gc = (0x06 & lt; & lt; 0), /* Dual Slope, Update on TOP and BOTTOM */
TC_WGMODE_DS_B_gc = (0x07 & lt; & lt; 0), /* Dual Slope, Update on BOTTOM */
} TC_WGMODE_t;

/* Event Action */
typedef enum TC_EVACT_enum
{
TC_EVACT_OFF_gc = (0x00 & lt; & lt; 5), /* No Event Action */
TC_EVACT_CAPT_gc = (0x01 & lt; & lt; 5), /* Input Capture */
TC_EVACT_UPDOWN_gc = (0x02 & lt; & lt; 5), /* Externally Controlled Up/Down Count */
TC_EVACT_QDEC_gc = (0x03 & lt; & lt; 5), /* Quadrature Decode */
TC_EVACT_RESTART_gc = (0x04 & lt; & lt; 5), /* Restart */
TC_EVACT_FRW_gc = (0x05 & lt; & lt; 5), /* Frequency Capture */
TC_EVACT_PW_gc = (0x06 & lt; & lt; 5), /* Pulse-width Capture */
} TC_EVACT_t;

/* Event Selection */
typedef enum TC_EVSEL_enum
{
TC_EVSEL_OFF_gc = (0x00 & lt; & lt; 0), /* No Event Source */
TC_EVSEL_CH0_gc = (0x08 & lt; & lt; 0), /* Event Channel 0 */
TC_EVSEL_CH1_gc = (0x09 & lt; & lt; 0), /* Event Channel 1 */
TC_EVSEL_CH2_gc = (0x0A & lt; & lt; 0), /* Event Channel 2 */
TC_EVSEL_CH3_gc = (0x0B & lt; & lt; 0), /* Event Channel 3 */
TC_EVSEL_CH4_gc = (0x0C & lt; & lt; 0), /* Event Channel 4 */
TC_EVSEL_CH5_gc = (0x0D & lt; & lt; 0), /* Event Channel 5 */
TC_EVSEL_CH6_gc = (0x0E & lt; & lt; 0), /* Event Channel 6 */
TC_EVSEL_CH7_gc = (0x0F & lt; & lt; 0), /* Event Channel 7 */
} TC_EVSEL_t;

/* Error Interrupt Level */
typedef enum TC_ERRINTLVL_enum
{
TC_ERRINTLVL_OFF_gc = (0x00 & lt; & lt; 2), /* Interrupt Disabled */
TC_ERRINTLVL_LO_gc = (0x01 & lt; & lt; 2), /* Low Level */
TC_ERRINTLVL_MED_gc = (0x02 & lt; & lt; 2), /* Medium Level */
TC_ERRINTLVL_HI_gc = (0x03 & lt; & lt; 2), /* High Level */
} TC_ERRINTLVL_t;

/* Overflow Interrupt Level */
typedef enum TC_OVFINTLVL_enum
{
TC_OVFINTLVL_OFF_gc = (0x00 & lt; & lt; 0), /* Interrupt Disabled */
TC_OVFINTLVL_LO_gc = (0x01 & lt; & lt; 0), /* Low Level */
TC_OVFINTLVL_MED_gc = (0x02 & lt; & lt; 0), /* Medium Level */
TC_OVFINTLVL_HI_gc = (0x03 & lt; & lt; 0), /* High Level */
} TC_OVFINTLVL_t;

/* Compare or Capture D Interrupt Level */
typedef enum TC_CCDINTLVL_enum
{
TC_CCDINTLVL_OFF_gc = (0x00 & lt; & lt; 6), /* Interrupt Disabled */
TC_CCDINTLVL_LO_gc = (0x01 & lt; & lt; 6), /* Low Level */
TC_CCDINTLVL_MED_gc = (0x02 & lt; & lt; 6), /* Medium Level */
TC_CCDINTLVL_HI_gc = (0x03 & lt; & lt; 6), /* High Level */
} TC_CCDINTLVL_t;

/* Compare or Capture C Interrupt Level */
typedef enum TC_CCCINTLVL_enum
{
TC_CCCINTLVL_OFF_gc = (0x00 & lt; & lt; 4), /* Interrupt Disabled */
TC_CCCINTLVL_LO_gc = (0x01 & lt; & lt; 4), /* Low Level */
TC_CCCINTLVL_MED_gc = (0x02 & lt; & lt; 4), /* Medium Level */
TC_CCCINTLVL_HI_gc = (0x03 & lt; & lt; 4), /* High Level */
} TC_CCCINTLVL_t;

/* Compare or Capture B Interrupt Level */
typedef enum TC_CCBINTLVL_enum
{
TC_CCBINTLVL_OFF_gc = (0x00 & lt; & lt; 2), /* Interrupt Disabled */
TC_CCBINTLVL_LO_gc = (0x01 & lt; & lt; 2), /* Low Level */
TC_CCBINTLVL_MED_gc = (0x02 & lt; & lt; 2), /* Medium Level */
TC_CCBINTLVL_HI_gc = (0x03 & lt; & lt; 2), /* High Level */
} TC_CCBINTLVL_t;

/* Compare or Capture A Interrupt Level */
typedef enum TC_CCAINTLVL_enum
{
TC_CCAINTLVL_OFF_gc = (0x00 & lt; & lt; 0), /* Interrupt Disabled */
TC_CCAINTLVL_LO_gc = (0x01 & lt; & lt; 0), /* Low Level */
TC_CCAINTLVL_MED_gc = (0x02 & lt; & lt; 0), /* Medium Level */
TC_CCAINTLVL_HI_gc = (0x03 & lt; & lt; 0), /* High Level */
} TC_CCAINTLVL_t;

/* Timer/Counter Command */
typedef enum TC_CMD_enum
{
TC_CMD_NONE_gc = (0x00 & lt; & lt; 2), /* No Command */
TC_CMD_UPDATE_gc = (0x01 & lt; & lt; 2), /* Force Update */
TC_CMD_RESTART_gc = (0x02 & lt; & lt; 2), /* Force Restart */
TC_CMD_RESET_gc = (0x03 & lt; & lt; 2), /* Force Hard Reset */
} TC_CMD_t;

/* Fault Detect Action */
typedef enum AWEX_FDACT_enum
{
AWEX_FDACT_NONE_gc = (0x00 & lt; & lt; 0), /* No Fault Protection */
AWEX_FDACT_CLEAROE_gc = (0x01 & lt; & lt; 0), /* Clear Output Enable Bits */
AWEX_FDACT_CLEARDIR_gc = (0x03 & lt; & lt; 0), /* Clear I/O Port Direction Bits */
} AWEX_FDACT_t;

/* High Resolution Enable */
typedef enum HIRES_HREN_enum
{
HIRES_HREN_NONE_gc = (0x00 & lt; & lt; 0), /* No Fault Protection */
HIRES_HREN_TC0_gc = (0x01 & lt; & lt; 0), /* Enable High Resolution on Timer/Counter 0 */
HIRES_HREN_TC1_gc = (0x02 & lt; & lt; 0), /* Enable High Resolution on Timer/Counter 1 */
HIRES_HREN_BOTH_gc = (0x03 & lt; & lt; 0), /* Enable High Resolution both Timer/Counters */
} HIRES_HREN_t;


/*
--------------------------------------------------------------------------
USART - Universal Asynchronous Receiver-Transmitter
--------------------------------------------------------------------------
*/

/* Universal Synchronous/Asynchronous Receiver/Transmitter */
typedef struct USART_struct
{
register8_t DATA; /* Data Register */
register8_t STATUS; /* Status Register */
register8_t reserved_0x02;
register8_t CTRLA; /* Control Register A */
register8_t CTRLB; /* Control Register B */
register8_t CTRLC; /* Control Register C */
register8_t BAUDCTRLA; /* Baud Rate Control Register A */
register8_t BAUDCTRLB; /* Baud Rate Control Register B */
} USART_t;

/* Receive Complete Interrupt level */
typedef enum USART_RXCINTLVL_enum
{
USART_RXCINTLVL_OFF_gc = (0x00 & lt; & lt; 4), /* Interrupt Disabled */
USART_RXCINTLVL_LO_gc = (0x01 & lt; & lt; 4), /* Low Level */
USART_RXCINTLVL_MED_gc = (0x02 & lt; & lt; 4), /* Medium Level */
USART_RXCINTLVL_HI_gc = (0x03 & lt; & lt; 4), /* High Level */
} USART_RXCINTLVL_t;

/* Transmit Complete Interrupt level */
typedef enum USART_TXCINTLVL_enum
{
USART_TXCINTLVL_OFF_gc = (0x00 & lt; & lt; 2), /* Interrupt Disabled */
USART_TXCINTLVL_LO_gc = (0x01 & lt; & lt; 2), /* Low Level */
USART_TXCINTLVL_MED_gc = (0x02 & lt; & lt; 2), /* Medium Level */
USART_TXCINTLVL_HI_gc = (0x03 & lt; & lt; 2), /* High Level */
} USART_TXCINTLVL_t;

/* Data Register Empty Interrupt level */
typedef enum USART_DREINTLVL_enum
{
USART_DREINTLVL_OFF_gc = (0x00 & lt; & lt; 0), /* Interrupt Disabled */
USART_DREINTLVL_LO_gc = (0x01 & lt; & lt; 0), /* Low Level */
USART_DREINTLVL_MED_gc = (0x02 & lt; & lt; 0), /* Medium Level */
USART_DREINTLVL_HI_gc = (0x03 & lt; & lt; 0), /* High Level */
} USART_DREINTLVL_t;

/* Character Size */
typedef enum USART_CHSIZE_enum
{
USART_CHSIZE_5BIT_gc = (0x00 & lt; & lt; 0), /* Character size: 5 bit */
USART_CHSIZE_6BIT_gc = (0x01 & lt; & lt; 0), /* Character size: 6 bit */
USART_CHSIZE_7BIT_gc = (0x02 & lt; & lt; 0), /* Character size: 7 bit */
USART_CHSIZE_8BIT_gc = (0x03 & lt; & lt; 0), /* Character size: 8 bit */
USART_CHSIZE_9BIT_gc = (0x07 & lt; & lt; 0), /* Character size: 9 bit */
} USART_CHSIZE_t;

/* Communication Mode */
typedef enum USART_CMODE_enum
{
USART_CMODE_ASYNCHRONOUS_gc = (0x00 & lt; & lt; 6), /* Asynchronous Mode */
USART_CMODE_SYNCHRONOUS_gc = (0x01 & lt; & lt; 6), /* Synchronous Mode */
USART_CMODE_IRDA_gc = (0x02 & lt; & lt; 6), /* IrDA Mode */
USART_CMODE_MSPI_gc = (0x03 & lt; & lt; 6), /* Master SPI Mode */
} USART_CMODE_t;

/* Parity Mode */
typedef enum USART_PMODE_enum
{
USART_PMODE_DISABLED_gc = (0x00 & lt; & lt; 4), /* No Parity */
USART_PMODE_EVEN_gc = (0x02 & lt; & lt; 4), /* Even Parity */
USART_PMODE_ODD_gc = (0x03 & lt; & lt; 4), /* Odd Parity */
} USART_PMODE_t;


/*
--------------------------------------------------------------------------
SPI - Serial Peripheral Interface
--------------------------------------------------------------------------
*/

/* Serial Peripheral Interface */
typedef struct SPI_struct
{
register8_t CTRL; /* Control Register */
register8_t INTCTRL; /* Interrupt Control Register */
register8_t STATUS; /* Status Register */
register8_t DATA; /* Data Register */
} SPI_t;

/* SPI Mode */
typedef enum SPI_MODE_enum
{
SPI_MODE_0_gc = (0x00 & lt; & lt; 2), /* SPI Mode 0 */
SPI_MODE_1_gc = (0x01 & lt; & lt; 2), /* SPI Mode 1 */
SPI_MODE_2_gc = (0x02 & lt; & lt; 2), /* SPI Mode 2 */
SPI_MODE_3_gc = (0x03 & lt; & lt; 2), /* SPI Mode 3 */
} SPI_MODE_t;

/* Prescaler setting */
typedef enum SPI_PRESCALER_enum
{
SPI_PRESCALER_DIV4_gc = (0x00 & lt; & lt; 0), /* System Clock / 4 */
SPI_PRESCALER_DIV16_gc = (0x01 & lt; & lt; 0), /* System Clock / 16 */
SPI_PRESCALER_DIV64_gc = (0x02 & lt; & lt; 0), /* System Clock / 64 */
SPI_PRESCALER_DIV128_gc = (0x03 & lt; & lt; 0), /* System Clock / 128 */
} SPI_PRESCALER_t;

/* Interrupt level */
typedef enum SPI_INTLVL_enum
{
SPI_INTLVL_OFF_gc = (0x00 & lt; & lt; 0), /* Interrupt Disabled */
SPI_INTLVL_LO_gc = (0x01 & lt; & lt; 0), /* Low Level */
SPI_INTLVL_MED_gc = (0x02 & lt; & lt; 0), /* Medium Level */
SPI_INTLVL_HI_gc = (0x03 & lt; & lt; 0), /* High Level */
} SPI_INTLVL_t;


/*
--------------------------------------------------------------------------
IRCOM - IR Communication Module
--------------------------------------------------------------------------
*/

/* IR Communication Module */
typedef struct IRCOM_struct
{
register8_t CTRL; /* Control Register */
register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */
register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */
} IRCOM_t;

/* Event channel selection */
typedef enum IRDA_EVSEL_enum
{
IRDA_EVSEL_OFF_gc = (0x00 & lt; & lt; 0), /* No Event Source */
IRDA_EVSEL_0_gc = (0x08 & lt; & lt; 0), /* Event Channel 0 */
IRDA_EVSEL_1_gc = (0x09 & lt; & lt; 0), /* Event Channel 1 */
IRDA_EVSEL_2_gc = (0x0A & lt; & lt; 0), /* Event Channel 2 */
IRDA_EVSEL_3_gc = (0x0B & lt; & lt; 0), /* Event Channel 3 */
IRDA_EVSEL_4_gc = (0x0C & lt; & lt; 0), /* Event Channel 4 */
IRDA_EVSEL_5_gc = (0x0D & lt; & lt; 0), /* Event Channel 5 */
IRDA_EVSEL_6_gc = (0x0E & lt; & lt; 0), /* Event Channel 6 */
IRDA_EVSEL_7_gc = (0x0F & lt; & lt; 0), /* Event Channel 7 */
} IRDA_EVSEL_t;


/*
--------------------------------------------------------------------------
AES - AES Module
--------------------------------------------------------------------------
*/

/* AES Module */
typedef struct AES_struct
{
register8_t CTRL; /* AES Control Register */
register8_t STATUS; /* AES Status Register */
register8_t STATE; /* AES State Register */
register8_t KEY; /* AES Key Register */
register8_t INTCTRL; /* AES Interrupt Control Register */
} AES_t;

/* Interrupt level */
typedef enum AES_INTLVL_enum
{
AES_INTLVL_OFF_gc = (0x00 & lt; & lt; 0), /* Interrupt Disabled */
AES_INTLVL_LO_gc = (0x01 & lt; & lt; 0), /* Low Level */
AES_INTLVL_MED_gc = (0x02 & lt; & lt; 0), /* Medium Level */
AES_INTLVL_HI_gc = (0x03 & lt; & lt; 0), /* High Level */
} AES_INTLVL_t;



/*
==========================================================================
IO Module Instances. Mapped to memory.
==========================================================================
*/

#define GPIO (*(GPIO_t *) 0x0000) /* General Purpose IO Registers */
#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */
#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */
#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */
#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */
#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */
#define CPU (*(CPU_t *) 0x0030) /* CPU Registers */
#define CLK (*(CLK_t *) 0x0040) /* Clock System */
#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */
#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */
#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */
#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */
#define PR (*(PR_t *) 0x0070) /* Power Reduction */
#define RST (*(RST_t *) 0x0078) /* Reset Controller */
#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */
#define MCU (*(MCU_t *) 0x0090) /* MCU Control */
#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */
#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */
#define AES (*(AES_t *) 0x00C0) /* AES Crypto Module */
#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */
#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */
#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */
#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */
#define ADCB (*(ADC_t *) 0x0240) /* Analog to Digital Converter B */
#define DACA (*(DAC_t *) 0x0300) /* Digital to Analog Converter A */
#define DACB (*(DAC_t *) 0x0320) /* Digital to Analog Converter B */
#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */
#define ACB (*(AC_t *) 0x0390) /* Analog Comparator B */
#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */
#define EBI (*(EBI_t *) 0x0440) /* External Bus Interface */
#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */
#define TWID (*(TWI_t *) 0x0490) /* Two-Wire Interface D */
#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */
#define TWIF (*(TWI_t *) 0x04B0) /* Two-Wire Interface F */
#define PORTA (*(PORT_t *) 0x0600) /* Port A */
#define PORTB (*(PORT_t *) 0x0620) /* Port B */
#define PORTC (*(PORT_t *) 0x0640) /* Port C */
#define PORTD (*(PORT_t *) 0x0660) /* Port D */
#define PORTE (*(PORT_t *) 0x0680) /* Port E */
#define PORTF (*(PORT_t *) 0x06A0) /* Port F */
#define PORTH (*(PORT_t *) 0x06E0) /* Port H */
#define PORTJ (*(PORT_t *) 0x0700) /* Port J */
#define PORTK (*(PORT_t *) 0x0720) /* Port K */
#define PORTQ (*(PORT_t *) 0x07C0) /* Port Q */
#define PORTR (*(PORT_t *) 0x07E0) /* Port R */
#define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */
#define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */
#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */
#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */
#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */
#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Asynchronous Receiver-Transmitter C1 */
#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */
#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */
#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */
#define TCD1 (*(TC1_t *) 0x0940) /* Timer/Counter D1 */
#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension D */
#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */
#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Asynchronous Receiver-Transmitter D1 */
#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */
#define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */
#define TCE1 (*(TC1_t *) 0x0A40) /* Timer/Counter E1 */
#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension E */
#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension E */
#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */
#define USARTE1 (*(USART_t *) 0x0AB0) /* Universal Asynchronous Receiver-Transmitter E1 */
#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface E */
#define TCF0 (*(TC0_t *) 0x0B00) /* Timer/Counter F0 */
#define TCF1 (*(TC1_t *) 0x0B40) /* Timer/Counter F1 */
#define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension F */
#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Asynchronous Receiver-Transmitter F0 */
#define USARTF1 (*(USART_t *) 0x0BB0) /* Universal Asynchronous Receiver-Transmitter F1 */
#define SPIF (*(SPI_t *) 0x0BC0) /* Serial Peripheral Interface F */


#endif /* !defined (__ASSEMBLER__) */


/* ========== Flattened fully qualified IO register names ========== */

/* GPIO - General Purpose IO Registers */
#define GPIO_GPIO0 _SFR_MEM8(0x0000)
#define GPIO_GPIO1 _SFR_MEM8(0x0001)
#define GPIO_GPIO2 _SFR_MEM8(0x0002)
#define GPIO_GPIO3 _SFR_MEM8(0x0003)
#define GPIO_GPIO4 _SFR_MEM8(0x0004)
#define GPIO_GPIO5 _SFR_MEM8(0x0005)
#define GPIO_GPIO6 _SFR_MEM8(0x0006)
#define GPIO_GPIO7 _SFR_MEM8(0x0007)
#define GPIO_GPIO8 _SFR_MEM8(0x0008)
#define GPIO_GPIO9 _SFR_MEM8(0x0009)
#define GPIO_GPIOA _SFR_MEM8(0x000A)
#define GPIO_GPIOB _SFR_MEM8(0x000B)
#define GPIO_GPIOC _SFR_MEM8(0x000C)
#define GPIO_GPIOD _SFR_MEM8(0x000D)
#define GPIO_GPIOE _SFR_MEM8(0x000E)
#define GPIO_GPIOF _SFR_MEM8(0x000F)

/* VPORT0 - Virtual Port 0 */
#define VPORT0_DIR _SFR_MEM8(0x0010)
#define VPORT0_OUT _SFR_MEM8(0x0011)
#define VPORT0_IN _SFR_MEM8(0x0012)
#define VPORT0_INTFLAGS _SFR_MEM8(0x0013)

/* VPORT1 - Virtual Port 1 */
#define VPORT1_DIR _SFR_MEM8(0x0014)
#define VPORT1_OUT _SFR_MEM8(0x0015)
#define VPORT1_IN _SFR_MEM8(0x0016)
#define VPORT1_INTFLAGS _SFR_MEM8(0x0017)

/* VPORT2 - Virtual Port 2 */
#define VPORT2_DIR _SFR_MEM8(0x0018)
#define VPORT2_OUT _SFR_MEM8(0x0019)
#define VPORT2_IN _SFR_MEM8(0x001A)
#define VPORT2_INTFLAGS _SFR_MEM8(0x001B)

/* VPORT3 - Virtual Port 3 */
#define VPORT3_DIR _SFR_MEM8(0x001C)
#define VPORT3_OUT _SFR_MEM8(0x001D)
#define VPORT3_IN _SFR_MEM8(0x001E)
#define VPORT3_INTFLAGS _SFR_MEM8(0x001F)

/* OCD - On-Chip Debug System */
#define OCD_OCDR0 _SFR_MEM8(0x002E)
#define OCD_OCDR1 _SFR_MEM8(0x002F)

/* CPU - CPU Registers */
#define CPU_CCP _SFR_MEM8(0x0034)
#define CPU_RAMPD _SFR_MEM8(0x0038)
#define CPU_RAMPX _SFR_MEM8(0x0039)
#define CPU_RAMPY _SFR_MEM8(0x003A)
#define CPU_RAMPZ _SFR_MEM8(0x003B)
#define CPU_EIND _SFR_MEM8(0x003C)
#define CPU_SPL _SFR_MEM8(0x003D)
#define CPU_SPH _SFR_MEM8(0x003E)
#define CPU_SREG _SFR_MEM8(0x003F)

/* CLK - Clock System */
#define CLK_CTRL _SFR_MEM8(0x0040)
#define CLK_PSCTRL _SFR_MEM8(0x0041)
#define CLK_LOCK _SFR_MEM8(0x0042)
#define CLK_RTCCTRL _SFR_MEM8(0x0043)

/* SLEEP - Sleep Controller */
#define SLEEP_CTRL _SFR_MEM8(0x0048)

/* OSC - Oscillator Control */
#define OSC_CTRL _SFR_MEM8(0x0050)
#define OSC_STATUS _SFR_MEM8(0x0051)
#define OSC_XOSCCTRL _SFR_MEM8(0x0052)
#define OSC_XOSCFAIL _SFR_MEM8(0x0053)
#define OSC_RC32KCAL _SFR_MEM8(0x0054)
#define OSC_PLLCTRL _SFR_MEM8(0x0055)
#define OSC_DFLLCTRL _SFR_MEM8(0x0056)

/* DFLLRC32M - DFLL for 32MHz RC Oscillator */
#define DFLLRC32M_CTRL _SFR_MEM8(0x0060)
#define DFLLRC32M_CALA _SFR_MEM8(0x0062)
#define DFLLRC32M_CALB _SFR_MEM8(0x0063)
#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064)
#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065)
#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066)

/* DFLLRC2M - DFLL for 2MHz RC Oscillator */
#define DFLLRC2M_CTRL _SFR_MEM8(0x0068)
#define DFLLRC2M_CALA _SFR_MEM8(0x006A)
#define DFLLRC2M_CALB _SFR_MEM8(0x006B)
#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C)
#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D)
#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E)

/* PR - Power Reduction */
#define PR_PRGEN _SFR_MEM8(0x0070)
#define PR_PRPA _SFR_MEM8(0x0071)
#define PR_PRPB _SFR_MEM8(0x0072)
#define PR_PRPC _SFR_MEM8(0x0073)
#define PR_PRPD _SFR_MEM8(0x0074)
#define PR_PRPE _SFR_MEM8(0x0075)
#define PR_PRPF _SFR_MEM8(0x0076)

/* RST - Reset Controller */
#define RST_STATUS _SFR_MEM8(0x0078)
#define RST_CTRL _SFR_MEM8(0x0079)

/* WDT - Watch-Dog Timer */
#define WDT_CTRL _SFR_MEM8(0x0080)
#define WDT_WINCTRL _SFR_MEM8(0x0081)
#define WDT_STATUS _SFR_MEM8(0x0082)

/* MCU - MCU Control */
#define MCU_DEVID0 _SFR_MEM8(0x0090)
#define MCU_DEVID1 _SFR_MEM8(0x0091)
#define MCU_DEVID2 _SFR_MEM8(0x0092)
#define MCU_REVID _SFR_MEM8(0x0093)
#define MCU_JTAGUID _SFR_MEM8(0x0094)
#define MCU_MCUCR _SFR_MEM8(0x0096)
#define MCU_EVSYSLOCK _SFR_MEM8(0x0098)
#define MCU_AWEXLOCK _SFR_MEM8(0x0099)

/* PMIC - Programmable Interrupt Controller */
#define PMIC_STATUS _SFR_MEM8(0x00A0)
#define PMIC_INTPRI _SFR_MEM8(0x00A1)
#define PMIC_CTRL _SFR_MEM8(0x00A2)

/* PORTCFG - Port Configuration */
#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0)
#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2)
#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3)
#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4)

/* AES - AES Crypto Module */
#define AES_CTRL _SFR_MEM8(0x00C0)
#define AES_STATUS _SFR_MEM8(0x00C1)
#define AES_STATE _SFR_MEM8(0x00C2)
#define AES_KEY _SFR_MEM8(0x00C3)
#define AES_INTCTRL _SFR_MEM8(0x00C4)

/* DMA - DMA Controller */
#define DMA_CTRL _SFR_MEM8(0x0100)
#define DMA_INTFLAGS _SFR_MEM8(0x0103)
#define DMA_STATUS _SFR_MEM8(0x0104)
#define DMA_TEMP _SFR_MEM16(0x0106)
#define DMA_CH0_CTRLA _SFR_MEM8(0x0110)
#define DMA_CH0_CTRLB _SFR_MEM8(0x0111)
#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112)
#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113)
#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114)
#define DMA_CH0_REPCNT _SFR_MEM8(0x0116)
#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118)
#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119)
#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A)
#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C)
#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D)
#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E)
#define DMA_CH1_CTRLA _SFR_MEM8(0x0120)
#define DMA_CH1_CTRLB _SFR_MEM8(0x0121)
#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122)
#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123)
#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124)
#define DMA_CH1_REPCNT _SFR_MEM8(0x0126)
#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128)
#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129)
#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A)
#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C)
#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D)
#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E)
#define DMA_CH2_CTRLA _SFR_MEM8(0x0130)
#define DMA_CH2_CTRLB _SFR_MEM8(0x0131)
#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132)
#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133)
#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134)
#define DMA_CH2_REPCNT _SFR_MEM8(0x0136)
#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138)
#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139)
#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A)
#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C)
#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D)
#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E)
#define DMA_CH3_CTRLA _SFR_MEM8(0x0140)
#define DMA_CH3_CTRLB _SFR_MEM8(0x0141)
#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142)
#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143)
#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144)
#define DMA_CH3_REPCNT _SFR_MEM8(0x0146)
#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148)
#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149)
#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A)
#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C)
#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D)
#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E)

/* EVSYS - Event System */
#define EVSYS_CH0MUX _SFR_MEM8(0x0180)
#define EVSYS_CH1MUX _SFR_MEM8(0x0181)
#define EVSYS_CH2MUX _SFR_MEM8(0x0182)
#define EVSYS_CH3MUX _SFR_MEM8(0x0183)
#define EVSYS_CH4MUX _SFR_MEM8(0x0184)
#define EVSYS_CH5MUX _SFR_MEM8(0x0185)
#define EVSYS_CH6MUX _SFR_MEM8(0x0186)
#define EVSYS_CH7MUX _SFR_MEM8(0x0187)
#define EVSYS_CH0CTRL _SFR_MEM8(0x0188)
#define EVSYS_CH1CTRL _SFR_MEM8(0x0189)
#define EVSYS_CH2CTRL _SFR_MEM8(0x018A)
#define EVSYS_CH3CTRL _SFR_MEM8(0x018B)
#define EVSYS_CH4CTRL _SFR_MEM8(0x018C)
#define EVSYS_CH5CTRL _SFR_MEM8(0x018D)
#define EVSYS_CH6CTRL _SFR_MEM8(0x018E)
#define EVSYS_CH7CTRL _SFR_MEM8(0x018F)
#define EVSYS_STROBE _SFR_MEM8(0x0190)
#define EVSYS_DATA _SFR_MEM8(0x0191)

/* NVM - Non Volatile Memory Controller */
#define NVM_ADDR0 _SFR_MEM8(0x01C0)
#define NVM_ADDR1 _SFR_MEM8(0x01C1)
#define NVM_ADDR2 _SFR_MEM8(0x01C2)
#define NVM_DATA0 _SFR_MEM8(0x01C4)
#define NVM_DATA1 _SFR_MEM8(0x01C5)
#define NVM_DATA2 _SFR_MEM8(0x01C6)
#define NVM_CMD _SFR_MEM8(0x01CA)
#define NVM_CTRLA _SFR_MEM8(0x01CB)
#define NVM_CTRLB _SFR_MEM8(0x01CC)
#define NVM_INTCTRL _SFR_MEM8(0x01CD)
#define NVM_STATUS _SFR_MEM8(0x01CF)
#define NVM_LOCKBITS _SFR_MEM8(0x01D0)

/* ADCA - Analog to Digital Converter A */
#define ADCA_CTRLA _SFR_MEM8(0x0200)
#define ADCA_CTRLB _SFR_MEM8(0x0201)
#define ADCA_REFCTRL _SFR_MEM8(0x0202)
#define ADCA_EVCTRL _SFR_MEM8(0x0203)
#define ADCA_PRESCALER _SFR_MEM8(0x0204)
#define ADCA_CALCTRL _SFR_MEM8(0x0205)
#define ADCA_INTFLAGS _SFR_MEM8(0x0206)
#define ADCA_CAL _SFR_MEM16(0x020C)
#define ADCA_CH0RES _SFR_MEM16(0x0210)
#define ADCA_CH1RES _SFR_MEM16(0x0212)
#define ADCA_CH2RES _SFR_MEM16(0x0214)
#define ADCA_CH3RES _SFR_MEM16(0x0216)
#define ADCA_CMP _SFR_MEM16(0x0218)
#define ADCA_CH0_CTRL _SFR_MEM8(0x0220)
#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221)
#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222)
#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223)
#define ADCA_CH0_RES _SFR_MEM16(0x0224)
#define ADCA_CH1_CTRL _SFR_MEM8(0x0228)
#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229)
#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A)
#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B)
#define ADCA_CH1_RES _SFR_MEM16(0x022C)
#define ADCA_CH2_CTRL _SFR_MEM8(0x0230)
#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231)
#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232)
#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233)
#define ADCA_CH2_RES _SFR_MEM16(0x0234)
#define ADCA_CH3_CTRL _SFR_MEM8(0x0238)
#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239)
#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A)
#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B)
#define ADCA_CH3_RES _SFR_MEM16(0x023C)

/* ADCB - Analog to Digital Converter B */
#define ADCB_CTRLA _SFR_MEM8(0x0240)
#define ADCB_CTRLB _SFR_MEM8(0x0241)
#define ADCB_REFCTRL _SFR_MEM8(0x0242)
#define ADCB_EVCTRL _SFR_MEM8(0x0243)
#define ADCB_PRESCALER _SFR_MEM8(0x0244)
#define ADCB_CALCTRL _SFR_MEM8(0x0245)
#define ADCB_INTFLAGS _SFR_MEM8(0x0246)
#define ADCB_CAL _SFR_MEM16(0x024C)
#define ADCB_CH0RES _SFR_MEM16(0x0250)
#define ADCB_CH1RES _SFR_MEM16(0x0252)
#define ADCB_CH2RES _SFR_MEM16(0x0254)
#define ADCB_CH3RES _SFR_MEM16(0x0256)
#define ADCB_CMP _SFR_MEM16(0x0258)
#define ADCB_CH0_CTRL _SFR_MEM8(0x0260)
#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261)
#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262)
#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263)
#define ADCB_CH0_RES _SFR_MEM16(0x0264)
#define ADCB_CH1_CTRL _SFR_MEM8(0x0268)
#define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269)
#define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A)
#define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B)
#define ADCB_CH1_RES _SFR_MEM16(0x026C)
#define ADCB_CH2_CTRL _SFR_MEM8(0x0270)
#define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271)
#define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272)
#define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273)
#define ADCB_CH2_RES _SFR_MEM16(0x0274)
#define ADCB_CH3_CTRL _SFR_MEM8(0x0278)
#define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279)
#define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A)
#define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B)
#define ADCB_CH3_RES _SFR_MEM16(0x027C)

/* DACA - Digital to Analog Converter A */
#define DACA_CTRLA _SFR_MEM8(0x0300)
#define DACA_CTRLB _SFR_MEM8(0x0301)
#define DACA_CTRLC _SFR_MEM8(0x0302)
#define DACA_EVCTRL _SFR_MEM8(0x0303)
#define DACA_TIMCTRL _SFR_MEM8(0x0304)
#define DACA_STATUS _SFR_MEM8(0x0305)
#define DACA_GAINCAL _SFR_MEM8(0x0308)
#define DACA_OFFSETCAL _SFR_MEM8(0x0309)
#define DACA_CH0DATA _SFR_MEM16(0x0318)
#define DACA_CH1DATA _SFR_MEM16(0x031A)

/* DACB - Digital to Analog Converter B */
#define DACB_CTRLA _SFR_MEM8(0x0320)
#define DACB_CTRLB _SFR_MEM8(0x0321)
#define DACB_CTRLC _SFR_MEM8(0x0322)
#define DACB_EVCTRL _SFR_MEM8(0x0323)
#define DACB_TIMCTRL _SFR_MEM8(0x0324)
#define DACB_STATUS _SFR_MEM8(0x0325)
#define DACB_GAINCAL _SFR_MEM8(0x0328)
#define DACB_OFFSETCAL _SFR_MEM8(0x0329)
#define DACB_CH0DATA _SFR_MEM16(0x0338)
#define DACB_CH1DATA _SFR_MEM16(0x033A)

/* ACA - Analog Comparator A */
#define ACA_AC0CTRL _SFR_MEM8(0x0380)
#define ACA_AC1CTRL _SFR_MEM8(0x0381)
#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382)
#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383)
#define ACA_CTRLA _SFR_MEM8(0x0384)
#define ACA_CTRLB _SFR_MEM8(0x0385)
#define ACA_WINCTRL _SFR_MEM8(0x0386)
#define ACA_STATUS _SFR_MEM8(0x0387)

/* ACB - Analog Comparator B */
#define ACB_AC0CTRL _SFR_MEM8(0x0390)
#define ACB_AC1CTRL _SFR_MEM8(0x0391)
#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392)
#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393)
#define ACB_CTRLA _SFR_MEM8(0x0394)
#define ACB_CTRLB _SFR_MEM8(0x0395)
#define ACB_WINCTRL _SFR_MEM8(0x0396)
#define ACB_STATUS _SFR_MEM8(0x0397)

/* RTC - Real-Time Counter */
#define RTC_CTRL _SFR_MEM8(0x0400)
#define RTC_STATUS _SFR_MEM8(0x0401)
#define RTC_INTCTRL _SFR_MEM8(0x0402)
#define RTC_INTFLAGS _SFR_MEM8(0x0403)
#define RTC_TEMP _SFR_MEM8(0x0404)
#define RTC_CNT _SFR_MEM16(0x0408)
#define RTC_PER _SFR_MEM16(0x040A)
#define RTC_COMP _SFR_MEM16(0x040C)

/* EBI - External Bus Interface */
#define EBI_CTRL _SFR_MEM8(0x0440)
#define EBI_SDRAMCTRLA _SFR_MEM8(0x0441)
#define EBI_REFRESH _SFR_MEM16(0x0444)
#define EBI_INITDLY _SFR_MEM16(0x0446)
#define EBI_SDRAMCTRLB _SFR_MEM8(0x0448)
#define EBI_SDRAMCTRLC _SFR_MEM8(0x0449)
#define EBI_CS0_CTRLA _SFR_MEM8(0x0450)
#define EBI_CS0_CTRLB _SFR_MEM8(0x0451)
#define EBI_CS0_BASEADDR _SFR_MEM16(0x0452)
#define EBI_CS1_CTRLA _SFR_MEM8(0x0454)
#define EBI_CS1_CTRLB _SFR_MEM8(0x0455)
#define EBI_CS1_BASEADDR _SFR_MEM16(0x0456)
#define EBI_CS2_CTRLA _SFR_MEM8(0x0458)
#define EBI_CS2_CTRLB _SFR_MEM8(0x0459)
#define EBI_CS2_BASEADDR _SFR_MEM16(0x045A)
#define EBI_CS3_CTRLA _SFR_MEM8(0x045C)
#define EBI_CS3_CTRLB _SFR_MEM8(0x045D)
#define EBI_CS3_BASEADDR _SFR_MEM16(0x045E)

/* TWIC - Two-Wire Interface C */
#define TWIC_CTRL _SFR_MEM8(0x0480)
#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481)
#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482)
#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483)
#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484)
#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485)
#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486)
#define TWIC_MASTER_DATA _SFR_MEM8(0x0487)
#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488)
#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489)
#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A)
#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B)
#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C)
#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D)

/* TWID - Two-Wire Interface D */
#define TWID_CTRL _SFR_MEM8(0x0490)
#define TWID_MASTER_CTRLA _SFR_MEM8(0x0491)
#define TWID_MASTER_CTRLB _SFR_MEM8(0x0492)
#define TWID_MASTER_CTRLC _SFR_MEM8(0x0493)
#define TWID_MASTER_STATUS _SFR_MEM8(0x0494)
#define TWID_MASTER_BAUD _SFR_MEM8(0x0495)
#define TWID_MASTER_ADDR _SFR_MEM8(0x0496)
#define TWID_MASTER_DATA _SFR_MEM8(0x0497)
#define TWID_SLAVE_CTRLA _SFR_MEM8(0x0498)
#define TWID_SLAVE_CTRLB _SFR_MEM8(0x0499)
#define TWID_SLAVE_STATUS _SFR_MEM8(0x049A)
#define TWID_SLAVE_ADDR _SFR_MEM8(0x049B)
#define TWID_SLAVE_DATA _SFR_MEM8(0x049C)
#define TWID_SLAVE_ADDRMASK _SFR_MEM8(0x049D)

/* TWIE - Two-Wire Interface E */
#define TWIE_CTRL _SFR_MEM8(0x04A0)
#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1)
#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2)
#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3)
#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4)
#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5)
#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6)
#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7)
#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8)
#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9)
#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA)
#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB)
#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC)
#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD)

/* TWIF - Two-Wire Interface F */
#define TWIF_CTRL _SFR_MEM8(0x04B0)
#define TWIF_MASTER_CTRLA _SFR_MEM8(0x04B1)
#define TWIF_MASTER_CTRLB _SFR_MEM8(0x04B2)
#define TWIF_MASTER_CTRLC _SFR_MEM8(0x04B3)
#define TWIF_MASTER_STATUS _SFR_MEM8(0x04B4)
#define TWIF_MASTER_BAUD _SFR_MEM8(0x04B5)
#define TWIF_MASTER_ADDR _SFR_MEM8(0x04B6)
#define TWIF_MASTER_DATA _SFR_MEM8(0x04B7)
#define TWIF_SLAVE_CTRLA _SFR_MEM8(0x04B8)
#define TWIF_SLAVE_CTRLB _SFR_MEM8(0x04B9)
#define TWIF_SLAVE_STATUS _SFR_MEM8(0x04BA)
#define TWIF_SLAVE_ADDR _SFR_MEM8(0x04BB)
#define TWIF_SLAVE_DATA _SFR_MEM8(0x04BC)
#define TWIF_SLAVE_ADDRMASK _SFR_MEM8(0x04BD)

/* PORTA - Port A */
#define PORTA_DIR _SFR_MEM8(0x0600)
#define PORTA_DIRSET _SFR_MEM8(0x0601)
#define PORTA_DIRCLR _SFR_MEM8(0x0602)
#define PORTA_DIRTGL _SFR_MEM8(0x0603)
#define PORTA_OUT _SFR_MEM8(0x0604)
#define PORTA_OUTSET _SFR_MEM8(0x0605)
#define PORTA_OUTCLR _SFR_MEM8(0x0606)
#define PORTA_OUTTGL _SFR_MEM8(0x0607)
#define PORTA_IN _SFR_MEM8(0x0608)
#define PORTA_INTCTRL _SFR_MEM8(0x0609)
#define PORTA_INT0MASK _SFR_MEM8(0x060A)
#define PORTA_INT1MASK _SFR_MEM8(0x060B)
#define PORTA_INTFLAGS _SFR_MEM8(0x060C)
#define PORTA_PIN0CTRL _SFR_MEM8(0x0610)
#define PORTA_PIN1CTRL _SFR_MEM8(0x0611)
#define PORTA_PIN2CTRL _SFR_MEM8(0x0612)
#define PORTA_PIN3CTRL _SFR_MEM8(0x0613)
#define PORTA_PIN4CTRL _SFR_MEM8(0x0614)
#define PORTA_PIN5CTRL _SFR_MEM8(0x0615)
#define PORTA_PIN6CTRL _SFR_MEM8(0x0616)
#define PORTA_PIN7CTRL _SFR_MEM8(0x0617)

/* PORTB - Port B */
#define PORTB_DIR _SFR_MEM8(0x0620)
#define PORTB_DIRSET _SFR_MEM8(0x0621)
#define PORTB_DIRCLR _SFR_MEM8(0x0622)
#define PORTB_DIRTGL _SFR_MEM8(0x0623)
#define PORTB_OUT _SFR_MEM8(0x0624)
#define PORTB_OUTSET _SFR_MEM8(0x0625)
#define PORTB_OUTCLR _SFR_MEM8(0x0626)
#define PORTB_OUTTGL _SFR_MEM8(0x0627)
#define PORTB_IN _SFR_MEM8(0x0628)
#define PORTB_INTCTRL _SFR_MEM8(0x0629)
#define PORTB_INT0MASK _SFR_MEM8(0x062A)
#define PORTB_INT1MASK _SFR_MEM8(0x062B)
#define PORTB_INTFLAGS _SFR_MEM8(0x062C)
#define PORTB_PIN0CTRL _SFR_MEM8(0x0630)
#define PORTB_PIN1CTRL _SFR_MEM8(0x0631)
#define PORTB_PIN2CTRL _SFR_MEM8(0x0632)
#define PORTB_PIN3CTRL _SFR_MEM8(0x0633)
#define PORTB_PIN4CTRL _SFR_MEM8(0x0634)
#define PORTB_PIN5CTRL _SFR_MEM8(0x0635)
#define PORTB_PIN6CTRL _SFR_MEM8(0x0636)
#define PORTB_PIN7CTRL _SFR_MEM8(0x0637)

/* PORTC - Port C */
#define PORTC_DIR _SFR_MEM8(0x0640)
#define PORTC_DIRSET _SFR_MEM8(0x0641)
#define PORTC_DIRCLR _SFR_MEM8(0x0642)
#define PORTC_DIRTGL _SFR_MEM8(0x0643)
#define PORTC_OUT _SFR_MEM8(0x0644)
#define PORTC_OUTSET _SFR_MEM8(0x0645)
#define PORTC_OUTCLR _SFR_MEM8(0x0646)
#define PORTC_OUTTGL _SFR_MEM8(0x0647)
#define PORTC_IN _SFR_MEM8(0x0648)
#define PORTC_INTCTRL _SFR_MEM8(0x0649)
#define PORTC_INT0MASK _SFR_MEM8(0x064A)
#define PORTC_INT1MASK _SFR_MEM8(0x064B)
#define PORTC_INTFLAGS _SFR_MEM8(0x064C)
#define PORTC_PIN0CTRL _SFR_MEM8(0x0650)
#define PORTC_PIN1CTRL _SFR_MEM8(0x0651)
#define PORTC_PIN2CTRL _SFR_MEM8(0x0652)
#define PORTC_PIN3CTRL _SFR_MEM8(0x0653)
#define PORTC_PIN4CTRL _SFR_MEM8(0x0654)
#define PORTC_PIN5CTRL _SFR_MEM8(0x0655)
#define PORTC_PIN6CTRL _SFR_MEM8(0x0656)
#define PORTC_PIN7CTRL _SFR_MEM8(0x0657)

/* PORTD - Port D */
#define PORTD_DIR _SFR_MEM8(0x0660)
#define PORTD_DIRSET _SFR_MEM8(0x0661)
#define PORTD_DIRCLR _SFR_MEM8(0x0662)
#define PORTD_DIRTGL _SFR_MEM8(0x0663)
#define PORTD_OUT _SFR_MEM8(0x0664)
#define PORTD_OUTSET _SFR_MEM8(0x0665)
#define PORTD_OUTCLR _SFR_MEM8(0x0666)
#define PORTD_OUTTGL _SFR_MEM8(0x0667)
#define PORTD_IN _SFR_MEM8(0x0668)
#define PORTD_INTCTRL _SFR_MEM8(0x0669)
#define PORTD_INT0MASK _SFR_MEM8(0x066A)
#define PORTD_INT1MASK _SFR_MEM8(0x066B)
#define PORTD_INTFLAGS _SFR_MEM8(0x066C)
#define PORTD_PIN0CTRL _SFR_MEM8(0x0670)
#define PORTD_PIN1CTRL _SFR_MEM8(0x0671)
#define PORTD_PIN2CTRL _SFR_MEM8(0x0672)
#define PORTD_PIN3CTRL _SFR_MEM8(0x0673)
#define PORTD_PIN4CTRL _SFR_MEM8(0x0674)
#define PORTD_PIN5CTRL _SFR_MEM8(0x0675)
#define PORTD_PIN6CTRL _SFR_MEM8(0x0676)
#define PORTD_PIN7CTRL _SFR_MEM8(0x0677)

/* PORTE - Port E */
#define PORTE_DIR _SFR_MEM8(0x0680)
#define PORTE_DIRSET _SFR_MEM8(0x0681)
#define PORTE_DIRCLR _SFR_MEM8(0x0682)
#define PORTE_DIRTGL _SFR_MEM8(0x0683)
#define PORTE_OUT _SFR_MEM8(0x0684)
#define PORTE_OUTSET _SFR_MEM8(0x0685)
#define PORTE_OUTCLR _SFR_MEM8(0x0686)
#define PORTE_OUTTGL _SFR_MEM8(0x0687)
#define PORTE_IN _SFR_MEM8(0x0688)
#define PORTE_INTCTRL _SFR_MEM8(0x0689)
#define PORTE_INT0MASK _SFR_MEM8(0x068A)
#define PORTE_INT1MASK _SFR_MEM8(0x068B)
#define PORTE_INTFLAGS _SFR_MEM8(0x068C)
#define PORTE_PIN0CTRL _SFR_MEM8(0x0690)
#define PORTE_PIN1CTRL _SFR_MEM8(0x0691)
#define PORTE_PIN2CTRL _SFR_MEM8(0x0692)
#define PORTE_PIN3CTRL _SFR_MEM8(0x0693)
#define PORTE_PIN4CTRL _SFR_MEM8(0x0694)
#define PORTE_PIN5CTRL _SFR_MEM8(0x0695)
#define PORTE_PIN6CTRL _SFR_MEM8(0x0696)
#define PORTE_PIN7CTRL _SFR_MEM8(0x0697)

/* PORTF - Port F */
#define PORTF_DIR _SFR_MEM8(0x06A0)
#define PORTF_DIRSET _SFR_MEM8(0x06A1)
#define PORTF_DIRCLR _SFR_MEM8(0x06A2)
#define PORTF_DIRTGL _SFR_MEM8(0x06A3)
#define PORTF_OUT _SFR_MEM8(0x06A4)
#define PORTF_OUTSET _SFR_MEM8(0x06A5)
#define PORTF_OUTCLR _SFR_MEM8(0x06A6)
#define PORTF_OUTTGL _SFR_MEM8(0x06A7)
#define PORTF_IN _SFR_MEM8(0x06A8)
#define PORTF_INTCTRL _SFR_MEM8(0x06A9)
#define PORTF_INT0MASK _SFR_MEM8(0x06AA)
#define PORTF_INT1MASK _SFR_MEM8(0x06AB)
#define PORTF_INTFLAGS _SFR_MEM8(0x06AC)
#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0)
#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1)
#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2)
#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3)
#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4)
#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5)
#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6)
#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7)

/* PORTH - Port H */
#define PORTH_DIR _SFR_MEM8(0x06E0)
#define PORTH_DIRSET _SFR_MEM8(0x06E1)
#define PORTH_DIRCLR _SFR_MEM8(0x06E2)
#define PORTH_DIRTGL _SFR_MEM8(0x06E3)
#define PORTH_OUT _SFR_MEM8(0x06E4)
#define PORTH_OUTSET _SFR_MEM8(0x06E5)
#define PORTH_OUTCLR _SFR_MEM8(0x06E6)
#define PORTH_OUTTGL _SFR_MEM8(0x06E7)
#define PORTH_IN _SFR_MEM8(0x06E8)
#define PORTH_INTCTRL _SFR_MEM8(0x06E9)
#define PORTH_INT0MASK _SFR_MEM8(0x06EA)
#define PORTH_INT1MASK _SFR_MEM8(0x06EB)
#define PORTH_INTFLAGS _SFR_MEM8(0x06EC)
#define PORTH_PIN0CTRL _SFR_MEM8(0x06F0)
#define PORTH_PIN1CTRL _SFR_MEM8(0x06F1)
#define PORTH_PIN2CTRL _SFR_MEM8(0x06F2)
#define PORTH_PIN3CTRL _SFR_MEM8(0x06F3)
#define PORTH_PIN4CTRL _SFR_MEM8(0x06F4)
#define PORTH_PIN5CTRL _SFR_MEM8(0x06F5)
#define PORTH_PIN6CTRL _SFR_MEM8(0x06F6)
#define PORTH_PIN7CTRL _SFR_MEM8(0x06F7)

/* PORTJ - Port J */
#define PORTJ_DIR _SFR_MEM8(0x0700)
#define PORTJ_DIRSET _SFR_MEM8(0x0701)
#define PORTJ_DIRCLR _SFR_MEM8(0x0702)
#define PORTJ_DIRTGL _SFR_MEM8(0x0703)
#define PORTJ_OUT _SFR_MEM8(0x0704)
#define PORTJ_OUTSET _SFR_MEM8(0x0705)
#define PORTJ_OUTCLR _SFR_MEM8(0x0706)
#define PORTJ_OUTTGL _SFR_MEM8(0x0707)
#define PORTJ_IN _SFR_MEM8(0x0708)
#define PORTJ_INTCTRL _SFR_MEM8(0x0709)
#define PORTJ_INT0MASK _SFR_MEM8(0x070A)
#define PORTJ_INT1MASK _SFR_MEM8(0x070B)
#define PORTJ_INTFLAGS _SFR_MEM8(0x070C)
#define PORTJ_PIN0CTRL _SFR_MEM8(0x0710)
#define PORTJ_PIN1CTRL _SFR_MEM8(0x0711)
#define PORTJ_PIN2CTRL _SFR_MEM8(0x0712)
#define PORTJ_PIN3CTRL _SFR_MEM8(0x0713)
#define PORTJ_PIN4CTRL _SFR_MEM8(0x0714)
#define PORTJ_PIN5CTRL _SFR_MEM8(0x0715)
#define PORTJ_PIN6CTRL _SFR_MEM8(0x0716)
#define PORTJ_PIN7CTRL _SFR_MEM8(0x0717)

/* PORTK - Port K */
#define PORTK_DIR _SFR_MEM8(0x0720)
#define PORTK_DIRSET _SFR_MEM8(0x0721)
#define PORTK_DIRCLR _SFR_MEM8(0x0722)
#define PORTK_DIRTGL _SFR_MEM8(0x0723)
#define PORTK_OUT _SFR_MEM8(0x0724)
#define PORTK_OUTSET _SFR_MEM8(0x0725)
#define PORTK_OUTCLR _SFR_MEM8(0x0726)
#define PORTK_OUTTGL _SFR_MEM8(0x0727)
#define PORTK_IN _SFR_MEM8(0x0728)
#define PORTK_INTCTRL _SFR_MEM8(0x0729)
#define PORTK_INT0MASK _SFR_MEM8(0x072A)
#define PORTK_INT1MASK _SFR_MEM8(0x072B)
#define PORTK_INTFLAGS _SFR_MEM8(0x072C)
#define PORTK_PIN0CTRL _SFR_MEM8(0x0730)
#define PORTK_PIN1CTRL _SFR_MEM8(0x0731)
#define PORTK_PIN2CTRL _SFR_MEM8(0x0732)
#define PORTK_PIN3CTRL _SFR_MEM8(0x0733)
#define PORTK_PIN4CTRL _SFR_MEM8(0x0734)
#define PORTK_PIN5CTRL _SFR_MEM8(0x0735)
#define PORTK_PIN6CTRL _SFR_MEM8(0x0736)
#define PORTK_PIN7CTRL _SFR_MEM8(0x0737)

/* PORTQ - Port Q */
#define PORTQ_DIR _SFR_MEM8(0x07C0)
#define PORTQ_DIRSET _SFR_MEM8(0x07C1)
#define PORTQ_DIRCLR _SFR_MEM8(0x07C2)
#define PORTQ_DIRTGL _SFR_MEM8(0x07C3)
#define PORTQ_OUT _SFR_MEM8(0x07C4)
#define PORTQ_OUTSET _SFR_MEM8(0x07C5)
#define PORTQ_OUTCLR _SFR_MEM8(0x07C6)
#define PORTQ_OUTTGL _SFR_MEM8(0x07C7)
#define PORTQ_IN _SFR_MEM8(0x07C8)
#define PORTQ_INTCTRL _SFR_MEM8(0x07C9)
#define PORTQ_INT0MASK _SFR_MEM8(0x07CA)
#define PORTQ_INT1MASK _SFR_MEM8(0x07CB)
#define PORTQ_INTFLAGS _SFR_MEM8(0x07CC)
#define PORTQ_PIN0CTRL _SFR_MEM8(0x07D0)
#define PORTQ_PIN1CTRL _SFR_MEM8(0x07D1)
#define PORTQ_PIN2CTRL _SFR_MEM8(0x07D2)
#define PORTQ_PIN3CTRL _SFR_MEM8(0x07D3)
#define PORTQ_PIN4CTRL _SFR_MEM8(0x07D4)
#define PORTQ_PIN5CTRL _SFR_MEM8(0x07D5)
#define PORTQ_PIN6CTRL _SFR_MEM8(0x07D6)
#define PORTQ_PIN7CTRL _SFR_MEM8(0x07D7)

/* PORTR - Port R */
#define PORTR_DIR _SFR_MEM8(0x07E0)
#define PORTR_DIRSET _SFR_MEM8(0x07E1)
#define PORTR_DIRCLR _SFR_MEM8(0x07E2)
#define PORTR_DIRTGL _SFR_MEM8(0x07E3)
#define PORTR_OUT _SFR_MEM8(0x07E4)
#define PORTR_OUTSET _SFR_MEM8(0x07E5)
#define PORTR_OUTCLR _SFR_MEM8(0x07E6)
#define PORTR_OUTTGL _SFR_MEM8(0x07E7)
#define PORTR_IN _SFR_MEM8(0x07E8)
#define PORTR_INTCTRL _SFR_MEM8(0x07E9)
#define PORTR_INT0MASK _SFR_MEM8(0x07EA)
#define PORTR_INT1MASK _SFR_MEM8(0x07EB)
#define PORTR_INTFLAGS _SFR_MEM8(0x07EC)
#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0)
#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1)
#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2)
#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3)
#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4)
#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5)
#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6)
#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7)

/* TCC0 - Timer/Counter C0 */
#define TCC0_CTRLA _SFR_MEM8(0x0800)
#define TCC0_CTRLB _SFR_MEM8(0x0801)
#define TCC0_CTRLC _SFR_MEM8(0x0802)
#define TCC0_CTRLD _SFR_MEM8(0x0803)
#define TCC0_CTRLE _SFR_MEM8(0x0804)
#define TCC0_INTCTRLA _SFR_MEM8(0x0806)
#define TCC0_INTCTRLB _SFR_MEM8(0x0807)
#define TCC0_CTRLFCLR _SFR_MEM8(0x0808)
#define TCC0_CTRLFSET _SFR_MEM8(0x0809)
#define TCC0_CTRLGCLR _SFR_MEM8(0x080A)
#define TCC0_CTRLGSET _SFR_MEM8(0x080B)
#define TCC0_INTFLAGS _SFR_MEM8(0x080C)
#define TCC0_TEMP _SFR_MEM8(0x080F)
#define TCC0_CNT _SFR_MEM16(0x0820)
#define TCC0_PER _SFR_MEM16(0x0826)
#define TCC0_CCA _SFR_MEM16(0x0828)
#define TCC0_CCB _SFR_MEM16(0x082A)
#define TCC0_CCC _SFR_MEM16(0x082C)
#define TCC0_CCD _SFR_MEM16(0x082E)
#define TCC0_PERBUF _SFR_MEM16(0x0836)
#define TCC0_CCABUF _SFR_MEM16(0x0838)
#define TCC0_CCBBUF _SFR_MEM16(0x083A)
#define TCC0_CCCBUF _SFR_MEM16(0x083C)
#define TCC0_CCDBUF _SFR_MEM16(0x083E)

/* TCC1 - Timer/Counter C1 */
#define TCC1_CTRLA _SFR_MEM8(0x0840)
#define TCC1_CTRLB _SFR_MEM8(0x0841)
#define TCC1_CTRLC _SFR_MEM8(0x0842)
#define TCC1_CTRLD _SFR_MEM8(0x0843)
#define TCC1_CTRLE _SFR_MEM8(0x0844)
#define TCC1_INTCTRLA _SFR_MEM8(0x0846)
#define TCC1_INTCTRLB _SFR_MEM8(0x0847)
#define TCC1_CTRLFCLR _SFR_MEM8(0x0848)
#define TCC1_CTRLFSET _SFR_MEM8(0x0849)
#define TCC1_CTRLGCLR _SFR_MEM8(0x084A)
#define TCC1_CTRLGSET _SFR_MEM8(0x084B)
#define TCC1_INTFLAGS _SFR_MEM8(0x084C)
#define TCC1_TEMP _SFR_MEM8(0x084F)
#define TCC1_CNT _SFR_MEM16(0x0860)
#define TCC1_PER _SFR_MEM16(0x0866)
#define TCC1_CCA _SFR_MEM16(0x0868)
#define TCC1_CCB _SFR_MEM16(0x086A)
#define TCC1_PERBUF _SFR_MEM16(0x0876)
#define TCC1_CCABUF _SFR_MEM16(0x0878)
#define TCC1_CCBBUF _SFR_MEM16(0x087A)

/* AWEXC - Advanced Waveform Extension C */
#define AWEXC_CTRL _SFR_MEM8(0x0880)
#define AWEXC_FDEVMASK _SFR_MEM8(0x0882)
#define AWEXC_FDCTRL _SFR_MEM8(0x0883)
#define AWEXC_STATUS _SFR_MEM8(0x0884)
#define AWEXC_DTBOTH _SFR_MEM8(0x0886)
#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887)
#define AWEXC_DTLS _SFR_MEM8(0x0888)
#define AWEXC_DTHS _SFR_MEM8(0x0889)
#define AWEXC_DTLSBUF _SFR_MEM8(0x088A)
#define AWEXC_DTHSBUF _SFR_MEM8(0x088B)
#define AWEXC_OUTOVEN _SFR_MEM8(0x088C)

/* HIRESC - High-Resolution Extension C */
#define HIRESC_CTRL _SFR_MEM8(0x0890)

/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */
#define USARTC0_DATA _SFR_MEM8(0x08A0)
#define USARTC0_STATUS _SFR_MEM8(0x08A1)
#define USARTC0_CTRLA _SFR_MEM8(0x08A3)
#define USARTC0_CTRLB _SFR_MEM8(0x08A4)
#define USARTC0_CTRLC _SFR_MEM8(0x08A5)
#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6)
#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7)

/* USARTC1 - Universal Asynchronous Receiver-Transmitter C1 */
#define USARTC1_DATA _SFR_MEM8(0x08B0)
#define USARTC1_STATUS _SFR_MEM8(0x08B1)
#define USARTC1_CTRLA _SFR_MEM8(0x08B3)
#define USARTC1_CTRLB _SFR_MEM8(0x08B4)
#define USARTC1_CTRLC _SFR_MEM8(0x08B5)
#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6)
#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7)

/* SPIC - Serial Peripheral Interface C */
#define SPIC_CTRL _SFR_MEM8(0x08C0)
#define SPIC_INTCTRL _SFR_MEM8(0x08C1)
#define SPIC_STATUS _SFR_MEM8(0x08C2)
#define SPIC_DATA _SFR_MEM8(0x08C3)

/* IRCOM - IR Communication Module */
#define IRCOM_CTRL _SFR_MEM8(0x08F8)
#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9)
#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA)

/* TCD0 - Timer/Counter D0 */
#define TCD0_CTRLA _SFR_MEM8(0x0900)
#define TCD0_CTRLB _SFR_MEM8(0x0901)
#define TCD0_CTRLC _SFR_MEM8(0x0902)
#define TCD0_CTRLD _SFR_MEM8(0x0903)
#define TCD0_CTRLE _SFR_MEM8(0x0904)
#define TCD0_INTCTRLA _SFR_MEM8(0x0906)
#define TCD0_INTCTRLB _SFR_MEM8(0x0907)
#define TCD0_CTRLFCLR _SFR_MEM8(0x0908)
#define TCD0_CTRLFSET _SFR_MEM8(0x0909)
#define TCD0_CTRLGCLR _SFR_MEM8(0x090A)
#define TCD0_CTRLGSET _SFR_MEM8(0x090B)
#define TCD0_INTFLAGS _SFR_MEM8(0x090C)
#define TCD0_TEMP _SFR_MEM8(0x090F)
#define TCD0_CNT _SFR_MEM16(0x0920)
#define TCD0_PER _SFR_MEM16(0x0926)
#define TCD0_CCA _SFR_MEM16(0x0928)
#define TCD0_CCB _SFR_MEM16(0x092A)
#define TCD0_CCC _SFR_MEM16(0x092C)
#define TCD0_CCD _SFR_MEM16(0x092E)
#define TCD0_PERBUF _SFR_MEM16(0x0936)
#define TCD0_CCABUF _SFR_MEM16(0x0938)
#define TCD0_CCBBUF _SFR_MEM16(0x093A)
#define TCD0_CCCBUF _SFR_MEM16(0x093C)
#define TCD0_CCDBUF _SFR_MEM16(0x093E)

/* TCD1 - Timer/Counter D1 */
#define TCD1_CTRLA _SFR_MEM8(0x0940)
#define TCD1_CTRLB _SFR_MEM8(0x0941)
#define TCD1_CTRLC _SFR_MEM8(0x0942)
#define TCD1_CTRLD _SFR_MEM8(0x0943)
#define TCD1_CTRLE _SFR_MEM8(0x0944)
#define TCD1_INTCTRLA _SFR_MEM8(0x0946)
#define TCD1_INTCTRLB _SFR_MEM8(0x0947)
#define TCD1_CTRLFCLR _SFR_MEM8(0x0948)
#define TCD1_CTRLFSET _SFR_MEM8(0x0949)
#define TCD1_CTRLGCLR _SFR_MEM8(0x094A)
#define TCD1_CTRLGSET _SFR_MEM8(0x094B)
#define TCD1_INTFLAGS _SFR_MEM8(0x094C)
#define TCD1_TEMP _SFR_MEM8(0x094F)
#define TCD1_CNT _SFR_MEM16(0x0960)
#define TCD1_PER _SFR_MEM16(0x0966)
#define TCD1_CCA _SFR_MEM16(0x0968)
#define TCD1_CCB _SFR_MEM16(0x096A)
#define TCD1_PERBUF _SFR_MEM16(0x0976)
#define TCD1_CCABUF _SFR_MEM16(0x0978)
#define TCD1_CCBBUF _SFR_MEM16(0x097A)

/* HIRESD - High-Resolution Extension D */
#define HIRESD_CTRL _SFR_MEM8(0x0990)

/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */
#define USARTD0_DATA _SFR_MEM8(0x09A0)
#define USARTD0_STATUS _SFR_MEM8(0x09A1)
#define USARTD0_CTRLA _SFR_MEM8(0x09A3)
#define USARTD0_CTRLB _SFR_MEM8(0x09A4)
#define USARTD0_CTRLC _SFR_MEM8(0x09A5)
#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6)
#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7)

/* USARTD1 - Universal Asynchronous Receiver-Transmitter D1 */
#define USARTD1_DATA _SFR_MEM8(0x09B0)
#define USARTD1_STATUS _SFR_MEM8(0x09B1)
#define USARTD1_CTRLA _SFR_MEM8(0x09B3)
#define USARTD1_CTRLB _SFR_MEM8(0x09B4)
#define USARTD1_CTRLC _SFR_MEM8(0x09B5)
#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6)
#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7)

/* SPID - Serial Peripheral Interface D */
#define SPID_CTRL _SFR_MEM8(0x09C0)
#define SPID_INTCTRL _SFR_MEM8(0x09C1)
#define SPID_STATUS _SFR_MEM8(0x09C2)
#define SPID_DATA _SFR_MEM8(0x09C3)

/* TCE0 - Timer/Counter E0 */
#define TCE0_CTRLA _SFR_MEM8(0x0A00)
#define TCE0_CTRLB _SFR_MEM8(0x0A01)
#define TCE0_CTRLC _SFR_MEM8(0x0A02)
#define TCE0_CTRLD _SFR_MEM8(0x0A03)
#define TCE0_CTRLE _SFR_MEM8(0x0A04)
#define TCE0_INTCTRLA _SFR_MEM8(0x0A06)
#define TCE0_INTCTRLB _SFR_MEM8(0x0A07)
#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08)
#define TCE0_CTRLFSET _SFR_MEM8(0x0A09)
#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A)
#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B)
#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C)
#define TCE0_TEMP _SFR_MEM8(0x0A0F)
#define TCE0_CNT _SFR_MEM16(0x0A20)
#define TCE0_PER _SFR_MEM16(0x0A26)
#define TCE0_CCA _SFR_MEM16(0x0A28)
#define TCE0_CCB _SFR_MEM16(0x0A2A)
#define TCE0_CCC _SFR_MEM16(0x0A2C)
#define TCE0_CCD _SFR_MEM16(0x0A2E)
#define TCE0_PERBUF _SFR_MEM16(0x0A36)
#define TCE0_CCABUF _SFR_MEM16(0x0A38)
#define TCE0_CCBBUF _SFR_MEM16(0x0A3A)
#define TCE0_CCCBUF _SFR_MEM16(0x0A3C)
#define TCE0_CCDBUF _SFR_MEM16(0x0A3E)

/* TCE1 - Timer/Counter E1 */
#define TCE1_CTRLA _SFR_MEM8(0x0A40)
#define TCE1_CTRLB _SFR_MEM8(0x0A41)
#define TCE1_CTRLC _SFR_MEM8(0x0A42)
#define TCE1_CTRLD _SFR_MEM8(0x0A43)
#define TCE1_CTRLE _SFR_MEM8(0x0A44)
#define TCE1_INTCTRLA _SFR_MEM8(0x0A46)
#define TCE1_INTCTRLB _SFR_MEM8(0x0A47)
#define TCE1_CTRLFCLR _SFR_MEM8(0x0A48)
#define TCE1_CTRLFSET _SFR_MEM8(0x0A49)
#define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A)
#define TCE1_CTRLGSET _SFR_MEM8(0x0A4B)
#define TCE1_INTFLAGS _SFR_MEM8(0x0A4C)
#define TCE1_TEMP _SFR_MEM8(0x0A4F)
#define TCE1_CNT _SFR_MEM16(0x0A60)
#define TCE1_PER _SFR_MEM16(0x0A66)
#define TCE1_CCA _SFR_MEM16(0x0A68)
#define TCE1_CCB _SFR_MEM16(0x0A6A)
#define TCE1_PERBUF _SFR_MEM16(0x0A76)
#define TCE1_CCABUF _SFR_MEM16(0x0A78)
#define TCE1_CCBBUF _SFR_MEM16(0x0A7A)

/* AWEXE - Advanced Waveform Extension E */
#define AWEXE_CTRL _SFR_MEM8(0x0A80)
#define AWEXE_FDEVMASK _SFR_MEM8(0x0A82)
#define AWEXE_FDCTRL _SFR_MEM8(0x0A83)
#define AWEXE_STATUS _SFR_MEM8(0x0A84)
#define AWEXE_DTBOTH _SFR_MEM8(0x0A86)
#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87)
#define AWEXE_DTLS _SFR_MEM8(0x0A88)
#define AWEXE_DTHS _SFR_MEM8(0x0A89)
#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A)
#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B)
#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C)

/* HIRESE - High-Resolution Extension E */
#define HIRESE_CTRL _SFR_MEM8(0x0A90)

/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */
#define USARTE0_DATA _SFR_MEM8(0x0AA0)
#define USARTE0_STATUS _SFR_MEM8(0x0AA1)
#define USARTE0_CTRLA _SFR_MEM8(0x0AA3)
#define USARTE0_CTRLB _SFR_MEM8(0x0AA4)
#define USARTE0_CTRLC _SFR_MEM8(0x0AA5)
#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6)
#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7)

/* USARTE1 - Universal Asynchronous Receiver-Transmitter E1 */
#define USARTE1_DATA _SFR_MEM8(0x0AB0)
#define USARTE1_STATUS _SFR_MEM8(0x0AB1)
#define USARTE1_CTRLA _SFR_MEM8(0x0AB3)
#define USARTE1_CTRLB _SFR_MEM8(0x0AB4)
#define USARTE1_CTRLC _SFR_MEM8(0x0AB5)
#define USARTE1_BAUDCTRLA _SFR_MEM8(0x0AB6)
#define USARTE1_BAUDCTRLB _SFR_MEM8(0x0AB7)

/* SPIE - Serial Peripheral Interface E */
#define SPIE_CTRL _SFR_MEM8(0x0AC0)
#define SPIE_INTCTRL _SFR_MEM8(0x0AC1)
#define SPIE_STATUS _SFR_MEM8(0x0AC2)
#define SPIE_DATA _SFR_MEM8(0x0AC3)

/* TCF0 - Timer/Counter F0 */
#define TCF0_CTRLA _SFR_MEM8(0x0B00)
#define TCF0_CTRLB _SFR_MEM8(0x0B01)
#define TCF0_CTRLC _SFR_MEM8(0x0B02)
#define TCF0_CTRLD _SFR_MEM8(0x0B03)
#define TCF0_CTRLE _SFR_MEM8(0x0B04)
#define TCF0_INTCTRLA _SFR_MEM8(0x0B06)
#define TCF0_INTCTRLB _SFR_MEM8(0x0B07)
#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08)
#define TCF0_CTRLFSET _SFR_MEM8(0x0B09)
#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A)
#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B)
#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C)
#define TCF0_TEMP _SFR_MEM8(0x0B0F)
#define TCF0_CNT _SFR_MEM16(0x0B20)
#define TCF0_PER _SFR_MEM16(0x0B26)
#define TCF0_CCA _SFR_MEM16(0x0B28)
#define TCF0_CCB _SFR_MEM16(0x0B2A)
#define TCF0_CCC _SFR_MEM16(0x0B2C)
#define TCF0_CCD _SFR_MEM16(0x0B2E)
#define TCF0_PERBUF _SFR_MEM16(0x0B36)
#define TCF0_CCABUF _SFR_MEM16(0x0B38)
#define TCF0_CCBBUF _SFR_MEM16(0x0B3A)
#define TCF0_CCCBUF _SFR_MEM16(0x0B3C)
#define TCF0_CCDBUF _SFR_MEM16(0x0B3E)

/* TCF1 - Timer/Counter F1 */
#define TCF1_CTRLA _SFR_MEM8(0x0B40)
#define TCF1_CTRLB _SFR_MEM8(0x0B41)
#define TCF1_CTRLC _SFR_MEM8(0x0B42)
#define TCF1_CTRLD _SFR_MEM8(0x0B43)
#define TCF1_CTRLE _SFR_MEM8(0x0B44)
#define TCF1_INTCTRLA _SFR_MEM8(0x0B46)
#define TCF1_INTCTRLB _SFR_MEM8(0x0B47)
#define TCF1_CTRLFCLR _SFR_MEM8(0x0B48)
#define TCF1_CTRLFSET _SFR_MEM8(0x0B49)
#define TCF1_CTRLGCLR _SFR_MEM8(0x0B4A)
#define TCF1_CTRLGSET _SFR_MEM8(0x0B4B)
#define TCF1_INTFLAGS _SFR_MEM8(0x0B4C)
#define TCF1_TEMP _SFR_MEM8(0x0B4F)
#define TCF1_CNT _SFR_MEM16(0x0B60)
#define TCF1_PER _SFR_MEM16(0x0B66)
#define TCF1_CCA _SFR_MEM16(0x0B68)
#define TCF1_CCB _SFR_MEM16(0x0B6A)
#define TCF1_PERBUF _SFR_MEM16(0x0B76)
#define TCF1_CCABUF _SFR_MEM16(0x0B78)
#define TCF1_CCBBUF _SFR_MEM16(0x0B7A)

/* HIRESF - High-Resolution Extension F */
#define HIRESF_CTRL _SFR_MEM8(0x0B90)

/* USARTF0 - Universal Asynchronous Receiver-Transmitter F0 */
#define USARTF0_DATA _SFR_MEM8(0x0BA0)
#define USARTF0_STATUS _SFR_MEM8(0x0BA1)
#define USARTF0_CTRLA _SFR_MEM8(0x0BA3)
#define USARTF0_CTRLB _SFR_MEM8(0x0BA4)
#define USARTF0_CTRLC _SFR_MEM8(0x0BA5)
#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6)
#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7)

/* USARTF1 - Universal Asynchronous Receiver-Transmitter F1 */
#define USARTF1_DATA _SFR_MEM8(0x0BB0)
#define USARTF1_STATUS _SFR_MEM8(0x0BB1)
#define USARTF1_CTRLA _SFR_MEM8(0x0BB3)
#define USARTF1_CTRLB _SFR_MEM8(0x0BB4)
#define USARTF1_CTRLC _SFR_MEM8(0x0BB5)
#define USARTF1_BAUDCTRLA _SFR_MEM8(0x0BB6)
#define USARTF1_BAUDCTRLB _SFR_MEM8(0x0BB7)

/* SPIF - Serial Peripheral Interface F */
#define SPIF_CTRL _SFR_MEM8(0x0BC0)
#define SPIF_INTCTRL _SFR_MEM8(0x0BC1)
#define SPIF_STATUS _SFR_MEM8(0x0BC2)
#define SPIF_DATA _SFR_MEM8(0x0BC3)



/*================== Bitfield Definitions ================== */

/* XOCD - On-Chip Debug System */
/* OCD.OCDR1 bit masks and bit positions */
#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */
#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */


/* CPU - CPU */
/* CPU.CCP bit masks and bit positions */
#define CPU_CCP_gm 0xFF /* CCP signature group mask. */
#define CPU_CCP_gp 0 /* CCP signature group position. */
#define CPU_CCP0_bm (1 & lt; & lt; 0) /* CCP signature bit 0 mask. */
#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */
#define CPU_CCP1_bm (1 & lt; & lt; 1) /* CCP signature bit 1 mask. */
#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */
#define CPU_CCP2_bm (1 & lt; & lt; 2) /* CCP signature bit 2 mask. */
#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */
#define CPU_CCP3_bm (1 & lt; & lt; 3) /* CCP signature bit 3 mask. */
#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */
#define CPU_CCP4_bm (1 & lt; & lt; 4) /* CCP signature bit 4 mask. */
#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */
#define CPU_CCP5_bm (1 & lt; & lt; 5) /* CCP signature bit 5 mask. */
#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */
#define CPU_CCP6_bm (1 & lt; & lt; 6) /* CCP signature bit 6 mask. */
#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */
#define CPU_CCP7_bm (1 & lt; & lt; 7) /* CCP signature bit 7 mask. */
#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */


/* CPU.SREG bit masks and bit positions */
#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */
#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */

#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */
#define CPU_T_bp 6 /* Transfer Bit bit position. */

#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */
#define CPU_H_bp 5 /* Half Carry Flag bit position. */

#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */
#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */

#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */
#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */

#define CPU_N_bm 0x04 /* Negative Flag bit mask. */
#define CPU_N_bp 2 /* Negative Flag bit position. */

#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */
#define CPU_Z_bp 1 /* Zero Flag bit position. */

#define CPU_C_bm 0x01 /* Carry Flag bit mask. */
#define CPU_C_bp 0 /* Carry Flag bit position. */


/* CLK - Clock System */
/* CLK.CTRL bit masks and bit positions */
#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */
#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */
#define CLK_SCLKSEL0_bm (1 & lt; & lt; 0) /* System Clock Selection bit 0 mask. */
#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */
#define CLK_SCLKSEL1_bm (1 & lt; & lt; 1) /* System Clock Selection bit 1 mask. */
#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */
#define CLK_SCLKSEL2_bm (1 & lt; & lt; 2) /* System Clock Selection bit 2 mask. */
#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */


/* CLK.PSCTRL bit masks and bit positions */
#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */
#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */
#define CLK_PSADIV0_bm (1 & lt; & lt; 2) /* Prescaler A Division Factor bit 0 mask. */
#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */
#define CLK_PSADIV1_bm (1 & lt; & lt; 3) /* Prescaler A Division Factor bit 1 mask. */
#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */
#define CLK_PSADIV2_bm (1 & lt; & lt; 4) /* Prescaler A Division Factor bit 2 mask. */
#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */
#define CLK_PSADIV3_bm (1 & lt; & lt; 5) /* Prescaler A Division Factor bit 3 mask. */
#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */
#define CLK_PSADIV4_bm (1 & lt; & lt; 6) /* Prescaler A Division Factor bit 4 mask. */
#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */

#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */
#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */
#define CLK_PSBCDIV0_bm (1 & lt; & lt; 0) /* Prescaler B and C Division factor bit 0 mask. */
#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */
#define CLK_PSBCDIV1_bm (1 & lt; & lt; 1) /* Prescaler B and C Division factor bit 1 mask. */
#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */


/* CLK.LOCK bit masks and bit positions */
#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */
#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */


/* CLK.RTCCTRL bit masks and bit positions */
#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */
#define CLK_RTCSRC_gp 1 /* Clock Source group position. */
#define CLK_RTCSRC0_bm (1 & lt; & lt; 1) /* Clock Source bit 0 mask. */
#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */
#define CLK_RTCSRC1_bm (1 & lt; & lt; 2) /* Clock Source bit 1 mask. */
#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */
#define CLK_RTCSRC2_bm (1 & lt; & lt; 3) /* Clock Source bit 2 mask. */
#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */

#define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */
#define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */


/* PR.PRGEN bit masks and bit positions */
#define PR_AES_bm 0x10 /* AES bit mask. */
#define PR_AES_bp 4 /* AES bit position. */

#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */
#define PR_EBI_bp 3 /* External Bus Interface bit position. */

#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */
#define PR_RTC_bp 2 /* Real-time Counter bit position. */

#define PR_EVSYS_bm 0x02 /* Event System bit mask. */
#define PR_EVSYS_bp 1 /* Event System bit position. */

#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */
#define PR_DMA_bp 0 /* DMA-Controller bit position. */


/* PR.PRPA bit masks and bit positions */
#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */
#define PR_DAC_bp 2 /* Port A DAC bit position. */

#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */
#define PR_ADC_bp 1 /* Port A ADC bit position. */

#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */
#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */


/* PR.PRPB bit masks and bit positions */
/* PR_DAC_bm Predefined. */
/* PR_DAC_bp Predefined. */

/* PR_ADC_bm Predefined. */
/* PR_ADC_bp Predefined. */

/* PR_AC_bm Predefined. */
/* PR_AC_bp Predefined. */


/* PR.PRPC bit masks and bit positions */
#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */
#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */

#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */
#define PR_USART1_bp 5 /* Port C USART1 bit position. */

#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */
#define PR_USART0_bp 4 /* Port C USART0 bit position. */

#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */
#define PR_SPI_bp 3 /* Port C SPI bit position. */

#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */
#define PR_HIRES_bp 2 /* Port C AWEX bit position. */

#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */
#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */

#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */
#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */


/* PR.PRPD bit masks and bit positions */
/* PR_TWI_bm Predefined. */
/* PR_TWI_bp Predefined. */

/* PR_USART1_bm Predefined. */
/* PR_USART1_bp Predefined. */

/* PR_USART0_bm Predefined. */
/* PR_USART0_bp Predefined. */

/* PR_SPI_bm Predefined. */
/* PR_SPI_bp Predefined. */

/* PR_HIRES_bm Predefined. */
/* PR_HIRES_bp Predefined. */

/* PR_TC1_bm Predefined. */
/* PR_TC1_bp Predefined. */

/* PR_TC0_bm Predefined. */
/* PR_TC0_bp Predefined. */


/* PR.PRPE bit masks and bit positions */
/* PR_TWI_bm Predefined. */
/* PR_TWI_bp Predefined. */

/* PR_USART1_bm Predefined. */
/* PR_USART1_bp Predefined. */

/* PR_USART0_bm Predefined. */
/* PR_USART0_bp Predefined. */

/* PR_SPI_bm Predefined. */
/* PR_SPI_bp Predefined. */

/* PR_HIRES_bm Predefined. */
/* PR_HIRES_bp Predefined. */

/* PR_TC1_bm Predefined. */
/* PR_TC1_bp Predefined. */

/* PR_TC0_bm Predefined. */
/* PR_TC0_bp Predefined. */


/* PR.PRPF bit masks and bit positions */
/* PR_TWI_bm Predefined. */
/* PR_TWI_bp Predefined. */

/* PR_USART1_bm Predefined. */
/* PR_USART1_bp Predefined. */

/* PR_USART0_bm Predefined. */
/* PR_USART0_bp Predefined. */

/* PR_SPI_bm Predefined. */
/* PR_SPI_bp Predefined. */

/* PR_HIRES_bm Predefined. */
/* PR_HIRES_bp Predefined. */

/* PR_TC1_bm Predefined. */
/* PR_TC1_bp Predefined. */

/* PR_TC0_bm Predefined. */
/* PR_TC0_bp Predefined. */


/* SLEEP - Sleep Controller */
/* SLEEP.CTRL bit masks and bit positions */
#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */
#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */
#define SLEEP_SMODE0_bm (1 & lt; & lt; 1) /* Sleep Mode bit 0 mask. */
#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */
#define SLEEP_SMODE1_bm (1 & lt; & lt; 2) /* Sleep Mode bit 1 mask. */
#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */
#define SLEEP_SMODE2_bm (1 & lt; & lt; 3) /* Sleep Mode bit 2 mask. */
#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */

#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */
#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */


/* OSC - Oscillator */
/* OSC.CTRL bit masks and bit positions */
#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */
#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */

#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */
#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */

#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */
#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */

#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */
#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */

#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */
#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */


/* OSC.STATUS bit masks and bit positions */
#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */
#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */

#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */
#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */

#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */
#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */

#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */
#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */

#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */
#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */


/* OSC.XOSCCTRL bit masks and bit positions */
#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */
#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */
#define OSC_FRQRANGE0_bm (1 & lt; & lt; 6) /* Frequency Range bit 0 mask. */
#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */
#define OSC_FRQRANGE1_bm (1 & lt; & lt; 7) /* Frequency Range bit 1 mask. */
#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */

#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */
#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */

#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */
#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */
#define OSC_XOSCSEL0_bm (1 & lt; & lt; 0) /* External Oscillator Selection and Startup Time bit 0 mask. */
#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */
#define OSC_XOSCSEL1_bm (1 & lt; & lt; 1) /* External Oscillator Selection and Startup Time bit 1 mask. */
#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */
#define OSC_XOSCSEL2_bm (1 & lt; & lt; 2) /* External Oscillator Selection and Startup Time bit 2 mask. */
#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */
#define OSC_XOSCSEL3_bm (1 & lt; & lt; 3) /* External Oscillator Selection and Startup Time bit 3 mask. */
#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */


/* OSC.XOSCFAIL bit masks and bit positions */
#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */
#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */

#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */
#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */


/* OSC.PLLCTRL bit masks and bit positions */
#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */
#define OSC_PLLSRC_gp 6 /* Clock Source group position. */
#define OSC_PLLSRC0_bm (1 & lt; & lt; 6) /* Clock Source bit 0 mask. */
#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */
#define OSC_PLLSRC1_bm (1 & lt; & lt; 7) /* Clock Source bit 1 mask. */
#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */

#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */
#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */
#define OSC_PLLFAC0_bm (1 & lt; & lt; 0) /* Multiplication Factor bit 0 mask. */
#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */
#define OSC_PLLFAC1_bm (1 & lt; & lt; 1) /* Multiplication Factor bit 1 mask. */
#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */
#define OSC_PLLFAC2_bm (1 & lt; & lt; 2) /* Multiplication Factor bit 2 mask. */
#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */
#define OSC_PLLFAC3_bm (1 & lt; & lt; 3) /* Multiplication Factor bit 3 mask. */
#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */
#define OSC_PLLFAC4_bm (1 & lt; & lt; 4) /* Multiplication Factor bit 4 mask. */
#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */


/* OSC.DFLLCTRL bit masks and bit positions */
#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */
#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */

#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */
#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */


/* DFLL - DFLL */
/* DFLL.CTRL bit masks and bit positions */
#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */
#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */


/* DFLL.CALA bit masks and bit positions */
#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */
#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */
#define DFLL_CALL0_bm (1 & lt; & lt; 0) /* DFLL Calibration bits [6:0] bit 0 mask. */
#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */
#define DFLL_CALL1_bm (1 & lt; & lt; 1) /* DFLL Calibration bits [6:0] bit 1 mask. */
#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */
#define DFLL_CALL2_bm (1 & lt; & lt; 2) /* DFLL Calibration bits [6:0] bit 2 mask. */
#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */
#define DFLL_CALL3_bm (1 & lt; & lt; 3) /* DFLL Calibration bits [6:0] bit 3 mask. */
#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */
#define DFLL_CALL4_bm (1 & lt; & lt; 4) /* DFLL Calibration bits [6:0] bit 4 mask. */
#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */
#define DFLL_CALL5_bm (1 & lt; & lt; 5) /* DFLL Calibration bits [6:0] bit 5 mask. */
#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */
#define DFLL_CALL6_bm (1 & lt; & lt; 6) /* DFLL Calibration bits [6:0] bit 6 mask. */
#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */


/* DFLL.CALB bit masks and bit positions */
#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */
#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */
#define DFLL_CALH0_bm (1 & lt; & lt; 0) /* DFLL Calibration bits [12:7] bit 0 mask. */
#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */
#define DFLL_CALH1_bm (1 & lt; & lt; 1) /* DFLL Calibration bits [12:7] bit 1 mask. */
#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */
#define DFLL_CALH2_bm (1 & lt; & lt; 2) /* DFLL Calibration bits [12:7] bit 2 mask. */
#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */
#define DFLL_CALH3_bm (1 & lt; & lt; 3) /* DFLL Calibration bits [12:7] bit 3 mask. */
#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */
#define DFLL_CALH4_bm (1 & lt; & lt; 4) /* DFLL Calibration bits [12:7] bit 4 mask. */
#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */
#define DFLL_CALH5_bm (1 & lt; & lt; 5) /* DFLL Calibration bits [12:7] bit 5 mask. */
#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */


/* RST - Reset */
/* RST.STATUS bit masks and bit positions */
#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */
#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */

#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */
#define RST_SRF_bp 5 /* Software Reset Flag bit position. */

#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */
#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */

#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */
#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */

#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */
#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */

#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */
#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */

#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */
#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */


/* RST.CTRL bit masks and bit positions */
#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */
#define RST_SWRST_bp 0 /* Software Reset bit position. */


/* WDT - Watch-Dog Timer */
/* WDT.CTRL bit masks and bit positions */
#define WDT_PER_gm 0x3C /* Period group mask. */
#define WDT_PER_gp 2 /* Period group position. */
#define WDT_PER0_bm (1 & lt; & lt; 2) /* Period bit 0 mask. */
#define WDT_PER0_bp 2 /* Period bit 0 position. */
#define WDT_PER1_bm (1 & lt; & lt; 3) /* Period bit 1 mask. */
#define WDT_PER1_bp 3 /* Period bit 1 position. */
#define WDT_PER2_bm (1 & lt; & lt; 4) /* Period bit 2 mask. */
#define WDT_PER2_bp 4 /* Period bit 2 position. */
#define WDT_PER3_bm (1 & lt; & lt; 5) /* Period bit 3 mask. */
#define WDT_PER3_bp 5 /* Period bit 3 position. */

#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */
#define WDT_ENABLE_bp 1 /* Enable bit position. */

#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */
#define WDT_CEN_bp 0 /* Change Enable bit position. */


/* WDT.WINCTRL bit masks and bit positions */
#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */
#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */
#define WDT_WPER0_bm (1 & lt; & lt; 2) /* Windowed Mode Period bit 0 mask. */
#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */
#define WDT_WPER1_bm (1 & lt; & lt; 3) /* Windowed Mode Period bit 1 mask. */
#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */
#define WDT_WPER2_bm (1 & lt; & lt; 4) /* Windowed Mode Period bit 2 mask. */
#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */
#define WDT_WPER3_bm (1 & lt; & lt; 5) /* Windowed Mode Period bit 3 mask. */
#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */

#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */
#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */

#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */
#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */


/* WDT.STATUS bit masks and bit positions */
#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */
#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */


/* MCU - MCU Control */
/* MCU.MCUCR bit masks and bit positions */
#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */
#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */


/* MCU.EVSYSLOCK bit masks and bit positions */
#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */
#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */

#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */
#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */


/* MCU.AWEXLOCK bit masks and bit positions */
#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */
#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */

#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */
#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */


/* PMIC - Programmable Multi-level Interrupt Controller */
/* PMIC.STATUS bit masks and bit positions */
#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */
#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */

#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */
#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */

#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */
#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */

#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */
#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */


/* PMIC.CTRL bit masks and bit positions */
#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */
#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */

#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */
#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */

#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */
#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */

#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */
#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */

#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */
#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */


/* DMA - DMA Controller */
/* DMA_CH.CTRLA bit masks and bit positions */
#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */
#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */

#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */
#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */

#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */
#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */

#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */
#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */

#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */
#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */

#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */
#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */
#define DMA_CH_BURSTLEN0_bm (1 & lt; & lt; 0) /* Channel Transfer Mode bit 0 mask. */
#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */
#define DMA_CH_BURSTLEN1_bm (1 & lt; & lt; 1) /* Channel Transfer Mode bit 1 mask. */
#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */


/* DMA_CH.CTRLB bit masks and bit positions */
#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */
#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */

#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */
#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */

#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */
#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */

#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */
#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */

#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */
#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */
#define DMA_CH_ERRINTLVL0_bm (1 & lt; & lt; 2) /* Transfer Error Interrupt Level bit 0 mask. */
#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */
#define DMA_CH_ERRINTLVL1_bm (1 & lt; & lt; 3) /* Transfer Error Interrupt Level bit 1 mask. */
#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */

#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */
#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */
#define DMA_CH_TRNINTLVL0_bm (1 & lt; & lt; 0) /* Transaction Complete Interrupt Level bit 0 mask. */
#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */
#define DMA_CH_TRNINTLVL1_bm (1 & lt; & lt; 1) /* Transaction Complete Interrupt Level bit 1 mask. */
#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */


/* DMA_CH.ADDRCTRL bit masks and bit positions */
#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */
#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */
#define DMA_CH_SRCRELOAD0_bm (1 & lt; & lt; 6) /* Channel Source Address Reload bit 0 mask. */
#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */
#define DMA_CH_SRCRELOAD1_bm (1 & lt; & lt; 7) /* Channel Source Address Reload bit 1 mask. */
#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */

#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */
#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */
#define DMA_CH_SRCDIR0_bm (1 & lt; & lt; 4) /* Channel Source Address Mode bit 0 mask. */
#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */
#define DMA_CH_SRCDIR1_bm (1 & lt; & lt; 5) /* Channel Source Address Mode bit 1 mask. */
#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */

#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */
#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */
#define DMA_CH_DESTRELOAD0_bm (1 & lt; & lt; 2) /* Channel Destination Address Reload bit 0 mask. */
#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */
#define DMA_CH_DESTRELOAD1_bm (1 & lt; & lt; 3) /* Channel Destination Address Reload bit 1 mask. */
#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */

#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */
#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */
#define DMA_CH_DESTDIR0_bm (1 & lt; & lt; 0) /* Channel Destination Address Mode bit 0 mask. */
#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */
#define DMA_CH_DESTDIR1_bm (1 & lt; & lt; 1) /* Channel Destination Address Mode bit 1 mask. */
#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */


/* DMA_CH.TRIGSRC bit masks and bit positions */
#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */
#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */
#define DMA_CH_TRIGSRC0_bm (1 & lt; & lt; 0) /* Channel Trigger Source bit 0 mask. */
#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */
#define DMA_CH_TRIGSRC1_bm (1 & lt; & lt; 1) /* Channel Trigger Source bit 1 mask. */
#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */
#define DMA_CH_TRIGSRC2_bm (1 & lt; & lt; 2) /* Channel Trigger Source bit 2 mask. */
#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */
#define DMA_CH_TRIGSRC3_bm (1 & lt; & lt; 3) /* Channel Trigger Source bit 3 mask. */
#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */
#define DMA_CH_TRIGSRC4_bm (1 & lt; & lt; 4) /* Channel Trigger Source bit 4 mask. */
#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */
#define DMA_CH_TRIGSRC5_bm (1 & lt; & lt; 5) /* Channel Trigger Source bit 5 mask. */
#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */
#define DMA_CH_TRIGSRC6_bm (1 & lt; & lt; 6) /* Channel Trigger Source bit 6 mask. */
#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */
#define DMA_CH_TRIGSRC7_bm (1 & lt; & lt; 7) /* Channel Trigger Source bit 7 mask. */
#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */


/* DMA.CTRL bit masks and bit positions */
#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */
#define DMA_ENABLE_bp 7 /* Enable bit position. */

#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */
#define DMA_RESET_bp 6 /* Software Reset bit position. */

#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */
#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */
#define DMA_DBUFMODE0_bm (1 & lt; & lt; 2) /* Double Buffering Mode bit 0 mask. */
#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */
#define DMA_DBUFMODE1_bm (1 & lt; & lt; 3) /* Double Buffering Mode bit 1 mask. */
#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */

#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */
#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */
#define DMA_PRIMODE0_bm (1 & lt; & lt; 0) /* Channel Priority Mode bit 0 mask. */
#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */
#define DMA_PRIMODE1_bm (1 & lt; & lt; 1) /* Channel Priority Mode bit 1 mask. */
#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */


/* DMA.INTFLAGS bit masks and bit positions */
#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */
#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */

#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */
#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */

#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */
#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */

#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */
#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */

#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */
#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */

#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */
#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */

#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */
#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */

#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */
#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */


/* DMA.STATUS bit masks and bit positions */
#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */
#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */

#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */
#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */

#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */
#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */

#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */
#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */

#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */
#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */

#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */
#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */

#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */
#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */

#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */
#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */


/* EVSYS - Event System */
/* EVSYS.CH0MUX bit masks and bit positions */
#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */
#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */
#define EVSYS_CHMUX0_bm (1 & lt; & lt; 0) /* Event Channel 0 Multiplexer bit 0 mask. */
#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */
#define EVSYS_CHMUX1_bm (1 & lt; & lt; 1) /* Event Channel 0 Multiplexer bit 1 mask. */
#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */
#define EVSYS_CHMUX2_bm (1 & lt; & lt; 2) /* Event Channel 0 Multiplexer bit 2 mask. */
#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */
#define EVSYS_CHMUX3_bm (1 & lt; & lt; 3) /* Event Channel 0 Multiplexer bit 3 mask. */
#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */
#define EVSYS_CHMUX4_bm (1 & lt; & lt; 4) /* Event Channel 0 Multiplexer bit 4 mask. */
#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */
#define EVSYS_CHMUX5_bm (1 & lt; & lt; 5) /* Event Channel 0 Multiplexer bit 5 mask. */
#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */
#define EVSYS_CHMUX6_bm (1 & lt; & lt; 6) /* Event Channel 0 Multiplexer bit 6 mask. */
#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */
#define EVSYS_CHMUX7_bm (1 & lt; & lt; 7) /* Event Channel 0 Multiplexer bit 7 mask. */
#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */


/* EVSYS.CH1MUX bit masks and bit positions */
/* EVSYS_CHMUX_gm Predefined. */
/* EVSYS_CHMUX_gp Predefined. */
/* EVSYS_CHMUX0_bm Predefined. */
/* EVSYS_CHMUX0_bp Predefined. */
/* EVSYS_CHMUX1_bm Predefined. */
/* EVSYS_CHMUX1_bp Predefined. */
/* EVSYS_CHMUX2_bm Predefined. */
/* EVSYS_CHMUX2_bp Predefined. */
/* EVSYS_CHMUX3_bm Predefined. */
/* EVSYS_CHMUX3_bp Predefined. */
/* EVSYS_CHMUX4_bm Predefined. */
/* EVSYS_CHMUX4_bp Predefined. */
/* EVSYS_CHMUX5_bm Predefined. */
/* EVSYS_CHMUX5_bp Predefined. */
/* EVSYS_CHMUX6_bm Predefined. */
/* EVSYS_CHMUX6_bp Predefined. */
/* EVSYS_CHMUX7_bm Predefined. */
/* EVSYS_CHMUX7_bp Predefined. */


/* EVSYS.CH2MUX bit masks and bit positions */
/* EVSYS_CHMUX_gm Predefined. */
/* EVSYS_CHMUX_gp Predefined. */
/* EVSYS_CHMUX0_bm Predefined. */
/* EVSYS_CHMUX0_bp Predefined. */
/* EVSYS_CHMUX1_bm Predefined. */
/* EVSYS_CHMUX1_bp Predefined. */
/* EVSYS_CHMUX2_bm Predefined. */
/* EVSYS_CHMUX2_bp Predefined. */
/* EVSYS_CHMUX3_bm Predefined. */
/* EVSYS_CHMUX3_bp Predefined. */
/* EVSYS_CHMUX4_bm Predefined. */
/* EVSYS_CHMUX4_bp Predefined. */
/* EVSYS_CHMUX5_bm Predefined. */
/* EVSYS_CHMUX5_bp Predefined. */
/* EVSYS_CHMUX6_bm Predefined. */
/* EVSYS_CHMUX6_bp Predefined. */
/* EVSYS_CHMUX7_bm Predefined. */
/* EVSYS_CHMUX7_bp Predefined. */


/* EVSYS.CH3MUX bit masks and bit positions */
/* EVSYS_CHMUX_gm Predefined. */
/* EVSYS_CHMUX_gp Predefined. */
/* EVSYS_CHMUX0_bm Predefined. */
/* EVSYS_CHMUX0_bp Predefined. */
/* EVSYS_CHMUX1_bm Predefined. */
/* EVSYS_CHMUX1_bp Predefined. */
/* EVSYS_CHMUX2_bm Predefined. */
/* EVSYS_CHMUX2_bp Predefined. */
/* EVSYS_CHMUX3_bm Predefined. */
/* EVSYS_CHMUX3_bp Predefined. */
/* EVSYS_CHMUX4_bm Predefined. */
/* EVSYS_CHMUX4_bp Predefined. */
/* EVSYS_CHMUX5_bm Predefined. */
/* EVSYS_CHMUX5_bp Predefined. */
/* EVSYS_CHMUX6_bm Predefined. */
/* EVSYS_CHMUX6_bp Predefined. */
/* EVSYS_CHMUX7_bm Predefined. */
/* EVSYS_CHMUX7_bp Predefined. */


/* EVSYS.CH4MUX bit masks and bit positions */
/* EVSYS_CHMUX_gm Predefined. */
/* EVSYS_CHMUX_gp Predefined. */
/* EVSYS_CHMUX0_bm Predefined. */
/* EVSYS_CHMUX0_bp Predefined. */
/* EVSYS_CHMUX1_bm Predefined. */
/* EVSYS_CHMUX1_bp Predefined. */
/* EVSYS_CHMUX2_bm Predefined. */
/* EVSYS_CHMUX2_bp Predefined. */
/* EVSYS_CHMUX3_bm Predefined. */
/* EVSYS_CHMUX3_bp Predefined. */
/* EVSYS_CHMUX4_bm Predefined. */
/* EVSYS_CHMUX4_bp Predefined. */
/* EVSYS_CHMUX5_bm Predefined. */
/* EVSYS_CHMUX5_bp Predefined. */
/* EVSYS_CHMUX6_bm Predefined. */
/* EVSYS_CHMUX6_bp Predefined. */
/* EVSYS_CHMUX7_bm Predefined. */
/* EVSYS_CHMUX7_bp Predefined. */


/* EVSYS.CH5MUX bit masks and bit positions */
/* EVSYS_CHMUX_gm Predefined. */
/* EVSYS_CHMUX_gp Predefined. */
/* EVSYS_CHMUX0_bm Predefined. */
/* EVSYS_CHMUX0_bp Predefined. */
/* EVSYS_CHMUX1_bm Predefined. */
/* EVSYS_CHMUX1_bp Predefined. */
/* EVSYS_CHMUX2_bm Predefined. */
/* EVSYS_CHMUX2_bp Predefined. */
/* EVSYS_CHMUX3_bm Predefined. */
/* EVSYS_CHMUX3_bp Predefined. */
/* EVSYS_CHMUX4_bm Predefined. */
/* EVSYS_CHMUX4_bp Predefined. */
/* EVSYS_CHMUX5_bm Predefined. */
/* EVSYS_CHMUX5_bp Predefined. */
/* EVSYS_CHMUX6_bm Predefined. */
/* EVSYS_CHMUX6_bp Predefined. */
/* EVSYS_CHMUX7_bm Predefined. */
/* EVSYS_CHMUX7_bp Predefined. */


/* EVSYS.CH6MUX bit masks and bit positions */
/* EVSYS_CHMUX_gm Predefined. */
/* EVSYS_CHMUX_gp Predefined. */
/* EVSYS_CHMUX0_bm Predefined. */
/* EVSYS_CHMUX0_bp Predefined. */
/* EVSYS_CHMUX1_bm Predefined. */
/* EVSYS_CHMUX1_bp Predefined. */
/* EVSYS_CHMUX2_bm Predefined. */
/* EVSYS_CHMUX2_bp Predefined. */
/* EVSYS_CHMUX3_bm Predefined. */
/* EVSYS_CHMUX3_bp Predefined. */
/* EVSYS_CHMUX4_bm Predefined. */
/* EVSYS_CHMUX4_bp Predefined. */
/* EVSYS_CHMUX5_bm Predefined. */
/* EVSYS_CHMUX5_bp Predefined. */
/* EVSYS_CHMUX6_bm Predefined. */
/* EVSYS_CHMUX6_bp Predefined. */
/* EVSYS_CHMUX7_bm Predefined. */
/* EVSYS_CHMUX7_bp Predefined. */


/* EVSYS.CH7MUX bit masks and bit positions */
/* EVSYS_CHMUX_gm Predefined. */
/* EVSYS_CHMUX_gp Predefined. */
/* EVSYS_CHMUX0_bm Predefined. */
/* EVSYS_CHMUX0_bp Predefined. */
/* EVSYS_CHMUX1_bm Predefined. */
/* EVSYS_CHMUX1_bp Predefined. */
/* EVSYS_CHMUX2_bm Predefined. */
/* EVSYS_CHMUX2_bp Predefined. */
/* EVSYS_CHMUX3_bm Predefined. */
/* EVSYS_CHMUX3_bp Predefined. */
/* EVSYS_CHMUX4_bm Predefined. */
/* EVSYS_CHMUX4_bp Predefined. */
/* EVSYS_CHMUX5_bm Predefined. */
/* EVSYS_CHMUX5_bp Predefined. */
/* EVSYS_CHMUX6_bm Predefined. */
/* EVSYS_CHMUX6_bp Predefined. */
/* EVSYS_CHMUX7_bm Predefined. */
/* EVSYS_CHMUX7_bp Predefined. */


/* EVSYS.CH0CTRL bit masks and bit positions */
#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */
#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */
#define EVSYS_QDIRM0_bm (1 & lt; & lt; 5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */
#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */
#define EVSYS_QDIRM1_bm (1 & lt; & lt; 6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */
#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */

#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */
#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */

#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */
#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */

#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */
#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */
#define EVSYS_DIGFILT0_bm (1 & lt; & lt; 0) /* Digital Filter bit 0 mask. */
#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */
#define EVSYS_DIGFILT1_bm (1 & lt; & lt; 1) /* Digital Filter bit 1 mask. */
#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */
#define EVSYS_DIGFILT2_bm (1 & lt; & lt; 2) /* Digital Filter bit 2 mask. */
#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */


/* EVSYS.CH1CTRL bit masks and bit positions */
/* EVSYS_DIGFILT_gm Predefined. */
/* EVSYS_DIGFILT_gp Predefined. */
/* EVSYS_DIGFILT0_bm Predefined. */
/* EVSYS_DIGFILT0_bp Predefined. */
/* EVSYS_DIGFILT1_bm Predefined. */
/* EVSYS_DIGFILT1_bp Predefined. */
/* EVSYS_DIGFILT2_bm Predefined. */
/* EVSYS_DIGFILT2_bp Predefined. */


/* EVSYS.CH2CTRL bit masks and bit positions */
/* EVSYS_QDIRM_gm Predefined. */
/* EVSYS_QDIRM_gp Predefined. */
/* EVSYS_QDIRM0_bm Predefined. */
/* EVSYS_QDIRM0_bp Predefined. */
/* EVSYS_QDIRM1_bm Predefined. */
/* EVSYS_QDIRM1_bp Predefined. */

/* EVSYS_QDIEN_bm Predefined. */
/* EVSYS_QDIEN_bp Predefined. */

/* EVSYS_QDEN_bm Predefined. */
/* EVSYS_QDEN_bp Predefined. */

/* EVSYS_DIGFILT_gm Predefined. */
/* EVSYS_DIGFILT_gp Predefined. */
/* EVSYS_DIGFILT0_bm Predefined. */
/* EVSYS_DIGFILT0_bp Predefined. */
/* EVSYS_DIGFILT1_bm Predefined. */
/* EVSYS_DIGFILT1_bp Predefined. */
/* EVSYS_DIGFILT2_bm Predefined. */
/* EVSYS_DIGFILT2_bp Predefined. */


/* EVSYS.CH3CTRL bit masks and bit positions */
/* EVSYS_DIGFILT_gm Predefined. */
/* EVSYS_DIGFILT_gp Predefined. */
/* EVSYS_DIGFILT0_bm Predefined. */
/* EVSYS_DIGFILT0_bp Predefined. */
/* EVSYS_DIGFILT1_bm Predefined. */
/* EVSYS_DIGFILT1_bp Predefined. */
/* EVSYS_DIGFILT2_bm Predefined. */
/* EVSYS_DIGFILT2_bp Predefined. */


/* EVSYS.CH4CTRL bit masks and bit positions */
/* EVSYS_QDIRM_gm Predefined. */
/* EVSYS_QDIRM_gp Predefined. */
/* EVSYS_QDIRM0_bm Predefined. */
/* EVSYS_QDIRM0_bp Predefined. */
/* EVSYS_QDIRM1_bm Predefined. */
/* EVSYS_QDIRM1_bp Predefined. */

/* EVSYS_QDIEN_bm Predefined. */
/* EVSYS_QDIEN_bp Predefined. */

/* EVSYS_QDEN_bm Predefined. */
/* EVSYS_QDEN_bp Predefined. */

/* EVSYS_DIGFILT_gm Predefined. */
/* EVSYS_DIGFILT_gp Predefined. */
/* EVSYS_DIGFILT0_bm Predefined. */
/* EVSYS_DIGFILT0_bp Predefined. */
/* EVSYS_DIGFILT1_bm Predefined. */
/* EVSYS_DIGFILT1_bp Predefined. */
/* EVSYS_DIGFILT2_bm Predefined. */
/* EVSYS_DIGFILT2_bp Predefined. */


/* EVSYS.CH5CTRL bit masks and bit positions */
/* EVSYS_DIGFILT_gm Predefined. */
/* EVSYS_DIGFILT_gp Predefined. */
/* EVSYS_DIGFILT0_bm Predefined. */
/* EVSYS_DIGFILT0_bp Predefined. */
/* EVSYS_DIGFILT1_bm Predefined. */
/* EVSYS_DIGFILT1_bp Predefined. */
/* EVSYS_DIGFILT2_bm Predefined. */
/* EVSYS_DIGFILT2_bp Predefined. */


/* EVSYS.CH6CTRL bit masks and bit positions */
/* EVSYS_DIGFILT_gm Predefined. */
/* EVSYS_DIGFILT_gp Predefined. */
/* EVSYS_DIGFILT0_bm Predefined. */
/* EVSYS_DIGFILT0_bp Predefined. */
/* EVSYS_DIGFILT1_bm Predefined. */
/* EVSYS_DIGFILT1_bp Predefined. */
/* EVSYS_DIGFILT2_bm Predefined. */
/* EVSYS_DIGFILT2_bp Predefined. */


/* EVSYS.CH7CTRL bit masks and bit positions */
/* EVSYS_DIGFILT_gm Predefined. */
/* EVSYS_DIGFILT_gp Predefined. */
/* EVSYS_DIGFILT0_bm Predefined. */
/* EVSYS_DIGFILT0_bp Predefined. */
/* EVSYS_DIGFILT1_bm Predefined. */
/* EVSYS_DIGFILT1_bp Predefined. */
/* EVSYS_DIGFILT2_bm Predefined. */
/* EVSYS_DIGFILT2_bp Predefined. */


/* NVM - Non Volatile Memory Controller */
/* NVM.CMD bit masks and bit positions */
#define NVM_CMD_gm 0xFF /* Command group mask. */
#define NVM_CMD_gp 0 /* Command group position. */
#define NVM_CMD0_bm (1 & lt; & lt; 0) /* Command bit 0 mask. */
#define NVM_CMD0_bp 0 /* Command bit 0 position. */
#define NVM_CMD1_bm (1 & lt; & lt; 1) /* Command bit 1 mask. */
#define NVM_CMD1_bp 1 /* Command bit 1 position. */
#define NVM_CMD2_bm (1 & lt; & lt; 2) /* Command bit 2 mask. */
#define NVM_CMD2_bp 2 /* Command bit 2 position. */
#define NVM_CMD3_bm (1 & lt; & lt; 3) /* Command bit 3 mask. */
#define NVM_CMD3_bp 3 /* Command bit 3 position. */
#define NVM_CMD4_bm (1 & lt; & lt; 4) /* Command bit 4 mask. */
#define NVM_CMD4_bp 4 /* Command bit 4 position. */
#define NVM_CMD5_bm (1 & lt; & lt; 5) /* Command bit 5 mask. */
#define NVM_CMD5_bp 5 /* Command bit 5 position. */
#define NVM_CMD6_bm (1 & lt; & lt; 6) /* Command bit 6 mask. */
#define NVM_CMD6_bp 6 /* Command bit 6 position. */
#define NVM_CMD7_bm (1 & lt; & lt; 7) /* Command bit 7 mask. */
#define NVM_CMD7_bp 7 /* Command bit 7 position. */


/* NVM.CTRLA bit masks and bit positions */
#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */
#define NVM_CMDEX_bp 0 /* Command Execute bit position. */


/* NVM.CTRLB bit masks and bit positions */
#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */
#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */

#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */
#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */

#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */
#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */

#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */
#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */


/* NVM.INTCTRL bit masks and bit positions */
#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */
#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */
#define NVM_SPMLVL0_bm (1 & lt; & lt; 2) /* SPM Interrupt Level bit 0 mask. */
#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */
#define NVM_SPMLVL1_bm (1 & lt; & lt; 3) /* SPM Interrupt Level bit 1 mask. */
#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */

#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */
#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */
#define NVM_EELVL0_bm (1 & lt; & lt; 0) /* EEPROM Interrupt Level bit 0 mask. */
#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */
#define NVM_EELVL1_bm (1 & lt; & lt; 1) /* EEPROM Interrupt Level bit 1 mask. */
#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */


/* NVM.STATUS bit masks and bit positions */
#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */
#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */

#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */
#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */

#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */
#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */

#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */
#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */


/* NVM.LOCKBITS bit masks and bit positions */
#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
#define NVM_BLBB0_bm (1 & lt; & lt; 6) /* Boot Lock Bits - Boot Section bit 0 mask. */
#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
#define NVM_BLBB1_bm (1 & lt; & lt; 7) /* Boot Lock Bits - Boot Section bit 1 mask. */
#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */

#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
#define NVM_BLBA0_bm (1 & lt; & lt; 4) /* Boot Lock Bits - Application Section bit 0 mask. */
#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
#define NVM_BLBA1_bm (1 & lt; & lt; 5) /* Boot Lock Bits - Application Section bit 1 mask. */
#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */

#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
#define NVM_BLBAT0_bm (1 & lt; & lt; 2) /* Boot Lock Bits - Application Table bit 0 mask. */
#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
#define NVM_BLBAT1_bm (1 & lt; & lt; 3) /* Boot Lock Bits - Application Table bit 1 mask. */
#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */

#define NVM_LB_gm 0x03 /* Lock Bits group mask. */
#define NVM_LB_gp 0 /* Lock Bits group position. */
#define NVM_LB0_bm (1 & lt; & lt; 0) /* Lock Bits bit 0 mask. */
#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */
#define NVM_LB1_bm (1 & lt; & lt; 1) /* Lock Bits bit 1 mask. */
#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */


/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */
#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
#define NVM_LOCKBITS_BLBB0_bm (1 & lt; & lt; 6) /* Boot Lock Bits - Boot Section bit 0 mask. */
#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
#define NVM_LOCKBITS_BLBB1_bm (1 & lt; & lt; 7) /* Boot Lock Bits - Boot Section bit 1 mask. */
#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */

#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
#define NVM_LOCKBITS_BLBA0_bm (1 & lt; & lt; 4) /* Boot Lock Bits - Application Section bit 0 mask. */
#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
#define NVM_LOCKBITS_BLBA1_bm (1 & lt; & lt; 5) /* Boot Lock Bits - Application Section bit 1 mask. */
#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */

#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
#define NVM_LOCKBITS_BLBAT0_bm (1 & lt; & lt; 2) /* Boot Lock Bits - Application Table bit 0 mask. */
#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
#define NVM_LOCKBITS_BLBAT1_bm (1 & lt; & lt; 3) /* Boot Lock Bits - Application Table bit 1 mask. */
#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */

#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */
#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */
#define NVM_LOCKBITS_LB0_bm (1 & lt; & lt; 0) /* Lock Bits bit 0 mask. */
#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */
#define NVM_LOCKBITS_LB1_bm (1 & lt; & lt; 1) /* Lock Bits bit 1 mask. */
#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */


/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */
#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */
#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */
#define NVM_FUSES_JTAGUSERID0_bm (1 & lt; & lt; 0) /* JTAG User ID bit 0 mask. */
#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */
#define NVM_FUSES_JTAGUSERID1_bm (1 & lt; & lt; 1) /* JTAG User ID bit 1 mask. */
#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */
#define NVM_FUSES_JTAGUSERID2_bm (1 & lt; & lt; 2) /* JTAG User ID bit 2 mask. */
#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */
#define NVM_FUSES_JTAGUSERID3_bm (1 & lt; & lt; 3) /* JTAG User ID bit 3 mask. */
#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */
#define NVM_FUSES_JTAGUSERID4_bm (1 & lt; & lt; 4) /* JTAG User ID bit 4 mask. */
#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */
#define NVM_FUSES_JTAGUSERID5_bm (1 & lt; & lt; 5) /* JTAG User ID bit 5 mask. */
#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */
#define NVM_FUSES_JTAGUSERID6_bm (1 & lt; & lt; 6) /* JTAG User ID bit 6 mask. */
#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */
#define NVM_FUSES_JTAGUSERID7_bm (1 & lt; & lt; 7) /* JTAG User ID bit 7 mask. */
#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */


/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */
#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */
#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */
#define NVM_FUSES_WDWP0_bm (1 & lt; & lt; 4) /* Watchdog Window Timeout Period bit 0 mask. */
#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */
#define NVM_FUSES_WDWP1_bm (1 & lt; & lt; 5) /* Watchdog Window Timeout Period bit 1 mask. */
#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */
#define NVM_FUSES_WDWP2_bm (1 & lt; & lt; 6) /* Watchdog Window Timeout Period bit 2 mask. */
#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */
#define NVM_FUSES_WDWP3_bm (1 & lt; & lt; 7) /* Watchdog Window Timeout Period bit 3 mask. */
#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */

#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */
#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */
#define NVM_FUSES_WDP0_bm (1 & lt; & lt; 0) /* Watchdog Timeout Period bit 0 mask. */
#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */
#define NVM_FUSES_WDP1_bm (1 & lt; & lt; 1) /* Watchdog Timeout Period bit 1 mask. */
#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */
#define NVM_FUSES_WDP2_bm (1 & lt; & lt; 2) /* Watchdog Timeout Period bit 2 mask. */
#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */
#define NVM_FUSES_WDP3_bm (1 & lt; & lt; 3) /* Watchdog Timeout Period bit 3 mask. */
#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */


/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */
#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */
#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */

#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */
#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */

#define NVM_FUSES_BODACT_gm 0x0C /* BOD Operation in Active Mode group mask. */
#define NVM_FUSES_BODACT_gp 2 /* BOD Operation in Active Mode group position. */
#define NVM_FUSES_BODACT0_bm (1 & lt; & lt; 2) /* BOD Operation in Active Mode bit 0 mask. */
#define NVM_FUSES_BODACT0_bp 2 /* BOD Operation in Active Mode bit 0 position. */
#define NVM_FUSES_BODACT1_bm (1 & lt; & lt; 3) /* BOD Operation in Active Mode bit 1 mask. */
#define NVM_FUSES_BODACT1_bp 3 /* BOD Operation in Active Mode bit 1 position. */

#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */
#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */
#define NVM_FUSES_BODPD0_bm (1 & lt; & lt; 0) /* BOD Operation in Power-Down Mode bit 0 mask. */
#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */
#define NVM_FUSES_BODPD1_bm (1 & lt; & lt; 1) /* BOD Operation in Power-Down Mode bit 1 mask. */
#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */


/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */
#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */
#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */
#define NVM_FUSES_SUT0_bm (1 & lt; & lt; 2) /* Start-up Time bit 0 mask. */
#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */
#define NVM_FUSES_SUT1_bm (1 & lt; & lt; 3) /* Start-up Time bit 1 mask. */
#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */

#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */
#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */

#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */
#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */


/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */
#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */
#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */

#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */
#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */
#define NVM_FUSES_BODLVL0_bm (1 & lt; & lt; 0) /* Brown Out Detection Voltage Level bit 0 mask. */
#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */
#define NVM_FUSES_BODLVL1_bm (1 & lt; & lt; 1) /* Brown Out Detection Voltage Level bit 1 mask. */
#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */
#define NVM_FUSES_BODLVL2_bm (1 & lt; & lt; 2) /* Brown Out Detection Voltage Level bit 2 mask. */
#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */


/* AC - Analog Comparator */
/* AC.AC0CTRL bit masks and bit positions */
#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */
#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */
#define AC_INTMODE0_bm (1 & lt; & lt; 6) /* Interrupt Mode bit 0 mask. */
#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */
#define AC_INTMODE1_bm (1 & lt; & lt; 7) /* Interrupt Mode bit 1 mask. */
#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */

#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */
#define AC_INTLVL_gp 4 /* Interrupt Level group position. */
#define AC_INTLVL0_bm (1 & lt; & lt; 4) /* Interrupt Level bit 0 mask. */
#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */
#define AC_INTLVL1_bm (1 & lt; & lt; 5) /* Interrupt Level bit 1 mask. */
#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */

#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */
#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */

#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */
#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */
#define AC_HYSMODE0_bm (1 & lt; & lt; 1) /* Hysteresis Mode bit 0 mask. */
#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */
#define AC_HYSMODE1_bm (1 & lt; & lt; 2) /* Hysteresis Mode bit 1 mask. */
#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */

#define AC_ENABLE_bm 0x01 /* Enable bit mask. */
#define AC_ENABLE_bp 0 /* Enable bit position. */


/* AC.AC1CTRL bit masks and bit positions */
/* AC_INTMODE_gm Predefined. */
/* AC_INTMODE_gp Predefined. */
/* AC_INTMODE0_bm Predefined. */
/* AC_INTMODE0_bp Predefined. */
/* AC_INTMODE1_bm Predefined. */
/* AC_INTMODE1_bp Predefined. */

/* AC_INTLVL_gm Predefined. */
/* AC_INTLVL_gp Predefined. */
/* AC_INTLVL0_bm Predefined. */
/* AC_INTLVL0_bp Predefined. */
/* AC_INTLVL1_bm Predefined. */
/* AC_INTLVL1_bp Predefined. */

/* AC_HSMODE_bm Predefined. */
/* AC_HSMODE_bp Predefined. */

/* AC_HYSMODE_gm Predefined. */
/* AC_HYSMODE_gp Predefined. */
/* AC_HYSMODE0_bm Predefined. */
/* AC_HYSMODE0_bp Predefined. */
/* AC_HYSMODE1_bm Predefined. */
/* AC_HYSMODE1_bp Predefined. */

/* AC_ENABLE_bm Predefined. */
/* AC_ENABLE_bp Predefined. */


/* AC.AC0MUXCTRL bit masks and bit positions */
#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */
#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */
#define AC_MUXPOS0_bm (1 & lt; & lt; 3) /* MUX Positive Input bit 0 mask. */
#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */
#define AC_MUXPOS1_bm (1 & lt; & lt; 4) /* MUX Positive Input bit 1 mask. */
#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */
#define AC_MUXPOS2_bm (1 & lt; & lt; 5) /* MUX Positive Input bit 2 mask. */
#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */

#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */
#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */
#define AC_MUXNEG0_bm (1 & lt; & lt; 0) /* MUX Negative Input bit 0 mask. */
#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */
#define AC_MUXNEG1_bm (1 & lt; & lt; 1) /* MUX Negative Input bit 1 mask. */
#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */
#define AC_MUXNEG2_bm (1 & lt; & lt; 2) /* MUX Negative Input bit 2 mask. */
#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */


/* AC.AC1MUXCTRL bit masks and bit positions */
/* AC_MUXPOS_gm Predefined. */
/* AC_MUXPOS_gp Predefined. */
/* AC_MUXPOS0_bm Predefined. */
/* AC_MUXPOS0_bp Predefined. */
/* AC_MUXPOS1_bm Predefined. */
/* AC_MUXPOS1_bp Predefined. */
/* AC_MUXPOS2_bm Predefined. */
/* AC_MUXPOS2_bp Predefined. */

/* AC_MUXNEG_gm Predefined. */
/* AC_MUXNEG_gp Predefined. */
/* AC_MUXNEG0_bm Predefined. */
/* AC_MUXNEG0_bp Predefined. */
/* AC_MUXNEG1_bm Predefined. */
/* AC_MUXNEG1_bp Predefined. */
/* AC_MUXNEG2_bm Predefined. */
/* AC_MUXNEG2_bp Predefined. */


/* AC.CTRLA bit masks and bit positions */
#define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */
#define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */


/* AC.CTRLB bit masks and bit positions */
#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */
#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */
#define AC_SCALEFAC0_bm (1 & lt; & lt; 0) /* VCC Voltage Scaler Factor bit 0 mask. */
#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */
#define AC_SCALEFAC1_bm (1 & lt; & lt; 1) /* VCC Voltage Scaler Factor bit 1 mask. */
#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */
#define AC_SCALEFAC2_bm (1 & lt; & lt; 2) /* VCC Voltage Scaler Factor bit 2 mask. */
#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */
#define AC_SCALEFAC3_bm (1 & lt; & lt; 3) /* VCC Voltage Scaler Factor bit 3 mask. */
#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */
#define AC_SCALEFAC4_bm (1 & lt; & lt; 4) /* VCC Voltage Scaler Factor bit 4 mask. */
#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */
#define AC_SCALEFAC5_bm (1 & lt; & lt; 5) /* VCC Voltage Scaler Factor bit 5 mask. */
#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */


/* AC.WINCTRL bit masks and bit positions */
#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */
#define AC_WEN_bp 4 /* Window Mode Enable bit position. */

#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */
#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */
#define AC_WINTMODE0_bm (1 & lt; & lt; 2) /* Window Interrupt Mode bit 0 mask. */
#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */
#define AC_WINTMODE1_bm (1 & lt; & lt; 3) /* Window Interrupt Mode bit 1 mask. */
#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */

#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */
#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */
#define AC_WINTLVL0_bm (1 & lt; & lt; 0) /* Window Interrupt Level bit 0 mask. */
#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */
#define AC_WINTLVL1_bm (1 & lt; & lt; 1) /* Window Interrupt Level bit 1 mask. */
#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */


/* AC.STATUS bit masks and bit positions */
#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */
#define AC_WSTATE_gp 6 /* Window Mode State group position. */
#define AC_WSTATE0_bm (1 & lt; & lt; 6) /* Window Mode State bit 0 mask. */
#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */
#define AC_WSTATE1_bm (1 & lt; & lt; 7) /* Window Mode State bit 1 mask. */
#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */

#define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */
#define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */

#define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */
#define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */

#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */
#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */

#define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */
#define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */

#define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */
#define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */


/* ADC - Analog/Digital Converter */
/* ADC_CH.CTRL bit masks and bit positions */
#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */
#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */

#define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */
#define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */
#define ADC_CH_GAINFAC0_bm (1 & lt; & lt; 2) /* Gain Factor bit 0 mask. */
#define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */
#define ADC_CH_GAINFAC1_bm (1 & lt; & lt; 3) /* Gain Factor bit 1 mask. */
#define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */
#define ADC_CH_GAINFAC2_bm (1 & lt; & lt; 4) /* Gain Factor bit 2 mask. */
#define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */

#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */
#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */
#define ADC_CH_INPUTMODE0_bm (1 & lt; & lt; 0) /* Input Mode Select bit 0 mask. */
#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */
#define ADC_CH_INPUTMODE1_bm (1 & lt; & lt; 1) /* Input Mode Select bit 1 mask. */
#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */


/* ADC_CH.MUXCTRL bit masks and bit positions */
#define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */
#define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */
#define ADC_CH_MUXPOS0_bm (1 & lt; & lt; 3) /* Positive Input Select bit 0 mask. */
#define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */
#define ADC_CH_MUXPOS1_bm (1 & lt; & lt; 4) /* Positive Input Select bit 1 mask. */
#define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */
#define ADC_CH_MUXPOS2_bm (1 & lt; & lt; 5) /* Positive Input Select bit 2 mask. */
#define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */
#define ADC_CH_MUXPOS3_bm (1 & lt; & lt; 6) /* Positive Input Select bit 3 mask. */
#define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */

#define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */
#define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */
#define ADC_CH_MUXINT0_bm (1 & lt; & lt; 3) /* Internal Input Select bit 0 mask. */
#define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */
#define ADC_CH_MUXINT1_bm (1 & lt; & lt; 4) /* Internal Input Select bit 1 mask. */
#define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */
#define ADC_CH_MUXINT2_bm (1 & lt; & lt; 5) /* Internal Input Select bit 2 mask. */
#define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */
#define ADC_CH_MUXINT3_bm (1 & lt; & lt; 6) /* Internal Input Select bit 3 mask. */
#define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */

#define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */
#define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */
#define ADC_CH_MUXNEG0_bm (1 & lt; & lt; 0) /* Negative Input Select bit 0 mask. */
#define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */
#define ADC_CH_MUXNEG1_bm (1 & lt; & lt; 1) /* Negative Input Select bit 1 mask. */
#define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */


/* ADC_CH.INTCTRL bit masks and bit positions */
#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */
#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */
#define ADC_CH_INTMODE0_bm (1 & lt; & lt; 2) /* Interrupt Mode bit 0 mask. */
#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */
#define ADC_CH_INTMODE1_bm (1 & lt; & lt; 3) /* Interrupt Mode bit 1 mask. */
#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */

#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */
#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */
#define ADC_CH_INTLVL0_bm (1 & lt; & lt; 0) /* Interrupt Level bit 0 mask. */
#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */
#define ADC_CH_INTLVL1_bm (1 & lt; & lt; 1) /* Interrupt Level bit 1 mask. */
#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */


/* ADC_CH.INTFLAGS bit masks and bit positions */
#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */
#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */


/* ADC.CTRLA bit masks and bit positions */
#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */
#define ADC_DMASEL_gp 6 /* DMA Selection group position. */
#define ADC_DMASEL0_bm (1 & lt; & lt; 6) /* DMA Selection bit 0 mask. */
#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */
#define ADC_DMASEL1_bm (1 & lt; & lt; 7) /* DMA Selection bit 1 mask. */
#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */

#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */
#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */

#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */
#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */

#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */
#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */

#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */
#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */

#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */
#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */

#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */
#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */


/* ADC.CTRLB bit masks and bit positions */
#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */
#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */

#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */
#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */

#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */
#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */
#define ADC_RESOLUTION0_bm (1 & lt; & lt; 1) /* Result Resolution bit 0 mask. */
#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */
#define ADC_RESOLUTION1_bm (1 & lt; & lt; 2) /* Result Resolution bit 1 mask. */
#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */


/* ADC.REFCTRL bit masks and bit positions */
#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */
#define ADC_REFSEL_gp 4 /* Reference Selection group position. */
#define ADC_REFSEL0_bm (1 & lt; & lt; 4) /* Reference Selection bit 0 mask. */
#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */
#define ADC_REFSEL1_bm (1 & lt; & lt; 5) /* Reference Selection bit 1 mask. */
#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */

#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */
#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */

#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */
#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */


/* ADC.EVCTRL bit masks and bit positions */
#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */
#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */
#define ADC_SWEEP0_bm (1 & lt; & lt; 6) /* Channel Sweep Selection bit 0 mask. */
#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */
#define ADC_SWEEP1_bm (1 & lt; & lt; 7) /* Channel Sweep Selection bit 1 mask. */
#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */

#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */
#define ADC_EVSEL_gp 3 /* Event Input Select group position. */
#define ADC_EVSEL0_bm (1 & lt; & lt; 3) /* Event Input Select bit 0 mask. */
#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */
#define ADC_EVSEL1_bm (1 & lt; & lt; 4) /* Event Input Select bit 1 mask. */
#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */
#define ADC_EVSEL2_bm (1 & lt; & lt; 5) /* Event Input Select bit 2 mask. */
#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */

#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */
#define ADC_EVACT_gp 0 /* Event Action Select group position. */
#define ADC_EVACT0_bm (1 & lt; & lt; 0) /* Event Action Select bit 0 mask. */
#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */
#define ADC_EVACT1_bm (1 & lt; & lt; 1) /* Event Action Select bit 1 mask. */
#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */
#define ADC_EVACT2_bm (1 & lt; & lt; 2) /* Event Action Select bit 2 mask. */
#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */


/* ADC.PRESCALER bit masks and bit positions */
#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */
#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */
#define ADC_PRESCALER0_bm (1 & lt; & lt; 0) /* Clock Prescaler Selection bit 0 mask. */
#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */
#define ADC_PRESCALER1_bm (1 & lt; & lt; 1) /* Clock Prescaler Selection bit 1 mask. */
#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */
#define ADC_PRESCALER2_bm (1 & lt; & lt; 2) /* Clock Prescaler Selection bit 2 mask. */
#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */


/* ADC.CALCTRL bit masks and bit positions */
#define ADC_CAL_bm 0x01 /* ADC Calibration Start bit mask. */
#define ADC_CAL_bp 0 /* ADC Calibration Start bit position. */


/* ADC.INTFLAGS bit masks and bit positions */
#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */
#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */

#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */
#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */

#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */
#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */

#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */
#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */


/* DAC - Digital/Analog Converter */
/* DAC.CTRLA bit masks and bit positions */
#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */
#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */

#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */
#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */

#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */
#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */

#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */
#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */

#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */
#define DAC_ENABLE_bp 0 /* Enable bit position. */


/* DAC.CTRLB bit masks and bit positions */
#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */
#define DAC_CHSEL_gp 5 /* Channel Select group position. */
#define DAC_CHSEL0_bm (1 & lt; & lt; 5) /* Channel Select bit 0 mask. */
#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */
#define DAC_CHSEL1_bm (1 & lt; & lt; 6) /* Channel Select bit 1 mask. */
#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */

#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */
#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */

#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */
#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */


/* DAC.CTRLC bit masks and bit positions */
#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */
#define DAC_REFSEL_gp 3 /* Reference Select group position. */
#define DAC_REFSEL0_bm (1 & lt; & lt; 3) /* Reference Select bit 0 mask. */
#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */
#define DAC_REFSEL1_bm (1 & lt; & lt; 4) /* Reference Select bit 1 mask. */
#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */

#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */
#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */


/* DAC.EVCTRL bit masks and bit positions */
#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */
#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */
#define DAC_EVSEL0_bm (1 & lt; & lt; 0) /* Event Input Selection bit 0 mask. */
#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */
#define DAC_EVSEL1_bm (1 & lt; & lt; 1) /* Event Input Selection bit 1 mask. */
#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */
#define DAC_EVSEL2_bm (1 & lt; & lt; 2) /* Event Input Selection bit 2 mask. */
#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */


/* DAC.TIMCTRL bit masks and bit positions */
#define DAC_CONINTVAL_gm 0x70 /* Conversion Intercal group mask. */
#define DAC_CONINTVAL_gp 4 /* Conversion Intercal group position. */
#define DAC_CONINTVAL0_bm (1 & lt; & lt; 4) /* Conversion Intercal bit 0 mask. */
#define DAC_CONINTVAL0_bp 4 /* Conversion Intercal bit 0 position. */
#define DAC_CONINTVAL1_bm (1 & lt; & lt; 5) /* Conversion Intercal bit 1 mask. */
#define DAC_CONINTVAL1_bp 5 /* Conversion Intercal bit 1 position. */
#define DAC_CONINTVAL2_bm (1 & lt; & lt; 6) /* Conversion Intercal bit 2 mask. */
#define DAC_CONINTVAL2_bp 6 /* Conversion Intercal bit 2 position. */

#define DAC_REFRESH_gm 0x0F /* Refresh Timing Control group mask. */
#define DAC_REFRESH_gp 0 /* Refresh Timing Control group position. */
#define DAC_REFRESH0_bm (1 & lt; & lt; 0) /* Refresh Timing Control bit 0 mask. */
#define DAC_REFRESH0_bp 0 /* Refresh Timing Control bit 0 position. */
#define DAC_REFRESH1_bm (1 & lt; & lt; 1) /* Refresh Timing Control bit 1 mask. */
#define DAC_REFRESH1_bp 1 /* Refresh Timing Control bit 1 position. */
#define DAC_REFRESH2_bm (1 & lt; & lt; 2) /* Refresh Timing Control bit 2 mask. */
#define DAC_REFRESH2_bp 2 /* Refresh Timing Control bit 2 position. */
#define DAC_REFRESH3_bm (1 & lt; & lt; 3) /* Refresh Timing Control bit 3 mask. */
#define DAC_REFRESH3_bp 3 /* Refresh Timing Control bit 3 position. */


/* DAC.STATUS bit masks and bit positions */
#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */
#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */

#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */
#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */


/* RTC - Real-Time Clounter */
/* RTC.CTRL bit masks and bit positions */
#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */
#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */
#define RTC_PRESCALER0_bm (1 & lt; & lt; 0) /* Prescaling Factor bit 0 mask. */
#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */
#define RTC_PRESCALER1_bm (1 & lt; & lt; 1) /* Prescaling Factor bit 1 mask. */
#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */
#define RTC_PRESCALER2_bm (1 & lt; & lt; 2) /* Prescaling Factor bit 2 mask. */
#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */


/* RTC.STATUS bit masks and bit positions */
#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */
#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */


/* RTC.INTCTRL bit masks and bit positions */
#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */
#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */
#define RTC_COMPINTLVL0_bm (1 & lt; & lt; 2) /* Compare Match Interrupt Level bit 0 mask. */
#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */
#define RTC_COMPINTLVL1_bm (1 & lt; & lt; 3) /* Compare Match Interrupt Level bit 1 mask. */
#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */

#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */
#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */
#define RTC_OVFINTLVL0_bm (1 & lt; & lt; 0) /* Overflow Interrupt Level bit 0 mask. */
#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */
#define RTC_OVFINTLVL1_bm (1 & lt; & lt; 1) /* Overflow Interrupt Level bit 1 mask. */
#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */


/* RTC.INTFLAGS bit masks and bit positions */
#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */
#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */

#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */


/* EBI - External Bus Interface */
/* EBI_CS.CTRLA bit masks and bit positions */
#define EBI_CS_ASPACE_gm 0x7C /* Address Space group mask. */
#define EBI_CS_ASPACE_gp 2 /* Address Space group position. */
#define EBI_CS_ASPACE0_bm (1 & lt; & lt; 2) /* Address Space bit 0 mask. */
#define EBI_CS_ASPACE0_bp 2 /* Address Space bit 0 position. */
#define EBI_CS_ASPACE1_bm (1 & lt; & lt; 3) /* Address Space bit 1 mask. */
#define EBI_CS_ASPACE1_bp 3 /* Address Space bit 1 position. */
#define EBI_CS_ASPACE2_bm (1 & lt; & lt; 4) /* Address Space bit 2 mask. */
#define EBI_CS_ASPACE2_bp 4 /* Address Space bit 2 position. */
#define EBI_CS_ASPACE3_bm (1 & lt; & lt; 5) /* Address Space bit 3 mask. */
#define EBI_CS_ASPACE3_bp 5 /* Address Space bit 3 position. */
#define EBI_CS_ASPACE4_bm (1 & lt; & lt; 6) /* Address Space bit 4 mask. */
#define EBI_CS_ASPACE4_bp 6 /* Address Space bit 4 position. */

#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */
#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */
#define EBI_CS_MODE0_bm (1 & lt; & lt; 0) /* Memory Mode bit 0 mask. */
#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */
#define EBI_CS_MODE1_bm (1 & lt; & lt; 1) /* Memory Mode bit 1 mask. */
#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */


/* EBI_CS.CTRLB bit masks and bit positions */
#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */
#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */
#define EBI_CS_SRWS0_bm (1 & lt; & lt; 0) /* SRAM Wait State Cycles bit 0 mask. */
#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */
#define EBI_CS_SRWS1_bm (1 & lt; & lt; 1) /* SRAM Wait State Cycles bit 1 mask. */
#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */
#define EBI_CS_SRWS2_bm (1 & lt; & lt; 2) /* SRAM Wait State Cycles bit 2 mask. */
#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */

#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */
#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */

#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */
#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */

#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */
#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */
#define EBI_CS_SDMODE0_bm (1 & lt; & lt; 0) /* SDRAM Mode bit 0 mask. */
#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */
#define EBI_CS_SDMODE1_bm (1 & lt; & lt; 1) /* SDRAM Mode bit 1 mask. */
#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */


/* EBI.CTRL bit masks and bit positions */
#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */
#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */
#define EBI_SDDATAW0_bm (1 & lt; & lt; 6) /* SDRAM Data Width Setting bit 0 mask. */
#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */
#define EBI_SDDATAW1_bm (1 & lt; & lt; 7) /* SDRAM Data Width Setting bit 1 mask. */
#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */

#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */
#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */
#define EBI_LPCMODE0_bm (1 & lt; & lt; 4) /* SRAM LPC Mode bit 0 mask. */
#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */
#define EBI_LPCMODE1_bm (1 & lt; & lt; 5) /* SRAM LPC Mode bit 1 mask. */
#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */

#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */
#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */
#define EBI_SRMODE0_bm (1 & lt; & lt; 2) /* SRAM Mode bit 0 mask. */
#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */
#define EBI_SRMODE1_bm (1 & lt; & lt; 3) /* SRAM Mode bit 1 mask. */
#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */

#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */
#define EBI_IFMODE_gp 0 /* Interface Mode group position. */
#define EBI_IFMODE0_bm (1 & lt; & lt; 0) /* Interface Mode bit 0 mask. */
#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */
#define EBI_IFMODE1_bm (1 & lt; & lt; 1) /* Interface Mode bit 1 mask. */
#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */


/* EBI.SDRAMCTRLA bit masks and bit positions */
#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */
#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */

#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */
#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */

#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */
#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */
#define EBI_SDCOL0_bm (1 & lt; & lt; 0) /* SDRAM Column Bits Setting bit 0 mask. */
#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */
#define EBI_SDCOL1_bm (1 & lt; & lt; 1) /* SDRAM Column Bits Setting bit 1 mask. */
#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */


/* EBI.SDRAMCTRLB bit masks and bit positions */
#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */
#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */
#define EBI_MRDLY0_bm (1 & lt; & lt; 6) /* SDRAM Mode Register Delay bit 0 mask. */
#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */
#define EBI_MRDLY1_bm (1 & lt; & lt; 7) /* SDRAM Mode Register Delay bit 1 mask. */
#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */

#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */
#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */
#define EBI_ROWCYCDLY0_bm (1 & lt; & lt; 3) /* SDRAM Row Cycle Delay bit 0 mask. */
#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */
#define EBI_ROWCYCDLY1_bm (1 & lt; & lt; 4) /* SDRAM Row Cycle Delay bit 1 mask. */
#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */
#define EBI_ROWCYCDLY2_bm (1 & lt; & lt; 5) /* SDRAM Row Cycle Delay bit 2 mask. */
#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */

#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */
#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */
#define EBI_RPDLY0_bm (1 & lt; & lt; 0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */
#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */
#define EBI_RPDLY1_bm (1 & lt; & lt; 1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */
#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */
#define EBI_RPDLY2_bm (1 & lt; & lt; 2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */
#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */


/* EBI.SDRAMCTRLC bit masks and bit positions */
#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */
#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */
#define EBI_WRDLY0_bm (1 & lt; & lt; 6) /* SDRAM Write Recovery Delay bit 0 mask. */
#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */
#define EBI_WRDLY1_bm (1 & lt; & lt; 7) /* SDRAM Write Recovery Delay bit 1 mask. */
#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */

#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */
#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */
#define EBI_ESRDLY0_bm (1 & lt; & lt; 3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */
#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */
#define EBI_ESRDLY1_bm (1 & lt; & lt; 4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */
#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */
#define EBI_ESRDLY2_bm (1 & lt; & lt; 5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */
#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */

#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */
#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */
#define EBI_ROWCOLDLY0_bm (1 & lt; & lt; 0) /* SDRAM Row-to-Column Delay bit 0 mask. */
#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */
#define EBI_ROWCOLDLY1_bm (1 & lt; & lt; 1) /* SDRAM Row-to-Column Delay bit 1 mask. */
#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */
#define EBI_ROWCOLDLY2_bm (1 & lt; & lt; 2) /* SDRAM Row-to-Column Delay bit 2 mask. */
#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */


/* TWI - Two-Wire Interface */
/* TWI_MASTER.CTRLA bit masks and bit positions */
#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */
#define TWI_MASTER_INTLVL0_bm (1 & lt; & lt; 6) /* Interrupt Level bit 0 mask. */
#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
#define TWI_MASTER_INTLVL1_bm (1 & lt; & lt; 7) /* Interrupt Level bit 1 mask. */
#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */

#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */
#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */

#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */
#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */

#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */
#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */


/* TWI_MASTER.CTRLB bit masks and bit positions */
#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */
#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */
#define TWI_MASTER_TIMEOUT0_bm (1 & lt; & lt; 2) /* Inactive Bus Timeout bit 0 mask. */
#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */
#define TWI_MASTER_TIMEOUT1_bm (1 & lt; & lt; 3) /* Inactive Bus Timeout bit 1 mask. */
#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */

#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */
#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */

#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */


/* TWI_MASTER.CTRLC bit masks and bit positions */
#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */

#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */
#define TWI_MASTER_CMD_gp 0 /* Command group position. */
#define TWI_MASTER_CMD0_bm (1 & lt; & lt; 0) /* Command bit 0 mask. */
#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */
#define TWI_MASTER_CMD1_bm (1 & lt; & lt; 1) /* Command bit 1 mask. */
#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */


/* TWI_MASTER.STATUS bit masks and bit positions */
#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */
#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */

#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */
#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */

#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */

#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */

#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */
#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */

#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */
#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */

#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */
#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */
#define TWI_MASTER_BUSSTATE0_bm (1 & lt; & lt; 0) /* Bus State bit 0 mask. */
#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */
#define TWI_MASTER_BUSSTATE1_bm (1 & lt; & lt; 1) /* Bus State bit 1 mask. */
#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */


/* TWI_SLAVE.CTRLA bit masks and bit positions */
#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */
#define TWI_SLAVE_INTLVL0_bm (1 & lt; & lt; 6) /* Interrupt Level bit 0 mask. */
#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
#define TWI_SLAVE_INTLVL1_bm (1 & lt; & lt; 7) /* Interrupt Level bit 1 mask. */
#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */

#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */
#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */

#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */
#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */

#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */
#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */

#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */
#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */

#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */
#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */

#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */


/* TWI_SLAVE.CTRLB bit masks and bit positions */
#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */

#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */
#define TWI_SLAVE_CMD_gp 0 /* Command group position. */
#define TWI_SLAVE_CMD0_bm (1 & lt; & lt; 0) /* Command bit 0 mask. */
#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */
#define TWI_SLAVE_CMD1_bm (1 & lt; & lt; 1) /* Command bit 1 mask. */
#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */


/* TWI_SLAVE.STATUS bit masks and bit positions */
#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */
#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */

#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */
#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */

#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */

#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */

#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */
#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */

#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */
#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */

#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */
#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */

#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */
#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */


/* TWI_SLAVE.ADDRMASK bit masks and bit positions */
#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */
#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */
#define TWI_SLAVE_ADDRMASK0_bm (1 & lt; & lt; 1) /* Address Mask bit 0 mask. */
#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */
#define TWI_SLAVE_ADDRMASK1_bm (1 & lt; & lt; 2) /* Address Mask bit 1 mask. */
#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */
#define TWI_SLAVE_ADDRMASK2_bm (1 & lt; & lt; 3) /* Address Mask bit 2 mask. */
#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */
#define TWI_SLAVE_ADDRMASK3_bm (1 & lt; & lt; 4) /* Address Mask bit 3 mask. */
#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */
#define TWI_SLAVE_ADDRMASK4_bm (1 & lt; & lt; 5) /* Address Mask bit 4 mask. */
#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */
#define TWI_SLAVE_ADDRMASK5_bm (1 & lt; & lt; 6) /* Address Mask bit 5 mask. */
#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */
#define TWI_SLAVE_ADDRMASK6_bm (1 & lt; & lt; 7) /* Address Mask bit 6 mask. */
#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */

#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */
#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */


/* TWI.CTRL bit masks and bit positions */
#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */
#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */

#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */
#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */


/* PORT - Port Configuration */
/* PORTCFG.VPCTRLA bit masks and bit positions */
#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */
#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */
#define PORTCFG_VP1MAP0_bm (1 & lt; & lt; 4) /* Virtual Port 1 Mapping bit 0 mask. */
#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */
#define PORTCFG_VP1MAP1_bm (1 & lt; & lt; 5) /* Virtual Port 1 Mapping bit 1 mask. */
#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */
#define PORTCFG_VP1MAP2_bm (1 & lt; & lt; 6) /* Virtual Port 1 Mapping bit 2 mask. */
#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */
#define PORTCFG_VP1MAP3_bm (1 & lt; & lt; 7) /* Virtual Port 1 Mapping bit 3 mask. */
#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */

#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */
#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */
#define PORTCFG_VP0MAP0_bm (1 & lt; & lt; 0) /* Virtual Port 0 Mapping bit 0 mask. */
#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */
#define PORTCFG_VP0MAP1_bm (1 & lt; & lt; 1) /* Virtual Port 0 Mapping bit 1 mask. */
#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */
#define PORTCFG_VP0MAP2_bm (1 & lt; & lt; 2) /* Virtual Port 0 Mapping bit 2 mask. */
#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */
#define PORTCFG_VP0MAP3_bm (1 & lt; & lt; 3) /* Virtual Port 0 Mapping bit 3 mask. */
#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */


/* PORTCFG.VPCTRLB bit masks and bit positions */
#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */
#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */
#define PORTCFG_VP3MAP0_bm (1 & lt; & lt; 4) /* Virtual Port 3 Mapping bit 0 mask. */
#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */
#define PORTCFG_VP3MAP1_bm (1 & lt; & lt; 5) /* Virtual Port 3 Mapping bit 1 mask. */
#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */
#define PORTCFG_VP3MAP2_bm (1 & lt; & lt; 6) /* Virtual Port 3 Mapping bit 2 mask. */
#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */
#define PORTCFG_VP3MAP3_bm (1 & lt; & lt; 7) /* Virtual Port 3 Mapping bit 3 mask. */
#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */

#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */
#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */
#define PORTCFG_VP2MAP0_bm (1 & lt; & lt; 0) /* Virtual Port 2 Mapping bit 0 mask. */
#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */
#define PORTCFG_VP2MAP1_bm (1 & lt; & lt; 1) /* Virtual Port 2 Mapping bit 1 mask. */
#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */
#define PORTCFG_VP2MAP2_bm (1 & lt; & lt; 2) /* Virtual Port 2 Mapping bit 2 mask. */
#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */
#define PORTCFG_VP2MAP3_bm (1 & lt; & lt; 3) /* Virtual Port 2 Mapping bit 3 mask. */
#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */


/* PORTCFG.CLKEVOUT bit masks and bit positions */
#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */
#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */
#define PORTCFG_CLKOUT0_bm (1 & lt; & lt; 0) /* Clock Output Port bit 0 mask. */
#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */
#define PORTCFG_CLKOUT1_bm (1 & lt; & lt; 1) /* Clock Output Port bit 1 mask. */
#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */

#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */
#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */
#define PORTCFG_EVOUT0_bm (1 & lt; & lt; 4) /* Event Output Port bit 0 mask. */
#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */
#define PORTCFG_EVOUT1_bm (1 & lt; & lt; 5) /* Event Output Port bit 1 mask. */
#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */


/* VPORT.INTFLAGS bit masks and bit positions */
#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */
#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */

#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */


/* PORT.INTCTRL bit masks and bit positions */
#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */
#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */
#define PORT_INT1LVL0_bm (1 & lt; & lt; 2) /* Port Interrupt 1 Level bit 0 mask. */
#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */
#define PORT_INT1LVL1_bm (1 & lt; & lt; 3) /* Port Interrupt 1 Level bit 1 mask. */
#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */

#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */
#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */
#define PORT_INT0LVL0_bm (1 & lt; & lt; 0) /* Port Interrupt 0 Level bit 0 mask. */
#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */
#define PORT_INT0LVL1_bm (1 & lt; & lt; 1) /* Port Interrupt 0 Level bit 1 mask. */
#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */


/* PORT.INTFLAGS bit masks and bit positions */
#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */
#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */

#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */


/* PORT.PIN0CTRL bit masks and bit positions */
#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */
#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */

#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */
#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */

#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */
#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */
#define PORT_OPC0_bm (1 & lt; & lt; 3) /* Output/Pull Configuration bit 0 mask. */
#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */
#define PORT_OPC1_bm (1 & lt; & lt; 4) /* Output/Pull Configuration bit 1 mask. */
#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */
#define PORT_OPC2_bm (1 & lt; & lt; 5) /* Output/Pull Configuration bit 2 mask. */
#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */

#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */
#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */
#define PORT_ISC0_bm (1 & lt; & lt; 0) /* Input/Sense Configuration bit 0 mask. */
#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */
#define PORT_ISC1_bm (1 & lt; & lt; 1) /* Input/Sense Configuration bit 1 mask. */
#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */
#define PORT_ISC2_bm (1 & lt; & lt; 2) /* Input/Sense Configuration bit 2 mask. */
#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */


/* PORT.PIN1CTRL bit masks and bit positions */
/* PORT_SRLEN_bm Predefined. */
/* PORT_SRLEN_bp Predefined. */

/* PORT_INVEN_bm Predefined. */
/* PORT_INVEN_bp Predefined. */

/* PORT_OPC_gm Predefined. */
/* PORT_OPC_gp Predefined. */
/* PORT_OPC0_bm Predefined. */
/* PORT_OPC0_bp Predefined. */
/* PORT_OPC1_bm Predefined. */
/* PORT_OPC1_bp Predefined. */
/* PORT_OPC2_bm Predefined. */
/* PORT_OPC2_bp Predefined. */

/* PORT_ISC_gm Predefined. */
/* PORT_ISC_gp Predefined. */
/* PORT_ISC0_bm Predefined. */
/* PORT_ISC0_bp Predefined. */
/* PORT_ISC1_bm Predefined. */
/* PORT_ISC1_bp Predefined. */
/* PORT_ISC2_bm Predefined. */
/* PORT_ISC2_bp Predefined. */


/* PORT.PIN2CTRL bit masks and bit positions */
/* PORT_SRLEN_bm Predefined. */
/* PORT_SRLEN_bp Predefined. */

/* PORT_INVEN_bm Predefined. */
/* PORT_INVEN_bp Predefined. */

/* PORT_OPC_gm Predefined. */
/* PORT_OPC_gp Predefined. */
/* PORT_OPC0_bm Predefined. */
/* PORT_OPC0_bp Predefined. */
/* PORT_OPC1_bm Predefined. */
/* PORT_OPC1_bp Predefined. */
/* PORT_OPC2_bm Predefined. */
/* PORT_OPC2_bp Predefined. */

/* PORT_ISC_gm Predefined. */
/* PORT_ISC_gp Predefined. */
/* PORT_ISC0_bm Predefined. */
/* PORT_ISC0_bp Predefined. */
/* PORT_ISC1_bm Predefined. */
/* PORT_ISC1_bp Predefined. */
/* PORT_ISC2_bm Predefined. */
/* PORT_ISC2_bp Predefined. */


/* PORT.PIN3CTRL bit masks and bit positions */
/* PORT_SRLEN_bm Predefined. */
/* PORT_SRLEN_bp Predefined. */

/* PORT_INVEN_bm Predefined. */
/* PORT_INVEN_bp Predefined. */

/* PORT_OPC_gm Predefined. */
/* PORT_OPC_gp Predefined. */
/* PORT_OPC0_bm Predefined. */
/* PORT_OPC0_bp Predefined. */
/* PORT_OPC1_bm Predefined. */
/* PORT_OPC1_bp Predefined. */
/* PORT_OPC2_bm Predefined. */
/* PORT_OPC2_bp Predefined. */

/* PORT_ISC_gm Predefined. */
/* PORT_ISC_gp Predefined. */
/* PORT_ISC0_bm Predefined. */
/* PORT_ISC0_bp Predefined. */
/* PORT_ISC1_bm Predefined. */
/* PORT_ISC1_bp Predefined. */
/* PORT_ISC2_bm Predefined. */
/* PORT_ISC2_bp Predefined. */


/* PORT.PIN4CTRL bit masks and bit positions */
/* PORT_SRLEN_bm Predefined. */
/* PORT_SRLEN_bp Predefined. */

/* PORT_INVEN_bm Predefined. */
/* PORT_INVEN_bp Predefined. */

/* PORT_OPC_gm Predefined. */
/* PORT_OPC_gp Predefined. */
/* PORT_OPC0_bm Predefined. */
/* PORT_OPC0_bp Predefined. */
/* PORT_OPC1_bm Predefined. */
/* PORT_OPC1_bp Predefined. */
/* PORT_OPC2_bm Predefined. */
/* PORT_OPC2_bp Predefined. */

/* PORT_ISC_gm Predefined. */
/* PORT_ISC_gp Predefined. */
/* PORT_ISC0_bm Predefined. */
/* PORT_ISC0_bp Predefined. */
/* PORT_ISC1_bm Predefined. */
/* PORT_ISC1_bp Predefined. */
/* PORT_ISC2_bm Predefined. */
/* PORT_ISC2_bp Predefined. */


/* PORT.PIN5CTRL bit masks and bit positions */
/* PORT_SRLEN_bm Predefined. */
/* PORT_SRLEN_bp Predefined. */

/* PORT_INVEN_bm Predefined. */
/* PORT_INVEN_bp Predefined. */

/* PORT_OPC_gm Predefined. */
/* PORT_OPC_gp Predefined. */
/* PORT_OPC0_bm Predefined. */
/* PORT_OPC0_bp Predefined. */
/* PORT_OPC1_bm Predefined. */
/* PORT_OPC1_bp Predefined. */
/* PORT_OPC2_bm Predefined. */
/* PORT_OPC2_bp Predefined. */

/* PORT_ISC_gm Predefined. */
/* PORT_ISC_gp Predefined. */
/* PORT_ISC0_bm Predefined. */
/* PORT_ISC0_bp Predefined. */
/* PORT_ISC1_bm Predefined. */
/* PORT_ISC1_bp Predefined. */
/* PORT_ISC2_bm Predefined. */
/* PORT_ISC2_bp Predefined. */


/* PORT.PIN6CTRL bit masks and bit positions */
/* PORT_SRLEN_bm Predefined. */
/* PORT_SRLEN_bp Predefined. */

/* PORT_INVEN_bm Predefined. */
/* PORT_INVEN_bp Predefined. */

/* PORT_OPC_gm Predefined. */
/* PORT_OPC_gp Predefined. */
/* PORT_OPC0_bm Predefined. */
/* PORT_OPC0_bp Predefined. */
/* PORT_OPC1_bm Predefined. */
/* PORT_OPC1_bp Predefined. */
/* PORT_OPC2_bm Predefined. */
/* PORT_OPC2_bp Predefined. */

/* PORT_ISC_gm Predefined. */
/* PORT_ISC_gp Predefined. */
/* PORT_ISC0_bm Predefined. */
/* PORT_ISC0_bp Predefined. */
/* PORT_ISC1_bm Predefined. */
/* PORT_ISC1_bp Predefined. */
/* PORT_ISC2_bm Predefined. */
/* PORT_ISC2_bp Predefined. */


/* PORT.PIN7CTRL bit masks and bit positions */
/* PORT_SRLEN_bm Predefined. */
/* PORT_SRLEN_bp Predefined. */

/* PORT_INVEN_bm Predefined. */
/* PORT_INVEN_bp Predefined. */

/* PORT_OPC_gm Predefined. */
/* PORT_OPC_gp Predefined. */
/* PORT_OPC0_bm Predefined. */
/* PORT_OPC0_bp Predefined. */
/* PORT_OPC1_bm Predefined. */
/* PORT_OPC1_bp Predefined. */
/* PORT_OPC2_bm Predefined. */
/* PORT_OPC2_bp Predefined. */

/* PORT_ISC_gm Predefined. */
/* PORT_ISC_gp Predefined. */
/* PORT_ISC0_bm Predefined. */
/* PORT_ISC0_bp Predefined. */
/* PORT_ISC1_bm Predefined. */
/* PORT_ISC1_bp Predefined. */
/* PORT_ISC2_bm Predefined. */
/* PORT_ISC2_bp Predefined. */


/* TC - 16-bit Timer/Counter With PWM */
/* TC0.CTRLA bit masks and bit positions */
#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */
#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */
#define TC0_CLKSEL0_bm (1 & lt; & lt; 0) /* Clock Selection bit 0 mask. */
#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
#define TC0_CLKSEL1_bm (1 & lt; & lt; 1) /* Clock Selection bit 1 mask. */
#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
#define TC0_CLKSEL2_bm (1 & lt; & lt; 2) /* Clock Selection bit 2 mask. */
#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
#define TC0_CLKSEL3_bm (1 & lt; & lt; 3) /* Clock Selection bit 3 mask. */
#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */


/* TC0.CTRLB bit masks and bit positions */
#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */
#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */

#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */
#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */

#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */
#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */

#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */
#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */

#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */
#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */
#define TC0_WGMODE0_bm (1 & lt; & lt; 0) /* Waveform generation mode bit 0 mask. */
#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */
#define TC0_WGMODE1_bm (1 & lt; & lt; 1) /* Waveform generation mode bit 1 mask. */
#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */
#define TC0_WGMODE2_bm (1 & lt; & lt; 2) /* Waveform generation mode bit 2 mask. */
#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */


/* TC0.CTRLC bit masks and bit positions */
#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */
#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */

#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */
#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */

#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */
#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */

#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */
#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */


/* TC0.CTRLD bit masks and bit positions */
#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */
#define TC0_EVACT_gp 5 /* Event Action group position. */
#define TC0_EVACT0_bm (1 & lt; & lt; 5) /* Event Action bit 0 mask. */
#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */
#define TC0_EVACT1_bm (1 & lt; & lt; 6) /* Event Action bit 1 mask. */
#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */
#define TC0_EVACT2_bm (1 & lt; & lt; 7) /* Event Action bit 2 mask. */
#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */

#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */
#define TC0_EVDLY_bp 4 /* Event Delay bit position. */

#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */
#define TC0_EVSEL_gp 0 /* Event Source Select group position. */
#define TC0_EVSEL0_bm (1 & lt; & lt; 0) /* Event Source Select bit 0 mask. */
#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
#define TC0_EVSEL1_bm (1 & lt; & lt; 1) /* Event Source Select bit 1 mask. */
#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
#define TC0_EVSEL2_bm (1 & lt; & lt; 2) /* Event Source Select bit 2 mask. */
#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
#define TC0_EVSEL3_bm (1 & lt; & lt; 3) /* Event Source Select bit 3 mask. */
#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */


/* TC0.CTRLE bit masks and bit positions */
#define TC0_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */
#define TC0_DTHM_bp 1 /* Dead Time Hold Mode bit position. */

#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */
#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */


/* TC0.INTCTRLA bit masks and bit positions */
#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */
#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */
#define TC0_ERRINTLVL0_bm (1 & lt; & lt; 2) /* Error Interrupt Level bit 0 mask. */
#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */
#define TC0_ERRINTLVL1_bm (1 & lt; & lt; 3) /* Error Interrupt Level bit 1 mask. */
#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */

#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */
#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */
#define TC0_OVFINTLVL0_bm (1 & lt; & lt; 0) /* Overflow interrupt level bit 0 mask. */
#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */
#define TC0_OVFINTLVL1_bm (1 & lt; & lt; 1) /* Overflow interrupt level bit 1 mask. */
#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */


/* TC0.INTCTRLB bit masks and bit positions */
#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */
#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */
#define TC0_CCDINTLVL0_bm (1 & lt; & lt; 6) /* Compare or Capture D Interrupt Level bit 0 mask. */
#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */
#define TC0_CCDINTLVL1_bm (1 & lt; & lt; 7) /* Compare or Capture D Interrupt Level bit 1 mask. */
#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */

#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */
#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */
#define TC0_CCCINTLVL0_bm (1 & lt; & lt; 4) /* Compare or Capture C Interrupt Level bit 0 mask. */
#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */
#define TC0_CCCINTLVL1_bm (1 & lt; & lt; 5) /* Compare or Capture C Interrupt Level bit 1 mask. */
#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */

#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */
#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */
#define TC0_CCBINTLVL0_bm (1 & lt; & lt; 2) /* Compare or Capture B Interrupt Level bit 0 mask. */
#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */
#define TC0_CCBINTLVL1_bm (1 & lt; & lt; 3) /* Compare or Capture B Interrupt Level bit 1 mask. */
#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */

#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */
#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */
#define TC0_CCAINTLVL0_bm (1 & lt; & lt; 0) /* Compare or Capture A Interrupt Level bit 0 mask. */
#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */
#define TC0_CCAINTLVL1_bm (1 & lt; & lt; 1) /* Compare or Capture A Interrupt Level bit 1 mask. */
#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */


/* TC0.CTRLFCLR bit masks and bit positions */
#define TC0_CMD_gm 0x0C /* Command group mask. */
#define TC0_CMD_gp 2 /* Command group position. */
#define TC0_CMD0_bm (1 & lt; & lt; 2) /* Command bit 0 mask. */
#define TC0_CMD0_bp 2 /* Command bit 0 position. */
#define TC0_CMD1_bm (1 & lt; & lt; 3) /* Command bit 1 mask. */
#define TC0_CMD1_bp 3 /* Command bit 1 position. */

#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */
#define TC0_LUPD_bp 1 /* Lock Update bit position. */

#define TC0_DIR_bm 0x01 /* Direction bit mask. */
#define TC0_DIR_bp 0 /* Direction bit position. */


/* TC0.CTRLFSET bit masks and bit positions */
/* TC0_CMD_gm Predefined. */
/* TC0_CMD_gp Predefined. */
/* TC0_CMD0_bm Predefined. */
/* TC0_CMD0_bp Predefined. */
/* TC0_CMD1_bm Predefined. */
/* TC0_CMD1_bp Predefined. */

/* TC0_LUPD_bm Predefined. */
/* TC0_LUPD_bp Predefined. */

/* TC0_DIR_bm Predefined. */
/* TC0_DIR_bp Predefined. */


/* TC0.CTRLGCLR bit masks and bit positions */
#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */
#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */

#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */
#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */

#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */
#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */

#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */
#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */

#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */


/* TC0.CTRLGSET bit masks and bit positions */
/* TC0_CCDBV_bm Predefined. */
/* TC0_CCDBV_bp Predefined. */

/* TC0_CCCBV_bm Predefined. */
/* TC0_CCCBV_bp Predefined. */

/* TC0_CCBBV_bm Predefined. */
/* TC0_CCBBV_bp Predefined. */

/* TC0_CCABV_bm Predefined. */
/* TC0_CCABV_bp Predefined. */

/* TC0_PERBV_bm Predefined. */
/* TC0_PERBV_bp Predefined. */


/* TC0.INTFLAGS bit masks and bit positions */
#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */
#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */

#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */
#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */

#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */
#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */

#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */
#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */

#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */

#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */


/* TC1.CTRLA bit masks and bit positions */
#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */
#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */
#define TC1_CLKSEL0_bm (1 & lt; & lt; 0) /* Clock Selection bit 0 mask. */
#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
#define TC1_CLKSEL1_bm (1 & lt; & lt; 1) /* Clock Selection bit 1 mask. */
#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
#define TC1_CLKSEL2_bm (1 & lt; & lt; 2) /* Clock Selection bit 2 mask. */
#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
#define TC1_CLKSEL3_bm (1 & lt; & lt; 3) /* Clock Selection bit 3 mask. */
#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */


/* TC1.CTRLB bit masks and bit positions */
#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */
#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */

#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */
#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */

#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */
#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */
#define TC1_WGMODE0_bm (1 & lt; & lt; 0) /* Waveform generation mode bit 0 mask. */
#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */
#define TC1_WGMODE1_bm (1 & lt; & lt; 1) /* Waveform generation mode bit 1 mask. */
#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */
#define TC1_WGMODE2_bm (1 & lt; & lt; 2) /* Waveform generation mode bit 2 mask. */
#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */


/* TC1.CTRLC bit masks and bit positions */
#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */
#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */

#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */
#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */


/* TC1.CTRLD bit masks and bit positions */
#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */
#define TC1_EVACT_gp 5 /* Event Action group position. */
#define TC1_EVACT0_bm (1 & lt; & lt; 5) /* Event Action bit 0 mask. */
#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */
#define TC1_EVACT1_bm (1 & lt; & lt; 6) /* Event Action bit 1 mask. */
#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */
#define TC1_EVACT2_bm (1 & lt; & lt; 7) /* Event Action bit 2 mask. */
#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */

#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */
#define TC1_EVDLY_bp 4 /* Event Delay bit position. */

#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */
#define TC1_EVSEL_gp 0 /* Event Source Select group position. */
#define TC1_EVSEL0_bm (1 & lt; & lt; 0) /* Event Source Select bit 0 mask. */
#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
#define TC1_EVSEL1_bm (1 & lt; & lt; 1) /* Event Source Select bit 1 mask. */
#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
#define TC1_EVSEL2_bm (1 & lt; & lt; 2) /* Event Source Select bit 2 mask. */
#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
#define TC1_EVSEL3_bm (1 & lt; & lt; 3) /* Event Source Select bit 3 mask. */
#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */


/* TC1.CTRLE bit masks and bit positions */
#define TC1_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */
#define TC1_DTHM_bp 1 /* Dead Time Hold Mode bit position. */

#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */
#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */


/* TC1.INTCTRLA bit masks and bit positions */
#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */
#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */
#define TC1_ERRINTLVL0_bm (1 & lt; & lt; 2) /* Error Interrupt Level bit 0 mask. */
#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */
#define TC1_ERRINTLVL1_bm (1 & lt; & lt; 3) /* Error Interrupt Level bit 1 mask. */
#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */

#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */
#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */
#define TC1_OVFINTLVL0_bm (1 & lt; & lt; 0) /* Overflow interrupt level bit 0 mask. */
#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */
#define TC1_OVFINTLVL1_bm (1 & lt; & lt; 1) /* Overflow interrupt level bit 1 mask. */
#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */


/* TC1.INTCTRLB bit masks and bit positions */
#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */
#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */
#define TC1_CCBINTLVL0_bm (1 & lt; & lt; 2) /* Compare or Capture B Interrupt Level bit 0 mask. */
#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */
#define TC1_CCBINTLVL1_bm (1 & lt; & lt; 3) /* Compare or Capture B Interrupt Level bit 1 mask. */
#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */

#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */
#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */
#define TC1_CCAINTLVL0_bm (1 & lt; & lt; 0) /* Compare or Capture A Interrupt Level bit 0 mask. */
#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */
#define TC1_CCAINTLVL1_bm (1 & lt; & lt; 1) /* Compare or Capture A Interrupt Level bit 1 mask. */
#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */


/* TC1.CTRLFCLR bit masks and bit positions */
#define TC1_CMD_gm 0x0C /* Command group mask. */
#define TC1_CMD_gp 2 /* Command group position. */
#define TC1_CMD0_bm (1 & lt; & lt; 2) /* Command bit 0 mask. */
#define TC1_CMD0_bp 2 /* Command bit 0 position. */
#define TC1_CMD1_bm (1 & lt; & lt; 3) /* Command bit 1 mask. */
#define TC1_CMD1_bp 3 /* Command bit 1 position. */

#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */
#define TC1_LUPD_bp 1 /* Lock Update bit position. */

#define TC1_DIR_bm 0x01 /* Direction bit mask. */
#define TC1_DIR_bp 0 /* Direction bit position. */


/* TC1.CTRLFSET bit masks and bit positions */
/* TC1_CMD_gm Predefined. */
/* TC1_CMD_gp Predefined. */
/* TC1_CMD0_bm Predefined. */
/* TC1_CMD0_bp Predefined. */
/* TC1_CMD1_bm Predefined. */
/* TC1_CMD1_bp Predefined. */

/* TC1_LUPD_bm Predefined. */
/* TC1_LUPD_bp Predefined. */

/* TC1_DIR_bm Predefined. */
/* TC1_DIR_bp Predefined. */


/* TC1.CTRLGCLR bit masks and bit positions */
#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */
#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */

#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */
#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */

#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */


/* TC1.CTRLGSET bit masks and bit positions */
/* TC1_CCBBV_bm Predefined. */
/* TC1_CCBBV_bp Predefined. */

/* TC1_CCABV_bm Predefined. */
/* TC1_CCABV_bp Predefined. */

/* TC1_PERBV_bm Predefined. */
/* TC1_PERBV_bp Predefined. */


/* TC1.INTFLAGS bit masks and bit positions */
#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */
#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */

#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */
#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */

#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */

#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */


/* AWEX.CTRL bit masks and bit positions */
#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */
#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */

#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */
#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */

#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */
#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */

#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */
#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */

#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */
#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */

#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */
#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */


/* AWEX.FDCTRL bit masks and bit positions */
#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */
#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */

#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */
#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */

#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */
#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */
#define AWEX_FDACT0_bm (1 & lt; & lt; 0) /* Fault Detect Action bit 0 mask. */
#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */
#define AWEX_FDACT1_bm (1 & lt; & lt; 1) /* Fault Detect Action bit 1 mask. */
#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */


/* AWEX.STATUS bit masks and bit positions */
#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */
#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */

#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */
#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */

#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */
#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */


/* HIRES.CTRL bit masks and bit positions */
#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */
#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */
#define HIRES_HREN0_bm (1 & lt; & lt; 0) /* High Resolution Enable bit 0 mask. */
#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */
#define HIRES_HREN1_bm (1 & lt; & lt; 1) /* High Resolution Enable bit 1 mask. */
#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */


/* USART - Universal Asynchronous Receiver-Transmitter */
/* USART.STATUS bit masks and bit positions */
#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */
#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */

#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */
#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */

#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */
#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */

#define USART_FERR_bm 0x10 /* Frame Error bit mask. */
#define USART_FERR_bp 4 /* Frame Error bit position. */

#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */
#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */

#define USART_PERR_bm 0x04 /* Parity Error bit mask. */
#define USART_PERR_bp 2 /* Parity Error bit position. */

#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */
#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */


/* USART.CTRLA bit masks and bit positions */
#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */
#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */
#define USART_RXCINTLVL0_bm (1 & lt; & lt; 4) /* Receive Interrupt Level bit 0 mask. */
#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */
#define USART_RXCINTLVL1_bm (1 & lt; & lt; 5) /* Receive Interrupt Level bit 1 mask. */
#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */

#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */
#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */
#define USART_TXCINTLVL0_bm (1 & lt; & lt; 2) /* Transmit Interrupt Level bit 0 mask. */
#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */
#define USART_TXCINTLVL1_bm (1 & lt; & lt; 3) /* Transmit Interrupt Level bit 1 mask. */
#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */

#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */
#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */
#define USART_DREINTLVL0_bm (1 & lt; & lt; 0) /* Data Register Empty Interrupt Level bit 0 mask. */
#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */
#define USART_DREINTLVL1_bm (1 & lt; & lt; 1) /* Data Register Empty Interrupt Level bit 1 mask. */
#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */


/* USART.CTRLB bit masks and bit positions */
#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */
#define USART_RXEN_bp 4 /* Receiver Enable bit position. */

#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */
#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */

#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */
#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */

#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */
#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */

#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */
#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */


/* USART.CTRLC bit masks and bit positions */
#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */
#define USART_CMODE_gp 6 /* Communication Mode group position. */
#define USART_CMODE0_bm (1 & lt; & lt; 6) /* Communication Mode bit 0 mask. */
#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */
#define USART_CMODE1_bm (1 & lt; & lt; 7) /* Communication Mode bit 1 mask. */
#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */

#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */
#define USART_PMODE_gp 4 /* Parity Mode group position. */
#define USART_PMODE0_bm (1 & lt; & lt; 4) /* Parity Mode bit 0 mask. */
#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */
#define USART_PMODE1_bm (1 & lt; & lt; 5) /* Parity Mode bit 1 mask. */
#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */

#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */
#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */

#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */
#define USART_CHSIZE_gp 0 /* Character Size group position. */
#define USART_CHSIZE0_bm (1 & lt; & lt; 0) /* Character Size bit 0 mask. */
#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */
#define USART_CHSIZE1_bm (1 & lt; & lt; 1) /* Character Size bit 1 mask. */
#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */
#define USART_CHSIZE2_bm (1 & lt; & lt; 2) /* Character Size bit 2 mask. */
#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */


/* USART.BAUDCTRLA bit masks and bit positions */
#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */
#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */
#define USART_BSEL0_bm (1 & lt; & lt; 0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */
#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */
#define USART_BSEL1_bm (1 & lt; & lt; 1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */
#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */
#define USART_BSEL2_bm (1 & lt; & lt; 2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */
#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */
#define USART_BSEL3_bm (1 & lt; & lt; 3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */
#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */
#define USART_BSEL4_bm (1 & lt; & lt; 4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */
#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */
#define USART_BSEL5_bm (1 & lt; & lt; 5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */
#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */
#define USART_BSEL6_bm (1 & lt; & lt; 6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */
#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */
#define USART_BSEL7_bm (1 & lt; & lt; 7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */
#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */


/* USART.BAUDCTRLB bit masks and bit positions */
#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */
#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */
#define USART_BSCALE0_bm (1 & lt; & lt; 4) /* Baud Rate Scale bit 0 mask. */
#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */
#define USART_BSCALE1_bm (1 & lt; & lt; 5) /* Baud Rate Scale bit 1 mask. */
#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */
#define USART_BSCALE2_bm (1 & lt; & lt; 6) /* Baud Rate Scale bit 2 mask. */
#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */
#define USART_BSCALE3_bm (1 & lt; & lt; 7) /* Baud Rate Scale bit 3 mask. */
#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */

/* USART_BSEL_gm Predefined. */
/* USART_BSEL_gp Predefined. */
/* USART_BSEL0_bm Predefined. */
/* USART_BSEL0_bp Predefined. */
/* USART_BSEL1_bm Predefined. */
/* USART_BSEL1_bp Predefined. */
/* USART_BSEL2_bm Predefined. */
/* USART_BSEL2_bp Predefined. */
/* USART_BSEL3_bm Predefined. */
/* USART_BSEL3_bp Predefined. */


/* SPI - Serial Peripheral Interface */
/* SPI.CTRL bit masks and bit positions */
#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */
#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */

#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */
#define SPI_ENABLE_bp 6 /* Enable Module bit position. */

#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */
#define SPI_DORD_bp 5 /* Data Order Setting bit position. */

#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */
#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */

#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */
#define SPI_MODE_gp 2 /* SPI Mode group position. */
#define SPI_MODE0_bm (1 & lt; & lt; 2) /* SPI Mode bit 0 mask. */
#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */
#define SPI_MODE1_bm (1 & lt; & lt; 3) /* SPI Mode bit 1 mask. */
#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */

#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */
#define SPI_PRESCALER_gp 0 /* Prescaler group position. */
#define SPI_PRESCALER0_bm (1 & lt; & lt; 0) /* Prescaler bit 0 mask. */
#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */
#define SPI_PRESCALER1_bm (1 & lt; & lt; 1) /* Prescaler bit 1 mask. */
#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */


/* SPI.INTCTRL bit masks and bit positions */
#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */
#define SPI_INTLVL_gp 0 /* Interrupt level group position. */
#define SPI_INTLVL0_bm (1 & lt; & lt; 0) /* Interrupt level bit 0 mask. */
#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */
#define SPI_INTLVL1_bm (1 & lt; & lt; 1) /* Interrupt level bit 1 mask. */
#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */


/* SPI.STATUS bit masks and bit positions */
#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */
#define SPI_IF_bp 7 /* Interrupt Flag bit position. */

#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */
#define SPI_WRCOL_bp 6 /* Write Collision bit position. */


/* IRCOM - IR Communication Module */
/* IRCOM.CTRL bit masks and bit positions */
#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */
#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */
#define IRCOM_EVSEL0_bm (1 & lt; & lt; 0) /* Event Channel Select bit 0 mask. */
#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */
#define IRCOM_EVSEL1_bm (1 & lt; & lt; 1) /* Event Channel Select bit 1 mask. */
#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */
#define IRCOM_EVSEL2_bm (1 & lt; & lt; 2) /* Event Channel Select bit 2 mask. */
#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */
#define IRCOM_EVSEL3_bm (1 & lt; & lt; 3) /* Event Channel Select bit 3 mask. */
#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */


/* AES - AES Module */
/* AES.CTRL bit masks and bit positions */
#define AES_START_bm 0x80 /* Start/Run bit mask. */
#define AES_START_bp 7 /* Start/Run bit position. */

#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */
#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */

#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */
#define AES_RESET_bp 5 /* AES Software Reset bit position. */

#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */
#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */

#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */
#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */


/* AES.STATUS bit masks and bit positions */
#define AES_ERROR_bm 0x80 /* AES Error bit mask. */
#define AES_ERROR_bp 7 /* AES Error bit position. */

#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */
#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */


/* AES.INTCTRL bit masks and bit positions */
#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */
#define AES_INTLVL_gp 0 /* Interrupt level group position. */
#define AES_INTLVL0_bm (1 & lt; & lt; 0) /* Interrupt level bit 0 mask. */
#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */
#define AES_INTLVL1_bm (1 & lt; & lt; 1) /* Interrupt level bit 1 mask. */
#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */



// Generic Port Pins

#define PIN0_bm 0x01
#define PIN0_bp 0
#define PIN1_bm 0x02
#define PIN1_bp 1
#define PIN2_bm 0x04
#define PIN2_bp 2
#define PIN3_bm 0x08
#define PIN3_bp 3
#define PIN4_bm 0x10
#define PIN4_bp 4
#define PIN5_bm 0x20
#define PIN5_bp 5
#define PIN6_bm 0x40
#define PIN6_bp 6
#define PIN7_bm 0x80
#define PIN7_bp 7


/* ========== Interrupt Vector Definitions ========== */
/* Vector 0 is the reset vector */

/* OSC interrupt vectors */
#define OSC_XOSCF_vect_num 1
#define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */

/* PORTC interrupt vectors */
#define PORTC_INT0_vect_num 2
#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */
#define PORTC_INT1_vect_num 3
#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */

/* PORTR interrupt vectors */
#define PORTR_INT0_vect_num 4
#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */
#define PORTR_INT1_vect_num 5
#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */

/* DMA interrupt vectors */
#define DMA_CH0_vect_num 6
#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */
#define DMA_CH1_vect_num 7
#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */
#define DMA_CH2_vect_num 8
#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */
#define DMA_CH3_vect_num 9
#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */

/* RTC interrupt vectors */
#define RTC_OVF_vect_num 10
#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */
#define RTC_COMP_vect_num 11
#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */

/* TWIC interrupt vectors */
#define TWIC_TWIS_vect_num 12
#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */
#define TWIC_TWIM_vect_num 13
#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */

/* TCC0 interrupt vectors */
#define TCC0_OVF_vect_num 14
#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */
#define TCC0_ERR_vect_num 15
#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */
#define TCC0_CCA_vect_num 16
#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */
#define TCC0_CCB_vect_num 17
#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */
#define TCC0_CCC_vect_num 18
#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */
#define TCC0_CCD_vect_num 19
#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */

/* TCC1 interrupt vectors */
#define TCC1_OVF_vect_num 20
#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */
#define TCC1_ERR_vect_num 21
#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */
#define TCC1_CCA_vect_num 22
#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */
#define TCC1_CCB_vect_num 23
#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */

/* SPIC interrupt vectors */
#define SPIC_INT_vect_num 24
#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */

/* USARTC0 interrupt vectors */
#define USARTC0_RXC_vect_num 25
#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */
#define USARTC0_DRE_vect_num 26
#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */
#define USARTC0_TXC_vect_num 27
#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */

/* USARTC1 interrupt vectors */
#define USARTC1_RXC_vect_num 28
#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */
#define USARTC1_DRE_vect_num 29
#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */
#define USARTC1_TXC_vect_num 30
#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */

/* AES interrupt vectors */
#define AES_INT_vect_num 31
#define AES_INT_vect _VECTOR(31) /* AES Interrupt */

/* NVM interrupt vectors */
#define NVM_EE_vect_num 32
#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */
#define NVM_SPM_vect_num 33
#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */

/* PORTB interrupt vectors */
#define PORTB_INT0_vect_num 34
#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */
#define PORTB_INT1_vect_num 35
#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */

/* ACB interrupt vectors */
#define ACB_AC0_vect_num 36
#define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */
#define ACB_AC1_vect_num 37
#define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */
#define ACB_ACW_vect_num 38
#define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */

/* ADCB interrupt vectors */
#define ADCB_CH0_vect_num 39
#define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */
#define ADCB_CH1_vect_num 40
#define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */
#define ADCB_CH2_vect_num 41
#define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */
#define ADCB_CH3_vect_num 42
#define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */

/* PORTE interrupt vectors */
#define PORTE_INT0_vect_num 43
#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */
#define PORTE_INT1_vect_num 44
#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */

/* TWIE interrupt vectors */
#define TWIE_TWIS_vect_num 45
#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */
#define TWIE_TWIM_vect_num 46
#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */

/* TCE0 interrupt vectors */
#define TCE0_OVF_vect_num 47
#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */
#define TCE0_ERR_vect_num 48
#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */
#define TCE0_CCA_vect_num 49
#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */
#define TCE0_CCB_vect_num 50
#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */
#define TCE0_CCC_vect_num 51
#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */
#define TCE0_CCD_vect_num 52
#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */

/* TCE1 interrupt vectors */
#define TCE1_OVF_vect_num 53
#define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */
#define TCE1_ERR_vect_num 54
#define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */
#define TCE1_CCA_vect_num 55
#define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */
#define TCE1_CCB_vect_num 56
#define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */

/* SPIE interrupt vectors */
#define SPIE_INT_vect_num 57
#define SPIE_INT_vect _VECTOR(57) /* SPI Interrupt */

/* USARTE0 interrupt vectors */
#define USARTE0_RXC_vect_num 58
#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */
#define USARTE0_DRE_vect_num 59
#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */
#define USARTE0_TXC_vect_num 60
#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */

/* USARTE1 interrupt vectors */
#define USARTE1_RXC_vect_num 61
#define USARTE1_RXC_vect _VECTOR(61) /* Reception Complete Interrupt */
#define USARTE1_DRE_vect_num 62
#define USARTE1_DRE_vect _VECTOR(62) /* Data Register Empty Interrupt */
#define USARTE1_TXC_vect_num 63
#define USARTE1_TXC_vect _VECTOR(63) /* Transmission Complete Interrupt */

/* PORTD interrupt vectors */
#define PORTD_INT0_vect_num 64
#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */
#define PORTD_INT1_vect_num 65
#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */

/* PORTA interrupt vectors */
#define PORTA_INT0_vect_num 66
#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */
#define PORTA_INT1_vect_num 67
#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */

/* ACA interrupt vectors */
#define ACA_AC0_vect_num 68
#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */
#define ACA_AC1_vect_num 69
#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */
#define ACA_ACW_vect_num 70
#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */

/* ADCA interrupt vectors */
#define ADCA_CH0_vect_num 71
#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */
#define ADCA_CH1_vect_num 72
#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */
#define ADCA_CH2_vect_num 73
#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */
#define ADCA_CH3_vect_num 74
#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */

/* TWID interrupt vectors */
#define TWID_TWIS_vect_num 75
#define TWID_TWIS_vect _VECTOR(75) /* TWI Slave Interrupt */
#define TWID_TWIM_vect_num 76
#define TWID_TWIM_vect _VECTOR(76) /* TWI Master Interrupt */

/* TCD0 interrupt vectors */
#define TCD0_OVF_vect_num 77
#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */
#define TCD0_ERR_vect_num 78
#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */
#define TCD0_CCA_vect_num 79
#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */
#define TCD0_CCB_vect_num 80
#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */
#define TCD0_CCC_vect_num 81
#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */
#define TCD0_CCD_vect_num 82
#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */

/* TCD1 interrupt vectors */
#define TCD1_OVF_vect_num 83
#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */
#define TCD1_ERR_vect_num 84
#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */
#define TCD1_CCA_vect_num 85
#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */
#define TCD1_CCB_vect_num 86
#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */

/* SPID interrupt vectors */
#define SPID_INT_vect_num 87
#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */

/* USARTD0 interrupt vectors */
#define USARTD0_RXC_vect_num 88
#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */
#define USARTD0_DRE_vect_num 89
#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */
#define USARTD0_TXC_vect_num 90
#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */

/* USARTD1 interrupt vectors */
#define USARTD1_RXC_vect_num 91
#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */
#define USARTD1_DRE_vect_num 92
#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */
#define USARTD1_TXC_vect_num 93
#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */

/* PORTQ interrupt vectors */
#define PORTQ_INT0_vect_num 94
#define PORTQ_INT0_vect _VECTOR(94) /* External Interrupt 0 */
#define PORTQ_INT1_vect_num 95
#define PORTQ_INT1_vect _VECTOR(95) /* External Interrupt 1 */

/* PORTH interrupt vectors */
#define PORTH_INT0_vect_num 96
#define PORTH_INT0_vect _VECTOR(96) /* External Interrupt 0 */
#define PORTH_INT1_vect_num 97
#define PORTH_INT1_vect _VECTOR(97) /* External Interrupt 1 */

/* PORTJ interrupt vectors */
#define PORTJ_INT0_vect_num 98
#define PORTJ_INT0_vect _VECTOR(98) /* External Interrupt 0 */
#define PORTJ_INT1_vect_num 99
#define PORTJ_INT1_vect _VECTOR(99) /* External Interrupt 1 */

/* PORTK interrupt vectors */
#define PORTK_INT0_vect_num 100
#define PORTK_INT0_vect _VECTOR(100) /* External Interrupt 0 */
#define PORTK_INT1_vect_num 101
#define PORTK_INT1_vect _VECTOR(101) /* External Interrupt 1 */

/* PORTF interrupt vectors */
#define PORTF_INT0_vect_num 104
#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */
#define PORTF_INT1_vect_num 105
#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */

/* TWIF interrupt vectors */
#define TWIF_TWIS_vect_num 106
#define TWIF_TWIS_vect _VECTOR(106) /* TWI Slave Interrupt */
#define TWIF_TWIM_vect_num 107
#define TWIF_TWIM_vect _VECTOR(107) /* TWI Master Interrupt */

/* TCF0 interrupt vectors */
#define TCF0_OVF_vect_num 108
#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */
#define TCF0_ERR_vect_num 109
#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */
#define TCF0_CCA_vect_num 110
#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */
#define TCF0_CCB_vect_num 111
#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */
#define TCF0_CCC_vect_num 112
#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */
#define TCF0_CCD_vect_num 113
#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */

/* TCF1 interrupt vectors */
#define TCF1_OVF_vect_num 114
#define TCF1_OVF_vect _VECTOR(114) /* Overflow Interrupt */
#define TCF1_ERR_vect_num 115
#define TCF1_ERR_vect _VECTOR(115) /* Error Interrupt */
#define TCF1_CCA_vect_num 116
#define TCF1_CCA_vect _VECTOR(116) /* Compare or Capture A Interrupt */
#define TCF1_CCB_vect_num 117
#define TCF1_CCB_vect _VECTOR(117) /* Compare or Capture B Interrupt */

/* SPIF interrupt vectors */
#define SPIF_INT_vect_num 118
#define SPIF_INT_vect _VECTOR(118) /* SPI Interrupt */

/* USARTF0 interrupt vectors */
#define USARTF0_RXC_vect_num 119
#define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */
#define USARTF0_DRE_vect_num 120
#define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */
#define USARTF0_TXC_vect_num 121
#define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */

/* USARTF1 interrupt vectors */
#define USARTF1_RXC_vect_num 122
#define USARTF1_RXC_vect _VECTOR(122) /* Reception Complete Interrupt */
#define USARTF1_DRE_vect_num 123
#define USARTF1_DRE_vect _VECTOR(123) /* Data Register Empty Interrupt */
#define USARTF1_TXC_vect_num 124
#define USARTF1_TXC_vect _VECTOR(124) /* Transmission Complete Interrupt */


#define _VECTOR_SIZE 4 /* Size of individual vector. */
#define _VECTORS_SIZE (125 * _VECTOR_SIZE)


/* ========== Constants ========== */

#define PROGMEM_START (0x0000)
#define PROGMEM_SIZE (139264)
#define PROGMEM_PAGE_SIZE (512)
#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1)

#define APP_SECTION_START (0x0000)
#define APP_SECTION_SIZE (131072)
#define APP_SECTION_PAGE_SIZE (512)
#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1)

#define APPTABLE_SECTION_START (0x1E000)
#define APPTABLE_SECTION_SIZE (8192)
#define APPTABLE_SECTION_PAGE_SIZE (512)
#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1)

#define BOOT_SECTION_START (0x20000)
#define BOOT_SECTION_SIZE (8192)
#define BOOT_SECTION_PAGE_SIZE (512)
#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1)

#define DATAMEM_START (0x0000)
#define DATAMEM_SIZE (16777216)
#define DATAMEM_PAGE_SIZE (0)
#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1)

#define IO_START (0x0000)
#define IO_SIZE (4096)
#define IO_PAGE_SIZE (0)
#define IO_END (IO_START + IO_SIZE - 1)

#define MAPPED_EEPROM_START (0x1000)
#define MAPPED_EEPROM_SIZE (2048)
#define MAPPED_EEPROM_PAGE_SIZE (0)
#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1)

#define INTERNAL_SRAM_START (0x2000)
#define INTERNAL_SRAM_SIZE (8192)
#define INTERNAL_SRAM_PAGE_SIZE (0)
#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1)

#define EXTERNAL_SRAM_START (0x4000)
#define EXTERNAL_SRAM_SIZE (16760832)
#define EXTERNAL_SRAM_PAGE_SIZE (0)
#define EXTERNAL_SRAM_END (EXTERNAL_SRAM_START + EXTERNAL_SRAM_SIZE - 1)

#define EEPROM_START (0x0000)
#define EEPROM_SIZE (2048)
#define EEPROM_PAGE_SIZE (32)
#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1)

#define FUSE_START (0x0000)
#define FUSE_SIZE (6)
#define FUSE_PAGE_SIZE (0)
#define FUSE_END (FUSE_START + FUSE_SIZE - 1)

#define LOCKBIT_START (0x0000)
#define LOCKBIT_SIZE (1)
#define LOCKBIT_PAGE_SIZE (0)
#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1)

#define SIGNATURES_START (0x0000)
#define SIGNATURES_SIZE (3)
#define SIGNATURES_PAGE_SIZE (0)
#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1)

#define USER_SIGNATURES_START (0x0000)
#define USER_SIGNATURES_SIZE (512)
#define USER_SIGNATURES_PAGE_SIZE (0)
#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1)

#define PROD_SIGNATURES_START (0x0000)
#define PROD_SIGNATURES_SIZE (52)
#define PROD_SIGNATURES_PAGE_SIZE (0)
#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1)

#define FLASHEND PROGMEM_END
#define SPM_PAGESIZE PROGMEM_PAGE_SIZE
#define RAMSTART INTERNAL_SRAM_START
#define RAMSIZE INTERNAL_SRAM_SIZE
#define RAMEND INTERNAL_SRAM_END
#define XRAMSTART EXTERNAL_SRAM_START
#define XRAMSIZE EXTERNAL_SRAM_SIZE
#define XRAMEND EXTERNAL_SRAM_END
#define E2END EEPROM_END
#define E2PAGESIZE EEPROM_PAGE_SIZE


/* ========== Fuses ========== */
#define FUSE_MEMORY_SIZE 6

/* Fuse Byte 0 */
#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */
#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */
#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */
#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */
#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */
#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */
#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */
#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */
#define FUSE0_DEFAULT (0xFF)

/* Fuse Byte 1 */
#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */
#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */
#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */
#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */
#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */
#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */
#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */
#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */
#define FUSE1_DEFAULT (0xFF)

/* Fuse Byte 2 */
#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */
#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */
#define FUSE_BODACT0 (unsigned char)~_BV(2) /* BOD Operation in Active Mode Bit 0 */
#define FUSE_BODACT1 (unsigned char)~_BV(3) /* BOD Operation in Active Mode Bit 1 */
#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */
#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */
#define FUSE2_DEFAULT (0xFF)

/* Fuse Byte 3 Reserved */

/* Fuse Byte 4 */
#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */
#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */
#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */
#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */
#define FUSE4_DEFAULT (0xFF)

/* Fuse Byte 5 */
#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */
#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */
#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */
#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */
#define FUSE5_DEFAULT (0xFF)


/* ========== Lock Bits ========== */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST
#define __BOOT_LOCK_APPLICATION_BITS_EXIST
#define __BOOT_LOCK_BOOT_BITS_EXIST


/* ========== Signature ========== */
#define SIGNATURE_0 0x1E
#define SIGNATURE_1 0x97
#define SIGNATURE_2 0x4C


#endif /* _AVR_ATxmega128A1_H_ */


xMega_official_drivers_and_examples.rar > documentation.h

/* Doxygen documentation mainpage ********************************************/
/*! \mainpage
* \section intro Introduction
* This documents the firmware for the application note. \n
*
* \section compinfo Compilation Info
* This firmware was compiled with IAR Embedded Workbench 5.10 and WinAVR 20080411.\n
*
* To make the project in IAR EWAVR:\n
* Add the .c files (and .S90 files where applicable) for the given example to your
* project. Use device ATxmega128A1 and enable bit definitions in I/O include files,
* optimization low for debug target and high for release, output format: ubrof8 for
* Debug and intel_extended for Release, select Normal DLIB as library. \n
*
* To make the project in WinAVR:\n
* Add the .c files (and .S files where applicable) for the given example to your project.
* Use device ATxmega128A1, optimization low for debug target and high for release. \n
*
* \section deviceinfo Device Info
* All XMEGA devices with the targeted module can be used. The example is
* written for ATxmega128A1.
*
* \section contactinfo Contact Info
* For more info about Atmel AVR visit http://www.atmel.com/products/AVR/ \n
* For application notes visit
* http://www.atmel.com/dyn/products/app_notes.asp?family_id=607 \n
* Support mail: avr@atmel.com \n
*
* $Revision: 1251 $
* $Date: 2008-02-18 15:33:18 +0100 (ma, 18 feb 2008) $
*
* Copyright (c) 2008, Atmel Corporation All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of ATMEL may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL " AS IS " AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
* SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*****************************************************************************/


xMega_official_drivers_and_examples.rar > port_driver.h

/* This file has been prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief
* XMEGA I/O Port driver header file.
*
* This file contains the function prototypes and enumerator definitions
* for various configuration parameters for the XMEGA I/O Port driver.
*
* This driver is intended for rapid prototyping and documentation
* purposes for getting started with the XMEGA I/O Ports. The driver is not
* optimized for speed or size. However, functions that are just a few
* lines of code are written as macros to eliminate function call overhead.
* When using these macros it is important to use the correct data type for
* the arguments, as this is not checked by the compiler.
*
* \par Application note:
* AVR1313: Using the XMEGA I/O Pins and External Interrupts
*
* \par Documentation
* For comprehensive code documentation, supported compilers, compiler
* settings and supported devices see readme.html
*
* \author
* Atmel Corporation: http://www.atmel.com \n
* Support email: avr@atmel.com
*
* $Revision: 1569 $
* $Date: 2008-04-22 13:03:43 +0200 (ti, 22 apr 2008) $ \n
*
* Copyright (c) 2008, Atmel Corporation All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of ATMEL may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL " AS IS " AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
* SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*****************************************************************************/

#ifndef PORT_DRIVER_H
#define PORT_DRIVER_H

#include " avr_compiler.h "

/* Definitions of macros. */

/*! \brief This macro sets the data direction for all I/O pins in the port or
* the virtual port.
*
* /note This macro can also be used to access virtual ports.
*
* \param _port Pointer to the PORT_t or VPORT_t instance.
* \param _directionMask The direction setting mask. The direction for pin n in
* the port is controlled by bit n. A 0 means input. A 1
* means output.
*/
#define PORT_SetDirection( _port, _directionMask) ( (_port)- & gt; DIR = _directionMask )



/*! \brief Sets the data direction of a set of pins to output
*
* This macro sets the data direction of the selected port pins to output
* without altering the data direction of the other pins in that port.
*
* \param _port Pointer to the PORT_t instance.
* \param _outputMask A bit mask of the pins to set as output. A one in bit
* location n will configure pin n as output.
*/
#define PORT_SetPinsAsOutput( _port, _outputMask ) ( (_port)- & gt; DIRSET = _outputMask )



/*! \brief Sets the data direction of a set of pins to input
*
* This macro sets the data direction of the selected port pins to input
* without altering the data direction of the other pins in that port.
*
* \param _port Pointer to the PORT_t instance.
* \param _inputMask A bit mask of the pins to set as input. A one in bit
* location n will configure pin n as input.
*/
#define PORT_SetPinsAsInput( _port, _inputMask) ( (_port)- & gt; DIRCLR = _inputMask )



/*! \brief Toggle the data direction of a set of pins
*
* This macro toggles the data direction of the selected port pins
* without altering the data direction of the other pins in that port.
*
* \param _port Pointer to the PORT_t instance.
* \param _toggleMask A bit mask of the pins on which to toggle input direction.
*/
#define PORT_ToggleDirection( _port, _toggleMask) ( (_port)- & gt; DIRTGL = _toggleMask )



/*! \brief This macro sets the output value/logic level of all pins in the
* I/O port or virtual port.
*
* /note This macro can also be used to access virtual ports.
*
* \param _port Pointer to the PORT_t or VPORT_t instance.
* \param _outValue The output value. Bit n in this parameter corresponds to
* pin n of the port.
*/
#define PORT_SetOutputValue( _port, _outValue) ( (_port)- & gt; OUT = _outValue )



/*! \brief Set the output value of a set of I/O pins to logic high.
*
* This macro sets the output value of a set of I/O pins to logic high.
* (Unless inverted I/O has been enabled for the pins) It does not alter the
* pins not specified in the bit mask.
*
* \param _port Pointer to the PORT_t instance.
* \param _setMask The bit mask of pins to set to logic high level.
*/
#define PORT_SetPins( _port, _setMask) ( (_port)- & gt; OUTSET = _setMask )



/*! \brief Set the output value of a set of I/O pins to logic low.
*
* This macro sets the output value of a set of I/O pins to logic low.
* (Unless inverted I/O has been enabled for the pins) It does not alter the
* pins not specified in the bit mask.
*
* \param _port Pointer to the PORT_t instance.
* \param _clearMask The bit mask of pins to set to logic low level.
*/
#define PORT_ClearPins( _port, _clearMask) ( (_port)- & gt; OUTCLR = _clearMask )



/*! \brief Toggle the output value of a set of I/O pins.
*
* This macro toggles the output value of a set of I/O pins. It does not
* alter the output value of pins not specified in the bit mask.
*
* \param _port Pointer to the PORT_t instance.
* \param _toggleMask The bit mask of pins to toggle.
*/
#define PORT_TogglePins( _port, _toggleMask ) ( (_port)- & gt; OUTTGL = _toggleMask )



/*! \brief This macro returns the current logic value of the port or virtual
* port.
*
* /note This macro can also be used to access virtual ports.
*
* \param _port Pointer to the PORT_t or VPORT_t instance.
* \return The current logic state of the port.
*/
#define PORT_GetPortValue( _port ) ( (_port)- & gt; IN )



/*! \brief This macro returns the current state of the interrupt flags, given by
* a bit mask, for an I/O port or a virtual port.
*
* /note This macro can also be used to access virtual ports.
*
* \param _port Pointer to the PORT_t or VPORT_t instance.
* \param _bitMask Bit mask for interrupt flags to read.
* \return The state of the interrupt flags.
*/
#define PORT_GetInterruptFlags( _port, _bitMask ) ( (_port)- & gt; INTFLAGS & _bitMask )



/*! \brief This macro clears interrupt flags, given by a bit mask, for an I/O
* port or a virtual port.
*
* /note This macro can be used for both I/O ports and virtual ports.
*
* \param _port Pointer to the PORT_t or VPORT_t instance.
* \param _bitMask Bit mask for interrupt flags to clear.
*/
#define PORT_ClearInterruptFlags( _port, _bitMask ) ( (_port)- & gt; INTFLAGS = _bitMask )



/*! \brief This macro sets a bit in the OUT register of an I/O port or virtual
* port.
*
* \note This macro is especially efficient with virtual ports, since only
* one SBI instruction is invoked.
*
* \param _port Pointer to the PORT_t or VPORT_t instance.
* \param _bitPosition Position of bit to set.
*/
#define PORT_SetOutputBit( _port, _bitPosition ) ( (_port)- & gt; OUT = (_port)- & gt; OUT | (1 & lt; & lt; _bitPosition) )



/*! \brief This macro clears a bit in the OUT register of an I/O port or virtual
* port.
*
* \note This macro is especially efficient with virtual ports, since only
* one CBI instruction is invoked.
*
* \param _port Pointer to the PORT_t or VPORT_t instance.
* \param _bitPosition Position of bit to cleared.
*/
#define PORT_ClearOutputBit( _port, _bitPosition ) ( (_port)- & gt; OUT = (_port)- & gt; OUT & ~(1 & lt; & lt; _bitPosition) )



/*! \brief This macro configures a pin in an I/O port or virtual port as an
* output.
*
* \note This macro is especially efficient with virtual ports, since only
* one SBI instruction is invoked.
*
* \param _port Pointer to the PORT_t or VPORT_t instance.
* \param _bitPosition Position of bit to set as output.
*/
#define PORT_SetPinAsOutput( _port, _bitPosition ) ( (_port)- & gt; DIR = (_port)- & gt; DIR | (1 & lt; & lt; _bitPosition) )



/*! \brief This macro configures a pin in an I/O port or virtual port as an
* input.
*
* \note This macro is especially efficient with virtual ports, since only
* one CBI instruction is invoked.
*
* \param _port Pointer to the PORT_t or VPORT_t instance.
* \param _bitPosition Position of bit to set as input.
*/
#define PORT_SetPinAsInput( _port, _bitPosition ) ( (_port)- & gt; DIR = (_port)- & gt; DIR & ~(1 & lt; & lt; _bitPosition) )



/* Prototyping of functions. Documentation is found in source file. */

void PORT_ConfigureInterrupt0( PORT_t * port,
PORT_INT0LVL_t intLevel,
uint8_t pinMask);

void PORT_ConfigureInterrupt1( PORT_t * port,
PORT_INT1LVL_t intLevel,
uint8_t pinMask);

void PORT_ConfigurePins( PORT_t * port,
uint8_t pinMask,
uint8_t slewRateEnable,
uint8_t invertEnable,
PORT_OPC_t opc,
PORT_ISC_t isc);

void PORT_MapVirtualPort0(PORTCFG_VP0MAP_t realPort);
void PORT_MapVirtualPort1(PORTCFG_VP1MAP_t realPort);
void PORT_MapVirtualPort2(PORTCFG_VP2MAP_t realPort);
void PORT_MapVirtualPort3(PORTCFG_VP3MAP_t realPort);


#endif


xMega_official_drivers_and_examples.rar > port_driver.c

/* This file has been prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief
* XMEGA I/O Port driver source file.
*
* This file contains the function implementations the XMEGA I/O Port driver.
*
* The driver is not intended for size and/or speed critical code, since
* most functions are just a few lines of code, and the function call
* overhead would decrease code performance. The driver is intended for
* rapid prototyping and documentation purposes for getting started with
* the XMEGA I/O Port module.
*
* For size and/or speed critical code, it is recommended to copy the
* function contents directly into your application instead of making
* a function call.
*
* Several functions use the following construct:
* " some_register = ... | (some_parameter ? SOME_BIT_bm : 0) | ... "
* Although the use of the ternary operator ( if ? then : else ) is discouraged,
* in some occasions the operator makes it possible to write pretty clean and
* neat code. In this driver, the construct is used to set or not set a
* configuration bit based on a boolean input parameter, such as
* the " some_parameter " in the example above.
*
* \par Application note:
* AVR1313: Using the XMEGA I/O Pins and External Interrupts
*
* \par Documentation
* For comprehensive code documentation, supported compilers, compiler
* settings and supported devices see readme.html
*
* \author
* Atmel Corporation: http://www.atmel.com \n
* Support email: avr@atmel.com
*
* $Revision: 1569 $
* $Date: 2008-04-22 13:03:43 +0200 (ti, 22 apr 2008) $ \n
*
* Copyright (c) 2008, Atmel Corporation All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of ATMEL may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL " AS IS " AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
* SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*****************************************************************************/
#include " port_driver.h "



/*! \brief Configures interrupt 0.
*
* This function configures interrupt 0 to be associated with a set of pins and
* sets the desired interrupt level.
*
* \param port The port to configure.
* \param intLevel The desired interrupt level for port interrupt 0.
* \param pinMask A mask that selects the pins to associate with port interrupt 0.
*/
void PORT_ConfigureInterrupt0( PORT_t * port,
PORT_INT0LVL_t intLevel,
uint8_t pinMask )
{
port- & gt; INTCTRL = ( port- & gt; INTCTRL & ~PORT_INT0LVL_gm ) | intLevel;
port- & gt; INT0MASK = pinMask;
}


/*! \brief Configures interrupt 1.
*
* This function configures interrupt 1 to be associated with a set of pins and
* sets the desired interrupt level.
*
* \param port The port to configure.
* \param intLevel The desired interrupt level for port interrupt 1.
* \param pinMask A mask that selects the pins to associate with port interrupt 1.
*/
void PORT_ConfigureInterrupt1( PORT_t * port,
PORT_INT1LVL_t intLevel,
uint8_t pinMask )
{
port- & gt; INTCTRL = ( port- & gt; INTCTRL & ~PORT_INT1LVL_gm ) | intLevel;
port- & gt; INT1MASK = pinMask;
}



/*! \brief This function changes the configuration of a set of pins.
*
* \param port The port.
* \param pinMask A bit mask that selects the pins to configure.
* \param slewRateEnable Enable/disable slew rate control.
* \param invertEnable Enable/disable I/O inversion.
* \param opc Output/Pull Configuration.
* \param isc Input/Sense Configuration.
*/
void PORT_ConfigurePins( PORT_t * port,
uint8_t pinMask,
uint8_t slewRateEnable,
uint8_t invertEnable,
PORT_OPC_t opc,
PORT_ISC_t isc)
{
/* Build pin control register value. */
uint8_t temp = (uint8_t) opc |
isc |
(slewRateEnable ? PORT_SRLEN_bm : 0) |
(invertEnable ? PORT_INVEN_bm : 0);

/* Configure the pins in one atomic operation. */

/* Save status register. */
uint8_t sreg = SREG;

cli();
PORTCFG.MPCMASK = pinMask;
port- & gt; PIN0CTRL = temp;

/* Restore status register. */
SREG = sreg;
}


/*! \brief Maps a real port to virtual port 0.
*
* This function maps a real port to virtual port 0 to make some of the
* registers available in I/O space.
*
* \param realPort Selects the real port to map to virtual port 0.
*/
void PORT_MapVirtualPort0(PORTCFG_VP0MAP_t realPort)
{
PORTCFG.VPCTRLA = ( PORTCFG.VPCTRLA & ~PORTCFG_VP0MAP_gm ) | realPort;
}


/*! \brief Maps a real port to virtual port 1.
*
* This function maps a real port to virtual port 1 to make some of the
* registers available in I/O space.
*
* \param realPort Selects the real port to map to virtual port 1.
*/
void PORT_MapVirtualPort1(PORTCFG_VP1MAP_t realPort)
{
PORTCFG.VPCTRLA = ( PORTCFG.VPCTRLA & ~PORTCFG_VP1MAP_gm ) | realPort;
}


/*! \brief Maps a real port to virtual port 2.
*
* This function maps a real port to virtual port 2 to make some of the
* registers available in I/O space.
*
* \param realPort Selects the real port to map to virtual port 2.
*/
void PORT_MapVirtualPort2(PORTCFG_VP2MAP_t realPort)
{
PORTCFG.VPCTRLB = ( PORTCFG.VPCTRLB & ~PORTCFG_VP2MAP_gm ) | realPort;
}


/*! \brief Maps a real port to virtual port 3.
*
* This function maps a real port to virtual port 3 to make some of the
* registers available in I/O space.
*
* \param realPort Selects the real port to map to virtual port 3.
*/
void PORT_MapVirtualPort3(PORTCFG_VP3MAP_t realPort)
{
PORTCFG.VPCTRLB = ( PORTCFG.VPCTRLB & ~PORTCFG_VP3MAP_gm ) | realPort;
}


xMega_official_drivers_and_examples.rar > avr_compiler.h

/* This file has been prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief This file implements some macros that makes the IAR C-compiler and
* avr-gcc work with the same code base for the AVR architecture.
*
* \par Documentation
* For comprehensive code documentation, supported compilers, compiler
* settings and supported devices see readme.html
*
* \author
* Atmel Corporation: http://www.atmel.com \n
* Support email: avr@atmel.com
*
* $Revision: 613 $
* $Date: 2006-04-07 14:40:07 +0200 (fr, 07 apr 2006) $ \n
*
* Copyright (c) 2008, Atmel Corporation All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of ATMEL may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL " AS IS " AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
* SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************/

#ifndef COMPILER_AVR_H
#define COMPILER_AVR_H

#ifndef F_CPU
/*! \brief Define default CPU frequency, if this is not already defined. */
#define F_CPU 2000000UL
#endif

#include & lt; stdint.h & gt;
#include & lt; stdbool.h & gt;
#include & lt; stdlib.h & gt;

/*! \brief This macro will protect the following code from interrupts. */
#define AVR_ENTER_CRITICAL_REGION( ) uint8_t volatile saved_sreg = SREG; \
cli();

/*! \brief This macro must always be used in conjunction with AVR_ENTER_CRITICAL_REGION
* so the interrupts are enabled again.
*/
#define AVR_LEAVE_CRITICAL_REGION( ) SREG = saved_sreg;

#if defined( __ICCAVR__ )

#include & lt; inavr.h & gt;
#include & lt; ioavr.h & gt;
#include & lt; intrinsics.h & gt;
#include & lt; pgmspace.h & gt;

#ifndef __HAS_ELPM__
#define _MEMATTR __flash
#else /* __HAS_ELPM__ */
#define _MEMATTR __farflash
#endif /* __HAS_ELPM__ */

/*! \brief Perform a delay of \c us microseconds.
*
* The macro F_CPU is supposed to be defined to a constant defining the CPU
* clock frequency (in Hertz).
*
* The maximal possible delay is 262.14 ms / F_CPU in MHz.
*
* \note For the IAR compiler, currently F_CPU must be a
* multiple of 1000000UL (1 MHz).
*/
#define delay_us( us ) ( __delay_cycles( ( F_CPU / 1000000UL ) * ( us ) ) )

/*! \brief Preprocessor magic.
*
* Some preprocessor magic to allow for a header file abstraction of
* interrupt service routine declarations for the IAR compiler. This
* requires the use of the C99 _Pragma() directive (rather than the
* old #pragma one that could not be used as a macro replacement), as
* well as two different levels of preprocessor concetanations in
* order to do both, assign the correct interrupt vector name, as well
* as construct a unique function name for the ISR.
*
* \note Do *NOT* try to reorder the macros below, as this will only
* work in the given order.
*/
#define PRAGMA(x) _Pragma( #x )
#define ISR(vec) PRAGMA( vector=vec ) __interrupt void handler_##vec(void)
#define sei( ) (__enable_interrupt( ))
#define cli( ) (__disable_interrupt( ))

/*! \brief Define the no operation macro. */
#define nop( ) (__no_operation())

/*! \brief Define the watchdog reset macro. */
#define watchdog_reset( ) (__watchdog_reset( ))


#define INLINE PRAGMA( inline=forced ) static

#define FLASH_DECLARE(x) _MEMATTR x
#define FLASH_STRING(x) ((_MEMATTR const char *)(x))
#define FLASH_STRING_T char const _MEMATTR *
#define FLASH_BYTE_ARRAY_T uint8_t const _MEMATTR *
#define PGM_READ_BYTE(x) *(x)
#define PGM_READ_WORD(x) *(x)

#define SHORTENUM /**/

#elif defined( __GNUC__ )

#include & lt; avr/io.h & gt;
#include & lt; avr/interrupt.h & gt;
#include & lt; avr/pgmspace.h & gt;
#include & lt; util/delay.h & gt;

/*! \brief Define the delay_us macro for GCC. */
#define delay_us( us ) (_delay_us( us ))

#define INLINE static inline

/*! \brief Define the no operation macro. */
#define nop() do { __asm__ __volatile__ ( " nop " ); } while (0)

#define MAIN_TASK_PROLOGUE int


#define MAIN_TASK_EPILOGUE() return -1;

#define SHORTENUM __attribute__ ((packed))

#else
#error Compiler not supported.
#endif

#endif


xMega_official_drivers_and_examples.rar > avr__compiler_8h-source.html

@DOC_TITLE@







Xmega Application Note







avr_compiler.h Go to the documentation of this file. 00001 /* This file has been prepared for Doxygen automatic documentation generation.*/
00045 #ifndef COMPILER_AVR_H
00046 #define COMPILER_AVR_H
00047
00048 #ifndef F_CPU
00049
00050 #define F_CPU 2000000UL
00051 #endif
00052
00053 #include & lt;stdint.h & gt;
00054 #include & lt;stdbool.h & gt;
00055 #include & lt;stdlib.h & gt;
00056
00058 #define AVR_ENTER_CRITICAL_REGION( ) uint8_t volatile saved_sreg = SREG; \
00059 cli();
00060
00064 #define AVR_LEAVE_CRITICAL_REGION( ) SREG = saved_sreg;
00065
00066 #if defined( __ICCAVR__ )
00067
00068 #include & lt;inavr.h & gt;
00069 #include & lt;ioavr.h & gt;
00070 #include & lt;intrinsics.h & gt;
00071 #include & lt;pgmspace.h & gt;
00072
00073 #ifndef __HAS_ELPM__
00074 #define _MEMATTR __flash
00075 #else /* __HAS_ELPM__ */
00076 #define _MEMATTR __farflash
00077 #endif /* __HAS_ELPM__ */
00078
00089 #define delay_us( us ) ( __delay_cycles( ( F_CPU / 1000000UL ) * ( us ) ) )
00090
00104 #define PRAGMA(x) _Pragma( #x )
00105 #define ISR(vec) PRAGMA( vector=vec ) __interrupt void handler_##vec(void)
00106 #define sei( ) (__enable_interrupt( ))
00107 #define cli( ) (__disable_interrupt( ))
00108
00110 #define nop( ) (__no_operation())
00111
00113 #define watchdog_reset( ) (__watchdog_reset( ))
00114
00115
00116 #define INLINE PRAGMA( inline=forced ) static
00117
00118 #define FLASH_DECLARE(x) _MEMATTR x
00119 #define FLASH_STRING(x) ((_MEMATTR const char *)(x))
00120 #define FLASH_STRING_T char const _MEMATTR *
00121 #define FLASH_BYTE_ARRAY_T uint8_t const _MEMATTR *
00122 #define PGM_READ_BYTE(x) *(x)
00123 #define PGM_READ_WORD(x) *(x)
00124
00125 #define SHORTENUM
00126
00127 #elif defined( __GNUC__ )
00128
00129 #include & lt;avr/io.h & gt;
00130 #include & lt;avr/interrupt.h & gt;
00131 #include & lt;avr/pgmspace.h & gt;
00132 #include & lt;util/delay.h & gt;
00133
00135 #define delay_us( us ) (_delay_us( us ))
00136
00137 #define INLINE static inline
00138
00140 #define nop() do { __asm__ __volatile__ ( " nop " ); } while (0)
00141
00142 #define MAIN_TASK_PROLOGUE int
00143
00144
00145 #define MAIN_TASK_EPILOGUE() return -1;
00146
00147 #define SHORTENUM __attribute__ ((packed))
00148
00149 #else
00150 #error Compiler not supported.
00151 #endif
00152
00153 #endif
00154




@DOC_TITLE@












Generated on Wed Apr 23 08:22:06 2008 for AVR1313 Using the XMEGA I/O Pins and External Interrupts by 1.5.5


xMega_official_drivers_and_examples.rar > documentation_8h-source.html

@DOC_TITLE@







Xmega Application Note







documentation.h Go to the documentation of this file. 00001 /* Doxygen documentation mainpage ********************************************/




@DOC_TITLE@












Generated on Wed Apr 23 08:22:06 2008 for AVR1313 Using the XMEGA I/O Pins and External Interrupts by 1.5.5


xMega_official_drivers_and_examples.rar > atmel-footer.html

@DOC_TITLE@












Generated on $datetime for $projectname by $doxygenversion


xMega_official_drivers_and_examples.rar > port__driver_8c.html

@DOC_TITLE@







Xmega Application Note








port_driver.c File Reference Detailed Description
XMEGA I/O Port driver source file.

This file contains the function implementations the XMEGA I/O Port driver.
The driver is not intended for size and/or speed critical code, since most functions are just a few lines of code, and the function call overhead would decrease code performance. The driver is intended for rapid prototyping and documentation purposes for getting started with the XMEGA I/O Port module.
For size and/or speed critical code, it is recommended to copy the function contents directly into your application instead of making a function call.
Several functions use the following construct: " some_register = ... | (some_parameter ? SOME_BIT_bm : 0) | ... " Although the use of the ternary operator ( if ? then : else ) is discouraged, in some occasions the operator makes it possible to write pretty clean and neat code. In this driver, the construct is used to set or not set a configuration bit based on a boolean input parameter, such as the " some_parameter " in the example above.
Application note: AVR1313: Using the XMEGA I/O Pins and External Interrupts
Documentation For comprehensive code documentation, supported compilers, compiler settings and supported devices see readme.html
Author: Atmel Corporation: http://www.atmel.com
Support email: avr@atmel.com
Revision 1569
Date 2008-04-22 13:03:43 +0200 (ti, 22 apr 2008)


Copyright (c) 2008, Atmel Corporation All rights reserved.
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
3. The name of ATMEL may not be used to endorse or promote products derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY ATMEL " AS IS " AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Definition in file port_driver.c .


#include & quot; port_driver.h & quot;



Include dependency graph for port_driver.c:







Go to the source code of this file.

Functions
void & nbsp; PORT_ConfigureInterrupt0 (PORT_t *port, PORT_INT0LVL_t intLevel, uint8_t pinMask)

& nbsp; Configures interrupt 0.
void & nbsp; PORT_ConfigureInterrupt1 (PORT_t *port, PORT_INT1LVL_t intLevel, uint8_t pinMask)

& nbsp; Configures interrupt 1.
void & nbsp; PORT_ConfigurePins (PORT_t *port, uint8_t pinMask, uint8_t slewRateEnable, uint8_t invertEnable, PORT_OPC_t opc, PORT_ISC_t isc)

& nbsp; This function changes the configuration of a set of pins.
void & nbsp; PORT_MapVirtualPort0 (PORTCFG_VP0MAP_t realPort)

& nbsp; Maps a real port to virtual port 0.
void & nbsp; PORT_MapVirtualPort1 (PORTCFG_VP1MAP_t realPort)

& nbsp; Maps a real port to virtual port 1.
void & nbsp; PORT_MapVirtualPort2 (PORTCFG_VP2MAP_t realPort)

& nbsp; Maps a real port to virtual port 2.
void & nbsp; PORT_MapVirtualPort3 (PORTCFG_VP3MAP_t realPort)

& nbsp; Maps a real port to virtual port 3.

Function Documentation





void PORT_ConfigureInterrupt0
(
PORT_t * & nbsp;
port ,




PORT_INT0LVL_t & nbsp;
intLevel ,




uint8_t & nbsp;
pinMask & nbsp;



)







Configures interrupt 0.

This function configures interrupt 0 to be associated with a set of pins and sets the desired interrupt level.
Parameters:

port & nbsp; The port to configure.
intLevel & nbsp; The desired interrupt level for port interrupt 0.
pinMask & nbsp; A mask that selects the pins to associate with port interrupt 0.



Definition at line 80 of file port_driver.c .

Referenced by Example4() .
00083 {
00084 port- & gt;INTCTRL = ( port- & gt;INTCTRL & amp; ~PORT_INT0LVL_gm ) | intLevel;
00085 port- & gt;INT0MASK = pinMask;
00086 }










void PORT_ConfigureInterrupt1
(
PORT_t * & nbsp;
port ,




PORT_INT1LVL_t & nbsp;
intLevel ,




uint8_t & nbsp;
pinMask & nbsp;



)







Configures interrupt 1.

This function configures interrupt 1 to be associated with a set of pins and sets the desired interrupt level.
Parameters:

port & nbsp; The port to configure.
intLevel & nbsp; The desired interrupt level for port interrupt 1.
pinMask & nbsp; A mask that selects the pins to associate with port interrupt 1.



Definition at line 98 of file port_driver.c .
00101 {
00102 port- & gt;INTCTRL = ( port- & gt;INTCTRL & amp; ~PORT_INT1LVL_gm ) | intLevel;
00103 port- & gt;INT1MASK = pinMask;
00104 }










void PORT_ConfigurePins
(
PORT_t * & nbsp;
port ,




uint8_t & nbsp;
pinMask ,




uint8_t & nbsp;
slewRateEnable ,




uint8_t & nbsp;
invertEnable ,




PORT_OPC_t & nbsp;
opc ,




PORT_ISC_t & nbsp;
isc & nbsp;



)







This function changes the configuration of a set of pins.

Parameters:

port & nbsp; The port.
pinMask & nbsp; A bit mask that selects the pins to configure.
slewRateEnable & nbsp; Enable/disable slew rate control.
invertEnable & nbsp; Enable/disable I/O inversion.
opc & nbsp; Output/Pull Configuration.
isc & nbsp; Input/Sense Configuration.



Definition at line 117 of file port_driver.c .

Referenced by Example2() , and Example4() .
00123 {
00124 /* Build pin control register value. */
00125 uint8_t temp = (uint8_t) opc |
00126 isc |
00127 (slewRateEnable ? PORT_SRLEN_bm : 0) |
00128 (invertEnable ? PORT_INVEN_bm : 0);
00129
00130 /* Configure the pins in one atomic operation. */
00131
00132 /* Save status register. */
00133 uint8_t sreg = SREG;
00134
00135 cli();
00136 PORTCFG.MPCMASK = pinMask;
00137 port- & gt;PIN0CTRL = temp;
00138
00139 /* Restore status register. */
00140 SREG = sreg;
00141 }










void PORT_MapVirtualPort0
(
PORTCFG_VP0MAP_t & nbsp;
realPort
& nbsp;) & nbsp;







Maps a real port to virtual port 0.

This function maps a real port to virtual port 0 to make some of the registers available in I/O space.
Parameters:

realPort & nbsp; Selects the real port to map to virtual port 0.



Definition at line 151 of file port_driver.c .

Referenced by Example3() .
00152 {
00153 PORTCFG.VPCTRLA = ( PORTCFG.VPCTRLA & amp; ~PORTCFG_VP0MAP_gm ) | realPort;
00154 }










void PORT_MapVirtualPort1
(
PORTCFG_VP1MAP_t & nbsp;
realPort
& nbsp;) & nbsp;







Maps a real port to virtual port 1.

This function maps a real port to virtual port 1 to make some of the registers available in I/O space.
Parameters:

realPort & nbsp; Selects the real port to map to virtual port 1.



Definition at line 164 of file port_driver.c .

Referenced by Example3() .
00165 {
00166 PORTCFG.VPCTRLA = ( PORTCFG.VPCTRLA & amp; ~PORTCFG_VP1MAP_gm ) | realPort;
00167 }










void PORT_MapVirtualPort2
(
PORTCFG_VP2MAP_t & nbsp;
realPort
& nbsp;) & nbsp;







Maps a real port to virtual port 2.

This function maps a real port to virtual port 2 to make some of the registers available in I/O space.
Parameters:

realPort & nbsp; Selects the real port to map to virtual port 2.



Definition at line 177 of file port_driver.c .
00178 {
00179 PORTCFG.VPCTRLB = ( PORTCFG.VPCTRLB & amp; ~PORTCFG_VP2MAP_gm ) | realPort;
00180 }










void PORT_MapVirtualPort3
(
PORTCFG_VP3MAP_t & nbsp;
realPort
& nbsp;) & nbsp;







Maps a real port to virtual port 3.

This function maps a real port to virtual port 3 to make some of the registers available in I/O space.
Parameters:

realPort & nbsp; Selects the real port to map to virtual port 3.



Definition at line 190 of file port_driver.c .
00191 {
00192 PORTCFG.VPCTRLB = ( PORTCFG.VPCTRLB & amp; ~PORTCFG_VP3MAP_gm ) | realPort;
00193 }









@DOC_TITLE@












Generated on Wed Apr 23 08:22:06 2008 for AVR1313 Using the XMEGA I/O Pins and External Interrupts by 1.5.5


xMega_official_drivers_and_examples.rar > port__driver_8h.html

@DOC_TITLE@







Xmega Application Note








port_driver.h File Reference Detailed Description
XMEGA I/O Port driver header file.

This file contains the function prototypes and enumerator definitions for various configuration parameters for the XMEGA I/O Port driver.
This driver is intended for rapid prototyping and documentation purposes for getting started with the XMEGA I/O Ports. The driver is not optimized for speed or size. However, functions that are just a few lines of code are written as macros to eliminate function call overhead. When using these macros it is important to use the correct data type for the arguments, as this is not checked by the compiler.
Application note: AVR1313: Using the XMEGA I/O Pins and External Interrupts
Documentation For comprehensive code documentation, supported compilers, compiler settings and supported devices see readme.html
Author: Atmel Corporation: http://www.atmel.com
Support email: avr@atmel.com
Revision 1569
Date 2008-04-22 13:03:43 +0200 (ti, 22 apr 2008)


Copyright (c) 2008, Atmel Corporation All rights reserved.
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
3. The name of ATMEL may not be used to endorse or promote products derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY ATMEL " AS IS " AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Definition in file port_driver.h .


#include & quot; avr_compiler.h & quot;



Include dependency graph for port_driver.h:








This graph shows which files directly or indirectly include this file:







Go to the source code of this file.

Defines
#define & nbsp; PORT_ClearInterruptFlags (_port, _bitMask) & nbsp; & nbsp; & nbsp;( (_port)- & gt;INTFLAGS = _bitMask )

& nbsp; This macro clears interrupt flags, given by a bit mask, for an I/O port or a virtual port.
#define & nbsp; PORT_ClearOutputBit (_port, _bitPosition) & nbsp; & nbsp; & nbsp;( (_port)- & gt;OUT = (_port)- & gt;OUT & amp; ~(1 & lt; & lt; _bitPosition) )

& nbsp; This macro clears a bit in the OUT register of an I/O port or virtual port.
#define & nbsp; PORT_ClearPins (_port, _clearMask) & nbsp; & nbsp; & nbsp;( (_port)- & gt;OUTCLR = _clearMask )

& nbsp; Set the output value of a set of I/O pins to logic low.
#define & nbsp; PORT_GetInterruptFlags (_port, _bitMask) & nbsp; & nbsp; & nbsp;( (_port)- & gt;INTFLAGS & amp; _bitMask )

& nbsp; This macro returns the current state of the interrupt flags, given by a bit mask, for an I/O port or a virtual port.
#define & nbsp; PORT_GetPortValue (_port) & nbsp; & nbsp; & nbsp;( (_port)- & gt;IN )

& nbsp; This macro returns the current logic value of the port or virtual port.
#define & nbsp; PORT_SetDirection (_port, _directionMask) & nbsp; & nbsp; & nbsp;( (_port)- & gt;DIR = _directionMask )

& nbsp; This macro sets the data direction for all I/O pins in the port or the virtual port.
#define & nbsp; PORT_SetOutputBit (_port, _bitPosition) & nbsp; & nbsp; & nbsp;( (_port)- & gt;OUT = (_port)- & gt;OUT | (1 & lt; & lt; _bitPosition) )

& nbsp; This macro sets a bit in the OUT register of an I/O port or virtual port.
#define & nbsp; PORT_SetOutputValue (_port, _outValue) & nbsp; & nbsp; & nbsp;( (_port)- & gt;OUT = _outValue )

& nbsp; This macro sets the output value/logic level of all pins in the I/O port or virtual port.
#define & nbsp; PORT_SetPinAsInput (_port, _bitPosition) & nbsp; & nbsp; & nbsp;( (_port)- & gt;DIR = (_port)- & gt;DIR & amp; ~(1 & lt; & lt; _bitPosition) )

& nbsp; This macro configures a pin in an I/O port or virtual port as an input.
#define & nbsp; PORT_SetPinAsOutput (_port, _bitPosition) & nbsp; & nbsp; & nbsp;( (_port)- & gt;DIR = (_port)- & gt;DIR | (1 & lt; & lt; _bitPosition) )

& nbsp; This macro configures a pin in an I/O port or virtual port as an output.
#define & nbsp; PORT_SetPins (_port, _setMask) & nbsp; & nbsp; & nbsp;( (_port)- & gt;OUTSET = _setMask )

& nbsp; Set the output value of a set of I/O pins to logic high.
#define & nbsp; PORT_SetPinsAsInput (_port, _inputMask) & nbsp; & nbsp; & nbsp;( (_port)- & gt;DIRCLR = _inputMask )

& nbsp; Sets the data direction of a set of pins to input.
#define & nbsp; PORT_SetPinsAsOutput (_port, _outputMask) & nbsp; & nbsp; & nbsp;( (_port)- & gt;DIRSET = _outputMask )

& nbsp; Sets the data direction of a set of pins to output.
#define & nbsp; PORT_ToggleDirection (_port, _toggleMask) & nbsp; & nbsp; & nbsp;( (_port)- & gt;DIRTGL = _toggleMask )

& nbsp; Toggle the data direction of a set of pins.
#define & nbsp; PORT_TogglePins (_port, _toggleMask) & nbsp; & nbsp; & nbsp;( (_port)- & gt;OUTTGL = _toggleMask )

& nbsp; Toggle the output value of a set of I/O pins.
Functions
void & nbsp; PORT_ConfigureInterrupt0 (PORT_t *port, PORT_INT0LVL_t intLevel, uint8_t pinMask)

& nbsp; Configures interrupt 0.
void & nbsp; PORT_ConfigureInterrupt1 (PORT_t *port, PORT_INT1LVL_t intLevel, uint8_t pinMask)

& nbsp; Configures interrupt 1.
void & nbsp; PORT_ConfigurePins (PORT_t *port, uint8_t pinMask, uint8_t slewRateEnable, uint8_t invertEnable, PORT_OPC_t opc, PORT_ISC_t isc)

& nbsp; This function changes the configuration of a set of pins.
void & nbsp; PORT_MapVirtualPort0 (PORTCFG_VP0MAP_t realPort)

& nbsp; Maps a real port to virtual port 0.
void & nbsp; PORT_MapVirtualPort1 (PORTCFG_VP1MAP_t realPort)

& nbsp; Maps a real port to virtual port 1.
void & nbsp; PORT_MapVirtualPort2 (PORTCFG_VP2MAP_t realPort)

& nbsp; Maps a real port to virtual port 2.
void & nbsp; PORT_MapVirtualPort3 (PORTCFG_VP3MAP_t realPort)

& nbsp; Maps a real port to virtual port 3.

Define Documentation





#define PORT_ClearInterruptFlags
(
_port,


_bitMask & nbsp;

& nbsp;) & nbsp;
& nbsp; & nbsp; & nbsp;( (_port)- & gt;INTFLAGS = _bitMask )






This macro clears interrupt flags, given by a bit mask, for an I/O port or a virtual port.

/note This macro can be used for both I/O ports and virtual ports.
Parameters:

_port & nbsp; Pointer to the PORT_t or VPORT_t instance.
_bitMask & nbsp; Bit mask for interrupt flags to clear.



Definition at line 201 of file port_driver.h .








#define PORT_ClearOutputBit
(
_port,


_bitPosition & nbsp;

& nbsp;) & nbsp;
& nbsp; & nbsp; & nbsp;( (_port)- & gt;OUT = (_port)- & gt;OUT & amp; ~(1 & lt; & lt; _bitPosition) )






This macro clears a bit in the OUT register of an I/O port or virtual port.

Note: This macro is especially efficient with virtual ports, since only one CBI instruction is invoked.
Parameters:

_port & nbsp; Pointer to the PORT_t or VPORT_t instance.
_bitPosition & nbsp; Position of bit to cleared.



Definition at line 227 of file port_driver.h .








#define PORT_ClearPins
(
_port,


_clearMask & nbsp;

& nbsp;) & nbsp;
& nbsp; & nbsp; & nbsp;( (_port)- & gt;OUTCLR = _clearMask )






Set the output value of a set of I/O pins to logic low.

This macro sets the output value of a set of I/O pins to logic low. (Unless inverted I/O has been enabled for the pins) It does not alter the pins not specified in the bit mask.
Parameters:

_port & nbsp; Pointer to the PORT_t instance.
_clearMask & nbsp; The bit mask of pins to set to logic low level.



Definition at line 152 of file port_driver.h .








#define PORT_GetInterruptFlags
(
_port,


_bitMask & nbsp;

& nbsp;) & nbsp;
& nbsp; & nbsp; & nbsp;( (_port)- & gt;INTFLAGS & amp; _bitMask )






This macro returns the current state of the interrupt flags, given by a bit mask, for an I/O port or a virtual port.

/note This macro can also be used to access virtual ports.
Parameters:

_port & nbsp; Pointer to the PORT_t or VPORT_t instance.
_bitMask & nbsp; Bit mask for interrupt flags to read.


Returns: The state of the interrupt flags.

Definition at line 189 of file port_driver.h .








#define PORT_GetPortValue
(
_port & nbsp;

& nbsp;) & nbsp;
& nbsp; & nbsp; & nbsp;( (_port)- & gt;IN )






This macro returns the current logic value of the port or virtual port.

/note This macro can also be used to access virtual ports.
Parameters:

_port & nbsp; Pointer to the PORT_t or VPORT_t instance.


Returns: The current logic state of the port.

Definition at line 176 of file port_driver.h .

Referenced by Example1() , and Example3() .








#define PORT_SetDirection
(
_port,


_directionMask & nbsp;

& nbsp;) & nbsp;
& nbsp; & nbsp; & nbsp;( (_port)- & gt;DIR = _directionMask )






This macro sets the data direction for all I/O pins in the port or the virtual port.

/note This macro can also be used to access virtual ports.
Parameters:

_port & nbsp; Pointer to the PORT_t or VPORT_t instance.
_directionMask & nbsp; The direction setting mask. The direction for pin n in the port is controlled by bit n. A 0 means input. A 1 means output.



Definition at line 75 of file port_driver.h .

Referenced by Example3() .








#define PORT_SetOutputBit
(
_port,


_bitPosition & nbsp;

& nbsp;) & nbsp;
& nbsp; & nbsp; & nbsp;( (_port)- & gt;OUT = (_port)- & gt;OUT | (1 & lt; & lt; _bitPosition) )






This macro sets a bit in the OUT register of an I/O port or virtual port.

Note: This macro is especially efficient with virtual ports, since only one SBI instruction is invoked.
Parameters:

_port & nbsp; Pointer to the PORT_t or VPORT_t instance.
_bitPosition & nbsp; Position of bit to set.



Definition at line 214 of file port_driver.h .








#define PORT_SetOutputValue
(
_port,


_outValue & nbsp;

& nbsp;) & nbsp;
& nbsp; & nbsp; & nbsp;( (_port)- & gt;OUT = _outValue )






This macro sets the output value/logic level of all pins in the I/O port or virtual port.

/note This macro can also be used to access virtual ports.
Parameters:

_port & nbsp; Pointer to the PORT_t or VPORT_t instance.
_outValue & nbsp; The output value. Bit n in this parameter corresponds to pin n of the port.



Definition at line 126 of file port_driver.h .

Referenced by Example1() , and Example3() .








#define PORT_SetPinAsInput
(
_port,


_bitPosition & nbsp;

& nbsp;) & nbsp;
& nbsp; & nbsp; & nbsp;( (_port)- & gt;DIR = (_port)- & gt;DIR & amp; ~(1 & lt; & lt; _bitPosition) )






This macro configures a pin in an I/O port or virtual port as an input.

Note: This macro is especially efficient with virtual ports, since only one CBI instruction is invoked.
Parameters:

_port & nbsp; Pointer to the PORT_t or VPORT_t instance.
_bitPosition & nbsp; Position of bit to set as input.



Definition at line 253 of file port_driver.h .








#define PORT_SetPinAsOutput
(
_port,


_bitPosition & nbsp;

& nbsp;) & nbsp;
& nbsp; & nbsp; & nbsp;( (_port)- & gt;DIR = (_port)- & gt;DIR | (1 & lt; & lt; _bitPosition) )






This macro configures a pin in an I/O port or virtual port as an output.

Note: This macro is especially efficient with virtual ports, since only one SBI instruction is invoked.
Parameters:

_port & nbsp; Pointer to the PORT_t or VPORT_t instance.
_bitPosition & nbsp; Position of bit to set as output.



Definition at line 240 of file port_driver.h .








#define PORT_SetPins
(
_port,


_setMask & nbsp;

& nbsp;) & nbsp;
& nbsp; & nbsp; & nbsp;( (_port)- & gt;OUTSET = _setMask )






Set the output value of a set of I/O pins to logic high.

This macro sets the output value of a set of I/O pins to logic high. (Unless inverted I/O has been enabled for the pins) It does not alter the pins not specified in the bit mask.
Parameters:

_port & nbsp; Pointer to the PORT_t instance.
_setMask & nbsp; The bit mask of pins to set to logic high level.



Definition at line 139 of file port_driver.h .

Referenced by Example4() .








#define PORT_SetPinsAsInput
(
_port,


_inputMask & nbsp;

& nbsp;) & nbsp;
& nbsp; & nbsp; & nbsp;( (_port)- & gt;DIRCLR = _inputMask )






Sets the data direction of a set of pins to input.

This macro sets the data direction of the selected port pins to input without altering the data direction of the other pins in that port.
Parameters:

_port & nbsp; Pointer to the PORT_t instance.
_inputMask & nbsp; A bit mask of the pins to set as input. A one in bit location n will configure pin n as input.



Definition at line 101 of file port_driver.h .

Referenced by Example1() , and Example4() .








#define PORT_SetPinsAsOutput
(
_port,


_outputMask & nbsp;

& nbsp;) & nbsp;
& nbsp; & nbsp; & nbsp;( (_port)- & gt;DIRSET = _outputMask )






Sets the data direction of a set of pins to output.

This macro sets the data direction of the selected port pins to output without altering the data direction of the other pins in that port.
Parameters:

_port & nbsp; Pointer to the PORT_t instance.
_outputMask & nbsp; A bit mask of the pins to set as output. A one in bit location n will configure pin n as output.



Definition at line 88 of file port_driver.h .

Referenced by Example1() , and Example4() .








#define PORT_ToggleDirection
(
_port,


_toggleMask & nbsp;

& nbsp;) & nbsp;
& nbsp; & nbsp; & nbsp;( (_port)- & gt;DIRTGL = _toggleMask )






Toggle the data direction of a set of pins.

This macro toggles the data direction of the selected port pins without altering the data direction of the other pins in that port.
Parameters:

_port & nbsp; Pointer to the PORT_t instance.
_toggleMask & nbsp; A bit mask of the pins on which to toggle input direction.



Definition at line 113 of file port_driver.h .








#define PORT_TogglePins
(
_port,


_toggleMask & nbsp;

& nbsp;) & nbsp;
& nbsp; & nbsp; & nbsp;( (_port)- & gt;OUTTGL = _toggleMask )






Toggle the output value of a set of I/O pins.

This macro toggles the output value of a set of I/O pins. It does not alter the output value of pins not specified in the bit mask.
Parameters:

_port & nbsp; Pointer to the PORT_t instance.
_toggleMask & nbsp; The bit mask of pins to toggle.



Definition at line 164 of file port_driver.h .

Referenced by ISR() .



Function Documentation





void PORT_ConfigureInterrupt0
(
PORT_t * & nbsp;
port ,




PORT_INT0LVL_t & nbsp;
intLevel ,




uint8_t & nbsp;
pinMask & nbsp;



)







Configures interrupt 0.

This function configures interrupt 0 to be associated with a set of pins and sets the desired interrupt level.
Parameters:

port & nbsp; The port to configure.
intLevel & nbsp; The desired interrupt level for port interrupt 0.
pinMask & nbsp; A mask that selects the pins to associate with port interrupt 0.



Definition at line 80 of file port_driver.c .

Referenced by Example4() .
00083 {
00084 port- & gt;INTCTRL = ( port- & gt;INTCTRL & amp; ~PORT_INT0LVL_gm ) | intLevel;
00085 port- & gt;INT0MASK = pinMask;
00086 }










void PORT_ConfigureInterrupt1
(
PORT_t * & nbsp;
port ,




PORT_INT1LVL_t & nbsp;
intLevel ,




uint8_t & nbsp;
pinMask & nbsp;



)







Configures interrupt 1.

This function configures interrupt 1 to be associated with a set of pins and sets the desired interrupt level.
Parameters:

port & nbsp; The port to configure.
intLevel & nbsp; The desired interrupt level for port interrupt 1.
pinMask & nbsp; A mask that selects the pins to associate with port interrupt 1.



Definition at line 98 of file port_driver.c .
00101 {
00102 port- & gt;INTCTRL = ( port- & gt;INTCTRL & amp; ~PORT_INT1LVL_gm ) | intLevel;
00103 port- & gt;INT1MASK = pinMask;
00104 }










void PORT_ConfigurePins
(
PORT_t * & nbsp;
port ,




uint8_t & nbsp;
pinMask ,




uint8_t & nbsp;
slewRateEnable ,




uint8_t & nbsp;
invertEnable ,




PORT_OPC_t & nbsp;
opc ,




PORT_ISC_t & nbsp;
isc & nbsp;



)







This function changes the configuration of a set of pins.

Parameters:

port & nbsp; The port.
pinMask & nbsp; A bit mask that selects the pins to configure.
slewRateEnable & nbsp; Enable/disable slew rate control.
invertEnable & nbsp; Enable/disable I/O inversion.
opc & nbsp; Output/Pull Configuration.
isc & nbsp; Input/Sense Configuration.



Definition at line 117 of file port_driver.c .

Referenced by Example2() , and Example4() .
00123 {
00124 /* Build pin control register value. */
00125 uint8_t temp = (uint8_t) opc |
00126 isc |
00127 (slewRateEnable ? PORT_SRLEN_bm : 0) |
00128 (invertEnable ? PORT_INVEN_bm : 0);
00129
00130 /* Configure the pins in one atomic operation. */
00131
00132 /* Save status register. */
00133 uint8_t sreg = SREG;
00134
00135 cli();
00136 PORTCFG.MPCMASK = pinMask;
00137 port- & gt;PIN0CTRL = temp;
00138
00139 /* Restore status register. */
00140 SREG = sreg;
00141 }










void PORT_MapVirtualPort0
(
PORTCFG_VP0MAP_t & nbsp;
realPort
& nbsp;) & nbsp;







Maps a real port to virtual port 0.

This function maps a real port to virtual port 0 to make some of the registers available in I/O space.
Parameters:

realPort & nbsp; Selects the real port to map to virtual port 0.



Definition at line 151 of file port_driver.c .

Referenced by Example3() .
00152 {
00153 PORTCFG.VPCTRLA = ( PORTCFG.VPCTRLA & amp; ~PORTCFG_VP0MAP_gm ) | realPort;
00154 }










void PORT_MapVirtualPort1
(
PORTCFG_VP1MAP_t & nbsp;
realPort
& nbsp;) & nbsp;







Maps a real port to virtual port 1.

This function maps a real port to virtual port 1 to make some of the registers available in I/O space.
Parameters:

realPort & nbsp; Selects the real port to map to virtual port 1.



Definition at line 164 of file port_driver.c .

Referenced by Example3() .
00165 {
00166 PORTCFG.VPCTRLA = ( PORTCFG.VPCTRLA & amp; ~PORTCFG_VP1MAP_gm ) | realPort;
00167 }










void PORT_MapVirtualPort2
(
PORTCFG_VP2MAP_t & nbsp;
realPort
& nbsp;) & nbsp;







Maps a real port to virtual port 2.

This function maps a real port to virtual port 2 to make some of the registers available in I/O space.
Parameters:

realPort & nbsp; Selects the real port to map to virtual port 2.



Definition at line 177 of file port_driver.c .
00178 {
00179 PORTCFG.VPCTRLB = ( PORTCFG.VPCTRLB & amp; ~PORTCFG_VP2MAP_gm ) | realPort;
00180 }










void PORT_MapVirtualPort3
(
PORTCFG_VP3MAP_t & nbsp;
realPort
& nbsp;) & nbsp;







Maps a real port to virtual port 3.

This function maps a real port to virtual port 3 to make some of the registers available in I/O space.
Parameters:

realPort & nbsp; Selects the real port to map to virtual port 3.



Definition at line 190 of file port_driver.c .
00191 {
00192 PORTCFG.VPCTRLB = ( PORTCFG.VPCTRLB & amp; ~PORTCFG_VP3MAP_gm ) | realPort;
00193 }









@DOC_TITLE@












Generated on Wed Apr 23 08:22:07 2008 for AVR1313 Using the XMEGA I/O Pins and External Interrupts by 1.5.5


xMega_official_drivers_and_examples.rar > port__driver_8c-source.html

@DOC_TITLE@







Xmega Application Note







port_driver.c Go to the documentation of this file. 00001 /* This file has been prepared for Doxygen automatic documentation generation.*/
00067 #include " port_driver.h "
00068
00069
00070
00080 void PORT_ConfigureInterrupt0 ( PORT_t * port,
00081 PORT_INT0LVL_t intLevel,
00082 uint8_t pinMask )
00083 {
00084 port- & gt;INTCTRL = ( port- & gt;INTCTRL & amp; ~PORT_INT0LVL_gm ) | intLevel;
00085 port- & gt;INT0MASK = pinMask;
00086 }
00087
00088
00098 void PORT_ConfigureInterrupt1 ( PORT_t * port,
00099 PORT_INT1LVL_t intLevel,
00100 uint8_t pinMask )
00101 {
00102 port- & gt;INTCTRL = ( port- & gt;INTCTRL & amp; ~PORT_INT1LVL_gm ) | intLevel;
00103 port- & gt;INT1MASK = pinMask;
00104 }
00105
00106
00107
00117 void PORT_ConfigurePins ( PORT_t * port,
00118 uint8_t pinMask,
00119 uint8_t slewRateEnable,
00120 uint8_t invertEnable,
00121 PORT_OPC_t opc,
00122 PORT_ISC_t isc)
00123 {
00124 /* Build pin control register value. */
00125 uint8_t temp = (uint8_t) opc |
00126 isc |
00127 (slewRateEnable ? PORT_SRLEN_bm : 0) |
00128 (invertEnable ? PORT_INVEN_bm : 0);
00129
00130 /* Configure the pins in one atomic operation. */
00131
00132 /* Save status register. */
00133 uint8_t sreg = SREG;
00134
00135 cli();
00136 PORTCFG.MPCMASK = pinMask;
00137 port- & gt;PIN0CTRL = temp;
00138
00139 /* Restore status register. */
00140 SREG = sreg;
00141 }
00142
00143
00151 void PORT_MapVirtualPort0 (PORTCFG_VP0MAP_t realPort)
00152 {
00153 PORTCFG.VPCTRLA = ( PORTCFG.VPCTRLA & amp; ~PORTCFG_VP0MAP_gm ) | realPort;
00154 }
00155
00156
00164 void PORT_MapVirtualPort1 (PORTCFG_VP1MAP_t realPort)
00165 {
00166 PORTCFG.VPCTRLA = ( PORTCFG.VPCTRLA & amp; ~PORTCFG_VP1MAP_gm ) | realPort;
00167 }
00168
00169
00177 void PORT_MapVirtualPort2 (PORTCFG_VP2MAP_t realPort)
00178 {
00179 PORTCFG.VPCTRLB = ( PORTCFG.VPCTRLB & amp; ~PORTCFG_VP2MAP_gm ) | realPort;
00180 }
00181
00182
00190 void PORT_MapVirtualPort3 (PORTCFG_VP3MAP_t realPort)
00191 {
00192 PORTCFG.VPCTRLB = ( PORTCFG.VPCTRLB & amp; ~PORTCFG_VP3MAP_gm ) | realPort;
00193 }




@DOC_TITLE@












Generated on Wed Apr 23 08:22:06 2008 for AVR1313 Using the XMEGA I/O Pins and External Interrupts by 1.5.5


xMega_official_drivers_and_examples.rar > port__example_8c-source.html

@DOC_TITLE@







Xmega Application Note







port_example.c Go to the documentation of this file. 00001 /* This file has been prepared for Doxygen automatic documentation generation.*/
00051 #include " avr_compiler.h "
00052 #include " port_driver.h "
00053
00054 void Example1 ( void );
00055 void Example2 ( void );
00056 void Example3 ( void );
00057 void Example4 ( void );
00058
00059
00060 void main ( void )
00061 {
00062 Example1 ();
00063 /*Example2();*/
00064 /*Example3();*/
00065 /*Example4();*/
00066
00067 while ( true ){
00068
00069 }
00070 }
00071
00072
00081 void Example1 ( void )
00082 {
00083 /* Configure data direction for PORTC and PORTD. */
00084 PORT_SetPinsAsInput ( & amp;PORTC, 0xFF );
00085 PORT_SetPinsAsOutput ( & amp;PORTD, 0xFF );
00086
00087 /* Continously copy the value from PORTC to PORTD. */
00088 do {
00089 uint8_t temp = PORT_GetPortValue ( & amp;PORTC );
00090 PORT_SetOutputValue ( & amp;PORTD, temp );
00091 } while ( true );
00092 }
00093
00094
00103 void Example2 ( void )
00104 {
00105 PORT_ConfigurePins ( & amp;PORTC,
00106 0x0F,
00107 false ,
00108 false ,
00109 PORT_OPC_WIREDANDPULL_gc,
00110 PORT_ISC_BOTHEDGES_gc );
00111 }
00112
00113
00122 void Example3 ( void )
00123 {
00124 /* Map the ports. */
00125 PORT_MapVirtualPort0 ( PORTCFG_VP0MAP_PORTC_gc );
00126 PORT_MapVirtualPort1 ( PORTCFG_VP1MAP_PORTD_gc );
00127
00128 /* Configure VPORT0 as input and VPORT1 as output. */
00129 PORT_SetDirection ( & amp;VPORT0, 0x00 );
00130 PORT_SetDirection ( & amp;VPORT1, 0xFF );
00131
00132 /* Continously copy the value from PORTC to PORTD using the
00133 * virtual ports.
00134 */
00135 do {
00136 uint8_t temp = PORT_GetPortValue ( & amp;VPORT0 );
00137 PORT_SetOutputValue ( & amp;VPORT1, temp );
00138 } while ( true );
00139 }
00140
00141
00151 void Example4 ( void )
00152 {
00153 /* Configure PC0 as input, triggered on rising edge. */
00154 PORT_ConfigurePins ( & amp;PORTC,
00155 0x01,
00156 false ,
00157 false ,
00158 PORT_OPC_TOTEM_gc,
00159 PORT_ISC_RISING_gc );
00160
00161 PORT_SetPinsAsInput ( & amp;PORTC, 0x01 );
00162
00163 /* Configure PORTD as output with the pattern 0x55. */
00164 PORT_SetPinsAsOutput ( & amp;PORTD, 0xFF );
00165 PORT_SetPins ( & amp;PORTD, 0x55 );
00166
00167 /* Configure Interrupt0 to have medium interrupt level, triggered by pin 0. */
00168 PORT_ConfigureInterrupt0 ( & amp;PORTC, PORT_INT0LVL_MED_gc, 0x01 );
00169
00170 /* Enable medium level interrupts in the PMIC. */
00171 PMIC.CTRL |= PMIC_MEDLVLEN_bm;
00172
00173 /* Enable the global interrupt flag. */
00174 sei();
00175 }
00176
00177
00183 ISR (PORTC_INT0_vect)
00184 {
00185 PORT_TogglePins ( & amp;PORTD, 0xFF );
00186 }
00187




@DOC_TITLE@












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xMega_official_drivers_and_examples.rar > globals_func.html

@DOC_TITLE@







Xmega Application Note









All
Functions
Defines



& nbsp;


Example1()
: port_example.c
Example2()
: port_example.c
Example3()
: port_example.c
Example4()
: port_example.c
ISR()
: port_example.c
main()
: port_example.c
PORT_ConfigureInterrupt0()
: port_driver.c
, port_driver.h
PORT_ConfigureInterrupt1()
: port_driver.h
, port_driver.c
PORT_ConfigurePins()
: port_driver.c
, port_driver.h
PORT_MapVirtualPort0()
: port_driver.h
, port_driver.c
PORT_MapVirtualPort1()
: port_driver.c
, port_driver.h
PORT_MapVirtualPort2()
: port_driver.c
, port_driver.h
PORT_MapVirtualPort3()
: port_driver.h
, port_driver.c





@DOC_TITLE@












Generated on Wed Apr 23 08:22:07 2008 for AVR1313 Using the XMEGA I/O Pins and External Interrupts by 1.5.5


xMega_official_drivers_and_examples.rar > avr__compiler_8h.html

@DOC_TITLE@







Xmega Application Note








avr_compiler.h File Reference Detailed Description
This file implements some macros that makes the IAR C-compiler and avr-gcc work with the same code base for the AVR architecture.

Documentation For comprehensive code documentation, supported compilers, compiler settings and supported devices see readme.html
Author: Atmel Corporation: http://www.atmel.com
Support email: avr@atmel.com
Revision 613
Date 2006-04-07 14:40:07 +0200 (fr, 07 apr 2006)


Copyright (c) 2008, Atmel Corporation All rights reserved.
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
3. The name of ATMEL may not be used to endorse or promote products derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY ATMEL " AS IS " AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Definition in file avr_compiler.h .


#include & lt;stdint.h & gt;
#include & lt;stdbool.h & gt;
#include & lt;stdlib.h & gt;



Include dependency graph for avr_compiler.h:






This graph shows which files directly or indirectly include this file:







Go to the source code of this file.

Defines
#define & nbsp; AVR_ENTER_CRITICAL_REGION ()

& nbsp; This macro will protect the following code from interrupts.
#define & nbsp; AVR_LEAVE_CRITICAL_REGION () & nbsp; & nbsp; & nbsp;SREG = saved_sreg;

& nbsp; This macro must always be used in conjunction with AVR_ENTER_CRITICAL_REGION so the interrupts are enabled again.
#define & nbsp; F_CPU & nbsp; & nbsp; & nbsp;2000000UL

& nbsp; Define default CPU frequency, if this is not already defined.

Define Documentation





#define AVR_ENTER_CRITICAL_REGION
(
& nbsp;

& nbsp;) & nbsp;







Value: uint8_t volatile saved_sreg = SREG; \
cli();
This macro will protect the following code from interrupts.


Definition at line 58 of file avr_compiler.h .








#define AVR_LEAVE_CRITICAL_REGION
(
& nbsp;

& nbsp;) & nbsp;
& nbsp; & nbsp; & nbsp;SREG = saved_sreg;






This macro must always be used in conjunction with AVR_ENTER_CRITICAL_REGION so the interrupts are enabled again.


Definition at line 64 of file avr_compiler.h .








#define F_CPU & nbsp; & nbsp; & nbsp;2000000UL






Define default CPU frequency, if this is not already defined.


Definition at line 50 of file avr_compiler.h .







@DOC_TITLE@












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xMega_official_drivers_and_examples.rar > main.html

@DOC_TITLE@







Xmega Application Note








AVR1313 Using the XMEGA I/O Pins and External Interrupts Documentation

Atmel AVR Application Notes
Introduction
This documents the firmware for the application note.

Compilation Info
This firmware was compiled with IAR Embedded Workbench 5.10 and WinAVR 20080411.

To make the project in IAR EWAVR:
Add the .c files (and .S90 files where applicable) for the given example to your project. Use device ATxmega128A1 and enable bit definitions in I/O include files, optimization low for debug target and high for release, output format: ubrof8 for Debug and intel_extended for Release, select Normal DLIB as library.

To make the project in WinAVR:
Add the .c files (and .S files where applicable) for the given example to your project. Use device ATxmega128A1, optimization low for debug target and high for release.

Device Info
All XMEGA devices with the targeted module can be used. The example is written for ATxmega128A1.
Contact Info
For more info about Atmel AVR visit http://www.atmel.com/products/AVR/
For application notes visit http://www.atmel.com/dyn/products/app_notes.asp?family_id=607
Support mail: avr@atmel.com

Revision 1251
Date 2008-02-18 15:33:18 +0100 (ma, 18 feb 2008)

Copyright (c) 2008, Atmel Corporation All rights reserved.
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
3. The name of ATMEL may not be used to endorse or promote products derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY ATMEL " AS IS " AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.



@DOC_TITLE@












Generated on Wed Apr 23 08:22:06 2008 for AVR1313 Using the XMEGA I/O Pins and External Interrupts by 1.5.5


xMega_official_drivers_and_examples.rar > port__driver_8h-source.html

@DOC_TITLE@







Xmega Application Note







port_driver.h Go to the documentation of this file. 00001 /* This file has been prepared for Doxygen automatic documentation generation.*/
00058 #ifndef PORT_DRIVER_H
00059 #define PORT_DRIVER_H
00060
00061 #include " avr_compiler.h "
00062
00063 /* Definitions of macros. */
00064
00075 #define PORT_SetDirection( _port, _directionMask) ( (_port)- & gt;DIR = _directionMask )
00076
00077
00078
00088 #define PORT_SetPinsAsOutput( _port, _outputMask ) ( (_port)- & gt;DIRSET = _outputMask )
00089
00090
00091
00101 #define PORT_SetPinsAsInput( _port, _inputMask) ( (_port)- & gt;DIRCLR = _inputMask )
00102
00103
00104
00113 #define PORT_ToggleDirection( _port, _toggleMask) ( (_port)- & gt;DIRTGL = _toggleMask )
00114
00115
00116
00126 #define PORT_SetOutputValue( _port, _outValue) ( (_port)- & gt;OUT = _outValue )
00127
00128
00129
00139 #define PORT_SetPins( _port, _setMask) ( (_port)- & gt;OUTSET = _setMask )
00140
00141
00142
00152 #define PORT_ClearPins( _port, _clearMask) ( (_port)- & gt;OUTCLR = _clearMask )
00153
00154
00155
00164 #define PORT_TogglePins( _port, _toggleMask ) ( (_port)- & gt;OUTTGL = _toggleMask )
00165
00166
00167
00176 #define PORT_GetPortValue( _port ) ( (_port)- & gt;IN )
00177
00178
00179
00189 #define PORT_GetInterruptFlags( _port, _bitMask ) ( (_port)- & gt;INTFLAGS & amp; _bitMask )
00190
00191
00192
00201 #define PORT_ClearInterruptFlags( _port, _bitMask ) ( (_port)- & gt;INTFLAGS = _bitMask )
00202
00203
00204
00214 #define PORT_SetOutputBit( _port, _bitPosition ) ( (_port)- & gt;OUT = (_port)- & gt;OUT | (1 & lt; & lt; _bitPosition) )
00215
00216
00217
00227 #define PORT_ClearOutputBit( _port, _bitPosition ) ( (_port)- & gt;OUT = (_port)- & gt;OUT & amp; ~(1 & lt; & lt; _bitPosition) )
00228
00229
00230
00240 #define PORT_SetPinAsOutput( _port, _bitPosition ) ( (_port)- & gt;DIR = (_port)- & gt;DIR | (1 & lt; & lt; _bitPosition) )
00241
00242
00243
00253 #define PORT_SetPinAsInput( _port, _bitPosition ) ( (_port)- & gt;DIR = (_port)- & gt;DIR & amp; ~(1 & lt; & lt; _bitPosition) )
00254
00255
00256
00257 /* Prototyping of functions. Documentation is found in source file. */
00258
00259 void PORT_ConfigureInterrupt0 ( PORT_t * port,
00260 PORT_INT0LVL_t intLevel,
00261 uint8_t pinMask);
00262
00263 void PORT_ConfigureInterrupt1 ( PORT_t * port,
00264 PORT_INT1LVL_t intLevel,
00265 uint8_t pinMask);
00266
00267 void PORT_ConfigurePins ( PORT_t * port,
00268 uint8_t pinMask,
00269 uint8_t slewRateEnable,
00270 uint8_t invertEnable,
00271 PORT_OPC_t opc,
00272 PORT_ISC_t isc);
00273
00274 void PORT_MapVirtualPort0 (PORTCFG_VP0MAP_t realPort);
00275 void PORT_MapVirtualPort1 (PORTCFG_VP1MAP_t realPort);
00276 void PORT_MapVirtualPort2 (PORTCFG_VP2MAP_t realPort);
00277 void PORT_MapVirtualPort3 (PORTCFG_VP3MAP_t realPort);
00278
00279
00280 #endif




@DOC_TITLE@












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xMega_official_drivers_and_examples.rar > files.html

@DOC_TITLE@







Xmega Application Note








File List Here is a list of all files with brief descriptions:
avr_compiler.h [code] This file implements some macros that makes the IAR C-compiler and avr-gcc work with the same code base for the AVR architecture
documentation.h [code]
port_driver.c [code] XMEGA I/O Port driver source file
port_driver.h [code] XMEGA I/O Port driver header file
port_example.c [code] XMEGA I/O Port driver example source





@DOC_TITLE@












Generated on Wed Apr 23 08:22:07 2008 for AVR1313 Using the XMEGA I/O Pins and External Interrupts by 1.5.5


xMega_official_drivers_and_examples.rar > globals.html

@DOC_TITLE@







Xmega Application Note









All
Functions
Defines




a
e
f
i
m
p





Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- a -
AVR_ENTER_CRITICAL_REGION
: avr_compiler.h
AVR_LEAVE_CRITICAL_REGION
: avr_compiler.h

- e -
Example1()
: port_example.c
Example2()
: port_example.c
Example3()
: port_example.c
Example4()
: port_example.c

- f -
F_CPU
: avr_compiler.h

- i -
ISR()
: port_example.c

- m -
main()
: port_example.c

- p -
PORT_ClearInterruptFlags
: port_driver.h
PORT_ClearOutputBit
: port_driver.h
PORT_ClearPins
: port_driver.h
PORT_ConfigureInterrupt0()
: port_driver.c
, port_driver.h
PORT_ConfigureInterrupt1()
: port_driver.c
, port_driver.h
PORT_ConfigurePins()
: port_driver.c
, port_driver.h
PORT_GetInterruptFlags
: port_driver.h
PORT_GetPortValue
: port_driver.h
PORT_MapVirtualPort0()
: port_driver.c
, port_driver.h
PORT_MapVirtualPort1()
: port_driver.c
, port_driver.h
PORT_MapVirtualPort2()
: port_driver.c
, port_driver.h
PORT_MapVirtualPort3()
: port_driver.c
, port_driver.h
PORT_SetDirection
: port_driver.h
PORT_SetOutputBit
: port_driver.h
PORT_SetOutputValue
: port_driver.h
PORT_SetPinAsInput
: port_driver.h
PORT_SetPinAsOutput
: port_driver.h
PORT_SetPins
: port_driver.h
PORT_SetPinsAsInput
: port_driver.h
PORT_SetPinsAsOutput
: port_driver.h
PORT_ToggleDirection
: port_driver.h
PORT_TogglePins
: port_driver.h





@DOC_TITLE@












Generated on Wed Apr 23 08:22:07 2008 for AVR1313 Using the XMEGA I/O Pins and External Interrupts by 1.5.5


xMega_official_drivers_and_examples.rar > atmel-header.html

@DOC_TITLE@







Xmega Application Note


xMega_official_drivers_and_examples.rar > documentation_8h.html

@DOC_TITLE@







Xmega Application Note








documentation.h File Reference



Go to the source code of this file.






@DOC_TITLE@












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xMega_official_drivers_and_examples.rar > index.html

AVR1313 Using the XMEGA I/O Pins and External Interrupts




Frames are disabled. Click here to go to the main page.


xMega_official_drivers_and_examples.rar > graph_legend.html

@DOC_TITLE@







Xmega Application Note








Graph Legend This page explains how to interpret the graphs that are generated by doxygen.
Consider the following example: /*! Invisible class because of truncation */
class Invisible { };

/*! Truncated class, inheritance relation is hidden */
class Truncated : public Invisible { };

/* Class not documented with doxygen comments */
class Undocumented { };

/*! Class that is inherited using public inheritance */
class PublicBase : public Truncated { };

/*! A template class */
template & lt; class T & gt; class Templ { };

/*! Class that is inherited using protected inheritance */
class ProtectedBase { };

/*! Class that is inherited using private inheritance */
class PrivateBase { };

/*! Class that is used by the Inherited class */
class Used { };

/*! Super class that inherits a number of other classes */
class Inherited : public PublicBase,
protected ProtectedBase,
private PrivateBase,
public Undocumented,
public Templ & lt;int & gt;
{
private :
Used *m_usedClass;
};
If the MAX_DOT_GRAPH_HEIGHT tag in the configuration file is set to 240 this will result in the following graph:




The boxes in the above graph have the following meaning:

A filled gray box represents the struct or class for which the graph is generated.

A box with a black border denotes a documented struct or class.

A box with a grey border denotes an undocumented struct or class.

A box with a red border denotes a documented struct or class forwhich not all inheritance/containment relations are shown. A graph is truncated if it does not fit within the specified boundaries.

The arrows have the following meaning:

A dark blue arrow is used to visualize a public inheritance relation between two classes.

A dark green arrow is used for protected inheritance.

A dark red arrow is used for private inheritance.

A purple dashed arrow is used if a class is contained or used by another class. The arrow is labeled with the variable(s) through which the pointed class or struct is accessible.

A yellow dashed arrow denotes a relation between a template instance and the template class it was instantiated from. The arrow is labeled with the template parameters of the instance.





@DOC_TITLE@












Generated on Wed Apr 23 08:22:07 2008 for AVR1313 Using the XMEGA I/O Pins and External Interrupts by 1.5.5


xMega_official_drivers_and_examples.rar > port__example_8c.html

@DOC_TITLE@







Xmega Application Note








port_example.c File Reference Detailed Description
XMEGA I/O Port driver example source.

This file contains an example application that demonstrates the I/O Port driver. It shows how to set up the I/O Ports as described in the examples in the " Getting Started " section of the application note document.
Application note: AVR1313: Using the XMEGA I/O pins and External Interrupts
Documentation For comprehensive code documentation, supported compilers, compiler settings and supported devices see readme.html
Author: Atmel Corporation: http://www.atmel.com
Support email: avr@atmel.com
Revision 1569
Date 2008-04-22 13:03:43 +0200 (ti, 22 apr 2008)


Copyright (c) 2008, Atmel Corporation All rights reserved.
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
3. The name of ATMEL may not be used to endorse or promote products derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY ATMEL " AS IS " AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Definition in file port_example.c .


#include & quot; avr_compiler.h & quot;
#include & quot; port_driver.h & quot;



Include dependency graph for port_example.c:







Go to the source code of this file.

Functions
void & nbsp; Example1 (void)

& nbsp; Getting started example 1.
void & nbsp; Example2 (void)

& nbsp; Getting started example 2.
void & nbsp; Example3 (void)

& nbsp; Getting started example 3.
void & nbsp; Example4 (void)

& nbsp; Getting started example 4.
& nbsp; ISR (PORTC_INT0_vect)

& nbsp; Interrupt service routine for Example4() .
void & nbsp; main (void)


Function Documentation





void Example1
(
void & nbsp;

& nbsp;) & nbsp;







Getting started example 1.

This function implements the " Basic Digital I/O " example from the " Getting Started " section in the application note.
This function will continously read input from 8 switches connected to PORTC and output the pin state to 8 LEDs connected to PORTD.
Definition at line 81 of file port_example.c .

References PORT_GetPortValue , PORT_SetOutputValue , PORT_SetPinsAsInput , and PORT_SetPinsAsOutput .

Referenced by main() .
00082 {
00083 /* Configure data direction for PORTC and PORTD. */
00084 PORT_SetPinsAsInput ( & amp;PORTC, 0xFF );
00085 PORT_SetPinsAsOutput ( & amp;PORTD, 0xFF );
00086
00087 /* Continously copy the value from PORTC to PORTD. */
00088 do {
00089 uint8_t temp = PORT_GetPortValue ( & amp;PORTC );
00090 PORT_SetOutputValue ( & amp;PORTD, temp );
00091 } while ( true );
00092 }










void Example2
(
void & nbsp;

& nbsp;) & nbsp;







Getting started example 2.

This function implements the " Configuring Several Pins in One Operation " example from the " Getting Started " section in the application note.
This function configures pins 0-3 on PORTC for Wired-AND with pull-up operation.
Definition at line 103 of file port_example.c .

References PORT_ConfigurePins() .
00104 {
00105 PORT_ConfigurePins ( & amp;PORTC,
00106 0x0F,
00107 false ,
00108 false ,
00109 PORT_OPC_WIREDANDPULL_gc,
00110 PORT_ISC_BOTHEDGES_gc );
00111 }





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void Example3
(
void & nbsp;

& nbsp;) & nbsp;







Getting started example 3.

This function implements the " Mapping Real Ports to Virtual Ports " example from the " Getting Started " section in the application note.
This function maps PORTC to Virtual port 0 and PORTD to Virtual PORT1, and performs the same task as in Example1() using virtual ports.
Definition at line 122 of file port_example.c .

References PORT_GetPortValue , PORT_MapVirtualPort0() , PORT_MapVirtualPort1() , PORT_SetDirection , and PORT_SetOutputValue .
00123 {
00124 /* Map the ports. */
00125 PORT_MapVirtualPort0 ( PORTCFG_VP0MAP_PORTC_gc );
00126 PORT_MapVirtualPort1 ( PORTCFG_VP1MAP_PORTD_gc );
00127
00128 /* Configure VPORT0 as input and VPORT1 as output. */
00129 PORT_SetDirection ( & amp;VPORT0, 0x00 );
00130 PORT_SetDirection ( & amp;VPORT1, 0xFF );
00131
00132 /* Continously copy the value from PORTC to PORTD using the
00133 * virtual ports.
00134 */
00135 do {
00136 uint8_t temp = PORT_GetPortValue ( & amp;VPORT0 );
00137 PORT_SetOutputValue ( & amp;VPORT1, temp );
00138 } while ( true );
00139 }





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void Example4
(
void & nbsp;

& nbsp;) & nbsp;







Getting started example 4.

This function implements the " Configuring an I/O Pin for Interrupt Generation " example from the " Getting Started " section in the application note.
This function configures PORTC interrupt0 as a medium level interrupt, triggered by the rising edge of PC0. The interrupt service routine toggles the output on PORTD.
Definition at line 151 of file port_example.c .

References PORT_ConfigureInterrupt0() , PORT_ConfigurePins() , PORT_SetPins , PORT_SetPinsAsInput , and PORT_SetPinsAsOutput .
00152 {
00153 /* Configure PC0 as input, triggered on rising edge. */
00154 PORT_ConfigurePins ( & amp;PORTC,
00155 0x01,
00156 false ,
00157 false ,
00158 PORT_OPC_TOTEM_gc,
00159 PORT_ISC_RISING_gc );
00160
00161 PORT_SetPinsAsInput ( & amp;PORTC, 0x01 );
00162
00163 /* Configure PORTD as output with the pattern 0x55. */
00164 PORT_SetPinsAsOutput ( & amp;PORTD, 0xFF );
00165 PORT_SetPins ( & amp;PORTD, 0x55 );
00166
00167 /* Configure Interrupt0 to have medium interrupt level, triggered by pin 0. */
00168 PORT_ConfigureInterrupt0 ( & amp;PORTC, PORT_INT0LVL_MED_gc, 0x01 );
00169
00170 /* Enable medium level interrupts in the PMIC. */
00171 PMIC.CTRL |= PMIC_MEDLVLEN_bm;
00172
00173 /* Enable the global interrupt flag. */
00174 sei();
00175 }





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ISR
(
PORTC_INT0_vect & nbsp;

& nbsp;) & nbsp;







Interrupt service routine for Example4() .

When initialized using Example4() , this ISR is called on every rising edge on PC0.
Definition at line 183 of file port_example.c .

References PORT_TogglePins .
00184 {
00185 PORT_TogglePins ( & amp;PORTD, 0xFF );
00186 }










void main
(
void & nbsp;

& nbsp;) & nbsp;








Definition at line 60 of file port_example.c .

References Example1() .
00061 {
00062 Example1 ();
00063 /*Example2();*/
00064 /*Example3();*/
00065 /*Example4();*/
00066
00067 while ( true ){
00068
00069 }
00070 }





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@DOC_TITLE@












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xMega_official_drivers_and_examples.rar > globals_defs.html

@DOC_TITLE@







Xmega Application Note









All
Functions
Defines



& nbsp;


AVR_ENTER_CRITICAL_REGION
: avr_compiler.h
AVR_LEAVE_CRITICAL_REGION
: avr_compiler.h
F_CPU
: avr_compiler.h
PORT_ClearInterruptFlags
: port_driver.h
PORT_ClearOutputBit
: port_driver.h
PORT_ClearPins
: port_driver.h
PORT_GetInterruptFlags
: port_driver.h
PORT_GetPortValue
: port_driver.h
PORT_SetDirection
: port_driver.h
PORT_SetOutputBit
: port_driver.h
PORT_SetOutputValue
: port_driver.h
PORT_SetPinAsInput
: port_driver.h
PORT_SetPinAsOutput
: port_driver.h
PORT_SetPins
: port_driver.h
PORT_SetPinsAsInput
: port_driver.h
PORT_SetPinsAsOutput
: port_driver.h
PORT_ToggleDirection
: port_driver.h
PORT_TogglePins
: port_driver.h





@DOC_TITLE@












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xMega_official_drivers_and_examples.rar > tree.html

TreeView







AVR1313 Using the XMEGA I/O Pins and External Interrupts

Main Page
File List

avr_compiler.h
documentation.h
port_driver.c
port_driver.h
port_example.c

Globals


xMega_official_drivers_and_examples.rar > port_example.c

/* This file has been prepared for Doxygen automatic documentation generation.*/
/*! \file *********************************************************************
*
* \brief XMEGA I/O Port driver example source.
*
* This file contains an example application that demonstrates the I/O Port
* driver. It shows how to set up the I/O Ports as described in the
* examples in the " Getting Started " section of the application note
* document.
*
* \par Application note:
* AVR1313: Using the XMEGA I/O pins and External Interrupts
*
* \par Documentation
* For comprehensive code documentation, supported compilers, compiler
* settings and supported devices see readme.html
*
* \author
* Atmel Corporation: http://www.atmel.com \n
* Support email: avr@atmel.com
*
* $Revision: 1569 $
* $Date: 2008-04-22 13:03:43 +0200 (ti, 22 apr 2008) $ \n
*
* Copyright (c) 2008, Atmel Corporation All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of ATMEL may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL " AS IS " AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
* SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*****************************************************************************/
#include " avr_compiler.h "
#include " port_driver.h "

void Example1( void );
void Example2( void );
void Example3( void );
void Example4( void );


void main( void )
{
Example1();
/*Example2();*/
/*Example3();*/
/*Example4();*/

while(true){

}
}


/*! \brief Getting started example 1.
*
* This function implements the " Basic Digital I/O " example from the
* " Getting Started " section in the application note.
*
* This function will continously read input from 8 switches connected to PORTC
* and output the pin state to 8 LEDs connected to PORTD.
*/
void Example1( void )
{
/* Configure data direction for PORTC and PORTD. */
PORT_SetPinsAsInput( & PORTC, 0xFF );
PORT_SetPinsAsOutput( & PORTD, 0xFF );

/* Continously copy the value from PORTC to PORTD. */
do {
uint8_t temp = PORT_GetPortValue( & PORTC );
PORT_SetOutputValue( & PORTD, temp );
} while (true);
}


/*! \brief Getting started example 2.
*
* This function implements the " Configuring Several Pins in One Operation "
* example from the " Getting Started " section in the application note.
*
* This function configures pins 0-3 on PORTC for Wired-AND with pull-up
* operation.
*/
void Example2( void )
{
PORT_ConfigurePins( & PORTC,
0x0F,
false,
false,
PORT_OPC_WIREDANDPULL_gc,
PORT_ISC_BOTHEDGES_gc );
}


/*! \brief Getting started example 3.
*
* This function implements the " Mapping Real Ports to Virtual Ports " example
* from the " Getting Started " section in the application note.
*
* This function maps PORTC to Virtual port 0 and PORTD to Virtual PORT1,
* and performs the same task as in Example1() using virtual ports.
*/
void Example3( void )
{
/* Map the ports. */
PORT_MapVirtualPort0( PORTCFG_VP0MAP_PORTC_gc );
PORT_MapVirtualPort1( PORTCFG_VP1MAP_PORTD_gc );

/* Configure VPORT0 as input and VPORT1 as output. */
PORT_SetDirection( & VPORT0, 0x00 );
PORT_SetDirection( & VPORT1, 0xFF );

/* Continously copy the value from PORTC to PORTD using the
* virtual ports.
*/
do {
uint8_t temp = PORT_GetPortValue( & VPORT0 );
PORT_SetOutputValue( & VPORT1, temp );
} while (true);
}


/*! \brief Getting started example 4.
*
* This function implements the " Configuring an I/O Pin for Interrupt Generation "
* example from the " Getting Started " section in the application note.
*
* This function configures PORTC interrupt0 as a medium level interrupt,
* triggered by the rising edge of PC0. The interrupt service routine toggles
* the output on PORTD.
*/
void Example4( void )
{
/* Configure PC0 as input, triggered on rising edge. */
PORT_ConfigurePins( & PORTC,
0x01,
false,
false,
PORT_OPC_TOTEM_gc,
PORT_ISC_RISING_gc );

PORT_SetPinsAsInput( & PORTC, 0x01 );

/* Configure PORTD as output with the pattern 0x55. */
PORT_SetPinsAsOutput( & PORTD, 0xFF );
PORT_SetPins( & PORTD, 0x55 );

/* Configure Interrupt0 to have medium interrupt level, triggered by pin 0. */
PORT_ConfigureInterrupt0( & PORTC, PORT_INT0LVL_MED_gc, 0x01 );

/* Enable medium level interrupts in the PMIC. */
PMIC.CTRL |= PMIC_MEDLVLEN_bm;

/* Enable the global interrupt flag. */
sei();
}


/*! \brief Interrupt service routine for Example4()
*
* When initialized using Example4(), this ISR is called on every rising edge
* on PC0.
*/
ISR(PORTC_INT0_vect)
{
PORT_TogglePins( & PORTD, 0xFF );
}


xMega_official_drivers_and_examples.rar > readme.html

Code Documentation Redirecting


xMega_official_drivers_and_examples.rar > XMEGA Watchdog Timer.pdf

AVR1310: Using the XMEGA Watchdog Timer
Features
o Watchdog timeout programmable through fuses
o Watchdog settings lockable through fuses
o Watchdog with normal and window mode
Normal mode:
Programmable timeout period between 8 ms and 8 seconds
Window mode:
Programmable "closed window" period between 8 ms and 8 seconds
Total timeout period between 16 ms and 16 seconds, using window mode
o Example source code
Initialization of normal and window mode operation
Disabling and reconfiguration of Watchdog

8-bit
XMEGA
Microcontrollers
Application Note

1 Introduction
Watchdog Timers are used to ensure that a system can recover from unforeseen
failures in firmware or hardware. The Watchdog Timer will, if used correctly, be
able to detect abnormalities in the program execution and respond by resetting the
MCU. This brings the MCU to a well-defined and known state from where normal
operation can be resumed.
The XMEGA(TM) AVR(R) family offers a very robust internal watchdog: Ordinary
integrated Watchdog Timers often use the CPU clock as clock source, while the
XMEGA Watchdog Timer's clock source is independent from the CPU clock. This
means that failure of the main clock would not affect the Watchdog Timer
operation.
Further, the XMEGA Watchdog Timer does not only offer the "normal mode",
where the Watchdog Timer must be reset before a given timeout period. It also
offers a "window mode" where the Watchdog Timer only can be reset within a
limited period. In window mode, if the Watchdog Timer is reset too early (or too
late), a system reset is triggered.
More information about using watchdog timers can be found in application note
AVR132.

Rev. 8034B-AVR-04/09

2 Theory of operation
Before the XMEGA Watchdog Timer can be discussed it is important to get a few
terms clear:
o The Watchdog Timer (WDT) is the peripheral module that can be configured to
generate a system reset if the timer is reset too early or too late according to
specified timeout periods. The timer value itself cannot be read or written, only
reset.
o A Watchdog Timer Reset (WDT reset) is when the timer in the WDT is cleared
(aka reset). This will make the timer start counting from zero again, and thus
restart the timeout period.
o A "system reset" is when the AVR microcontroller is reset, resetting the CPU and
I/O register to default values, and restart program execution from address 0x0000
(or boot section). The WDT can cause a system reset if it times out or, in window
mode, if the WDT is reset too early.

2.1 Normal Mode
The WDT can be used in normal mode, which is when a single timeout period is set
for the WDT; if the WDT is not reset before the timeout occurs the WDT will cause a
system reset. Figure 2-1 illustrates this. The "Open" range along the "WDT Count"
axis indicates that the WDT can be reset at any time before the WDT timeout (TOWDT)
expires (please refer to section 2.5 for exact timing details), as opposed to when
using the window mode where the WDT cannot be reset until after the Watchdog
Window timeout (TOWDTW) expires.
Figure 2-1. Timely and late (missing) Watchdog Timer reset in normal mode.
System Reset
WDT Count
Timely WDT
Reset

Open

TOWDT = 16

WDT Timeout

5

2

10

15

20

25
30
TOWDT

35

t [ms]

AVR1310
8034B-AVR-04/09

AVR1310
2.2 Window Mode
When the WDT is used in window mode, it uses two different timeout periods, a
"closed" window timeout period (TOWDTW) and the normal WDT timeout period
(TOWDT). The first defines a period from 8 ms to 8s where the WDT cannot be reset: if
the WDT is reset in this period the WDT will cause a system reset. The normal WDT
timeout period, which is also 8 ms to 8s, defines the duration of the "open" period, in
which the WDT can (and should) be reset. The open period will always follow the
closed period, and thus the total duration of the WDT timeout is the sum of the
windowed and the normal timeouts. The closed and open periods used in window
mode are illustrated in Figure 2-2.
Figure 2-2. Timely and early Watchdog Timer reset in Window mode.
WDT Count
Timely WDT
Reset
Open

TOWDT = 8

Early WDT Reset

Closed

TOWDTW = 8

System Reset
5

10

15
20
TOWDTW

25
30
TOWDT

35

t [ms]

2.3 Timer Clock
The WDT is clocked from an internal 1kHz ultra low power (ULP) RC oscillator. This
oscillator can also be used by the RTC timer and is used by the Brown Out Detection
circuit - if used in sampled mode. If any of these modules are configured to used the
ULP oscillator the oscillator is running. The additional current consumption by
enabling additional modules using the ULP RC oscillator is very low. Please refer to
the datasheet for more information about power consumption.
It is important to be aware that the clock for the WDT is not very accurate. This is due
to the fact that the oscillator is designed to draw very little power to be able to use the
WDT even in long-life battery powered applications. The downside of low power
oscillators is low accuracy. The typical accuracy of the clock for the WDT is +/-30%
(please refer to datasheet for exact information on accuracy of the clock). This means
that one have to be aware that the clock frequency can vary from one device to
another. When designing software which uses the WDT the device-to-device variation
must be kept in mind to ensure that the timeout periods used are valid for all devices,
and not only the ones used in the lab during development.
Further, one has to consider that the clock source may vary over temperature and
supply voltage - though this variation is significantly less than the +/-30% device-todevice variations. Please refer to the datasheet for more information on this topic.

3
8034B-AVR-04/09

2.4 Timeout Periods
The WDT offers a wide range of timeout periods, from 8 ms to 8 seconds (please
refer to datasheet for details). The timeout period for the WDT period and the WDT
window period is controlled by respectively the WDT Period (PER) bits and the WDT
Window Period (WPER) bits located in the WDT Control Register (CTRL) and WDT
Window Control Register (WINCTRL).
The WDT is reset when a valid write access to CTRL or WINCTRL register is
performed (refer the description of the timed sequence required to write the control
registers found in section 2.6.2).

2.5 Digital timing of the Watchdog Timer
The WDT is operating in a different clock domain than the CPU and synchronization
between the two domains should be considered when using the WDT.
It takes up to 2-3 WDT clock cycles to configure the WDT: when configuration
settings are written to the WDT control registers (CTRL and WINCTRL), the new
configuration becomes effective from the next WDT clock edge (rising edge of WDT
clock in Figure 2-3), i.e. between 2 and 3 ms after the configuration is written. This
means that the initial timeout period is up to 3 ms longer than the specified timeout. If
the specified timeout is 8 ms, the actual timeout will be between 10 and 11 ms. This
will mainly be relevant when using window mode and short timeout periods. This
characteristic is not unique to the WDT; all asynchronous timers operate in this way
due to synchronization between clock domains.
Again, the WDT is reset when a valid write access to the control registers is
performed (please refer to section 2.6.2 for further details).
Figure 2-3. Digital timing of the XMEGA Watchdog Timer.
System Reset
WDT count

WDT timeout

Execution of WDR instruction
WD timer reset

8

TOWD = 8

7
6

6

5

5

4
3
2

4
3

TWDT_Reset

2

1

1

0
T0

0
5

10

15

t [ms]

WDT clock

4

AVR1310
8034B-AVR-04/09

AVR1310
Another timing characteristic that one has to be aware of is that the duration between
the execution of the Watchdog Timer Reset instruction (WDR) and the actual
resetting of the WDT, is also subject to synchronization between clock domains: the
WDT is reset on the third WDT clock edge after the WDR is executed (see TWDT_Reset
in Figure 2-3), which means that the WDT is reset between 2 ms and 3 ms after the
WDR instruction is executed. Considering the use of a 8 ms timeout period, one
therefore have to realize that the first WDR instruction should be executed within 5
ms after enabling the WD. Taking the +/-30% accuracy of the ULP oscillator into
account as well, the WDR instruction must be executed within 3.5 ms or less. The
interval between subsequent WDR instructions should be 4.9 ms or less (8 ms - 1 ms
uncertainty - 30% oscillator uncertainty). The effect of this synchronization is
minimized when the timeout period increases. This should however provide a strong
hint that use of window mode in combination with short timeout periods requires very
strict timing.
If the WDT causes a system reset, e.g. by timing out, the system reset occurs on the
first following WDT clock edge (see Figure 2-3). This means that the system reset
occurs 1 ms after the WDT timeout period has expired. This should normally not
cause any problem, but it is useful to know if trying to measure the WD timeout period
by monitoring the logic level of a pin. A better way to determine the actual frequency
of the WDT clock is to use the XMEGA Real Time Clock timer, which can also be
clocked by the ULP oscillator.
All of the above-mentioned conditions apply to both the WDT normal mode timeout
and the WDT window mode timeouts.

2.6 Watchdog enabling and timing configuration
The WDT can be enabled and configured in two ways, either through fuses, which
makes the AVR load the specified settings before leaving system reset. Alternatively,
the WDT can be enabled at run-time, which means that the firmware writes the
desired settings to the WDT control registers at run-time.
2.6.1 Fused enabling of the Watchdog
The WDT can be initialized automatically during system reset by writing the fuses
corresponding to the normal mode and to window mode. These fuses will determine
both the Watchdog Timer timeout period and the duration of the WDT closed window,
and can also be used to enable the WDT at start-up. Please refer to the datasheet for
more information about the fuses controlling the WDT.
Note that the window mode cannot be enabled through fuses, as it is an advantage to
be able to enable it run-time to ensure proper timing when using window mode.
To provide maximum protection, it is possible to program the Watchdog Lock
(WDLOCK) fuse, which ensures that the WDT cannot be disabled run-time - neither
accidentally, nor on purpose. This can be desirable if considering that a system failure
may have a duration in time that for some reason impairs the enabling of the
Watchdog at run-time (in the firmware).

5
8034B-AVR-04/09

Figure 2-4. State chart for enabling WD through fuses.
System initialization,
WDT config and enabling
(hence CPU is active)

System
Reset

Timely execution of
WDR instruction

WDT Active
(WDT
counting)

WDT Reset

Resume counting
WDT timeout or
Early execution of WDR

2.6.2 Run-time enabling of the Watchdog Timer
In some applications it can be required to be able to disable the WDT to reduce the
power consumption in sleep mode to an absolute minimum. This can be the case in
long life battery powered applications. If it is desirable to use the WDT in periods
where the CPU is active, but not in sleep modes, it is convenient to be able to enable
and disable the WDT, though this may reduce the protection offered by the WD. Note
however that if other modules are using the ULP oscillator in sleep mode (BOD and
RTC) the additional current consumption spend by leaving the WDT on is very low.
To enable the WDT in run-mode or to change the timeout period a timed sequence
must be used: The timed sequence involved the Configuration Change Protection
register (CCP), which controls access to certain registers. After writing the signature
0xD8 to the CCP, the WDT can be reconfigured within the next four instruction
cycles. During these four instruction cycles the global interrupts are automatically
disabled to ensure that the timed sequence is not invalidated by an interrupt. Note
that the timeout is given in instruction cycles, and not clock cycles, a DMA transfers
will therefore not affect the timing: DMA transfers are not counted as instruction
cycles - only instructions executed by the CPU are counted.
Within four instruction cycles after writing the 0xD8 signature to the CCP, the WDT
control registers (CTRL and WINCTRL) can be modified. The procedure for doing so is
specified in the datasheet, and examples how to do it can be found in the code
example for this application note.
Note that it is not possible to change the WDT or the WDT window mode
configuration while the WDLOCK fuse is set, but it is possible to enable/disable the
WDT window mode.

6

AVR1310
8034B-AVR-04/09

AVR1310
Figure 2-5. State chart for enabling WDT run-time.
WDT configuration and
enabling
Timely execution of
WDR instruction

CPU Active
(WDT
Disabled)

System initialization
(CPU in Reset)

WDT Active
(WDT
counting)

System
Reset

WDT Reset

Resume counting

WDT timeout or
Early execution of WDR

2.7 Intended use of the Watchdog
A WDT is meant to save the day if the system has an unforeseen failure that is not
handled in firmware or hardware, or if an external disturbance causes the system to
fail. A well-used WDT would be able to generate a system reset, which the end-user
will not or will barely notice. Seeing this in contrast to a product that needs power
cycling every now and then to return to an operational state, the difference should be
apparent: Whether the end-user is satisfied with the product or not.
In general it is recommended to issue a WDT reset from somewhere in the main loop
of the firmware. Do not reset the WDT in interrupt service routines - unless the
interrupt routine checks a series of flags that confirms correct execution of various
parts of the firmware. If these simple rules are followed, the WDT is hard to misuse.
The WDT window mode is a bit more challenging to use than the normal mode, as it
involves more strict control of the WDT reset timing. In window mode the WDT should
be reset from somewhere within the main loop, never in interrupt service routines, as
this would impair the closed window protection: Because the closed window defines
the minimum expected duration of the main loop (or subsections of the main loop), it
can be used to catch cases where parts of the main loop code is not executed, or
cases where early exit from function calls happens. An example could be that some
algorithm or other software failure causes an operation to finish too quickly. For
instance, the expected duration of writing a value to the EEPROM is 4 ms, but if it
completes in a few microseconds (inspection of a flag failed?), a subsequent WDT
Reset would arrive too early. Another example could be corruption of the return stack
or stack pointer itself, causing abnormal program execution.
Another case where the window mode offers good protection is if the code execution
is stuck in a loop where the WDR instruction is executed repeatedly: if the WDT reset
occurs more frequently than anticipated the WDT will "assume" that a failure has
occurred and reset the system to bring it back to an operational state.

7
8034B-AVR-04/09

3 Examples
This application note includes a source code package with a basic Watchdog Timer
driver implemented in C.
Note that this Watchdog Timer driver is not intended for use with high-performance
code. It is designed as a library to get started with the XMEGA Watchdog Timer. For
timing and code space critical application development, you should access the
Watchdog Timer registers directly. Please refer to the driver source code and device
datasheet for more details.

3.1 Files
The source code package consists of three files:
o wdt_driver.c - Watchdog Timer driver source file
o wdt_driver.h - Watchdog Timer driver header file
o wdt_example.c - Example code using the driver
For a complete overview of the available driver interface functions and their use,
please refer to the source code documentation.

3.2 Doxygen Documentation
All source code is prepared for automatic documentation generation using Doxygen.
Doxygen is a tool for generating documentation from source code by analyzing the
source code and using special keywords. For more details about Doxygen please visit
http://www.doxygen.org. Precompiled Doxygen documentation is also supplied with
the source code accompanying this application note, available from the readme.html
file in the source code folder.

8

AVR1310
8034B-AVR-04/09

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8034B-AVR-04/09


xMega_official_drivers_and_examples.rar > XMEGA Timer_Counter.pdf

AVR1306: Using the XMEGA Timer/Counter
Features
o True 16 bit operation
o Double buffered timer period setting
o 4 (2) compare or capture channels per timer
- 4 channels on each Timer 0
- 2 channels on each Timer 1
- Double buffered
o 32 bit operation with 32 bit input capture by timer cascading
o Event counter
o Timer overflow and error interrupts (and events)
o Input capture interrupts (and events)

8-bit
Microcontrollers
Application Note

1 Introduction
The XMEGA(TM) Timer/Counter modules are true 16-bit Timer/Counters with Input
Capture and Pulse Width Modulation (PWM) functionality.
This application note gives an introduction on how to use the XMEGA
Timer/Counter modules for timing, Input Capture and PWM.

Rev. 8045A-AVR-02/08

2 Definitions
The definitions listed in Table 2-1 will be used throughout this document.
Table 2-1. Definitions used in this document.
Name

Description

BOTTOM

The Timer/Counter reaches the BOTTOM when it becomes zero.

MAX

The Timer/Counter reaches it MAXimum when it becomes 0xFFFF.

TOP

The Timer/Counter reaches the TOP when it becomes equal to the highest value
in the count sequence. The TOP value can be equal to the period register
(PER[H:L]) or Compare or Capture register A (CCA[H:L]), depending on the
selected Waveform Generation Mode (WGM).

UPDATE

The Timer/Counter signalizes an update when it reaches BOTTOM or TOP
depending on the selected waveform generation mode (WGM).

3 Module Overview
The XMEGA Timer/Counter (TC) modules are 16-bit Timer/Counters with input
capture and compare match with optional output to I/O pin. Typical applications
include:
o
o
o
o
o
o

Timing.
Periodic interrupt/event generation.
Pulse Width Modulation.
Event time stamping.
Event counting.
Signal parameter measurements (Period, duty cycle, etc.).

3.1 Timer/Counter Variants
An XMEGA TC module is related to an I/O port through the I/O pins it can control with
the output compare module. The naming of the TC modules reflects the I/O port it is
connected and the available features for that Timer/Counter. Each TC module has a
name that follows the form: TCxn. TC is short for Timer/Counter, x indicates the port it
is connected to and n is the TC number within PORTx. As an example, TCD0 is
Timer/Counter 0 connected to PORTD.
Timers are available on PORTC, PORTD, PORTE or PORTF, if available on device.
Timer0 on each port has 4 compare or capture channels, while Timer1 has 2
compare or capture channels. Figure 3-1 shows how the output compare channels
are connected to the associated I/O port. Timer0 has its outputs connected to pins 03 within the port, while Timer1 is mapped to pins 4 and 5.

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Figure 3-1. Output compare to I/O port pin mapping
PORTx
CCA

Px0

CCB

Px1

CCC

Px2

CCD

Px3

CCA

Px4

CCB

Px5

TCx0

TCx1
Px6
Px7

3.2 Clock Sources
The available clock source selections for the XMEGA TC modules are listed in Table
3-1.
Table 3-1. XMEGA Timer/Counter clock sources.
Symbol

Clock selection

TC_CSEL_OFF_gc

TC off (no clock selected)

TC_CSEL_DIV1_gc

fCLK,SYS

TC_CSEL_DIV2_gc

fCLK,SYS / 2

TC_CSEL_DIV4_gc

fCLK,SYS / 4

TC_CSEL_DIV8_gc

fCLK,SYS / 8

TC_CSEL_DIV64_gc

fCLK,SYS / 64

TC_CSEL_DIV256_gc

fCLK,SYS / 256

TC_CSEL_DIV1024_gc

fCLK,SYS / 1024

TC_CSEL_EV0_gc

Event channel 0

TC_CSEL_EV1_gc

Event channel 1

TC_CSEL_EV2_gc

Event channel 2

TC_CSEL_EV3_gc

Event channel 3

TC_CSEL_EV4_gc

Event channel 4

TC_CSEL_EV5_gc

Event channel 5

TC_CSEL_EV6_gc

Event channel 6

TC_CSEL_EV7_gc

Event channel 7

3.3 Interrupts
Interrupts can be generated in the following situations:

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o Timer overflow.
o Timer error (Input capture data lost because input capture buffer is full).
o Compare or capture. Separate interrupts for each channel.

3.4 Period Setting
Each TC module has a period register (PER[H:L]) that controls the TOP value of the
counter (except in frequency generation mode).
The PER[H:L] register is double buffered through the PERBUF[H:L] register. Double
buffered registers are covered in section 3.7.
The PER[H:L] register is automatically initialized to 0xFFFF after a reset.

3.5 Capture or Compare Channels
Each TC module has two or four capture or compare channels. The channels can be
set up for either input capture or compare match. It is not possible to use the same
TC module for both input capture and compare match at the same time. Input capture
can be used to time stamp event, measuring waveform parameters like frequency or
duty cycle. The compare match feature can be used to generate interrupts or events
at certain time points, or for PWM/waveform generation.
The compare or capture channels consist of a set of 16-bit registers named CCx[H:L],
where x indicates the channel. Timer0, with 4 channels, has CCA[H:L], CCB[H:L],
CCC[H:L] and CCD[H:L], while Timer1 has CCA[H:L] and CCB[H:L]. In addition, each
CCx[H:L] register has an associated buffer register CCxBUF[H:L]. Double buffered
registers are covered in detail in section 3.7.
When used for input capture, the value of the PER register determines how input
capture values are interpreted. If bit 15 of PER is set to one, the entire 16 bit counter
value is stored in the capture buffer. If bit 15 of PER is zero, the event polarity is
stored in bit 15 in the capture buffer. This can be used to measure frequency
parameters like duty cycle using only one input pin and one capture channel.

3.6 Event Input Selection
The TC input capture system uses the XMEGA event system to trigger an input
capture. Refer to application note AVR1001 for more information about the XMEGA
event system.
When the TC is used for input capture, all enabled input capture channels must be
associated with an event channel. The EVSEL[3:0] bits of the CTRLD register select
the event channels that are associated with the input capture channels. EVSEL3 must
be 1 to select an event source. EVSEL[2:0] selects between the 8 event channels.
The event channels associated with the different channels cannot be selected
individually. Table 3-2 shows the mapping between global event channels and input
capture channels when EVSEL3 = 1 and EVSEL[2:0] = N. The "%" is the modulo
operator. Note that when a set of event channels have been selected for the TC, this
does not mean that these event channels are used exclusively by the TC. The TC
simply "listens" to the selected channels and is able to receive events on these event
channels.

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Table 3-2. Event channel to input capture channel mapping.
Input capture channel

Global event channel

A

N

B

(N + 1) % 8

C (If available)

(N + 2) % 8

D (If available)

(N + 3) % 8

Example 1:
EVSEL3 = 1 and EVSEL[2:0] = 0 means that input capture channels A, B, C and D
are triggered by event channels 0, 1, 2 and 3 respectively.
Example 2:
EVSEL3 = 1 and EVSEL[2:0] = 6 means that input capture channels A, B, C and D
are triggered by event channels 6, 7, 0 and 1 respectively.
If the event source is subject to noise, e.g. caused by the bouncing of an external
switch, it is possible to enable digital filtering on the event channel. See application
note AVR1001 for more information on the event system and its digital filtering
capabilities.

3.7 Double Buffered Registers
The PER[H:L] and CCx[H:L] registers in the TC modules are double buffered. They
have dedicated buffer registers named PERBUF[H:L] and CCxBUF[H:L].
Using the PER[H:L] register as an example: when writing to PER[H:L] directly, the
value will be updated immediately. If the value is instead written to PERBUF[H:L], the
value of PER[H:L] will not be updated instantly, but instead transferred from
PERBUF[H:L] on the next UPDATE condition. Each buffer register has a related
"buffer valid" flag in the CTRLE register. The buffer valid flag is set when a new value
is written to the corresponding buffer register. The flag is cleared when the buffer
register is copied to its destination. This ensures that only new values are copied.
It is also possible to lock the automatic update from buffer registers. This enables
simultaneous updates of several registers at one update condition. Setting the Timer
Lock Update (LUPD) bit in the CTRLE register enables update locking.
When the TC module is used for PWM, the buffering is typically used to make sure
that the duty cycles are not altered in the middle of a PWM period, and to synchronize
changes to all PWM channels. New compare/TOP values are typically written to the
buffer registers instead of writing directly to the CCx registers. This way, all PWM
channels can be updated at the same time (on the UPDATE event).
In Input Capture mode, the input capture values are double-buffered. A new input
capture-value is first put in the CCxBUF[H:L] register. Values stored in CCxBUF[H:L]
are transferred to CCx[H:L] if the CCIFx flag is not set. The CCIFx flag is cleared
automatically when CCx[H:L] is read. In practice, this means that the user only needs
to read the CCx[H:L] register, while the rest is handled automatically.

3.8 Modes of Operation
The TC has six different modes of operation:

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o
o
o
o
o
o

Normal mode.
Frequency Generation mode.
Single Slope PWM.
Dual Slope PWM, overflow on TOP.
Dual Slope PWM, overflow on TOP and BOTTOM.
Dual Slope PWM, overflow on BOTTOM.

3.8.1 Normal Mode
In Normal Mode, the counter will count in the direction set by the DIR bit in CTRLF for
each clock until it reaches TOP set by PER[H:L] or BOTTOM (zero). When TOP is
reached when up-counting the counter will be set to zero when the next clock is
given. If the TC is down-counting the value will wrap around to the value in PER[H:L]
after reaching BOTTOM.
Figure 3-2. Normal mode with period setting.

Timer value

TOP
TOP
TOP

Time
As shown in Figure 3-2, changing the counter value while the counter is running is
allowed. The write access has higher priority than count, clear, or reload and will be
immediate. However, if the value written is outside the BOTTOM-TOP boundary the
counter either has to count down until TOP is reached or count up until wraparound
(passing MAX) for the timer to re-stabilize to the period time.

This mode of operation must be used when using the Timer/Counter for Input
Capture.
3.8.2 Frequency Generation Mode
There is little difference between the frequency waveform generation mode (FRQ)
and the normal mode of operation. For FRQ the period (T) is controlled by the
CCA[H:L] register instead of PER[H:L], which in this case is not in use. In addition the
Waveform Generation (WG) output is toggled on each compare match between
CNT[H:L] and CCA[H:L] as shown in Figure 3-3.

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AVR1306
Figure 3-3. Frequency Generation Mode
Period (T)

DirectionChange

CNTwritten

MAX
" update "

TCNT

TOP

BOT

WG Output

The waveform generated will have a maximum frequency of fclk/2 when CCA[H:L] is
set to zero (0x0000). The waveform frequency is defined by Equation 3-1.
Equation 3-1. Frequency Calculation, Frequency generation mode

f FRQ =

f CLK
2 ? N (CCA + 1)

Where N represents the TC clock prescaler.
The Overflow Status Flag (OVFIF) or Compare A Flag (CCAIF) can be used to
generate interrupts. If enabled, the interrupt handler routine can be used for updating
CCA[H:L] to change the output frequency.
3.8.3 Single Slope PWM Mode
As Figure 3-4 shows, in this mode of operation the counter counts from BOTTOM to
TOP then restarts from BOTTOM. The waveform generator output is set on the
compare match between the count and compare registers, and cleared at TOP.
Figure 3-4. Single slope PWM
Period (T)

CCx=BOT

CCx=TOP

" update "
" match "

M AX
TOP

CNT
CCx

BOT

WG Output

The single-slope Pulse Width Modulation (PWM) provides twice the PWM frequency
compared to dual-slope PWM. The high frequency makes this mode well suited for
power regulation, rectification, and DAC applications. High frequency allows
physically small sized external filtering components, which reduces total system cost.
The period register (PER[H:L]) defines the PWM resolution. The minimum resolution
allowed for this module is 2-bit (PER[H:L]=0x0003), and maximum resolution is 16-bit
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(PER[H:L]=MAX). Equation 3-2 can be used to calculate the exact bit resolution for
single-slope PWM.
Equation 3-2. PWM Resolution, Single Slope PWM Mode

R PWM _ SS = log 2 (PER + 1)

The PWM base frequency depends on the period setting (PER[H:L]), system clock
frequency, and clock prescaler. The PWM base frequency can be calculated using
Equation 3-3.
Equation 3-3. Frequency calculation, Single Slope PWM Mode

f PWM _ SS =

f CLK
N (PER + 1)

Where N represents the TC clock prescaler.
The Overflow Status Flag (OVFIF) or Compare Flag (CCxIF) can be used to generate
interrupts. If enabled, the interrupt service routine can be used for updating the period
and compare buffer values.
3.8.4 Dual Slope PWM Modes
The counter behavior in dual-slope operation is shown in Figure 3-5. The counter
counts repeatedly from BOTTOM to TOP and then to BOTTOM. When the counter
hits BOTTOM or TOP, the counter changes direction immediately, holding the
BOTTOM and TOP values for only one TC clock cycle. The current counting direction
can be determined by inspecting the DIR flag in CTRLF.
The Waveform Generation (WG) output is set on BOTTOM and cleared on compare
match. The output duty cycle is thus proportional to the compare value.
Figure 3-5. Dual slope PWM
Period (T)

CCx=BOT

CCx=TOP

" update "
" match "

M AX
CCx

CNT

TOP

BOT

WG Output

The dual-slope PWM result in a lower operating frequency at equal resolution
compared to the single-slope PWM mode.
The period register (PER[H:L]) defines the PWM resolution. The minimum resolution
allowed for this module is 2-bit (PER[H:L]=0x0003), and maximum resolution is 16-bit
(PER[H:L]=0xFFFF). Equation 3-4 can be used for calculate the exact resolution for
dual-slope PWM.

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AVR1306
Equation 3-4. PWM Resolution, Dual Slope PWM Mode

R PWM _ DS = log 2 (PER + 1)

The PWM base frequency depends on the period setting (PER[H:L]), system clock
frequency and clock prescaler and can be calculated using Equation 3-5.
Equation 3-5. Frequency calculation, Dual Slope PWM Mode

f PWM _ DS =

f CLK
2 ? N ? PER

Where N represents the TC clock prescaler.
The Overflow Status Flag (OVFIF) or Compare Flag (CCxIF) can be used to generate
interrupts. If enabled, the interrupt service routine can be used for updating the period
and compare buffer values.

3.9 Timer/Counter Commands
The CMD[1:0] bits in CTRLFSET are used to issue special commands to the TC.
These are described below.
3.9.1 Force Update
The "Force update" command is used to force an UPDATE condition. Buffer registers
are copied to their destination when the UPDATE conditions are met. Issuing this
command forces an UPDATE condition regardless of the counter value. This can be
used to update both the period and compare registers at the exact same time. In input
capture mode, the "Force update" command only has effect on the PERBUF/PER
registers. See section 3.7 for more information about double buffered registers.
3.9.2 Force Restart
The "Force restart" command clears the CNT[H:L] registers and the direction bit to its
reset value.
3.9.3 Force Hard Reset
The "Force hard reset" command puts all registers in that TC instance back to their
reset state. For safety reasons, the TC clock selection must be set to OFF for this
command to have any effect.

4 Accessing 16-bit Registers
Since the XMEGA has a bus width of 8 bits, 16-bit registers are accessed as two 8-bit
registers. All accesses to 16-bit registers are performed using a hardware-controlled 8
bit temporary register to ensure concurrent update of the high and low byte registers.
Each Timer/Counter has one dedicated temporary register, TEMP, that is used for
this purpose. The TEMP register is shared for all 16-bit accesses in that TC module.
Usage of the TEMP register is automatically handled when the correct byte access
order is used, but it is important to understand the mechanism to avoid corruption of
registers.
Note that on the XMEGA, the byte order for multi-byte access is always from the least
significant byte to the most significant byte.
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4.1 16-bit Read
Figure 4-1 illustrates how to perform a 16-bit read of CNT, and what happens
internally:
1. Read CNTL. This will cause the contents of CNTH to be transferred to TEMP in the
same clock cycle.
2. Read CNTH. This will automatically cause the contents of TEMP to be read instead
of the current value of CNTH.
The result is a snapshot of the 16-bit CNT[H:L] value at the time CNTL was read.
Figure 4-1. 16- bit read access.
CNTH
1

CNTL

TEMP

R(n+1)

2

Rn

CNTH

CNTL

TEMP

R(n+1)

Rn

4.2 16-bit Write
Figure 4-2 illustrates how to perform a 16-bit and what happens internally:
1. Write CNTL. This will cause the TEMP register to be updated with the new value
for CNTL.
2. Write CNTH. This will cause CNTL to be updated with the contents of the TEMP
register at the same time as CNTH is updated.
The result is that the 16-bit CNT[H:L] value is updated in the same clock cycle.

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AVR1306
Figure 4-2. 16-bit write access.
CNTH
1

CNTL

TEMP

R(n+1)

2

Rn

CNTH

CNTL

TEMP

R(n+1)

Rn

4.3 Implications of Having a Shared TEMP Register
Since one TEMP register is shared for all 16-bit registers within one TC module, there
is a possibility of register corruption if the necessary measures are not taken.
Consider the following scenario: One part of the program running in the foreground
loop is about to perform a write to CNT[H:L]. The foreground task has just finished a
write to CNTL, resulting in the TEMP register holding the low byte temporarily. Before
the foreground loop is able to write to CNTH, an interrupt is triggered. This interrupt
service routine (ISR) performs a write to the 16-bit PER[H:L] register. During this
process, the TEMP register is used for the low byte of PER[H:L]. When the ISR
returns, the contents of TEMP are corrupted. The foreground task completes the write
operation by writing to CNTH, causing the corrupted low-byte to be transferred from
TEMP to CNTL.
There are two possible solutions to this problem:
1. Make sure that every 16-bit access is performed as an atomic operation by
disabling interrupts during the access. Since the XMEGA is equipped with a multilevel interrupt controller, this does not only apply to the foreground code, but also
low and medium level interrupts.
2. If an ISR can interrupt another 16-bit access in the same TC module, it must store
the contents of the TEMP register before the 16-bit access is performed, and
restore the TEMP register again before leaving the ISR.

4.4 16-bit Access in On-Chip Debug Stopped Mode
When the XMEGA is in On-Chip Debug (OCD) stopped mode ('break' in AVR Studio),
the TEMP register is bypassed. It is thus possible to access both the high and low
byte of 16-bit registers directly and there will be no automatic transfers of data to the
TEMP register. For debugging purposes the TEMP register itself can also be
read/written during OCD stopped mode.
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5 Using two 16-bit Timer/Counters as one 32-bit Timer/Counter
It is possible to use the event system to cascade two 16-bit Timer/Counter modules
into one 32-bit Timer/Counter with 32-bit input capture functionality.

5.1 Cascading two 16-bit Timer/Counter Modules
All Timer/Counter modules have the option of being clocked by one of the event
channels. To cascade two 16-bit TC modules and thus get a 32-bit TC, the overflow
event from the low word TC must be routed through the event system and used as
the clock for the high word TC. Figure 5-1 shows how this is done using TCC0 as low
word and TCC1 as high word, through event channel 0. Event channel 0 is configured
through the EVSYS.CH0MUX register to use the TCC0 overflow event as event
source. The CLKSEL bits in TCC1.CTRLA are configured to use event channel 0 as
clock source. The result is that TCC1 will increase by one each time TCC0 overflows.
In effect, this creates a 32-bit TC. Note that any two TC modules can be cascaded in
this way.
Figure 5-1. Cascading two 16-bit Timer/Counter modules.
OVF

TCC1H

TCC1L
Clock
signal for
high word
T/C

High word
EVMUX0

Overflow

OVF

TCC0H

TCC0L

Low word

5.2 Accessing the 32-bit Value
When reading the cascaded TC, the 32-bit value must be manually assembled from
the two 16-bit parts. However, since there is no temporary register for the 32-bit
counter value, the high and low words will not be read in the same clock cycle. The
low word TC might overflow just after it has been read. This would lead to an incorrect
value being read, since the overflow of the low word would lead the high word to be
increased by 1. One way to avoid this is to stop the low word TC while reading the 32bit count value. If stopping the TC is not acceptable, the best solution is to use a 32bit input capture.
The same problems can occur when a new value is written to the cascaded TC. The
safest way to write a new 32-bit value is to stop the TC, write the value and start the
TC again.

5.3 Using 32-bit Input Capture
A 32-bit Timer/Counter can be set up to perform 32-bit input capture. First, a 32-bit
Timer/Counter must be set up as described in section 5.1. Both TCs are configured
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AVR1306
for input capture, with the same event channels as capture sources. However, there
is a one clock-cycle delay in the propagation of the overflow bit from the low word TC
to the high word TC. This means that it is necessary to delay the event to the high
word TC to ensure the correct input capture value. To delay the event, the EVDLY bit
in the CTRLD register must be set.
It is possible to use the EVSYS.STROBE register in the event system to manually
trigger an event on any of the available event channels. This can be used as an
alternative to reading the TC directly from software.

6 Getting Started
This section describes the basic steps for getting up and running with the
Timer/Counters in different configurations. Each of the examples listed here are
implemented in the accompanying example source code.

6.1 Basic Timer/Counter Operation
Task: Set up a Timer/Counter for use as a regular timer.
1. Set the PER[H:L] register to control the period/top value of the TC. This sets the
point where the TC wraps around to zero and where the TC overflow
interrupt/event occurs.
2. Start TC by selecting a clock source (CLKSEL in CTRLA).
In this configuration, the current timer value can be read directly from the CNT[H:L]
register. The TC overflow bit indicates whether an overflow has occurred. This bit can
be used to generate interrupts at fixed intervals.

6.2 Using the Input Capture Functionality
Task: Configure TCC0 with Input Capture Channel A enabled. The Input Capture is
triggered by the falling edge of PC0.
3. Configure PC0 for input, triggered on falling edge.
4. Select PC0 as multiplexer input for event channel 0.
5. Configure TCC0 for input capture by setting event source and event action to
"Input capture" in CTRLD.
6. Enable input capture channel A by setting the CCAEN bit in CTRLB.
7. Start the TC by selecting a clock source (CLKSEL in CTRLA).
8. Wait for Input Capture Interrupt Flag A in INTFLAGS to be set.
9. Read input capture value from the CCA[H:L] register.
10.Go to step 6.

6.3 Using Input Capture to Calculate Frequency and Duty Cycle of a Signal
Task: Configure Timer/Counter C0 to measure the frequency and duty cycle of a
signal applied to PC0.
1. Select event source(s). See section 3.6 for details on this.
2. Select event action = input capture.
3. Enable input capture channels (CCENx).
4. Set PER[H:L] to 0x7FFF. (MSB must be cleared)
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5. Start the TC by selecting a clock source.
6. Wait for Input Capture Interrupt Flag A in INTFLAGS to be set.
7. Read input capture value from the CCA[H:L] register into 'thisCapture'.
8. Check bit 15 of 'thisCapture'.
9. If bit 15 of 'thisCapture' is 1
a. Save 'thisCapture' in 'lastRising'
10. else
a. Calculate total period:

6.4 Using a Timer/Counter for PWM Generation
Task: Configure TCC0 for pulse width modulation output with varying duty cycle on
channel A.
1. Configure PC0 for output by setting bit 0 in PORTC.DIR.
2. Select the timer period by setting the PER[H:L] register.
3. Select a waveform generation mode by setting the WGMODE[2:0] bits in
4. Enable Compare Channel A by setting the CCAEN bit in CTRLB.
5. Start the TC by selecting a clock source (CLKSEL[3:0] in CTRLA).
6. Calculate the desired compare value.
7. Write the new compare value to CCA[H:L].
8. Wait for the TC Overflow Flag to be set. (OVFIF in INTFLAGS).
9. Clear the TC Overflow flag.
10.Go to step 6.
Using this sequence, the compare value will be updated once every PWM period.

6.5 Event Counting
Task: Configure TCC0 to count the number of switch presses on PC0, using event
channel 0. Generate interrupt after 5 key presses that toggle PC1.
1. Configure PC0 as input, sense on falling edge.
2. Configure PC1 as output.
3. Select PC0 as multiplexer input for event channel 0.
4. Enable filtering on event channel 0.
5. Set the period of TCC0 to 4 (to generate overflow interrupt after 5 switch presses).
6. Enable TCC0 overflow interrupt at low level.
7. Select event channel 0 as clock source for the TC.
In the TCC0 overflow interrupt service routine, toggle PC1.
In this configuration, the CNT[H:L] register will contain the number of times a switch
connected to PC0 has been pressed. After 5 presses, an overflow interrupt service
handler will be triggered, toggling PC1 while CNT[H:L] wraps around to 0.

14

AVR1306
8045A-AVR-02/08

AVR1306
6.6 Setting up a 32-bit Timer/Counter With Input Capture
Task: Configure TCC0 and TCC1 as one 32-bit TC with input capture channel A
triggered by a falling edge on PC0. Event channel 0 is used for overflow propagation,
while the input capture signal from PC0 is routed through event channel 1.
1. Configure PC0 for input, triggered on falling edge.
2. Select PC0 as multiplexer input for event channel 1.
3. Select TCC0 overflow as multiplexer input for event channel 0.
4. Configure TCC0 and TCC1 for input capture with event channel 1 as trigger.
5. Enable event delay on TCC1. (This will delay the input capture event by one clock
cycle to allow the overflow from TCC0 to propagate to TCC1 before the input
capture happens.)
6. Enable Input Capture Channel A on TCC0 and TCC1.
7. Select event channel 0 as clock source for TCC1 (CLKSEL in CTRLA).
8. Start the TCC0 by selecting system clock as clock source (CLKSEL in CTRLA).
9. Wait for TCC0 (or TCC1) input capture interrupt flag A in INTFLAGS to be set.
10.Read low word input capture value from the TCC0.CCA[H:L] register.
11.Read high word input capture value from the TCC1.CCA[H:L] register.
12.Combine low word and high word to a 32-bit input capture value.
13.Go to step 9.

7 Advanced Features
In this application note, the Timer/Counter modules have been used as standalone
modules. There are some advanced features on the XMEGA that can be used as
"glue" between modules to reduce the amount of code needed and automate parts of
the application.

7.1 DMA Controller
Instead of using polling or interrupt handlers to read input capture values, it is
possible to use the XMEGA DMA controller to move data from one or more registers
to memory buffers or other peripheral modules. This moving of data is done without
CPU intervention and leaves the CPU ready for other tasks; even without executing
interrupt handlers.
For more information, please refer to the device datasheet or the application note
AVR1304.

7.2 Event Generation
The event system has been used in this application note as triggering and clock
sources. The XMEGA TCs can be also be used as event sources for other parts of
the system. The TC modules can generate the following events
o

Timer overflow.

o

Timer error. (Input capture data lost because input capture buffer is full).

o

Separate events for compare or capture on all channels.

15
8045A-AVR-02/08

This allows for complex interaction between different parts of the system,
independent of any code running. The event system is covered more in-depth in the
application note AVR1001.

7.3 Timer/Counter Extension Modules
The Timer/Counter functionality can be extended through Timer/Counter extension
modules, such as the Advanced Waveform eXtension (AWeX) and High-Resolution
(Hi-Res) extension. The extension modules are not covered in this document. Please
refer to application note AVR1311 for more information.

8 Driver Implementation
The included driver has functions that control all the major features of the
Timer/Counter modules (including waveform generation). All functions take a pointer
to a Timer/Counter module as its first argument, so the same functions can be reused
for all Timer/Counter modules on one XMEGA. The driver is written in ANSI(R) C, and
should compile on all compilers with XMEGA support.
Note that this driver is not written with high performance in mind. It is designed as a
library to get started with the XMEGA Timer/Counters and an easy-to-use framework
for rapid prototyping. For time and code space critical application development,
consider replacing function calls with macros or direct access to registers.

8.1 Files
The driver package consists of the following files:
o tc_driver.c - Timer/Counter driver source file
o tc_driver.h - Timer/Counter driver header file
o tc_example.c - Examples using the Timer/Counter driver.

8.2 Doxygen Documentation
All source code is prepared for automatic documentation generation using Doxygen.
Doxygen is a tool for generating documentation from source code by analyzing the
source code and using special keywords. For more details about Doxygen please visit
http://www.doxygen.org. Precompiled Doxygen documentation is also supplied with
the source code accompanying this application note, available from the readme.html
file in the source code folder.

16

AVR1306
8045A-AVR-02/08

Disclaimer

Headquarters

International

Atmel Corporation
2325 Orchard Parkway
San Jose, CA 95131
USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600

Atmel Asia
Room 1219
Chinachem Golden Plaza
77 Mody Road Tsimshatsui
East Kowloon
Hong Kong
Tel: (852) 2721-9778
Fax: (852) 2722-1369

Atmel Europe
Le Krebs
8, Rue Jean-Pierre Timbaud
BP 309
78054 Saint-Quentin-enYvelines Cedex
France
Tel: (33) 1-30-60-70-00
Fax: (33) 1-30-60-71-11

Atmel Japan
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
Tel: (81) 3-3523-3551
Fax: (81) 3-3523-7581

Technical Support
avr@atmel.com

Sales Contact
www.atmel.com/contacts

Product Contact
Web Site
www.atmel.com

Literature Request
www.atmel.com/literature

Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any
intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL'S TERMS AND
CONDITIONS OF SALE LOCATED ON ATMEL'S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED
OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS,
BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS
BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the
contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any
commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in,
automotive applications. Atmel's products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.

(C) 2008 Atmel Corporation. All rights reserved. Atmel(R), logo and combinations thereof, AVR(R) and others, are the registered trademarks or
trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.

8045A-AVR-02/08


xMega_official_drivers_and_examples.rar > XMEGA DAC.pdf

AVR1301: Using the XMEGA DAC
Features
o
o
o
o
o
o

8-bit
Microcontrollers

12 bit resolution
Up to 1 M conversions per second
Continuous drive or sample-and-hold output
Built-in offset and gain calibration
High drive capabilities
Driver source code included

Application Note

1 Introduction
The XMEGA(TM) DAC module is a high-performance Digital-to-Analog converter
capable of conversion rates up to 1 M conversions per second with a resolution of
12 bits. High output driving capabilities, dual sample-and-hold outputs and optional
routing of DAC output to on-board comparator or Analog-to-Digital converter (ADC)
make this a flexible module suitable for a huge range of applications, such as
stereo sound output, high-speed signal generation, calibration and signal
compensation.
This application note describes the basic functionality of the XMEGA DAC with
code examples to get up and running quickly. A driver interface written in C is
included as well.
Advanced use, such as Direct Memory Access (DMA) and the XMEGA Event
System, is outside the scope of this application note. Please refer to the device
datasheets and other relevant application notes for details.

Figure 1-1. DAC Overview
Data Register 0

S/H

1x

S/H

1x

DAC Block
Data Register 1
Event
System

Rev. 8033B-AVR-04/08

2 Module Overview
This section provides an overview of the basic configuration options and functionality
of the DAC. Section 3 then walks you through the basic steps to get up and running,
with register descriptions and configuration details.

2.1 Conversion Triggers
A DAC conversion can be triggered either by (1) the data registers being written to or
(2) from an incoming event from the XMEGA Event System.
When triggered by data write operations, the conversion starts when the high byte
register is updated.
When the Event System is used, the conversion starts when an event arrives, not
when the data registers are updated. This means that the data registers can be
updated several times without triggering any conversion. When the event arrives, the
current value of the data registers are used in the conversion.
Even if software that manually writes to the data registers could achieve fairly good
timing, it is recommended to use a timer base together with events and DMA
transfers for applications that require precise timing. However, for applications that do
not have strict timing requirements or use static output values, it is not necessary to
utilize these advanced features.
Trigger mode is configured with the Trigger Mode bits (CHnTRIG) in Control Register
B (CTRLB). Note that trigger mode can be individually configured for the two
channels. For instance, channel 0 can be triggered on data write while channel 1
uses events.

2.2 Single and Dual Channel Operation
The DAC module contains two data channels with corresponding data registers, but
only one conversion block. The user can choose between using channel 0 as a
continuous-drive output or both channels as two Sample/Hold outputs.
The channel operation mode is configured with the Channel Select bitfield (CHSEL) in
Control Register B (CTRLB).
2.2.1 Single Channel Operation
In single channel operation, the DAC conversion block is always connected to the
data registers and output driver stage of channel 0. Hence the concept continuousdrive output.
Figure 2-1 below shows the DAC in single channel operation mode. Note that the
Sample/Hold stage is bypassed.

2

AVR1301
8033B-AVR-04/08

AVR1301
Figure 2-1. Single Channel Operation
Data Register 0

DAC Block

1x

Event
System

2.2.2 Dual Channel Operation
In dual channel operation, the DAC conversion block is alternately used to convert
values for channel 0 and 1. Sample/Hold blocks are used to keep the output values
between conversions. To be able to maintain a stable output value on the two
outputs, the channels need to be refreshed regularly. Please consult the Electrical
Characteristics section of the datasheet for details on minimum refresh rate. Note that
a higher refresh rate causes higher power consumption. Detail on power consumption
versus conversion rate is also found in the datasheet.
The event system could be used to maintain the required refresh rate, but in most
cases, the event system is used to generate the sample rate instead. If the sample
rate is slower than the refresh rate, the DAC module has an internal refresh interval
generator as well. The automatic refresh interval is configured with the Refresh
Timing Control bitfield (REFRESH) in the Timing Control register (TIMCTRL).
Note that manual conversions or event triggering does not affect the refresh interval.
This means that the channels will be refreshed at constant intervals even if extra
conversions are done in between, caused by for instance a manual update of a data
register. Figure 2-2 below shows an example. The sample interval is covered in the
Section 2.2.3.

Figure 2-2. Channel refresh and conversion request
Sample Interval

Refresh Interval

Channel 0
Convert & Sample

Channel 1
Convert & Sample

Refresh interval

Channel 0
update or event

Channel 1
update or event
1

2

3

4

5

6

1) A refresh interval starts and a conversion and sampling of channel 0 follows.
After one sample interval, channel 1 is converted and sampled.
2) A conversion request (register update or event) for channel 0 triggers a
conversion and sampling of channel 0 only, even if we are in the middle of
one refresh interval.
3) Another refresh interval starts, similar to 1).

3
8033B-AVR-04/08

4) A conversion request (register update or event) for channel 1 triggers a
conversion and sampling of channel 1 only, even if both channels were just
refreshed.
5) Another refresh interval starts, similar to 1). Note that the conversion request
for channel 0 is delayed until 6).
6) The delayed conversion request from 5) triggers another conversion and
sampling of channel 0 immediately after finishing channel 1.

Note that if the arrival rate of conversion requests approaches the refresh rate, the
conversion timing might become imprecise, as an ordinary refresh could be in
progress when the conversion request arrives. A request that arrive in the middle of a
refresh is delayed until both channels have been refreshed. If more than one request
arrives for a channel before the first one is served, the extra requests will be ignored.
If this is a problem for the application in question, a solution is to disable the
automatic refresh interval and instead ensure that the data arrives at a high enough
rate. Note that it is not possible to turn of automatic refresh for one channel only.
2.2.3 Sample Interval
When using dual channel operation, there is a certain minimum time delay required
from conversion of channel 0 starts until channel 1 can start. This is due to a finite
settling time of the DAC conversion block output. This delay is minimum 1 us, which
limits the sample rate to maximum 1 MHz.
The sample interval is configured with the Channel Separation Control bitfield
(CHSEP) in the Timing Control register (TIMCTRL).

2.3 Left and Right Adjusted Values
The 12-bit input value to the DAC is contained in two 8-bit registers, referred to as the
high and low registers. By default, the 12-bit value is distributed with the 8 LSB in the
low register and 4 MSB in the high register. This distribution is convenient when the
application stores 12-bit DAC values as 16-bit integers, e.g. unsigned short int.
However, some applications find it useful to work with left-adjusted data, e.g. 16-bit
values where the 4 LSB is treated as a fractional part. Another alternative is that the
application stores DAC values in 8-bit variables, e.g. unsigned char, and thus
leaves the 4 LSB of the 12-bit DAC value equal to zero.
The XMEGA DAC module can be configured to accept left adjusted values by setting
the Left-adjust Value bit (LEFTADJ) in Control Register C (CTRLC). Figure 2-3 shows
the difference between right and left adjusted values in the DAC value registers.

4

AVR1301
8033B-AVR-04/08

AVR1301
Figure 2-3. Left and Right Adjusted Values
High Register

Low Register

MSB

LSB
Right-adjusted value (default)

High Register

MSB

Low Register

LSB
Left-adjusted value

2.4 Voltage References
The application can choose between the following voltage references for conversions:
o Bandgap Reference (1.1V)
o Analog voltage supply (VDD)
o External reference (VREF+)
Note that the external reference pin VREF+ is shared with the ADC module. The
voltage reference is select with the Reference bitfield (REFSEL) in Control Register C
(CTRLB).

2.5 Driving Strength
Regardless of operation mode, the DAC outputs are capable of driving external
resistive loads of 1 k? or capacitive loads of 100 pF. Please refer to the module
datasheet for detailed characteristics.

2.6 Calibration
To achieve optimal accuracy for the DAC output, the built-in calibration capabilities
allows fine-tuning of process related offset and gain errors. Two registers, Gain
Calibration (GAINCAL) and Offset Calibration (OFFSETCAL), are used for this
purpose. Both calibration register use 7 bits, where the MSB (bit 6) determines the
direction of the calibration and the 6 LSBs (bit 5..0) determine the calibration
amplitude.
When calibrating the DAC, you need to measure the output somehow. For this
purpose, the DAC can be internally connected to one of the ADC channels (with a
properly calibration ADC) or some external equipment. Using the XMEGA ADC
module enables fully automatic DAC calibration, while using external equipment might
give even higher accuracy if required. For more information on the ADC module,
please refer to the device datasheet or the application note "AVR1000: Getting
Started with the XMEGA ADC".
When calibrating, first tune the offset value until a value of 0x800 gives exactly half
the reference voltage. Then tune the gain value until a value of 0xFFF gives exactly

5
8033B-AVR-04/08

full reference voltage. Note that it is not possible to tune the gain value using 0x000,
as the conversion block is not able to reach down to 0V.
The calibration is not affected by single or dual channel modes, as the same DAC
block is used for both modes.
A flowchart for the calibration process is shown in Figure 2-4 below.
Figure 2-4. Calibration of DAC using the ADC
DAC Calibration

Read ADC and determine
gain tuning direction

Read ADC and determine
offset tuning direction

Tune gain value by linear or
binary search

Tune offset value by linear or
binary search

Store calibration values in
EEPROM if required

Gain calibration

Set DAC value to 0xFFF

Set DAC value to 0x800
Offset calibration

Configure ADC channel to
measure internal DAC output

END

3 Getting Started
This section walks you through the basic steps for getting up and running with simple
conversions and experimenting with different operating modes. The necessary
registers are described along with relevant bit settings.

3.1 Single Channel Operation
Task: Set static value on DAC channel 0 in single channel operation using analog
supply voltage as conversion reference.
o Set the Channel Select bitfield (CHSEL) in Control Register B (CTRLB) equal to
0x00 to select single channel operation.
o Clear the Event Trig Enable bit for channel 0 (CH0TRIG) in Control Register B
(CTRLB) to trigger conversions when data is written, instead of trigging on
incoming events.
o Set the Reference Selection bitfield (REFSEL) in Control Register C (CTRLC) equal
to 0x01 to use analog supply voltage as conversion reference.
o Set the Channel 0 Enable bit (CH0EN) in Control Register A (CTRLA) to enable
DAC output 0.
o Set the Enable bit (ENABLE) in Control Register A (CTRLA) to enable the DAC
module itself.
o Write a 12-bit right adjusted value to Channel 0 Data register (CH0DATA) to trigger
a conversion. Note that the low byte must be written first.
Note that the data registers are right adjusted by default.

6

AVR1301
8033B-AVR-04/08

AVR1301
3.2 Dual Channel Operation
Task: Set static value on both DAC channels in dual channel operation using analog
supply voltage as conversion reference.
o Set the Channel Select bitfield (CHSEL) in Control Register B (CTRLB) equal to
0x02 to select dual channel operation.
o Clear the Event Trig Enable bit for channel 0 and 1 (CH0TRIG and CH1TRIG) in
Control Register B (CTRLB) to trigger conversions when data is written, instead of
trigging on incoming events.
o Set the Reference Selection bitfield (REFSEL) in Control Register C (CTRLC) equal
to 0x01 to use analog supply voltage as conversion reference.
o Set the Channel 0 Enable and Channel 1 Enable bits (CH0EN and CH1EN) in
Control Register A (CTRLA) to enable both DAC outputs.
o Set the Channel Separation bitfield (CHSEP) in the Timing Control register
(TIMCTRL) equal to 0x04 to use 16 clock cycles for the sample interval, which
means 2 us with a peripheral clock of 8 MHz.
o Set the Refresh Timing bitfield (REFRESH) in the Timing Control register (TIMCTRL)
equal to 0x06 to use 128 clock cycles for the refresh interval, which means 16 us
with a peripheral clock of 8 MHz.
o Set the Enable bit (ENABLE) in Control Register A (CTRLA) to enable the DAC
module itself.
o Write 12-bit right adjusted values to the channel data register to trigger
conversions. The outputs will be refreshed every 16 us when no data is written to
the data registers.

4 Advanced Features
This section introduces more advanced features and possibilities with the DAC. Indepth treatment is outside the scope of this application note and the user is advised
to study the device datasheet and relevant application notes.
Note that the DAC module does not use interrupts.

4.1 DMA Controller
Instead of using polling or timed code to write data and start conversions, it is
possible to use the XMEGA DMA Controller to move data to the conversion registers
from memory buffers or other peripheral modules. This moving of data is done without
CPU intervention, and leaves the CPU ready for other tasks. Note that it is
recommended to use the Event System as conversion trigger source when using
DMA to achieve accurate conversion timing.
For more information, please refer to the device datasheet or the application note
"AVR1304: Getting Started with the XMEGA DMA Controller".

4.2 Event System
To improve conversion timing and further offload work from the CPU, the DAC is
connected to the XMEGA Event System. This makes it possible to use incoming
events to trigger data conversions.
For more information, please refer to the device datasheet or the application note
"AVR1303: Getting Started with the XMEGA Event System".
7
8033B-AVR-04/08

5 Driver Implementation
This application note includes a source code package with a basic DAC driver
implemented in C. It is written for the IAR Embedded Workbench(R) compiler, but it is
also compatible with AVR-GCC.
Note that this DAC driver is not intended for use with high-performance code. It is
designed as a library to get started with the DAC. For timing and code space critical
application development, you should access the DAC registers directly. Please refer
to the driver source code and device datasheet for more details.

5.1 Files
The source code package consists of three files:
o dac_driver.c - DAC driver source file
o dac_driver.h - DAC driver header file
o main.c - Example code using the driver
Note that the driver and example code does not include support for DMA data transfer
or the XMEGA Event System.
For a complete overview of the available driver interface functions and their use,
please refer to the source code documentation.

5.2 Doxygen Documentation
All source code is prepared for automatic documentation generation using Doxygen.
Doxygen is a tool for generating documentation from source code by analyzing the
source code and using special keywords. For more details about Doxygen please visit
http://www.doxygen.org. Precompiled Doxygen documentation is also supplied with
the source code accompanying this application note, available from the readme.html
file in the source code folder.

8

AVR1301
8033B-AVR-04/08

Disclaimer

Headquarters

International

Atmel Corporation
2325 Orchard Parkway
San Jose, CA 95131
USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600

Atmel Asia
Room 1219
Chinachem Golden Plaza
77 Mody Road Tsimshatsui
East Kowloon
Hong Kong
Tel: (852) 2721-9778
Fax: (852) 2722-1369

Atmel Europe
Le Krebs
8, Rue Jean-Pierre Timbaud
BP 309
78054 Saint-Quentin-enYvelines Cedex
France
Tel: (33) 1-30-60-70-00
Fax: (33) 1-30-60-71-11

Atmel Japan
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
Tel: (81) 3-3523-3551
Fax: (81) 3-3523-7581

Technical Support
avr@atmel.com

Sales Contact
www.atmel.com/contacts

Product Contact
Web Site
www.atmel.com

Literature Request
www.atmel.com/literature

Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any
intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL'S TERMS AND
CONDITIONS OF SALE LOCATED ON ATMEL'S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED
OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS,
BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS
BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the
contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any
commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in,
automotive applications. Atmel's products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.

(C) 2008 Atmel Corporation. All rights reserved. Atmel(R), logo and combinations thereof, AVR(R) and others, are the registered trademarks or
trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.

8033B-AVR-04/08


xMega_official_drivers_and_examples.rar > XMEGA ADC.pdf

AVR1300: Using the XMEGA ADC
Features
o
o
o
o
o
o
o
o
o
o

Up to 12 bit resolution
Up to 2M samples per second
Signed and unsigned mode
Selectable gain
Pipelined architecture
Up to 4 virtual channels
Result comparator
Automatic calibration
Internal connection to DAC output
Driver source code included

1 Introduction
The XMEGA(TM) ADC module is a high-performance Analog-to-Digital converter
capable of conversion rates up to 2 million samples per second (Msps) with a
resolution of 12 bits. Wide range of multiplexer (MUX) settings, integrated gain
stage and four virtual input channels make this a flexible module suitable for a wide
range of applications, such as data acquisition, embedded control and general
signal processing.

8-bit
Microcontrollers
Application Note

Preliminary

This application note describes the basic functionality of the XMEGA ADC with
code examples to get up and running quickly. A driver interface written in C is
included as well.
Advanced usage, such as Direct Memory Access (DMA) and the XMEGA Event
System, is outside the scope of this application note. Please refer to the device
datasheets and other relevant application notes for details.
Figure 1-1. ADC Overview

Rev. 8032D-AVR-02/10

2 Module Overview
This section provides an overview of the functionality and basic configuration options
of the ADC. Section 3 will walk you through the basic setup and usage of ADC on
register level.

2.1 Pipeline Architecture and Virtual Channels
The ADC conversion block has a 12-stage pipelined architecture capable of sampling
several signals in parallel. There are four input selection multiplexers with individual
configurations. The separate configuration settings for the four multiplexers can be
viewed as virtual channels, with one set of result registers each, all sharing the same
ADC conversion block. Refer to Figure 1-1 page 1.
The multiplexer outputs can be sampled every four ADC clock cycles and each signal
propagates through the pipeline, where one bit is converted at each stage. In this way
the ADC is capable of sampling one signal every four ADC clock cycles, even if each
signal must propagate through all stages in the pipeline before the result is ready in
the result register. The propagation time for one single signal conversion through the
pipeline is 7 ADC clock cycles for 12-bit conversions and 5 cycles for 8-bit
conversions. If Gain is used the propagation time increases by one cycle. At full
utilization the ADC delivers one result every ADC clock cycle. The relation between
the XMEGA peripheral clock and the ADC clock is described in Section 2.8.
Figure 2-1, page 3, shows a simplified 4-stage pipeline during conversion of two input
signals. The figure shows that once the signal has been sampled into the pipeline, the
first stage converts the MSB of the first signal. While the second stage is converting
the next bit of the signal, the first stage now converts the MSB of the second signal.

2

AVR1300
8032D-AVR-02/10

AVR1300
Figure 2-1. Simplified ADC pipeline with two propagating signals
1

2
2

1

0

3

3

2

3

Channel 1

Channel 0

3

1

0

2

1

0

3

3

4
3

2

1

0

3

2

Result Register 0
3

2
3

1

1

2

2

3

3

2

1

0

0

1

2

3

5
3

2

1

0

Result Register 1
3

2

1

0

0
1
2
3

Note that it is also possible to repeatedly convert signals from a single channel. The
pipeline can sample and convert a signal from one channel even if there is already a
previous sample from that channel on its way through the pipeline.
All the four virtual channels have one MUX Control register (CHnMUXCTRL), one
Channel Control register (CHnCTRL) and one Result register pair
(CHnRESL/CHnRESH) each, in addition to several control bits distributed in shared
registers.

2.2 Gain Stage
The ADC has an internal gain stage which can be configured to amplify a voltage to
allow measurement of smaller voltages.
This is a shared gain stage that can be used by all the channels. When the channel is
configured to use gain, the gain stage is inserted between the channel input selection
MUX and the conversion block. The available gain settings are 1x, 2x, 4x, 8x, 16x,
32x and 64x. The Gain Factor bit field (GAINFACT) in the Channel Control register
(CHnCTRL) set the gain factor for the channel.
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It is possible to have individual gain settings for all the virtual channels.
The propagation delay for an ADC sample through the ADC increases by one ADC
clock cycle when using the gain stage.
Using the gain setting of 1x gives no amplification, but it can be used to give the
propagation delay for a channel with no amplification identical to channels that use
amplification. However, to minimize the analog signal path for best possible ADC
results it is recommended to configure the channel without gain unless having
identical propagation delay is important in the application.

2.3 Conversion Mode
The conversion block can be put in the unsigned or signed conversion mode.
Signed mode can be used as input mode for both differential and single-ended inputs,
while unsigned mode is only available for the single-ended or internal input.
In unsigned mode the conversion range is from ground to the reference voltage. To
be able to have zero-cross detection a ?V is subtracted. The ?V is approximately
0.05*Vref, so the ground level will be approximately 0.05 of the total value range (0.05
* 4095 with 12-bit resolution). This will also limit the maximum input voltage of
0.05*Vref, so the maximum input voltage is Vref - ?V. This is illustrated in Figure 2-2.
In signed mode the range is from negative to positive reference voltage, but the input
voltage must be within GND and Vref. The figure below shows the difference in
conversion ranges.
Figure 2-2. Unsigned and signed conversion mode
Unsigned Mode
+VREF - ?V

Signed Mode
4095

+VREF

VINN

GND
Input voltage

Approx.
200
Digital result

VINN-VREF
Input voltage

2047

0

-2048
Digital result

The figure shows that the unsigned mode gives higher resolution on positive values
than signed mode, but cannot convert negative values. The signed mode can convert
negative values, but at the cost of lower resolution overall.
When the ADC uses differential inputs signed mode must be used, while in the other
modes both signed and unsigned mode can be used.

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Note that conversion mode is configured for the whole ADC, not individually for each
channel, which means that the ADC must be put in the signed mode even if only one
of the channels uses differential inputs.
The conversion mode is configured using the Conversion Mode bit (CONVMODE) in
Control Register B (CTRLB).
Note that even if the difference between two inputs could be negative, voltages below
GND or above VCC should under no circumstances be applied to any input pin.

2.4 Multiplexer Settings
The MUXes are used to select input signal for each virtual channel. There are four
different configuration choices that can be selected using the Channel Input mode
bitfield (INPUTMODE) in the Channel Control register (CHnCTRL):
o Differential Input without Gain
o Differential Input with Gain Stage
o Single-ended Input
o Internal Input
The positive and negative inputs are selected using the MUX Positive Input and MUX
Negative Input bitfields (MUXPOS and MUXNEG) in the Channel Mux Control register
(MUXCTRL). An alternative name for the MUX Positive Input bitfield used in the
header files is MUX Internal Input (MUXINT) when measuring internal inputs.
In devices with two ADCs, the inputs can only be connected to the corresponding
port. Meaning that ADC A can be connected to PORT A and ADC B can be
connected to PORT B. The positive input can be connected to any one of the eight
input signals of corresponding port. The negative input can be connected to one of
the first four input signals (PIN0 - PIN3) of the corresponding port for differential
without Gain and the second four input signals (PIN4 -PIN7) for differential with Gain.
In devices with only one ADC but several analog ports, the positive input can be
connected to any of the available input signals from both PORT A and PORT B. The
negative input can be connected to one of the first four input signals (PIN0 - PIN3) of
the corresponding port for differential without Gain and the second four input signals
(PIN4 -PIN7) for differential with Gain.
Refer to the datasheet to determine the number of ADC and the devices pin
configuration.
Note that even if the difference between two inputs could be negative, voltages below
GND or above VCC should under no circumstances be applied to any input pin.
Note that the sampling capacitor is drained between each sample for all modes
except for differential mode with gain. In the differential mode with gain, the charge on
the sampling capacitor is maintained and this can be used to get a higher sample rate
on slow changing signal. This can be used to get higher sampling rates on high
impedance sources compared to single channel or differential channel (without gain)
sampling. This will however propagate to other channels if the sample rate is too high
compared to the source impedance.

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2.4.1 Differential Input without gain
With this setting, the MUX measures the difference between two input signals. In
differential mode without gain all ADC inputs can be used for the positive input of the
ADC but only the lower 4 pins can be used as the negative input. When using
differential mode, offset can be measured quite easily by setting up the positive and
negative input on the same pin, and the offset can be measure directly as the ADC
does not need to know where the ground level is.
One common misunderstanding is that the ADC can measure negative voltages. The
fact is that the ADC can not measure voltage levels below ground level and not above
the voltage reference level. What is actually meant by having negative results is that
the voltage on the negative ADC input is greater than that on the positive ADC input.

Pin inputs

Figure 2-3. Differential input without gain stage

Positive input

Pin inputs

Pipelined
ADC Block

Negative input

2.4.2 Differential Input with Gain Stage
This setting is almost identical to differential input without gain stage. With this setting
the gain stage is inserted in the signal path for this channel, providing up to 64 times
amplification of the differential input signal. When the gain stage is used, the
propagation delay through the ADC block is increased by 1 ADC clock cycle.

Pin inputs

Figure 2-4. Differential input with gain stage

Pin inputs

Positive input

Gain

Pipelined
ADC Block

Negative input

Note that the gain stage does not load the input and external signal source will see
very high input impedance for channels that use the gain stage. This is useful for
measuring weak signal sources. Details can be found in the datasheet for the device.
The voltage on any of the two inputs can be between GND and Vref, but the difference
between them must not be larger than Vref/GAIN because this will saturate the ADC
and the converted value will only equal the top value of the ADC.
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2.4.3 Single-ended Input
With this setting, the ADC measures the value of one input signal. The difference
between this setting and differential measurement is that the negative input is always
connected internally to a defined level depending on if signed or unsigned mode is
being used. For signed mode the negative input is tied to GND while in unsigned
mode it is connected to Vref/2 - ?V.
Figure 2-5. Single-ended input in signed mode

?V is a fixed internally generated voltage of approximately 0.05*Vref. This offset
needs to be measured by connecting the positive input to ground (GND). The offset
will typically correspond to a value of about 200 when measured.
The advantage of ?V is that it will be possible to measure a negative offset in the
ADC block because ?V will be larger than any offset. ?V will allow the XMEGA ADC
to be used in applications where it is essential to know and compensate for offset
errors. The disadvantage is that some of the upper range is lost since any
measurement above Vref - ?V will saturate to the top value.
In addition to connecting the negative input the ADC will in unsigned single ended
mode automatically add 2048 to the result. This gives a possible output range from 0
to 4096 as opposed to -2048 to 2047 for signed mode.
Figure 2-6. Single-ended input in unsigned mode

2.4.4 Internal Input
With this setting, the MUX measures one of several internal signals. The negative
input is always connected to GND while the positive input can be connected to one of
the following internal sources: Temperature Reference, DAC Internal Output, VCC/10
(for supply voltage measurement) or Bandgap Reference. Note that two channels can
select different internal sources. They are not limited to one common setting, as
opposed to the shared gain stage setting.

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The internal DAC input can be used for calibration of the DAC. For more information
about DAC configuration, please refer to the device datasheet or the application note
"AVR1301: Getting Started with the XMEGA DAC".
The Bandgap Reference can be used as a reference to calculate the external
reference, like a battery voltage, if the voltage is unknown. With a measurement of a
known voltage (the Bandgap Reference, 1.1 V) using an unknown reference, it is
easy to calculate the actual voltage of the external reference.
Figure 2-7. Internal input in signed mode

Figure 2-8. Internal input in unsigned mode

Note that if no other modules are using the Bandgap Reference. It must be turned on
using the Bandgap Enable bit (BANDGAP) in the Reference Control register
(REFCTRL).
The same goes for the Temperature Reference, which is not shared with any other
modules. The Temperature Reference is turned on using the Temperature Reference
Enable bit (TEMPREF). Also note that there is a certain settling time for both
Bandgap and Temperature Reference, hence should be enabled in due time before
starting any conversions.
Note that input sampling speed of the internal inputs can be slower than the
maximum conversion range of the device. (example: 100ksps/2Msps) See device
datasheet for more information.
2.4.5 Temperature sensor
The internal temperature sensor is linear. Ideally the measured value at 0°K will
correspond to a "0" result from the ADC. An approximate linear line can be made from
the 0°K to the measured value in the production. This measured production value is
stored in the signature row and the value correspond to a measurement done at 85°C
(358°K) with an accuracy of +- 5°C. The inaccuracy will result in some offset when
measuring temperatures.
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The measurement stored in the signature row is done in unsigned mode with 12-bit
resolution with the internal 1V reference. The ADC setup has to be the same if this
value is going to be used in the application. The stored value can be used for a 2point calibration where the second point will be 0°K and the ADC value will be 0.
The best way to get accurate results is to do a 2-point calibration to get the incline of
the curve. To do a 2-point calibration, select 2 temperatures where you can do the
measurements where the temperature is known and is accurate. Do a measurement
at both temperatures with the wanted setup of the ADC (mode, sample rate,
resolution). When you have these values, you can calculate the coefficient for the
curve and you can use this in you application. The formula below can be used to
calculate the temperature change per bit:

Temp / bit =

TempHigh - TempLow
ValueHigh - ValueLow

2.5 Conversion Result
2.5.1 Signed mode
In signed mode the conversion result from the ADC is:

V - VINN
RES = INP
* GAIN * TOP
VREF
VINP is the positive input and VINN is the negative input to the ADC. GAIN corresponds
to the gain setting used. GAIN is 1 if gain is not used. TOP is the top value given by
the configured resolution, which is 2048 for 12 bit mode and 128 for 8 bit mode.
In signed mode the result is returned as a signed number represented on a two's
complement format where the MSB represents the sign bit. In 12-bit right adjusted
mode, the sign bit (bit 11) is padded to bits 12-15 to create a signed 16-bit number
directly. In 8-bit mode, the sign bit (bit 7) is padded to the entire high byte.
With 12-bit resolution the range from -VREF to +VREF will be -2048 to +2047 (0xF800 0x07FF).

2.5.2 Unsigned mode
In unsigned mode the conversion result from the ADC is:

V + ?V
RES = INP
* GAIN * TOP
VREF
VINP is the positive input while GAIN corresponds to the gain setting used. GAIN is 1 if
gain is not used. TOP is the top value given by the configured resolution. For 12 bit
mode TOP is 4096 and 8 bit mode TOP is 256.
The positive offset given by ?V is typically 0.05*VREF. This typically corresponds to a
measurement result of approximately 200 when the input pin is connected to ground.
In order to measure this offset accurately the ADC should be configured as it will be
used in the application (ie. voltages, speed and other settings) and the input pin
should be connected externally to ground.
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This offset is not compensated for automatically, and the software needs to subtract
the measured offset from the conversion results.
With 12-bit resolution the range from GND to VREF - ?V will be from approximately
200 to +4095 (0x00C8 - 0x0FFF).

2.6 Result Presentation
The ADC can be configured to present conversion results in the following formats:
o 12 bits, right adjusted
o 8 bits, right adjusted
o 12 bits, left adjusted
Note that a lower resolution gives faster conversions, as there are fewer pipeline
stages for the signal samples to propagate through. Therefore, selecting result
presentation is a tradeoff between resolution and conversion speed.
The ADC resolution is configured using the Conversion result Resolution bitfield
(RESOLUTION) in Control Register B (CTRLB).
The result will be stored in the result registers for each channel. The channels have
separate flags to indicate when a new conversion is ready. If the result is not read
before a new conversion is done, the current result will be lost.
The DMA can be set up to transfer the result from the result register into the SRAM
when a new conversion is ready. This can be done for all channels when doing
sweep and store all 4 channels in one burst.

2.7 Voltage References
The application can choose between the following voltage references (VREF) for
conversion results:
o
o
o
o

INT1V - Internal reference of 1.0 V
INTVCC - Internal reference of VCC / 1.6 V
AREFA - External reference pin on PORTA
AREFB - External reference pin on PORTB

The internal INT1V reference is a 1.00V reference from the bandgap of the device.
The bandgap voltage is 1.10V and the reference voltage is 10/11 of the bandgap
voltage, giving the 1.00V reference. The accuracy of the reference is dependent on
the bandgap. The accuracy of the bandgap is stated in the device's datasheet.
The INTVCC is a reference voltage based on Vcc divided by 1.6. The accuracy is
depending on the accuracy and stability of the analog supply voltage (AVcc) and
filtering should be used if the AVcc is connected to the digital Vcc.
Note that the external reference pin AREFA/B is shared with the DAC module. The
voltage reference is configured using the Reference Selection bitfield (REFSEL) in the
Reference Control register (REFCTRL). The external reference is located at pin 0 on
PORTA and PORTB (AREFA and AREFB).

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Note that for the external references the maximum voltage to be used is Vcc - 0.6V
and the minimum voltage is 1V. The accuracy of the external reference is depending
on the external circuitry and this has to be designed to satisfy the required accuracy
for the ADC measurements.

2.8 Conversion Speed
The ADC clock is derived from a prescaled version of the XMEGA peripheral clock,
where the available factors are 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256 and 1/512. The
ADC clock has to be set within the minimum and maximum recommended speed for
the ADC module to guarantee correct operation. The ADC Clock is configured using
the Clock Prescaler register (PRESCALER).
Please consult the device datasheet for details on recommended minimum and
maximum ADC clock speeds.
Note that having a fast ADC clock gives a short propagation time for each sample,
but does not mean that you cannot sample a signal at a much slower rate. For
instance, an application could sample at a rate of 10kHz even if the ADC clock is
8MHz. However, it is not possible to sample at a rate higher than one fourth of the
ADC clock speed since the maximum ADC clock is 1/4th of the peripheral clock. See
device datasheet for more information.
Note that the ADC clock has to be 100kHz when sampling the internal signals.
The conversion rate must satisfy the requirements for the given source impedance. If
the sampling rate is too high compared to the source impedance, the results will not
be accurate. It's important that you do not sample faster than the inclination rate of
the signal to follow. The maximum sample rate is defined by the formula:

f ADC <=

1
2 ? ( Rsource + Rchannel + Rswitch ) ? Csample ? ln(2 n +1 )

The values for Csample, Rchannel and Rswitch can be found in the datasheet of the device.
The n represent the number of bits in the conversion and can be 8 or 12. The Rsource
is the impedance of the analog signal source which can be calculated from the
circuitry or found in the datasheet of the device if using integrated sensors.
To give an illustration of how this will affect the sampling rate, we will use worst case
numbers for Rchannel, Rsource and Csample. This is 5kOhm for Rchannel, Rsource and 4.4pF for
Csample. This will give the relationship between source impedance and the maximum
sampling rate as shown in Figure 2-9 page 12.

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Figure 2-9. Sampling rate vs. Source impedance (log/log plot)

2.9 Free-running Mode
Instead of manually starting conversions by setting one or more of the Start
Conversion bits (CHnSTART) in Control Register A (CTRLA) or assigning events to
virtual channels, the ADC can be put in free-running mode. This means that a number
of channels are repeatedly converted in sequence as long as the mode is active.
The Channel Sweep Selection bitfield (SWEEP) in the Event Control register (EVCTRL)
selects which channels to include in free-running mode. You can choose between
channel 0 only, channel 0 and 1, channel 0 to 2 or all four channels.
Note that the same bits are used to select the channels to include in an eventtriggered conversion sweep, but that is outside the scope of this application note.
Care should be taken not to change any involved MUX settings when in free-running
mode, as this would corrupt conversion results.

2.10 Interrupts
To avoid having to poll a register to check when conversions are finished, the ADC
can be configured to issue interrupt requests upon conversion complete. This can be
used to do result processing using interrupt handler code while leaving the CPU
ready for other tasks most of the time.
For more information, please refer to the device datasheet or the application note
"AVR1305: Getting Started with the XMEGA Interrupt Controller".
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2.11 Result Comparator Interrupt
Instead of merely converting an input value, the ADC can be configured to compare
the result to a given value and only issue an interrupt or event when the result is
above or below that value. Interrupts on compare match (above/below) can be
configured individually on each channel, but the compare register is shared between
all four virtual channels.
Typical use of this feature is to leave one or more ADC channels in free-running
mode and configure the ADC to issue an interrupt when one of the input signals reach
a certain threshold.

2.12 Calibration
The ADC module has been calibrated during production of the device. This calibration
value is stored in the production signature row of the device. The calibration value
compensates for mismatch between the individual steps of the ADC pipeline and it
improves the linearity of the ADC.
The calibration value is not loaded automatically, and should always be loaded from
the production signature row (ADCxCAL0/1) and written to the corresponding ADC
calibration registers (CALL/CALH) before enabling the ADC.
Flowcharts for loading stored calibration settings are shown in Figure 2-9 below.
Figure 2-10. Using stored calibration settings
Stored calibration

Configure ADC

W rite calibration
registers using stored
values

Enable ADC by setting
the ADCEN bit

ADC ready

The calibration value is factory calibrated with high accuracy equipment to the
datasheet accuracy, and is not intended for user calibration.
The application note "AVR120: ADC Characteristics and Calibration" contains more
information on characteristics of ADCs and how to compensate for gain and offset
errors.
2.12.1 Offset error
The offset error is defined as the deviation of the actual ADC's transfer function from
the ideal straight line at zero input voltage.
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When the transition from output value 0 to 1 does not occur at an input value of 1/2
LSB, then we say that there is an offset error. With positive offset errors, the output
value is larger than 0 when the input voltage approaches 1/2 LSB from below. With
negative offset errors, the input value is larger than 1/2 LSB when the first output value
transition occurs. In other words, if the actual transfer function lies below the ideal
line, there is a negative offset and vice versa. Negative and positive offsets are shown
in Figure 2-11.
Figure 2-11. Examples of positive (A) and negative (B) offset errors
Output value

Output value

+1 1/2 LSB offset
Analog input

Analog input
-2 LSB offset

(A)

(B)

Since single-ended conversion gives positive results only, the offset measurement
procedures are different when using single-ended and differential channels.
2.12.2 Offset error - single-ended channels
To measure the offset error, increase the input voltage from GND until the first
transition in the output value occurs. Calculate the difference between the input
voltage for which the perfect ADC would have shown the same transition and the
input voltage corresponding to the actual transition. This difference, converted to LSB,
equals the offset error.
In
Figure 2-12A, the first transition occurs at 1 LSB. The transition is from 2 to 3, which
equals an input voltage of 2 1/2 LSB for the perfect ADC. The difference is +1 1/2 LSB,
which equals the offset error. The double-headed arrows show the differences.
The same procedure applies to
Figure 2-12B. The first transition occurs at 2 LSB. The transition is from 0 to 1, which
equals an input voltage of 1/2 LSB for the perfect ADC. The difference is -1 1/2 LSB,
which equals the offset error.

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Output value

Output value

Figure 2-12. Positive (A) and negative (B) offset errors in single-ended mode

+1 1/2 LSB offset

Analog input
(A)

-1 1/2 LSB offset

Analog input
(B)

To compensate for offset errors when using single ended channels, subtract the
offset error from every measured value. Be aware that offset errors limit the available
range for the ADC. A large positive offset error causes the output value to saturate at
maximum before the input voltage reaches maximum. A large negative offset error
gives output value 0 for the smallest input voltages.
2.12.3 Offset error - differential channels
With differential channels, the offset measurement can be performed much easier
since no external input voltage is required. The two differential inputs can be
connected to the same voltage internally and the resulting output value is then the
offset error. Since this method gives no exact information on where the first transition
occurs, it gives an error of 1/2 to 1 LSB (worst case).
To compensate for offset errors when using differential channels, subtract the offset
error from every measured value.
2.12.4 Gain error
The gain error is defined as the deviation of the last output step's midpoint from the
ideal straight line, after compensating for offset error.
After compensating for offset errors, applying an input voltage of 0 always give an
output value of 0. However, gain errors cause the actual transfer function slope to
deviate from the ideal slope. This gain error can be measured and compensated for
by scaling the output values.
Run-time compensation often uses integer arithmetic, since floating point calculation
takes too long to perform. Therefore, to get the best possible precision, the slope
deviation should be measured as far from 0 as possible. The larger the values, the
better precision you get. This is described in detail later in this document.
The example of a 3-bit ADC transfer functions with gain errors is shown in Figure
2-13. The following description holds for both single-ended and differential modes.

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Figure 2-13. Examples of positive (A) and negative (B) gain errors

111

111
110
+1 1/2 LSB error

101
100
011

Output code

Output code

110

-1 1/2 LSB error

101
100
011

010

010

001

001

000

0/8 1/8 2/8 3/8 4/8 5/8 6/8 7/8 AREF
Analog input

000

0/8 1/8 2/8 3/8 4/8 5/8 6/8 7/8 AREF
Analog input

(A)

(B)

To measure the gain error, the input value is increased from 0 until the last output
step is reached. The scaling factor for gain compensation equals the ideal output
value for the midpoint of the last step divided by the actual value of the step.
2.12.5 Non-linearity
When offset and gain errors are compensated for, the actual transfer function should
be equal to the transfer function of perfect ADC. However, non-linearity in the ADC
may cause the actual curve to deviate slightly from the perfect curve, even if the two
curves are equal around 0 and at the point where the gain error was measured. There
are two methods for measuring non-linearity, both described below. Figure 2-14
shows examples of both measurements.
Figure 2-14. Example of a non-linear ADC conversion curve
111

110
Output code

Output code

110

111
1/2 LSB wide,
DNL = - 1/2 LSB

101
100
011
010

1 1/2 LSB wide,
DNL = + 1/2 LSB

001
000

101
100
011

Max INL = + 3/4 LSB

010
001
000

0/8 1/8 2/8 3/8 4/8 5/8 6/8 7/8 AREF
Analog input
(A)

0/8 1/8 2/8 3/8 4/8 5/8 6/8 7/8 AREF
Analog input
(B)

2.12.6 Differential non-linearity
Differential Non-Linearity (DNL) is defined as the maximum and minimum difference
between the step width and the perfect width (1 LSB) of any output step.
Non-linearity produces quantization steps with varying widths. All steps should be 1
LSB wide, but some are narrower or wider.
To measure DNL, a ramp input voltage is applied and all output value transitions are
recorded. The step lengths are found from the distance between the transitions, and
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the most positive and negative deviations from 1 LSB are used to report the
maximum and minimum DNL.
2.12.7 Integral non-linearity
Integral Non-Linearity (INL) is defined as the maximum vertical difference between
the actual and the perfect curve.
INL can be interpreted as a sum of DNLs. E.g. several consecutive negative DNLs
raise the actual curve above the perfect curve as shown in Figure 2-14. Negative
INLs indicate that the actual curve is below the perfect curve.
The maximum and minimum INL are measured using the same ramp input voltage as
in DNL measurement. Record the deviation at each conversion step midpoint and
report the most positive and negative deviations as maximum and minimum INL.
2.12.8 Measurements and compensation
It is important that DNL and INL values are measured after offset and gain error
compensation. If not, the results will be infected by the offset and gain error and thus
not reveal the true DNL and INL.
Non-linearity cannot be compensated for with simple calculations. Polynomial
approximations or table lookups can be used for that purpose. However, the typical
DNL and INL values are less than ?2 LSB for the 12-bit ADC of the XMEGA, and are
rarely of any concern in real life applications.

2.13 Best practice use for improving accuracy
The accuracy of the XMEGA ADC depends on the quality of the input signals and
power supplies. The following items should be taken into consideration for best
possible accuracy of the ADC measurements:
o

Understand the ADC, its features and how they are intended used.

o

Understand the applications requirements.

o

Make sure the source impedance is not too high compared to the sampling
rate that is used. If the source impedance is too high, the internal sampling
capacitor will not be charged to the correct level and the result will not be
accurate.

o

It is important to take great care when designing the analog signal paths like
analog reference (VREF) and analog power supply (AVCC). Filtering should be
used if the analog power supply is connected to the digital power supply.

o

Avoid having the analog signal path close to digital signal path with high
switching noise (i.e. communication lines, clock signals).

o

Consider decoupling of the analog signal. Decoupling between signal and
ground for single ended inputs and decoupling between the differential signal
pair for differential measurements.

o

Try to toggle as few pins as possible while the ADC is converting to avoid
switching noise internally and on power supply. The ADC is most sensitive to
switching the I/O pins that are powered by the analog power supply
(PORTA/PORTB).

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o

Switch off unused peripherals by setting PRR registers to eliminate noise
from unused peripherals.

o

Put the XMEGA in the "Idle" sleep mode directly after starting the ADC
conversion to reduce noise from the CPU.

o

Load the calibration values from the signature row into the calibration register
in the ADC.

o

Use the lowest gain possible to avoid amplifying external noise.

o

Wait until the ADC, reference or sources are stabilized before sampling as
some sources (e.g. bandgap) need time to stabilize after they are enabled.

o

Apply offset and gain calibration to the measurement.

o

Use over-sampling to increase resolution and eliminate random noise.

For randomly distributed noise using oversampling will help reducing any noise and
improve accuracy. Using 8x oversampling will increase resolution by 2 bits, and due
to the pipelined design of the ADC only take 8 additional ADC clock cycles.
See application note "AVR121: Enhancing ADC resolution by oversampling" for more
information on oversampling.

2.14 Examples
For some more practical description of what is needed in the real world, some
examples will be presented in this section.
2.14.1 Decoupling
To get stable results, we need decoupling. This is needed both for the analog signals
measured and for the reference used.
To be able to have a common reference for all signals measured over time, the
voltage reference has to be exactly the same. To achieve this, the reference has to
be decoupled with a large capacitor. For internal references this is not directly
possible, but the AVcc and Vcc have to be decoupled sufficiently. For both AVcc and
for the external references decoupling and filtering should be done. Using a filter
inductor and a large capacitor will help on keeping the reference stable. The larger
the capacitor, the better stability is achieved. A 1uF or larger capacitor is
recommended. When using the ADC you have to wait until the capacitor is fully
charged and stable, before measurements can be done. The time until stable have to
be calculated from the rise time of the RC connection of the capacitor.
For the analog signals, decoupling should also be done. When having single ended
signals, the decoupling should be done between the signal and ground and for
differential signals the decoupling has to be between the positive and negative input.
Decoupling of the signals is a more complex situation than the reference and this has
to take the signals into account. If the signals are switching fast, the decoupling
capacitor has to be lower. The decoupling capacitor should be as high as possible
without changing the rise and fall time of the signal. It is therefore hard to give an
exact value for the decoupling, and this has to be calculated as an RC circuit.
2.14.2 Source impedance
This is a very common problem when doing ADC designs. The source impedance is
the sources capability to deliver charge to the internal sampling capacitor fast
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enough. If the internal capacitor is not charged to the same level as the analog signal,
the result will be wrong.
When using a direct connection from a sensor IC, the impedance is usually stated in
the datasheet of the device and it is easy to adjust the speed for the given
impedance.
When the circuitry is made up by passive components, calculations have to be done
to find the actual source impedance. For example, a resistor ladder dividing a high
voltage down to a voltage that can be handled by the microcontroller can have very
high impedance as large resistors are used to get the voltage sufficiently down. The
solution is then to either lower the sample rate to be able to measure the correct
signal or to lower the resistance value. Lowering the resistance would cause more
leakage current and this can again be solved by adding switching FET to enable and
disable the analogue source. An example of this can be seen in the schematic below.
Another thing to be aware of in such an application is the time for the source to be
stable, as the decoupling will take some time to charge to the correct level after
enabling the analog source.

3 Getting Started
This section walks you through the basic steps for getting up and running with simple
conversion and experimenting with MUX settings. The necessary registers are
described along with relevant bit settings.

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Note that this section only covers manual polling of status bits. Interrupt control is not
covered, but is an easy step after studying the application note "AVR1305: Getting
Started with the XMEGA Interrupt Controller".

3.1 Single Conversion
Task: One single-ended conversion of ADC input 1 using virtual channel 2.
o Set the Input Mode bitfield (INPUTMODE) in Channel 2 Control Register (CH2CTRL)
equal to 0x01 to select single-ended input.
o Set the MUX Positive Input bitfield (MUXPOS) in Channel 2 MUX Control Register
(CH2MUXCTRL) equal to 0x01 to select ADC input 1.
o Set the Enable bit (ENABLE) in Control Register A (CTRLA) to enable the ADC
module without calibrating.
o Set the Start Conversion bit for channel 2 (CH2START) in Control Register A
(CTRLA) to start a single conversion.
o Wait for the Interrupt Flag bit for channel 2 (CH2IF) in the Interrupt Flags register
(INTFLAGS) to be set, indicating that the conversion is finished.
o Read the Result register pair for channel 2 (CH2RESL/CH2RESH) to get the 12-bit
conversion result as a 2-byte value.

3.2 Multiple Channels
Task: One single-ended conversion of ADC input 3 and 6 using virtual channel 1 and
3.
o Set the Input Mode bitfield (INPUTMODE) in Channel 1 Control Register (CH1CTRL)
and Channel 3 Control Register (CH3CTRL) equal to 0x01 to select single-ended
input on both channels.
o Set the MUX Positive Input bitfield (MUXPOS) in the MUX Control Register for
channel 1 and 3 (CH1MUXCTRL and CH3MUXCTRL) equal to 0x03 and 0x06
respectively.
o Set the Enable bit (ENABLE) in Control Register A (CTRLA) to enable the ADC
module without calibrating.
o Set the Start Conversion bit for channel 1 and 3 (CH1START and CH3START) in
Control Register A (CTRLA) to start two conversions.
o Wait for the Interrupt Flag bits for channel 1 and 3 (CH1IF and CH3IF) in the
Interrupt Flags register (INTFLAGS) to be set, indicating that the conversions are
finished.
o Read the Result register pair for channel 1 and 3 (CH1RESL/CH1RESH and
CH3RESL/CH3RESH) to get the 12-bit conversion results as 2-byte values.

3.3 Free-running Mode
Task: Free-running differential conversion on channel 0, using ADC0 and ADC3 as
positive and negative inputs.
o Set the MUX Positive Input and MUX Negative Input bitfields (MUXPOS and
MUXNEG) in Channel 0 (CH0MUXCTRL) to 0x00 and 0x03 respectively.
o Set the Free Run bit (FREERUN) in Control Register B (CTRLB) to enable free
running mode.

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o Set the Enable bit (ENABLE) in Control Register A (CTRLA) to enable the ADC
module without calibrating.
o Optionally wait for the Interrupt Flag bit for channel 0 (CH0IF) in the Interrupt
Flags register (INTFLAGS) to be set, indicating that a new conversion is finished.
Clear the flag by writing a one to it, as it is going to be used later.
o Read the Result register pair for channel 0 (CH0RESL/CH0RESH) to retrieve the
latest 12-bit conversion results as a 2-byte value.
Note that it is not strictly required to wait for the interrupt flag when using free-running
mode. However, to make sure you have a fresh conversion, you should wait for the
flag, clear it and then read the result. Also note that it is recommended to use the
Free-running Mode together with DMA data transfer to offload work from the CPU.

4 Advanced Features
This section introduces more advanced features and possibilities with the ADC. Indepth treatment is outside the scope of this application note and the user is advised
to study the device datasheet and relevant application notes.

4.1 DMA Controller
Instead of using interrupt handlers to read and process the result registers, it is
possible to use the XMEGA DMA Controller to move data from one or more result
registers to memory buffers or other peripheral modules. This moving of data is done
without CPU intervention, and leaves the CPU ready for other tasks, even without
having to execute interrupt handlers.
For more information, please refer to the device datasheet or the application note
"AVR1304: Getting Started with the XMEGA DMA Controller".

4.2 Event System
To improve conversion timing and further offload work from the CPU, the ADC is
connected to the XMEGA Event System. This makes it possible to use incoming
events to trigger single conversions or conversion sweeps across several channels.
The ADC conversion complete conditions also serve as event sources available for
other peripheral modules connected to the event system.
For more information, please refer to the device datasheet or the application note
"AVR1001: Getting Started with the XMEGA Event System".

5 Driver Implementation
This application note includes a source code package with a basic ADC driver
implemented in C and in Assembly. It is written for the IAR Embedded Workbench(R)
compiler.
Note that this ADC driver is not intended for use with high-performance code. It is
designed as a library to get started with the ADC. For timing and code space critical
application development, you should access the ADC registers directly. Please refer
to the driver source code and device datasheet for more details.

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5.1 Files
Note that the driver and example code does not include support for DMA data transfer
or the XMEGA Event System.
For a complete overview of the available driver interface functions and their use,
please refer to the source code documentation.

5.2 Doxygen Documentation
All source code is prepared for automatic documentation generation using Doxygen.
Doxygen is a tool for generating documentation from source code by analyzing the
source code and using special keywords. For more details about Doxygen please visit
http://www.doxygen.org. Precompiled Doxygen documentation is also supplied with
the source code accompanying this application note, available from the readme.html
file in the source code folder.
U

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