tda8920_1.pdf

brak opisu 2 elementów we wzmacniaczu 2x50

Mam schemat wzmacniacza opartego na scalaku TDA8920 i nie wiem jakie mają być wartości elementu Rlim i Cstab. Czy wie ktoś co tam wstawić??


INTEGRATED CIRCUITS

DATA SHEET

TDA8920
2 × 50 W class-D power amplifier
Preliminary specification
File under Integrated Circuits, IC01

1998 Dec 01

Philips Semiconductors

Preliminary specification

2 × 50 W class-D power amplifier

TDA8920

FEATURES

APPLICATIONS

o High efficiency (90%)

o Television sets

o Operating voltage from ?15 V to ?30 V

o Home-sound systems

o Very low quiescent current

o Multimedia systems.

o Low distortion
o Fixed gain of 30 dB

GENERAL DESCRIPTION

o High output power

The TDA8920 is a high efficiency class-D audio power
amplifier. It can be used in a mono Bridge-Tied Load (BTL)
or in a stereo Single-Ended (SE) configuration. The device
operates over a wide supply voltage range from
?15 V up to ?30 V and consumes a very low quiescent
current.

o Output power limiter
o Good ripple rejection
o Usable as a mono amplifier in Bridge-Tied Load (BTL) or
as a stereo Single-Ended (SE) amplifier
o Tracking possibility for oscillator frequency
o Differential audio inputs
o No switch-on or switch-off plops
o Short-circuit proof across the load
o Electrostatic discharge protection on all pins
o Thermally protected.
QUICK REFERENCE DATA
SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

General
VDD

operating supply voltage

?15

?25

?30

V

Iq(tot)

total quiescent current

-

50

60

mA

?

efficiency

Po = 10 W

85

90

-

%

THD = 10%

tbf

35

-

W

29

30

31

dB

Stereo single-ended configuration
Po

output power

Gv(cl)

closed loop voltage gain

?Zi?

input impedance

80

120

-

kOhm

Vn(o)

noise output voltage

-

100

-

uV

SVRR

supply voltage ripple rejection

60

-

-

dB

?cs

channel separation

50

tbf

-

dB

-

130

-

W

Mono bridge-tied load configuration
Po

output power

Gv(cl)

closed loop voltage gain

35

36

37

dB

?Zi?

input impedance

40

60

-

kOhm

Vn(o)

noise output voltage

-

140

-

uV

SVRR

supply voltage ripple rejection

66

-

-

dB

??VO?

DC output offset voltage

-

-

50

mV

1998 Dec 01

THD = 10%

2

Philips Semiconductors

Preliminary specification

2 × 50 W class-D power amplifier

TDA8920

ORDERING INFORMATION
TYPE
NUMBER

PACKAGE
NAME

DESCRIPTION

VERSION

TDA8920J

DBS17P

plastic DIL-bent-SIL power package; 17 leads (lead length 12 mm)

SOT243-1

TDA8920TH

HSOP20

heatsink small outline package; 20 leads

SOT418-1

BLOCK DIAGRAM

VDD2

handbook, full pagewidth

13

IN1+

5

6

BOOT1

4

IN1-

VDD1

3

ANALOG

7

DIGITAL

OUT1

VSS1
LIM

16

TDA8920J

PROTECTION

12

BOOT2

VDD2
IN2+

14
ANALOG

IN2-

11

DIGITAL

OUT2

15

VSS2
17
MODE

MODE

OSCILLATOR

2
SGND

1
OSC

STABILIZER

8

3

STAB

10

VSS1 VSS2

Fig.1 Block diagram (SOT243-1).

1998 Dec 01

9

MGR657

Philips Semiconductors

Preliminary specification

2 × 50 W class-D power amplifier

TDA8920

PINNING
SYMBOL

PIN

DESCRIPTION

OSC

1

oscillator frequency adjustment

SGND

2

signal ground (0 V)

IN1-

3

negative input channel 1

IN1+

4

positive input channel 1

VDD1

5

positive supply voltage 1

BOOT1

6

bootstrapping capacitor 1

OUT1

7

output 1

VSS1

8

negative supply voltage 1; note 1

STAB

9

internal stabilizer decoupling

VSS2

10

OUT2
BOOT2
VDD2

13

positive supply voltage 2

IN2+

14

positive input channel 2

IN2-

15

negative input channel 2

LIM

16

current limiting adjustment

MODE

17

mode select input

handbook, halfpage

OSC

1

SGND

2

IN1-

3

IN1+

4

VDD1

5

BOOT1

6

negative supply voltage 2; note 1

OUT1

7

11

output 2

VSS1

8

12

bootstrapping capacitor 2

STAB

9

TDA8920J

VSS2 10
OUT2 11
BOOT2 12
VDD2 13
IN2+ 14

Note

IN2- 15

1. The case of the package is connected to pins 8 and 10
(VSS1 and VSS2). Therefore no other voltage than VSS
should be connected to the case or the heatsink.

LIM 16
MODE 17
MGR658

Fig.2 Pin configuration (SOT243-1).

1998 Dec 01

4

Philips Semiconductors

Preliminary specification

2 × 50 W class-D power amplifier

TDA8920

FUNCTIONAL DESCRIPTION

Current limiting

The TDA8920 is a multi purpose audio power amplifier in
class-D technology. It contains two independent amplifiers
with high output power, high efficiency (90%), low
distortion and a low quiescent current. The amplifiers can
be connected in the following configurations:

With an external resistor RLIM connected between pin LIM
and VSS the maximum output current of the amplifiers can
be set. If pin LIM is short-circuited to VSS, then the
maximum output current is limited to 7 A. The relationship
between maximum output current and resistor value is
given by:

o Mono bridge-tied load amplifier
o Stereo single-ended amplifiers.

3

70.10
I O(max) = ------------------------------------------ [ A ]
3
?
?
? 10.10 + R LIM ?

The amplifier can be switched in three operating modes
with the mode select input:
o Standby mode, with a very low supply current
(practically zero)

Protections

o Mute mode; the amplifiers are operational but the audio
signal at the output is suppressed

Protections are included to avoid the device being
damaged at:

o Operating mode (amplifier fully operational) with output
signal.

o Over-temperature Tj & gt; 150 °C
o Short-circuit of the loudspeaker terminals: when
short-circuited the power dissipation is limited

For suppressing plop noise the amplifier will remain
automatically for approximately 500 ms in the mute
mode before switching to operating mode. During this
time the coupling capacitors at the input are fully
charged. An example of a switching circuit for driving the
mode select input is illustrated in Fig.3.

o A maximum current limiter which limits the maximum
output current to 7 A, or to the value set by RLIM. During
limiting the current is measured and when the current is
higher than 7 A, the amplifier is switched off within 3 us
and every 20 ms the IC tries to restart. The dissipation
will be low because of this low duty cycle.

Pulse Width Modulation (PWM) frequency

o ESD protection (human body model: 3000 V and
machine model: 300 V).

The output signal of the amplifier is a PWM signal with a
sample frequency of 500 kHz. The use of a second order
LC filter in the application results in an analog audio signal
across the loudspeaker. This switching frequency is fixed
by an external resistor ROSC connected between pin OSC
and pin SGND. With the resistor value given in the
application diagram, the oscillating frequency is typical
500 kHz. The oscillator frequency can be calculated using:

handbook, halfpage +5 V

9

5.10
f osc = ------------- [ Hz ]
R OSC

R

If two or more devices are used in the same audio system
it is advised to have both devices working on the same
oscillation frequency. This can be realized by connecting
all OSC pins together.

standby/on

pin MODE
R

mute
SGND
MGR660

Fig.3 Mode select input drive circuit.

1998 Dec 01

5

Philips Semiconductors

Preliminary specification

2 × 50 W class-D power amplifier

TDA8920

LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

-

?30

V

with respect to SGND -

5.5

V

short-circuit voltage of output pins

-

?30

V

IOSM

non-repetitive peak output current

-

10

A

IORM

repetitive peak output current

-

7.5

A

Ptot

total power dissipation

-

60

W

Tstg

storage temperature

-55

+150

°C

Tamb

operating ambient temperature

-40

+85

°C

Tvj

virtual junction temperature

-

150

°C

VDD

supply voltage

Vms

mode select switch voltage

Vsc

THERMAL CHARACTERISTICS
SYMBOL

PARAMETER

CONDITIONS

thermal resistance from junction to ambient

Rth(j-c)

UNIT

40

K/W

10

Rth(j-a)

VALUE

K/W

thermal resistance from junction to case

in free air

QUALITY SPECIFICATION
Quality according to "SNW-FQ-611-part E", if this type is used as an audio amplifier.
SWITCHING CHARACTERISTICS
VDD = ?25 V; Tamb = 25 °C; measured in Fig.5; unless otherwise specified.
SYMBOL

PARAMETER

MIN.

TYP.

MAX.

UNIT

fosc

oscillator frequency

400

500

600

kHz

VOSC(p-p)

voltage at tracking point (peak-to-peak value)

-

1.75

-

V

1998 Dec 01

6

Philips Semiconductors

Preliminary specification

2 × 50 W class-D power amplifier

TDA8920

DC CHARACTERISTICS
VDD = ?25 V; Tamb = 25 °C; measured in Fig.5; unless otherwise specified.
SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

Supplies
VDD

supply voltage range

?15

?25

?30

V

Iq(tot)

total quiescent current

-

50

60

mA

Istb

standby current

-

0.2

50

uA

note 1

Amplifier outputs
?VOO?

output offset voltage

on and mute

-

-

50

mV

??VOO?

delta output offset voltage

on <-> mute

-

-

30

mV

Mode select input; see Fig.4
Vms

input voltage range

note 2

0

-

5.5

V

Ims

input current

Vms = 5.5 V

-

-

tbf

uA

Vth1+

threshold voltage

standby -> mute; note 2

-

-

2

V

Vth1-

threshold voltage

mute -> standby; note 2

1

-

-

V

Vms(hys1)

hysteresis ?(Vth1+) - (Vth1-)?

-

200

-

mV

Vth2+

threshold voltage

mute -> on; note 2

-

-

4

V

Vth2-

threshold voltage

on -> mute; note 2

3

-

-

V

Vms(hys2)

hysteresis ?(Vth2+) - (Vth2-)?

-

200

-

mV

Notes
1. The circuit is DC adjusted at VDD = ?15 V to ?30 V.
2. Referenced to SGND (0 V).

handbook, full pagewidth

on

mute

standby
Vms(hys1)
Vth1-

Vms(hys2)

Vth1+

Vth2-

Vms

Vth2+
MGR662

Fig.4 Mode select transfer characteristic.

1998 Dec 01

7

Philips Semiconductors

Preliminary specification

2 × 50 W class-D power amplifier

TDA8920

AC CHARACTERISTICS
Stereo single-ended application
VDD = ?25 V; RL = 8 Ohm; fi = 1 kHz; Tamb = 25 °C; measured in Fig.5; unless otherwise specified.
SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

-

W

tbf

35

-

W

-

40

-

W

-

50

-

W

fi = 1 kHz

-

0.1

0.15

%

fi = 10 kHz

total harmonic distortion

30

THD = 10%; Vp = ?30 V
THD

tbf

THD = 0.5%; Vp = ?30 V

output power

THD = 0.5%
THD = 10%

Po

-

0.2

-

%

29

30

31

dB

Po = 1 W; note 1

Gv(cl)

closed loop voltage gain

?

efficiency

Po = tbf W; fi = 1 kHz; note 2

85

90

-

%

SVRR

supply voltage ripple
rejection

on; note 3

-

60

-

dB

on; note 4

tbf

tbf

-

dB

mute; note 3

-

60

-

dB

standby; note 3

-

80

-

dB

80

120

on; note 5

-

100

200

uV

on; note 6

-

tbf

-

uV

mute; note 7

-

100

-

uV

note 8

50

tbf

-

dB

-

-

1

dB

-

-

500

uV

-

65

-

dB

?Zi?

input impedance

Vn(o)

noise output voltage

?cs

channel separation

??Gv?

channel unbalance

Vo

output signal

CMRR

common mode rejection ratio Vi(CM)(rms) = 1 V

mute; note 9

kOhm

Notes
1. Total harmonic distortion is measured in a bandwidth of 22 Hz to 22 kHz, using an 11th-order low-pass filter. When
distortion is measured using a lower order low-pass filter a significantly higher value will be found, due to the
switching frequency outside the audio band.
2. Output power measured across the loudspeaker load.
3. Vripple = Vripple(max) = 2 V (p-p); fi = 100 Hz; Rs = 0 Ohm.
4. Vripple = Vripple(max) = 2 V (p-p); fi = 1 kHz; Rs = 0 Ohm.
5. B = 22 Hz to 22 kHz; Rs = 0 Ohm.
6. B = 22 Hz to 22 kHz; Rs = 10 kOhm.
7. B = 22 Hz to 22 kHz; independent of Rs.
8. Po = tbf W; Rs = 0 Ohm.
9. Vi = Vi(max) = 1 V (RMS).

1998 Dec 01

8

Philips Semiconductors

Preliminary specification

2 × 50 W class-D power amplifier

TDA8920

Mono bridge-tied load application
VDD = ?25 V; RL = 8 Ohm; fi = 1 kHz; Tamb = 25 °C; measured in Fig.6; unless otherwise specified.
SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

-

W

tbf

130

-

W

-

150

-

W

-

190

-

W

fi = 1 kHz

-

0.1

0.15

%

fi = 10 kHz

total harmonic distortion

100

THD = 10%; Vp = ?30 V
THD

tbf

THD = 0.5%; Vp = ?30 V

output power

THD = 0.5%
THD = 10%

Po

-

0.2

-

%

Po = 1 W; note 1

Gv(cl)

closed loop voltage gain

35

36

37

dB

?

efficiency

Po = tbf W; fi = 1 kHz; note 2

tbf

tbf

-

%

SVRR

supply voltage ripple rejection

on; note 3

-

66

-

dB

on; note 4

tbf

-

-

dB

mute; note 3

-

66

-

dB

standby; note 3

80

-

-

dB

40

60

-

kOhm

?Zi?

input impedance

Vn(o)

noise output voltage

on; note 5

-

140

280

uV

on; note 6

-

tbf

-

uV

mute; note 7

-

140

-

uV

Vo

output signal

mute; note 8

-

-

tbf

mV

CMRR

common mode rejection ratio

Vi(CM)(rms) = 1 V

-

65

-

dB

Notes
1. Total harmonic distortion is measured in a bandwidth of 22 Hz to 22 kHz, using an 11th-order low-pass filter. When
distortion is measured using a lower order low-pass filter a significantly higher value will be found, due to the
switching frequency outside the audio band.
2. Output power measured across the loudspeaker load.
3. Vripple = Vripple(max) = 2 V (p-p); fi = 100 Hz; Rs = 0 Ohm.
4. Vripple = Vripple(max) = 2 V (p-p); fi = 1 kHz; Rs = 0 Ohm.
5. B = 22 Hz to 22 kHz; Rs = 0 Ohm.
6. B = 22 Hz to 22 kHz; Rs = 10 kOhm.
7. B = 22 Hz to 22 kHz; independent of Rs.
8. Vi = Vi(max) = 1 V (RMS).

1998 Dec 01

9

Philips Semiconductors

Preliminary specification

2 × 50 W class-D power amplifier

TDA8920

APPLICATION AND TEST INFORMATION

VDD

handbook, full pagewidth

VDD2

VDD1

13

5

100
nF

2200
uF

6 BOOT1

25 V

CBOOT1
100 nF

100 nF

Vi1

IN1+
IN1-

47 nF

4
ANALOG

OUT1

7

DIGITAL

100 uH

3

390
nF

SGND

8Ohm

VSS1
LIM 16
Vi2

PROTECTION

TDA8920J

100 nF

BOOT2

12
VDD2

RLIM

SGND

47 nF

IN2+ 14
IN2- 15

0V

CBOOT2

ANALOG

11 OUT2

DIGITAL

100 uH
390
nF

8Ohm

100
nF

2200
uF

VSS2
MODE 17
MODE

OSCILLATOR

STABILIZER

9

STAB
CSTAB

2

1

8

SGND

OSC

VSS1 VSS2

Vms
ROSC
10 kOhm

10

25 V

VSS
SGND
MGR663

Maximum value of CBOOT = tbf nF.
Filter coil is type tbf, Rs &amp; lt; tbf Ohm.
The case of the package is internally connected to VSS.

Fig.5 Application circuit for stereo single-ended application (SOT243-1).

1998 Dec 01

10

Philips Semiconductors

Preliminary specification

2 × 50 W class-D power amplifier

TDA8920

VDD

handbook, full pagewidth

VDD2

VDD1

13

5

100
nF

2200
uF

6 BOOT1

25 V

CBOOT1
100 nF
Vi

IN1+

100 nF

IN1-

47 nF

4
ANALOG

OUT1

7

DIGITAL

100 uH

3

390
nF

8Ohm

VSS1
LIM 16

PROTECTION

TDA8920J
BOOT2

12
VDD2

RLIM

SGND

47 nF

IN2+ 14
IN2- 15

0V

CBOOT2

ANALOG

11 OUT2

DIGITAL

100 uH
390
nF
VSS2

MODE 17
MODE

OSCILLATOR

STABILIZER

9

STAB
CSTAB

2

1

8

SGND

OSC

100
nF

VSS1 VSS2

Vms
ROSC
10 kOhm

10

2200
uF

25 V

VSS
SGND
MGR664

Maximum value of CBOOT = tbf nF.
Filter coil is type tbf, Rs &amp; lt; tbf Ohm.
The case of the package is internally connected to VSS.

Fig.6 Application circuit for mono bridge-tied load application (SOT243-1).

1998 Dec 01

11

Philips Semiconductors

Preliminary specification

2 × 50 W class-D power amplifier

TDA8920

PACKAGE OUTLINES
DBS17P: plastic DIL-bent-SIL power package; 17 leads (lead length 12 mm)

SOT243-1

non-concave
Dh

x

D

Eh

view B: mounting base side

d

A2

B
j

E
A

L3

L

Q
c

1

vM

17
e1

Z

bp

e

e2

m

wM

0

5

10 mm

scale
DIMENSIONS (mm are the original dimensions)
UNIT

A

A2

bp

c

D (1)

d

Dh

E (1)

e

mm

17.0
15.5

4.6
4.2

0.75
0.60

0.48
0.38

24.0
23.6

20.0
19.6

10

12.2
11.8

2.54

e1

e2

1.27 5.08

Eh

j

L

L3

m

Q

v

w

x

Z (1)

6

3.4
3.1

12.4
11.0

2.4
1.6

4.3

2.1
1.8

0.8

0.4

0.03

2.00
1.45

Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION

REFERENCES
IEC

JEDEC

EIAJ

ISSUE DATE
95-03-11
97-12-16

SOT243-1

1998 Dec 01

EUROPEAN
PROJECTION

12

Philips Semiconductors

Preliminary specification

2 × 50 W class-D power amplifier

TDA8920

HSOP20: heatsink small outline package; 20 leads

SOT418-1

A

E
D

x

X

c
E2

y

HE

vM A

D1
D2
1

10
pin 1 index
Q
A2

A

E1

(A3)

A1

?
Lp
detail X
20

11

Z

wM

bp

e

0

5

10 mm

scale
DIMENSIONS (mm are the original dimensions)
UNIT
mm

A
A1
max.

A2

A3

0.3
0.1

3.5
3.2

0.35

3.7

D1

D2

E(1)

E1

E2

e

HE

Lp

Q

0.53 0.32 16.0 13.0
0.40 0.23 15.8 12.6

1.1
0.9

11.1
10.9

6.2
5.8

2.9
2.5

1.27

14.5
13.9

1.1
0.8

1.7
1.5

bp

c

D(1)

v

w

x

0.25 0.25 0.03

y

Z

?

0.1

2.5
2.0




Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION

REFERENCES
IEC

JEDEC

EIAJ

ISSUE DATE
97-11-03
98-02-25

SOT418-1

1998 Dec 01

EUROPEAN
PROJECTION

13

Philips Semiconductors

Preliminary specification

2 × 50 W class-D power amplifier

TDA8920
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.

SOLDERING
Introduction
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our "Data Handbook IC26; Integrated Circuit Packages"
(document order number 9398 652 90011).

WAVE SOLDERING
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mount components are mixed on
one printed-circuit board. However, wave soldering is not
always suitable for surface mount ICs, or for printed-circuit
boards with high population densities. In these situations
reflow soldering is often used.

To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
o Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.

Through-hole mount packages
SOLDERING BY DIPPING OR BY SOLDER WAVE

o For packages with leads on two sides and a pitch (e):

The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joints for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.

- larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
- smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.

The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg(max)). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.

The footprint must incorporate solder thieves at the
downstream end.
o For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

MANUAL SOLDERING
Apply the soldering iron (24 V or less) to the lead(s) of the
package, either below the seating plane or not more than
2 mm above it. If the temperature of the soldering iron bit
is less than 300 °C it may remain in contact for up to
10 seconds. If the bit temperature is between
300 and 400 °C, contact may be up to 5 seconds.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Surface mount packages
REFLOW SOLDERING

MANUAL SOLDERING

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
1998 Dec 01

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
14

Philips Semiconductors

Preliminary specification

2 × 50 W class-D power amplifier

TDA8920

Suitability of IC packages for wave, reflow and dipping soldering methods
SOLDERING METHOD
MOUNTING

PACKAGE
WAVE

REFLOW(1)

DIPPING

Through-hole mount DBS, DIP, HDIP, SDIP, SIL

suitable(2)

-

suitable

Surface mount

not suitable

suitable

-

suitable

-

suitable

-

not

recommended(4)(5)

suitable

-

not

recommended(6)

suitable

-

BGA, SQFP

suitable(3)

HLQFP, HSQFP, HSOP, HTSSOP, SMS

not

PLCC(4), SO, SOJ

suitable

LQFP, QFP, TQFP
SSOP, TSSOP, VSO
Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods".
2. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board.
3. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
5. Wave soldering is only suitable for LQFP, QFP and TQFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
6. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
DEFINITIONS
Data sheet status
Objective specification

This data sheet contains target or goal specifications for product development.

Preliminary specification

This data sheet contains preliminary data; supplementary data may be published later.

Product specification

This data sheet contains final product specifications.

Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

1998 Dec 01

15

Philips Semiconductors - a worldwide company
Argentina: see South America
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Czech Republic: see Austria
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Tel. +60 3 750 5214, Fax. +60 3 757 4880
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Tel. +9-5 800 234 7381

Middle East: see Italy
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,
Tel. +31 40 27 82785, Fax. +31 40 27 88399
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,
Tel. +64 9 849 4160, Fax. +64 9 849 7811
Norway: Box 1, Manglerud 0612, OSLO,
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Pakistan: see Singapore
Philippines: Philips Semiconductors Philippines Inc.,
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474
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Portugal: see Spain
Romania: see Italy
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Tel. +7 095 755 6918, Fax. +7 095 755 6919
Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,
Tel. +65 350 2538, Fax. +65 251 6500
Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,
2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,
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04547-130 S?O PAULO, SP, Brazil,
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Spain: Balmes 22, 08007 BARCELONA,
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Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. +46 8 5985 2000, Fax. +46 8 5985 2745
Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. +41 1 488 2741 Fax. +41 1 488 3263
Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
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Tel. +66 2 745 4090, Fax. +66 2 398 0793
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Tel. +90 212 279 2770, Fax. +90 212 282 6707
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381
Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 625 344, Fax.+381 11 635 777

For all other countries apply to: Philips Semiconductors,
International Marketing &amp; Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825

Internet: http://www.semiconductors.philips.com

(C) Philips Electronics N.V. 1998

SCA60

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Printed in The Netherlands

545102/25/01/pp16

Date of release: 1998 Dec 01

Document order number:

9397 750 04343


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