Mam identyczną sytuację z Lenovo L340-15IRH (NM-C362) po uszkodzeniu gniazda zasilania. ? Czyli co : - brak zasilania cpu ? - brak 3/5V na LV5083A/ * PU501 LV5075BGQV PL3502 - 5V PL3501 - 3.3V PL503 - 1.05V - zasilanie kbc IT8586E fxa i SPI Bios ? - o tym modelu jest tylko 1-en temat na tym forum Link_ wsad bios_BGCN31WW * wsad kbc jest w There is in the dump Bios . EC FW with 600000h. Search ->Site EC Serial numbers from the address 632000 to 633FFF.. Podaj jakie pomiary do tej pory zrobieś ? p.s płyta NM-C362 /- C361 oparta o chipset HM370 (sr40b) - charger BQ24780S * opcja dodatk. gpu GTX1650 4Gb SM (płatny) Compal (LCFC) NM-C362 FG541 FG741 REV 0.1 - Lenovo L340-15IRH np. Link_ po zdaniu testu ** płatny Link lub patrz zał.
A
B
C
D
E
LCFC Confidential
1
1
L340-IRH +N18P MB Schematics Document
Coffee Lake-R with DDR4 + Nvidia N18P-G0
2
2
2018-09-21
REV:0.1
3
3
4
4
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/08/20
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
A
B
https://Dr-Bios.com
C
Cover Page
2018/09/20
Deciphered Date
Size Document Number
Custom
Date:
D
Rev
0.1
FG541/FG741
Thursday, January 03, 2019
E
Sheet
1
of
69
A
B
C
D
E
LCFC confidential
NV: N18P-G0
Package: GB4D-128
Page 24~30
PCI-Express
16x Gen3
PCIe Port 1~4
Intel CPU
Coffee Lake-H 30/35W
DDR4 SO-DIMM x1
Page 12
Memory Bus (Dual Channel)
BGA-1440
42mm*28mm
1
VRAM: 256M*32
GDDR5*4: 4GB
Page 31~34
1
DDR4 Memory Down
1.2V DDR4 2400MT/s
4pcs x16
Page 13
Page 5~11
DMI *4
1GB/s * 4 Total 4GB/s
HDMI Conn.
USB3.0 Left Conn
USB3.0 x1
USB2.0 x1
HDMI 2.0 (DDI 1)
USB3.0 Port1
USB2.0 Port1
Page 39
USB3.0 Left Conn
USB3.0 x1
USB2.0 x1
Page 46
eDP x2 Lane
Int. Camera Conn.
USB3.0 x1
USB2.0 x1
USB2.0 x1
USB2.0 Port4
2
USB3.0 Port3
USB2.0 Port3
eDP x2 Lane
eDP Conn
Page 46
Type-C IC
Page 48
Intel PCH
Cannon Lake-H
Int. MIC Conn.
Page 38
SATA HDD
Page 47
Type-C Conn
Realtek RTS5449E
SATA Gen3 x1
SATA Port0
PCIe Gen1 x1
NGFF WLAN & BT/CNVi
USB2.0 x1
FCBGA
26mm*24mm
PCIE SSD
(or Optane Memory)
PCIe Port13
USB2.0 Port14
CNVi
M.2 CRF Module
Page 45
PCIe Port 9~12
PCIe Gen1 x1
3
Page 45
LAN Chip
Realtek_RTL8111GUL
SPI
SPK Conn.
Page 43
3
SPI ROM (16MB)
W25Q128JVSIQ
Codec
Page 18
HD Audio
HP & Mic Combo Conn.
RJ45 Conn.
Page 42
PCIe Port5
Page 35
2
Page 48
I2C
Realtek ALC3287
Page 3~16
Page 35
LPC
Page 35
TPM (Reserved)
USB2.0 Port5
Z32H320TC
EC
ITE IT8586E-LQFP
Page 49
4
Page 50
Thermal Sensor
(Reserved)
Int.KBD
Page 50
4
Page 44
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/08/20
B
https://Dr-Bios.com
C
Block Diagram
2018/09/20
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
A
Page 37
Touch Pad
D
Size Document Number
Custom
Date:
Rev
0.1
FG541/FG741
Thursday, January 03, 2019
E
Sheet
2
of
69
A
B
Voltage Rails ( O -- & gt; Means ON
C
D
E
, X -- & gt; Means OFF )
SIGNAL
STATE
SLP_S3# SLP_S4# SLP_S5#
+VALW
+V
+VS
Clock
Full ON
HIGH
HIGH
HIGH
ON
ON
ON
ON
S3 (Suspend to RAM)
LOW
HIGH
HIGH
ON
ON
OFF
OFF
S4 (Suspend to Disk)
LOW
LOW
LOW
ON
OFF
OFF
OFF
S5 (Soft OFF)
LOW
LOW
LOW
ON
OFF
OFF
OFF
Power Plane
+3VALW
+5VALW
+3VALW_PCH
+1.8VALW
+1.0VALW
1
V20B+
+5VS
+1.2V
+3VS
+VCCIO
+2.5V_DDR
1
+VCCSTG
+VCCSA
+VCCST
+VCC_GT
+CPU_CORE
State
+0.6VS
HSIO PORT
5
O
S5 S4
AC & Battery
don't exist
X
X
X
X
Touch Panel
Bluetooth
8
USB2.0
Cardreader
Camera
NC
NC
1~4
S5 S4
Battery only
O
X
Finger Print
5
10
O
O
USB3.0 Conn Left
9
S5 S4
AC Only
O
USB Type-C
7
O
USB3.0 Conn Left
2
X
X
DGPU
X
5
SOURCE
BATT
Charger
DGPU
IT8586E
Memory
Down
PCH
PMIC
SODIMM
Thermal
Sensor
SATA HDD
SATA ODD
Optane
Memory
X4 PCIE
3
EC_SMB_CK1
IT8586E
EC_SMB_DA1
+3VL_EC
EC_SMB_CK2
IT8586E
EC_SMB_DA2
+3VS
EC_SMB_CK3
IT8586E
EC_SMB_DA3
+3VL_EC
PCH_SMB_CLK
PCH
V
V
X
V
X
X
X
X
X
V
V
+3VG_AON
X
X
SATA
X
V
+3VS
X
V
X
X
V
X
HDD
ODD
1B
used as PCIE
+3VALW_PCH
X
X
V
V
X
X
X
V
X
For 15 " or 17 " part
For Cannonlake part
For ME part
For TPM part
For C cost down
For Dual MIC part
For EMC part
2
For EMC 15 " part
For EMC nu-stuff part
For EMC PX part
For EMC PX nu-stuff part
For ES CPU
For EXO GPU
For touch screen part
For nu-touch part
For GPU part
For NV GPU part
For AMD GPU part
For VRAM rank A part
For VRAM rank B part
For Realtek SD part
For single MIC part
3
For single VRAN rank part
For dual VRAN rank part
For UMA part
X
+3VL_EC
X
X
X
X
X
+3VALW_PCH
EC SMBus2 address
+3VS
EC SMBus3 address
V
+3VS
PCH SM Bus address
Device
Address
Device
Address
Device
Address
Device
Address
Smart Battery
4
For 17 " part
used as PCIE
2
X
+3VL_EC
PCH_SMB_DATA +3VALW_PCH
EC SMBus1 address
X
0
1A
X
For 15 " part
TPM@
UMA@
WLAN
9~12
WLAN
WiMAX
6
8
SMBUS Control Table
LAN
7
PCIE
For 14 " part
ME@
TS@
TS_NS@
DIS@
OPT@
PX@
RANKA@
RANKB@
Realtek_SD@
SINGLEMIC@
SINGLERANK@
DUALRANK@
X
X
Not stuff
Cannonlake@
CD@
DUALMIC@
EMC@
EMC_15@
EMC_NS@
EMC_PX@
EMC_PXNS@
ES@
EXO@
X4 PCIE
X
BTO Item
NC
6
2
O
NC
4
S3
Battery only
O
O
NC
3
O
O
4
1
S3
O
USB3.0 Conn Left
6
O
USB Type-C
3
S0
USB3.0 Conn Left
2
USB3.0
BOM Structure
@
14@
15@
17@
15or17@
Function
1
need to update
Thermal Sensor(NCT7718W)
1001_100xb
PMIC
need to update
DDR4 SODIMM
need to update
Charger
0001 0010 b
PCH
need to update
W lan
Reserved
DGPU
need to update
4
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/08/20
https://Dr-Bios.com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
A
B
C
Notes List
2018/09/20
Deciphered Date
D
Size Document Number
Custom
Date:
Rev
0.1
FG541/FG741
Thursday, January 03, 2019
E
Sheet
3
of
69
5
4
3
2
1
+3.3V_LDO_RTS5400
2.2K
RTS5400
+3VALW
RTS5400_SM_SCL
RTS5400_SM_SDA
D
D
+3VALW
Control
Dual MOS
2.2K
EC_SMB_CK0
EC_SMB_DA0
+3VALW_R
Battery JBATT2
2.2K
EC
IT8226
Change IC PU102
BQ24780SRUYR
EC_SMB_CK1
EC_SMB_DA1
C
C
+3VS_AON
+3VALW_PCH
2.2K
2.2K
NV GPU( UV1 )
+3VS
PCH( UH1 )
VGA_SMB_CK2
VGA_SMB_DA2
Dual MOS
2.2K
SML1CLK
SML1DATA
+3VS_AON
Control
Dual MOS
+3VS
Control
Thermal sensor U1
F75303M
EC_SMB_CK2
EC_SMB_DA2
B
B
SMBUS Control Table
SOURCE
DDR1
DDR2
WLAN
VGA
EC_SMB_CK1
2.2K
2.2K
X
IT8226
V
EC_SMB_DA2
PCH
EC_SMB_DA1
+3VS
IT8226
+3VALW
EC_SMB_CK2
+3VALW_PCH
BATT
IT8586E
SODIMM
WLAN
WiMAX
X
X
Thermal
Sensor
PCH
TP
Module
charger
X
X
X
V
V
V
X
X
X
X
TP
+3VS
V
+3VGS
X
V
+3VALW
V
+3VS
X
X
X
V
V
+3VS
+3VS
PCH_SMB_CLK
PCH
PCH_SMB_DATA +3VALW_PCH
+3VS
Control
Dual MOS
EC SM Bus1 address
X
X
+3VS
+3VALW_PCH
X
V
+3VALW_PCH
EC SM Bus2 address
VGA_SMB_CK2
VGA_SMB_DA2
Device
PCH SM Bus address
Address
DDR DIMMA
1010 000Xb
DDR DIMMB
1010 010Xb
VGA
0x41(default)
WLAN
Rsvd
need to update
0xD4
Device
Smart Battery
0X16
Charger
0001 0010 b
Security Classification
Issued Date
Device
1001_100xb
RTS5400
PCH_SMBCLK
PCH_SMBDATA
Address
PCH
A
Thermal Sensor F75303M
T itle
LC Future Center Secret Data
2015/02/26
Deciphered Date
2018/09/20
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Blank4
Size
Document Number
Custom
4
3
https://Dr-Bios.com
2
1
Rev
0.1
FG541/FG741
Thursday, January 03, 2019
Date:
5
A
Sheet
4
of
69
5
4
3
2
1
{25} PCIE_CRX_GTX_N[0..15]
{25} PCIE_CRX_GTX_P[0..15]
PCIE_CTX_C_GRX_N[0..15]
{25}
PCIE_CTX_C_GRX_P[0..15]
{25}
D
D
PCIE_CRX_GTX_P15
PCIE_CRX_GTX_N15
PCIE_CRX_GTX_P14
PCIE_CRX_GTX_N14
UC1C
E25
D25
E24
F24
PCIE_CRX_GTX_P13
PCIE_CRX_GTX_N13
E23
D23
PCIE_CRX_GTX_P12
PCIE_CRX_GTX_N12
E22
F22
PCIE_CRX_GTX_P11
PCIE_CRX_GTX_N11
E21
D21
PCIE_CRX_GTX_P10
PCIE_CRX_GTX_N10
E20
F20
PCIE_CRX_GTX_P9
PCIE_CRX_GTX_N9
E19
D19
PCIE_CRX_GTX_P8
PCIE_CRX_GTX_N8
E18
F18
PCIE_CRX_GTX_P7
PCIE_CRX_GTX_N7
D17
E17
C
PCIE_CRX_GTX_P6
PCIE_CRX_GTX_N6
F16
E16
PCIE_CRX_GTX_P5
PCIE_CRX_GTX_N5
D15
E15
PCIE_CRX_GTX_P4
PCIE_CRX_GTX_N4
F14
E14
PCIE_CRX_GTX_P3
PCIE_CRX_GTX_N3
D13
E13
PCIE_CRX_GTX_P2
PCIE_CRX_GTX_N2
PCIE_CRX_GTX_P1
PCIE_CRX_GTX_N1
RC1
2
F10
E10
PEG_COMP
1 24.9_0402_1%
CAD Note:
Place R_comp inside CPU cavity
Trace width=12 mils ,Spacing=15mil
Max length= 400 mils.
{19} DMI_CRX_PTX_P0
B
D11
E11
PCIE_CRX_GTX_P0
PCIE_CRX_GTX_N0
VCCIO
F12
E12
G2
DMI_CRX_PTX_P0
DMI_CRX_PTX_N0
{19} DMI_CRX_PTX_P3
{19} DMI_CRX_PTX_N3
D5
E5
DMI_CRX_PTX_P3
DMI_CRX_PTX_N3
{19} DMI_CRX_PTX_P2
{19} DMI_CRX_PTX_N2
E6
F6
DMI_CRX_PTX_P2
DMI_CRX_PTX_N2
{19} DMI_CRX_PTX_P1
{19} DMI_CRX_PTX_N1
D8
E8
DMI_CRX_PTX_P1
DMI_CRX_PTX_N1
{19} DMI_CRX_PTX_N0
J8
J9
PEG_RXP_0
PEG_RXN_0
PEG_RXP_1
PEG_RXN_1
PEG_TXP_0
PEG_TXN_0
PEG_TXP_1
PEG_TXN_1
PEG_RXP_2
PEG_RXN_2
PEG_TXP_2
PEG_TXN_2
PEG_RXP_3
PEG_RXN_3
PEG_TXP_3
PEG_TXN_3
PEG_RXP_4
PEG_RXN_4
PEG_RXP_5
PEG_RXN_5
PEG_RXP_6
PEG_RXN_6
PEG_TXP_4
PEG_TXN_4
PEG_TXP_5
PEG_TXN_5
PEG_TXP_6
PEG_TXN_6
PEG_RXP_7
PEG_RXN_7
PEG_TXP_7
PEG_TXN_7
PEG_RXP_8
PEG_RXN_8
PEG_TXP_8
PEG_TXN_8
PEG_RXP_9
PEG_RXN_9
PEG_TXP_9
PEG_TXN_9
PEG_RXP_10
PEG_RXN_10
PEG_RXP_11
PEG_RXN_11
PEG_RXP_12
PEG_RXN_12
PEG_TXP_10
PEG_TXN_10
PEG_TXP_11
PEG_TXN_11
PEG_TXP_12
PEG_TXN_12
PEG_RXP_13
PEG_RXN_13
PEG_TXP_13
PEG_TXN_13
PEG_RXP_14
PEG_RXN_14
PEG_TXP_14
PEG_TXN_14
PEG_RXP_15
PEG_RXN_15
PEG_TXP_15
PEG_TXN_15
B25
A25
PCIE_CTX_GRX_P15
PCIE_CTX_GRX_N15
OPT@
OPT@
CC32 1
CC16 1
2 0.22U_0201_6.3V6-K
2 0.22U_0201_6.3V6-K
PCIE_CTX_C_GRX_P15
PCIE_CTX_C_GRX_N15
B24
C24
PCIE_CTX_GRX_P14
PCIE_CTX_GRX_N14
OPT@
OPT@
CC31 1
CC15 1
2 0.22U_0201_6.3V6-K
2 0.22U_0201_6.3V6-K
PCIE_CTX_C_GRX_P14
PCIE_CTX_C_GRX_N14
B23
A23
PCIE_CTX_GRX_P13
PCIE_CTX_GRX_N13
OPT@
OPT@
CC30 1
CC14 1
2 0.22U_0201_6.3V6-K
2 0.22U_0201_6.3V6-K
PCIE_CTX_C_GRX_P13
PCIE_CTX_C_GRX_N13
B22
C22
PCIE_CTX_GRX_P12
PCIE_CTX_GRX_N12
OPT@
OPT@
CC29 1
CC13 1
2 0.22U_0201_6.3V6-K
2 0.22U_0201_6.3V6-K
PCIE_CTX_C_GRX_P12
PCIE_CTX_C_GRX_N12
B21
A21
PCIE_CTX_GRX_P11
PCIE_CTX_GRX_N11
OPT@
OPT@
CC28 1
CC12 1
2 0.22U_0201_6.3V6-K
2 0.22U_0201_6.3V6-K
PCIE_CTX_C_GRX_P11
PCIE_CTX_C_GRX_N11
B20
C20
PCIE_CTX_GRX_P10
PCIE_CTX_GRX_N10
OPT@
OPT@
CC27 1
CC11 1
2 0.22U_0201_6.3V6-K
2 0.22U_0201_6.3V6-K
PCIE_CTX_C_GRX_P10
PCIE_CTX_C_GRX_N10
B19
A19
PCIE_CTX_GRX_P9
PCIE_CTX_GRX_N9
OPT@
OPT@
CC26 1
CC10 1
2 0.22U_0201_6.3V6-K
2 0.22U_0201_6.3V6-K
PCIE_CTX_C_GRX_P9
PCIE_CTX_C_GRX_N9
B18
C18
PCIE_CTX_GRX_P8
PCIE_CTX_GRX_N8
OPT@
OPT@
CC25 1
CC9 1
2 0.22U_0201_6.3V6-K
2 0.22U_0201_6.3V6-K
PCIE_CTX_C_GRX_P8
PCIE_CTX_C_GRX_N8
A17
B17
PCIE_CTX_GRX_P7
PCIE_CTX_GRX_N7
OPT@
OPT@
CC24 1
CC8 1
2 0.22U_0201_6.3V6-K
2 0.22U_0201_6.3V6-K
PCIE_CTX_C_GRX_P7
PCIE_CTX_C_GRX_N7
C16
B16
PCIE_CTX_GRX_P6
PCIE_CTX_GRX_N6
OPT@
OPT@
CC23 1
CC7 1
2 0.22U_0201_6.3V6-K
2 0.22U_0201_6.3V6-K
PCIE_CTX_C_GRX_P6
PCIE_CTX_C_GRX_N6
A15
B15
PCIE_CTX_GRX_P5
PCIE_CTX_GRX_N5
OPT@
OPT@
CC22 1
CC6 1
2 0.22U_0201_6.3V6-K
2 0.22U_0201_6.3V6-K
PCIE_CTX_C_GRX_P5
PCIE_CTX_C_GRX_N5
C14
B14
PCIE_CTX_GRX_P4
PCIE_CTX_GRX_N4
OPT@
OPT@
CC21 1
CC5 1
2 0.22U_0201_6.3V6-K
2 0.22U_0201_6.3V6-K
PCIE_CTX_C_GRX_P4
PCIE_CTX_C_GRX_N4
A13
B13
PCIE_CTX_GRX_P3
PCIE_CTX_GRX_N3
OPT@
OPT@
CC20 1
CC4 1
2 0.22U_0201_6.3V6-K
2 0.22U_0201_6.3V6-K
PCIE_CTX_C_GRX_P3
PCIE_CTX_C_GRX_N3
C12
B12
PCIE_CTX_GRX_P2
PCIE_CTX_GRX_N2
OPT@
OPT@
CC19 1
CC3 1
2 0.22U_0201_6.3V6-K
2 0.22U_0201_6.3V6-K
PCIE_CTX_C_GRX_P2
PCIE_CTX_C_GRX_N2
A11
B11
PCIE_CTX_GRX_P1
PCIE_CTX_GRX_N1
OPT@
OPT@
CC18 1
CC2 1
2 0.22U_0201_6.3V6-K
2 0.22U_0201_6.3V6-K
PCIE_CTX_C_GRX_P1
PCIE_CTX_C_GRX_N1
C10
B10
PCIE_CTX_GRX_P0
PCIE_CTX_GRX_N0
OPT@
OPT@
CC17 1
CC1 1
2 0.22U_0201_6.3V6-K
2 0.22U_0201_6.3V6-K
PCIE_CTX_C_GRX_P0
PCIE_CTX_C_GRX_N0
B8
A8
DMI_CTX_PRX_P0
DMI_CTX_PRX_N0
C6
B6
DMI_CTX_PRX_P1
DMI_CTX_PRX_N1
B5
A5
DMI_CTX_PRX_P2
DMI_CTX_PRX_N2
D4
B4
DMI_CTX_PRX_P3
DMI_CTX_PRX_N3
C
PEG_RCOMP
DMI_RXP_0
DMI_RXN_0
DMI_TXP_0
DMI_TXN_0
DMI_RXP_1
DMI_RXN_1
DMI_TXP_1
DMI_TXN_1
DMI_RXP_2
DMI_RXN_2
DMI_TXP_2
DMI_TXN_2
DMI_RXP_3 3 OF 13 DMI_TXP_3
DMI_RXN_3
DMI_TXN_3
COFFEELAKE-H-CPU_BGA1440
@
DMI_CTX_PRX_P0 {19}
DMI_CTX_PRX_N0 {19}
B
DMI_CTX_PRX_P1 {19}
DMI_CTX_PRX_N1 {19}
DMI_CTX_PRX_P2 {19}
DMI_CTX_PRX_N2 {19}
DMI_CTX_PRX_P3 {19}
DMI_CTX_PRX_N3 {19}
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/02/26
2018/09/20
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
5
4
https://Dr-Bios.com
3
CPU (1/7) DMI,PEG
Size Document Number
Custom
2
Rev
0.1
FG541/FG741
Date:
Thursday, January 03, 2019
1
Sheet
5
of
69
4
3
2
CPU_BCLK
CPU_BCLK#
1
RC66
100_0402_1%
CC1404
0.1u_0201_10V6K
2
E31
D31
BCLKP
BCLKN
CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
PCI_BCLKP
PCI_BCLKN
CLK24P
CLK24N
1
2
2
{17} PCH_CPU_NSSC_CLK
{17} PCH_CPU_NSSC_CLK#
D35
C36
CPU_NSSC_CLK
CPU_NSSC_CLK#
{17} PCH_CPU_PCIBCLK
{17} PCH_CPU_PCIBCLK#
B31
A32
CPU_PCIBCLK
CPU_PCIBCLK#
{17} PCH_CPU_BCLK
{17} PCH_CPU_BCLK#
VCCST
RC76
RC3043
100_0402_1% 56.2_0402_1%
2
D
1
1
@
RC65
RC3
RC14
RC9
{63} SVID_ALERT#
{63} SVID_CLK
{63} SVID_DATA
{49,61,63} H_PROCHOT#
RC7
VCCSTG
1
2 1K_0402_5%
1
1
1
1
CC178
@
220_0402_5%
0_0402_5%
0_0402_5%
499_0402_1%
1
2
VR_SVID_ALRT#_R
VR_SVID_CLK
VR_SVID_DAT
H_PROCHOT#_R
BH31
BH32
BH29
BR30
.1U_0402_10V6-K
2
2
2
2
DDR_PG_CTRL
BT13
VIDALERT#
VIDSCK
VIDSOUT
PROCHOT#
DDR_VTT_CNTL
CFG_17
CFG_16
CFG_19
CFG_18
VCCST_PWRGD
BPM#_0
BPM#_1
BPM#_2
BPM#_3
BN25
BN27
BN26
BN28
BR20
BM20
BT20
BP20
BR23
BR22
BT23
BT22
BM19
BR19
BP19
BT19
CFG0
CFG1 @
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8 @
CFG9 @
CFG10@
CFG11@
CFG12@
CFG13@
CFG14@
CFG15@
BN23
BP23
BP22
BN22
BR27
BT27
BM31
BT30
PAD
1
1
CFG STRAPS for CPU
UC1E
TC89
Stall reset sequence after PCU PLL lock until de-asserted
CFG3 {41}
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
1
1
1
1
1
1
1
1
@
@
@
@
PAD
PAD
PAD
PAD
1
1
1
1
@
@
@
@
PAD
PAD
PAD
PAD
1
1
1
1
0
Reserved
RC33 1
2 20_0402_5%
RC34 1
2 0_0402_5%
2 10K_0402_5%
BR33
BN1
H_CATERR#
2
1
@2
AT13
AW13
@2
AU13
AY13
PROCPWRGD
RESET#
PM_SYNC
PM_DOWN
PECI
THERMTRIP#
PROC_TDO
PROC_TDI
PROC_TMS
PROC_TCK
PROC_TRST#
PROC_PREQ#
PROC_PRDY#
SKTOCC#
PROC_SELECT#
CATERR#
CFG_RCOMP
N/A
PCI Express* Static x16 Lane Numbering Reversal
TC27
TC28
TC29
TC42
CFG2
1 = Normal operation
0 = Lane numbers reversed.
*
BT28
BL32
BP28
BR28
XDP_TDO {41}
XDP_TDI {41}
XDP_TMS {41}
XDP_TCK {41}
BP30
BL30
BP27
Reserved
CFG3
XDP_TRST# {41}
XDP_PREQ# {41}
XDP_PRDY# {41}
BT25
ZVM#
MSM#
lane
D
configuration
lane.
N/A
eDP enable
1 = Disabled.
RC175
49.9_0402_1%
RSVD1
RSVD2
CFG4
close to CPU
0
*
5 OF 13
COFFEELAKE-H-CPU_BGA1440
@
+3VS
+3VALW
BM30
1
CC177
.1U_0402_10V6-K
1
CC176
.1U_0402_10V6-K
33P_0402_50V8J
CC175
2 1K_0402_5%
@ 1
RC174
BT31
BP35
BM34
BP31
BT34
J31
1
RC11 1
VCCST
H13
CPUPWRGOOD_R
BUF_CPU_RST#
H_PM_SYNC
H_PM_DOWN_R
EC_PECI
THRMTRIP#_CPU
2 1/20W_22_5%_0201
2 0_0402_5%
Stall.
2
VCCST_PWRGD
RC32 1
RC22 1
=
configuration
CFG1
TC85
TC86
TC87
TC88
change from VCCST to VCCSTG 0619
{16} H_CPUPWRGD
{14} CPU_PLTRST#
{14} H_PM_SYNC
{14} H_PM_DOWN
{14,49} EC_PECI
{14,25} H_THRMTRIP#
1 = (Default) Normal Operation;
No stall.
*
CFG0
TC77
TC78
TC79
TC80
TC81
TC82
TC83
TC84
5
PCI
Express*
=
Enabled.
Bifurcation
C
C
@
CPU_DRAMPG_CNTL
CPU_DRAMPG_CNTL
2
1
RC18
1K_0402_5%
2
{61}
BR1
BT2
BN35
C
QC1
MMBT3904WH_SOT323-3
B
E2
E3
E1
D1
J24
H24
BN33
BL34
3
E
DDR_PG_CTRL
2
N29
R14
AE29
AA14
AP29
AP14
A36
1
RC179
10K_0402_5%
@
Logic
A37
Debug Pin
Buffer
{22} CPU_TRIGIN
{22} PCH_TRIGIN
PCH_TRIGIN RC4
1
CPU_TRIGIN
CPU_TRIGOUT
2 30_0402_1%
1
2
B
H23
J23
F30
CC174
.1U_0402_10V6-K
@
E30
B30
C30
G3
J3
+3VS
BR35
BR31
BH30
VCCST
+3VALW
RSVD_TP5
IST_TRIG
RSVD_TP4
RSVD_TP3
VCCST
RSVD_TP1
RSVD_TP2
RSVD11
RSVD10
BK28
BJ28
10 = 2 x8 PCI Express*
11 = 1 x16 PCI Express*
*
RC57
51_0402_5%
@
RSVD15
01 = reserved
CFG[6:5]
1
1
1
1 PAD
TC111
1
+1.2V
00 = 1 x8, 2 x4 PCI Express*
PEG
Training
2
2
2
UC1M
RC178
100K_0402_5%
RC177
100K_0402_5%
@
*
RSVD28
RSVD27
RSVD14
RSVD13
XDP_PREQ#
CFG7
RSVD30
RSVD31
RSVD33
RSVD32
RSVD5
RSVD4
VSS_A36
1 = (default) PEG Train
immediately following
RESET# deassertion.
0 = PEG Wait for BIOS for training.
Reserved configuration lane.
CFG[19:8] N/A
VSS_A37
PROC_TRIGIN
PROC_TRIGOUT
RSVD24
RSVD23
RSVD7
RSVD21
RSVD12
RSVD3
RSVD25
B
BL31
AJ8
G13
VCCIO
RSVD26
RSVD29
RSVD22
RSVD20
RSVD17
RSVD16
RSVD8
RSVD6
RSVD19
RSVD18
RSVD9
C38
C1
BR2
BP1
B38
B2
1
RC144
1K_0402_5%
2
RC143
1K_0402_5%
2
2
RC142
1K_0402_5%
1
1
1
1
1
1
RC52
1K_0402_5%
@
RC51
1K_0402_5%
@
RC55
1K_0402_5%
@
2
RC54
1K_0402_5%
2
RC53
1K_0402_5%
2
RC56
1K_0402_5%
@
1
1
RC146
1K_0402_5%
@
2
R322
1K_0402_1%
@
CC33
0.022U_0402_16V7-K
@
1
1
2
CC179
330P_0402_50V8J
2
2
S L2N7002KWT1G_SOT323-3
2
1
L2N7002KWT1G_SOT323-3
3
3
G
S
2
D
2
G
1
Q2
1
D
1
1
Q1
2
RC141
1K_0402_5%
@
CFG7
CFG6
CFG5
CFG4
CFG2
CFG0
CFG1
CPUCORE_ON
RC140
1K_0402_5%
@
2
2
CFG3
1
VCCST_PWRGD
2
2
1
2
RC139
1K_0402_5%
@
RC50 1
60.4_0402_1%
{49,63} CPUCORE_ON
1
COFFEELAKE-H-CPU_BGA1440
@
RC75
1K_0402_5%
1
1
R291
10K_0402_5%
2
2
2
13 OF 13
R292
10K_0402_5%
@
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/02/26
Deciphered Date
https://Dr-Bios.com
2018/09/20
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
5
4
3
2
CPU (2/7) PM, XDP, CLK, CFG
Size Document Number
Custom
Rev
0.1
FG541/FG741
Date:
Thursday, January 24, 2019
1
Sheet
6
of
69
5
4
3
DDRA_DQ[0..63]
UC1A
AG1
AG2
AK2
AK1
AL3
AK3
AL2
AL1
{12} DDRA_CLK0
{12} DDRA_CLK0#
D
AT1
AT2
AT3
AT5
{12} DDRA_CKE0
AD5
AE2
AD2
AE5
{12} DDRA_CS0#
DDRA_ODT0
{12} DDRA_ODT0
DDRA_BA0
DDRA_BA1
{12} DDRA_BA0
{12} DDRA_BA1
{12} DDRA_BG0
{12}
{12}
{12}
{12}
AH5
AH1
AU1
AH4
AG4
AD1
{12} DDRA_MA16_RAS#
{12} DDRA_MA14_WE#
{12} DDRA_MA15_CAS#
{12} DDRA_MA[0..9]
C
AD3
AE4
AE1
AD4
DDRA_MA0
DDRA_MA1
DDRA_MA2
DDRA_MA3
DDRA_MA4
DDRA_MA5
DDRA_MA6
DDRA_MA7
DDRA_MA8
DDRA_MA9
DDRA_MA10
DDRA_MA11
DDRA_MA12
DDRA_MA13
DDRA_MA10
DDRA_MA11
DDRA_MA12
DDRA_MA13
{12} DDRA_BG1
AH3
AP4
AN4
AP5
AP2
AP1
AP3
AN1
AN3
AT4
AH2
AN2
AU4
AE3
AU2
AU3
DDRA_ACT#
{12} DDRA_ACT#
DDRA_PAR
AG3
DDRA_ALERT# AU5
{12} DDRA_PAR
{12} DDRA_ALERT#
{12} DDRA_DQS#[0..7]
DDRA_DQS#0
DDRA_DQS#1
DDRA_DQS#2
DDRA_DQS#3
DDRA_DQS#4
DDRA_DQS#5
DDRA_DQS#6
DDRA_DQS#7
DDRA_DQS0
DDRA_DQS1
DDRA_DQS2
DDRA_DQS3
DDRA_DQS4
DDRA_DQS5
DDRA_DQS6
DDRA_DQS7
{12} DDRA_DQS[0..7]
BR5
BL3
BG3
BD3
AA3
U3
P3
L3
BP5
BK3
BF3
BC3
AB3
V3
R3
M3
AY3
BA3
DDR0_CKP_0/DDR0_CKP_0
DDR0_CKN_0/DDR0_CKN_0
DDR0_CKP_1/DDR0_CKP_1
DDR0_CKN_1/DDR0_CKN_1
NC/DDR0_CKP_2
NC/DDR0_CKN_2
NC/DDR0_CKP_3
NC/DDR0_CKN_3
DDR0_DQ_0/DDR0_DQ_0
DDR0_DQ_1/DDR0_DQ_1
DDR0_DQ_2/DDR0_DQ_2
DDR0_DQ_3/DDR0_DQ_3
DDR0_DQ_4/DDR0_DQ_4
DDR0_DQ_5/DDR0_DQ_5
DDR0_DQ_6/DDR0_DQ_6
DDR0_DQ_7/DDR0_DQ_7
DDR0_DQ_8/DDR0_DQ_8
DDR0_CKE_0/DDR0_CKE_0
DDR0_DQ_9/DDR0_DQ_9
DDR0_CKE_1/DDR0_CKE_1 DDR0_DQ_10/DDR0_DQ_10
DDR0_CKE_2/DDR0_CKE_2 DDR0_DQ_11/DDR0_DQ_11
DDR0_CKE_3/DDR0_CKE_3 DDR0_DQ_12/DDR0_DQ_12
DDR0_DQ_13/DDR0_DQ_13
DDR0_CS#_0/DDR0_CS#_0 DDR0_DQ_14/DDR0_DQ_14
DDR0_CS#_1/DDR0_CS#_1 DDR0_DQ_15/DDR0_DQ_15
NC/DDR0_CS#_2
DDR0_DQ_16/DDR0_DQ_32
NC/DDR0_CS#_3
DDR0_DQ_17/DDR0_DQ_33
DDR0_DQ_18/DDR0_DQ_34
DDR0_ODT_0/DDR0_ODT_0 DDR0_DQ_19/DDR0_DQ_35
NC/DDR0_ODT_1
DDR0_DQ_20/DDR0_DQ_36
NC/DDR0_ODT_2
DDR0_DQ_21/DDR0_DQ_37
NC/DDR0_ODT_3
DDR0_DQ_22/DDR0_DQ_38
DDR0_DQ_23/DDR0_DQ_39
DDR0_CAB_4/DDR0_BA_0 DDR0_DQ_24/DDR0_DQ_40
DDR0_CAB_6/DDR0_BA_1 DDR0_DQ_25/DDR0_DQ_41
DDR0_CAA_5/DDR0_BG_0 DDR0_DQ_26/DDR0_DQ_42
DDR0_DQ_27/DDR0_DQ_43
DDR0_CAB_3/DDR0_MA_16 DDR0_DQ_28/DDR0_DQ_44
DDR0_CAB_2/DDR0_MA_14 DDR0_DQ_29/DDR0_DQ_45
DDR0_CAB_1/DDR0_MA_15 DDR0_DQ_30/DDR0_DQ_46
DDR0_DQ_31/DDR0_DQ_47
DDR0_CAB_9/DDR0_MA_0
DDR0_DQ_32/DDR1_DQ_0
DDR0_CAB_8/DDR0_MA_1
DDR0_DQ_33/DDR1_DQ_1
DDR0_CAB_5/DDR0_MA_2
DDR0_DQ_34/DDR1_DQ_2
NC/DDR0_MA_3
DDR0_DQ_35/DDR1_DQ_3
NC/DDR0_MA_4
DDR0_DQ_36/DDR1_DQ_4
DDR0_CAA_0/DDR0_MA_5
DDR0_DQ_37/DDR1_DQ_5
DDR0_CAA_2/DDR0_MA_6
DDR0_DQ_38/DDR1_DQ_6
DDR0_CAA_4/DDR0_MA_7
DDR0_DQ_39/DDR1_DQ_7
DDR0_CAA_3/DDR0_MA_8
DDR0_DQ_40/DDR1_DQ_8
DDR0_CAA_1/DDR0_MA_9
DDR0_DQ_41/DDR1_DQ_9
DDR0_CAB_7/DDR0_MA_10 DDR0_DQ_42/DDR1_DQ_10
DDR0_CAA_7/DDR0_MA_11 DDR0_DQ_43/DDR1_DQ_11
DDR0_CAA_6/DDR0_MA_12 DDR0_DQ_44/DDR1_DQ_12
DDR0_CAB_0/DDR0_MA_13 DDR0_DQ_45/DDR1_DQ_13
DDR0_CAA_9/DDR0_BG_1 DDR0_DQ_46/DDR1_DQ_14
DDR0_CAA_8/DDR0_ACT# DDR0_DQ_47/DDR1_DQ_15
DDR0_DQ_48/DDR1_DQ_32
NC/DDR0_PAR
DDR0_DQ_49/DDR1_DQ_33
NC/DDR0_ALERT#
DDR0_DQ_50/DDR1_DQ_34
DDR0_DQ_51/DDR1_DQ_35
DDR0_DQ_52/DDR1_DQ_36
DDR0_DQSN_0/DDR0_DQSN_0
DDR0_DQ_53/DDR1_DQ_37
DDR0_DQSN_1/DDR0_DQSN_1
DDR0_DQ_54/DDR1_DQ_38
DDR0_DQSN_2/DDR0_DQSN_4
DDR0_DQ_55/DDR1_DQ_39
DDR0_DQSN_3/DDR0_DQSN_5
DDR0_DQ_56/DDR1_DQ_40
DDR0_DQSN_4/DDR1_DQSN_0
DDR0_DQ_57/DDR1_DQ_41
DDR0_DQSN_5/DDR1_DQSN_1
DDR0_DQ_58/DDR1_DQ_42
DDR0_DQSN_6/DDR1_DQSN_4
DDR0_DQ_59/DDR1_DQ_43
DDR0_DQSN_7/DDR1_DQSN_5
DDR0_DQ_60/DDR1_DQ_44
DDR0_DQ_61/DDR1_DQ_45
DDR0_DQSP_0/DDR0_DQSP_0
DDR0_DQ_62/DDR1_DQ_46
DDR0_DQSP_1/DDR0_DQSP_1
DDR0_DQ_63/DDR1_DQ_47
DDR0_DQSP_2/DDR0_DQSP_4
DDR0_DQSP_3/DDR0_DQSP_5
NC/DDR0_ECC_0
DDR0_DQSP_4/DDR1_DQSP_0
NC/DDR0_ECC_1
DDR0_DQSP_5/DDR1_DQSP_1
NC/DDR0_ECC_2
DDR0_DQSP_6/DDR1_DQSP_4
NC/DDR0_ECC_3
DDR0_DQSP_7/DDR1_DQSP_5
NC/DDR0_ECC_4
DDR CHANNEL ANC/DDR0_ECC_5
DDR0_DQSP_8/DDR0_DQSP_8
NC/DDR0_ECC_6
1
DDR0_DQSN_8/DDR0_DQSN_8OF 13
NC/DDR0_ECC_7
BR6
BT6
BP3
BR3
BN5
BP6
BP2
BN3
BL4
BL5
BL2
BM1
BK4
BK5
BK1
BK2
BG4
BG5
BF4
BF5
BG2
BG1
BF1
BF2
BD2
BD1
BC4
BC5
BD5
BD4
BC1
BC2
AB1
AB2
AA4
AA5
AB5
AB4
AA2
AA1
V5
V2
U1
U2
V1
V4
U5
U4
R2
P5
R4
P4
R5
P2
R1
P1
M4
M1
L4
L2
M5
M2
L5
L1
DDRA_DQ0
DDRA_DQ1
DDRA_DQ2
DDRA_DQ3
DDRA_DQ4
DDRA_DQ5
DDRA_DQ6
DDRA_DQ7
DDRA_DQ8
DDRA_DQ9
DDRA_DQ10
DDRA_DQ11
DDRA_DQ12
DDRA_DQ13
DDRA_DQ14
DDRA_DQ15
DDRA_DQ16
DDRA_DQ17
DDRA_DQ18
DDRA_DQ19
DDRA_DQ20
DDRA_DQ21
DDRA_DQ22
DDRA_DQ23
DDRA_DQ24
DDRA_DQ25
DDRA_DQ26
DDRA_DQ27
DDRA_DQ28
DDRA_DQ29
DDRA_DQ30
DDRA_DQ31
DDRA_DQ32
DDRA_DQ33
DDRA_DQ34
DDRA_DQ35
DDRA_DQ36
DDRA_DQ37
DDRA_DQ38
DDRA_DQ39
DDRA_DQ40
DDRA_DQ41
DDRA_DQ42
DDRA_DQ43
DDRA_DQ44
DDRA_DQ45
DDRA_DQ46
DDRA_DQ47
DDRA_DQ48
DDRA_DQ49
DDRA_DQ50
DDRA_DQ51
DDRA_DQ52
DDRA_DQ53
DDRA_DQ54
DDRA_DQ55
DDRA_DQ56
DDRA_DQ57
DDRA_DQ58
DDRA_DQ59
DDRA_DQ60
DDRA_DQ61
DDRA_DQ62
DDRA_DQ63
2
1
{12}
DDRB_DQ[0..63]
UC1B
{13}
{13}
{13}
{13}
AM9
AN9
AM7
AM8
AM11
AM10
AJ10
AJ11
DDRB_CLK0
DDRB_CLK0#
DDRB_CLK1
DDRB_CLK1#
{13} DDRB_CKE0
{13} DDRB_CKE1
AT8
AT10
AT7
AT11
{13} DDRB_CS0#
{13} DDRB_CS1#
DDR1_CKP_0/DDR1_CKP_0
DDR1_CKN_0/DDR1_CKN_0
DDR1_CKP_1/DDR1_CKP_1
DDR1_CKN_1/DDR1_CKN_1
NC/DDR1_CKP_2
NC/DDR1_CKN_2
NC/DDR1_CKP_3
NC/DDR1_CKN_3
AF11
AE7
AF10
AE10
DDRB_ODT0
DDRB_ODT1
{13} DDRB_ODT0
{13} DDRB_ODT1
{13}
{13}
{13}
{13}
{13}
{13}
DDR1_CS#_0/DDR1_CS#_0
DDR1_CS#_1/DDR1_CS#_1
NC/DDR1_CS#_2
NC/DDR1_CS#_3
AF7
AE8
AE9
AE11
DDR1_ODT_0/DDR1_ODT_0
NC/DDR1_ODT_1
NC/DDR1_ODT_2
NC/DDR1_ODT_3
AH10
AH11
AF8
{13} DDRB_MA16_RAS#
{13} DDRB_MA14_WE#
{13} DDRB_MA15_CAS#
{13}
{13}
{13}
{13}
DDR1_CKE_0/DDR1_CKE_0
DDR1_CKE_1/DDR1_CKE_1
DDR1_CKE_2/DDR1_CKE_2
DDR1_CKE_3/DDR1_CKE_3
DDR1_CAB_3/DDR1_MA_16
DDR1_CAB_2/DDR1_MA_14
DDR1_CAB_1/DDR1_MA_15
AH8
AH9
AR9
DDRB_BA0
DDRB_BA1
DDRB_BG0
DDRB_MA[0..9]
DDRB_MA0
DDRB_MA1
DDRB_MA2
DDRB_MA3
DDRB_MA4
DDRB_MA5
DDRB_MA6
DDRB_MA7
DDRB_MA8
DDRB_MA9
DDRB_MA10
DDRB_MA11
DDRB_MA12
DDRB_MA13
DDRB_BG1
DDRB_ACT#
DDRB_MA10
DDRB_MA11
DDRB_MA12
DDRB_MA13
DDRB_BG1
DDRB_ACT#
DDR1_CAB_4/DDR1_BA_0
DDR1_CAB_6/DDR1_BA_1
DDR1_CAA_5/DDR1_BG_0
AJ9
AK6
AK5
AL5
AL6
AM6
AN7
AN10
AN8
AR11
AH7
AN11
AR10
AF9
AR7
AT9
DDRB_PAR
DDRB_ALERT#
DDRB_DQS#0
DDRB_DQS#1
DDRB_DQS#2
DDRB_DQS#3
DDRB_DQS#4
DDRB_DQS#5
DDRB_DQS#6
DDRB_DQS#7
DDRB_DQS0
DDRB_DQS1
DDRB_DQS2
DDRB_DQS3
DDRB_DQS4
DDRB_DQS5
DDRB_DQS6
DDRB_DQS7
DDR1_DQ_40/DDR1_DQ_24
DDR1_DQ_41/DDR1_DQ_25
DDR1_DQ_42/DDR1_DQ_26
DDR1_DQ_43/DDR1_DQ_27
DDR1_DQ_44/DDR1_DQ_28
DDR1_DQ_45/DDR1_DQ_29
DDR1_DQ_46/DDR1_DQ_30
DDR1_DQ_47/DDR1_DQ_31
DDR1_DQ_48/DDR1_DQ_48
NC/DDR1_PAR
DDR1_DQ_49/DDR1_DQ_49
NC/DDR1_ALERT#
DDR1_DQ_50/DDR1_DQ_50
DDR1_DQ_51/DDR1_DQ_51
DDR1_DQ_52/DDR1_DQ_52
DDR1_DQSN_0/DDR0_DQSN_2
DDR1_DQ_53/DDR1_DQ_53
DDR1_DQSN_1/DDR0_DQSN_3
DDR1_DQ_54/DDR1_DQ_54
DDR1_DQSN_2/DDR0_DQSN_6
DDR1_DQ_55/DDR1_DQ_55
DDR1_DQSN_3/DDR0_DQSN_7
DDR1_DQ_56/DDR1_DQ_56
DDR1_DQSN_4/DDR1_DQSN_2
DDR1_DQ_57/DDR1_DQ_57
DDR1_DQSN_5/DDR1_DQSN_3
DDR1_DQ_58/DDR1_DQ_58
DDR1_DQSN_6/DDR1_DQSN_6
DDR1_DQ_59/DDR1_DQ_59
DDR1_DQSN_7/DDR1_DQSN_7
DDR1_DQ_60/DDR1_DQ_60
DDR1_DQ_61/DDR1_DQ_61
DDR1_DQSP_0/DDR0_DQSP_2
DDR1_DQ_62/DDR1_DQ_62
DDR1_DQSP_1/DDR0_DQSP_3
DDR1_DQ_63/DDR1_DQ_63
DDR1_DQSP_2/DDR0_DQSP_6
DDR1_DQSP_3/DDR0_DQSP_7
NC/DDR1_ECC_0
DDR1_DQSP_4/DDR1_DQSP_2
NC/DDR1_ECC_1
DDR1_DQSP_5/DDR1_DQSP_3
NC/DDR1_ECC_2
DDR1_DQSP_6/DDR1_DQSP_6
NC/DDR1_ECC_3
DDR1_DQSP_7/DDR1_DQSP_7
NC/DDR1_ECC_4
NC/DDR1_ECC_5
DDR1_DQSP_8/DDR1_DQSP_8
NC/DDR1_ECC_6
DDR1_DQSN_8/DDR1_DQSN_8
NC/DDR1_ECC_7
BN9
BL9
BG9
BC9
AC9
W9
R9
M9
{13} DDRB_DQS[0..7]
DDR1_CAA_3/DDR1_MA_8
DDR1_CAA_1/DDR1_MA_9
DDR1_CAB_7/DDR1_MA_10
DDR1_CAA_7/DDR1_MA_11
DDR1_CAA_6/DDR1_MA_12
DDR1_CAB_0/DDR1_MA_13
DDR1_CAA_9/DDR1_BG_1
DDR1_CAA_8/DDR1_ACT#
AJ7
AR8
{13} DDRB_DQS#[0..7]
DDR1_CAB_9/DDR1_MA_0
DDR1_CAB_8/DDR1_MA_1
DDR1_CAB_5/DDR1_MA_2
NC/DDR1_MA_3
NC/DDR1_MA_4
DDR1_CAA_0/DDR1_MA_5
DDR1_CAA_2/DDR1_MA_6
DDR1_CAA_4/DDR1_MA_7
BP9
BJ9
BF9
BB9
AA9
V9
P9
L9
{13} DDRB_PAR
{13} DDRB_ALERT#
BA2
BA1
AY4
AY5
BA5
BA4
AY1
AY2
AW9
AY9
COFFEELAKE-H-CPU_BGA1440
@
DDR_SA_VREFCA
+V_DDR_REF_R
+V_DDR_REFB_R
{12} DDR_SA_VREFCA
B
DDR1_DQ_0/DDR0_DQ_16
DDR1_DQ_1/DDR0_DQ_17
DDR1_DQ_2/DDR0_DQ_18
DDR1_DQ_3/DDR0_DQ_19
DDR1_DQ_4/DDR0_DQ_20
DDR1_DQ_5/DDR0_DQ_21
DDR1_DQ_6/DDR0_DQ_22
DDR1_DQ_7/DDR0_DQ_23
DDR1_DQ_8/DDR0_DQ_24
DDR1_DQ_9/DDR0_DQ_25
DDR1_DQ_10/DDR0_DQ_26
DDR1_DQ_11/DDR0_DQ_27
DDR1_DQ_12/DDR0_DQ_28
DDR1_DQ_13/DDR0_DQ_29
DDR1_DQ_14/DDR0_DQ_30
DDR1_DQ_15/DDR0_DQ_31
DDR1_DQ_16/DDR0_DQ_48
DDR1_DQ_17/DDR0_DQ_49
DDR1_DQ_18/DDR0_DQ_50
DDR1_DQ_19/DDR0_DQ_51
DDR1_DQ_20/DDR0_DQ_52
DDR1_DQ_21/DDR0_DQ_53
DDR1_DQ_22/DDR0_DQ_54
DDR1_DQ_23/DDR0_DQ_55
DDR1_DQ_24/DDR0_DQ_56
DDR1_DQ_25/DDR0_DQ_57
DDR1_DQ_26/DDR0_DQ_58
DDR1_DQ_27/DDR0_DQ_59
DDR1_DQ_28/DDR0_DQ_60
DDR1_DQ_29/DDR0_DQ_61
DDR1_DQ_30/DDR0_DQ_62
DDR1_DQ_31/DDR0_DQ_63
DDR1_DQ_32/DDR1_DQ_16
DDR1_DQ_33/DDR1_DQ_17
DDR1_DQ_34/DDR1_DQ_18
DDR1_DQ_35/DDR1_DQ_19
DDR1_DQ_36/DDR1_DQ_20
DDR1_DQ_37/DDR1_DQ_21
DDR1_DQ_38/DDR1_DQ_22
DDR1_DQ_39/DDR1_DQ_23
BN13
BP13
BR13
DDR_VREF_CA
DDR0_VREF_DQ
DDR1_VREF_DQ
DDR CHANNEL B
2 OF 13
DDR_RCOMP_0
DDR_RCOMP_1
DDR_RCOMP_2
BT11
BR11
BT9
BR8
BP11
BN11
BP8
BN8
BL12
BL11
BL8
BJ8
BJ11
BJ10
BL7
BJ7
BG11
BG10
BG8
BF8
BF11
BF10
BG7
BF7
BB11
BC11
BB8
BC8
BC10
BB10
BC7
BB7
AA11
AA10
AC11
AC10
AA7
AA8
AC8
AC7
W8
W7
V10
V11
W11
W10
V7
V8
R11
P11
P7
R8
R10
P10
R7
P8
L11
M11
L7
M8
L10
M10
M7
L8
{13}
DDRB_DQ0
DDRB_DQ1
DDRB_DQ2
DDRB_DQ3
DDRB_DQ4
DDRB_DQ5
DDRB_DQ6
DDRB_DQ7
DDRB_DQ8
DDRB_DQ9
DDRB_DQ10
DDRB_DQ11
DDRB_DQ12
DDRB_DQ13
DDRB_DQ14
DDRB_DQ15
DDRB_DQ16
DDRB_DQ17
DDRB_DQ18
DDRB_DQ19
DDRB_DQ20
DDRB_DQ21
DDRB_DQ22
DDRB_DQ23
DDRB_DQ24
DDRB_DQ25
DDRB_DQ26
DDRB_DQ27
DDRB_DQ28
DDRB_DQ29
DDRB_DQ30
DDRB_DQ31
DDRB_DQ32
DDRB_DQ33
DDRB_DQ34
DDRB_DQ35
DDRB_DQ36
DDRB_DQ37
DDRB_DQ38
DDRB_DQ39
DDRB_DQ40
DDRB_DQ41
DDRB_DQ42
DDRB_DQ43
DDRB_DQ44
DDRB_DQ45
DDRB_DQ46
DDRB_DQ47
DDRB_DQ48
DDRB_DQ49
DDRB_DQ50
DDRB_DQ51
DDRB_DQ52
DDRB_DQ53
DDRB_DQ54
DDRB_DQ55
DDRB_DQ56
DDRB_DQ57
DDRB_DQ58
DDRB_DQ59
DDRB_DQ60
DDRB_DQ61
DDRB_DQ62
DDRB_DQ63
D
C
AW11
AY11
AY8
AW8
AY10
AW10
AY7
AW7
G1
H1
J2
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
B
COFFEELAKE-H-CPU_BGA1440
@
DDRA_CLK0#
1
2
CC1390
3.3P_0201_50V8-C
@
1 +VREF_DQ_DIMM_R RC36 1
PAD @ TC109
RC37 1
+VREF_DQ_DIMMB_R
DDRA_CLK0
2 0_0402_5% @
2 0_0402_5%
+V_DDR_REF_R
+V_DDR_REFB_R
CAD Note:
Trace width= 20 mil, Spcing=20 mils
Follow 1.0PDG to reserve 3.3P_0201 capacitor
between DDRA_CLK0 and DDRA_CLK0# --SF0904
DDR_VREF_CA : Connected to
DDR0_VREF_DQ : NC
DDR1_VREF_DQ : Connected to
VREF_CA on DIMM CH-A
VREF_CA on DIMM CH-B
DDR4 COMPENSATION SIGNALS
SM_RCOMP0
RC5 1
2 121_0402_1%
SM_RCOMP1
RC6
1
2 75_0402_1%
SM_RCOMP2
RC8
1
2 100_0402_1%
CAD Note:
Trace width=12~15 mil, Spcing=20 mils
Max trace length= 500 mil
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/02/26
Deciphered Date
https://Dr-Bios.com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
5
4
3
2
CPU (3/7) DDRVI
2018/09/20
Size
C
Date:
Document Number
Rev
0.1
FG541/FG741
Thursday, January 03, 2019
1
Sheet
7
of
69
5
4
3
2
1
UC1D
change HDMI DDI from CPU to GPU
D
K36
K37
J35
J34
H37
H36
J37
J38
D27
E27
H34
H33
F37
G38
F34
F35
E37
E36
F26
E26
C34
D34
B36
B34
F33
E33
C33
B33
C
A27
B27
DDI1_TXP_0
DDI1_TXN_0
DDI1_TXP_1
DDI1_TXN_1
DDI1_TXP_2
DDI1_TXN_2
DDI1_TXP_3
DDI1_TXN_3
EDP_TXP_0
EDP_TXN_0
EDP_TXP_1
EDP_TXN_1
EDP_TXP_2
EDP_TXN_2
EDP_TXP_3
EDP_TXN_3
DDI1_AUXP
DDI1_AUXN
EDP_AUXP
EDP_AUXN
DDI2_TXP_0
DDI2_TXN_0
DDI2_TXP_1
DDI2_TXN_1
DDI2_TXP_2
DDI2_TXN_2
DDI2_TXP_3
EDP_DISP_UTIL
DISP_RCOMP
CPU_EDP_TX0+
CPU_EDP_TX0CPU_EDP_TX1+
CPU_EDP_TX1-
C26
B26
CPU_EDP_AUX
CPU_EDP_AUX#
CPU_EDP_TX0+
CPU_EDP_TX0CPU_EDP_TX1+
CPU_EDP_TX1-
D
{38}
{38}
{38}
{38}
CPU_EDP_AUX {38}
CPU_EDP_AUX# {38}
VCCIO
A33
D37
EDP_COMP
2
24.9_0402_1%
1
RC49
COMPENSATION PU FOR eDP
DDI2_TXN_3
CAD Note:Trace width=20 mils ,Spacing=25mil,
Max length=100 mils.
DDI2_AUXP
DDI2_AUXN
DDI3_TXP_0
DDI3_TXN_0
DDI3_TXP_1
DDI3_TXN_1
DDI3_TXP_2
DDI3_TXN_2
DDI3_TXP_3
DDI3_TXN_3
DDI3_AUXP
DDI3_AUXN
D29
E29
F28
E28
A29
B29
C28
B28
C
PROC_AUDIO_CLK
PROC_AUDIO_SDI
PROC_AUDIO_SDO
G27 PROC_AUDIO_CLK_CPU
G25 PROC_AUDIO_SDO_CPU
G29 PROC_AUDIO_SDI_CPU_R
RC180
1
PROC_AUDIO_CLK_CPU {16}
PROC_AUDIO_SDO_CPU {16}
PROC_AUDIO_SDI_CPU {16}
2 20_0402_1%
4 of 13
Place near CPU.
1
COFFEELAKE-H-CPU_BGA1440
@
2
RH762
33_0402_5%
@
1
CH264
10P_0402_50V8J
2@
B
B
A
A
Title
LC Future Center Secret Data
Security Classification
Issued Date
2015/02/26
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
5
4
https://Dr-Bios.com
3
CPU (4/7) eDP, DDI
2018/09/20
Size
A3
Date:
2
Document Number
Rev
0.1
FG541/FG741
Thursday, January 03, 2019
Sheet
1
8
of
69
5
4
3
VCCGFXCORE
UC1J
VCCCPUCORE
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98
VCC99
VCC100
VCC101
VCC102
VCC103
VCC104
VCC105
VCC106
VCC107
VCC108
VCC109
VCC110
VCC111
VCC112
VCC113
VCC114
VCC115
VCC116
VCC117
VCC118
VCC119
VCC120
VCC121
VCC122
VCC123
VCC124
C
VCC_SENSE
VSS_SENSE
9 OF 13
AH13
AH14
AH29
AH30
AH31
AH32
AJ14
AJ29
AJ30
AJ31
AJ32
AJ33
AJ34
AJ35
AJ36
AK31
AK32
AK33
AK34
AK35
AK36
AK37
AK38
AL13
AL29
AL30
AL31
AL32
AL35
AL36
AL37
AL38
AM13
AM14
AM29
AM30
AM31
AM32
AM33
AM34
AM35
AM36
AN13
AN14
AN31
AN32
AN33
AN34
AN35
AN36
AN37
AN38
AP13
AP30
AP31
AP32
AP35
AP36
AP37
AP38
K13
AG37
AG38
K14
L13
L14
N13
N14
N30
N31
N32
N35
N36
N37
N38
P13
P14
P29
P30
P31
P32
P33
P34
P35
P36
R13
R31
R32
R33
R34
R35
R36
R37
R38
T29
T30
T31
T32
T35
T36
T37
T38
U29
U30
U31
U32
U33
U34
U35
U36
V13
V14
V31
V32
V33
V34
V35
V36
V37
V38
W13
W14
W29
W30
W31
W32
VCC125
VCC126
VCC127
VCC128
VCC129
VCC130
VCC131
VCC132
VCC133
VCC134
VCC135
VCC136
VCC137
VCC138
VCC139
VCC140
VCC141
VCC142
VCC143
VCC144
VCC145
VCC146
VCC147
VCC148
VCC149
VCC150
VCC151
VCC152
VCC153
VCC154
VCC155
VCC156
VCC157
VCC158
VCC159
VCC160
VCC161
VCC162
VCC163
VCC164
VCC165
VCC166
VCC167
VCC168
VCC169
VCC170
VCC171
VCC172
VCC173
VCC174
VCC175
VCC176
VCC177
VCC178
VCC179
VCC180
VCC181
VCC182
VCC183
VCC184
VCC185
VCC186
VCC187
W35
W36
W37
W38
Y29
Y30
Y31
Y32
Y33
Y34
Y35
Y36
VCC188
VCC189
VCC190
VCC191
VCC192
VCC193
VCC194
VCC195
VCC196
VCC197
VCC198
VCC199
10 OF 13
COFFEELAKE-H-CPU_BGA1440
@
VCCCORE_SENSE
VSSCORE_SENSE
COFFEELAKE-H-CPU_BGA1440
@
CRB place to CPU
VCCCPUCORE
1
VCC_SENSE
RC59
100_0402_1%
VCCGT1
VCCGT2
VCCGT3
VCCGT4
VCCGT5
VCCGT6
VCCGT7
VCCGT8
VCCGT9
VCCGT10
VCCGT11
VCCGT12
VCCGT13
VCCGT14
VCCGT15
VCCGT16
VCCGT17
VCCGT18
VCCGT19
VCCGT20
VCCGT21
VCCGT22
VCCGT23
VCCGT24
VCCGT25
VCCGT26
VCCGT27
VCCGT28
VCCGT29
VCCGT30
VCCGT31
VCCGT32
VCCGT33
VCCGT34
VCCGT35
VCCGT36
VCCGT37
VCCGT38
VCCGT39
VCCGT40
VCCGT41
VCCGT42
VCCGT43
VCCGT44
VCCGT45
VCCGT46
VCCGT47
VCCGT48
VCCGT49
VCCGT50
VCCGT51
VCCGT52
VCCGT53
VCCGT54
VCCGT55
VCCGT56
VCCGT57
VCCGT58
VCCGT59
VCCGT60
VCCGT61
VCCGT62
VCCGT63
VCCGT64
VCCGT65
VCCGT66
VCCGT67
VCCGT68
VCCGT69
VCCGT70
VCCGT71
VCCGT72
VCCGT73
VCCGT74
VCCGT75
VCCGT76
VCCGT77
VCCGT78
VCCGT79
VCCGT159
VCCGT160
VCCGT161
VCCGT162
VCCGT163
VCCGT80
VCCGT81
VCCGT82
VCCGT83
VCCGT84
VCCGT85
VCCGT86
VCCGT87
VCCGT88
VCCGT89
VCCGT90
VCCGT91
VCCGT92
VCCGT93
VCCGT94
VCCGT95
VCCGT96
VCCGT97
VCCGT98
VCCGT99
VCCGT100
VCCGT101
VCCGT102
VCCGT103
VCCGT104
VCCGT105
VCCGT106
VCCGT107
VCCGT108
VCCGT109
VCCGT110
VCCGT111
VCCGT112
VCCGT113
VCCGT114
VCCGT115
VCCGT116
VCCGT117
VCCGT118
VCCGT119
VCCGT120
VCCGT121
VCCGT122
VCCGT123
VCCGT124
VCCGT125
VCCGT126
VCCGT127
VCCGT128
VCCGT129
VCCGT130
VCCGT131
VCCGT132
VCCGT133
VCCGT134
VCCGT135
VCCGT136
VCCGT137
VCCGT138
VCCGT139
VCCGT140
VCCGT141
VCCGT142
VCCGT143
VCCGT144
VCCGT145
VCCGT146
VCCGT147
VCCGT148
VCCGT149
VCCGT150
VCCGT151
VCCGT152
VCCGT153
VCCGT154
VCCGT155
VCCGT156
VCCGT157
VCCGT158
VCCGT164
VCCGT165
VCCGT166
VCCGT167
VCCGT168
2
VSSGT_SENSE
11 OF VCCGT_SENSE
13
VCCCORE_SENSE
BD35
BD36
BE31
BE32
BE33
BE34
BE35
BE36
BE37
BE38
BF13
BF14
BF29
BF30
BF31
BF32
BF35
BF36
BF37
BF38
BG29
BG30
BG31
BG32
BG33
BG34
BG35
BG36
BH33
BH34
BH35
BH36
BH37
BH38
BJ16
BJ17
BJ19
BJ20
BJ21
BJ23
BJ24
BJ26
BJ27
BJ37
BJ38
BK16
BK17
BK19
BK20
BK21
BK23
BK24
BK26
BK27
BL15
BL16
BL17
BL23
BL24
BL25
BL26
BL27
BL28
BL36
BL37
BM15
BM16
BM17
BM36
BM37
BN15
BN16
BN17
BN36
BN37
BN38
BP15
BP16
BP17
BR37
BT15
BT16
BT17
BT37
AH37
AH38
D
C
CRB place to CPU
VSSGT_SENSE
VCCGT_SENSE
RC60
100_0402_1%
{63} VCCGT_SENSE
{63} VSSGT_SENSE
COFFEELAKE-H-CPU_BGA1440
@
{63} VCCCORE_SENSE
VCCGFXCORE
VCCGT_SENSE
1
D
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
1
UC1K
AT14
AT31
AT32
AT33
AT34
AT35
AT36
AT37
AT38
AU14
AU29
AU30
AU31
AU32
AU35
AU36
AU37
AU38
AV29
AV30
AV31
AV32
AV33
AV34
AV35
AV36
AW14
AW31
AW32
AW33
AW34
AW35
AW36
AW37
AW38
AY29
AY30
AY31
AY32
AY35
AY36
AY37
AY38
BA13
BA14
BA29
BA30
BA31
BA32
BA33
BA34
BA35
BA36
BB13
BB14
BB31
BB32
BB33
BB34
BB35
BB36
BB37
BB38
BC29
BC30
BC31
BC32
BC35
BC36
BC37
BC38
BD13
BD14
BD29
BD30
BD31
BD32
BD33
BD34
BP37
BP38
BR15
BR16
BR17
UC1I
AA13
AA31
AA32
AA33
AA34
AA35
AA36
AA37
AA38
AB29
AB30
AB31
AB32
AB35
AB36
AB37
AB38
AC13
AC14
AC29
AC30
AC31
AC32
AC33
AC34
AC35
AC36
AD13
AD14
AD31
AD32
AD33
AD34
AD35
AD36
AD37
AD38
AE13
AE14
AE30
AE31
AE32
AE35
AE36
AE37
AE38
AF29
AF30
AF31
AF32
AF33
AF34
AF35
AF36
AF37
AF38
AG14
AG31
AG32
AG33
AG34
AG35
AG36
2
VCCGFXCORE
VCCCPUCORE
1
VCCCPUCORE
2
VCCCPUCORE
2
RC63
100_0402_1%
VSSCORE_SENSE
1
{63} VSSCORE_SENSE
2
RC62
100_0402_1%
VCCGFXCORE
10uF
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
1
1
1
1
1uF
2
2pcs
1
2
1
2
1
2
1
2
CH169
1U_0201_6.3V6K
CD@
2
1
CH166
1U_0201_6.3V6K
CD@
2
1
CH167
1U_0201_6.3V6K
2
1
CH165
1U_0201_6.3V6K
2
12pcs，
CD
1
CH163
1U_0201_6.3V6K
2
1
CH164
1U_0201_6.3V6K
2
1
CH161
1U_0201_6.3V6K
1
CH162
1U_0201_6.3V6K
1
CD75
CD76
33P_0402_50V8J 33P_0402_50V8J
RF_NS@
RF_NS@
2
CH160
1U_0201_6.3V6K
2
2
CH159
1U_0201_6.3V6K
2
CD@
CH158
1U_0201_6.3V6K
2
CH157
1U_0201_6.3V6K
2
CD@ CD@
CC90
10U 6.3V M X5R 0402
CD@
2
CC84
10U 6.3V M X5R 0402
1
CC83
10U 6.3V M X5R 0402
2
CC74
10U 6.3V M X5R 0402
1
CC85
10U 6.3V M X5R 0402
2
CC93
10U 6.3V M X5R 0402
1
CC87
10U 6.3V M X5R 0402
2
CC86
10U 6.3V M X5R 0402
1
CC89
10U 6.3V M X5R 0402
2
CC92
10U 6.3V M X5R 0402
1
CC88
10U 6.3V M X5R 0402
2
CC91
10U 6.3V M X5R 0402
1
CC81
10U 6.3V M X5R 0402
2
CC75
10U 6.3V M X5R 0402
1
CC76
10U 6.3V M X5R 0402
2
CC77
10U 6.3V M X5R 0402
1
CC78
10U 6.3V M X5R 0402
2
CC82
10U 6.3V M X5R 0402
1
CC79
10U 6.3V M X5R 0402
2
CC80
10U 6.3V M X5R 0402
CC62
10U 6.3V M X5R 0402
2
1
B
CD@
10uF 21pcs,CD 4pcs
1
CC109
10U 6.3V M X5R 0402
2
CC103
10U 6.3V M X5R 0402
2
1pcs
1
CC102
10U 6.3V M X5R 0402
2
1
CC104
10U 6.3V M X5R 0402
2
1
CC105
10U 6.3V M X5R 0402
2
1
CC106
10U 6.3V M X5R 0402
2
10pcs，
CD
1
CC110
10U 6.3V M X5R 0402
2
1
CC107
10U 6.3V M X5R 0402
VCCCPUCORE
1
CC108
10U 6.3V M X5R 0402
2
B
CC98
10U 6.3V M X5R 0402
1
1
1
2
2
1
CD77
33P_0402_50V8J
RF_NS@
2
CD78
33P_0402_50V8J
RF_NS@
Near CPU
2
CD@
1
2
Near CPU
CH116
1U_0201_6.3V6K
2
1
CH115
1U_0201_6.3V6K
2
1
CH114
1U_0201_6.3V6K
2
1
CH113
1U_0201_6.3V6K
2
1
CH112
1U_0201_6.3V6K
2
CD@
1
CH111
1U_0201_6.3V6K
2
1
CH110
1U_0201_6.3V6K
2
1
CH109
1U_0201_6.3V6K
CD@
2
CD@
1
CH108
1U_0201_6.3V6K
2
1
CH107
1U_0201_6.3V6K
2
1
CH106
1U_0201_6.3V6K
CD@
2
1
CH105
1U_0201_6.3V6K
2
1
CH104
1U_0201_6.3V6K
2
CD@
1
CH103
1U_0201_6.3V6K
2
1
CH102
1U_0201_6.3V6K
2
1
CH101
1U_0201_6.3V6K
CD@
2
1
CH100
1U_0201_6.3V6K
CD@
2
CD@
1
CH99
1U_0201_6.3V6K
2
1
CH98
1U_0201_6.3V6K
2
CD@
1
CH97
1U_0201_6.3V6K
2
1
CH96
1U_0201_6.3V6K
2
CD@
1
CH95
1U_0201_6.3V6K
CD@
1
CH94
1U_0201_6.3V6K
2
CH93
1U_0201_6.3V6K
1
CD@
CD@
1uF 48pcs,CD 3pcs，
24pcs @(delete6pcs)
1
2
CD@
2
1
2
1
2
1
CD@
2
1
1
2
2
CD@
1
2
1
2
CH138
1U_0201_6.3V6K
@
1
CH137
1U_0201_6.3V6K
@
2
CH136
1U_0201_6.3V6K
@
1
CH134
1U_0201_6.3V6K
@
2
CH135
1U_0201_6.3V6K
1
CH133
1U_0201_6.3V6K
2
CH132
1U_0201_6.3V6K
1
CH131
1U_0201_6.3V6K
2
CH129
1U_0201_6.3V6K
@
1
CH130
1U_0201_6.3V6K
2
CH128
1U_0201_6.3V6K
@
1
CH127
1U_0201_6.3V6K
@
2
CH126
1U_0201_6.3V6K
@
1
CH125
1U_0201_6.3V6K
@
2
CH124
1U_0201_6.3V6K
@
1
CH123
1U_0201_6.3V6K
@
CH122
1U_0201_6.3V6K
@
2
CH121
1U_0201_6.3V6K
1
A
1
2
A
Security Classification
Issued Date
T itle
LC Future Center Secret Data
2015/02/26
Deciphered Date
2018/09/20
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
CPU (5/7) PWR, BYPASS
Size
D
Document Number
4
3
https://Dr-Bios.com
2
Rev
0.1
FG541/FG741
Tuesday, January 22, 2019
Date:
5
1
Sheet
9
of
69
5
4
3
2
VCCSA
1
10uF 7pcs
+1.2V
VCCSA
UC1L
1
2
1
2
1
2
1
CD79
33P_0402_50V8J
RF_NS@
2
CD80
33P_0402_50V8J
RF_NS@
D
1uF 1pcs
+1.2V
VCCPLL_OC1
VCCPLL_OC2
VCCPLL_OC3
2
1
2
CC1394 CD@
2
10U_0603_6.3V6M
2
1
CC60
10U_0603_6.3V6M
2
1
CC59
10U_0603_6.3V6M
2
1
CC58
10U_0603_6.3V6M
2
1
CC57
10U_0603_6.3V6M
2
10uF 11pcs,CD 1pcs
2
1
2
22U_0603_6.3V6-M
CC66
2
1
22U_0603_6.3V6-M
CC65
2
1
22U_0603_6.3V6-M
CC64
CRB place to CPU
2
1
C
1
22U_0603_6.3V6-M
CC63
2
2
1
22uF 4pcs
47U_0805_6.3V6-M
2
1
@
1
2
1
CC56
10U_0603_6.3V6M
H14 VCC_IO_SEN
J14 VSSIO_SENSE_R
2
2
1
CC55
10U_0603_6.3V6M
@
2
2
1
1
CC54
10U 6.3V M X5R 0402
M38 VCCSA_SENSE
M37 VSSSA_SENSE
1
1
CC53
10U 6.3V M X5R 0402
2
C10120
VCCIO_SENSE
VSSIO_SENSE
1
VCCST
H28
J28
1
CC52
10U 6.3V M X5R 0402
VCCSA_SENSE
VSSSA_SENSE
G30
CH242
1U_0402_6.3V6K
VCCPLL1
VCCPLL2
H29
CH250
1U_0402_6.3V6K
VCCSTG1
1
VCCSTG
CC51
10U 6.3V M X5R 0402
VCCSTG2
VDDQ DECOUPLING
+1.2V
VCCST
H30
CH252
1U_0402_6.3V6K
VCCST
BH13
BJ13
G11
Follow PDG Rev1.0 0828SF
CRB place to CPU
VCCIO
RC155
100_0402_1%
@
2
2
RC151
100_0402_1%
1
VCCIO_SENSE
VCCSA
1
2
CD@
CC142
10U 6.3V M X5R 0402
1
CC141
10U 6.3V M X5R 0402
2
CC140
10U 6.3V M X5R 0402
1
CD@
COFFEELAKE-H-CPU_BGA1440
@
VCCSA_SENSE
2
Near CPU
1
2
12 OF 13
C
1
CC139
10U 6.3V M X5R 0402
2
2
CC138
10U 6.3V M X5R 0402
1
1
CC137
10U 6.3V M X5R 0402
+1.2V
CH251
1U_0402_6.3V6K
10uF 6pcs,CD 3pcs
2
CC150
1U_0402_6.3V6K
2
VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8
VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21
1
CH249
1U_0402_6.3V6K
CD@
2
1
CC149
10U 6.3V M X5R 0402
2
1
CC148
10U 6.3V M X5R 0402
CD@
2
1
CC147
10U 6.3V M X5R 0402
2
1
CC1395
10U 6.3V M X5R 0402
CD@
1
CC1396
10U 6.3V M X5R 0402
2
CC1397
10U 6.3V M X5R 0402
1
AG12
G15
G17
G19
G21
H15
H16
H17
H19
H20
H21
H26
H27
J15
J16
J17
J19
J20
J21
J26
J27
AA6
AE12
AF5
AF6
AG5
AG9
AJ12
AL11
AP6
AP7
AR12
AR6
AT12
AW6
AY6
J5
J6
K12
K6
L12
L6
R6
T6
W6
Y12
CH223
1U_0402_6.3V6K
VCCIO
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18
VDDQ19
VDDQ20
VDDQ21
VDDQ22
VDDQ23
VDDQ24
VDDQ25
CC136
10U 6.3V M X5R 0402
D
VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA7
VCCSA8
VCCSA9
VCCSA10
VCCSA11
VCCSA12
VCCSA13
VCCSA14
VCCSA15
VCCSA16
VCCSA17
VCCSA18
VCCSA19
VCCSA20
VCCSA21
VCCSA22
CC172
10U_0603_6.3V6M
J30
K29
K30
K31
K32
K33
K34
K35
L31
L32
L35
L36
L37
L38
M29
M30
M31
M32
M33
M34
M35
M36
{63} VCCSA_SENSE
{62} VCC_IO_SEN
VSSIO_SENSE_R
1
1
{63} VSSSA_SENSE
2
2
RC149
100_0402_1%
RC153
100_0402_1%
@
B
B
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/02/26
Deciphered Date
https://Dr-Bios.com
2018/09/20
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
5
4
3
2
CPU (6/7) PWR, BYPASS
Size
C
Date:
Document Number
Rev
0.1
FG541/FG741
Saturday, February 02, 2019
1
Sheet
10
of
69
5
4
D
3
UC1F
A10
A12
A16
A18
A20
A22
A24
A26
A28
A30
A6
A9
AA12
AA29
AA30
AB33
AB34
AB6
AC1
AC12
AC2
AC3
AC37
AC38
AC4
AC5
AC6
AD10
AD11
AD12
AD29
AD30
AD6
AD8
AD9
AE33
AE34
AE6
AF1
AF12
AF13
AF14
AF2
AF3
AF4
AG10
AG11
AG13
AG29
AG30
AG6
AG7
AG8
AH12
AH33
AH34
AH35
AH36
AH6
AJ1
AJ13
AJ2
AJ3
AJ37
AJ38
AJ4
AJ5
AJ6
W4
W5
Y10
Y11
Y13
Y14
Y37
Y38
Y7
Y8
Y9
AK29
AK30
C
B
VSS_1
VSS_82
VSS_2
VSS_83
VSS_3
VSS_84
VSS_4
VSS_85
VSS_5
VSS_86
VSS_6
VSS_87
VSS_7
VSS_88
VSS_8
VSS_89
VSS_9
VSS_90
VSS_10
VSS_91
VSS_11
VSS_92
VSS_12
VSS_93
VSS_13
VSS_94
VSS_14
VSS_95
VSS_15
VSS_96
VSS_16
VSS_97
VSS_17
VSS_98
VSS_18
VSS_99
VSS_19
VSS_100
VSS_20
VSS_101
VSS_21
VSS_102
VSS_22
VSS_103
VSS_23
VSS_104
VSS_24
VSS_105
VSS_25
VSS_106
VSS_26
VSS_107
VSS_27
VSS_108
VSS_28
VSS_109
VSS_29
VSS_110
VSS_30
VSS_111
VSS_31
VSS_112
VSS_32
VSS_113
VSS_33
VSS_114
VSS_34
VSS_115
VSS_35
VSS_116
VSS_36
VSS_117
VSS_37
VSS_118
VSS_38
VSS_119
VSS_39
VSS_120
VSS_40
VSS_121
VSS_41
VSS_122
VSS_42
VSS_123
VSS_43
VSS_124
VSS_44
VSS_125
VSS_45
VSS_126
VSS_46
VSS_127
VSS_47
VSS_128
VSS_48
VSS_129
VSS_49
VSS_130
VSS_50
VSS_131
VSS_51
VSS_132
VSS_52
VSS_133
VSS_53
VSS_134
VSS_54
VSS_135
VSS_55
VSS_136
VSS_56
VSS_137
VSS_57
VSS_138
VSS_58
VSS_139
VSS_59
VSS_140
VSS_60
VSS_141
VSS_61
VSS_142
VSS_62
VSS_143
VSS_63
VSS_144
VSS_64
VSS_145
VSS_65
VSS_146
VSS_66
VSS_147
VSS_67
VSS_148
VSS_68
VSS_149
VSS_69
VSS_150
VSS_70
VSS_151
VSS_71
VSS_152
VSS_72
VSS_153
VSS_73
VSS_154
VSS_74
VSS_155
VSS_75
VSS_156
VSS_76
VSS_157
VSS_77
VSS_158
VSS_78
VSS_159
VSS_79
VSS_160
VSS_80
VSS_161
VSS_81 6 OF 13 VSS_162
2
UC1G
AK4
AL10
AL12
AL14
AL33
AL34
AL4
AL7
AL8
AL9
AM1
AM12
AM2
AM3
AM37
AM38
AM4
AM5
AN12
AN29
AN30
AN5
AN6
AP10
AP11
AP12
AP33
AP34
AP8
AP9
AR1
AR13
AR14
AR2
AR29
AR3
AR30
AR31
AR32
AR33
AR34
AR35
AR36
AR37
AR38
AR4
AR5
AT29
AT30
AT6
AU10
AU11
AU12
AU33
AU34
AU6
AU7
AU8
AU9
AV37
AV38
AW1
AW12
AW2
AW29
AW3
AW30
AW4
U6
V12
V29
V30
A14
AD7
V6
W1
W12
W2
W3
W33
W34
AW5
AY12
AY33
AY34
B9
BA10
BA11
BA12
BA37
BA38
BA6
BA7
BA8
BA9
BB1
BB12
BB2
BB29
BB3
BB30
BB4
BB5
BB6
BC12
BC13
BC14
BC33
BC34
BC6
BD10
BD11
BD12
BD37
BD6
BD7
BD8
BD9
BE1
BE2
BE29
BE3
BE30
BE4
BE5
BE6
BF12
BF33
BF34
BF6
BG12
BG13
BG14
BG37
BG38
BG6
BH1
BH10
BH11
BH12
BH14
BH2
BH3
BH4
BH5
BH6
BH7
BH8
BH9
T2
T3
T33
T34
T4
T5
T7
T8
T9
U37
U38
BJ12
BJ14
COFFEELAKE-H-CPU_BGA1440
@
1
D
UC1H
VSS_163
VSS_244
VSS_164
VSS_245
VSS_165
VSS_246
VSS_166
VSS_247
VSS_167
VSS_248
VSS_168
VSS_249
VSS_169
VSS_250
VSS_170
VSS_251
VSS_171
VSS_252
VSS_172
VSS_253
VSS_173
VSS_254
VSS_174
VSS_255
VSS_175
VSS_256
VSS_176
VSS_257
VSS_177
VSS_258
VSS_178
VSS_259
VSS_179
VSS_260
VSS_180
VSS_261
VSS_181
VSS_262
VSS_182
VSS_263
VSS_183
VSS_264
VSS_184
VSS_265
VSS_185
VSS_266
VSS_186
VSS_267
VSS_187
VSS_268
VSS_188
VSS_269
VSS_189
VSS_270
VSS_190
VSS_271
VSS_191
VSS_272
VSS_192
VSS_273
VSS_193
VSS_274
VSS_194
VSS_275
VSS_195
VSS_276
VSS_196
VSS_277
VSS_197
VSS_278
VSS_198
VSS_279
VSS_199
VSS_280
VSS_200
VSS_281
VSS_201
VSS_282
VSS_202
VSS_283
VSS_203
VSS_284
VSS_204
VSS_285
VSS_205
VSS_286
VSS_206
VSS_287
VSS_207
VSS_288
VSS_208
VSS_289
VSS_209
VSS_290
VSS_210
VSS_291
VSS_211
VSS_292
VSS_212
VSS_293
VSS_213
VSS_294
VSS_214
VSS_295
VSS_215
VSS_296
VSS_216
VSS_297
VSS_217
VSS_298
VSS_218
VSS_299
VSS_219
VSS_300
VSS_220
VSS_301
VSS_221
VSS_302
VSS_222
VSS_303
VSS_223
VSS_304
VSS_224
VSS_305
VSS_225
VSS_306
VSS_226
VSS_307
VSS_227
VSS_308
VSS_228
VSS_309
VSS_229
VSS_310
VSS_230
VSS_311
VSS_231
VSS_312
VSS_232
VSS_313
VSS_233
VSS_314
VSS_234
VSS_315
VSS_235
VSS_316
VSS_236
VSS_317
VSS_237
VSS_318
VSS_238
VSS_319
VSS_239
VSS_320
VSS_240
VSS_321
VSS_241
VSS_322
VSS_242
VSS_323
VSS_243 OF 13 VSS_324
7
BJ15
BJ18
BJ22
BJ25
BJ29
BJ30
BJ31
BJ32
BJ33
BJ34
BJ35
BJ36
BK13
BK14
BK15
BK18
BK22
BK25
BK29
BK6
BL13
BL14
BL18
BL19
BL20
BL21
BL22
BL29
BL33
BL35
BL38
BL6
BM11
BM12
BM13
BM14
BM18
BM2
BM21
BM22
BM23
BM24
BM25
BM26
BM27
BM28
BM29
BM3
BM33
BM35
BM38
BM5
BM6
BM7
BM8
BM9
BN12
BN14
BN18
BN19
BN2
BN20
BN21
BN24
BN29
BN30
BN31
BN34
P38
P6
R12
R29
AY14
BD38
R30
T1
T10
T11
T12
T13
T14
BN4
BN7
BP12
BP14
BP18
BP21
BP24
BP25
BP26
BP29
BP33
BP34
BP7
BR12
BR14
BR18
BR21
BR24
BR25
BR26
BR29
BR34
BR36
BR7
BT12
BT14
BT18
BT21
BT24
BT26
BT29
BT32
BT5
C11
C13
C15
C17
C19
C21
C23
C25
C27
C29
C31
C37
C5
C8
C9
D10
D12
D14
D16
D18
D20
D22
D24
D26
D28
D3
D30
D33
D6
D9
E34
E35
E38
E4
E9
N3
N33
N34
N4
N5
N6
N7
N8
N9
P12
P37
M14
M6
N1
F11
F13
COFFEELAKE-H-CPU_BGA1440
@
VSS_325
VSS_409
VSS_326
VSS_410
VSS_327
VSS_411
VSS_328
VSS_412
VSS_329
VSS_413
VSS_330
VSS_414
VSS_331
VSS_415
VSS_332
VSS_416
VSS_333
VSS_417
VSS_334
VSS_418
VSS_335
VSS_419
VSS_336
VSS_420
VSS_337
VSS_421
VSS_338
VSS_422
VSS_339
VSS_423
VSS_340
VSS_424
VSS_341
VSS_425
VSS_342
VSS_426
VSS_343
VSS_427
VSS_344
VSS_428
VSS_345
VSS_429
VSS_346
VSS_430
VSS_347
VSS_431
VSS_348
VSS_432
VSS_349
VSS_433
VSS_350
VSS_434
VSS_351
VSS_435
VSS_352
VSS_436
VSS_353
VSS_437
VSS_354
VSS_438
VSS_355
VSS_439
VSS_356
VSS_440
VSS_357
VSS_441
VSS_358
VSS_442
VSS_359
VSS_443
VSS_360
VSS_444
VSS_361
VSS_445
VSS_362
VSS_446
VSS_363
VSS_447
VSS_364
VSS_448
VSS_365
VSS_449
VSS_366
VSS_450
VSS_367
VSS_451
VSS_368
VSS_452
VSS_369
VSS_453
VSS_370
VSS_454
VSS_371
VSS_455
VSS_372
VSS_456
VSS_373
VSS_457
VSS_374
VSS_458
VSS_375
VSS_459
VSS_376
VSS_460
VSS_377
VSS_461
VSS_378
VSS_462
VSS_379
VSS_463
VSS_380
VSS_464
VSS_381
VSS_465
VSS_382
VSS_466
VSS_383
VSS_467
VSS_384
VSS_468
VSS_385
VSS_469
VSS_386
VSS_470
VSS_387
VSS_471
VSS_388
VSS_472
VSS_389
VSS_473
VSS_390
VSS_474
VSS_391
VSS_475
VSS_392
VSS_476
VSS_393
VSS_477
VSS_394
VSS_478
VSS_395
VSS_479
VSS_396
VSS_397
VSS_A3
VSS_A34
VSS_398
VSS_399
VSS_A4
VSS_400
VSS_B3
VSS_401
VSS_B37
VSS_402
VSS_BR38
VSS_403
VSS_BT3
VSS_404
VSS_BT35
VSS_405
VSS_BT36
VSS_406
VSS_BT4
VSS_407
VSS_C2
VSS_408 OF 13VSS_D38
8
F15
F17
F19
F2
F21
F23
F25
F27
F29
F3
F31
F36
F4
F5
F8
F9
G10
G12
G14
G16
G18
G20
G22
G23
G24
G26
G28
G4
G5
G6
G8
G9
H11
H12
H18
H22
H25
H32
H35
J10
J18
J22
J25
J32
J33
J36
J4
J7
K1
K10
K11
K2
K3
K38
K4
K5
K7
K8
K9
L29
L30
L33
L34
M12
M13
N10
N11
N12
N2
BT8
BR9
C
A3
A34
A4
B3
B37
BR38
BT3
BT35
BT36
BT4
C2
D38
B
COFFEELAKE-H-CPU_BGA1440
@
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/02/26
Deciphered Date
https://Dr-Bios.com
2018/09/20
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
5
4
3
2
CPU (6/7) PWR, VSS
Size
C
Date:
Document Number
Rev
0.1
FG541/FG741
Thursday, January 03, 2019
1
Sheet
11
of
69
5
4
3
2
1
+1.2V
DDRA_DQ[0..63]
DDRA_DQ[0..63]
CD47
2
F1
H1
A2
D2
E3
A8
D8
E8
C9
H9
0.1u_0201_10V6K
@ 1
P1
C
PAR
VREFCA
TEN
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
RESET_N
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10
NC
DDRA_BG0
M2
DDRA_ODT0
K3
+2.5V_DDR
B1
R9
+VREF_CA_MD
M1
E1
K1
N1
T1
B2
G8
E9
K9
M9
1
MD@
UD1_DDRA_UZQ
DDRA_BG1_R
2
DDRA_PAR
@
1
2
MD@
1
2
CD@
1
2
RD95 1 MD@
T3
2 10K_0402_5% TEN_UD2
N9
PCH_DRAMRST#
@
1
T7
2
P1
F1
H1
A2
D2
E3
A8
D8
E8
C9
H9
RD101
0_0402_5%
DDP@
ZQ
F9
1
2
F9
ODT
L3
L7
P9
BA0
BA1
ACT_N
CS_N
ALERT_N
BG0
ODT
VPP1
VPP2
PAR
VREFCA
TEN
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
RESET_N
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10
NC
2 0_0402_5%
1
2
1
1
1 MD@
1 MD@
2
2
36_0402_1%
36_0402_1%
RD53
1 MD@
2
36_0402_1%
RD54
RD55
RD56
RD57
1 MD@
1 MD@
1 MD@
1 MD@
2
2
2
2
36_0402_1%
36_0402_1%
36_0402_1%
36_0402_1%
RD58
RD59
RD60
RD61
1 MD@
1 MD@
1 MD@
1 MD@
2
2
2
2
36_0402_1%
36_0402_1%
36_0402_1%
36_0402_1%
RD62
RD63
RD64
RD67
1 MD@
1 MD@
1 MD@
1 MD@
2
2
2
2
36_0402_1%
36_0402_1%
36_0402_1%
36_0402_1%
1 MD@
1 MD@
1 MD@
1 MD@
2
2
2
2
36_0402_1%
36_0402_1%
36_0402_1%
36_0402_1%
DDRA_MA16_RAS#
RD74
DDRA_BG0
RD75
DDRA_BA0
RD76
DDRA_BA1
RD77
1 MD@
1 MD@
1 MD@
1 MD@
2
2
2
2
36_0402_1%
36_0402_1%
36_0402_1%
36_0402_1%
DDRA_ACT#
DDRA_PAR
RD78
RD79
1 MD@
1 MD@
2
2
36_0402_1%
36_0402_1%
RD234
1 DDP@
2
36_0402_1%
D
DDRA_MA0
DDRA_MA1
DDRA_MA2
DDRA_MA3
2
1 SDP@
R10145
UD2_DDRA_UZQ
2 240_0402_1%
1 SDP@
R10147
2 0_0402_5%
RD231 1 DDP@
UD3_DDRA_UZQ
2 0_0402_5%
1 DDP@
RD233
2 240_0402_1%
1 SDP@
R10151
2 0_0402_5%
1 DDP@
RD232
UD4_DDRA_UZQ
2 240_0402_1%
1 SDP@
R10148
+2.5V_DDR
B1
R9
DDRA_MA8
DDRA_MA9
DDRA_MA10
DDRA_MA11
2 0_0402_5%
2 240_0402_1%
+VREF_CA_MD
MD@
1
2
UD2_DDRA_UZQ
DDRA_BG1_R
1
@
2
MD@
1
2
MD@
1
2
DDRA_BG1_R
+0.6VS
+1.2V
DDRA_ALERT#
DDRA_CLK0#
1 MD@
RD86
2 49.9_0402_1%
RD49
1 MD@
2
RD50
1 MD@
2
@
36_0402_1%
RD98
0_0402_5%
36_0402_1%
T7
C10121
1
RD102
0_0402_5%
DDP@
ZQ
DDRA_CLK0
2
0.01U_0201_10V6K
MD@
C
Follow 1.0PDG add termination 0.01UF_0201 capacitor
between DDRA_CLK0 and DDRA_CLK0#
Terminate CLK signals PH to VDDQ --SF0904
2
R10575
1
RD51
RD52
DDRA_CKE0
R13 DDP@ 0R short
DDRA_BG1_R
DDRA_CS0#
DDRA_ODT0
DDRA_MA12
RD70
DDRA_MA13
RD71
DDRA_MA14_WE#
RD72
DDRA_MA15_CAS#
RD73
2
2
2
RD40 MT40A512M16HA083EA_FBGA96
MD@ 240_0402_1%
2
MD@ RD39 MT40A512M16HA083EA_FBGA96
240_0402_1%
+0.6VS
@
CD112
0.1u_0201_10V6K
MD@
RD228 1 DDP@
A1
C1
G1
F2
J2
F8
J8
A9
D9
G9
E1
K1
N1
T1
B2
G8
E9
K9
M9
{7}
+VREF_CA_MD
1
RD47
MD@ 1.8K_0402_1%
UD1_DDRA_UZQ
M1
{7}
2
N9
PCH_DRAMRST#
N2
N8
DDRA_ACT#
DDRA_CS0#
DDRA_ALERT#
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
DDRA_DQS[0..7]
DDRA_MA[0..13]
1
T3
2 10K_0402_5% TEN_UD1
VPP1
VPP2
DDRA_BA0
DDRA_BA1
NF/UDM_N/UDBI_N
NF/LDM_N/LDBI_N
{7}
DDRA_DQS[0..7]
DDRA_MA[0..13]
1
1U_0402_6.3V6K
RD94 1 MD@
BG0
E2
E7
1
DDRA_PAR
{7} DDRA_PAR
{13,16} PCH_DRAMRST#
ACT_N
CS_N
ALERT_N
DDRA_DM3
DDRA_DM2
LDQS_C
LDQS_T
UDQS_C
UDQS_T
1U_0402_6.3V6K
K3
2 0_0402_5%
2 0_0402_5%
CKE
DDRA_DQS#[0..7]
MD@
RD45
1.8K_0402_1%
DDRA_MA4
DDRA_MA5
DDRA_MA6
DDRA_MA7
CD125
M2
DDRA_ODT0
{7} DDRA_ODT0
@
@
CK_C
CK_T
D1
J1
L1
R1
B3
G7
B9
J9
L9
T9
CD124
DDRA_BG0
{7} DDRA_BG0
BA0
BA1
RD66 1
RD69 1
RD48
24.9_0402_1%
0.1u_0201_10V6K
L3
L7
P9
+1.2V
A1
C1
G1
F2
J2
F8
J8
A9
D9
G9
MD@
CD111
0.022U_0201_6.3V6-K
+1.2V
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
2
2 MD@
RD46 1
2.7_0402_1%
{7} DDR_SA_VREFCA
.047U_0201_6.3V6K
N2
N8
DDRA_ACT#
DDRA_CS0#
DDRA_ALERT#
{7} DDRA_ACT#
{7} DDRA_CS0#
{7} DDRA_ALERT#
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
WE_N/A14
CAS_N/A15
RAS_N/A16
1
@
CD119
0.1u_0201_10V6K
DDRA_DQ18
DDRA_DQ19
DDRA_DQ22
DDRA_DQ21
DDRA_DQ23
DDRA_DQ17
DDRA_DQ16
DDRA_DQ20
DDRA_DQ30
DDRA_DQ28
DDRA_DQ26
DDRA_DQ25
DDRA_DQ31
DDRA_DQ24
DDRA_DQ27
DDRA_DQ29
G2
F7
H3
H7
H2
H8
J3
J7
A3
B8
C3
C7
C2
C8
D3
D7
CD122
DDRA_BA0
DDRA_BA1
{7} DDRA_BA0
{7} DDRA_BA1
NF/UDM_N/UDBI_N
NF/LDM_N/LDBI_N
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
CD114
E2
E7
F3
G3
A7
B7
DDRA_DQS#[0..7]
@
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC_N
A13
2
DDRA_DM1
DDRA_DM0
CD48
2 0_0402_5%
2 0_0402_5%
K2
DDRA_DQS#2
DDRA_DQS2
DDRA_DQS#3
DDRA_DQS3
0.1u_0201_10V6K
@
@
K8
K7
DDRA_CKE0
1U_0402_6.3V6K
RD65 1
RD68 1
LDQS_C
LDQS_T
UDQS_C
UDQS_T
1U_0402_6.3V6K
+1.2V
CKE
CD123
F3
G3
A7
B7
CD121
K2
DDRA_DQS#0
DDRA_DQS0
DDRA_DQS#1
DDRA_DQS1
D1
J1
L1
R1
B3
G7
B9
J9
L9
T9
L2
M8
L8
DDRA_CLK0#
DDRA_CLK0
+1.2V
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
P3
P7
R3
N7
N3
P8
P2
R8
R2
R7
M3
T2
M7
T8
DDRA_MA14_WE#
DDRA_MA15_CAS#
DDRA_MA16_RAS#
0.1u_0201_10V6K
DDRA_CKE0
{7} DDRA_CKE0
CK_C
CK_T
DDRA_MA0
DDRA_MA1
DDRA_MA2
DDRA_MA3
DDRA_MA4
DDRA_MA5
DDRA_MA6
DDRA_MA7
DDRA_MA8
DDRA_MA9
DDRA_MA10
DDRA_MA11
DDRA_MA12
DDRA_MA13
.047U_0201_6.3V6K
K8
K7
WE_N/A14
CAS_N/A15
RAS_N/A16
UD2
DDRA_DQ2
DDRA_DQ3
DDRA_DQ6
DDRA_DQ1
DDRA_DQ7
DDRA_DQ0
DDRA_DQ4
DDRA_DQ5
DDRA_DQ11
DDRA_DQ13
DDRA_DQ14
DDRA_DQ12
DDRA_DQ15
DDRA_DQ8
DDRA_DQ10
DDRA_DQ9
G2
F7
H3
H7
H2
H8
J3
J7
A3
B8
C3
C7
C2
C8
D3
D7
CD120
DDRA_CLK0#
DDRA_CLK0
{7} DDRA_CLK0#
{7} DDRA_CLK0
L2
M8
L8
@
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
CD113
DDRA_MA14_WE#
DDRA_MA15_CAS#
DDRA_MA16_RAS#
{7} DDRA_MA14_WE#
{7} DDRA_MA15_CAS#
{7} DDRA_MA16_RAS#
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC_N
A13
1
D
P3
P7
R3
N7
N3
P8
P2
R8
R2
R7
M3
T2
M7
T8
1
UD1
DDRA_MA0
DDRA_MA1
DDRA_MA2
DDRA_MA3
DDRA_MA4
DDRA_MA5
DDRA_MA6
DDRA_MA7
DDRA_MA8
DDRA_MA9
DDRA_MA10
DDRA_MA11
DDRA_MA12
DDRA_MA13
{7}
DDRA_BG1
DDRA_BG1 {7}
1
DDP@
+1.2V
(1uF_0402_6.3V) *16
Place 4 near each DRAM
2
R10576
0_0402_5%
SDP@
NC
2
CD@
1
2
MD@
1
2
CD146
2
10U_0603_6.3V6M
10U_0603_6.3V6M
CD145
CD144
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
CD143
1
1
2
CD109
22P_0402_50V8-J
RF@
2
1
2
CD110
22P_0402_50V8-J
RF@
B
+2.5V_DDR
E1
K1
N1
T1
B2
G8
E9
K9
M9
MD@
1
2
UD4_DDRA_UZQ
DDRA_BG1_R
@
1
2
CD@
1
2
MD@
1
2
MD@
1
2
MD@
1
2
CD@
1
2
1
2
CD157
22P_0402_50V8-J
RF@
1
2
CD148
22P_0402_50V8-J
RF@
T7
+0.6VS
(1uF_0402_6.3V) *8
Place 2 near each DRAM
RD100
0_0402_5%
DDP@
ZQ
(1OuF_0603_6.3V) *2
Place around the DRAMs
1
2
CD@
CD@
1
2
CD@
1
2
1
2
Issued Date
MD@
CD@
1
2
MD@
1
2
1
2
MD@
CD@
1
2
10U_0603_6.3V6M
2
CD167
1
10U_0603_6.3V6M
CD158
MD@
1U_0402_6.3V6K
2
2
CD166
1
2
MD@
+0.6VS
1
2
Deciphered Date
CD168
22P_0402_50V8-J
RF@
https://Dr-Bios.com
2
2
CD169
22P_0402_50V8-J
RF@
A
DDR4 Memory Down
2018/09/20
Size
Document
Custom
Number
1
Re v
0.1
FG541/FG741
Thursday, January 03, 2019
Date :
3
1
Title
LC Future Center Secret Data
2016/12/14
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
4
1
+1.2V
CD@
Security Classification
5
MD@
1U_0402_6.3V6K
1
1U_0402_6.3V6K
MD@
CD141
2
1U_0402_6.3V6K
1
CD140
CD@
1U_0402_6.3V6K
2
CD139
1
1U_0402_6.3V6K
MD@
CD138
2
1U_0402_6.3V6K
1
CD137
MD@
1U_0402_6.3V6K
2
CD136
1
1U_0402_6.3V6K
MD@
CD135
2
1U_0402_6.3V6K
1
CD134
1U_0402_6.3V6K
MD@
CD133
1U_0402_6.3V6K
1
2
CD132
1U_0402_6.3V6K
CD130
CD131
1U_0402_6.3V6K
1U_0402_6.3V6K
CD129
1U_0402_6.3V6K
CD128
CD127
CD126
CD142
+VREF_CA_MD
M1
RD44 MT40A512M16HA083EA_FBGA96
MD@ 240_0402_1%
A
CD@
1U_0402_6.3V6K
RD43 MT40A512M16HA083EA_FBGA96
MD@ 240_0402_1%
2
CD165
F9
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10
1
CD164
RD99
0_0402_5%
DDP@
ZQ
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
RESET_N
CD@
1U_0402_6.3V6K
2
F1
H1
A2
D2
E3
A8
D8
E8
C9
H9
VREFCA
TEN
1
2
1U_0402_6.3V6K
1
PAR
MD@
CD163
@
P1
1
2
CD162
N9
PCH_DRAMRST#
CD@
10U_0603_6.3V6M
T3
TEN_UD4
MD@ 2 10K_0402_5%
CD147
DDRA_PAR
RD97 1
1U_0402_6.3V6K
2
10U_0603_6.3V6M
1
1
2
CD161
T7
CD@
1
2
MD@
1U_0402_6.3V6K
2
10U_0603_6.3V6M
1
MD@
(1OuF_0603_6.3V) *3
Place around the DRAMs
CD160
2
CD@
1
2
CD156
2
1
2
CD@
1U_0402_6.3V6K
DDRA_BG1_R
@
1U_0402_6.3V6K
UD3_DDRA_UZQ
1
1
(1OuF_0603_6.3V) *5
Place around the DRAMs
+2.5V_DDR
CD152
MD@
MD@
+2.5V_DDR
B1
R9
1U_0402_6.3V6K
E1
K1
N1
T1
B2
G8
E9
K9
M9
VPP1
VPP2
A1
C1
G1
F2
J2
F8
J8
A9
D9
G9
1U_0402_6.3V6K
M1
ODT
1
2
CD155
K3
BG0
CD@
CD154
DDRA_ODT0
+VREF_CA_MD
ACT_N
CS_N
ALERT_N
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
D1
J1
L1
R1
B3
G7
B9
J9
L9
T9
0.1u_0201_10V6K
M2
BA0
BA1
2
CD159
NC
L3
L7
P9
DDRA_BG0
NF/UDM_N/UDBI_N
NF/LDM_N/LDBI_N
1
+1.2V
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
.047U_0201_6.3V6K
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10
1
F9
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
RESET_N
DDRA_ACT#
DDRA_CS0#
DDRA_ALERT#
+2.5V_DDR
B1
R9
LDQS_C
LDQS_T
UDQS_C
UDQS_T
CD@
+1.2V
CD153
F1
H1
A2
D2
E3
A8
D8
E8
C9
H9
VREFCA
TEN
N2
N8
CKE
1
2
CD116
2
PAR
E2
E7
CK_C
CK_T
MD@
DDRA_DQ59
DDRA_DQ56
DDRA_DQ63
DDRA_DQ60
DDRA_DQ62
DDRA_DQ61
DDRA_DQ58
DDRA_DQ57
DDRA_DQ52
DDRA_DQ48
DDRA_DQ55
DDRA_DQ54
DDRA_DQ53
DDRA_DQ50
DDRA_DQ51
DDRA_DQ49
G2
F7
H3
H7
H2
H8
J3
J7
A3
B8
C3
C7
C2
C8
D3
D7
1
CD107
1
0.1u_0201_10V6K
@
P1
2 0_0402_5%
2 0_0402_5%
WE_N/A14
CAS_N/A15
RAS_N/A16
@
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
2
N9
PCH_DRAMRST#
ODT
VPP1
VPP2
@
@
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC_N
A13
1
T3
2 10K_0402_5% TEN_UD3
BG0
RD89 1
RD90 1
DDRA_DM6
DDRA_DM7
DDRA_BA0
DDRA_BA1
+1.2V
A1
C1
G1
F2
J2
F8
J8
A9
D9
G9
F3
G3
A7
B7
0.1u_0201_10V6K
RD96 1 MD@
ACT_N
CS_N
ALERT_N
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
K2
DDRA_DQS#7
DDRA_DQS7
DDRA_DQS#6
DDRA_DQS6
CD108
DDRA_PAR
BA0
BA1
K8
K7
DDRA_CKE0
1U_0402_6.3V6K
K3
NF/UDM_N/UDBI_N
NF/LDM_N/LDBI_N
L2
M8
L8
DDRA_CLK0#
DDRA_CLK0
D1
J1
L1
R1
B3
G7
B9
J9
L9
T9
CD151
M2
LDQS_C
LDQS_T
UDQS_C
UDQS_T
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
1U_0402_6.3V6K
L3
L7
P9
DDRA_ODT0
2 0_0402_5%
2 0_0402_5%
N2
N8
DDRA_BG0
@
@
E2
E7
DDRA_ACT#
DDRA_CS0#
DDRA_ALERT#
RD87 1
RD88 1
DDRA_DM4
DDRA_DM5
DDRA_BA0
DDRA_BA1
+1.2V
F3
G3
A7
B7
CKE
CD150
DDRA_DQS#5
DDRA_DQS5
DDRA_DQS#4
DDRA_DQS4
CK_C
CK_T
P3
P7
R3
N7
N3
P8
P2
R8
R2
R7
M3
T2
M7
T8
DDRA_MA14_WE#
DDRA_MA15_CAS#
DDRA_MA16_RAS#
+1.2V
0.1u_0201_10V6K
K2
DDRA_MA0
DDRA_MA1
DDRA_MA2
DDRA_MA3
DDRA_MA4
DDRA_MA5
DDRA_MA6
DDRA_MA7
DDRA_MA8
DDRA_MA9
DDRA_MA10
DDRA_MA11
DDRA_MA12
DDRA_MA13
.047U_0201_6.3V6K
K8
K7
DDRA_CKE0
UD4
DDRA_DQ47
DDRA_DQ45
DDRA_DQ42
DDRA_DQ41
DDRA_DQ43
DDRA_DQ40
DDRA_DQ46
DDRA_DQ44
DDRA_DQ34
DDRA_DQ37
DDRA_DQ39
DDRA_DQ32
DDRA_DQ38
DDRA_DQ33
DDRA_DQ35
DDRA_DQ36
G2
F7
H3
H7
H2
H8
J3
J7
A3
B8
C3
C7
C2
C8
D3
D7
CD149
DDRA_CLK0#
DDRA_CLK0
WE_N/A14
CAS_N/A15
RAS_N/A16
@
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
CD115
L2
M8
L8
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC_N
A13
2
DDRA_MA14_WE#
DDRA_MA15_CAS#
DDRA_MA16_RAS#
B
P3
P7
R3
N7
N3
P8
P2
R8
R2
R7
M3
T2
M7
T8
1
UD3
DDRA_MA0
DDRA_MA1
DDRA_MA2
DDRA_MA3
DDRA_MA4
DDRA_MA5
DDRA_MA6
DDRA_MA7
DDRA_MA8
DDRA_MA9
DDRA_MA10
DDRA_MA11
DDRA_MA12
DDRA_MA13
1U_0402_6.3V6K
R17 SDP@ 0R PD
Sheet
12
of
69
5
4
3
2
1
+1.2V
DDR4 SO-DIMM
DDRB_DQ[0..63]
{7}
1
DDRB_DQ[0..63]
DDRB_DQS#[0..7]
+1.2V
+1.2V
+1.2V
DDRB_DQS#[0..7]
+1.2V
{7}
+1.2V
DDRB_DQS[0..7]
JDDR1A
+1.2V
+1.2V
RD91
240_0402_1%
@
+1.2V
JDDR1B
{7}
2
DDRB_DQS[0..7]
D
DDRB_DQ7
DDRB_DQ10
DDRB_DQ14
DDRB_DQ11
DDRB_DQ15
DDRB_DQ16
DDRB_DQ17
DDRB_DQS#2
DDRB_DQS2
DDRB_DQ21
DDRB_DQ20
DDRB_DQ25
DDRB_DQ30
+1.2V
DDRB_DQ29
1
1
DDRB_DQ24
2
RD93
240_0402_1%
2
RD92
240_0402_1%
DDRB_DQS#8
DDRB_DQS8
C
DDRB_CKE0
{7} DDRB_CKE0
{7} DDRB_BG1
{7} DDRB_BG0
{7} DDRB_MA12
{7} DDRB_MA9
{7} DDRB_MA8
{7} DDRB_MA6
DDRB_BG1
DDRB_BG0
DDRB_MA12
DDRB_MA9
DDRB_MA8
DDRB_MA6
{7} DDRB_MA3
{7} DDRB_MA1
DDRB_DQ5
DDRB_DQ1
131
133
135
137
139
141
143
DDRB_CLK0
DDRB_CLK0#
{7} DDRB_CLK0
{7} DDRB_CLK0#
DDRB_PAR
{7} DDRB_PAR
DDRB_DQ3
DDRB_DQ6
DDRB_BA1
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
205
207
209
211
213
215
217
219
221
223
225
227
229
231
233
235
237
239
241
243
245
247
249
251
253
255
257
259
{7} DDRB_BA1
DDRB_DQ9
DDRB_DQ8
DDRB_DQS#1
DDRB_DQS1
DDRB_CS0#
DDRB_MA14_WE#
{7} DDRB_CS0#
{7} DDRB_MA14_WE#
{7} DDRB_ODT0
{7} DDRB_CS1#
DDRB_ODT0
DDRB_CS1#
DDRB_ODT1
{7} DDRB_ODT1
DDRB_DQ13
DDRB_DQ12
DDRB_DQ35
DDRB_DQ22
DDRB_DQ39
DDRB_DQ18
DDRB_DQS#4
DDRB_DQS4
DDRB_DQ19
DDRB_DQ36
DDRB_DQ23
DDRB_DQ34
DDRB_DQ27
DDRB_DQ45
DDRB_DQ28
DDRB_DQ40
DDRB_DQS#3
DDRB_DQS3
DDRB_DQ47
DDRB_DQ26
DDRB_DQ42
DDRB_DQ31
DDRB_DQ48
DDRB_DQ52
DDRB_DQS#6
DDRB_DQS6
DDRB_DQ53
DDRB_DQ49
CPU_DRAMRST#
DDRB_CKE1
DDRB_DQ59
PCH_DRAMRST# {12,16}
DDRB_CKE1 {7}
DDRB_ACT#
DDRB_ALERT#
DDRB_MA11
DDRB_MA7
DDRB_MA5
DDRB_MA4
DDRB_DQ62
1
CD3
0.1u_0201_10V6K
@
DDRB_ACT# {7}
DDRB_ALERT# {7}
DDRB_MA11 {7}
DDRB_MA7 {7}
2
DDRB_DQ58
DDRB_DQ56
DDRB_MA5 {7}
DDRB_MA4 {7}
RD1
+3VS
ARGOS_D4AS0-26001-1P60
ME@
CD4
2.2U_0402_6.3V6M
RD2
+2.5V_DDR
SMB_CLK_S3
+VDD_SPD
{16} SMB_CLK_S3
1
2
@
0_0603_5%
1
1
2
2
261
CD5
0.1u_0201_10V6K
A3
A1
VDD_9
CK0_t
CK0_c
VDD_11
Parity
A2
EVENT_n
VDD_10
CK1_t
CK1_c
VDD_12
A0
BA1
A10/AP
VDD_13
VDD_14
CS0_n
BA0
WE_n/A14
RAS_n/A16
VDD_15
VDD_16
ODT0
CAS_n/A15
CS1_n
A13
VDD_17
VDD_18
ODT1
C0/CS2_n/NC
VDD_19
VREFCA
C1/CS3_n/NC
SA2
VSS_53
VSS_54
DQ37
DQ36
VSS_55
VSS_56
DQ33
DQ32
VSS_57
VSS_58
DQS4_c DM4_n/DBl4_n/NC
DQS4_t
VSS_59
VSS_60
DQ39
DQ38
VSS_61
VSS_62
DQ35
DQ34
VSS_63
VSS_64
DQ45
DQ44
VSS_65
VSS_66
DQ41
DQ40
VSS_67
VSS_68
DQS5_c
DM5_n/DBl5_n/NC DQS5_t
VSS_69
VSS_70
DQ46
DQ47
VSS_71
VSS_72
DQ42
DQ43
VSS_73
VSS_74
DQ52
DQ53
VSS_75
VSS_76
DQ49
DQ48
VSS_77
VSS_78
DQS6_c DM6_n/DBl6_n/NC
DQS6_t
VSS_79
VSS_80
DQ54
DQ55
VSS_81
VSS_82
DQ50
DQ51
VSS_83
VSS_84
DQ60
DQ61
VSS_85
VSS_86
DQ57
DQ56
VSS_87
VSS_88
DQS7_c
DM7_n/DBl7_n/NC DQS7_t
VSS_89
VSS_90
DQ62
DQ63
VSS_91
VSS_92
DQ58
DQ59
VSS_93
VSS_94
SCL
SDA
VDDSPD
SA0
VPP_1
Vtt
VPP_2
SA1
GND_1
GND_2
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
208
210
212
214
216
218
220
222
224
226
228
230
232
234
236
238
240
242
244
246
248
250
252
254
256
258
260
DDRB_MA10
DDRB_MA2 {7}
DDRB_CLK1
DDRB_CLK1#
DDRB_CLK1 {7}
DDRB_CLK1# {7}
DDRB_MA0
DDRB_MA0 {7}
D
DDRB_MA10 {7}
DDRB_BA0
DDRB_MA16_RAS#
DDRB_BA0 {7}
DDRB_MA16_RAS# {7}
DDRB_MA15_CAS#
DDRB_MA13
DDRB_MA15_CAS# {7}
DDRB_MA13 {7}
+VREF_CA_DIMM
DDRB_SA2
@
DDRB_DQ33
1
DDRB_DQ38
2
DDRB_DQ32
@
1
2
2.2U_0402_6.3V6M
DDRB_DQ2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
0.1u_0201_10V6K
DDRB_DQS#0
DDRB_DQS0
VSS_1
VSS_2
DQ5
DQ4
VSS_3
VSS_4
DQ1
DQ0
VSS_5
VSS_6
DQS0_C DM0_n/DBIO_n/NC
DQS0_t
VSS_7
VSS_8
DQ6
DQ7
VSS_9
VSS_10
DQ2
DQ3
VSS_11
VSS_12
DQ12
DQ13
VSS_13
VSS_14
DQ8
DQ9
VSS_15
VSS_16
DQS1_c
DM1_n/DBl1_n/NC DQS1_t
VSS_17
VSS_18
DQ15
DQ14
VSS_19
VSS_20
DQ10
DQ11
VSS_21
VSS_22
DQ21
DQ20
VSS_23
VSS_24
DQ17
DQ16
VSS_25
VSS_26
DQS2_c DM2_n/DBl2_n/NC
DQS2_t
VSS_27
VSS_28
DQ22
DQ23
VSS_29
VSS_30
DQ18
DQ19
VSS_31
VSS_32
DQ28
DQ29
VSS_33
VSS_34
DQ24
DQ25
VSS_35
VSS_36
DQS3_c
DM3_n/DBl3_n/NC DQS3_t
VSS_37
VSS_38
DQ30
DQ31
VSS_39
VSS_40
DQ26
DQ27
VSS_41
VSS_42
CB5/NC
CB4/NC
VSS_43
VSS_44
CB1/NC
CB0/NC
VSS_45
VSS_46
DQS8_c DM8_n/DBI8_n/NC
DQS8_t
VSS_47
VSS_48
CB6/NC
CB2/NC
VSS_49
VSS_50
CB7/NC
CB3/NC
VSS_51
VSS_52
RESET_n
CKE0
CKE1
VDD_1
VDD_2
BG1
ACT_n
BG0
ALERT_n
VDD_3
VDD_4
A12
A11
A9
A7
VDD_5
VDD_6
A8
A5
A6
A4
VDD_7
VDD_8
CD2
DDRB_DQ0
DDRB_MA2
DDRB_EVENT#
CD1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
DDRB_DQ4
DDRB_MA3
DDRB_MA1
DDRB_DQ37
DDRB_DQ41
DDRB_DQ44
DDRB_DQS#5
DDRB_DQS5
DDRB_DQ46
DDRB_DQ43
DDRB_DQ51
DDRB_DQ54
DDRB_DQ55
DDRB_DQ50
C
DDRB_DQ61
DDRB_DQ57
DDRB_DQS#7
DDRB_DQS7
DDRB_DQ60
DDRB_DQ63
SMB_DATA_S3
DDRB_SA0
SMB_DATA_S3 {16}
+0.6VS
DDRB_SA1
262
ARGOS_D4AS0-26001-1P60
ME@
1
2
@
0_0603_5%
+VPP
+1.2V
1
2
@
2
CD@
1
2
1
2
CD@
1
2
1U_0402_6.3V6K
1
1U_0402_6.3V6K
CD@
CD12
2
10U_0603_6.3V6M
1
CD11
2
10U_0603_6.3V6M
1
CD10
CD14
0.1u_0201_10V6K
2
CD9
RD5
1K_0402_1%
CD6
1 @
1
CD13
0.022U_0201_6.3V6-K
1
B
2
1
2
2
10U_0603_6.3V6M
1
+VREF_CA_DIMM
1
2
2_0402_5%
10U_0603_6.3V6M
RD4
1
CD8
2
B
+2.5V_DDR
1U_0402_6.3V6K
+0.6VS
Layout Note:
Place near DIMM
CD7
Note:
VREF trace width:20 mils at least
Spacing:20mils to other signal/planes
Place near DIMM scoket
RD3
1K_0402_1%
1U_0402_6.3V6K
2
CD118
@
CD117
0.1u_0201_10V6K
1
+VREF_DQ_DIMMB_R
RD6
24.9_0402_1%
+3VS
+3VS
1
2
CD@
1
2
1U_0402_6.3V6K
1
1U_0402_6.3V6K
2
CD34
1
1U_0402_6.3V6K
2
CD33
1
CD32
1U_0402_6.3V6K
2
CD31
CD@
1
1U_0402_6.3V6K
2
CD30
1
1U_0402_6.3V6K
2
1U_0402_6.3V6K
1
CD29
2
1U_0402_6.3V6K
1
CD28
2
10U_0603_6.3V6M
1
CD27
2
10U_0603_6.3V6M
1
CD26
CD@
2
10U_0603_6.3V6M
1
CD25
2
10U_0603_6.3V6M
1
CD24
2
10U_0603_6.3V6M
1
CD23
10U_0603_6.3V6M
2
CD22
10U_0603_6.3V6M
1
CD21
2
1
CD@
1
+3VS
1
CD19
2
10U_0603_6.3V6M
1
CD20
2
+1.2V
For EMC
RF@
2
A
Near JDDRL1
Issued Date
Title
LC Future Center Secret Data
Security Classification
SPD Address = 2H
1
33P_0402_50V8J
2
CD37
RF@
1
33P_0402_50V8J
2
CD36
EMC_NS@
1
0.1u_0201_10V6K
2
0.1u_0201_10V6K
1
CD18
2
EMC_NS@
1
4.7U_0402_6.3V6M
CD15
RD12
0_0402_5%
@
2
RD11
0_0402_5%
@
2
2
RD10
0_0402_5%
@
1
1
1
2
EMC_NS@
EMC_NS@
1
DDRB_SA2
CD17
DDRB_SA1
A
CD16
DDRB_SA0
RD9
0_0402_5%
@
2
2
2
RD8
0_0402_5%
@
4.7U_0402_6.3V6M
+1.2V
RD7
0_0402_5%
@
2015/08/20
DDR4 SO-DIMM
2018/09/20
Deciphered Date
https://Dr-Bios.com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Size
Document Number
Custom
Date:
5
4
3
2
Re v
0.1
FG541/FG741
Tuesday, January 22, 2019
Sheet
1
13
of
69
5
4
3
2
1
1
+3VS
UH1C
P48
V47
V48
W47
{20,49} EC_SCI#
RH95
EC_SCI#
{45}
{45}
{45}
{45}
@
PAD
@
IT36
Reserve interrupt for UCMcx
NGFF SSD
1
2
L47
L46
U48
U47
N48
N47
P47
R46
0_0201_5%
1
PCIE_PTX_DRX_P11
PCIE_PTX_DRX_N11
PCIE_PRX_DTX_P11
PCIE_PRX_DTX_N11
PCIE_PTX_DRX_P11
PCIE_PTX_DRX_N11
PCIE_PRX_DTX_P11
PCIE_PRX_DTX_N11
C36
B36
F39
G38
AR42
AR48
AU47
AU46
LAN
C
WLAN
NGFF SSD
{42}
{42}
{42}
{42}
PCIE_PTX_C_DRX_N14
PCIE_PTX_C_DRX_P14
PCIE_PRX_DTX_N14
PCIE_PRX_DTX_P14
{45}
{45}
{45}
{45}
PCIE_PTX_C_DRX_N13
PCIE_PTX_C_DRX_P13
PCIE_PRX_DTX_N13
PCIE_PRX_DTX_P13
{45}
{45}
{45}
{45}
CH15 1
CH16 1
CH17 1
CH18 1
2 0.1u_0201_10V6K
2 0.1u_0201_10V6K
PCIE_PTX_DRX_N14
PCIE_PTX_DRX_P14
PCIE_PRX_DTX_N14
PCIE_PRX_DTX_P14
C39
D39
D46
C47
PCIE_SATA_PTX_DRX_P12
PCIE_SATA_PTX_DRX_N12
PCIE_SATA_PRX_DTX_P12
PCIE_SATA_PRX_DTX_N12
PCIE_PTX_DRX_N13
PCIE_PTX_DRX_P13
PCIE_PRX_DTX_N13
PCIE_PRX_DTX_P13
B38
C38
C45
C46
PCIE_SATA_PTX_DRX_P12
PCIE_SATA_PTX_DRX_N12
PCIE_SATA_PRX_DTX_P12
PCIE_SATA_PRX_DTX_N12
2 0.1u_0201_10V6K
2 0.1u_0201_10V6K
E37
D38
J41
H42
B44
A44
R37
R35
D43
C44
N42
M44
CL_CLK
CL_DATA
CL_RST#
PCIE9_RXN
PCIE9_RXP
PCIE9_TXN
PCIE9_TXP
GPP_K8
GPP_K9
GPP_K10
GPP_K11
PCIE10_RXN
PCIE10_RXP
PCIE10_TXN
PCIE10_TXP
GPP_K0
GPP_K1
GPP_K2
GPP_K3
GPP_K4
GPP_K5
GPP_K6
GPP_K7
PCIE15_RXN/SATA2_RXN
PCIE15_RXP/SATA2_RXP
PCIE15_TXN/SATA2_TXN
PCIE15_TXP/SATA2_TXP
PCIE16_RXN/SATA3_RXN
PCIE16_RXP/SATA3_RXP
PCIE16_TXN/SATA3_TXN
PCIE16_TXP/SATA3_TXP
PCIE11_TXP/SATA0A_TXP
PCIE11_TXN/SATA0A_TXN
PCIE11_RXP/SATA0A_RXP
PCIE11_RXN/SATA0A_RXN
PCIE17_RXN/SATA4_RXN
PCIE17_RXP/SATA4_RXP
PCIE17_TXN/SATA4_TXN
PCIE17_TXP/SATA4_TXP
GPP_F10/SATA_SCLOCK
GPP_F11/SATA_SLOAD
GPP_F13/SATA_SDATAOUT0
GPP_F12/SATA_SDATAOUT1
PCIE14_TXN/SATA1B_TXN
PCIE14_TXP/SATA1B_TXP
PCIE14_RXN/SATA1B_RXN
PCIE14_RXP/SATA1B_RXP
PCIE13_TXN/SATA0B_TXN
PCIE13_TXP/SATA0B_TXP
PCIE13_RXN/SATA0B_RXN
PCIE13_RXP/SATA0B_RXP
PCIE18_RXN/SATA5_RXN
PCIE18_RXP/SATA5_RXP
PCIE18_TXN/SATA5_TXN
PCIE18_TXP/SATA5_TXP
GPP_E8/SATA_LED#
GPP_E0/SATAXPCIE0/SATAGP0
GPP_E1/SATAXPCIE1/SATAGP1
GPP_E2/SATAXPCIE2/SATAGP2
GPP_F0/SATAXPCIE3/SATAGP_3
GPP_F1/SATAXPCIE4/SATAGP4
GPP_F2/SATAXPCIE5/SATAGP5
GPP_F3/SATAXPCIE6/SATAGP6
GPP_F4/SATAXPCIE7/SATAGP7
GPP_F21/EDP_BKLTCTL
GPP_F20/EDP_BKLTEN
GPP_F19/EDP_VDDEN
THRMTRIP#
PECI
PM_SYNC
PLTRST_CPU#
PM_DOWN
PCIE_PRX_DTX_N9
PCIE_PRX_DTX_P9
PCIE_PTX_DRX_N9
PCIE_PTX_DRX_P9
K37
J37
C35
B35
PCIE_PRX_DTX_N10
PCIE_PRX_DTX_P10
PCIE_PTX_DRX_N10
PCIE_PTX_DRX_P10
PCIE_PRX_DTX_N9
PCIE_PRX_DTX_P9
PCIE_PTX_DRX_N9
PCIE_PTX_DRX_P9
{45}
{45}
{45}
{45}
PCIE_PRX_DTX_N10
PCIE_PRX_DTX_P10
PCIE_PTX_DRX_N10
PCIE_PTX_DRX_P10
D
NGFF SSD
{45}
{45}
{45}
{45}
NGFF SSD
F44
E45
B40
C40
L41
M40
B41
C41
K43
K44
A42
B42
SATA_PRX_DTX_N0
SATA_PRX_DTX_P0
SATA_PTX_DRX_N0
SATA_PTX_DRX_P0
{47}
{47}
{47}
{47}
HDD
P41
R40
C42
D42
AK48
AH41
AJ43
AK47
AN47
AM46
AM43
AM47
AM48
SATA_LED#
RH15 1
C
2 10K_0402_5%
+3VS
SSD_DET#
SSD_DET# {45}
change to SATA PORT1 by Bing 0621
AU48
AV46
AV44
AD3
AF2
AF3
AG5
AE2
PCH_EDP_PWM {38}
PCH_EDP_ENBKL {38}
PCH_EDP_ENVDD {38}
THRMTRIP#_PCH
PCH_PECI
H_PM_SYNC_R
CPU_PLTRST#
H_PM_DOWN
RH34 1
RH35 1
RH13 1
1
@2
B
CH281
.1U_0402_10V6-K
CH280
.1U_0402_10V6-K
PCIE12_TXP/SATA1A_TXP
PCIE12_TXN/SATA1A_TXN
PCIE12_RXP/SATA_1A_RXP
PCIE12_RXN/SATA1A_RXN
PCIE20_TXP/SATA7_TXP
PCIE20_TXN/SATA7_TXN
PCIE20_RXP/SATA7_RXP
PCIE20_RXN/SATA7_RXN
PCIE19_TXP/SATA6_TXP
PCIE19_TXN/SATA6_TXN
PCIE19_RXP/SATA6_RXP
PCIE19_RXN/SATA6_RXN 3 OF 13
CANNONLAKE-H-PCH_FCBGA874
@
G36
F36
C34
D34
2 620_0402_5%
2 13_0402_5%
2 30_0402_1%
H_THRMTRIP# {6,25}
EC_PECI {6,49}
H_PM_SYNC {6}
CPU_PLTRST# {6}
H_PM_DOWN {6}
1
2
AR2
AT5
AU4
1
@2
@
RH836
10K_0201_5%
2
RH133
10K_0402_5%
D
B
A
A
Title
LC Future Center Secret Data
Security Classification
Issued Date
2015/02/26
Deciphered Date
2018/09/20
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
5
4
https://Dr-Bios.com
3
PCH (1/9) PCIe/SATA/GPPFG
Size
A3
Date:
2
Document Number
Rev
0.1
FG541/FG741
Tuesday, February 26, 2019
Sheet
1
14
of
69
5
4
3
2
1
Follow PDG add R/C 1010SF
close to PCH
LPC_AD0 CC1399 1
EMC_NS@
2 27P_0402_50V8J
EMC_NS@
LPC_AD2 CC1402 1
2 27P_0402_50V8J
EMC_NS@
LPC_AD3 CC1400 1
HM370 only have 4(#1-#4) USB3.1 GEN2 port
2 27P_0402_50V8J
LPC_AD1 CC1403 1
2 27P_0402_50V8J
EMC_NS@
+3VS
{48} USB30_TX_N2
{48} USB30_TX_P2
{48} USB30_RX_N2
{48} USB30_RX_P2
Type-C
USB30_TX_N2
USB30_TX_P2
USB30_RX_N2
USB30_RX_P2
F9
F7
D11
C11
C3
D4
B9
C9
C17
C16
G14
F14
C15
B15
J13
K13
{46} USB30_TX_P3
{46} USB30_TX_N3
{46} USB30_RX_P3
{46} USB30_RX_N3
LEFT USB3.0
C
Type-C
{48} USB30_TX_P4
{48} USB30_TX_N4
{48} USB30_RX_P4
{48} USB30_RX_N4
USB30_TX_P3
USB30_TX_N3
USB30_RX_P3
USB30_RX_N3
USB30_TX_P4
USB30_TX_N4
USB30_RX_P4
USB30_RX_N4
G12
F11
C10
B10
C14
B14
J15
K16
USB31_1_TXN
USB31_1_TXP
USB31_1_RXN
USB31_1_RXP
USB31_2_TXN
USB31_2_TXP
USB31_2_RXN
USB31_2_RXP
USB31_6_TXN
USB31_6_TXP
USB31_6_RXN
USB31_6_RXP
USB31_5_TXN
USB31_5_TXP
USB31_5_RXN
USB31_5_RXP
GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3
GPP_A5/LFRAME#/ESPI_CS0#
GPP_A6/SERIRQ/ESPI_CS1#
GPP_A7/PIRQA#/ESPI_ALERT0#
GPP_A0/RCIN#/ESPI_ALERT1#
GPP_A14/SUS_STAT#/ESPI_RESET#
LPC_AD0_R
LPC_AD1_R
LPC_AD2_R
LPC_AD3_R
BE38
AW35
BA36
BE39
BF38
LPC_FRAME#
SERIRQ
TPM_PIRQ
KBRST#
1
1
1
1
RH128
RH130
RH131
RH132
2
2
2
2
@
@
@
@
0_0201_5%
0_0201_5%
0_0201_5%
0_0201_5%
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
{49}
{49}
{49}
{49}
RH104
10K_0402_5%
RH113
10K_0402_5%
LPC_FRAME# {49}
SERIRQ {49}
TPM_PIRQ {37}
KBRST# {49}
For LPC_CLK
R：
0Ω
t o 22
Ω
GPP_A9/CLKOUT_LPC0/ESPI_CLK
GPP_A10/CLKOUT_LPC1
GPP_K19/SMI#
GPP_K18/NMI#
USB31_3_TXP
USB31_3_TXN
USB31_3_RXP
USB31_3_RXN
USB31_4_TXP
USB31_4_TXN
USB31_4_RXP
USB31_4_RXN
BB39
AW37
AV37
BA38
2
USB30_TX_N1
USB30_TX_P1
USB30_RX_N1
USB30_RX_P1
2
{46} USB30_TX_N1
{46} USB30_TX_P1
{46} USB30_RX_N1
{46} USB30_RX_P1
LEFT USB3.0
UH1F
1
D
1
D
6 OF 13
GPP_E6/SATA_DEVSLP2
GPP_E5/SATA_DEVSLP1
GPP_E4/SATA_DEVSLP0
GPP_F9/SATA_DEVSLP7
GPP_F8/SATA_DEVSLP6
GPP_F7/SATA_DEVSLP5
GPP_F6/SATA_DEVSLP4
GPP_F5/SATA_DEVSLP3
BB36
BB34
CLK_PCI_EC_R
T48
T47
PCH_SMI#
RH84 1
2 0_0402_5%
RH129 @1
AH40
AH35
AL48
AP47
AN37
AN46
AR47
AP48
RH821 @1
2 10K_0402_5%
DEVSLP0 {45}
2 22_0402_5%
CLK_PCI_EC
CLK_PCI_EC
{49}
EC_SMI# {49}
+3VS
EMC_NS@
CE52
10P_0402_50V8J
NGFF SSD
change DEVSLP to SATA Port1 by Bing 0621
H：
Sleep
Mode
L：
Active
Mode
1
2
reserved for EMC need 0803SF
C
CANNONLAKE-H-PCH_FCBGA874
@
+3VS
B
DDPB_CLK
{39} HDMI_HPD
@
HDMI_HPD
TH40
RH26
1
1
PAD @
{45} CNVI_EN#
{38} PCH_EDP_HPD
2 0_0402_5%
GPP_I0
CNVI_EN#
PCH_EDP_HPD
UH1E
AT6
AN10
AP9
AL15
AN6
GPP_I0/DDPB_HPD0/DISP_MISC0
GPP_I1/DDPC_HPD1/DISP_MISC1
GPP_I2/DPPD_HPD2/DISP_MISC2
GPP_I3/DPPE_HPD3/DISP_MISC3
GPP_I5/DDPB_CTRLCLK
GPP_I6/DDPB_CTRLDATA
GPP_I7/DDPC_CTRLCLK
GPP_I8/DDPC_CTRLDATA
GPP_I9/DDPD_CTRLCLK
GPP_I10/DDPD_CTRLDATA
GPP_F23/DDPF_CTRLDATA
GPP_F22/DDPF_CTRLCLK
GPP_F14/EXT_PWR_GATE#/PS_ON#
GPP_I4/EDP_HPD/DISP_MISC4
GPP_K23/IMGCLKOUT1
GPP_K22/IMGCLKOUT0
GPP_K21
GPP_K20
GPP_H23/TIME_SYNC0
5 OF 13
CANNONLAKE-H-PCH_FCBGA874
@
AL13
AR8
AN13
AL10
AL9
AR3
AN40
AT49
DDPB_CLK
DDPB_DATA
DDPC_CLK
DDPC_DATA
DDPD_CLK
DDPD_DATA
1
1
DDPB_DATA RH823
DDPB_CLK
DDPB_DATA
PAD @
TH35
TH36
RH853
@
2
B
1 2.2K_0402_5%
2
1 2.2K_0402_5%
@
PAD @
+3VS
DDPC_DATA RH10 @
2
1 2.2K_0402_5%
DDPD_DATA RH16 @
2
1 2.2K_0402_5%
AP41
M45
L48
T45
T46
AJ47
*
DDPB_CTRLDATA
The signal has a weak internal pull-down.
H
Port B is detected.
L
Port B is not detected.
*
*
A
Issued Date
2015/02/26
Deciphered Date
2018/09/20
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
5
4
https://Dr-Bios.com
3
DDPD_CTRLDATA
The signal has a weak internal pull-down.
H
Port D is detected.
L
Port D is not detected. (Default)
A
Title
LC Future Center Secret Data
Security Classification
DDPC_CTRLDATA
The signal has a weak internal pull-down.
H
Port C is detected.
L
Port C is not detected. (Default)
PCH (2/9) USB3/GPPAEFGHI
Size
A3
Date:
2
Document Number
Rev
0.1
FG541/FG741
Tuesday, February 26, 2019
Sheet
1
15
of
69
5
4
3
2
1
+3VALW_PCH
*HDA_SDO
2
This signal has a weak internal pull-down.
0 = Enable security measures defined in the Flash Descriptor.
1 = Disable Flash Descriptor Security (override). This
strap should only be asserted high using external pullup in manufacturing/debug environments ONLY.
RH25
1K_0402_5%
@
1
+1.2V
1@
RH805 1
{35} HDA_BITCLK_AUDIO
{35} HDA_SDIN0
{35} HDA_SDOUT_AUDIO
{35} HDA_SYNC_AUDIO
D
2 33_0402_5%
2 33_0402_5%
PLACE NEAR PCH
1 30_0402_1%
RH754 2
{8} PROC_AUDIO_SDO_CPU
{8} PROC_AUDIO_SDI_CPU
{8} PROC_AUDIO_CLK_CPU
RH755 2
BD11
BE11
BF12
BG13
HDA_RST#
1
@ PAD TH39
UH1D
HDA_BIT_CLK
HDA_SDIN0
HDA_SDOUT
HDA_SYNC
2 33_0402_5%
RH806 1
RH804 1
1 30_0402_1%
PROC_AUDIO_CLK_PCH
AV18
AW18
BA17
BE16
BF15
BD16
AV16
AW15
PCH_RTCRST#
PCH_SRTCRST#
1@
1
2 0_0402_5%
2 0_0402_5%
@
@
RC1710 2
PCH_DPWROK_R
1
RC81
1 0_0402_5%
@
DPWROK_EC
PCH_PWROK_R
PCH_RSMRST#_R
SML0CLK
SML0DATA
{49}
SMB1_ALERT#
SML1CLK
SML1DATA
+3VALW_PCH
RH56 1
@
2 10K_0402_5%
DSW_PWROK
GPP_C2/SMBALERT#
GPP_C0/SMBCLK
GPP_C1/SMBDATA
GPP_C5/SML0ALERT#
GPP_C3/SML0CLK
GPP_C4/SML0DATA
GPP_B23/SML1ALERT#/PCHHOT#
GPP_C6/SML1CLK
GPP_C7/SML1DATA
4 OF 13
PCH_LAN_WAKE#
PCH_AC_PRESENT_R
PM_SLP_SUS#_R
RC89
PM_PWRBTN#_R
PCH_DRAMRST#
1@
2 0_0402_5%
@
RH69 1
PAD @
PAD @
PAD @
@
RH70 1
RH71 1
@
TH33 PAD @
2 0_0402_5%
RH193
TH30
TH31
TH32
2 0_0402_5%
2 0_0402_5%
PM_SLP_S3# {49}
PM_SLP_S4# {49}
SUSCLK {45}
SUSACK#_R
SUSWARN#_R
@
1
2 0_0402_5%
@
RH75 1
@
2 0_0402_5%
PM_SLP_SUS#
RH76
1
SYS_RESET#
1
RH745
2 0_0201_5%
@
AC_PRESENT {49}
PM_SLP_SUS# {49}
PBTN_OUT# {41,49}
SYS_RESET# {41}
PCH_BEEP {35}
H_CPUPWRGD {6}
2 0_0402_5%
ITP_PMODE {41}
JTAGX {41}
PCH_TMS {41}
PCH_TDO {41}
PCH_TDI {41}
PCH_TCK {41}
@
@
2
2 20K_0402_5%
CH1
1U_0402_6.3V6K
RH4 1
PCH_RTCRST#
1
CH5
1U_0402_6.3V6K
2
@
2
0_0402_5%
@
1
@
2 0_0201_5%
QH3B
@
QH3A
D
EC_RTC_RST#
{49}
RC1624
2
S
ALW_PWRGD
G
{60}
L2N7002KDW1T1G_SOT363-6
S
L2N7002KDW1T1G_SOT363-6
2
〃
SMB_CLK_S3
2
G
1
EC_SMB_CK2
EC_SMB_CK2 {28,44,49}
QH2A
L2N7002KDW1T1G_SOT363-6
L2N7002KDW1T1G_SOT363-6
3
SML1DATA
SMB_DATA_S3
4
SMB_DATA_S3 {13}
D
QH1B
GPU, EC, Thermal Sensor
B
6
SML1CLK
SMB_CLK_S3 {13}
G
5
G
QH1A
+3VS
4
3
2.2K_0404_4P2R_5%
2.2K_0404_4P2R_5%
S
3
1
2
+3VS
2
D
PCH_SMBDATA
1
4
3
D
GPP_B23 /SML1ALERT# /PCHHOT#
0 = Disable Intel DCI-OOB (Default)
1 = Enable Intel DCI-OOB
Note:When used as PCHHOT# and strap low, a 150K
pull-up is needed to ensure it does not override the
internal pull-down strap sampling.
6
1
2
5
2
2.2K_0404_4P2R_5%
PCH_SMBCLK
+3VALW_PCH
RPH7
2N7002KDWH
Vth= min 1V, max 2.5V
ESD 2KV
G
4
3
2
S
¨
〃
1
2
2
RPH8
DIMM1, DIMM2, WLAN, TP
+3VS
RPH4
+3VALW_PCH
GPP_C5 /SML0ALERT#
This signal has a weak internal pull-down.
0 = LPC is selected (for EC). (Default)
1 = eSPI is selected (for EC).
2
1
2.2P_0402_50V8-C
2
1
CH286 EMC_NS@
CH293
1000P_0201_50V7-K
EMC@
close to PCH
1
2.2P_0402_50V8-C
2
1
CH284 EMC_NS@
1
CH294
1000P_0201_50V7-K
EMC@
1
2.2P_0402_50V8-C
2
1
HDA_RST#
HDA_SDOUT
HDA_SDIN0
PCH_DPWROK_R
CH283 EMC_NS@
1
SYS_PWROK_R
.1U_0402_10V6-K
¨
PCH_PWROK
CH85 EMC@
Strap
GPP_C2 /SMBALERT#
This signal has a weak internal pull-down.
0 = Disable Intel ME Crypto Transport Layer Security
(TLS) cipher suite (no confidentiality). (Default)
1 = Enable Intel ME Crypto Transport Layer Security
(TLS) cipher suite (with confidentiality). Must be
pulled up to support Intel AMT with TLS.
2 2.2K_0402_5%
2 2.2K_0402_5%
2 2.2K_0402_5%
AS EMC request
PCH_RTCRST#
.1U_0402_10V6-K
*
2 2.2K_0402_5% SMB_ALERT# RH768 @1
2 2.2K_0402_5% SMB0_ALERT# RH769 @1
2 2.2K_0402_5% SMB1_ALERT# RH770 @1
PCH_SRTCRST#
CH84 EMC@
2.2K_0404_4P2R_5%
PCH_BEEP
EC_SMB_DA2
4
S
2 1K_0402_5%
.1U_0402_10V6-K
SML0DATA
SML0CLK
@
SPKR / GPP_B14
The signal has a weak internal pull-down.
0 = Disable
Top Swap
mode . (Default
)
1 = Enable
Top Swap
mode. This inverts an address
on access to SPI and firmware hub, so the processor
believes it fetches the alternate boot block instead of
the original boot-block. PCH will invert A16 (default)
for cycles going to the upper two 64-KB blocks in the
FWH or the appropriate address lines (A16, A17, or
A18) as selected in Top Swap Block size soft strap
(handled through FITC).
CH83 EMC@
@
1
@
JCMOS1
SHORT PADS
EMC request add 0322SF
RH28 1
RPH3
RH765 1
RH766 @1
RH767 @1
RC272
C
SYS_PWROK_R
PCH_PWROK
PCH_RSMRST#_R
PCH_DPWROK_R
+3VALW_PCH
4
3
D
5
2 20K_0402_5%
+3VALW
@
PCH_SRTCRST#
G
2@
+3VALW_PCH
1
2
@
JME1
SHORT PADS
+3VL
2 0_0201_5%
EC_SMB_DA2 {28,44,49}
D
2 100K_0402_5%
1 10K_0402_5%
2 10K_0402_5%
2 100K_0402_5%
1
CH4
1U_0402_6.3V6K
RH3 1
1
CNVI_RF_RESET#
RH829 1 CNVI@ 2 75K_0402_5%
CNVi@ 2
CNVI_MODEM_CLKREQ
RH830 1
71.5K_0402_1%
RH18 1
RH54 2
RH59 1
RH61 1
@
+RTCVCC
0_0402_5%
6
2
2 0_0201_5%
@
1
1
3 2
+RTCVCC
RH2
@
1
RC273
100K_0402_5%
4
SYS_RESET#
PM_CLKRUN#
S
2 10K_0402_5%
2 8.2K_0402_5%
1
RC279
RC276
0_0402_5%
1
VCCRTC
RH67 1
RH65 1
RC278
@
W=20mils
2
+3VS
RSMRST# sequence control circuit
SVT un-stuff0322SF
2
CMOS
1
BATLOW#
WAKE#
PCH_LAN_WAKE#
1EC_RSMRST#
PM_PWRBTN#_R
PCH_AC_PRESENT_R
1
2 10K_0402_5%
2 10K_0402_5%
2 10K_0402_5%
2 1K_0402_5%
2 10K_0201_5%
2
RH17 1
RH58 1
RH60 1
RH80 1
RH747 1
W=20mils
B
SYS_PWROK {41,49}
CANNONLAKE-H-PCH_FCBGA874
+3VALW
C
{12,13}
PCIE_WAKE# {42,45,49}
AL3
AH4
AJ4
AH3
AH2
AJ3
ITP_PMODE
PCH_JTAGX
PCH_JTAG_TMS
PCH_JTAG_TDO
PCH_JTAG_TDI
PCH_JTAG_TCK
SUSWARN#_R
SUSCLK
BATLOW#
SUSACK#_R
SUSWARN#_R
BG44
BG42
BD39
BE46
AU2
AW29
AE3
GPD2/LAN_WAKE#
GPD1/ACPRESENT
SLP_SUS#
GPD3/PWRBTN#
SYS_RESET#
GPP_B14/SPKR
CPUPWRGD
WAKE#
SLP_A#
1
SLP_LAN#
1
SLP_S0
1
PM_SLP_S3#_R
PM_SLP_S4#_R
PM_SLP_S5#_R 1
BE45
BF44
BE35
BC37
GPD8/SUSCLK
GPD0/BATLOW#
GPP_A15/SUSACK#
GPP_A13/SUSWARN#/SUSPWRDNACK
SYS_PWROK_R
BB47
BE40
BF40
BC28
BF42
BE42
BC42
WAKE#
GPD6/SLP_A#
SLP_LAN#
GPP_B12/SLP_S0#
GPD4/SLP_S3#
GPD5/SLP_S4#
GPD10/SLP_S5#
PCH_PWROK
RSMRST#
AW41
BE25
BE26
BF26
BF24
BF25
BE24
BD33
BF27
BE27
D
PM_SLP_WLAN# {45}
BB46
BE32
BF33
BE29
R47
AP29
AU3
DRAM_RESET#
GPP_B2/VRALERT#
GPP_B1/GSPI1_CS1#/TIME_SYNC1
GPP_B0/GSPI0_CS1#
GPP_K17/ADR_COMPLETE
GPP_B11/I2S_MCLK
SYS_PWROK
RTCRST#
SRTCRST#
AY42
BA47
PCH_DPWROK_R
SMB_ALERT#
PCH_SMBCLK
PCH_SMBDATA
SMB0_ALERT#
EC_RSMRST#
2 0_0402_5%
BE47
BD46
BD42
GPD9/SLP_WLAN#
GPP_D8/I2S2_SCLK
GPP_D7/I2S2_RXD
GPP_D6/I2S2_TXD/MODEM_CLKREQ
GPP_D5/I2S2_SFRM/CNV_RF_RESET#
GPP_D20/DMIC_DATA0/SNDW4_DATA
GPP_D19/DMIC_CLK0/SNDW4_CLK
GPP_D18/DMIC_DATA1/SNDW3_DATA
GPP_D17/DMIC_CLK1/SNDW3_CLK
RH756
470_0402_5%
PM_CLKRUN#
BF41
GPD11/LANPHYPC
HDACPU_SDO
HDACPU_SDI
HDACPU_SCLK
AN3
AM3
BF36
AV32
GPP_A12/BM_BUSY#/ISH_GP6/SX_EXIT_HOLDOFF#
GPP_A8/CLKRUN#
HDA_RST#/I2S1_SCLK
HDA_SDI1/I2S1_RXD
I2S1_TXD/SNDW2_DATA
I2S1_SFRM/SNDW2_CLK
PROC_AUDIO_SDO_PCH AM2
PCH_RTCRST#
RH12
RH14
HDA_BCLK/I2S0_SCLK
HDA_SDI0/I2S0_RXD
HDA_SDO/I2S0_TXD
HDA_SYNC/I2S0_SFRM
BE10
BF10
BE12
BD12
CNVI_MODEM_CLKREQ
CNVI_RF_RESET#
{41,49} PCH_PWROK
{41,49} EC_RSMRST#
1
2 0_0402_5%
2
RH9
{49} ME_FLASH
QH2B
L2N7002KDW1T1G_SOT363-6
L2N7002KDW1T1G_SOT363-6
For CNVI function update:change GPIO Group D to 1.8V and delete level shift1205SF
CNVI_MODEM_CLKREQ
CNVI_RF_RESET#
CNVI_MODEM_CLKREQ
{45}
CNVI_RF_RESET#
{45}
A
A
Security Classification
Title
LC Future Center Secret Data
PCH (3/9) HDA,RTC,SMBUS,PM
https://Dr-Bios.com
Issued Date
2015/02/26
Deciphered Date
2018/09/20
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF
Size Document
Custom
Date:
5
4
3
2
Number
Re v
0.1
FG541/FG741
LC FUTURE CENTER.
Tuesday, February 26, 2019
1
Sheet
16
of
69
5
4
3
2
1
UH1G
BE33
D7
C6
{6} PCH_CPU_NSSC_CLK
{6} PCH_CPU_NSSC_CLK#
D
B8
C8
{6} PCH_CPU_BCLK
{6} PCH_CPU_BCLK#
XTAL24_OUT
XTAL24_IN
RH6
1
PCH_CLK_BIASREF
2 60.4_0402_1%
@
2 10K_0402_5%
WLAN_CLKREQ#
RH89 1
2 10K_0402_5%
LAN_CLKREQ#
RH93 1
2 10K_0402_5%
SSD_CLKREQ#
RH94 1
2 10K_0402_5%
GPU_CLKREQ#
BA49
BA48
BF31
BE31
WLAN_CLKREQ# AR32
LAN_CLKREQ#
BB30
BA30
AN29
AE47
SSD_CLKREQ#
AC48
AE41
AF48
AC41
GPU_CLKREQ#
AC39
AE39
AB48
AC44
AC43
{45} WLAN_CLKREQ#
{42} LAN_CLKREQ#
RH90 1
T3
PCH_RTCX1
PCH_RTCX2
PDG_0.71 60Ω ± 1%
CRB 60.4Ω ± 1
%
need to confirm
+3VS
U9
U10
{45} SSD_CLKREQ#
{25} GPU_CLKREQ#
V2
V3
C
T2
T1
AA1
Y2
AC7
AC6
Y3
Y4
GPP_A16/CLKOUT_48
CLKOUT_ITPXDP
CLKOUT_ITPXDP_P
CLKOUT_CPUNSSC_P
CLKOUT_CPUNSSC
CLKOUT_CPUPCIBCLK
CLKOUT_CPUPCIBCLK_P
CLKOUT_CPUBCLK_P
CLKOUT_CPUBCLK
CLKOUT_PCIE_N0
CLKOUT_PCIE_P0
XTAL_OUT
XTAL_IN
CLKOUT_PCIE_N1
CLKOUT_PCIE_P1
XCLK_BIASREF
CLKOUT_PCIE_N2
RTCX1
CLKOUT_PCIE_P2
RTCX2
CLKOUT_PCIE_N3
GPP_B5/SRCCLKREQ0#
CLKOUT_PCIE_P3
GPP_B6/SRCCLKREQ1#
GPP_B7/SRCCLKREQ2#
CLKOUT_PCIE_N4
GPP_B8/SRCCLKREQ3#
CLKOUT_PCIE_P4
GPP_B9/SRCCLKREQ4#
GPP_B10/SRCCLKREQ5# CLKOUT_PCIE_N5
GPP_H0/SRCCLKREQ6#
CLKOUT_PCIE_P5
GPP_H1/SRCCLKREQ7#
GPP_H2/SRCCLKREQ8#
CLKOUT_PCIE_N6
GPP_H3/SRCCLKREQ9#
CLKOUT_PCIE_P6
GPP_H4/SRCCLKREQ10#
GPP_H5/SRCCLKREQ11# CLKOUT_PCIE_N7
GPP_H6/SRCCLKREQ12# CLKOUT_PCIE_P7
GPP_H7/SRCCLKREQ13#
GPP_H8/SRCCLKREQ14# CLKOUT_PCIE_N8
GPP_H9/SRCCLKREQ15# CLKOUT_PCIE_P8
CLKOUT_PCIE_N15
CLKOUT_PCIE_P15
AE14 CLK_PCIE_WLAN#
AE15 CLK_PCIE_WLAN
CLK_PCIE_WLAN#
CLK_PCIE_WLAN
AE6 CLK_PCIE_LAN#
AE7 CLK_PCIE_LAN
CLK_PCIE_LAN#
CLK_PCIE_LAN
{45}
{45}
{42}
{42}
WLAN
LAN
AC2
AC3
AB2
AB3
W4
W3
W7
W6
CLK_PCIE_SSD#
CLK_PCIE_SSD
CLK_PCIE_SSD#
CLK_PCIE_SSD
{45}
{45}
M.2 SSD
AC14
AC15
U2
U3
CLKOUT_PCIE_N11
CLKOUT_PCIE_P11
CLKOUT_PCIE_N12
CLKOUT_PCIE_P12 13
7 OF
CANNONLAKE-H-PCH_FCBGA874
@
D
AH9
AH10
CLKOUT_PCIE_N10
CLKOUT_PCIE_P10
CLKOUT_PCIE_N13
CLKOUT_PCIE_P13
PCH_CPU_PCIBCLK# {6}
PCH_CPU_PCIBCLK {6}
AJ6
AJ7
CLKOUT_PCIE_N9
CLKOUT_PCIE_P9
CLKOUT_PCIE_N14
CLKOUT_PCIE_P14
B6
A6
C
AC9
AC11
AE9 CLK_PCIE_GPU#
AE11 CLK_PCIE_GPU
CLK_PCIE_GPU# {25}
CLK_PCIE_GPU {25}
R6
CLKIN_XTAL
RH824 1
GPU
CLKIN_XTAL_LCP {45}
2 10K_0402_5%
change from 0ohm to 10K on 1002SF
change to 200K± 1% on 0703
RH92
2
1 200K_0402_1%
YH2
4
B
XTAL24_OUT
1
RH32
@
2
0_0402_5%
XTAL24_OUT_LR
1
1
2
NC2
1
3
NC1
XTAL24_IN_LR
3
1
RH30
@
2
XTAL24_IN
0_0402_5%
2
24MHZ_12PF_7V24000023
CH9
15P_0402_50V8J
B
1
2
CH10
15P_0402_50V8J
PCH_RTCX1
RH1
1
PCH_RTCX2
2 10M_0402_5%
YH1
1
2
32.768KHZ_9PF_X1A0001410002
1
Default De-Pop, if want to Pop in BOM, need change PN to SM070004400
@
EXC24CH500U_4P
XTAL24_IN
4
XTAL24_OUT
1
4
3
1
L33
2
3
2
XTAL24_IN_LR
2
1
CH2
10P_0402_50V8J
CH3
10P_0402_50V8J
2
XTAL24_OUT_LR
A
A
Title
LC Future Center Secret Data
Security Classification
Issued Date
2015/02/26
Deciphered Date
2018/09/20
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
5
4
https://Dr-Bios.com
3
PCH (3/9) CLOCK,GPPBH
Size
A3
Date:
2
Document Number
Rev
0.1
FG541/FG741
Tuesday, February 26, 2019
Sheet
1
17
of
69
5
@
RH858 1
@
RH859 1
@
RH860 1
{49} EC_SPI_SI
{49} EC_SPI_SO
{49} EC_SPI_CLK
@
RH109 1
RH111 1 @
@
RH105 1
SPI_SI_F
SPI_SO_F
To flash ROM
SPI_CLK_PCH_F
D
UH1A
2 0_0402_5%
2 0_0402_5%
BE36
R15
R13
2 0_0402_5%
@
RH854 1
@
RH855 1
SPI_SI_R
SPI_SO_R
RH862 1
SPI_CS0#_F
@
RH861 1
@
1
2 0_0402_5%
2 0_0402_5%
2 0_0402_5%
RH826 1
{49} EC_SPI_CS0#
2
2 0_0402_5%
SPI_CLK_PCH_R
RH856 1
@
2 0_0402_5%
2 0_0402_5%
@
2 0_0402_5%
2 0_0402_5%
1 PAD
TH37
@
SPI_SI
SPI_SO
SPI_CS0#
SPI_CLK_PCH
AL37
AN35
AU41
BA45
AY47
AW47
AW48
2 0_0402_5%
SPI_WP#
{41} SPI_WP#
SPI_WP#_F
RH250 1
SPI_HOLD#_F
RH252 1
AY48
BA46
AT40
SPI_HOLD#
SPI_CS2#
@
2 0_0402_5%
@
BE19
BF19
BF18
BE18
BC17
BD17
2 0_0402_5%
GPP_A11/PME#/SD_VDD2_PWR_EN#
RSVD9
RSVD10
AV29
GPP_B13/PLTRST#
GPP_K16/GSXCLK
GPP_K12/GSXDOUT
GPP_K13/GSXSLOAD
GPP_K14/GSXDIN
GPP_K15/GSXSRESET#
VSS_247
TP_1
SPI0_MOSI
SPI0_MISO
SPI0_CS0#
SPI0_CLK
SPI0_CS1#
GPP_D1/SPI1_CLK/SBK1_BK1
GPP_D0/SPI1_CS#/SBK0_BK0
GPP_D3/SPI1_MOSI/SBK3_BK3
GPP_D2/SPI1_MISO/SBK2_BK2
GPP_D22/SPI1_IO3
GPP_D21/SPI1_IO2
PLT_RST# {28,37,41,42,45,49}
Y47
Y46
Y48
W46
AA45
RH43
100K_0402_5%
1
CH295
220P_0201_25V7-K
EMC_NS@
2
AL47
AM45
BF32
BC33
GPP_E3/CPU_GP0
GPP_E7/CPU_GP1
GPP_B3/CPU_GP2
GPP_B4/CPU_GP3
SPI0_IO2
SPI0_IO3
SPI0_CS2#
PLT_RST#
1
To EC
3
2
D
4
AE44
AJ46
AE43
AC47
AD48
AF47
AB47
AD47
AE48
GPP_H18/SML4ALERT#
GPP_H17/SML4DATA
GPP_H16/SML4CLK
GPP_H15/SML3ALERT#
GPP_H14/SML3DATA
GPP_H13/SML3CLK
GPP_H12/SML2ALERT#
GPP_H11/SML2DATA
GPP_H10/SML2CLK
INTRUDER#
BB44
+3VALW_PCH
RH825
1
RH753
1
RH743
2 100K_0402_5%
2
@
Follow
PDG:100K
2 4.7K_0402_5%
Follow
CRB:4.7K
Strap PIN
1 1M_0402_5%
+RTCVCC
1 OF 13
CANNONLAKE-H-PCH_FCBGA874
@
change TPM interface to SPI,need double check_SF20180530
SPI_CLK_PCH_R
RC4710 2 TPM@
1 33_0402_5%
SPI_CS2#
RC4712 1 TPM@
2
SPI_SO_R
RC4714 2 TPM@
1 33_0402_5%
RC4716 2 TPM@
1 33_0402_5%
+3VALW_PCH
TPM_SPI_CLK {37}
0_0402_5%
change to 100K pull-up on 0703
TPM_SPI_CS# {37}
TPM_SPI_MISO {37}
1
2 100K_0402_5%
SPI_WP#
RH125
1
2 100K_0402_5%
SPI_HOLD#
1
2 1K_0402_5%
SPI_SO
RH773
SPI_SI_R
RH123
RH772
C
1
2 100K_0402_5%
SPI_SI
TPM_SPI_MOSI {37}
@
RH833
1
RH771
1
@
2 1K_0402_5%
@
2 1K_0402_5%
SPI_SI_XDP {41}
change to 100K pull-up on 0704
SPI0_MOSI,SPI0_MISO,SPI0_IO[2:3] all have internal pull up
SPI0_MOSI
External pull-up is required. Recommend 100K if pulled
up to 3.3V or 75K if pulled up to 1.8V.
This strap should sample HIGH. There should NOT be
any on-board device driving it to opposite direction
during strap sampling.
GPP_H15 /SML3ALERT# (Strap reserved)
External pull-up is required. Recommend 100K if pulled
up to 3.3V or 75K if pulled up to 1.8V.
This strap should sample HIGH. There should NOT be
any on-board device driving it to opposite direction
during strap sampling.
Power Plane: Primary Well
C
GPP_H12 /SML2ALERT#
This signal has a weak internal pull-down.
0 = Master Attached Flash Sharing (MAFS) enabled
(Default)
1 = Slave Attached Flash Sharing (SAFS) enabled.
Warning: This strap must be configured to ‘ 0’
(SAFS is disabled) if the eSPI or LPC
strap is configured to ‘ 0’ (eSP I is
disabled)
Notes:
1. The internal pull-down is disabled after RSMRST#
de-asserts.
2. This signal is in the primary well.
SPI0_IO2
External pull-up is required. Recommend 100K if pulled
up to 3.3V or 75K if pulled up to 1.8V.
This strap should sample HIGH. There should NOT be
any on-board device driving it to opposite direction
during strap sampling.
+3V_SPI
NPI@ 2
+3VALW_PCH
1
SPI0_IO3
External pull-up is required. Recommend 100K if pulled
up to 3.3V or 75K if pulled up to 1.8V.
This strap should sample HIGH. There should NOT be
any on-board device driving it to opposite direction
during strap sampling.
128Mb Flash ROM，
change t o SA00008 A300 SF0911
+3V_SPI
D2201 RB520CM-30T2R_VMN2M2
@
RC171 1
2 0_0402_5%
1
+3VS
RC172 1
@
2 0_0402_5%
B
SPI_CS0#_F
SPI_SO_F
+3V_SPI
2
3
4
/CS
DO(IO1)
VCC
/HOLD(IO3)
/WP(IO2)
GND
CLK
DI(IO0)
CH13
.1U_0402_10V6-K
8
2
7
6
B
SPI_HOLD#_F
SPI_CLK_PCH_F
5
SPI_SI_F
2
*
SPI_WP#_F
1. If support DS3, connect to +3VS and don't support EC mirror code;
2. If don't support DS3, connect to +3VALW_PCH and support EC mirror code.
UC3
1
W25Q128JVSIQ_SO8
RH119
1
10_0402_5%@
1
EMC_NS@
1
EMC_NS@
2
CH268
5P_50V_B_NPO_0402
CH11
10P_0402_50V8J
2
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
Deciphered Date
2015/02/26
2018/09/20
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
5
4
https://Dr-Bios.com
3
PCH (5/9) SPI,SMBUS,GPPBEGH
Size
A2
Date:
2
Document Number
Rev
0.1
FG541/FG741
Tuesday, February 26, 2019
1
Sheet
18
of
69
3
{5}
{5}
{5}
{5}
{5}
{5}
{5}
{5}
{5}
{5}
{5}
{5}
{5}
{5}
{5}
{5}
D
UH1B
DMI_CTX_PRX_N0
DMI_CTX_PRX_P0
DMI_CRX_PTX_N0
DMI_CRX_PTX_P0
DMI_CTX_PRX_N1
DMI_CTX_PRX_P1
DMI_CRX_PTX_N1
DMI_CRX_PTX_P1
DMI_CTX_PRX_N2
DMI_CTX_PRX_P2
DMI_CRX_PTX_N2
DMI_CRX_PTX_P2
DMI_CTX_PRX_N3
DMI_CTX_PRX_P3
DMI_CRX_PTX_N3
DMI_CRX_PTX_P3
DMI_CTX_PRX_N0
DMI_CTX_PRX_P0
DMI_CRX_PTX_N0
DMI_CRX_PTX_P0
DMI_CTX_PRX_N1
DMI_CTX_PRX_P1
DMI_CRX_PTX_N1
DMI_CRX_PTX_P1
DMI_CTX_PRX_N2
DMI_CTX_PRX_P2
DMI_CRX_PTX_N2
DMI_CRX_PTX_P2
DMI_CTX_PRX_N3
DMI_CTX_PRX_P3
DMI_CRX_PTX_N3
DMI_CRX_PTX_P3
2
K34
J35
C33
B33
G33
F34
C32
B32
K32
J32
C31
B31
G30
F30
C29
B29
A25
B25
P24
R24
C26
B26
F26
G26
B27
C27
L26
M26
D29
E28
K29
M29
G17
F16
A17
B17
R21
P21
B18
C18
K18
J18
B19
C19
N18
R18
D20
C20
F20
G20
B21
A22
K21
J21
D21
C21
L24
J24
C23
B23
F24
G24
B24
C24
C
DMI0_RXN
DMI0_RXP
DMI0_TXN
DMI0_TXP
DMI1_RXN
DMI1_RXP
DMI1_TXN
DMI1_TXP
DMI2_RXN
DMI2_RXP
DMI2_TXN
DMI2_TXP
DMI3_RXN
DMI3_RXP
DMI3_TXN
DMI3_TXP
DMI7_TXP
DMI7_TXN
DMI7_RXP
DMI7_RXN
DMI6_TXP
DMI6_TXN
DMI6_RXP
DMI6_RXN
DMI5_TXP
DMI5_TXN
DMI5_RXP
DMI5_RXN
DMI4_TXP
DMI4_TXN
DMI4_RXP
DMI4_RXN
J3
J2
N13
N15
K4
K3
M10
L9
M1
L2
K7
K6
L4
L3
G4
G5
M6
N8
H3
H2
R10
P9
G1
G2
N3
N2
E5
F6
GPP_E9/USB2_OC0#
GPP_E10/USB2_OC1#
GPP_E11/USB2_OC2#
GPP_E12/USB2_OC3#
PCIE1_RXN/USB31_7_RXN
GPP_F15/USB2_OC4#
PCIE1_RXP/USB31_7_RXPGPP_F16/USB2_OC5#
PCIE1_TXN/USB31_7_TXNGPP_F17/USB2_OC6#
PCIE1_TXP/USB31_7_TXP GPP_F18/USB2_OC7#
PCIE2_RXN/USB31_8_RXN
PCIE2_RXP/USB31_8_RXP
USB2_COMP
PCIE2_TXN/USB31_8_TXN USB2_VBUSSENSE
PCIE2_TXP/USB31_8_TXP
RSVD11
PCIE3_RXN/USB31_9_RXN
USB2_ID
PCIE3_RXP/USB31_9_RXP
PCIE3_TXN/USB31_9_TXN
GPD7
PCIE3_TXP/USB31_9_TXP
PCIE4_RXN/USB31_10_RXN
PCIE24_TXP
PCIE4_RXP/USB31_10_RXP
PCIE24_TXN
PCIE4_TXN/USB31_10_TXN
PCIE24_RXP
PCIE4_TXP/USB31_10_TXP
PCIE24_RXN
PCIE5_RXN
PCIE23_TXP
PCIE5_RXP
PCIE23_TXN
PCIE5_TXN
PCIE23_RXP
PCIE5_TXP
PCIE23_RXN
PCIE6_RXN
PCIE22_TXP
PCIE6_RXP
PCIE22_TXN
PCIE6_TXN
PCIE22_RXP
PCIE6_TXP
PCIE22_RXN
PCIE7_RXN
PCIE21_TXP
PCIE7_RXP
PCIE21_TXN
PCIE7_TXN
PCIE21_RXP
PCIE7_TXP
PCIE21_RXN
PCIE8_RXN
PCIE8_RXP
PCIE8_TXN
PCIE8_TXP
2 OF 13
CANNONLAKE-H-PCH_FCBGA874
@
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
AH36
AL40
AJ44
AL41
AV47
AR35
AR37
AV43
USB2N_1
USB2P_1
USB2N_2
USB2P_2
USB2N_3
USB2P_3
USB2N_4
USB2P_4
USB2N_5
USB2P_5
USB2N_6
USB2P_6
USB2N_7
USB2P_7
USB2N_8
USB2P_8
USB2N_9
USB2P_9
USB2N_10
USB2P_10
USB2N_11
USB2P_11
USB2N_12
USB2P_12
USB2N_13
USB2P_13
USB2N_14
USB2P_14
USB_OC0#
USB_OC1#
USB_OC2# RC1728 1
USB_OC3#
USB_OC4#
USB_OC5#
USB_OC6#
USB_OC7#
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N8
USB20_P8
1
LEFT USB3.0
Type-C
LEFT USB3.0
Finger Print delete 0927SF
Card reader delete 20180529SF
Touch panel delete 20180704SF
{46}
{46}
{48}
{48}
{46}
{46}
D
+3VALW_PCH
Camera
USB20_N8 {38}
USB20_P8 {38}
RPH5
USB_OC4#
USB_OC5#
USB_OC6#
USB_OC7#
USB20_N14
USB20_P14
USB20_N14 {45}
USB20_P14 {45}
@
4
3
2
1
BT
5
6
7
8
10K_1206_8P4R_5%
RPH6
USB_OC1# {46}
TYPE_C_OCP# {48}
2 0_0402_5%
USB_OC0#
USB_OC3#
USB_OC2#
USB_OC1#
9/05 Reserve TYPE_C_OCP# to PCH USB_OC2# SF
4
3
2
1
5
6
7
8
10K_1206_8P4R_5%
F4 Within
F3
U13
G3
BE41
RH127
RC184
2
2
1 113_0402_1%
1 1K_0402_5%
RC183
500 mils
2
1 1K_0402_5%
+3VALW_PCH
1 RH814 2
100K_0402_5%
GPD7
G45
G46
Y41
Y40
G48
G49
W44
W43
H48
H47
U41
U40
F46
G47
R44
T43
C
Strap Pin, refer PDG
2
4
RH837
10K_0201_5%
@
1
5
+3VS
RH19
2
PCH_GPU_EVENT#
1 10K_0402_5%
@
Need to confirm with intel 0526@Stone
+1.8VALW
B
B
RH815 1
RH809
1
UH1M
GPP_J4
2 20K_0402_5%
1
RH810
2 10K_0201_5%
@
GPP_J6
RH812 @1
2 2.2K_0201_5%
GPP_J9
RH808
1
2 2.2K_0402_5%
@
2 2.2K_0201_5%
PXS_PWREN
PCH_GPU_EVENT#
@
RC10 2
PXS_RST#
{28,51} PXS_PWREN
{28} PCH_GPU_EVENT#
RC12 1
{28} PXS_RST#
Strap Pin
@
1 0_0402_5%
PXS_PWREN_R
2 0_0201_5%
PXS_RST#_R
PCH_FB_GC6_EN
{28} PCH_FB_GC6_EN
RH832
20K_0402_5%
@
2
2
RH831
20K_0402_5%
@
{45} CNVI_BRI_DT
{45} CNVI_BRI_RSP
{45} CNVI_RGI_DT
{45} CNVI_RGI_RSP
AP3
AP2
AN4
AM7
1
1
+1.8VALW
AW13
BE9
BF8
BF9
BG8
BE8
BD8
AV13
R10389 1 CNVI@ 2 33_0402_5%
R10393 1 CNVI@ 2 33_0402_5%
GPP_J4
GPP_J6
GPP_J9
AV6
AY3
AR13
AV7
AW3
AT10
AV4
AY2
BA4
AV3
AW2
AU9
GPP_G0/SD_CMD
GPP_G1/SD_A0
GPP_G2/SD_A1
GPP_G3/SD_A2
GPP_G4/SD_A3
GPP_G5/SD_CD#
GPP_G6/SD_CLK
GPP_G7/SD_WP
CNV_WR_CLKN
CNV_WR_CLKP
CNV_WR_D0N
CNV_WR_D0P
CNV_WR_D1N
CNV_WR_D1P
CNV_WT_CLKN
CNV_WT_CLKP
GPP_I11/M2_SKT2_CFG0
GPP_I12/M2_SKT2_CFG1
GPP_I13/M2_SKT2_CFG2
GPP_I14/M2_SKT2_CFG3
CNV_WT_D0N
CNV_WT_D0P
CNV_WT_D1N
CNV_WT_D1P
CNV_WT_RCOMP
GPP_J0/CNV_PA_BLANKING
GPP_ J1 / CPU_C10_GATE#
GPP_J11/A4WP_PRESENT
PCIE_RCOMPN
GPP_J10
PCIE_RCOMPP
GPP_J2
SD_1P8_RCOMP
GPP_J3
SD_3P3_RCOMP
GPP_J4/CNV_BRI_DT_UART0B_RTS# GPPJ_RCOMP_1P8_1
GPP_J5/CNV_BRI_RSP/UART0B_RXD GPPJ_RCOMP_1P8_2
GPP_J6/CNV_RGI_DT/UART0B_TXD GPPJ_RCOMP_1P8_3
GPP_J7/CNV_RGI_RSP/UART0B_CTS#
GPP_J8/CNV_MFUART2_RXD
RSVD12
GPP_J9/CNV_MFUART2_TXD
RSVD13
13 OF 13
RSVD14
TP_2
BD4 CNVI_WR_CLK_N
BE3 CNVI_WR_CLK_P
BB3
BB4
BA3
BA2
CNVI_WR_CLK_N
CNVI_WR_CLK_P
CNVI_WR_D0_N
CNVI_WR_D0_P
CNVI_WR_D1_N
CNVI_WR_D1_P
CNVI_WR_D0_N
CNVI_WR_D0_P
CNVI_WR_D1_N
CNVI_WR_D1_P
BC5 CNVI_WT_CLK_N
BB6 CNVI_WT_CLK_P
CNVI_WT_CLK_N
CNVI_WT_CLK_P
BE6 CNVI_WT_D0_N
BD7 CNVI_WT_D0_P
BG6 CNVI_WT_D1_N
BF6 CNVI_WT_D1_P
BA1
R10391 1 CNVI@ 2
150_0402_1%
B12 PCIE_RCOMN
A13 PCIE_RCOMP
RH741
BE5 SD_1P8_RCOMP
RH742
SD_3P3_RCOMP
BE4
RH819
BD1
RCOMP_1P8
BE1
RH820
BE2
CNVI_WT_D0_N
CNVI_WT_D0_P
CNVI_WT_D1_N
CNVI_WT_D1_P
{45}
{45}
{45}
{45}
{45}
{45}
{45}
{45}
{45}
{45}
{45}
{45}
2
1
1
1
100_0402_1%
2 200_0402_1%
2 200_0402_1%
1
2 200_0402_1%
CAD Note:
Trace width=15 mils ,Spacing=15mil
Max length= N/A mils.
0602 Stone: Add refer to EDS & CRB
Y35
Y36
BC1
AL35
CNVI_LDO_MON 1
TH38 @
CANNONLAKE-H-PCH_FCBGA874
@
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/02/26
Deciphered Date
Blank
2018/09/20
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Size
Document
Custom
4
3
https://Dr-Bios.com
2
Number
Rev
0.1
FG541/FG741
Date:
5
Tuesday, February 26, 2019
1
Sheet
19
of
69
5
4
3
2
1
+3VS
Bit 6
@
RH160
2
1 10K_0402_5%
RH161
2 @
1 10K_0402_5%
PCH_WLAN_OFF#
SPI
1
GPP_B22 /GSPI1_MOSI (Boot BIOS Strap Bit BBS)
This Signal has a weak internal pull-down.
This field determines the destination of accesses to the
BIOS memory range. Also controllable using Boot BIOS
Destination bit (Bus0, Device31, Function0, offset DCh,bit6)
0: SPI(default)
1: LPC
Notes:
1. The internal pull-down is disabled after PCH_PWROK is high.
4. This signal is in the primary well.
D
Boot BIOS
Destination
0
PCH_BT_OFF#
LPC
(Default)
D
Add Board ID reserve 1130SF
+3VALW_PCH
+3VALW_PCH
+3VALW_PCH
Strap PIN
C
PCH_RTS5455_SCL
PCH_RTS5455_SDA
DIMM_ONLY@
1
2
1
2
RH776
10K_0402_5%
2
1
RH774
10K_0402_5%
2
@
1
10K_0402_5%
2
1
10K_0402_5%
2
1
10K_0402_5%
2
1
10K_0402_5%
2
1
10K_0402_5%
2
1
DIMM_ONLY@
RH163
2
@
1
@
10K_0402_5%
2
RH777
1
@
RH775
10K_0402_5%
2
RH195
1
RH159
10K_0402_5%
15@
RH158
2
RH157
@ 2
18P@
1
@
1
@
RH847
RH851
2
RH849
10K_0402_5%
GPP_C19/I2C1_SCL
GPP_C18/I2C1_SDA
GPP_C17/I2C0_SCL
GPP_C16/I2C0_SDA
GPP_D4/ISH_I2C2_SDA/I2C3_SDA/SBK4_BK4
GPP_D23/ISH_I2C2_SCL/I2C3_SCL 11 OF 13
PCH_GPA23
PCH_GPA22
PCH_GPA21
PCH_GPA20
PCH_GPA19
PCH_GPA18
PCH_GPA17
@
GPP_C23/UART2_CTS#
GPP_C22/UART2_RTS#
GPP_C21/UART2_TXD
GPP_C20/UART2_RXD
@
RH153
PCH_GPH21
AV34
AW32
BA33
BE34
BD34
BF35
BD38
2
GPP_A23/ISH_GP5
GPP_A22/ISH_GP4
GPP_A21/ISH_GP3
GPP_A20/ISH_GP2
GPP_A19/ISH_GP1
GPP_A18/ISH_GP0
GPP_A17/SD_VDD1_PWR_EN#/ISH_GP7
AH47
AH48
1
BE21
BF21
BC22
BF23
BE15
BE14
GPP_H22/ISH_I2C1_SCL
GPP_H21/ISH_I2C1_SDA
PCH_GPH21
PCH_GPH19
17@
RH155
10K_0402_5%
{50} TP_I2C_SCL0
{50} TP_I2C_SDA0
GPP_C15/UART1_CTS#/ISH_UART1_CTS#
GPP_C14/UART1_RTS#/ISH_UART1_RTS#
GPP_C13/UART1_TXD/ISH_UART1_TXD
GPP_C12/UART1_RXD/ISH_UART1_RXD
PCH_GPH19
AG45
AH46
RH152
10K_0402_5%
{45} PCH_UART2_TXD
{45} PCH_UART2_RXD
AV21
AW21
BE20
BD20
GPP_H20/ISH_I2C0_SCL
GPP_H19/ISH_I2C0_SDA
17P@
PCH_GPA17
PCH_GPA18
PCH_GPA19
PCH_GPA20
PCH_GPA21
PCH_GPA23
PCH_GPA22
1
PCH_UART2_TXD
PCH_UART2_RXD
BD21
AW24
AP21
AU24
GPP_C9/UART0A_TXD
GPP_C8/UART0A_RXD
GPP_C11/UART0A_CTS#
GPP_C10/UART0A_RTS#
@
RH846
10K_0402_5%
VGA_ALERT#_PCH
BB24
BE23
AP24
BA24
@
BF14
AR18
BF17
BE17
2
{25,28} VGA_PWRGD
2 0_0402_5%
GPP_D16/ISH_UART0_CTS#/CNV_WCEN
GPP_D15/ISH_UART0_RTS#/GSPI2_CS1#/CNV_WFEN
GPP_D14/ISH_UART0_TXD/I2C2_SCL
GPP_D13/ISH_UART0_RXD/I2C2_SDA
RH852
1
RH780 @1
GPP_B18/GSPI0_MOSI
GPP_B17/GSPI0_MISO
GPP_B16/GSPI0_CLK
GPP_B15/GSPI0_CS0#
BA20
BB20
BB16
AN18
10K_0402_5%
EC_SCI#
PCH_BT_OFF#
PCH_TP_INT#
{14,49} EC_SCI#
{45} PCH_BT_OFF#
{50} PCH_TP_INT#
{46} USBDEBUG
GPP_D9/ISH_SPI_CS#/GSPI2_CS0#
GPP_D10/ISH_SPI_CLK/GSPI2_CLK
GPP_D11/ISH_SPI_MISO/GP_BSSB_CLK/GSPI2_MISO
GPP_D12/ISH_SPI_MOSI/GP_BSSB_DI/GSPI2_MOSI
10K_0402_5%
BE30
BD29
BF29
BB26
{41} GPP_B18_NO_REBOOT
{42,49} LAN_PWR_ON#
RH848
GPP_B22/GSPI1_MOSI
GPP_B21/GSPI1_MISO
GPP_B20/GSPI1_CLK
GPP_B19/GSPI1_CS0#
2
GPP_B18_NO_REBOOT
BA26
BD30
AU26
AW26
1
2 4.7K_0402_5%
10K_0402_5%
RH750 @1
PCH_WLAN_OFF#
PCH_CMOS_ON#
{45} PCH_WLAN_OFF#
{38} PCH_CMOS_ON#
10K_0402_5%
DIMM_ONLY@
UH1K
C
CANNONLAKE-H-PCH_FCBGA874
@
reservd by Bing 0627
PCH is input
+1.8VS_AON
SKU ID
DRAM
Memory
Down(DDR4)
DRAMCFG
PCH_GPA22
PCH_GPA21
L/RH775
L/RH777
L/RH195
1(0x001)
L/RH775
L/RH777
H/RH163
2(0x010)
L/RH775
H/RH776
L/RH195
3(0x011)
2
G
2666 MT/s
3
1
S
VGA_ALERT#_PCH
D
{28} VGA_ALERT#
PCH_GPA23
0(0x000)
L/RH775
H/RH776
H/RH163
Samsung 8Gb
Board ID
Description
Hynix 8Gb
Stuff R
8Gb
QV22
LBSS139WT1G_SC70-3
@
0
15 "
EG530
1
17 "
EG730
Micron 8Gb
RH157
RH152
2666 MT/s
PCH_GPA18
B
2666 MT/s
Samsung 4Gb
2400 MT/s
Hynix 4Gb
0
RH158
2400 MT/s
4(0x100)
H/RH774
L/RH777
L/RH195
touch
RH155
Micron 4Gb
2400 MT/s
5(0x101)
H/RH774
L/RH777
H/RH163
0
non-KB BL
RH159
X
6(0x110)
H/RH774
H/RH776
L/RH195
1
KB BL
RH153
SO-DIMM
7(0x111)
H/RH774
H/RH776
H/RH163
0
Reserved
RH847
1
Reserved
RH846
0
Reserved
RH849
1
Reserved
RH848
0
Reserved
RH851
1
PCH_RTS5455_SDA
PCH_RTS5455_SCL
non-touch
1
reservd for UCMcx by Bing 0718
Reserved
RH852
8Gb
PCH_GPA19
+3VALW_PCH
RP5
1
2
4
3
B
PCH_GPA20
2.2K_0404_4P2R_5%
@
PCH_GPA17
PCH_GPH19
PCH_GPH21
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/02/26
Deciphered Date
https://Dr-Bios.com
2018/09/20
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
5
4
3
2
PCH (6/9) GPPPABCD, I2C
Size
C
Date:
Document Number
Rev
0.1
FG541/FG741
Thursday, January 03, 2019
1
Sheet
20
of
69
5
4
3
2
1
+3VALW_PCH
1
1
+3VS
RH760
0_0805_5%
RH759
0_0805_5%
@
2
@
2
+VCCPFUSE_3P3
+VCCPRIM_1P05
@
+1.05VALW
RH789
0_0805_5%
Need short
JC2
1
@
RH791 1
UH1H
1
2
@
+VCCPRIM_FUSE_1P05
2
2
AA22
AA23
AB20
AB22
AB23
AB27
AB28
AB30
AD20
AD23
AD27
AD28
AD30
AF23
AF27
AF30
U26
U29
V25
V27
V28
V30
V31
JUMP_43X79
@
2 0_0402_5%
+VCCPRIM_CNV_HVLDO_1P05
@
RH790 1
+VCCDUSB_1P05
2 0_0402_5%
4.174A (VCCPRIM_1P05)
@
RH792 1
+VCCDSW_1P05
2 0_0402_5%
+VCCPRIM_1P05
@
+VCCMPHY_1P05
JC4
RH793 1
2 0_0402_5%
1
+VCCCLPLLEBB_1P05
RH794 1
+VCCAZPLL_1P05
1
2
2 0_0402_5%
@
2 0_0402_5%
+VCCA_OCPLL1_1P05
BG45
BG46
+VCCDSW_1P05
@
RH787 1
2 0_0402_5%
+VCCCLPLLEBB_1P05
+VCCAZPLL_1P05
RH798 1
2 0_0402_5%
W31
D1
E1
+VCCAMPHYPLL_1P05
@
+VCCA_BCLKPLL2_1P05
W22
W23
+VCCDUSB_1P05
RH797 1
C49
D49
E49
@
RH799 1
2 0_0402_5%
+VCCA_XTAL_1P05
+VCCA_SRC_1P05
+VCCPRIM_1P05
P2
P3
W19
W20
+VCCFHV1_1P05
@
RH199 1
2 0_0402_5%
V19
B1
B2
B3
+VCCA_BCLKPLL2_1P05
VCCPRIM_3P3_5
VCCSPI
VCCRTC_1
VCCRTC_2
VCCPGPPG_3P3
VCCPRIM_3P3_3
VCCPRIM_3P3_4
VCCPGPPHK_1
VCCPGPPHK_2
VCCPGPPEF_1
VCCPGPPEF_2
VCCPGPPD
VCCPGPPBC_1
VCCPGPPBC_2
VCCPRIM_1P05_14
VCCPRIM_1P05_15
VCCPGPPA
VCCDUSB_1P05_1
VCCDUSB_1P05_2
VCCPRIM_3P3_1
VCCDSW_3P3_1
VCCDSW_3P3_2
VCCDSW_1P05_1
VCCDSW_1P05_2
VCCHDA
VCCPRIM_MPHY_1P05
VCCPRIM_1P05_21
VCCPRIM_1P05_22
VCCPRIM_1P8_3
VCCPRIM_1P8_4
VCCPRIM_1P8_5
VCCPRIM_1P8_6
VCCPRIM_1P8_7
VCCAMPHYPLL_1P05_1
VCCAMPHYPLL_1P05_2
VCCAMPHYPLL_1P05_3
VCCPRIM_1P8_1
VCCPRIM_1P8_2
VCCA_XTAL_1P05_1
VCCA_XTAL_1P05_2
VCCPRIM_1P05_20
VCCPRIM_1P05_19
VCCA_SRC_1P05_1
VCCA_SRC_1P05_2
VCCPRIM_1P24_1
VCCPRIM_1P24_2
VCCAPLL_1P05_4
VCCAPLL_1P05_5
VCCDPHY_1P24_1
VCCDPHY_1P24_2
VCCDPHY_1P24_3
VCCA_BCLK_1P05
VCCAPLL_1P05_1
VCCAPLL_1P05_2
VCCAPLL_1P05_3
8 OF 13
VCCMPHY_SENSE
VSSMPHY_SENSE
AW9
+VCCPHV_3P3
+VCCPGPPA
BF47
BG47
V23
AN44
+VCCPUSB2_3P3
+3V_SPI
BC49
BD49
+VCCRTC_3P3
AN21
AY8
BB7
@
2
RH222 1
+VCCPGPPBC
RH223 1
2 0_0402_5%
+VCCPGPPEF
@
@
+VCCPGPPG
+VCCPHVLDO_3P3
2 0_0402_5%
@
1
RH224 1
2 0_0402_5%
+VCCPGPPG
@
AC35
AC36
AE35
AE36
+VCCPGPPHK
RH225 1
+VCCPUSB2_3P3
+VCCPGPPEF
2 0_0402_5%
@
RH226 1
AN24
2 0_0402_5%
+VCCPGPPD
@
+VCCPGPPBC
RH784 1
AN32
+VCCPGPPA
AT44
+VCCPHV_3P3
+VCCPHVLDO_3P3
2 0_0402_5%
2
@
RH785 1
+VCCHDA
AG19
AG20
AN15
AR15
BB11
1
C
RH221 1
@
2 0_0402_5%
+VCCPRIM_1P8
AF19
AF20
+VCCPHVLDO_1P8
AG31
AF31
+VCCFHV1_1P05
+VCCFHV0_1P05
AK22
AK23
+VCCPHVLDO_1P8
RH807
1
+VCCPRIM_1P8
2 0_0402_5%
@
1
@
+VCCLDOSRAM_IN_1P24
AJ22
AJ23
BG5
Option1:Use external VRM(default)
stuff RH816,unstuff RH807
Option2:Use internal LDO
unstuff RH816,stuff RH807
2 0_0402_5%
1
+VCCDPHY_1P24
+VCCDPHY_1P24_MAR
K47
K46
2
1
2@
+VCCLDOSRAM_IN_1P24
1 @
Place close to BG5
2
+VCCPRIM_1P05
+VCCA_XTAL_1P05
RH827 1
B
2 0_0603_5%
2@
2 0_0603_5%
2@
1
+VCCRTC_3P3
@
RH216 1
2 0_0402_5%
1
2@
2
1
2
.1U_0402_10V6-K
CH245
1
VCCRTC
2@
CH244
1U_0402_6.3V6K
2
22U_0603_6.3V6-M
CH275
1
22U_0603_6.3V6-M
CH273
folllow PDG:
placeholder LC filter
If used,need to confirm LC spec
1U_0402_6.3V6K
CH255
@
1
22U_0603_6.3V6-M
CH274
1
+VCCAMPHYPLL_1P05
1
22U_0603_6.3V6-M
CH276
@
LH2
C10119
4.7U_0603_6.3V6K
2
.1U_0402_10V6-K
CH292
2
2 0_0402_5%
+VCCDUSB_1P05
CH272
@
1U_0402_6.3V6K
1
1
CH25
2
2
1U_0402_6.3V6K
2
1
1U_0402_6.3V6K
CH30
2
1
22U_0603_6.3V6-M
CH29
@
CH279
1U_0402_6.3V6K
22U_0603_6.3V6-M
CH253
2
1
+VCCDPHY_1P24
2 0_0402_5%
@
RH818 1
1
1
B
+1.8VALW
RH816
@
+VCCA_BCLKPLL2_1P05
@
2 0_0402_5%
RH817 1
+VCCDSW_1P05
2
+VCCPGPPD
+VCCDPHY_1P24_MAR
+VCCMPHY_1P05
1
@
RH746 1
+VCCDSW
BB14
2 0_0402_5%
@
+VCCPFUSE_3P3
BE48
BE49
CANNONLAKE-H-PCH_FCBGA874
@
+VCCPRIM_1P05
+VCCPGPPHK
+VCCPGPPEF
+VCCPGPPHK
AN26
AP26
4.7U_0603_6.3V6K
C10118
+VCCA_OC_1P05
2 0_0402_5%
DCPRTC_1
DCPRTC_2
1U_0402_6.3V6K
CH278
+VCCFHV0_1P05
@
RH200 1
C1
C2
+VCCA_OCPLL1_1P05
VCCPRIM_3P3_2
.1U_0402_10V6-K
CH270
+VCCA_SRC_1P05
+VCCA_OC_1P05
AD31
AE17
+VCCPRIM_FUSE_1P05
+VCCPRIM_CNV_HVLDO_1P05
2 0_0402_5%
VCCPRIM_1P05_1
VCCPRIM_1P05_2
VCCPRIM_1P05_3
VCCPRIM_1P05_4
VCCPRIM_1P05_5
VCCPRIM_1P05_6
VCCPRIM_1P05_7
VCCPRIM_1P05_8
VCCPRIM_1P05_9
VCCPRIM_1P05_10
VCCPRIM_1P05_11
VCCPRIM_1P05_12
VCCPRIM_1P05_13
VCCPRIM_1P05_16
VCCPRIM_1P05_17
VCCPRIM_1P05_18
VCCPRIM_1P05_23
VCCPRIM_1P05_24
VCCPRIM_1P05_25
VCCPRIM_1P05_26
VCCPRIM_1P05_27
VCCPRIM_1P05_28
VCCPRIM_1P05_29
.1U_0402_10V6-K
CH81
@
RH795 1
C
2
JUMP_43X79
@
Add Jump by Bing 0627
@
D
2 0_0402_5% +3VALW_PCH_R
RH220 1
+VCCPRIM_1P05
CH26
.1U_0402_10V6-K
1
D
+VCCHDA
+3VALW
@
RC292 1
2 0_0402_5%
+3VALW_PCH
+VCCDSW
RH206 1
@
+3VALW
+3VS
2 0_0402_5%
@
+VCCAZPLL_1P05
1
@
2 0_0402_5%
+VCCA_OC_1P05
RH205 1
2
C10050
2@
1
1@
1
2 0_0402_5%
1
A
@
2
2@
Issued Date
Title
LC Future Center Secret Data
Security Classification
follow CRB
reservd by Bing 0627
5
.1U_0402_10V6-K
CH291
2@
2
1U_0402_6.3V6K
CH290
2
1
.1U_0402_10V6-K
CH289
1@
1
.1U_0402_10V6-K
CH288
1
1U_0402_6.3V6K
CH287
2
1U_0603_25V7K
A
.1U_0402_10V6-K
CH248
+VCCCLPLLEBB_1P05
.1U_0402_10V6-K
CH271
LH3
+VCCA_OCPLL1_1P05 +VCCPHVLDO_3P3
2015/02/26
Deciphered Date
https://Dr-Bios.com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
4
3
2
PCH (7/9) PWR
2018/09/20
Size
C
Date:
Document Number
Rev
0.1
FG541/FG741
Tuesday, February 26, 2019
1
Sheet
21
of
69
5
4
3
2
1
UH1L
BG3
BG33
BG37
BG4
BG48
C12
C25
C30
C4
C48
C5
D12
D16
D17
D30
D33
D8
E10
E13
E15
E17
E19
E22
E24
E26
E31
E33
E35
E40
E42
E8
F41
F43
F47
G44
G6
H8
J10
J26
J29
J4
J40
J46
J47
J48
J9
K11
K39
M16
M18
M21
D
C
VSS_145
VSS_196
VSS_146
VSS_197
VSS_147
VSS_198
VSS_148
VSS_199
VSS_149
VSS_200
VSS_150
VSS_201
VSS_151
VSS_202
VSS_152
VSS_203
VSS_153
VSS_204
VSS_154
VSS_205
VSS_155
VSS_206
VSS_156
VSS_207
VSS_157
VSS_208
VSS_158
VSS_209
VSS_159
VSS_210
VSS_160
VSS_211
VSS_161
VSS_212
VSS_162
VSS_213
VSS_163
VSS_214
VSS_164
VSS_215
VSS_165
VSS_216
VSS_166
VSS_217
VSS_167
VSS_218
VSS_168
VSS_219
VSS_169
VSS_220
VSS_170
VSS_221
VSS_171
VSS_222
VSS_172
VSS_223
VSS_173
VSS_224
VSS_174
VSS_225
VSS_175
VSS_226
VSS_176
VSS_227
VSS_177
VSS_228
VSS_178
VSS_229
VSS_179
VSS_230
VSS_180
VSS_231
VSS_181
VSS_232
VSS_182
VSS_233
VSS_183
VSS_234
VSS_184
VSS_235
VSS_185
VSS_236
VSS_186
VSS_237
VSS_187
VSS_238
VSS_188
VSS_239
VSS_189
VSS_240
VSS_190
VSS_241
VSS_191
VSS_242
VSS_192
VSS_243
VSS_193
VSS_244
VSS_194
VSS_195 OF 13
VSS_245
12
VSS_246
M24
M32
M34
M49
M5
N12
N16
N34
N35
N37
N38
P26
P29
P4
P46
R12
R16
R26
R29
R3
R34
R38
R4
T17
T18
T32
T4
T49
T5
T7
U12
U15
U17
U21
U24
U33
U38
V20
V22
V4
V46
W25
W27
W28
W30
Y10
Y12
Y17
Y33
UH1I
A2
A28
A3
A33
A37
A4
A45
A46
A47
A48
A5
A8
AA19
AA20
AA25
AA27
AA28
AA30
AA31
AA49
AA5
AB19
AB25
AB31
AC12
AC17
AC33
AC38
AC4
AC46
AD1
AD19
AD2
AD22
AD25
AD49
AE12
AE33
AE38
AE4
AE46
AF22
AF25
AF28
AG1
AG22
AG23
AG25
AG27
AG28
AG30
AG49
AH12
AH17
AH33
AH38
AJ19
AJ20
AJ25
AJ27
AJ28
AJ30
AJ31
AK19
AK20
AK25
AK27
AK28
AK30
AK31
AK4
AK46
Y38
Y9
CANNONLAKE-H-PCH_FCBGA874
@
B
VSS_1
VSS_73
VSS_2
VSS_74
VSS_3
VSS_75
VSS_4
VSS_76
VSS_5
VSS_77
VSS_6
VSS_78
VSS_7
VSS_79
VSS_8
VSS_80
VSS_9
VSS_81
VSS_10
VSS_82
VSS_11
VSS_83
VSS_12
VSS_84
VSS_13
VSS_85
VSS_14
VSS_86
VSS_15
VSS_87
VSS_16
VSS_88
VSS_17
VSS_89
VSS_18
VSS_90
VSS_19
VSS_91
VSS_20
VSS_92
VSS_21
VSS_93
VSS_22
VSS_94
VSS_23
VSS_95
VSS_24
VSS_96
VSS_25
VSS_97
VSS_26
VSS_98
VSS_27
VSS_99
VSS_28
VSS_100
VSS_29
VSS_101
VSS_30
VSS_102
VSS_31
VSS_103
VSS_32
VSS_104
VSS_33
VSS_105
VSS_34
VSS_106
VSS_35
VSS_107
VSS_36
VSS_108
VSS_37
VSS_109
VSS_38
VSS_110
VSS_39
VSS_111
VSS_40
VSS_112
VSS_41
VSS_113
VSS_42
VSS_114
VSS_43
VSS_115
VSS_44
VSS_116
VSS_45
VSS_117
VSS_46
VSS_118
VSS_47
VSS_119
VSS_48
VSS_120
VSS_49
VSS_121
VSS_50
VSS_122
VSS_51
VSS_123
VSS_52
VSS_124
VSS_53
VSS_125
VSS_54
VSS_126
VSS_55
VSS_127
VSS_56
VSS_128
VSS_57
VSS_129
VSS_58
VSS_130
VSS_59
VSS_131
VSS_60
VSS_132
VSS_61
VSS_133
VSS_62
VSS_134
VSS_63
VSS_135
VSS_64
VSS_136
VSS_65
VSS_137
VSS_66
VSS_138
VSS_67
VSS_139
VSS_68
VSS_140
VSS_69
VSS_141
VSS_70
VSS_142
VSS_71
VSS_143
VSS_72 9 OF 13 VSS_144
AL12
AL17
AL21
AL24
AL26
AL29
AL33
AL38
AM1
AM18
AM32
AM49
AN12
AN16
AN34
AN38
AP4
AP46
AR12
AR16
AR34
AR38
AT1
AT16
AT18
AT21
AT24
AT26
AT29
AT32
AT34
AT45
AV11
AV39
AW10
AW4
AW40
AW46
B47
B48
B49
BA12
BA14
BA44
BA5
BA6
BB41
BB43
BB9
BC10
BC13
BC15
BC19
BC24
BC26
BC31
BC35
BC40
BC45
BC8
BD43
BE44
BF1
BF2
BF3
BF48
BF49
BG17
BG2
BG22
BG25
BG28
D
UH1J
RSVD7
RSVD8
RSVD6
RSVD5
RSVD3
RSVD4
RSVD2
RSVD1
PREQ#
PRDY#
CPU_TRST#
TRIGGER_OUT
TRIGGER_IN
10 OF 13
Y14
Y15
U37
U35
N32
R32
AH15
AH14
AL2
AM5
AM4
AK3 PCH_TRIGOUT
AK2
RH7581
2 30_0402_1%
PCH_PREQ# {41}
PCH_PRDY# {41}
CPU_TRST# {41}
CPU_TRIGIN {6}
PCH_TRIGIN {6}
C
CANNONLAKE-H-PCH_FCBGA874
@
B
CANNONLAKE-H-PCH_FCBGA874
@
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/02/26
Deciphered Date
PCH (9/9) VSS
2018/09/20
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Size
B
Date:
5
4
3
https://Dr-Bios.com
2
Document Number
Re v
0.1
FG541/FG741
Thursday, January 03, 2019
Sheet
1
22
of
69
5
4
3
2
1
D
D
C
C
B
B
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/08/20
Deciphered Date
https://Dr-Bios.com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
5
4
3
2
Cover Page
2018/09/20
Size
C
Date:
Document Number
Rev
0.1
FG541/FG741
Thursday, January 03, 2019
1
Sheet
23
of
69
5
4
3
STRAP2
N17P-G1 GPIO
2
STRAP1
STRAP0
RAMCFG[4:0]
L
L
L
H
L
00010
PWM Output to control NVVDD
L
H
H
00011
FB Enable for GC6 2.1
H
H
L
00110
-
GPU wake signal for GC6 2.1
H
H
H
00111
-
M=Middle: Tied to 0.9V
00000
L
1
H=High: Tied to 1.8V
PWM Output to control the SRAM power supply
GPIO
I/O
ACTIVE
GPIO0
OUT
-
GPIO1
OUT
-
GPIO2
IN
GPIO3
OUT
Function Description
I/O Termination
L=Low: Tied to
0V
D
D
GPIO4
OUT
-
GPU power sequencing for GC6 2.1 --- 1V8_MAIN_EN
GPIO5
IN
N/A
Active low Frame Lock
GPIO9
I/O
-
Memory VREF Control
OUT
-
GPIO12
GPIO13
IN
OUT
-
N/A
GPIO14
IN
N/A
IN
N/A
Hot Plug Detect for IFPB
GPIO16
OUT
-
IN
N/A
Hot Plug Detect for IFPD
GPIO18
IN
N/A
Hot Plug Detect for IFPE
GPIO19
OUT
N/A
3D Vision L/R Signal
GPIO20
N/A
GC5_MODE
GPIO21
I/O
N/A
I/O
N/A
1001
H
H
H
1000
L
M
0111
M
L
0110
M
H
0101
H
M
0100
L
M
0011
M
L
0010
M
H
0001
H
M
SOR0/1/2/3 ENABLE
0000
UNUSED
GPIO22
1111 DEFAULT
C
System side PCIe reset monitor
GPIO17
L
H
Hot Plug Detect for IFPA
GPIO15
1010
H
H
LCD Panel Backlight Enable
H
L
(10K pull High)
1011
L
L
AC power detect or power supply overdraw input
L
L
(100K pull Down)
1100
L
L
Panel Power enable
1101
H
H
OUT
GPIO11
L
H
H
GPIO10
H
1:ENABLE 0:DISABLE
111 0
H
Active Low Thermal Alert
H
H
Memory voltage Control
L
L
H
Panel Backlight enable
L
L
Phase Shedding, NVVDD_PSI
N/A
-
SOR_EXPOSED[3:0]
L
-
OUT
OUT
ROM_SCLK
L
OUT
GPIO7
GPIO8
ROM_SI
L
GPIO6
C
ROM_SO
UNUSED
STRAP5
H
1
1
1
1
M
H
L
1
1
1
0
0:DEVID_SEL ORIGNAL
M
L
H
1
1
0
1
1:PCIE_CFG LOW POWER
M
L
L
1
1
0
0
L
H
M
1
0
1
1
L
M
H
1
0
1
0
L
M
L
1
0
0
1
L
L
M
1
0
0
0
H
H
H
0
1
1
1
H
H
L
0
1
1
0
H
L
H
0
1
0
1
H
L
L
0
1
0
0
L
H
H
0
0
1
1
L
H
L
0
0
1
0
NVVDD
L
L
H
0
0
0
1 DEFAULT
NVVDDS/+1.0VGS
L
L
L
0
0
0
0
OUT
-
GPU PCIe self-reset control
GPIO24
IN
N/A
Hot Plug Detect for IFPF
GPIO25
N/A
GPIO26
GPIO27
N/A
IN
N/A
UNUSED
UNUSED
Hot Plug Detect for IFPC
B
N17P-G1 Power Sequence
+1.8VS_AON
NVVDDS/+1.0VGS
+1.8VGS
DEVID_SEL
1:SMB_ALT_ADDR ENABLE
STRAP3
H
GPIO23
SMB_ALT_ADDR
VGA_DEVICE
STRAP4
M
PCIE_CFG
0:SMB_ALT_ADDR DISABLE
1:DEVID_SEL REBRAND
0:PCIE_CFG HIGH POWER
1:VGA_DEVICE ENABLE
0:VGA_DEVICE DISABLE
B
NVVDD
FBVDDQ
A
A
1. All power rail ramp up time should be larger than 40us
and is recommended to be less than 2ms.
1. NVVDDS/PEX_DVDD must ramp down before NVVDD, all
other power rails can ramp down together with NVVDD.
2. T (from 1V8_MAIN_EN to PEX_DVDD/NVVDD_Pgood)
must NOT exceed 4ms.
2. All 3.3V devices that connect to the GPU must be
ramp down before 1V8_AON; GPU can NOT have any 3.3V
leakage path after 1V8_AON and 1.8V_MAIN power down.
3. All 3.3V devices that connect to the GPU must be
powered after 1V8_AON; GPU can NOT have any 3.3V
leakage path before 1V8_AON present.
3. The previous power rail must ramp down to 10% before
the next power rail can start ramping down.
Issued Date
Title
LC Future Center Secret Data
Security Classification
4. The previous power rail must ramp up to 90% before
the next power rail can start ramping up.
2015/08/20
Deciphered Date
https://Dr-Bios.com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
5
4
3
2
VGA Notes List
2018/09/20
Size
C
Date:
Document Number
Rev
0.1
FG541/FG741
Thursday, January 03, 2019
1
Sheet
24
of
69
5
4
3
2
3A
UV1A
2 0.22U_0201_6.3V6-K OPT@
2 0.22U_0201_6.3V6-K OPT@
{5} PCIE_CRX_GTX_P14
{5} PCIE_CRX_GTX_N14
{5} PCIE_CTX_C_GRX_P13
{5} PCIE_CTX_C_GRX_N13
PCIE_CRX_GTX_P14
CV54 1
PCIE_CRX_GTX_N14
CV55 1
2 0.22U_0201_6.3V6-K OPT@
2 0.22U_0201_6.3V6-K OPT@
{5} PCIE_CRX_GTX_P15
{5} PCIE_CRX_GTX_N15
{5} PCIE_CTX_C_GRX_P14
{5} PCIE_CTX_C_GRX_N14
PCIE_CRX_GTX_P15
CV56 1
PCIE_CRX_GTX_N15
CV57 1
RF_NS@
CD86
33P_0402_50V8J
RF_NS@
CD85
33P_0402_50V8J
OPT@
CV553
10U_0603_6.3V6M
OPT18@
CV551
10U_0603_6.3V6M
OPT18@
CV552
10U_0603_6.3V6M
OPT18@
CV555
22U_0603_6.3V6-M
OPT@
CV554
22U_0603_6.3V6-M
OPT18@
CV548
4.7U_0603_6.3V6K
OPT@
CV549
4.7U_0603_6.3V6K
OPT@
CV550
4.7U_0603_6.3V6K
CV537
1U_6.3V_M_X5R_0201
@
CV1448
1U_6.3V_K_X5R_0201
@
CV1449
1U_6.3V_K_X5R_0201
@
CV1450
1U_6.3V_K_X5R_0201
@
CV1451
1U_6.3V_K_X5R_0201
@
CV1452
1U_6.3V_K_X5R_0201
@
CV1453
1U_6.3V_K_X5R_0201
OPT@
CV5
1U_6.3V_M_X5R_0201
OPT18@
CV536
1U_6.3V_M_X5R_0201
OPT18@
OPT@
CV4
1U_6.3V_M_X5R_0201
CV3
1U_6.3V_M_X5R_0201
OPT@
CV2
1U_6.3V_M_X5R_0201
OPT@
1
Near
D
Midway
PEX_HVDD
Decouling
+1.8VS_VGA
1
1
2
2
Near GPU
1
2
1
1
1
1
1
2
2
2
2
2
2
1
1
2
2
1
1
2
2
1
1
1
1
2
2
2
2
1
1
2
MLCC
N18
1.0uF 13/6
Mid way
2
1
CV535
22U_0603_6.3V6-M
OPT@
1
150mils)
CV302
22U_0603_6.3V6-M
OPT18@
GPU(below
OPT@
1
2
1
2
N17
4
4.7uF
3
0
3
2
0
Under
2
0
0
2
0
location
0
4.7uF
2
1
10uF
22uF
10uF
22uF
Near
Midway
MAX:250mA
MAX:100mA
CORE_PLLVDD
PEX_RX8
PEX_RX8*
2
1
2
30ohms (ESR=0.01)
P/N;SM01000M300
N18 change
PEX_TX9
PEX_TX9*
Bead
PEX_RX9
PEX_RX9*
1
2
1
2
1
2
2
1
1
2
XSN_PLLVDD
GPCPLL_AVDD
SP_PLLVDD
AD7
VID_PLLVDD
MLCC
PEX_RX10
PEX_RX10*
CV31
N18
1uf
XTALSSIN
XTAL_IN
H1
EXT_REFCLK_FL
H3
XTAL_OUTBUFF
XTAL_IN
XTAL_OUT
J4
H2
XTAL_OUT
RV46
10K_0402_5%
OPT@
RV209
Place near GPU
1
2
10M_0402_5%
OPT@
RV14
10K_0402_5%
OPT@
Near
PEX_TX11
PEX_TX11*
C
XTALOUT
N18P-FCBGA960_BGA960
N17 location
0.1uf
RV211
10K_0402_5%
@
2
PEX_PLL_HVDD/Q Decouling Value
PEX_TX10
PEX_TX10*
YV1
XTAL_IN
Core_PLLVDD Decouling Value
PEX_RX11
PEX_RX11*
1
2
MLCC
PEX_TX12
PEX_TX12*
N18
N17 location
CV16
1uf
0.1uf
1uf
0.1uf
1uf
0.1uf
PEX_RX13
PEX_RX13*
PEX_TX14
PEX_TX14*
1uf
0.1uf
Under
4
GND2
GND1
OSC2
XTAL_OUT
3
1
27MHZ_10PF_7V27000050
CV262
OPT@
8P_50V_B_NPO_0402
OPT@
Under
CV37
2
PEX_TX13
PEX_TX13*
OSC1
Under
CV33
1
Under
CV32
PEX_RX12
PEX_RX12*
AP26
AP27
+1.8VS_AON
AD8
H26
AE8
2
1
LV1
HCB1608KF-300T60_2P
OPT@
11/17 XTAL_PLL
Place Under GPU/1 cap per pin
CORE_PLLVDD
1
PEX_TX8
PEX_TX8*
UV1Q
CORE_PLLVDD
1
+1.8VS_VGA
2 0_0402_5%
1
1
OPT18@
RV7
OPT18@
PEX_PLL_HVDD
PEX_PLL_HVDD
CV37
1U_6.3V_M_X5R_0201
PEX_RX7
PEX_RX7*
AH12
CV33
1U_6.3V_M_X5R_0201
+1.8VS_VGA
Near GPU
2
CV263
8P_50V_B_NPO_0402
OPT@
Change CV262 & CV263 from 12P to 8P
SIT 0129SF
PEX_RX14
PEX_RX14*
AL25
AK25
AN27
AM27
PEX_TX15
PEX_TX15*
PEX_RX15
PEX_RX15*
PEX_TERMP
N18P-FCBGA960_BGA960
AP29
PEX_TERMP 1
2
RV34
2.49K_0402_1%
OPT@
B
3
4
2
D
S
5
6
G
G
1
S
2
G
3
A
QV1B
LBSS138DW1T1G_SOT363-6
@
S
1
QV2
LBSS139WT1G_SC70-3
@
RV8
0_0402_5%
@
1
LBSS138LT1G
Vds=50V
Id=200mA
Rdson=Max10ohm
Vgs= +-20V
Vgs(th)=0.5V--1V
2
1
CLK_REQ_GPU#
3
QV5
LSI1012XT1G_SC-89-3
OPT@
1U_6.3V_K_X5R_0201
A
Vgs(th)≤ 0.9V
1@
CV21
2
+1.8VS_AON
CV66
.1U_0402_10V6-K
@
1@
CV20
2
RV29
0_0402_5%
2
{17} GPU_CLKREQ#
D
2
RV3
0_0402_5%
@
{20,28} VGA_PWRGD
1U_6.3V_K_X5R_0201
QV1A
LBSS138DW1T1G_SOT363-6
@
1
PLT_RST_VGA#
2
{6,14}
For UMA mode
D
2
OVERT#
1
{28} OVERT#
H_THRMTRIP#
1@
CV1
1
1
RV2
10K_0402_5%
@
choose one
RV1243
5.6K_0402_1%
@
For SWG mode
2
1
1
RV1
0_0402_5%
@
2
+1.8VS_AON
+1.8VS_VGA
{28}
WRST# {49}
RV31
10K_0402_5%
OPT@
OVERT#_NVEN
2
2
2
1
RV20
0_0402_5%
@
2
1
RV1207
0_0402_5%
@
2
B
1A
Near GPU
Under
PEX_TX7
PEX_TX7*
AK24
AJ24
Change PEG from X8 to X16
SF SDV 20170810
AG13
AG15
AG16
AG18
AG25
AH15
AH18
AH26
AH27
AJ27
AK27
AL27
AM28
AN28
PEX_RX6
PEX_RX6*
AN26
AM26
PCIE_CTX_C_GRX_P15
PCIE_CTX_C_GRX_N15
0
Under
PEX_TX6
PEX_TX6*
AH23
AG23
PCIE_CRX_C_GTX_P15
PCIE_CRX_C_GTX_N15
2
0
0
1
PEX_RX5
PEX_RX5*
AN24
AM24
PCIE_CTX_C_GRX_P14
PCIE_CTX_C_GRX_N14
0
3
2
0
10uF
location
PEX_TX5
PEX_TX5*
AK23
AJ23
PCIE_CRX_C_GTX_P14
PCIE_CRX_C_GTX_N14
0
4.7uF
2
PEX_RX4
PEX_RX4*
AP23
AP24
PCIE_CRX_C_GTX_P13
PCIE_CRX_C_GTX_N13
2
2
PEX_TX4
PEX_TX4*
AL22
AK22
PCIE_CTX_C_GRX_P13
PCIE_CTX_C_GRX_N13
2 0.22U_0201_6.3V6-K OPT@
2 0.22U_0201_6.3V6-K OPT@
PEX_RX3
PEX_RX3*
AN23
AM23
PCIE_CTX_C_GRX_P12
PCIE_CTX_C_GRX_N12
{5} PCIE_CTX_C_GRX_P15
{5} PCIE_CTX_C_GRX_N15
PEX_TX3
PEX_TX3*
AK21
AJ21
PCIE_CRX_C_GTX_P12
PCIE_CRX_C_GTX_N12
2
3
2
{5} PCIE_CRX_GTX_P13
{5} PCIE_CRX_GTX_N13
{5} PCIE_CTX_C_GRX_P12
{5} PCIE_CTX_C_GRX_N12
PCIE_CRX_GTX_P13
CV49 1
PCIE_CRX_GTX_N13
CV50 1
2 0.22U_0201_6.3V6-K OPT@
2 0.22U_0201_6.3V6-K OPT@
PEX_RX2
PEX_RX2*
AN21
AM21
PCIE_CTX_C_GRX_P11
PCIE_CTX_C_GRX_N11
2 0.22U_0201_6.3V6-K OPT@
2 0.22U_0201_6.3V6-K OPT@
2
N17
4
4.7uF
1
2
{5} PCIE_CRX_GTX_P12
{5} PCIE_CRX_GTX_N12
{5} PCIE_CTX_C_GRX_P11
{5} PCIE_CTX_C_GRX_N11
PCIE_CRX_GTX_P12
CV47 1
PCIE_CRX_GTX_N12
CV48 1
PEX_TX2
PEX_TX2*
AP20
AP21
PCIE_CRX_C_GTX_P11
PCIE_CRX_C_GTX_N11
1
1
1
{5} PCIE_CRX_GTX_P11
{5} PCIE_CRX_GTX_N11
{5} PCIE_CTX_C_GRX_P10
{5} PCIE_CTX_C_GRX_N10
PCIE_CRX_GTX_P11
CV45 1
PCIE_CRX_GTX_N11
CV46 1
PEX_HVDD_1
PEX_HVDD_2
PEX_HVDD_3
PEX_HVDD_4
PEX_HVDD_5
PEX_HVDD_6
PEX_HVDD_7
PEX_HVDD_8
PEX_HVDD_9
PEX_HVDD_10
PEX_HVDD_11
PEX_HVDD_12
PEX_HVDD_13
PEX_HVDD_14
PEX_RX1
PEX_RX1*
AH20
AG20
PCIE_CTX_C_GRX_P10
PCIE_CTX_C_GRX_N10
2
1
CV534
10U_0603_6.3V6M
OPT18@
AK20
AJ20
PCIE_CRX_C_GTX_P10
PCIE_CRX_C_GTX_N10
2
1
CV1493
10U_0603_6.3V6M
OPT@
AN20
AM20
PCIE_CTX_C_GRX_P9
PCIE_CTX_C_GRX_N9
2
1
OPT18@
2 0.22U_0201_6.3V6-K OPT@
2 0.22U_0201_6.3V6-K OPT@
2
1
CV32
1U_6.3V_M_X5R_0201
{5} PCIE_CTX_C_GRX_P9
{5} PCIE_CTX_C_GRX_N9
PCIE_CRX_GTX_P10
CV43 1
PCIE_CRX_GTX_N10
CV44 1
AL19
AK19
PCIE_CRX_C_GTX_P9
PCIE_CRX_C_GTX_N9
2
1
OPT18@
{5} PCIE_CRX_GTX_P10
{5} PCIE_CRX_GTX_N10
AN18
AM18
PCIE_CTX_C_GRX_P8
PCIE_CTX_C_GRX_N8
2
1
CV16
1U_6.3V_M_X5R_0201
2 0.22U_0201_6.3V6-K OPT@
2 0.22U_0201_6.3V6-K OPT@
2
1
OPT@
CV15
4.7U_0603_6.3V6K
{5} PCIE_CTX_C_GRX_P8
{5} PCIE_CTX_C_GRX_N8
PCIE_CRX_GTX_P9
CV40 1
PCIE_CRX_GTX_N9
CV42 1
{5} PCIE_CRX_GTX_P8
{5} PCIE_CRX_GTX_N8
AK18
AJ18
PCIE_CRX_C_GTX_P8
PCIE_CRX_C_GTX_N8
2
1
OPT@
2 0.22U_0201_6.3V6-K OPT@
2 0.22U_0201_6.3V6-K OPT@
{5} PCIE_CRX_GTX_P9
{5} PCIE_CRX_GTX_N9
C
{5} PCIE_CTX_C_GRX_P7
{5} PCIE_CTX_C_GRX_N7
PCIE_CRX_GTX_P8
CV452 1
PCIE_CRX_GTX_N8
CV39 1
AP17
AP18
PCIE_CRX_C_GTX_P7
PCIE_CRX_C_GTX_N7
2
1
1
{5} PCIE_CRX_GTX_P7
{5} PCIE_CRX_GTX_N7
2 0.22U_0201_6.3V6-K OPT@
2 0.22U_0201_6.3V6-K OPT@
2
1
CV11
22U_0805_6.3V6M
{5} PCIE_CTX_C_GRX_P6
{5} PCIE_CTX_C_GRX_N6
PCIE_CRX_GTX_P7
CV35 1
PCIE_CRX_GTX_N7
CV36 1
AH17
AG17
PCIE_CRX_C_GTX_P6
PCIE_CRX_C_GTX_N6
2
1
CV1492
10U_0603_6.3V6M
OPT@
2 0.22U_0201_6.3V6-K OPT@
2 0.22U_0201_6.3V6-K OPT@
2
1
CV528
1U_6.3V_M_X5R_0201
OPT18@
CV1381
4.7U_0603_6.3V6K
OPT@
CV532
4.7U_0603_6.3V6K
OPT@
CV533
4.7U_0603_6.3V6K
{5} PCIE_CTX_C_GRX_P5
{5} PCIE_CTX_C_GRX_N5
PCIE_CRX_GTX_P6
CV30 1
PCIE_CRX_GTX_N6
CV34 1
2
1
CV527
1U_6.3V_M_X5R_0201
@
CV1441
1U_6.3V_K_X5R_0201
OPT18@
{5} PCIE_CRX_GTX_P6
{5} PCIE_CRX_GTX_N6
AN17
AM17
PCIE_CRX_C_GTX_P5
PCIE_CRX_C_GTX_N5
2
1
CV526
1U_6.3V_M_X5R_0201
@
CV1442
1U_6.3V_K_X5R_0201
OPT18@
2 0.22U_0201_6.3V6-K OPT@
2 0.22U_0201_6.3V6-K OPT@
2
1
CV522
1U_6.3V_M_X5R_0201
OPT@
CV523
1U_6.3V_M_X5R_0201
@
CV524
1U_6.3V_M_X5R_0201
@
CV1444
1U_6.3V_K_X5R_0201
OPT@
CV525
1U_6.3V_M_X5R_0201
@
CV1443
1U_6.3V_K_X5R_0201
OPT18@
{5} PCIE_CTX_C_GRX_P4
{5} PCIE_CTX_C_GRX_N4
PCIE_CRX_GTX_P5
CV28 1
PCIE_CRX_GTX_N5
CV29 1
AK17
AJ17
PCIE_CTX_C_GRX_P7
PCIE_CTX_C_GRX_N7
{5} PCIE_CRX_GTX_P5
{5} PCIE_CRX_GTX_N5
AN15
AM15
PCIE_CRX_C_GTX_P4
PCIE_CRX_C_GTX_N4
PCIE_CTX_C_GRX_P6
PCIE_CTX_C_GRX_N6
2 0.22U_0201_6.3V6-K OPT@
2 0.22U_0201_6.3V6-K OPT@
AL16
AK16
PCIE_CTX_C_GRX_P5
PCIE_CTX_C_GRX_N5
{5} PCIE_CTX_C_GRX_P3
{5} PCIE_CTX_C_GRX_N3
PCIE_CRX_GTX_P4
CV26 1
PCIE_CRX_GTX_N4
CV27 1
PCIE_CRX_C_GTX_P3
PCIE_CRX_C_GTX_N3
PCIE_CTX_C_GRX_P4
PCIE_CTX_C_GRX_N4
{5} PCIE_CRX_GTX_P4
{5} PCIE_CRX_GTX_N4
AP14
AP15
PCIE_CTX_C_GRX_P3
PCIE_CTX_C_GRX_N3
2 0.22U_0201_6.3V6-K OPT@
2 0.22U_0201_6.3V6-K OPT@
2
1
22uF
10uF
22uF
PEX_TX1
PEX_TX1*
Decouling
N18
1.0uF 12/6
PEX_RX0
PEX_RX0*
AK15
AJ15
PCIE_CTX_C_GRX_P2
PCIE_CTX_C_GRX_N2
2 0.22U_0201_6.3V6-K OPT@
2 0.22U_0201_6.3V6-K OPT@
2
1
MLCC
Near GPU Mid way
PEX_TX0
PEX_TX0*
AN14
AM14
PCIE_CRX_C_GTX_P2
PCIE_CRX_C_GTX_N2
1
150mils)
PEX_REFCLK
PEX_REFCLK*
AH14
AG14
PCIE_CTX_C_GRX_P1
PCIE_CTX_C_GRX_N1
2 0.22U_0201_6.3V6-K OPT@
2 0.22U_0201_6.3V6-K OPT@
{5} PCIE_CTX_C_GRX_P2
{5} PCIE_CTX_C_GRX_N2
PCIE_CRX_GTX_P3
CV24 1
PCIE_CRX_GTX_N3
CV25 1
{5} PCIE_CRX_GTX_P3
{5} PCIE_CRX_GTX_N3
AN12
AM12
PCIE_CRX_C_GTX_P1
PCIE_CRX_C_GTX_N1
GPU(below
@
CV1445
1U_6.3V_K_X5R_0201
@
CV1446
1U_6.3V_K_X5R_0201
@
CV1447
1U_6.3V_K_X5R_0201
{5} PCIE_CRX_GTX_P2
{5} PCIE_CRX_GTX_N2
{5} PCIE_CTX_C_GRX_P1
{5} PCIE_CTX_C_GRX_N1
PCIE_CRX_GTX_P2
CV22 1
PCIE_CRX_GTX_N2
CV23 1
AK14
AJ14
PEX_RST*
PEX_CLKREQ*
1
OPT18@
{5} PCIE_CTX_C_GRX_P0
{5} PCIE_CTX_C_GRX_N0
PCIE_CRX_GTX_P1
CV17 1
PCIE_CRX_GTX_N1
CV19 1
PCIE_CRX_C_GTX_P0
PCIE_CRX_C_GTX_N0
PEX_DVDD_1
PEX_DVDD_2
PEX_DVDD_3
PEX_DVDD_4
PEX_CVDD_1
PEX_CVDD_2
AG21
AG22
AG24
AH25
AG19
AH21
CV31
1U_6.3V_M_X5R_0201
{5} PCIE_CRX_GTX_P1
{5} PCIE_CRX_GTX_N1
2 0.22U_0201_6.3V6-K OPT@
2 0.22U_0201_6.3V6-K OPT@
AL13
AK13
PCIE_CTX_C_GRX_P0
PCIE_CTX_C_GRX_N0
CV12 1
CV13 1
Under
PEX_WAKE*
AJ12
AK12
CLK_PCIE_GPU
CLK_PCIE_GPU#
{17} CLK_PCIE_GPU
{17} CLK_PCIE_GPU#
PCIE_CRX_GTX_P0
PCIE_CRX_GTX_N0
{5} PCIE_CRX_GTX_P0
{5} PCIE_CRX_GTX_N0
AJ11
PLT_RST_VGA#
CLK_REQ_GPU#
{28} PLT_RST_VGA#
D
PEX_WAKE#
1
PEX_DVDD
+1.0VGS
2000mA
1/17 FBA
TV12@
1
1U_6.3V_K_X5R_0201
Security Classification
Issued Date
Title
LC Future Center Secret Data
2015/08/20
Deciphered Date
https://Dr-Bios.com
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF
5
4
3
2
N17P_(1/6):PEG I/F
2018/09/20
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Size Document
Custom
Number
Date:
Re v
0.1
FG541/FG741
LC FUTURE CENTER.
Wednesday, February 27, 2019
1
Sheet
25
of
69
5
4
3
2
1
Ref NV DG-08780-001
If an IFP link is unused, in general it should be left unconnected.
This includes Main and Aux links.
IFPxy_RSET and IFPxy_PLLVDD (xy=AB,CD,EF)
can be left unconnected if neither of IFPx /IFPy is in use
UV1K
UV1N
5/17 IFPAB
8/17 IFPE
DP
AH8
IFPAB_PLLVDD
1@
CV7
2
1U_6.3V_K_X5R_0201
TXD1/1
TXD1/1
TXD2/2
TXD2/2
IFPA_L1*
IFPA_L1
IFPA_L0*
IFPA_L0
IFPA_AUX_SDA*
IFPA_AUX_SCL
TXC
TXC
+1.0VGS
2
1
1
OPT18@
2
1
CV70
1U_6.3V_M_X5R_0201
OPT18@
OPT@
CV445
4.7U_0603_6.3V6K
OPT@
1
2
2
CV71
1U_6.3V_M_X5R_0201
+IFPAB_IOVDD
2 1/10W_0_+-5%_0603
CV69
1U_6.3V_M_X5R_0201
1 OPT@
@
CV1175
1U_6.3V_K_X5R_0201
RV72
AG8
IFPB_L3*
IFPB_L3
IFP_IOVDD_5
1
IFP_IOVDD_6
2
TXD0/3
TXD0/3
IFPB_L2*
IFPB_L2
IFPB_L1*
IFPB_L1
TXD2/5
TXD2/5
IFPB_L0*
IFPB_L0
IFPB_AUX_SDA*
IFPB_AUX_SCL
near
GPU
under
HDMI
RV1124
1
@
+IFPEF_PLLVDD
2 0_0603_5%
AN3
AP3
AM5
AN5
AB8
AK6
AL6
AH6
AJ6
TXC
TXC
2
IFPE_L3*
IFPE_L3
TXD0
TXD0
IFPE_L2*
IFPE_L2
TXD1
TXD1
TXD2
TXD2
+1.0VGS
+IFPF_IOVDD
2 1/10W_0_+-5%_0603
AH9
AJ9
AP5
AP6
1
AL7
AM7
2
AM8
AN8
AL8
AK8
1
2
OPT@
near
1
2
GPU
1
2
under
DP
IFPE_AUX_SDA*
IFPE_AUX_SCL
IFPE_PLLVDD
1
RV337 1 OPT@
TXD1/4
TXD1/4
AG9
IFPE_RSET
CORE_PLLVDD
AN6
AM6
OPT18@
+IFPAB_PLLVDD
2 1/10W_0_+-5%_0603
AD6
CV461
1U_6.3V_M_X5R_0201
1
IFPA_L2*
IFPA_L2
AC7
AC8
IFPE_L1*
IFPE_L1
IFPE_L0*
IFPE_L0
D
AB4
AB3
HDMI1_DAT
HDMI1_CLK
AC5
AC4
HDMI1_TXCHDMI1_TXC+
AC3
AC2
HDMI1_TX0HDMI1_TX0+
AC1
AD1
HDMI1_TX1HDMI1_TX1+
AD3
AD2
HDMI1_TX2HDMI1_TX2+
IFP_IOVDD_1
IFP_IOVDD_2
{39}
{39}
HDMI1_TXC- {39}
HDMI1_TXC+ {39}
HDMI CLK
HDMI1_TX0- {39}
HDMI1_TX0+ {39}
HDMI D0
HDMI1_TX1- {39}
HDMI1_TX1+ {39}
HDMI D1
HDMI1_TX2- {39}
HDMI1_TX2+ {39}
HDMI D2
ADD HDMI2.0 Port 20180531SF
N18P-FCBGA960_BGA960
1
OPT18@
RV69
@
IFPA_L3*
IFPA_L3
CV446
1U_6.3V_M_X5R_0201
TXD0/0
TXD0/0
OPT18@
TXC/TXC
TXC/TXC
IFPAB_RSET
CV462
1U_6.3V_M_X5R_0201
AJ8
CV463
1U_6.3V_M_X5R_0201
IFPAB_RSET
1
1K_0402_1%
2 @
RV68
CORE_PLLVDD
OPT@
CV460
4.7U_0603_6.3V6K
D
IFPEF_RSET
1
1K_0402_1%
2
RV1140 OPT@
SL/DL
@
CV1176
1U_6.3V_K_X5R_0201
DVI
2
GPU
GPU
IFPAB
C
Decouling Value
C
N18P-FCBGA960_BGA960
MLCC
CV7
1uf
N18
0.1uf
N17 location
CV222
1uf
0.1uf
CV461
1uf
0.1uf
Under
CV70
1uf
0.1uf
Under
CV71
1uf
0.1uf
Under
Under
Under
IFPD_AUX- RV112 1
EDP_OPT@
IFPD_AUX+ RV113 1
EDP_OPT@
UV1L
UV1M
7/17 IFPD
HDMI
6/17 IFPC
IFPCD_RSET
1
1K_0402_1%
EDP_OPT@ 2
RV73
AF8
CV223
IFPCD_RSET
HDMI
IFPC_AUX_SDA*
IFPC_AUX_SCL
CORE_PLLVDD
LV4
1
EDP_OPT@
+IFPCD_PLLVDD
2 1/10W_0_+-5%_0603
AF7
1
EDP_OPT@
CV222
1U_6.3V_M_X5R_0201
2
IFPC
TXC
TXC
IFPC_L3*
IFPC_L3
TXD0
TXD0
IFPCD_PLLVDD
IFPC_L2*
IFPC_L2
TXD1
TXD1
TXD2
TXD2
+1.0VGS
+IFPC_IOVDD
2
near
1
2
GPU
1
2
under
CV68
1U_6.3V_M_X5R_0201
2
ADD HDMI Port
1
CV223
1U_6.3V_M_X5R_0201
OPT18@
OPT@
CV227
4.7U_0603_6.3V6K
OPT@
1
AF6
OPT18@
OPT@ 2 1/10W_0_+-5%_0603
CV459
1U_6.3V_M_X5R_0201
1
B
@
CV1174
1U_6.3V_K_X5R_0201
LV5
DP
1
2
IFPC_L1*
IFPC_L1
IFPC_L0*
IFPC_L0
AG2
AG3
1uf
0.1uf
Under
CV68
1uf
0.1uf
Under
CV462
CV484
1uf
0.1uf
Under
1uf
0.1uf
Under
TXC
TXC
TXD0
TXD0
AJ2
AJ3
IFPD_L2*
IFPD_L2
TXD1
TXD1
AH4
AH3
IFPD_L3*
IFPD_L3
IFPD_L1*
IFPD_L1
TXD2
TXD2
AG4
AG5
2 100K_0402_5%
DP
IFPD_AUX_SDA*
IFPD_AUX_SCL
IFPD
2 100K_0402_5%
IFPD_L0*
IFPD_L0
AK2
AK3
IFPD_AUX- {38}
IFPD_AUX+ {38}
AK5
AK4
AL4
AL3
AM4
AM3
IFPD_L1IFPD_L1+
AM2
AM1
IFPD_L0IFPD_L0+
IFPD_L1- {38}
IFPD_L1+ {38}
IFPD_L0- {38}
IFPD_L0+ {38}
AJ1
AK1
IFP_IOVDD_3
N18P-FCBGA960_BGA960
AG6
B
IFP_IOVDD_4
N18P-FCBGA960_BGA960
GPU
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
Deciphered Date
2015/08/20
https://Dr-Bios.com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
5
4
3
N17P_(2/6):DIGITAL OUT I/F
2018/09/20
Size
Document Number
Custom
Date:
2
Re v
0.1
FG541/FG741
Wednesday, February 27, 2019
1
Sheet
26
of
69
5
4
3
2
1
GDDR5
Mode H - Mirror Mode Mapping
UV1B
2/17 FBA
DATA Bus
+FB_PLLAVDD
B
{31}
{31}
{31}
{31}
{32}
{32}
{32}
{32}
FBA_DBI0#
FBA_DBI1#
FBA_DBI2#
FBA_DBI3#
FBA_DBI4#
FBA_DBI5#
FBA_DBI6#
FBA_DBI7#
FBA_EDC0
FBA_EDC1
FBA_EDC2
FBA_EDC3
FBA_EDC4
FBA_EDC5
FBA_EDC6
FBA_EDC7
FBA_EDC0
FBA_EDC1
FBA_EDC2
FBA_EDC3
FBA_EDC4
FBA_EDC5
FBA_EDC6
FBA_EDC7
M31
G31
E33
M33
AE31
AK30
AN33
AF33
FB_REFPLL_AVDD
K27
OPT18@
1
FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30
FBA_CMD31
FBA_CMD32
FBA_CMD33
FBA_CMD34
FBA_CMD35
FBA_CLK0
FBA_CLK0*
FBA_CLK1
FBA_CLK1*
FBA_WCK01
FBA_WCK01*
FBA_WCK23
FBA_WCK23*
FBA_WCK45
FBA_WCK45*
FBA_WCK67
FBA_WCK67*
FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7
FBA_DQS_WP0
FBA_DQS_WP1
FBA_DQS_WP2
FBA_DQS_WP3
FBA_DQS_WP4
FBA_DQS_WP5
FBA_DQS_WP6
FBA_DQS_WP7
FBA_WCKB01
FBA_WCKB01*
FBA_WCKB23
FBA_WCKB23*
FBA_WCKB45
FBA_WCKB45*
FBA_WCKB67
FBA_WCKB67*
U30
T31
U29
R34
R33
U32
U33
U28
V28
V29
V30
U34
U31
V34
V33
Y32
AA31
AA29
AA28
AC34
AC33
AA32
AA33
Y28
Y29
W31
Y30
AA34
Y31
Y34
Y33
V31
R28
AC28
R32
AC32
R30
R31
AB31
AC31
K31
L30
H34
J34
AG30
AG31
AJ34
AK34
Under
FBA_DEBUG0
FBA_DEBUG1
FBA_CLK0
FBA_CLK0#
FBA_CLK1
FBA_CLK1#
FBC_D0
FBC_D1
FBC_D2
FBC_D3
FBC_D4
FBC_D5
FBC_D6
FBC_D7
FBC_D8
FBC_D9
FBC_D10
FBC_D11
FBC_D12
FBC_D13
FBC_D14
FBC_D15
FBC_D16
FBC_D17
FBC_D18
FBC_D19
FBC_D20
FBC_D21
FBC_D22
FBC_D23
FBC_D24
FBC_D25
FBC_D26
FBC_D27
FBC_D28
FBC_D29
FBC_D30
FBC_D31
FBC_D32
FBC_D33
FBC_D34
FBC_D35
FBC_D36
FBC_D37
FBC_D38
FBC_D39
FBC_D40
FBC_D41
FBC_D42
FBC_D43
FBC_D44
FBC_D45
FBC_D46
FBC_D47
FBC_D48
FBC_D49
FBC_D50
FBC_D51
FBC_D52
FBC_D53
FBC_D54
FBC_D55
FBC_D56
FBC_D57
FBC_D58
FBC_D59
FBC_D60
FBC_D61
FBC_D62
FBC_D63
FBA_CS#_L {31}
FBA_MA3_BA3_L {31}
FBA_MA2_BA0_L {31}
FBA_MA4_BA2_L {31}
FBA_MA5_BA1_L {31}
FBA_WE#_L {31}
FBA_MA7_MA8_L {31}
FBA_MA6_MA11_L {31}
FBA_ABI#_L {31}
FBA_MA12_RFU_L {31}
FBA_MA0_MA10_L {31}
FBA_MA1_MA9_L {31}
FBA_RAS#_L {31}
FBA_RST#_L {31}
FBA_CKE_L {31}
FBA_CAS#_L {31}
FBA_CS#_H {32}
FBA_MA3_BA3_H {32}
FBA_MA2_BA0_H {32}
FBA_MA4_BA2_H {32}
FBA_MA5_BA1_H {32}
FBA_WE#_H {32}
FBA_MA7_MA8_H {32}
FBA_MA6_MA11_H {32}
FBA_ABI#_H {32}
FBA_MA12_RFU_H {32}
FBA_MA0_MA10_H {32}
FBA_MA1_MA9_H {32}
FBA_RAS#_H {32}
FBA_RST#_H {32}
FBA_CKE_H {32}
FBA_CAS#_H {32}
1
RV119
60.4_0402_1%
1
@
RV120
60.4_0402_1%
@
2
1.55V
+1.35VGS
2
FBA_CLK0 {31}
FBA_CLK0# {31}
FBA_CLK1 {32}
FBA_CLK1# {32}
FBA_WCK0
FBA_WCK0_N
FBA_WCK1
FBA_WCK1_N
FBA_WCK2
FBA_WCK2_N
FBA_WCK3
FBA_WCK3_N
FBA_WCK0 {31}
FBA_WCK0_N {31}
FBA_WCK1 {31}
FBA_WCK1_N {31}
FBA_WCK2 {32}
FBA_WCK2_N {32}
FBA_WCK3 {32}
FBA_WCK3_N {32}
{33}
{33}
{33}
{33}
{34}
{34}
{34}
{34}
{33}
{33}
{33}
{33}
{34}
{34}
{34}
{34}
J30
J31
J32
J33
AH31
AJ31
AJ32
AJ33
FBx_CMD2
FBC_EDC0
FBC_EDC1
FBC_EDC2
FBC_EDC3
FBC_EDC4
FBC_EDC5
FBC_EDC6
FBC_EDC7
D10
D5
C3
B9
E23
E28
B30
A23
FBB_D0
FBB_D1
FBB_D2
FBB_D3
FBB_D4
FBB_D5
FBB_D6
FBB_D7
FBB_D8
FBB_D9
FBB_D10
FBB_D11
FBB_D12
FBB_D13
FBB_D14
FBB_D15
FBB_D16
FBB_D17
FBB_D18
FBB_D19
FBB_D20
FBB_D21
FBB_D22
FBB_D23
FBB_D24
FBB_D25
FBB_D26
FBB_D27
FBB_D28
FBB_D29
FBB_D30
FBB_D31
FBB_D32
FBB_D33
FBB_D34
FBB_D35
FBB_D36
FBB_D37
FBB_D38
FBB_D39
FBB_D40
FBB_D41
FBB_D42
FBB_D43
FBB_D44
FBB_D45
FBB_D46
FBB_D47
FBB_D48
FBB_D49
FBB_D50
FBB_D51
FBB_D52
FBB_D53
FBB_D54
FBB_D55
FBB_D56
FBB_D57
FBB_D58
FBB_D59
FBB_D60
FBB_D61
FBB_D62
FBB_D63
FBB_DQM0
FBB_DQM1
FBB_DQM2
FBB_DQM3
FBB_DQM4
FBB_DQM5
FBB_DQM6
FBB_DQM7
FBB_CMD0
FBB_CMD1
FBB_CMD2
FBB_CMD3
FBB_CMD4
FBB_CMD5
FBB_CMD6
FBB_CMD7
FBB_CMD8
FBB_CMD9
FBB_CMD10
FBB_CMD11
FBB_CMD12
FBB_CMD13
FBB_CMD14
FBB_CMD15
FBB_CMD16
FBB_CMD17
FBB_CMD18
FBB_CMD19
FBB_CMD20
FBB_CMD21
FBB_CMD22
FBB_CMD23
FBB_CMD24
FBB_CMD25
FBB_CMD26
FBB_CMD27
FBB_CMD28
FBB_CMD29
FBB_CMD30
FBB_CMD31
FBB_CMD32
FBB_CMD33
FBB_CMD34
FBB_CMD35
FBC_CS#_L
FBC_MA3_BA3_L
FBC_MA2_BA0_L
FBC_MA4_BA2_L
FBC_MA5_BA1_L
FBC_WE#_L
FBC_MA7_MA8_L
FBC_MA6_MA11_L
FBC_ABI#_L
FBC_MA12_RFU_L
FBC_MA0_MA10_L
FBC_MA1_MA9_L
FBC_RAS#_L
FBC_RST#_L
FBC_CKE_L
FBC_CAS#_L
FBC_CS#_H
FBC_MA3_BA3_H
FBC_MA2_BA0_H
FBC_MA4_BA2_H
FBC_MA5_BA1_H
FBC_WE#_H
FBC_MA7_MA8_H
FBC_MA6_MA11_H
FBC_ABI#_H
FBC_MA12_RFU_H
FBC_MA0_MA10_H
FBC_MA1_MA9_H
FBC_RAS#_H
FBC_RST#_H
FBC_CKE_H
FBC_CAS#_H
D13
E14
F14
A12
B12
C14
B14
G15
F15
E15
D15
A14
D14
A15
B15
C17
D18
E18
F18
A20
B20
C18
B18
G18
G17
F17
D16
A18
D17
A17
B17
E17
G14
G20
C12
C20
A2_BA0
FBx_CMD3
A4_BA2
FBx_CMD4
A5_BA1
FBx_CMD5
WE#
FBx_CMD6
A7_A8
FBx_CMD7
A6_A11
FBx_CMD8
ABI#
FBx_CMD9
A12_RFU
FBx_CMD10
A0_A10
FBx_CMD11
A1_A9
FBx_CMD12
RAS#
FBx_CMD13
RST#
FBx_CMD14
CKE#
FBx_CMD15
FBC_CS#_L {33}
FBC_MA3_BA3_L {33}
FBC_MA2_BA0_L {33}
FBC_MA4_BA2_L {33}
FBC_MA5_BA1_L {33}
FBC_WE#_L {33}
FBC_MA7_MA8_L {33}
FBC_MA6_MA11_L {33}
FBC_ABI#_L {33}
FBC_MA12_RFU_L {33}
FBC_MA0_MA10_L {33}
FBC_MA1_MA9_L {33}
FBC_RAS#_L {33}
FBC_RST#_L {33}
FBC_CKE_L {33}
FBC_CAS#_L {33}
FBC_CS#_H {34}
FBC_MA3_BA3_H {34}
FBC_MA2_BA0_H {34}
FBC_MA4_BA2_H {34}
FBC_MA5_BA1_H {34}
FBC_WE#_H {34}
FBC_MA7_MA8_H {34}
FBC_MA6_MA11_H {34}
FBC_ABI#_H {34}
FBC_MA12_RFU_H {34}
FBC_MA0_MA10_H {34}
FBC_MA1_MA9_H {34}
FBC_RAS#_H {34}
FBC_RST#_H {34}
FBC_CKE_H {34}
FBC_CAS#_H {34}
A3_BA3
CAS#
D
FBB_DEBUG1
FBB_CLK0
FBB_CLK0*
FBB_CLK1
FBB_CLK1*
FBB_WCK01
FBB_WCK01*
FBB_WCK23
FBB_WCK23*
FBB_WCK45
FBB_WCK45*
FBB_WCK67
FBB_WCK67*
FBB_WCKB01
FBB_WCKB01*
FBB_WCKB23
FBB_WCKB23*
FBB_WCKB45
FBB_WCKB45*
FBB_WCKB67
FBB_WCKB67*
D12
E12
E20
F20
FBC_CLK0
FBC_CLK0#
FBC_CLK1
FBC_CLK1#
F8
E8
A5
A6
D24
D25
B27
C27
A5_BA1
WE#
A7_A8
A6_A11
FBx_CMD24
ABI#
FBx_CMD25
A12_RFU
A0_A10
FBx_CMD27
FBC_WCK0
FBC_WCK0_N
FBC_WCK1
FBC_WCK1_N
FBC_WCK2
FBC_WCK2_N
FBC_WCK3
FBC_WCK3_N
A4_BA2
FBx_CMD20
FBx_CMD23
A1_A9
FBx_CMD28
RAS#
FBx_CMD29
RST#
FBx_CMD30
CKE#
FBx_CMD31
+1.35VGS
A2_BA0
FBx_CMD19
FBx_CMD22
2
A3_BA3
FBx_CMD18
FBx_CMD21
1
RV121
60.4_0402_1%
1
@
RV122
60.4_0402_1%
@
CS#
FBx_CMD17
FBx_CMD26
FBB_DEBUG0
FBx_CMD16
CAS#
1.55V
2
FBC_CLK0 {33}
FBC_CLK0# {33}
FBC_CLK1 {34}
FBC_CLK1# {34}
FBC_WCK0 {33}
FBC_WCK0_N {33}
FBC_WCK1 {33}
FBC_WCK1_N {33}
FBC_WCK2 {34}
FBC_WCK2_N {34}
FBC_WCK3 {34}
FBC_WCK3_N {34}
C
D6
D7
C6
B6
F26
E26
A26
A27
+FB_PLLAVDD
Core_PLLVDD
MLCC
CV64
+FB_PLLAVDD
N18
Decouling
FBB_DQS_WP0
FBB_DQS_WP1
FBB_DQS_WP2
FBB_DQS_WP3
FBB_DQS_WP4
FBB_DQS_WP5
FBB_DQS_WP6
FBB_DQS_WP7
B
FBB_PLL_AVDD
+FB_PLLAVDD
H17
1
N18P-FCBGA960_BGA960
Value
2
N17 location
1uf
0.1uf
Under
CV1160 1uf
0.1uf
Under
U27
Under
CV1160
1U_6.3V_M_X5R_0201
FBA_PLL_AVDD
FBC_DBI0#
FBC_DBI1#
FBC_DBI2#
FBC_DBI3#
FBC_DBI4#
FBC_DBI5#
FBC_DBI6#
FBC_DBI7#
E11
E3
A3
C9
F23
F27
C30
A24
FBC_EDC0
FBC_EDC1
FBC_EDC2
FBC_EDC3
FBC_EDC4
FBC_EDC5
FBC_EDC6
FBC_EDC7
GPU
G9
E9
G8
F9
F11
G11
F12
G12
G6
F5
E6
F6
F4
G4
E2
F3
C2
D4
D3
C1
B3
C4
B5
C5
A11
C11
D11
B11
D8
A8
C8
B8
F24
G23
E24
G24
D21
E21
G21
F21
G27
D27
G26
E27
E29
F29
E30
D30
A32
C31
C32
B32
D29
A29
C29
B29
B21
C23
A21
C21
B24
C24
B26
C26
FBC_DBI0#
FBC_DBI1#
FBC_DBI2#
FBC_DBI3#
FBC_DBI4#
FBC_DBI5#
FBC_DBI6#
FBC_DBI7#
2
32..63
CS#
FBx_CMD1
{33,34} FBC_D[0..63]
FBA_CS#_L
FBA_MA3_BA3_L
FBA_MA2_BA0_L
FBA_MA4_BA2_L
FBA_MA5_BA1_L
FBA_WE#_L
FBA_MA7_MA8_L
FBA_MA6_MA11_L
FBA_ABI#_L
FBA_MA12_RFU_L
FBA_MA0_MA10_L
FBA_MA1_MA9_L
FBA_RAS#_L
FBA_RST#_L
FBA_CKE_L
FBA_CAS#_L
FBA_CS#_H
FBA_MA3_BA3_H
FBA_MA2_BA0_H
FBA_MA4_BA2_H
FBA_MA5_BA1_H
FBA_WE#_H
FBA_MA7_MA8_H
FBA_MA6_MA11_H
FBA_ABI#_H
FBA_MA12_RFU_H
FBA_MA0_MA10_H
FBA_MA1_MA9_H
FBA_RAS#_H
FBA_RST#_H
FBA_CKE_H
FBA_CAS#_H
0..31
FBx_CMD0
OPT18@
{31}
{31}
{31}
{31}
{32}
{32}
{32}
{32}
FBA_DBI0# P30
FBA_DBI1# F31
FBA_DBI2# F34
FBA_DBI3# M32
FBA_DBI4# AD31
FBA_DBI5# AL29
FBA_DBI6# AM32
FBA_DBI7# AF34
FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63
CV1161
1U_6.3V_M_X5R_0201
C
3/17 FBB
L28
M29
L29
M28
N31
P29
R29
P28
J28
H29
J29
H28
G29
E31
E32
F30
C34
D32
B33
C33
F33
F32
H33
H32
P34
P32
P31
P33
L31
L34
L32
L33
AG28
AF29
AG29
AF28
AD30
AD29
AC29
AD28
AJ29
AK29
AJ30
AK28
AM29
AM31
AN29
AM30
AN31
AN32
AP30
AP32
AM33
AL31
AK33
AK32
AD34
AD32
AC30
AD33
AF31
AG34
AG32
AG33
CV64
1U_6.3V_M_X5R_0201
FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63
D
Address
UV1C
{31,32} FBA_D[0..63]
GPU
1
CV1161 1uf
0.1uf
Under
Near
2
RV123
10K_0402_1%
OPT@
2
2
A
1
1
RV124
10K_0402_1%
OPT@
RV126
10K_0402_1%
OPT@
RV125
10K_0402_1%
OPT@
2
1
2
2
1
1
1
1
2
RV308
10K_0402_1%
OPT@
FBC_RST#_L
FBC_RST#_H
2
+FB_PLLAVDD
1
CV562
4.7U_0603_6.3V6K
OPT18@
2
1
CV474
4.7U_0603_6.3V6K
OPT18@
1
LV7
HCB1608KF-300T60_2P
OPT@
Place close to BGA
+FB_PLLAVDD
CV475
22U_0603_6.3V6-M
OPT@
+1.8VS_VGA
RV309
10K_0402_1%
OPT@
FBC_CKE_L
FBC_CKE_H
FBA_RST#_L
FBA_RST#_H
+FB_PLLAVDD
30ohms (ESR=0.01) Bead
P/N;SM01000M300
N18 change
RV307
10K_0402_1%
OPT@
2
FBA_CKE_L
FBA_CKE_H
2
RV306
10K_0402_1%
OPT@
GPU
2
Under
A
+1.35VGS
2
1
OPT18@
N18P-FCBGA960_BGA960
RC702
1/20W_49.9_1%_0201
+1.35VGS
1
OPT18@
FB_VREF
1
2
H31
Issued Date
Title
LC Future Center Secret Data
Security Classification
GPU
2015/08/20
Deciphered Date
N17P_(3/6):VRAM I/F
2018/09/20
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Size
Document
Custom
4
3
https://Dr-Bios.com
2
Number
1
Re v
0.1
FG541/FG741
Tuesday, January 22, 2019
Date :
5
Sheet
27
of
69
5
4
3
2
1
RV197
100K_0402_5%
@
RV1202
10K_0402_1%
@
1
+1.8VS_AON
2
1
2
3
4
CS#
DO
WP#
GND
VCC
HOLD#
CLK
DI
8
7
6
5
ROM_SCLK_R
ROM_SI_R
2
RV1103 2 OPT18@ 1 33_0402_5%
RV1104 2 OPT18@ 1 33_0402_5%
ROM_SCLK
RV200
100K_0402_5%
OPT@
RV1203
10K_0402_1%
OPT@
L
L
L
SOR_EXPOSED[3:0]
H
L
1110
ENABLE
RV202
100K_0402_5%
OPT18@
2
E1
1
BUFRST*
ROM_SCLK
L
N18P
ROM_SCLK
ROM_SI
W25Q80EWSNIG_SO8
RV16
40.2K_0402_1%
@
ROM_SI
N17P
1
0_0402_5%
@
2
UV3
ROM_CS#_R
ROM_SO_R
RV1102 2 OPT18@ 1 33_0402_5%
@
2 0_0402_5%
RV1101 1
1:ENABLE 0:DISABLE
SOR0 DISABLE
SOR1/2/3 ENABLE
ROM_SO
GPU
ROM_SO
CV464
.1U_0402_10V6-K
OPT18@
2
ROM_CS#
ROM_SO
1
1
OPT18@
CV465
10U 6.3V M X5R 0402
@
1
1
1
2
ROM_SI
ROM_SO
ROM_SCLK
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
STRAP5
RV199
100K_0402_5%
OPT17@
ROM_SI
RV1105
10K_0402_5%
OPT18@
ROM_SI
ROM_SO
ROM_SCLK
H5
H7
H4
2
RV17
1
STRAP5
J2
J7
J6
J5
J3
J1
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
MULTI_STRAP
ROM_CS#
H6
1
ROM_CS*
2
+1.8VS_AON
12/17 MISC2
1
UV1P
2
1
2
+1.8VS_AON
2
NV RVL
RV203
10K_0402_5%
@
SPI ROM need doublecheck
change to SA00009RB00_0928SF
2
N18P-FCBGA960_BGA960
D
D
+1.8VS_AON
VRAMCFG
ADC_IN
AM9
ADC_IN*
2
L
L
H
H5GC8H24MJR-R0C
2(0x0010)
L
H
L
K4G41325FE-HC28
7(0x0111)
H
H
H
H5GC4H24AJR-R0C
6(0x0110)
H
H
L
Micron 4Gb
EDW4032BABG-70-F
8(0x1000)
L
L
M
1
1
1
2
2
2
only 0831SF
STRAP0
L
L
RV194
100K_0402_5%
X76@
4Gb
1
1
100K_0402_5%
1
2
RV193
100K_0402_5%
X76@
RV381 1 OPT18@ 2 10K_0402_5%
MEM_VREF
RV32 2 OPT@
NB_FGC6
1
100K_0402_5%
RV758 2 OPT18@ 1 10K_0402_5%
+1.8VS_AON
VGA_DEVICE
STRAP5
+1.8VS_AON
VRAM_VDDQ_ADJ
2
@
RV41
OPT@ 2
RV43
add HDMI HPD 20180604SF
1 10K_0402_5%
1 10K_0402_5%
RV19
100K_0402_5%
OPT@
RV21
100K_0402_5%
@
VGA_ALERT#
@
2
1
SMB_ALT_ADDR
DEVID_SEL
0
PCIE_CFG
VGA_DEVICE
0
1
0
0: SMB_ALT_ADDR DISABLE
{20}
1
OPT@ 2
DV1
H
1: SMB_ALT_ADDR ENABLE
STRAP4
DV6
VGA_AC_DET_R
N18P-FCBGA960_BGA960
STRAP3
L
L
RV74
100K_0402_5%
@
STRAP5
VGA_ALERT#
STRAP4
2
JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TDO
JTAG_TRST*
NVJTAG_SEL
AN9
ADC_IN_N_GPU
10K_0402_5%
@
1
1
RV1229 OPT18@ 2 0_0402_5%
ADC_IN_P_GPU
STRAP1
L
1(0x0001)
RB751V-40_SOD323-2
1: DEVID_SEL REBRAND
STRAP3
VGA_AC_DET
RB751V-40_SOD323-2
0: DEVID_SEL ORIGNAL
{49}
2
JTAG_TRST
NVJTAG_SEL
1
RV1228 OPT18@ 2 0_0402_5%
ADC_MUX_SEL
10K_0402_5%
2
RV26 1 OPT@
VGA_AC_DET_R
NVVDD_PWM_VID
RV192
100K_0402_5%
X76@
2
RV23 1 OPT@
VGA_ALERT#
P6
FB_GC6_EN
NVVDD_PWM_VID
{68}
M3 GPU_EVENT#
L6
NVVDDS_VID
NVVDD & NVVDDS merge
P5
1V8_MAIN_EN
P7
NVVDDS_VID PU to 1V8_AON
GPU_FRAME_LOCK#
1V8_MAIN_EN
L7
GPU_FRAME_LOCK#
{38}
NVVDD_PSI_GPU
M7 GPU_EDP_PWM
2 @
1 0_0402_5%
RV107
NVVDD_PSI {68}
N8
VRAM_VDDQ_ADJ
GPU_EDP_PWM {38}
L3
VGA_ALERT#
VRAM_VDDQ_ADJ
{67}
M2 MEM_VREF
L1
GPU_EDP_ENVDD
MEM_VREF {31,33}
M5 VGA_AC_DET_R
GPU_EDP_ENVDD
{38}
N3
GPU_EDP_ENBKL
M4
2 0_0402_5%
RV1245 1
GPU_EDP_ENBKL {28,38}
N4
OPT17@
P2
SYS_PEX_RST_MON#_R
R8
1
PAD @ TV13
IFPD_HPD
M6
IFPE_HPD
IFPD_HPD {38}
R1
IFPE_HPD {39}
P3
NB_FGC6
P4
RV1244
GPU_EDP_ENBKL
0_0402_5%
P1 ADC_MUX_SEL_R
2
1
RV1239
GPU_EDP_ENBKL {28,38}
P8 GPU_PEX_RST_HOLD#_R 2
1
0_0402_5%
ADC_MUX_SEL {69}
T8
@ 1
PAD
L2
TV14
FBVDDQ_PSI
R4
@ 1
GPIO26_FP_FUSE
PAD
R5
TV15
GPIO26_FP_FUSE {29}
U3
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23
GPIO24
GPIO25
GPIO26
GPIO27
RV28 1
NVVDD_PSI
OPT@
OPT@
STRAP2
0(0x0000)
MT51J256M32HF-70:A
Hynix 4Gb
10K_0402_5%
2
{69} ADC_IN_N
AM10
AP11
AM11
AP12
AN11
AK11
2 2.2K_0402_5%
2 2.2K_0402_5%
1
RAMCFG[4:0]
K4G80325FB-HC28
STRAP0
1
RV37
OPT@ 1
RV24 1
OPT@
{69} ADC_IN_P
1
1
1
1
THERMDP
RV22 1
RV25 1
10K_0402_5%
2
K3
+1.8VS_AON
I2CB_SCL
I2CB_SDA
1
RV27 2 OPT@
1V8_MAIN_EN
I2CC_SCL
I2CC_SDA
R7
R6
I2CB_SCL
I2CB_SDA
THERMDN
RV336 2 @
Internal Thermal Sensor
R2
R3
I2CC_SCL
I2CC_SDA
TS_VREF
K4
TV1 @
TV2 @
TV3 @
TV4 @
2 10K_0402_5%
2 10K_0402_5%
T4
T3
I2CS_SCL
I2CS_SDA
OVERT
AP9
VGA_SMB_CK2
VGA_SMB_DA2
2
1
1
TV5 @
FB Memory (GDDR5)
8Gb
STRAP2
TS_AVDD
M1
OVERT#
{25} OVERT#
GPU
RV189
100K_0402_5%
X76@
STRAP1
NVVDDS_VID
AG10
RV188
100K_0402_5%
X76@
1
2
RV214
100K_0402_5%
OPT@
+1.8VS_AON
OPT18@
UV1O
CV1185
10/17 MISC1
1U_0402_6.3V6K
2
2
1
Micron 8Gb
Samsung 4Gb
RV187
100K_0402_5%
X76@
2
0_0402_5%
@
Samsung 8Gb
Hynix 8Gb
RV1201
1
2
2
+1.8VS_AON
+1.8VS_AON
1: PCIE_CFG LOW POWER
RV77
100K_0402_5%
OPT@
0: PCIE_CFG HIGH POWER
1
1
RV75
100K_0402_5%
OPT@
1
RV78
100K_0402_5%
@
1: VGA_DEVICE ENABLE
0: VGA_DEVICE DISABLE
+1.8VS_AON
+1.8VS_AON
+3VS
C
C
PCH_FB_GC6_EN
{19}
2
1
discharger circuit
DG Power on/off sequence
PXS_PWREN
RV313
10K_0402_5%
OPT@
{19,51} PXS_PWREN
RV220
1
2 0_0402_5%
3
+1.8VS_AON
1
+5VALW
RV109
10K_0402_5%
OPT@
PXS_PWREN#
OPT@
1
1V8_MAIN_EN_R
+3VS
RV108
47K_0402_5%
OPT@
NVVDD_EN
{29,68}
RV66
470_0603_5%
OPT@
2 0_0402_5%
1
@
RV333
PXS_PWREN
RV335
100K_0402_1%
@
2 0_0402_5%
PXS_PWREN#
D
2
G
S
QV18
LBSS139WT1G_SC70-3
OPT@
D
2
G
2
2
@
3
RV55 1
1
BAT54AW_SOT323-3
1
RV1210
0_0402_5%
@
3
2
1
2
1
RV334
10K_0402_1%
1
Vgs(th)≤ 1.0V
RV13
0_0402_5%
@
OPT@
DV9
2
@
QV7A
LBSS138DW1T1G_SOT363-6
OPT@
2
S
1
D
2
G
{68}
+3VS
1
NVDD_SDA
QV35A
PJT7838_SOT363-6
OPT@
2
+1.8VS_VGA
2
1
1
2
DV10
OVERT#_NVEN
{25} OVERT#_NVEN
1
QV7B
LBSS138DW1T1G_SOT363-6
OPT@
2
FB_GC6_EN
6
D1
3
6
S1
2
RB751V-40_SOD323-2
1
1
G
1
2
G1
I2CC_SDA
S
5
1
RV1211
0_0402_5%
@
RV51
1
FB_GC6_EN_R
D
4
2
RV57
10K_0402_5%
OPT@
{68}
QV35B
PJT7838_SOT363-6
OPT@
2
NVDD_SCL
RV12
10K_0402_5%
OPT@
0_0402_5%
2
RV1213
2.2K_0402_5%
OPT@
3
D2
1
S2
1
G2
1
4
2
2
RV1212
2.2K_0402_5%
OPT@
5
RV1208
2.2K_0402_5%
OPT@
1
RV1209
2.2K_0402_5%
OPT@
I2CC_SCL
1
2
2
+3VS
+3VALW
QV13
S 2N7002KW_SOT323-3
OPT@
RV115
100K_0402_5%
@
+3VS
+1.8VS_AON
+1.8VS_AON
1
GPU_EVENT#_R
2
2
2
{16,44,49}
2
1
2
PCH_GPU_EVENT#
{19}
1V8_MAIN_EN_R
1V8_MAIN_EN_R
1
For GC6 20180827 ref Y540 change0927SF
G
RV317 1
@
2 0_0402_5%
1V8_MAIN_EN
UV12
2 0_0402_5%
2 0_0402_5%
@
1
2
2 0_0402_5%
3
IN B OUT Y
IN A
GND
Vcc
4
FBVDDQ_PWR_EN
1
RV1218
2 0_0402_5%
{30,67}
1
2
CV458
0.1U_0402_25V6
B
follow 330G-ICH NV review result SF0926
1
2
QV32A
LBSS138DW1T1G_SOT363-6
OPT@
RV1133
10K_0402_5%
@
+3VS
@
MC74VHC1G32DFT2G_SC70-5
S
G
FBVDDQ_PWR_EN
5
1
FB_GC6_EN_R
1
RV110
1.0VGS_PG
1
RV325
NVVDD_PWRGD
RV1123 1
QV32B
LBSS138DW1T1G_SOT363-6
OPT@
D
2
1
RV1235
0_0402_5%
@
S
{29}
D
5
Vgs(th)≤ 0.9V
PU AT EC SIDE, +3VS AND 4.7K
RV1129
10K_0402_5%
OPT@
1
RV318
1
QV8
LSI1012XT1G_SC-89-3
GC6@
3
3
RV1132
10K_0402_5%
OPT@
4
EC_SMB_DA2
Vgs(th)≤ 1.0V
2
+3VS
+3VALW
0_0402_5%
QV3A
PJT7838_SOT363-6
OPT@
B
{30,51,67}
2
2
GPU_EVENT#
1
6
D1
1V0_MAIN_EN
6
S1
1
0_0402_5%
@
RV330
10K_0402_1%
OPT@
2
1
BAT54AW_SOT323-3
OPT@
1
2
2
RV98
2
3
2
RV320
10K_0402_5%
OPT@
1
RV319
10K_0402_5%
OPT@
{16,44,49}
2
EC_SMB_CK2
RV59
0_0402_5%
RV331
8.2K_0402_1%
OPT@
1
2
1
3
D2
RV1238
0_0402_5%
@
G1
VGA_SMB_DA2
1 OPT@
RV4
10K_0402_5%
RV89
10K_0402_5%
@
DV7
2 0_0402_5% 2
NVVDD_PWRGD
2
5
S2
QV3B
PJT7838_SOT363-6
OPT@
2
RB751V-40_SOD323-2
2 0_0402_5%
+3VS
+3VS
G2
4
RV1135 1
RV1134 1
@
NVVDD_PWRGD
1
1
2
2
DV8
For Power ON {68}
1
OPT@
1V8_MAIN_EN
For GC6 Power OFF
+1.8VS_AON
VGA_SMB_CK2
PXS_PWREN
1V8_MAIN_EN_R
@
+1.8VS_AON
RV6
2.2K_0402_5%
OPT@
1
RV5
2.2K_0402_5%
OPT@
1
For Optimus Power OFF
RV1240
0_0402_5%
@
1
1
RV1138
0_0402_5%
1
RV1241
10K_0402_5%
@
RV1136
10K_0402_5%
@
1
2
2
2
2
1
PLT_RST_VGA#
+1.8VS_AON
CV1189
.1U_0402_10V6-K
OPT@
@
1V8_MAIN_EN
1
RV1231
@
2 0_0402_5%
1V8_MAIN_EN_R
2
+3VS
BAT5 4 AW
VF=0.32V @ IF=1mA
DV3
{67} 1.0VGS_PG
RV49
2
1 0_0402_5%
2
RV64
2
1 0_0402_5%
RV104
10K_0402_5%
OPT@
3
1
{67} VDDQPWROK
+3VS
1
VGA_PWRGD
{20,25}
BAT54AW_SOT323-3
2
OPT@
RV38
0_0402_5%
1
+3VS
+1.8VS_AON
2
CV58
.1U_0402_10V6-K
OPT@
2
2
1
RV216
10K_0402_5%
@
RV50
10K_0402_5%
OPT@
PLT_RST#
B
A
Y
4
VGA_RST#
RV44
1
2 0_0402_5%
PLT_RST_VGA#
PLT_RST_VGA#
{25}
MC74VHC1G09DFT2G_SC70-5
OPT@
1
3
RV217
100K_0402_5%
OPT@
RV324
100K_0402_5%
OPT@
2
1
2
1
1
2
{19} PXS_RST#
P
{18,37,41,42,45,49}
UV2
G
5
1
PLT_RST#
A
A
https://Dr-Bios.com
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/08/20
Deciphered Date
N17P_(4/6):GPIO
2018/09/20
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF
LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEP
ARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD P
ARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Size
Document Number
Custom
4
3
2
1
Rev
0.1
FG541/FG741
Friday, March 01, 2019
D a te :
5
She e t
28
of
69
5
4
3
2
5A Peak 8A
0.5A
1
2
1
2
1
2
1
2
1
2
+1.35VGS
2
1
1
CV88
10U_0603_6.3V6M
OPT@
2
CV87
10U_0603_6.3V6M
OPT@
CV86
10U_0603_6.3V6M
OPT@
CV94
10U_0603_6.3V6M
@
Under GPU(below 150mils)
2
2
1
1
Near GPU
CV93
22U_0603_6.3V6-M
CV91
22U_0603_6.3V6-M
CD@
1
1
1
1
1
1
2
2
2
2
2
2
2
1
2
1
2
2
1
1
1
1
2
2
2
2
CV213
1U_0402_6.3V6K
OPT18@
CV1477
1U_0402_6.3V6K
@
CV1478
1U_0402_6.3V6K
@
CV1479
1U_0402_6.3V6K
@
CV207
4.7U_0603_6.3V6K
OPT@
2
GPU
1
CV211
4.7U_0603_6.3V6K
OPT18@
near
1
CV203
4.7U_0603_6.3V6K
OPT@
2
GPU
1
OPT18@
1
2
2
1
D
N18P-FCBGA960_BGA960
1.8VS_AON Decouling Value
FP_FUSE_GPU
RV1200
1/16W_2.21K_1%_0402
OPT18@
1
1uf
0.1uf
Under
2
CV1104
2.2U_0402_6.3V6M
OPT18@
MLCC
CV205
N18
N17
location
CV206
1uf
0.1uf
Under
CV1475
N17P
N18P
FB_CAL_x_PD_VDDQ
40.2Ohm
40.2Ohm
FB_CAL_x_PU_GND
40.2Ohm
40.2Ohm
@
Under
@
@
Under
40.2Ohm
60.4Ohm
@
CV1476
CALIBRATION PIN
RV94
40.2ohm
60.4ohm
only for N18P
+1.8VS_AON
OPT@
1
2
CV97
22U_0603_6.3V6-M
OPT@
CD@
CV92
22U_0603_6.3V6-M
C
1
CV90
22U_0603_6.3V6-M
@
2
CD90
33P_0402_50V8J
RF_NS@
CD89
33P_0402_50V8J
RF_NS@
1
CV89
10U_0603_6.3V6M
CD@
CV95
10U_0603_6.3V6M
OPT@
Near GPU
2
FP_FUSE_SRC
1
FB_CAL_xTERM_GND
+1.35VGS
2
1
AG12
F1
2 0_0402_5%
FBVDDQ_SENSE_GND_GPU
RV91 1
2 0_0402_5%
J27
PROBE_FB_GND
FB_CAL_PD_VDDQ
RV90 1 OPT@
F2
FBVDDQ_SENSE
FBVDDQ_SENSE_GPU
FBCAL_VDDQ
H27 FBCAL_GND
FB_CAL_PU_GND
H25 FBCAL_TERM
FB_CAL_TERM_GND
1
RV92
1
RV93
1
RV94
@
FBVDD_VCC_SENSE
{67}
UV11
CV1103 1
2.2U_0402_6.3V6M
2
40.2_0402_1% OPT@
2
40.2_0402_1% OPT@
2
40.2_0402_1% OPT18@
2 OPT18@
A2
B1
+1.35VGS
VIN
GND
Vout
ON
A1
FP_FUSE_GPU
B2
GPIO26_FP_FUSE
AP22913CN4-7_X1-WLB0909-4
OPT18@
{28}
RV1198
10K_0402_5%
OPT18@
Place near balls
N18P-FCBGA960_BGA960
C
GPIO26_FP_FUSE
1
2
under
J8
K8
1V8_AON_1
1V8_AON_2
2
1
2
@ CV1491
1U_6.3V_K_X5R_0201
1
@ CV1490
1U_6.3V_K_X5R_0201
2
@ CV1489
1U_6.3V_K_X5R_0201
1
2
@ CV1488
1U_6.3V_K_X5R_0201
1
@ CV1487
1U_6.3V_K_X5R_0201
2
@ CV1486
1U_6.3V_K_X5R_0201
1
OPT@
CV865
1U_6.3V_M_X5R_0201
2
CD@
CV868
1U_6.3V_M_X5R_0201
1
OPT@
CV864
1U_6.3V_M_X5R_0201
2
@ CV862
1U_6.3V_K_X5R_0201
OPT@
CV863
1U_6.3V_M_X5R_0201
1
@ CV873
1U_6.3V_K_X5R_0201
Partition B Under GPU(below 150mils)
FBVDDQ_01
FBVDDQ_02
FBVDDQ_03
FBVDDQ_04
FBVDDQ_05
FBVDDQ_06
FBVDDQ_07
FBVDDQ_08
FBVDDQ_09
FBVDDQ_10
FBVDDQ_11
FBVDDQ_12
FBVDDQ_13
FBVDDQ_14
FBVDDQ_15
FBVDDQ_16
FBVDDQ_17
FBVDDQ_18
FBVDDQ_19
FBVDDQ_20
FBVDDQ_21
FBVDDQ_22
FBVDDQ_23
FBVDDQ_24
FBVDDQ_25
FBVDDQ_26
FBVDDQ_27
FBVDDQ_28
FBVDDQ_29
FBVDDQ_30
FBVDDQ_31
FBVDDQ_32
FBVDDQ_33
FBVDDQ_34
FBVDDQ_35
FBVDDQ_36
FBVDDQ_37
FBVDDQ_38
FBVDDQ_39
FBVDDQ_40
FBVDDQ_41
FBVDDQ_42
FBVDDQ_43
FBVDDQ_44
CV206
1U_6.3V_M_X5R_0201
2
AA27
AA30
AB27
AB33
AC27
AD27
AE27
AF27
AG27
B13
B16
B19
E13
E16
E19
H10
H11
H12
H13
H14
H15
H16
H18
H19
H20
H21
H22
H23
H24
H8
H9
L27
M27
N27
P27
R27
T27
T30
T33
V27
W27
W30
W33
Y27
CV1476
1U_6.3V_K_X5R_0201
OPT18@
@
CV205
1U_6.3V_M_X5R_0201
2
1
17/17 1V8_AON
CV1475
1U_6.3V_K_X5R_0201
@
2
1
@ CV102
1U_6.3V_K_X5R_0201
2
@ CV101
1U_6.3V_K_X5R_0201
2
1
@ CV100
1U_6.3V_K_X5R_0201
2
1
@
CV99
1U_6.3V_K_X5R_0201
2
1
@ CV113
1U_6.3V_K_X5R_0201
1
@ CV112
1U_6.3V_K_X5R_0201
1
OPT@
2
CV115
1U_6.3V_M_X5R_0201
1
OPT@
2
CV106
1U_6.3V_M_X5R_0201
2
1
OPT@
1
CV105
1U_6.3V_M_X5R_0201
2
@ CV103
1U_6.3V_K_X5R_0201
OPT@
CV104
1U_6.3V_M_X5R_0201
@ CV114
1U_6.3V_K_X5R_0201
2
D
1
+1.8VS_AON
+1.8VS_AON
CV208
1U_0402_6.3V6K
OPT@
14/17 FBVDDQ
Partition A Under GPU(below 150mils)
1
UV1I
CV204
1U_0603_10V6K
OPT@
UV1H
for N18P reserve 0928sf
1
Cost down list:
1U 4Pcs
2
+1.35VGS
1
1.8V Total 1A (AON+MAIN)
+1.35VGS
FBVDD_VCC_SENSE
RV310
1
@
2 2_0402_5%
PLACE MIDWAY BETWEEN FBA AND FBB
UV1J
4/17 NC
+1.8VS_VGA
B
OPT17@ 1
RV1225
AG26,AJ28 NC pin,
only for under GPU
1.8VS_VGA
2
0_0402_5%
layout
AK9
AL10
AL11
AL9
AN2
AP8
C15
D19
D20
under GPU
D23
D26
L8 +1.8VS_VGA_R
M8
V32
U2
1
U1
OPT17@
CV667
0.1U_6.3V_K_X7R_0201
2
+1.8VS_VGA
1
NC_1
NC_20
NC_2
NC_21
NC_3
NC_22
NC_4
NC_23
NC_5
NC_24
NC_6
NC_25
NC_7
NC_26
NC_8
NC_27
NC_9
NC_28
NC_10
NC_29
NC_11
NC_30
NC_12
NC_31
NC_13
NC_32
NC_14
NC_33
NC_15 RSVD_GNDS_SENSE
NC_16 RSVD_VDDS_SENSE
NC_17
NC_18
NC_19
OPT17@
RV1226
1/10W_0_+-5%_0603
B
2
AC6
AD4
AD5
AE3
AE4
AF1
AF2
AF3
AF4
AF5
AG1
AG26
AG7
AH11
AJ26
AJ28
AJ4
AJ5
AK26
1
OPT17@
CV1507
0.1U_6.3V_K_X7R_0201
2
trace
2A
QV16
1
3
4
2
D
S QV9B
5
1
2 0_0402_5%
RV1285 1
2 0_0402_5%
2
2 PR5
0_0402_5%
1
2
2
@
@
RV1284
2
{28,68} NVVDD_EN
1 0_0402_5%
1
1
@
1
1
RV84
100K_0402_5%
@
2
3 PR4
0_0402_5%
1
2
CV38
0.1U_0402_25V6
@
G
PD3
S
QV9A
OPT@
1
1
2
CV73
RV85
0.01U_0402_25V7K 47_0603_5%
@
OPT@
1 CV74
10U_0603_6.3V6M
OPT@
2
2
GPU
1
2
2
1
CV75
0.1U_0402_25V6
OPT@
D
+1.8VGS_PWR_EN# 2
G
2
OPT@
1
2
RV83
1K_0402_5%
OPT@
RV47
210K_0402_1%
OPT@
OPT@
3
RV58
D
LBSS138DW1T1G_SOT363-6
{28} 1V8_MAIN_EN_R
@
LBSS138DW1T1G_SOT363-6
A
6
G
1
CV72
0.1U_0402_25V6
@
near
1
1
1
Vg=16.4V@AC
Vg=7.38V@Battery
RV86
47K_0402_5%
OPT@
+1.8VGS_PWR_EN#
4
2
S1
S2
S3
D
G
1
+5VALW
@
5
+1.8VS_VGA
N18P-FCBGA960_BGA960
2
47K_0402_5%
OPT@
1
2
3
CV1505
4.7U_0603_6.3V6K
OPT17@
2
AON7408L_DFN8-5
RV42
CV1506
1U_0402_6.3V6K
OPT17@
+1.8VS_VGA
+1.8VS_AON
V20B+
AON7408L
Vds=30V
Ids=15A
Rdson=28mohm@Vgs=4.66V
=20mohm@Vgs=6V
=18mohm@Vgs & gt; 10V
Vgs=+-20V
Vgsth=1~3V
S
QV20
2N7002KW_SOT323-3
OPT@
A
+1.8V_MAIN discharger circuit
LBAT54SWT1G_SOT323-3
@
https://Dr-Bios.com
Issued Date
5
4
Title
LC Future Center Secret Data
Security Classification
Reserve PD3/PR4/PR5/CV38 for NV sequence requirement
2015/08/20
Deciphered Date
3
2
N17P_(5/6):PWR
2018/09/20
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Size
Document Number
Custom
Date:
Re v
0.1
FG541/FG741
Wednesday, February 27, 2019
1
Sheet
29
of
69
5
4
3
BOTH GP107 AND N18P-G5 NEED
NC AF30,AF32,AK31,AM34,E34,H30,M30,M34,
A30,A9,B2,B23,D22,D28,D9,E4
CV1157
22U_0603_6.3V6-M
CD@
2
CV1158
22U_0603_6.3V6-M
OPT@
2
1
CD93
33P_0402_50V8J
RF_NS@
2
1
2
D
CV1159
22U_0603_6.3V6-M
OPT@
1
2
CV1156
22U_0603_6.3V6-M
CD@
1
2
CV1154
22U_0603_6.3V6-M
OPT@
1
2
CD94
33P_0402_50V8J
RF_NS@
CV1149
22U_0603_6.3V6-M
OPT18@
CV149
22U_0603_6.3V6-M
OPT18@
CV1148
22U_0603_6.3V6-M
OPT18@
CV134
22U_0603_6.3V6-M
OPT18@
CV137
22U_0603_6.3V6-M
OPT18@
1
2
CV1155
22U_0603_6.3V6-M
CD@
CV1150
22U_0603_6.3V6-M
OPT@
2
1
CV1152
22U_0603_6.3V6-M
OPT@
CV1119
1U_0201_6.3V6K
CV1118
1U_0201_6.3V6K
CD@
+
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
CV437
10U_0603_6.3V6M
CD@
2
CV1120
10U_0603_6.3V6M
OPT@
2
CV1121
10U_0603_6.3V6M
OPT@
CV1122
10U_0603_6.3V6M
OPT@
2
2
CV1132
10U_0603_6.3V6M
CD@
CV1133
10U_0603_6.3V6M
OPT@
CV1134
10U_0603_6.3V6M
OPT@
CV1135
10U_0603_6.3V6M
OPT@
CV1145
10U_0603_6.3V6M
OPT@
CV1146
10U_0603_6.3V6M
CD@
CV1519
1U_0201_6.3V6K
1
2
CV436
10U_0603_6.3V6M
OPT@
CV1142
10U_0603_6.3V6M
CD@
2
1
+
2
CV1131
10U_0603_6.3V6M
OPT@
CV1141
10U_0603_6.3V6M
OPT@
1
1
1
CV1144
10U_0603_6.3V6M
OPT@
CV1129
10U_0603_6.3V6M
CD@
2
CV1140
10U_0603_6.3V6M
CD@
@
CV434
10U_0603_6.3V6M
OPT@
CV1128
10U_0603_6.3V6M
CD@
2
2
2
CV435
10U_0603_6.3V6M
CD@
CV433
10U_0603_6.3V6M
CD@
CV1127
10U_0603_6.3V6M
OPT@
2
1
2
2
CV1130
10U_0603_6.3V6M
CD@
CV429
10U_0603_6.3V6M
OPT18@
2
1
1
1
2
2
CV1117
1U_0201_6.3V6K
OPT@
CV1116
1U_0201_6.3V6K
OPT@
1
2
CV1143
10U_0603_6.3V6M
OPT@
CV428
10U_0603_6.3V6M
OPT18@
2
2
1
1
2
2
2
2
1
CV1115
1U_0201_6.3V6K
OPT@
OPT@
CV1515
1U_0201_6.3V6K
CV1514
1U_0201_6.3V6K
@
2
1
1
1
1
2
CV1126
10U_0603_6.3V6M
OPT@
2
2
CV1139
10U_0603_6.3V6M
OPT@
2
2
CV1125
10U_0603_6.3V6M
OPT@
2
CV1513
1U_0201_6.3V6K
@
CV1512
1U_0201_6.3V6K
@
2
CV1511
1U_0201_6.3V6K
@
CV155
4.7U_0603_6.3V6K
OPT17@
2
CV1510
1U_0201_6.3V6K
@
CV1509
1U_0201_6.3V6K
@
2
2
2
CV1518
1U_0201_6.3V6K
@
1
2
2
CV1517
1U_0201_6.3V6K
@
1
1
CV146
1U_0201_6.3V6K
1
2
2
CV1114
1U_0201_6.3V6K
OPT@
CV145
1U_0201_6.3V6K
CD@
1
2
CV1516
1U_0201_6.3V6K
@
CV144
1U_0201_6.3V6K
OPT@
1
CV143
1U_0201_6.3V6K
OPT@
1
CV142
1U_0201_6.3V6K
CD@
1
CV141
1U_0201_6.3V6K
OPT@
1
1
1
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
XVDD_28
XVDD_29
XVDD_30
XVDD_31
XVDD_32
XVDD_33
XVDD_34
XVDD_35
1
1
2
2
W8
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
XVDD_19
XVDD_20
XVDD_21
XVDD_22
XVDD_23
XVDD_24
XVDD_25
XVDD_26
XVDD_27
1
1
2
V5
V6
V7
V8
W2
W3
W4
W5
W7
XVDD_10
XVDD_11
XVDD_12
XVDD_13
XVDD_14
XVDD_15
XVDD_16
XVDD_17
XVDD_18
1
1
U4
U5
U6
U7
U8
V1
V2
V3
V4
XVDD_01
XVDD_02
XVDD_03
XVDD_04
XVDD_05
XVDD_06
XVDD_07
XVDD_08
XVDD_09
CV140
1U_0201_6.3V6K
OPT@
1
CHANNELS
@
CV1422
330U_B2_2.5VM_R9M
OPT17@
CV83
330U_B2_2.5VM_R9M
CONFIGURABLE
POWE R
CV1151
22U_0603_6.3V6-M
OPT@
P12
P14
P16
P19
P21
P23
R11
R13
R15
R17
R18
R20
R22
R24
T12
T14
T16
T19
T21
T23
U11
U13
U15
U17
U18
U20
U22
U24
V11
V13
V15
V17
V18
V20
V22
V24
W12
W14
W16
W19
W21
W23
Y11
Y13
Y15
Y17
Y18
Y20
Y22
Y24
CV1124
10U_0603_6.3V6M
OPT@
VDD_51
VDD_52
VDD_53
VDD_54
VDD_55
VDD_56
VDD_57
VDD_58
VDD_59
VDD_60
VDD_61
VDD_62
VDD_63
VDD_64
VDD_65
VDD_66
VDD_67
VDD_68
VDD_69
VDD_70
VDD_71
VDD_72
VDD_73
VDD_74
VDD_75
VDD_76
VDD_77
VDD_78
VDD_79
VDD_80
VDD_81
VDD_82
VDD_83
VDD_84
VDD_85
VDD_86
VDD_87
VDD_88
VDD_89
VDD_90
VDD_91
VDD_92
VDD_93
VDD_94
VDD_95
VDD_96
VDD_97
VDD_98
VDD_99
VDD_100
CV1138
10U_0603_6.3V6M
CD@
VDD_01
VDD_02
VDD_03
VDD_04
VDD_05
VDD_06
VDD_07
VDD_08
VDD_09
VDD_10
VDD_11
VDD_12
VDD_13
VDD_14
VDD_15
VDD_16
VDD_17
VDD_18
VDD_19
VDD_20
VDD_21
VDD_22
VDD_23
VDD_24
VDD_25
VDD_26
VDD_27
VDD_28
VDD_29
VDD_30
VDD_31
VDD_32
VDD_33
VDD_34
VDD_35
VDD_36
VDD_37
VDD_38
VDD_39
VDD_40
VDD_41
VDD_42
VDD_43
VDD_44
VDD_45
VDD_46
VDD_47
VDD_48
VDD_49
VDD_50
CD@
AA12
AA14
AA16
AA19
AA21
AA23
AB11
AB13
AB15
AB17
AB18
AB20
AB22
AB24
AC12
AC14
AC16
AC19
AC21
AC23
AD11
AD13
AD15
AD17
AD18
AD20
AD22
AD24
L11
L13
L15
L17
L18
L20
L22
L24
M12
M14
M16
M19
M21
M23
N11
N13
N15
N17
N18
N20
N22
N24
CV1137
10U_0603_6.3V6M
CD@
GND_OPT_1
GND_OPT_2
P18
P20
P22
P24
R12
R14
R16
R19
R21
R23
T11
T13
T15
T17
T18
T2
T20
T22
T24
T28
T32
T5
T7
U12
U14
U16
U19
U21
U23
V12
V14
V16
V19
V21
V23
W11
W13
W15
W17
W18
W20
W22
W24
W28
Y12
Y14
Y16
Y19
Y21
CV139
1U_0201_6.3V6K
OPT@
GND_190
GND_191
GND_192
GND_193
GND_194
GND_195
GND_196
GND_197
GND_198
GND_199
GND_200
GND_201
GND_202
GND_203
GND_204
GND_205
GND_206
GND_207
GND_208
GND_209
GND_210
GND_211
GND_212
GND_213
GND_214
GND_215
GND_216
GND_217
GND_218
GND_219
GND_220
GND_221
GND_222
GND_223
GND_224
GND_225
GND_226
GND_227
GND_228
GND_229
GND_230
GND_231
GND_232
GND_233
GND_234
GND_235
GND_236
GND_237
GND_238
@
GND_141
GND_142
GND_143
GND_144
GND_145
GND_146
GND_147
GND_148
GND_149
GND_150
GND_151
GND_152
GND_153
GND_154
GND_155
GND_156
GND_157
GND_158
GND_159
GND_160
GND_161
GND_162
GND_163
GND_164
GND_165
GND_166
GND_167
GND_168
GND_169
GND_239
GND_170
GND_171
GND_172
GND_173
GND_174
GND_175
GND_176
GND_177
GND_178
GND_179
GND_180
GND_181
GND_182
GND_183
GND_184
GND_185
GND_186
GND_187
GND_188
GND_189
CV1508
1U_0201_6.3V6K
@
G25
G28
G3
G30
G32
G33
G5
G7
H30
K2
K28
K30
K32
K33
K5
K7
L12
L14
L16
L19
L21
L23
M11
M13
M15
M17
M18
M20
M22
Y23
M24
M30
M34
N12
N14
N16
N19
N2
N21
N23
N28
N30
N32
N33
N5
N7
P11
P13
P15
P17
CV1153
22U_0603_6.3V6-M
OPT@
NVVDD
13/17 NVVDD
CV154
4.7U_0603_6.3V6K
OPT17@
GND_071
GND_072
GND_073
GND_074
GND_075
GND_076
GND_077
GND_078
GND_079
GND_080
GND_081
GND_082
GND_083
GND_084
GND_085
GND_086
GND_087
GND_088
GND_089
GND_090
GND_091
GND_092
GND_093
GND_094
GND_095
GND_096
GND_097
GND_098
GND_099
GND_100
GND_101
GND_102
GND_103
GND_104
GND_105
GND_106
GND_107
GND_108
GND_109
GND_110
GND_111
GND_112
GND_113
GND_114
GND_115
GND_116
GND_117
GND_118
GND_119
GND_120
GND_121
GND_122
GND_123
GND_124
GND_125
GND_126
GND_127
GND_128
GND_129
GND_130
GND_131
GND_132
GND_133
GND_134
GND_135
GND_136
GND_137
GND_138
GND_139
GND_140
NEAR GPU
POSCAP for N17
UNDER GPU
9/17 XVDD
CV1123
10U_0603_6.3V6M
OPT@
C
GND_001
GND_002
GND_003
GND_004
GND_005
GND_006
GND_007
GND_008
GND_009
GND_010
GND_011
GND_012
GND_013
GND_014
GND_015
GND_016
GND_017
GND_018
GND_019
GND_020
GND_021
GND_022
GND_023
GND_024
GND_025
GND_026
GND_027
GND_028
GND_029
GND_030
GND_031
GND_032
GND_033
GND_034
GND_035
GND_036
GND_037
GND_038
GND_039
GND_040
GND_041
GND_042
GND_043
GND_044
GND_045
GND_046
GND_047
GND_048
GND_049
GND_050
GND_051
GND_052
GND_053
GND_054
GND_055
GND_056
GND_057
GND_058
GND_059
GND_060
GND_061
GND_062
GND_063
GND_064
GND_065
GND_066
GND_067
GND_068
GND_069
GND_070
UV1E
CV1136
10U_0603_6.3V6M
OPT@
15/17 GND_1/2
D
NVVDD
UV1G
16/17 GND_2/2
AL18
AL2
AL20
AL21
AL23
AL24
AL26
AL28
AL30
AL32
AL33
AL5
AM13
AM16
AM19
AM22
AM25
AM34
AN1
AN10
AN13
AN16
AN19
AN22
AN25
AN30
AN34
AN4
AN7
AP2
AP33
B1
B10
B2
B22
B23
B25
B28
B31
B34
B4
B7
C10
C13
C19
C22
C25
C28
C7
D2
D22
D28
D31
D33
D9
E10
E22
E25
E34
E4
E5
E7
F28
F7
G10
G13
G16
G19
G2
G22
1
NVVDD
NVVDD
NVVDD
UV1F
UV1D
AG11
A2
A30
A33
A9
AA11
AA13
AA15
AA17
AA18
AA20
AA22
AA24
AB12
AB14
AB16
AB19
AB2
AB21
AB23
AB28
AB30
AB32
AB5
AB7
AC11
AC13
AC15
AC17
AC18
AC20
AC22
AC24
AD12
AD14
AD16
AD19
AD21
AD23
AE2
AE28
AE30
AE32
AE33
AE5
AE7
AF30
AF32
AH10
AH13
AH16
AH19
AH2
AH22
AH24
AH28
AH29
AH30
AH32
AH33
AH5
AH7
AJ7
AK10
AK31
AK7
AL12
AL14
AL15
AL17
2
1
2
1
2
1
1
1
1
2
C
1
C16
W32
N18P-FCBGA960_BGA960
Optional CMD GNDs (2)
1
1
1
1
1
1
1
1
1
1
2
1
2
1
2
NC for 4-Lyr cards
N18P-FCBGA960_BGA960
1
2
trace width: 16mils
differential voltage sensing.
differential signal routing.
N18P-FCBGA960_BGA960
VDD_SENSE
GND_SENSE
L4
NVVDD_VDD_SENSE
NVVDD_VDD_SENSE
NVVDD_VSS_SENSE
NVVDD_VSS_SENSE
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
{68}
L5
1
{68}
N18P-FCBGA960_BGA960
B
B
Add RV332 for NVVDDS discharge Hai Y520 SVT
Change NVVDDS & +1.0VGS discharge circuit
HLZ SIV 0725
NVVDD
Change QV6/RV48/QV4/RV62 from REV@ to ns Hai Y520 SVT
+1.0VGS
OPT@
15_0805_1%
RV326 1
OPT@
15_0805_1%
RV327 1
OPT@
15_0805_1%
RV63 1
OPT@
15_0805_1%
RV328 1
OPT@
15_0805_1%
RV329 1
2
2
2
2
2
1
3
2
1
1
D
6
S
OPT@
2
D
QV6A
2N7002KDWH_SOT363-6
G
@
QV12
A
S
1
S
{28,67} FBVDDQ_PWR_EN
3
S
QV29
AO3402_SOT-23-3
G
4
D
2
G
3
LBSS139WT1G_SC70-3
S
QV11
QV6B
2N7002KDWH_SOT363-6
G
@
2
1
3
G
OPT@
D
2
D
5
2
A
2
OPT@
15_0805_1%
RV45 1
2
RV60
47K_0402_5%
OPT@
{28,51,67} 1V0_MAIN_EN
RV61
470_0603_5%
@
RV48
47K_0402_5%
@
1
+5VALW
1
OPT@
15_0805_1%
RV332 1
2
+1.35VGS
+5VALW
AO3402_SOT-23-3
OPT@
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/08/20
Deciphered Date
N17P_(6/6):PWR,VSS
2018/09/20
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Size
Document
Custom
Date:
5
4
3
https://Dr-Bios.com
2
Number
Rev
0.1
FG541/FG741
Tuesday, January 22, 2019
1
Sheet
30
of
69
5
4
3
2
1
Memory Partition A - Lower 64 bits(MF=0)
UV4
MF=0
1
1
QV26
LSI1012XT1G_SC-89-3
OPT@
2
1
2
CV315
1U_0402_6.3V6K
CD@
CV313
1U_0402_6.3V6K
CD@
1
1
CV314
1U_0402_6.3V6K
OPT@
2
2
GDDR5
Mode H - Mirror Mode Mapping
1
2
1
2
1
2
1
2
1
2
1
1
2
A2_BA0
FBx_CMD3
A4_BA2
FBx_CMD4
1
A3_BA3
FBx_CMD2
2
CV327
1U_0402_6.3V6K
OPT@
1
32..63
CS#
FBx_CMD1
A5_BA1
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
A1_A9
RAS#
RST#
FBx_CMD14
CKE#
FBx_CMD15
1
A0_A10
FBx_CMD13
2
CV1536
1U_0402_6.3V6K
@
1
2
CV1530
1U_0402_6.3V6K
@
1
2
A12_RFU
FBx_CMD11
FBx_CMD12
2
ABI#
FBx_CMD10
UNDER DRAM
A6_A11
FBx_CMD9
+1.35VGS
A7_A8
FBx_CMD8
CLOSE TO DRAM
WE#
FBx_CMD6
FBx_CMD7
AROUND DRAM
FBx_CMD5
CAS#
B
FBx_CMD16
1
2
1
2
1
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
A5_BA1
FBx_CMD21
WE#
FBx_CMD22
1
A4_BA2
FBx_CMD20
2
A2_BA0
FBx_CMD19
2
A3_BA3
FBx_CMD18
2
CS#
FBx_CMD17
UNDER DRAM
A7_A8
FBx_CMD23
A6_A11
FBx_CMD24
A0_A10
FBx_CMD27
A1_A9
FBx_CMD28
RAS#
RST#
FBx_CMD30
CKE#
FBx_CMD31
CV178
820P_0402_25V7
OPT@
A12_RFU
FBx_CMD26
{32}
ABI#
FBx_CMD25
+FBA_VREFC0
RV138
1.33K_0402_1%
OPT@
0..31
FBx_CMD0
2
C
DATA Bus
Address
CLOSE TO DRAM
AROUND DRAM
16 mil
2
1
2
2
3
{28} MEM_VREF
1
H5GC2H24BFR-T2C_BGA170
+FBA_VREFC0
A
2
X76@
RV136
549_0402_1%
OPT@
2
1
FBx_CMD29
+1.35VGS
1
RV137
931_0402_1%
OPT@
2
CV1537
1U_0402_6.3V6K
@
SGRAM GDDR5
1
CV1535
1U_0402_6.3V6K
@
170-BALL
A1
C1
E1
N1
R1
U1
H2
K2
A3
C3
E3
N3
R3
U3
C4
R4
F5
M5
F10
M10
C11
R11
A12
C12
E12
N12
R12
U12
H13
K13
A14
C14
E14
N14
R14
U14
2
1
CV1528
1U_0402_6.3V6K
@
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10
VSSQ11
VSSQ12
VSSQ13
VSSQ14
VSSQ15
VSSQ16
VSSQ17
VSSQ18
VSSQ19
VSSQ20
VSSQ21
VSSQ22
VSSQ23
VSSQ24
VSSQ25
VSSQ26
VSSQ27
VSSQ28
VSSQ29
VSSQ30
VSSQ31
VSSQ32
VSSQ33
VSSQ34
VSSQ35
VSSQ36
2
CV1529
1U_0402_6.3V6K
@
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
1
CV326
1U_0402_6.3V6K
@
RESET#
2
CV325
1U_0402_6.3V6K
OPT@
VREFD1
VREFD2
VREFC
UV4 SIDE
CV324
1U_0402_6.3V6K
CD@
WCK01#
WCK01
+1.35VGS
CV312
10U_0603_6.3V6M
OPT@
WCK23#
WCK23
WCK23#
WCK23
Cost down list:
22U 2Pcs
CV323
1U_0402_6.3V6K
@
WCK01#
WCK01
2A Peak 3A
CV311
10U_0603_6.3V6M
OPT@
CAS#
WE#
RAS#
CS#
B1
D1
F1
M1
P1
T1
G2
L2
B3
D3
F3
H3
K3
M3
P3
T3
E5
N5
E10
N10
B12
D12
F12
H12
K12
M12
P12
T12
G13
L13
B14
D14
F14
M14
P14
T14
CV1532
1U_0402_6.3V6K
@
B
ABI#
RAS#
CS#
CAS#
WE#
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18
VDDQ19
VDDQ20
VDDQ21
VDDQ22
VDDQ23
VDDQ24
VDDQ25
VDDQ26
VDDQ27
VDDQ28
VDDQ29
VDDQ30
VDDQ31
VDDQ32
VDDQ33
VDDQ34
VDDQ35
VDDQ36
CV1533
1U_0402_6.3V6K
OPT@
G1
L1
G4
L4
C5
R5
C10
R10
D11
G11
L11
P11
G14
L14
+1.35VGS
MF
SEN
ZQ
CV1531
1U_0402_6.3V6K
@
H1
K1
B5
G5
L5
T5
B10
D10
G10
L10
P10
T10
H14
K14
DQ24-DQ31/EDC3/DBI3#/WCK1
CV1534
1U_0402_6.3V6K
@
+1.35VGS
J2
BYTE3
CV322
1U_0402_6.3V6K
OPT@
FBA_RST#_L
{27} FBA_RST#_L
A10
U10
J14
{27}
CV1522
1U_0402_6.3V6K
@
+FBA_VREFC0
FBA_D[24..31]
CV1520
1U_0402_6.3V6K
@
2
DQ16-DQ23/EDC2/DBI2#/WCK1
CV1527
1U_0402_6.3V6K
@
P5
P4
BYTE2
CV1521
1U_0402_6.3V6K
@
1
D5
D4
FBA_WCK1_N
FBA_WCK1
{27} FBA_WCK1_N
{27} FBA_WCK1
{27}
CV310
10U_0603_6.3V6M
OPT@
FBA_WCK0_N
FBA_WCK0
{27} FBA_WCK0_N
{27} FBA_WCK0
FBA_D[16..23]
CV321
1U_0402_6.3V6K
OPT@
2
D
CV309
10U_0603_6.3V6M
OPT@
1
RV135
40.2_0402_1%
OPT@
CV177
0.01U_0402_25V7K
OPT@
FBA_CLK0#
2
C
DQ8-DQ15/EDC1/DBI1#/WCK0
CV1524
1U_0402_6.3V6K
@
2
BYTE1
CV1523
1U_0402_6.3V6K
@
1
RV133
40.2_0402_1%
OPT@
RV134
80.6_0402_1%
@
J4
G3
G12
L3
L12
DQ0-DQ7/EDC0/DBI0#/WCK0
CV1525
1U_0402_6.3V6K
@
1
FBA_CLK0
FBA_ABI#_L
FBA_RAS#_L
FBA_CS#_L
FBA_CAS#_L
FBA_WE#_L
{27} FBA_ABI#_L
{27} FBA_RAS#_L
{27} FBA_CS#_L
{27} FBA_CAS#_L
{27} FBA_WE#_L
VPP/NC1
VPP/NC2
{27}
BYTE0
CV1526
1U_0402_6.3V6K
CD@
Follow DG
OPT@
J1
J10
J13
A10/A0
A11/A6
A8/A7
A9/A1
FBA_D[8..15]
{27}
CV352
1U_0402_6.3V6K
OPT@
@
2 0_0402_5%
2 0_0402_5%
1 121_0402_1%
A8/A7
A9/A1
A10/A0
A11/A6
A12/RFU/NC
FBA_D[0..7]
CV356
1U_0402_6.3V6K
OPT@
1
1
2
BA2/A4
BA3/A3
BA0/A2
BA1/A5
FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
CV308
10U_0603_6.3V6M
CD@
RV127
RV129
RV131
BA0/A2
BA1/A5
BA2/A4
BA3/A3
A4
A2
B4
B2
E4
E2
F4
F2
A11
A13
B11
B13
E11
E13
F11
F13
U11
U13
T11
T13
N11
N13
M11
M13
U4
U2
T4
T2
N4
N2
M4
M2
CV351
1U_0402_6.3V6K
OPT@
A5
U5
change from 1k to 0OHM 0928sf
@
CK
CK#
CKE#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
CV350
1U_0402_6.3V6K
OPT@
K4
H5
H4
K5
J5
DBI3#
DBI2#
DBI1#
DBI0#
MF=0
CV355
1U_0402_6.3V6K
CD@
FBA_MA7_MA8_L
FBA_MA1_MA9_L
FBA_MA0_MA10_L
FBA_MA6_MA11_L
FBA_MA12_RFU_L
FBA_MA7_MA8_L
FBA_MA1_MA9_L
FBA_MA0_MA10_L
FBA_MA6_MA11_L
FBA_MA12_RFU_L
DBI0#
DBI1#
DBI2#
DBI3#
MF=1
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CV354
1U_0402_6.3V6K
OPT@
H11
K10
K11
H10
EDC3
EDC2
EDC1
EDC0
CV188
10U_0603_6.3V6M
OPT@
FBA_MA2_BA0_L
FBA_MA5_BA1_L
FBA_MA4_BA2_L
FBA_MA3_BA3_L
{27} FBA_MA2_BA0_L
{27} FBA_MA5_BA1_L
{27} FBA_MA4_BA2_L
{27} FBA_MA3_BA3_L
J12
J11
J3
MF=1
EDC0
EDC1
EDC2
EDC3
2
1
CV316
22U_0603_6.3V6-M
CD@
2
1
CV317
22U_0603_6.3V6-M
@
2
1
CV318
22U_0603_6.3V6-M
@
2
1
CV319
22U_0603_6.3V6-M
OPT@
2
1
CV320
22U_0603_6.3V6-M
OPT@
D2
D13
P13
P2
FBA_CLK0
FBA_CLK0#
FBA_CKE_L
{27} FBA_CLK0
{27} FBA_CLK0#
{27} FBA_CKE_L
{27}
{27}
{27}
{27}
{27}
FBA_DBI0#
FBA_DBI1#
FBA_DBI2#
FBA_DBI3#
FBA_DBI0#
FBA_DBI1#
FBA_DBI2#
FBA_DBI3#
C2
C13
R13
R2
CV357
1U_0402_6.3V6K
OPT@
{27}
{27}
{27}
{27}
D
FBA_EDC0
FBA_EDC1
FBA_EDC2
FBA_EDC3
FBA_EDC0
FBA_EDC1
FBA_EDC2
FBA_EDC3
CV358
1U_0402_6.3V6K
CD@
{27}
{27}
{27}
{27}
CAS#
A
Vgs(th)≤ 0.9V
Issued Date
Title
LC Future Center Secret Data
Security Classification
Deciphered Date
2015/08/20
N17P_GDDR5_A Lower
2018/09/20
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Size
Document Number
Custom
Date:
5
4
3
https://Dr-Bios.com
2
Rev
0.1
FG541/FG741
Tuesday, February 26, 2019
1
Sheet
31
of
69
5
4
3
2
1
Memory Partition A- Upper 64 bits(MF=0)
UV6
MF=0
A8/A7
A9/A1
A10/A0
A11/A6
A12/RFU/NC
{27}
FBA_D[56..63]
BYTE6
DQ48-DQ55/EDC6/DBI6#/WCK3
BYTE7
FBA_D[48..55]
DQ56-DQ63/EDC7/DBI7#/WCK3
{27}
1
2
1
2
1
2
1
2
1
A3_BA3
FBx_CMD2
A2_BA0
FBx_CMD3
A4_BA2
FBx_CMD4
1
A5_BA1
FBx_CMD5
A6_A11
FBx_CMD8
ABI#
FBx_CMD9
A12_RFU
FBx_CMD10
A0_A10
FBx_CMD11
A1_A9
FBx_CMD12
RAS#
FBx_CMD13
RST#
FBx_CMD14
CKE#
FBx_CMD15
CAS#
CLOSE TO DRAM
2
1
AROUND DRAM
2
1
2
1
2
1
2
1
2
1
2
CV328
1U_0402_6.3V6K
OPT@
A1
C1
E1
N1
R1
U1
H2
K2
A3
C3
E3
N3
R3
U3
C4
R4
F5
M5
F10
M10
C11
R11
A12
C12
E12
N12
R12
U12
H13
K13
A14
C14
E14
N14
R14
U14
A7_A8
FBx_CMD7
32..63
WE#
FBx_CMD6
AROUND DRAM
C
CS#
FBx_CMD1
2
CV337
1U_0402_6.3V6K
OPT@
2
CV336
1U_0402_6.3V6K
OPT@
1
CV335
1U_0402_6.3V6K
OPT@
2
1
CV333
10U_0603_6.3V6M
OPT@
2
CV334
10U_0603_6.3V6M
OPT@
1
0..31
FBx_CMD0
1
CLOSE TO DRAM
FBx_CMD16
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
A4_BA2
FBx_CMD20
A5_BA1
FBx_CMD21
WE#
FBx_CMD22
1
A2_BA0
FBx_CMD19
2
A3_BA3
FBx_CMD18
UNDER DRAM
CS#
FBx_CMD17
+1.35VGS
CV1554
1U_0402_6.3V6K
@
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
2
Address
CV1548
1U_0402_6.3V6K
@
G1
L1
G4
L4
C5
R5
C10
R10
D11
G11
L11
P11
G14
L14
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10
VSSQ11
VSSQ12
VSSQ13
VSSQ14
VSSQ15
VSSQ16
VSSQ17
VSSQ18
VSSQ19
VSSQ20
VSSQ21
VSSQ22
VSSQ23
VSSQ24
VSSQ25
VSSQ26
VSSQ27
VSSQ28
VSSQ29
VSSQ30
VSSQ31
VSSQ32
VSSQ33
VSSQ34
VSSQ35
VSSQ36
UV6 SIDE
CV348
1U_0402_6.3V6K
CD@
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
DATA Bus
+1.35VGS
CV347
1U_0402_6.3V6K
OPT@
H1
K1
B5
G5
L5
T5
B10
D10
G10
L10
P10
T10
H14
K14
GDDR5
Mode H - Mirror Mode Mapping
CV346
1U_0402_6.3V6K
OPT@
RESET#
Cost down list:
22U 2Pcs
CV344
1U_0402_6.3V6K
CD@
J2
2A Peak 3A
CV332
10U_0603_6.3V6M
OPT@
VREFD1
VREFD2
VREFC
B1
D1
F1
M1
P1
T1
G2
L2
B3
D3
F3
H3
K3
M3
P3
T3
E5
N5
E10
N10
B12
D12
F12
H12
K12
M12
P12
T12
G13
L13
B14
D14
F14
M14
P14
T14
CV331
10U_0603_6.3V6M
CD@
WCK01#
WCK01
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18
VDDQ19
VDDQ20
VDDQ21
VDDQ22
VDDQ23
VDDQ24
VDDQ25
VDDQ26
VDDQ27
VDDQ28
VDDQ29
VDDQ30
VDDQ31
VDDQ32
VDDQ33
VDDQ34
VDDQ35
VDDQ36
CV1546
1U_0402_6.3V6K
@
+1.35VGS
D
CV1550
1U_0402_6.3V6K
@
1
DQ40-DQ47/EDC5/DBI5#/WCK2
CV1549
1U_0402_6.3V6K
@
+FBA_VREFC0
{31} +FBA_VREFC0
BYTE5
CV1540
1U_0402_6.3V6K
OPT@
16 mil
{27}
CV345
1U_0402_6.3V6K
OPT@
FBA_RST#_H
WCK23#
WCK23
WCK23#
WCK23
A10
U10
J14
CAS#
WE#
RAS#
CS#
WCK01#
WCK01
P5
P4
{27} FBA_RST#_H
B
ABI#
RAS#
CS#
CAS#
WE#
D5
D4
+FBA_VREFC0
CV197
820P_0402_25V7
2 OPT@
MF
SEN
ZQ
J4
G3
G12
L3
L12
FBA_WCK3_N
FBA_WCK3
FBA_D[40..47]
CV343
1U_0402_6.3V6K
CD@
{27} FBA_WCK3_N
{27} FBA_WCK3
DQ32-DQ39/EDC4/DBI4#/WCK2
CV1539
1U_0402_6.3V6K
@
{27} FBA_WCK2_N
{27} FBA_WCK2
BYTE4
+1.35VGS
J1
J10
J13
FBA_WCK2_N
FBA_WCK2
{27}
CV1542
1U_0402_6.3V6K
@
C
FBA_ABI#_H
FBA_RAS#_H
FBA_CS#_H
FBA_CAS#_H
FBA_WE#_H
FBA_D[32..39]
FBA_D39
FBA_D38
FBA_D36
FBA_D37
FBA_D34
FBA_D33
FBA_D32
FBA_D35
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63
CV361
1U_0402_6.3V6K
CD@
2
OPT@
VPP/NC1
VPP/NC2
A4
A2
B4
B2
E4
E2
F4
F2
A11
A13
B11
B13
E11
E13
F11
F13
U11
U13
T11
T13
N11
N13
M11
M13
U4
U2
T4
T2
N4
N2
M4
M2
CV1541
1U_0402_6.3V6K
OPT@
1
FBA_ABI#_H
FBA_RAS#_H
FBA_CS#_H
FBA_CAS#_H
FBA_WE#_H
@
2 0_0402_5%
2 0_0402_5%
1 121_0402_1%
A10/A0
A11/A6
A8/A7
A9/A1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
CV330
10U_0603_6.3V6M
OPT@
{27}
{27}
{27}
{27}
{27}
2
1
1
2
BA2/A4
BA3/A3
BA0/A2
BA1/A5
MF=0
CV359
1U_0402_6.3V6K
OPT@
1
RV150
40.2_0402_1%
OPT@
CV196
0.01U_0402_25V7K
OPT@
2
K4
H5
H4
K5
J5
BA0/A2
BA1/A5
BA2/A4
BA3/A3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CV329
10U_0603_6.3V6M
OPT@
1
RV143
RV145
RV147
DBI3#
DBI2#
DBI1#
DBI0#
CK
CK#
CKE#
H11
K10
K11
H10
change from 1k to @
0OHM 0928sf
2
MF=1
EDC3
EDC2
EDC1
EDC0
DBI0#
DBI1#
DBI2#
DBI3#
A5
U5
1
RV148
40.2_0402_1%
OPT@
MF=1
EDC0
EDC1
EDC2
EDC3
J12
J11
J3
FBA_MA7_MA8_H
FBA_MA1_MA9_H
FBA_MA0_MA10_H
FBA_MA6_MA11_H
FBA_MA12_RFU_H
{27} FBA_MA7_MA8_H
{27} FBA_MA1_MA9_H
{27} FBA_MA0_MA10_H
{27} FBA_MA6_MA11_H
{27} FBA_MA12_RFU_H
RV149
80.6_0402_1%
@
FBA_CLK1#
D2
D13
P13
P2
FBA_MA2_BA0_H
FBA_MA5_BA1_H
FBA_MA4_BA2_H
FBA_MA3_BA3_H
{27} FBA_MA2_BA0_H
{27} FBA_MA5_BA1_H
{27} FBA_MA4_BA2_H
{27} FBA_MA3_BA3_H
Follow DG
FBA_DBI4#
FBA_DBI5#
FBA_DBI6#
FBA_DBI7#
FBA_CLK1
FBA_CLK1#
FBA_CKE_H
{27} FBA_CLK1
{27} FBA_CLK1#
{27} FBA_CKE_H
FBA_CLK1
C2
C13
R13
R2
CV360
1U_0402_6.3V6K
CD@
FBA_DBI4#
FBA_DBI5#
FBA_DBI6#
FBA_DBI7#
FBA_EDC4
FBA_EDC5
FBA_EDC6
FBA_EDC7
2
1
CV338
22U_0603_6.3V6-M
OPT@
2
1
CV339
22U_0603_6.3V6-M
CD@
2
1
CV340
22U_0603_6.3V6-M
@
2
1
CV341
22U_0603_6.3V6-M
OPT@
2
1
CV342
22U_0603_6.3V6-M
@
{27}
{27}
{27}
{27}
D
FBA_EDC4
FBA_EDC5
FBA_EDC6
FBA_EDC7
CV365
1U_0402_6.3V6K
OPT@
{27}
{27}
{27}
{27}
A7_A8
FBx_CMD23
A6_A11
1
2
1
FBx_CMD26
RAS#
FBx_CMD29
H5GC2H24BFR-T2C_BGA170
A1_A9
FBx_CMD28
1
A0_A10
FBx_CMD27
2
CV1555
1U_0402_6.3V6K
@
1
2
CV1552
1U_0402_6.3V6K
@
1
2
CV1547
1U_0402_6.3V6K
@
1
2
CV1551
1U_0402_6.3V6K
@
1
2
CV1553
1U_0402_6.3V6K
@
1
2
CV1545
1U_0402_6.3V6K
@
1
2
CV1538
1U_0402_6.3V6K
@
1
2
CV1543
1U_0402_6.3V6K
@
CV364
1U_0402_6.3V6K
OPT@
1
2
CV1544
1U_0402_6.3V6K
@
CV363
1U_0402_6.3V6K
CD@
CV362
1U_0402_6.3V6K
OPT@
CV366
1U_0402_6.3V6K
OPT@
X76@
1
2
A12_RFU
RST#
FBx_CMD30
1
2
ABI#
FBx_CMD25
2
FBx_CMD24
CKE#
FBx_CMD31
170-BALL
SGRAM GDDR5
UNDER DRAM
B
CAS#
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
Deciphered Date
2015/08/20
N17P_GDDR5_A Upper
2018/09/20
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Size
Document Number
Custom
Date:
5
4
3
https://Dr-Bios.com
2
Rev
0.1
FG541/FG741
Tuesday, February 26, 2019
1
Sheet
32
of
69
5
4
3
2
1
Memory Partition B - Lower 32 bits(MF=0)
UV8
MF=0
VPP/NC1
VPP/NC2
AROUND DRAM
2
2
CV376
1U_0402_6.3V6K
CD@
1
1
1
Address
FBx_CMD0
CV386
1U_0402_6.3V6K
CD@
CV387
1U_0402_6.3V6K
OPT@
1
1
1
1
1
CLOSE TO DRAM
+1.35VGS
UNDER DRAM
2
A0_A10
A1_A9
RAS#
RST#
CKE#
CAS#
B
2
2
2
2
2
2
2
2
2
2
CV1564
1U_0402_6.3V6K
@
CV1565
1U_0402_6.3V6K
@
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
A4_BA2
FBx_CMD20
UNDER DRAM
A2_BA0
FBx_CMD19
1
A3_BA3
FBx_CMD18
CV1572
1U_0402_6.3V6K
@
1
CS#
FBx_CMD17
2
CV1567
1U_0402_6.3V6K
@
FBx_CMD16
A5_BA1
WE#
FBx_CMD22
2
1
A12_RFU
FBx_CMD21
2
1
ABI#
FBx_CMD9
CV367
1U_0402_6.3V6K
OPT@
1
A6_A11
FBx_CMD8
2
1
AROUND DRAM
FBx_CMD7
FBx_CMD15
2
WE#
FBx_CMD14
2
A7_A8
FBx_CMD13
2
32..63
A7_A8
CV1573
1U_0402_6.3V6K
@
FBx_CMD23
2
1
1
1
1
1
1
1
1
1
1
A6_A11
CV216
820P_0402_25V7
OPT@
A0_A10
FBx_CMD27
{34}
ABI#
FBx_CMD26
1
A12_RFU
A1_A9
RAS#
RST#
FBx_CMD30
1
FBx_CMD25
FBx_CMD28
1
FBx_CMD24
CKE#
CAS#
A
1
2
A5_BA1
FBx_CMD12
2
FBx_CMD6
FBx_CMD10
2
H5GC2H24BFR-T2C_BGA170
+FBC_VREFC0
A
A4_BA2
FBx_CMD11
A1
C1
E1
N1
R1
U1
H2
K2
A3
C3
E3
N3
R3
U3
C4
R4
F5
M5
F10
M10
C11
R11
A12
C12
E12
N12
R12
U12
H13
K13
A14
C14
E14
N14
R14
U14
2
X76@
16 mil
1
A2_BA0
FBx_CMD5
+FBC_VREFC0
RV168
1.33K_0402_1%
OPT@
A3_BA3
FBx_CMD2
CLOSE TO DRAM
CS#
FBx_CMD1
1
0..31
FBx_CMD3
1
C
DATA Bus
2
CV375
1U_0402_6.3V6K
OPT@
2
CV374
1U_0402_6.3V6K
CD@
2
CV372
10U_0603_6.3V6M
OPT@
CV373
10U_0603_6.3V6M
OPT@
1
FBx_CMD31
1
2
2
1
2
1
FBx_CMD29
+1.35VGS
1
RV167
931_0402_1%
OPT@
2
1
CV1571
1U_0402_6.3V6K
@
SGRAM GDDR5
2
FBx_CMD4
1
CV1566
1U_0402_6.3V6K
@
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10
VSSQ11
VSSQ12
VSSQ13
VSSQ14
VSSQ15
VSSQ16
VSSQ17
VSSQ18
VSSQ19
VSSQ20
VSSQ21
VSSQ22
VSSQ23
VSSQ24
VSSQ25
VSSQ26
VSSQ27
VSSQ28
VSSQ29
VSSQ30
VSSQ31
VSSQ32
VSSQ33
VSSQ34
VSSQ35
VSSQ36
2
CV1569
1U_0402_6.3V6K
@
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
GDDR5
Mode H - Mirror Mode Mapping
UV8 SIDE
CV385
1U_0402_6.3V6K
CD@
RESET#
+1.35VGS
CV383
1U_0402_6.3V6K
OPT@
WCK01#
WCK01
VREFD1
VREFD2
VREFC
Cost down list:
22U 2Pcs
CV1568
1U_0402_6.3V6K
@
WCK23#
WCK23
2A Peak 3A
CV1570
1U_0402_6.3V6K
@
WCK23#
WCK23
B1
D1
F1
M1
P1
T1
G2
L2
B3
D3
F3
H3
K3
M3
P3
T3
E5
N5
E10
N10
B12
D12
F12
H12
K12
M12
P12
T12
G13
L13
B14
D14
F14
M14
P14
T14
CV370
10U_0603_6.3V6M
OPT@
WCK01#
WCK01
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18
VDDQ19
VDDQ20
VDDQ21
VDDQ22
VDDQ23
VDDQ24
VDDQ25
VDDQ26
VDDQ27
VDDQ28
VDDQ29
VDDQ30
VDDQ31
VDDQ32
VDDQ33
VDDQ34
VDDQ35
VDDQ36
CV1558
1U_0402_6.3V6K
@
CAS#
WE#
RAS#
CS#
170-BALL
RV166
549_0402_1%
OPT@
DQ24-DQ31/EDC3/DBI3#/WCK1
CV1563
1U_0402_6.3V6K
@
B
BYTE3
CV371
10U_0603_6.3V6M
OPT@
ABI#
RAS#
CS#
CAS#
WE#
+1.35VGS
G1
L1
G4
L4
C5
R5
C10
R10
D11
G11
L11
P11
G14
L14
{27}
CV384
1U_0402_6.3V6K
OPT@
H1
K1
B5
G5
L5
T5
B10
D10
G10
L10
P10
T10
H14
K14
FBC_D[24..31]
CV382
1U_0402_6.3V6K
CD@
J2
DQ16-DQ23/EDC2/DBI2#/WCK1
CV1556
1U_0402_6.3V6K
@
FBC_RST#_L
{27} FBC_RST#_L
BYTE2
CV1557
1U_0402_6.3V6K
@
A10
U10
J14
{27}
CV1559
1U_0402_6.3V6K
@
P5
P4
+FBC_VREFC0
{27} FBC_WCK1_N
{27} FBC_WCK1
D5
D4
FBC_WCK1_N
FBC_WCK1
FBC_D[16..23]
CV1560
1U_0402_6.3V6K
@
FBC_WCK0_N
FBC_WCK0
{27} FBC_WCK0_N
{27} FBC_WCK0
D
+1.35VGS
MF
SEN
ZQ
2
C
DQ8-DQ15/EDC1/DBI1#/WCK0
CV1562
1U_0402_6.3V6K
@
J4
G3
G12
L3
L12
A10/A0
A11/A6
A8/A7
A9/A1
BYTE1
{27}
CV1561
1U_0402_6.3V6K
@
J10
J13
A8/A7
A9/A1
A10/A0
A11/A6
A12/RFU/NC
DQ0-DQ7/EDC0/DBI0#/WCK0
CV390
1U_0402_6.3V6K
OPT@
CV215
0.01U_0402_25V7K
OPT@
OPT@
FBC_ABI#_L
FBC_RAS#_L
FBC_CS#_L
FBC_CAS#_L
FBC_WE#_L
{27} FBC_ABI#_L
{27} FBC_RAS#_L
{27} FBC_CS#_L
{27} FBC_CAS#_L
{27} FBC_WE#_L
1
2 0_0402_5%
1 121_0402_1%
BA2/A4
BA3/A3
BA0/A2
BA1/A5
BYTE0
CV389
1U_0402_6.3V6K
OPT@
1
2
RV165
40.2_0402_1%
OPT@
@
1
2
BA0/A2
BA1/A5
BA2/A4
BA3/A3
FBC_D[8..15]
{27}
CV392
1U_0402_6.3V6K
OPT@
2
RV159
RV161
CK
CK#
CKE#
FBC_D[0..7]
FBC_D0
FBC_D1
FBC_D2
FBC_D3
FBC_D4
FBC_D5
FBC_D6
FBC_D7
FBC_D8
FBC_D9
FBC_D10
FBC_D11
FBC_D12
FBC_D13
FBC_D14
FBC_D15
FBC_D16
FBC_D17
FBC_D18
FBC_D19
FBC_D20
FBC_D21
FBC_D22
FBC_D23
FBC_D24
FBC_D25
FBC_D26
FBC_D27
FBC_D28
FBC_D29
FBC_D30
FBC_D31
CV393
1U_0402_6.3V6K
CD@
A5
U5
change from 11k to 0OHM 0928sf
@
2 0_0402_5%
J1
RV157
DBI3#
DBI2#
DBI1#
DBI0#
A4
A2
B4
B2
E4
E2
F4
F2
A11
A13
B11
B13
E11
E13
F11
F13
U11
U13
T11
T13
N11
N13
M11
M13
U4
U2
T4
T2
N4
N2
M4
M2
CV369
10U_0603_6.3V6M
CD@
K4
H5
H4
K5
J5
DBI0#
DBI1#
DBI2#
DBI3#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
CV368
10U_0603_6.3V6M
OPT@
1
1
2
RV163
40.2_0402_1%
OPT@
RV164
80.6_0402_1%
@
FBC_CLK0#
FBC_MA7_MA8_L
FBC_MA1_MA9_L
FBC_MA0_MA10_L
FBC_MA6_MA11_L
FBC_MA12_RFU_L
{27} FBC_MA7_MA8_L
{27} FBC_MA1_MA9_L
{27} FBC_MA0_MA10_L
{27} FBC_MA6_MA11_L
{27} FBC_MA12_RFU_L
Follow DG
FBC_CLK0
H11
K10
K11
H10
EDC3
EDC2
EDC1
EDC0
MF=0
CV388
1U_0402_6.3V6K
OPT@
FBC_MA2_BA0_L
FBC_MA5_BA1_L
FBC_MA4_BA2_L
FBC_MA3_BA3_L
FBC_MA2_BA0_L
FBC_MA5_BA1_L
FBC_MA4_BA2_L
FBC_MA3_BA3_L
J12
J11
J3
EDC0
EDC1
EDC2
EDC3
MF=1
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CV391
1U_0402_6.3V6K
OPT@
FBC_CLK0
FBC_CLK0#
FBC_CKE_L
{27} FBC_CLK0
{27} FBC_CLK0#
{27} FBC_CKE_L
{27}
{27}
{27}
{27}
D2
D13
P13
P2
MF=1
2
1
CV377
22U_0603_6.3V6-M
CD@
2
1
CV378
22U_0603_6.3V6-M
OPT@
2
1
CV379
22U_0603_6.3V6-M
@
2
1
CV380
22U_0603_6.3V6-M
OPT@
2
1
CV381
22U_0603_6.3V6-M
@
FBC_DBI0#
FBC_DBI1#
FBC_DBI2#
FBC_DBI3#
{27} FBC_DBI0#
{27} FBC_DBI1#
{27} FBC_DBI2#
{27} FBC_DBI3#
D
C2
C13
R13
R2
CV394
1U_0402_6.3V6K
OPT@
FBC_EDC0
FBC_EDC1
FBC_EDC2
FBC_EDC3
FBC_EDC0
FBC_EDC1
FBC_EDC2
FBC_EDC3
CV395
1U_0402_6.3V6K
OPT@
{27}
{27}
{27}
{27}
2
3
{28} MEM_VREF
QV28
LSI1012XT1G_SC-89-3
OPT@
Issued Date
Title
LC Future Center Secret Data
Security Classification
Vgs(th)≤ 0.9V
2015/08/20
Deciphered Date
N17P_GDDR5_B Lower
2018/09/20
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Size
Document Number
Custom
Date:
5
4
3
https://Dr-Bios.com
2
Rev
0.1
FG541/FG741
Tuesday, February 26, 2019
1
Sheet
33
of
69
5
4
3
2
1
Memory Partition B - Upper 32 bits(MF=0)
UV10
MF=0
BA0/A2
BA1/A5
BA2/A4
BA3/A3
BA2/A4
BA3/A3
BA0/A2
BA1/A5
A8/A7
A9/A1
A10/A0
A11/A6
A12/RFU/NC
A10/A0
A11/A6
A8/A7
A9/A1
VPP/NC1
VPP/NC2
2
CV405
1U_0402_6.3V6K
CD@
1
1
Address
1
0..31
FBx_CMD0
A3_BA3
FBx_CMD2
A2_BA0
FBx_CMD3
CLOSE TO DRAM
A4_BA2
A5_BA1
CV415
1U_0402_6.3V6K
OPT@
CV416
1U_0402_6.3V6K
CD@
1
1
1
1
1
1
CLOSE TO DRAM
+1.35VGS
UNDER DRAM
ABI#
FBx_CMD9
CV396
1U_0402_6.3V6K
OPT@
1
AROUND DRAM
FBx_CMD8
2
WE#
A12_RFU
A0_A10
A1_A9
RAS#
RST#
CKE#
FBx_CMD15
2
A6_A11
FBx_CMD14
2
A7_A8
FBx_CMD13
2
FBx_CMD7
FBx_CMD12
2
FBx_CMD6
FBx_CMD10
2
FBx_CMD5
FBx_CMD11
A1
C1
E1
N1
R1
U1
H2
K2
A3
C3
E3
N3
R3
U3
C4
R4
F5
M5
F10
M10
C11
R11
A12
C12
E12
N12
R12
U12
H13
K13
A14
C14
E14
N14
R14
U14
2
32..63
CS#
FBx_CMD1
FBx_CMD4
Cost down
AROUND DRAM
CAS#
2
2
2
2
2
2
2
2
2
2
B
CV1583
1U_0402_6.3V6K
@
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
A4_BA2
FBx_CMD20
UNDER DRAM
A2_BA0
FBx_CMD19
1
A3_BA3
FBx_CMD18
CV1590
1U_0402_6.3V6K
@
FBx_CMD17
2
CS#
A5_BA1
WE#
FBx_CMD22
2
FBx_CMD16
FBx_CMD21
2
1
A7_A8
FBx_CMD23
2
A6_A11
1
1
1
1
1
1
1
1
1
X76@
H5GC2H24BFR-T2C_BGA170
A0_A10
FBx_CMD27
1
ABI#
FBx_CMD26
A1_A9
RAS#
RST#
CKE#
FBx_CMD31
1
A12_RFU
FBx_CMD29
1
FBx_CMD25
FBx_CMD28
1
FBx_CMD24
FBx_CMD30
SGRAM GDDR5
C
DATA Bus
2
CV403
1U_0402_6.3V6K
CD@
1
2
CV404
1U_0402_6.3V6K
OPT@
1
CV401
10U_0603_6.3V6M
OPT@
CV402
10U_0603_6.3V6M
OPT@
CV399
10U_0603_6.3V6M
OPT@
CV400
10U_0603_6.3V6M
OPT@
1
2
CV1591
1U_0402_6.3V6K
@
170-BALL
1
2
CV1589
1U_0402_6.3V6K
@
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10
VSSQ11
VSSQ12
VSSQ13
VSSQ14
VSSQ15
VSSQ16
VSSQ17
VSSQ18
VSSQ19
VSSQ20
VSSQ21
VSSQ22
VSSQ23
VSSQ24
VSSQ25
VSSQ26
VSSQ27
VSSQ28
VSSQ29
VSSQ30
VSSQ31
VSSQ32
VSSQ33
VSSQ34
VSSQ35
VSSQ36
1
2
CV414
1U_0402_6.3V6K
OPT@
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
2
CV1582
1U_0402_6.3V6K
@
B
RESET#
1
2
CV1584
1U_0402_6.3V6K
@
G1
L1
G4
L4
C5
R5
C10
R10
D11
G11
L11
P11
G14
L14
VREFD1
VREFD2
VREFC
2
CV1585
1U_0402_6.3V6K
@
+1.35VGS
WCK01#
WCK01
GDDR5
Mode H - Mirror Mode Mapping
UV10 SIDE
CV1587
1U_0402_6.3V6K
@
2
CV235
820P_0402_25V7
OPT@
WCK23#
WCK23
+1.35VGS
CV1586
1U_0402_6.3V6K
@
1
WCK23#
WCK23
CV1588
1U_0402_6.3V6K
@
+FBC_VREFC0
{33} +FBC_VREFC0
WCK01#
WCK01
Cost down list:
22U 2Pcs
2A Peak 3A
CV411
1U_0402_6.3V6K
OPT@
16 mil
CAS#
WE#
RAS#
CS#
B1
D1
F1
M1
P1
T1
G2
L2
B3
D3
F3
H3
K3
M3
P3
T3
E5
N5
E10
N10
B12
D12
F12
H12
K12
M12
P12
T12
G13
L13
B14
D14
F14
M14
P14
T14
CV413
1U_0402_6.3V6K
OPT@
H1
K1
B5
G5
L5
T5
B10
D10
G10
L10
P10
T10
H14
K14
ABI#
RAS#
CS#
CAS#
WE#
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18
VDDQ19
VDDQ20
VDDQ21
VDDQ22
VDDQ23
VDDQ24
VDDQ25
VDDQ26
VDDQ27
VDDQ28
VDDQ29
VDDQ30
VDDQ31
VDDQ32
VDDQ33
VDDQ34
VDDQ35
VDDQ36
CV1576
1U_0402_6.3V6K
@
J2
+1.35VGS
MF
SEN
ZQ
CV1581
1U_0402_6.3V6K
@
FBC_RST#_H
DQ56-DQ63/EDC7/DBI7#/WCK3
{27}
CV412
1U_0402_6.3V6K
OPT@
A10
U10
J14
DQ48-DQ55/EDC6/DBI6#/WCK3
CV1574
1U_0402_6.3V6K
@
P5
P4
{27}
FBC_D[56..63]
BYTE6
BYTE7
FBC_D[48..55]
CV1577
1U_0402_6.3V6K
@
{27} FBC_RST#_H
FBC_WCK3_N
FBC_WCK3
D
CV1575
1U_0402_6.3V6K
@
{27} FBC_WCK3_N
{27} FBC_WCK3
D5
D4
DQ40-DQ47/EDC5/DBI5#/WCK2
CV1580
1U_0402_6.3V6K
@
{27} FBC_WCK2_N
{27} FBC_WCK2
FBC_WCK2_N
FBC_WCK2
+FBC_VREFC0
C
BYTE5
CV418
1U_0402_6.3V6K
OPT@
J4
G3
G12
L3
L12
{27}
CV1578
1U_0402_6.3V6K
@
FBC_ABI#_H
FBC_RAS#_H
FBC_CS#_H
FBC_CAS#_H
FBC_WE#_H
J10
J13
FBC_D[40..47]
CV420
1U_0402_6.3V6K
OPT@
OPT@
DQ32-DQ39/EDC4/DBI4#/WCK2
CV1579
1U_0402_6.3V6K
@
FBC_ABI#_H
FBC_RAS#_H
FBC_CS#_H
FBC_CAS#_H
FBC_WE#_H
2 0_0402_5%
1 121_0402_1%
BYTE4
CV398
10U_0603_6.3V6M
OPT@
{27}
{27}
{27}
{27}
{27}
2
1
2
{27}
CV419
1U_0402_6.3V6K
OPT@
RV174
RV175
1
@
FBC_D[32..39]
FBC_D32
FBC_D33
FBC_D34
FBC_D35
FBC_D36
FBC_D37
FBC_D38
FBC_D39
FBC_D40
FBC_D41
FBC_D42
FBC_D43
FBC_D44
FBC_D45
FBC_D46
FBC_D47
FBC_D48
FBC_D49
FBC_D50
FBC_D51
FBC_D52
FBC_D53
FBC_D54
FBC_D55
FBC_D56
FBC_D57
FBC_D58
FBC_D59
FBC_D60
FBC_D61
FBC_D62
FBC_D63
CV417
1U_0402_6.3V6K
CD@
2
RV180
40.2_0402_1%
OPT@
CK
CK#
CKE#
change from 1k to0_0402_5% 0928sf
0OHM
@
2
J1
RV172 1
CV234
0.01U_0402_25V7K
OPT@
1
DBI3#
DBI2#
DBI1#
DBI0#
A4
A2
B4
B2
E4
E2
F4
F2
A11
A13
B11
B13
E11
E13
F11
F13
U11
U13
T11
T13
N11
N13
M11
M13
U4
U2
T4
T2
N4
N2
M4
M2
CV422
1U_0402_6.3V6K
CD@
A5
U5
2
FBC_CLK1#
K4
H5
H4
K5
J5
DBI0#
DBI1#
DBI2#
DBI3#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
CV421
1U_0402_6.3V6K
OPT@
FBC_MA7_MA8_H
FBC_MA1_MA9_H
FBC_MA0_MA10_H
FBC_MA6_MA11_H
FBC_MA12_RFU_H
EDC3
EDC2
EDC1
EDC0
MF=0
CV397
10U_0603_6.3V6M
CD@
1
RV179
80.6_0402_1%
@
FBC_MA7_MA8_H
FBC_MA1_MA9_H
FBC_MA0_MA10_H
FBC_MA6_MA11_H
FBC_MA12_RFU_H
H11
K10
K11
H10
EDC0
EDC1
EDC2
EDC3
MF=1
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
2
1
CV406
22U_0603_6.3V6-M
CD@
2
1
CV408
22U_0603_6.3V6-M
@
2
1
CV407
22U_0603_6.3V6-M
OPT@
2
1
CV409
22U_0603_6.3V6-M
OPT@
2
1
CV410
22U_0603_6.3V6-M
@
{27}
{27}
{27}
{27}
{27}
1
2
RV178
40.2_0402_1%
OPT@
FBC_MA2_BA0_H
FBC_MA5_BA1_H
FBC_MA4_BA2_H
FBC_MA3_BA3_H
J12
J11
J3
FBC_MA2_BA0_H
FBC_MA5_BA1_H
FBC_MA4_BA2_H
FBC_MA3_BA3_H
{27}
{27}
{27}
{27}
Follow DG
D2
D13
P13
P2
FBC_CLK1
FBC_CLK1#
FBC_CKE_H
{27} FBC_CLK1
{27} FBC_CLK1#
{27} FBC_CKE_H
FBC_CLK1
FBC_DBI4#
FBC_DBI5#
FBC_DBI6#
FBC_DBI7#
MF=1
CV423
1U_0402_6.3V6K
CD@
{27} FBC_DBI4#
{27} FBC_DBI5#
{27} FBC_DBI6#
{27} FBC_DBI7#
D
C2
C13
R13
R2
CV424
1U_0402_6.3V6K
OPT@
{27} FBC_EDC4
{27} FBC_EDC5
{27} FBC_EDC6
{27} FBC_EDC7
FBC_EDC4
FBC_EDC5
FBC_EDC6
FBC_EDC7
CAS#
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/08/20
Deciphered Date
N17P_GDDR5_B Upper
2018/09/20
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Size
Document Number
Custom
Date:
5
4
3
https://Dr-Bios.com
2
Rev
0.1
FG541/FG741
Tuesday, February 26, 2019
1
Sheet
34
of
69
5
4
3
2
1
+1.8V_AUDIO
DVDD_IO
DVDD_IO
27
HPOUT_R
+5VS
+5VA
1
LA25
EMC_NS@
1
2
BLM15PD600SN1D_2P
2 0_0603_SM
@
2 0_0603_SM
1@
2
1
2
2
1
2
1
0.1U_0201_6.3V6-K
CA19
1
0.1U_0201_6.3V6-K
CA18
@
20
41
46
40
AVDD1
PVDD1
PVDD2
18
3
JD1
MIC2-L/RING2
GPIO1/DMIC-CLK
31
PC_BEEP
MIC2-R/SLEEVE
I2C-DATA
34
PCBEEP
I2C-CLK
1
2 10K_0402_5%
VDD_STB
NC1
33
LINE2-R
5VSTB
NC2
35
LINE2-L
36
LINE2-R
NC3
LINE2-L
NC4
NC5
+1.8V_AUDIO
RA225
1
CA48 1
2 1U_0402_6.3V6K
23
2 0_0402_5%
CBP
CBN
24
2 0_0402_5%
2.2U_0402_6.3V6M
2 @
1
2 CA1
19
1
2 CA185
21
1
2 CA43
39
MIC2-CAP
DC DET/EAPD
LDO3-CAP
48
HDA_SYNC_AUDIO
JSENSE
1 RA205
PLUG_IN
2 0_0402_5%
@
@
{16}
{16}
+3VS
2 @ 1 0.1U_0201_6.3V6-K
1
4
5
DMIC_DATA_R
RA19 1
@
2 0_0402_5%
RA18 1
DMIC_CLK_R
@
2 0_0402_5%
DMIC_DATA {38}
DMIC_CLK {38}
6
7
8
9
10
11
12
SPK_R+
SPK_R-
43
SPK_LSPK_L+
13
16
SDATA-IN
LDO2-CAP
SDATA-OUT
17
LDO1-CAP
37
CPVEE
Thermal Pad
AVSS2
AVSS1
RA43
10K_0402_5%
@
2 0_0402_5%
HDA_BITCLK_AUDIO
100K_0402_1% 2
RA204 1
VREF
2
@
38
SDATA_IN
2
33_0402_5%
1 RA16
HDA_SDIN0
{16}
HDA_SDOUT_AUDIO
HDA_SDOUT_AUDIO
C
{16}
25
2
CA47
1U_0402_6.3V6K
1
ALC3287-CG_MQFN48_6X6
49
LRB751V-40T1G_SOD323-2
RA35 1
1 CA44
1
1
{49} EC_MUTE#
2
2.2U_0402_6.3V6M
SPKR_MUTE#
HDA_SYNC_AUDIO
47
42
SPK-OUT-L+
32
2.2U_0402_6.3V6M
DA4
EC_MUTE#
1 CA41
2.2U_0402_6.3V6M
C
2
22
1
D
HDA_BITCLK_AUDIO
15
44
SPK-OUT-RSPK-OUT-L-
2.2U_0402_6.3V6M
RA226
14
45
SPK-OUT-R+
@
+1.8VALW
1
SPKR_MUTE#
+5VA
RA203
+1.8VS
2
1
CA197
GPIO0/DMIC-DATA12
30
RING3_CONN
2
2
MIC2-VREFO-R
SPDIF-OUT/GPIO2/DMIC-DATA34/DMIC-CLK-IN
10U_0603_6.3V6M
CA178
RA10 1
JD2
MIC2-VREFO-L
29
RING2_CONN
10U_0603_6.3V6M
CA194
1
2
1U_0402_6.3V6K
CA20
0.1U_0201_6.3V6-K
CA42
2
BCLK
SYNC
HPOUT-R
28
MIC2_VREFOR
+5VD
+5VS
RA7
PDB
HPOUT-L
26
MIC2_VREFOL
CPVDD/AVDD2
HPOUT_L
Close to Pin7
DVDD
2
DVDD-IO
1
UA1
2.2U_0402_6.3V6M
CA192
1
1
CA4
0.1U_0201_6.3V6-K
2
2
+5VA
2 0_0402_5%
@
2
10U 6.3V M X5R 0402
CA179 CD@
1
RA227
1
0.1U_0201_6.3V6-K
CA180
2 0_0402_5%
+1.8VALW
CA2
0.1U_0201_6.3V6-K
@
1
2 0_0402_5%
CA193
2.2U_0402_6.3V6M
+1.8VS
RA216
@
+5VD
RA213 1
D
Analog power for DACs, ADCs
+3VS
+3VALW
CA3
1
RA5
2 4.7K_0402_5%
1
2
0.1U_0201_6.3V6-K
DA1
2
{49} EC_BEEP#
RA6
1PC_BEEP1
1
CA40
1
2
2
PC_BEEP
3
4.7K_0402_5%
LBAT54CWT1G_SOT323-3
@
RA14
10K_0402_5%
@
2
@
0_0402_5%
2
1
RA211
0.1U_0201_6.3V6-K
1
{16} PCH_BEEP
Speaker
RA223 1 CD@
RA224 1 CD@
RA32 1 CD@
RA33 1 CD@
HDA_SYNC_AUDIO
2
1
220P_0201_25V7-K
CA30
220P_0201_25V7-K
CA29
CD@ CD@
2
2
1
CD@ CD@
1
2
1
2
1
2
EMC@
2
1
1
1
2
1500P_50V_K_X7R_0402
1
2
CA182
2
1
1500P_50V_K_X7R_0402
GNDA
1
CA39
100P_0201_25V8J
EMC_NS@
2
CA38
100P_0201_25V8J
EMC@
1
CA26
33P_0201_50V8-J
EMC_NS@
2
CA25
33P_0201_50V8-J
EMC_NS@
1
CA24
22P_0201_258J
EMC_NS@
GND
2
CA23
22P_0201_258J
EMC_NS@
1
2
EMC@
1
2 0_0402_5%
EMC_NS@
DMIC_DATA
1500P_50V_K_X7R_0402
RA12
DMIC_CLK
1
2
3
4
CA181
2 0_0402_5%
ME@
JSPK1
SPK_R+_CONN
SPK_R-_CONN
SPK_L+_CONN
SPK_L-_CONN
EMC@
2 0_0402_5%
@
2 0_0603_5%
2 0_0603_5%
2 0_0603_5%
2 0_0603_5%
EMC@
@
1
@
@
@
@
CA32
1
RA9
B
RA222 1
RA221 1
RA30 1
RA34 1
1500P_50V_K_X7R_0402
RA4
HDA_BITCLK_AUDIO
2
27_0402_5%
EMC_NS@
HDA_SDIN0
1
RA27
SPK_R+
SPK_RSPK_L+
SPK_L-
CA31
1
2 0_0402_5%
EMC_NS@
220P_0201_25V7-K
CA183
RA1
220P_0201_25V7-K
CA184
HDA_SDOUT_AUDIO
2 15_0402_5%
2 15_0402_5%
2 15_0402_5%
2 15_0402_5%
RA228
0_0402_5%
1
2
@
RING3_CONN
RING2_CONN
A_HP_OUTL_R
A_HP_OUTR_R
PLUG_IN
CA187
470P_0201_50V7-K
1
2 @
1
1
2
2
1
1
2
2
1
1
2
2
1
1
2
2
1
1
LINE2-L
A_HP_OUTR_R
CA5
CA6
5
1 @ 2 1U_0402_6.3V6K
HPOUT_R
MIC2_VREFOR
RA3
10K_0402_5%
1
2
@
PLUG_IN
1 @ 2 1U_0402_6.3V6K
LINE2-R
3
1
RA20 1
RA38 2
6
A_HP_OUTR_R
2 56_0402_5%
2
RING3_CONN
1 2.2K_0402_5%
1
2@
2
1@
1
2
4
1
2
CA191
100P_0201_25V8J
EMC@
2
B
RING2_CONN
A_HP_OUTL_R
1 2.2K_0402_5%
2 56_0402_5%
100P 25V J NPO 0201
CA195
2
CA188
470P_0201_50V7-K
1
2 @
RA37 2
RA21 1
CA190
100P_0201_25V8J
EMC@
DA9
RA229
0_0402_5%
1
2
@
MIC2_VREFOL
HPOUT_L
100P 25V J NPO 0201
CA196
DA8
EMC@
AZ5123-01F.R7GR_DFN1006P2X2
DA7
EMC_NS@
AZ5123-01F.R7GR_DFN1006P2X2
EMC_NS@
AZ5123-01F.R7GR_DFN1006P2X2
EMC_NS@
AZ5123-01F.R7GR_DFN1006P2X2
EMC_NS@
AZ5123-01F.R7GR_DFN1006P2X2
CA189
47P_0201_25V8-J
EMC_NS@
2
DA6
GND1
GND2
ACES_88231-04001
ME@
JHP1
A_HP_OUTL_R
RA2
10K_0402_5%
1
2
@
DA5
1
2
3
4
Audio Jack
For EMI
1
5
6
7
G/M
L
5
6
R
M/G
MS
SINGA_2SJ3095-140111F
A
A
Security Classification
Issued Date
T itle
LC Future Center Secret Data
2015/08/20
Deciphered Date
2018/09/20
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Codec & CR_RTS5199
Size
D
Document Number
4
3
https://Dr-Bios.com
2
Rev
0.1
FG541/FG741
Wednesday, February 27, 2019
Date:
5
1
Sheet
35
of
69
5
4
3
2
1
D
D
C
C
B
B
A
A
Title
LC Future Center Secret Data
Security Classification
Issued Date
2015/08/20
Cardreader
2018/09/20
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Size Document Number
Custom
Date:
5
4
3
https://Dr-Bios.com
2
R ev
0.1
FG541/FG741
Thursday, January 03, 2019
Sheet
1
36
of
69
5
D
+3VALW
4
3
2
1
+3VALW_TPM
1
2
1
2
0.1U_6.3V_K_X5R_0201
C257
@
2
0.1U_6.3V_K_X5R_0201
CTPM4TPM@
1
D
0.1U_6.3V_K_X5R_0201
CTPM3TPM@
2
10U_0603_6.3V6M
CTPM1
RTPM1
1
2
0.01_0603_1%
TPM@
1@
+3VALW_TPM
1
2
TPM_PIRQ#
TPM@
18
21
24
20
{18} TPM_SPI_CS#
19
{18} TPM_SPI_CLK
PLT_RST#
17
C
6
7
1
1
NCI1
NCI2
NCI3
NCI4
NCI5
NCI6
NCI7
VDD/NCI8
NCI9
GND/NCI10
NCI11
NCI12
NCI13
NCI14
NCI15
MOSI
MISO
CS#
SCLK
RST#
GPIO
3
4
5
10
11
12
13
14
15
16
25
26
27
28
31
C
PP
GND5
33
GND4
32
GND3
GND2
9
2
2
R1123
0_0402_5%
@
23
GND1
1
TPM_PP
PIRQ#
8
22
1
1 0_0402_5%
2
2
R2110
{18} TPM_SPI_MOSI
{18} TPM_SPI_MISO
R2104
10K_0402_5%
@
R505
0_0402_5%
@
NCI/VDD1
1
{15} TPM_PIRQ
UTPM1
VDD2
R2103
10K_0402_5%
TPM@
R2102
10K_0402_5%
TPM@
VDD3
2
2
+3VALW_TPM
NC1
NC2
29
30
R1124
1
@
2 0_0402_5%
PLT_RST# {18,28,41,42,45,49}
SLB9670VQ2.0FW7.61_VQFN32_5X5
TPM@
B
B
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/08/20
Deciphered Date
https://Dr-Bios.com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
5
4
3
2
TPM
2018/09/20
Size
C
Date:
Document Number
Rev
0.1
FG541/FG741
Thursday, January 03, 2019
1
Sheet
37
of
69
5
4
3
2
1
LCD POWER CIRCUIT
+3VS
2
+3VS_CMOS
1
2
LP2301ALT1G_SOT23-3
Q7
C5
0.1u_0201_10V6K
@
CMOS_ON#
2
C14
3A_32V_0497003PKRHF
2
@
2
1
1
2
C9
0.01U_0201_25V6-K
EMC_NS@
1
0.1U_0201_25V6-K
CD@
1
C15
0_0805_5%
2
4.7U_0805_25V6-K
2
F3
1
EMC@
2A 80 mil
@
1
R17
1
1
2
R5 1
@
100K_0402_5%
For RF
+LEDVDD
3
@
RF_NS@
1
2
2
C6
C121
@
+3VS_CMOS_R
@
1
1
G
U5 EN PIN VIH MIN 1.5V
V20B+
2A 80 mil
J1
JUMP_43X39
2
2
0.1u_0201_10V6K
1
C123
3
OCB
SY6288C20AAC_SOT23-5
D
Need short
+3VS
W=40 mils
D
EN
W=60mils
2
@
0_0805_5%
4.7U_0402_6.3V6M
4
1
C122
GND
EDP_ENVDD
2
R263
2
33P_0402_50V8J
1
OUT
S
C1
0.1u_0201_10V6K
CMOS Camera
+LCDVDD_CON
1
IN
2
2
W=40mils
R3 1
@
2
0_0603_SM
0.01U_0201_10V6K
+LCDVDD
U5
5
1
1
1@
C4
10U_0603_6.3V6M
2
F4
C3
1
2
0.1u_0201_10V6K
CD@
2
0.5A_32V_ERBRD0R50X
@
C10
0.1u_0201_10V6K
@
For EMI
Close to R5
D
EMI Request
R10565
{14} PCH_EDP_ENVDD
1
2
2
EDP_ENVDD
0_0402_5%
0_0402_5%
R296
1
@
2
1
@
2
CMOS_ON#
0_0402_5%
R297
{20} PCH_CMOS_ON#
R10566 1
EDP_OPTNS@
0_0402_5%
JEDP1
EDP_TX0+
EDP_TX0-
R1
100K_0402_5%
2
EDP_TX1+
EDP_TX1EDP_AUX
EDP_AUX#
DISPOFF#
2
2
+3VS
R8
100K_0402_1%
1
@
INVT_PWM
1
R9
100K_0402_1%
@
eDP_HPD_CON
GSYNC#
C19
C16
1
1
2 .1U_0402_10V6-K
2 .1U_0402_10V6-K
EDP_CPU@
EDP_CPU@
C17
C18
1
1
2 .1U_0402_10V6-K
2 .1U_0402_10V6-K
EDP_CPU@
EDP_CPU@
C20
C21
1
1
2 .1U_0402_10V6-K
2 .1U_0402_10V6-K
1
1
2 .1U_0402_10V6-K
2 .1U_0402_10V6-K
EDP_OPTNS@
C10140
EDP_OPTNS@
C10141
1
1
2 .1U_0402_10V6-K
2 .1U_0402_10V6-K
EDP_OPTNS@
C10143
EDP_OPTNS@
C10142
CPU_EDP_AUX
CPU_EDP_AUX#
{8} CPU_EDP_AUX
{8} CPU_EDP_AUX#
EDP_CPU@
EDP_CPU@
EDP_OPTNS@
C10139
EDP_OPTNS@
C10138
CPU_EDP_TX1+
CPU_EDP_TX1-
1
1
2 .1U_0402_10V6-K
2 .1U_0402_10V6-K
@
EDP_TX0+
EDP_TX0-
USB20_P8_R
2 0_0402_5%
USB20_N8_R
2 0_0402_5%
R182 1
@
R183 1
@
+3VS_CMOS
{19} USB20_P8
{19} USB20_N8
1
CPU_EDP_TX0+
CPU_EDP_TX0-
+3VS
{35} DMIC_DATA
{35} DMIC_CLK
R13
100K_0402_1%
@
1
R15
100K_0402_1%
{8} CPU_EDP_TX1+
{8} CPU_EDP_TX1-
+LCDVDD_CON
2
2
EDP_AUX
EDP_AUX#
{8} CPU_EDP_TX0+
{8} CPU_EDP_TX0-
W=40mils
EDP_TX1+
EDP_TX1-
IFPD_L1+
IFPD_L1-
{26} IFPD_L1+
{26} IFPD_L1-
IFPD_AUX+
IFPD_AUX-
C
{26} IFPD_AUX+
{26} IFPD_AUX-
1
C24
.047U_0201_6.3V6K
EMC_NS@
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
G1
G2
DRAPH_FC5AF301-3181H
ME@
2
EDP_AUX
EDP_AUX#
EMI
IFPD_L0+
IFPD_L0-
{26} IFPD_L0+
{26} IFPD_L0-
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
+LEDVDD
{49} EC_CMOS_ON#
1
{28} GPU_EDP_ENVDD
request
EDP_TX0+
EDP_TX0EDP_TX1+
EDP_TX1EDP_AUX
EDP_AUX#
C
+3VS
2
+1.8VS_AON
1
1
2
G2
@
4
6
2
@
QV47A
PJT7838_SOT363-6
D1
2
GSYNC#
S1
EDP_OPT@
R10568
100K_0402_5%
5
RV1258
10K_0402_5%
EDP_OPT@
QV37A
PJT7838_SOT363-6
G1
{28}
G1
S1
@
Vgs(th)≤ 1.0V
2
1
1
R16
100K_0402_5%
GPU_FRAME_LOCK#
QV47B
PJT7838_SOT363-6
D2
1
S2
2
{28} GPU_EDP_ENBKL
ENBKL {49}
@
1
ENBKL
1
0_0402_5%
@
RV1283
10K_0402_5%
3
EDP_OPT@
QV37B
PJT7838_SOT363-6
S2
3
D2
G2
4
6
DISPOFF#
GPU_EDP_ENBKL
2
2 0_0402_5% ENBKL
EDP_OPTNS@
1
2
2 0_0402_5%
@
D1
1
R14 1
{14} PCH_EDP_ENBKL
1
+LCDVDD
1
1
R12
{49} BKOFF#
5
1
@
2
0_0402_5%
RV1282
10K_0402_5%
+3VALW
R10569
RV1252
10K_0402_5%
EDP_OPT@
2
R10
4.7K_0402_5%
@
R11
ENBKL
2
RV1253
2.2K_0402_5%
EDP_OPT@
+3VALW
+3VS
2
Vgs(th)≤ 1.0V
2
+LCDVDD
RV1248
2.2K_0402_5%
EDP_OPT@
2
EMC_NS@
1
C13
2
470P_0201_50V7-K
2
B
S1
2
EDP_OPT@
R10567
100K_0402_5%
1
1
G1
INVT_PWM
1
C12
1
Vgs(th)≤ 1.0V
2
2
D1
GPU_EDP_PWM
{28} GPU_EDP_PWM
request
DISPOFF#
470P_0201_50V7-K
3
DMIC_CLK
EDP_OPT@
QV36A
PJT7838_SOT363-6
1
R20
100K_0402_5%
EMI
INVT_PWM
S2
INVT_PWM
0_0402_5%
6
2
G2
2 0_0402_5%
EDP_OPTNS@
4
R19 1
{14} PCH_EDP_PWM
D2
1
5
1
B
1
EDP_OPT@
QV36B
PJT7838_SOT363-6
EMC_NS@
2
R18
1K_0402_5%
@
EMC_NS@
C11
2
R10570
RV1247
10K_0402_5%
EDP_OPT@
100P_0201_25V8J
1
+3VALW
+3VS
+1.8VS_AON
2
0_0402_5%
For EMI
eDP_HPD_CON
USB20_N8
1
1
update by SF
20181023
1
R10223
R10400
100K_0402_5%
R317
10K_0402_5%
EDP_OPT@
USB20_P8
L12
1
EMC_NS@
1
2
4
4
3
2
3
USB20_N8_R
USB20_P8_R
EXC24CH900U_4P
2
PCH_EDP_HPD
{15} PCH_EDP_HPD
IFPD_HPD
EDP_OPT@
Q181
MMBT3904WH_SOT323-3
1
2
{28} IFPD_HPD
C
2
1
R318
2 100K_0402_5%
EDP_OPT@
1
3
B
E
1
2
1
R319
EDP_OPTNS@
C366
220P_0402_50V7K
EDP_OPT@
eDP_HPD_CON
2 0_0402_5%
1
2
C367
220P_0402_50V7K
EDP_OPT@
2
R324
100K_0402_5%
EDP_OPT@
Touch Screen
delete TS function0704SF
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/08/20
https://Dr-Bios.com
eDP/CMOS/Touch screen
2018/09/20
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Size
Document
Custom
Date:
5
4
3
2
Number
Re v
0.1
FG541/FG741
Sheet
Wednesday, February 27, 2019
1
38
of
69
5
4
3
2
1
+1.8VS_AON
@
CRE251
HDMI1_TX0+
{26} HDMI1_TX0+
2 0.1u_0201_10V6K
2 0_0402_5%
EMC_NS@
HDMI1_TX0-_C
L2 1
HDMI1_TX0+_C
4
1
HDMI1_TX0-_R
2
2
4
3
HDMI1_TX0+_R
3
2
HDMI D0
2 0.1u_0201_10V6K
EXC24CH500U_4P
2 0_0402_5%
R10505 1 @
10K_0402_5%
RRE59
CRE261
1
R10498 1
HDMI1_TX0{26} HDMI1_TX0-
IFPE_HPD
{28} IFPE_HPD
1
QRE3
MMBT3904WH_SOT323-3
C
HDMI1_TX1+_C
4
1
2
4
@
CRE301
CRE291
HDMI1_TX2+
{26} HDMI1_TX2+
2 0.1u_0201_10V6K
2 0.1u_0201_10V6K
L4 1
HDMI1_TX2+_C
4
1
4
3
@
+3VS
HPD
CRE311
HDMI1_TXC+
{26} HDMI1_TXC+
2 0.1u_0201_10V6K
HDMI1_CLK+_C
L5 1
4
1
RRE61
1M_0402_5%
4
2
3
2
3
HDMI_HPD
HDMI1_CLK+_R
{15} HDMI_HPD
QRE6
PJA138K_SOT23-3
EXC24CH500U_4P
2 0_0402_5%
R10502 1 @
HDMI1_TX0+_B
R31
@
2 0_0402_5%
HDMI1_TX0-_B
R10427 1
@
2 0_0402_5%
2 499_0402_1%
HDMI1_TX1+_B
R10428 1
@
2 0_0402_5%
1
2 499_0402_1%
HDMI1_TX1-_B
R10429 1
@
2 0_0402_5%
R10430 1
@
2 0_0402_5%
HDMI1_TX2+_B
R37
2 499_0402_1%
HDMI1_TX2-_B
R10431 1
@
2 499_0402_1%
HDMI1_CLK+_B
R10432 1
@
2 499_0402_1%
R10433 1
@
2 0_0402_5%
+5VS_HDMI1_F
QRE4
LP2301ALT1G_SOT23-3
+5VS_HDMI1
2 0_0402_5%
1
+5VS
2 0_0402_5%
1
1
S
3
D
2
1
2
1
@
D4322
RB751V-40_SOD323-2
1
suggestion
2
@
1
3
S
NV
1
@
R10540
0_0805_5%
@
2N7002KW_SOT323-3
G
R42
1
@
D4321
RB751V-40_SOD323-2
2
1
CRE11
.1U_0402_10V6-K
2
Q13
2
1
{51} SUSP
D
2
+3VS
R10539
0_0805_5%
1.1A_8V_1206L110THYR
2
HDMI1_CLK-_B
C
F2
1
1
HDMI1_CLK-_C
1
R30
HDMI1_CLK+_C
2 499_0402_1%
R29
HDMI1_TX2-_C
1
R38
C
G
HDMI1_TX2+_C
R10426 1
2 499_0402_1%
1
R34
HDMI1_TX1-_C
2 499_0402_1%
1
R33
HDMI1_TX1+_C
1
R32
HDMI1_TX0-_C
2
HDMI1_TX0+_C
HDMI1_HPD_CON
D
HDMI CLK
2 0.1u_0201_10V6K
HDMI1_CLK-_R
S
CRE321
{26} HDMI1_TXC-
2 0_0402_5%
EMC_NS@
HDMI1_CLK-_C
D
G
HDMI1_TXC-
2
HDMI1_TX2+_R
3
EXC24CH500U_4P
2 0_0402_5%
R10503 1 @
R10501 1
HDMI1_HPD_CON
RE281
100K_0402_5%
HDMI1_TX2-_R
2
2
2 0_0402_5%
CRE9
220P_0402_50V7K
2 0_0402_5%
EMC_NS@
HDMI1_TX2-_C
1
RRE58
1
1
R10500 1
HDMI1_TX2{26} HDMI1_TX2-
2 100K_0402_5%
1
3
EXC24CH500U_4P
2 0_0402_5%
R10504 1 @
HDMI D2
1
RRE56
100K_0402_5%
HDMI1_TX1+_R
3
3
RRE57
B
HDMI1_TX1-_R
2
2
2
2 0.1u_0201_10V6K
L3 1
1
CRE271
{26} HDMI1_TX1+
HDMI1_TX1-_C
2
HDMI1_TX1+
2 0.1u_0201_10V6K
1
CRE281
3
HDMI D1
E
2
HDMI1_TX1{26} HDMI1_TX1-
D
2 0_0402_5%
EMC_NS@
2
@
R10499 1
RRE15
2.2K_0402_5%
RRE16
2.2K_0402_5%
JHDMI2
18
HDMI1_TX0+_R
HDMI1_TX0-_R
HDMI1_TX1+_R
HDMI1_TX1-_R
HDMI1_TX2+_R
HDMI1_TX2-_R
Close to JHDMI1
HDMI1_HPD_CON
HDMI1_DAT_CON
1
2
4
+5VS_HDMI1
5
3
8
Line-1
NC1
Line-2
NC2
Line-3
NC3
Line-4
1
1
1
1
1
1
2
2
2
2
2
2
1/16W_6.8_5%_0402
1/16W_6.8_5%_0402
1/16W_6.8_5%_0402
1/16W_6.8_5%_0402
1/16W_6.8_5%_0402
1/16W_6.8_5%_0402
HDMI1_TX0+_CON
HDMI1_TX0-_CON
HDMI1_TX1+_CON
HDMI1_TX1-_CON
HDMI1_TX2+_CON
HDMI1_TX2-_CON
7
9
4
6
1
3
D7
D3
HDMI1_CLK_CON
R10319
R10320
R10321
R10322
R10323
R10324
NC4
10
HDMI1_HPD_CON
HDMI1_TX0-_R
1
HDMI1_DAT_CON
HDMI1_TX0+_R
7
HDMI1_CLK_CON
HDMI1_CLK-_R
6
+5VS_HDMI1
Line-1
4
NC4
10
9
HDMI1_TX0-_R
HDMI1_TX1+_R
HDMI1_TX0+_R
7
HDMI1_TX2-_R
HDMI1_CLK-_R
6
1
Line-1
HDMI1_TX2+_R
3
NC4
10
9
7
6
HDMI1_TX1-_R
8
5
2
HDMI1_TX1+_R
SCL
SDA
CEC
DDC/CEC_Ground
Hot_Plug_Detect
TMDS_Data0_Shield
TMDS_Data1_Shield
TMDS_Data2_Shield
Utility
HDMI1_TX2-_R
HDMI1_CLK+_R
HDMI1_CLK-_R
HDMI1_TX2+_R
R10325 1
R10326 1
2 1/16W_6.8_5%_0402
2 1/16W_6.8_5%_0402
HDMI1_CLK+_CON
HDMI1_CLK-_CON
11
10
12
GND1
GND2
GND3
GND4
TMDS_Clock_Shield
TMDS_Clock+
TMDS_Clock-
15
16
13
17
19
HDMI1_CLK_CON
HDMI1_DAT_CON
HDMI1_HPD_CON
14
20
21
22
23
GND1
8
GND2
NC3
Line-4
5
NC2
Line-3
4
NC1
Line-2
2
HDMI1_CLK+_R
GND1
8
GND2
NC3
Line-4
3
GND1
NC2
Line-3
2
NC1
Line-2
HDMI1_CLK+_R 5
9
HDMI1_TX1-_R
D6
ME@
+5V_Power
TMDS_Data0+
TMDS_Data0TMDS_Data1+
TMDS_Data1TMDS_Data2+
TMDS_Data2-
2
2
100K_0402_5%
GND2
ALLTO_C128S9-K1935-L
For EMC
AZ1143-04F-R7G_DFN2510P10E10
AZ1143-04F-R7G_DFN2510P10E10
For EMC
AZ1143-04F-R7G_DFN2510P10E10
EMC_NS@
EMC_NS@
EMC_NS@
B
B
6
D1
2
2
1
NV
suggestion
RRE54
10K_0402_5%
2
S1
1
R10536
@ 0_0402_5%
1
1
2
RRE55
10K_0402_5%
G1
HDMI1_DAT_CON
+1.8VS_AON
R10535
0_0402_5%
1
@
2
AUX
+1.8VS_VGA
R10538
@ 0_0402_5%
1
R10537
0_0402_5%
1
@
2
+1.8VS_AON
2
+1.8VS_VGA
HDMI1_DAT {26}
G2
5
PJT7838_SOT363-6
Q37A
HDMI1_CLK_CON
3
Vgs(th)≤ 1V
D2
S2
4
HDMI1_CLK {26}
PJT7838_SOT363-6
Q37B
A
A
Security Classification
Issued Date
T itle
LC Future Center Secret Data
2015/08/20
Deciphered Date
HDMI_CONN
2018/09/20
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Size
D
Document Number
4
3
https://Dr-Bios.com
2
Rev
0.1
FG541/FG741
Friday, March 01, 2019
Date:
5
1
Sheet
39
of
69
5
4
3
2
1
D
D
C
C
B
B
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/08/20
P35-Blank
2018/09/20
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Size Document Number
Custom
Date:
5
4
3
https://Dr-Bios.com
2
R ev
0.1
FG541/FG741
Thursday, January 03, 2019
Sheet
1
40
of
69
4
3
2
JTAGX
R593 1
2 0_0402_5%
XDP_TMS
R594 1
2 0_0402_5%
XDP_TDI
CPU_TRST#
R595 1
2 0_0402_5%
XDP_TRST#
{16} PCH_TDI
DCI 2.0
w/o connector
{22} CPU_TRST#
2 0_0402_5%
R657 1
2 0_0402_5%
XDP_PRDY#
PCH_PREQ#
R658 1
2 0_0402_5%
XDP_PREQ#
{22} PCH_PRDY#
{22} PCH_PREQ#
VCCST
RC176
51_0402_1%
R217 1
@
2 0_0402_5%
TDI
PCH_TDO
R218 1
@
2 0_0402_5%
TDO
XDP_TDI
B
ASM
ASM
ASM
ASM
ASM
ASM
ASM
ASM
ASM
ASM
ASM
ASM
ASM
ASM
ASM
ASM
@
@
@
@
@
@
@
2
2
2
2
2
@
@
1
@
C70
0.1U_0402_25V6
PAD
TDI
TDO
1
@
PAD
PAD
PAD
PAD
1
1
1
1
@
IT22
@
IT23
@
IT24
@
IT25
PAD
PAD
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
1
1
@
IT26
@
IT27
1
@
IT21
IT16
R228 1
{6} CFG3
@
2 0_0402_5%
PAD
1
@
R229 1
@
2 1K_0402_5%
PAD
1
@
R230 1
EC_RSMRST#
DCI@ 2 0_0402_5%
PAD
1
@
PAD
PAD
1
1
@
IT32
@
IT33
IT29
IT30
IT31
need change to 1.5K refer CRB
place within 500mil of T-connection
B
{6} XDP_PRDY#
{6} XDP_PREQ#
R231 1
R232 1
@
@
2 0_0402_5%
2 0_0402_5%
Change XDP CONN to Test Point
HLZ SVD 0527
NO ASM
1
〃
〃
R10420
2.2K_0402_5%
@
R10419
1K_0402_5%
@
Place near PCH
PAD
{16,49} PBTN_OUT#
GPP_B18_NO_REBOOT
1
@
PAD
{18} SPI_SI_XDP
2
LOGIC
+3VALW
1
ASM
R563
1K_0402_5%
@
+3V_SPI
2
1
R563
GPP_B18_NO_REBOOT
0 = Disable
No Reboot
mode . (Default
)
1 = Enable
No Reboot
mod e (PC H wil l disabl e th e
TCO
Timer system reboot feature). This function is useful
when running ITP/XDP.
¨
*
TABLE : Functional Strap
¨
+3VS
Disable " No Reboot " Mode (Default )
1
PAD
XDP_TMS
XDP_TDI
XDP_TRST#
XDP_TDO
{16,49} SYS_PWROK
LOGIC
Enable " No Reboot " Mode
@
1K_0402_5%
R234
2 1K_0402_5%
2 1K_0402_5%
R220
R221
R222
R223
R224
Ref Y530 add 1207SF
LOW
C
2 0_0402_5%
2 0_0402_5%
1
1
1
1
1
R225 1
R226 1
PCH_TMS
ASM
ASM
ASM
ASM
ASM
ASM
ASM
ASM
HIGH
+1.05VALW
2
1
R4681
2.2K_0402_5%
@
2
2
DCI@
R233
51_0402_1%
R99 1
R219 1
{16} PCH_TCK
{6} XDP_TCK
DCI 2.0
w/o connector
GPP_B18/GSPI0_MOSI (No Reboot)
+3VALW
2
{16} SYS_RESET#
{18,28,37,42,45,49} PLT_RST#
{16,49} PCH_PWROK
{16} ITP_PMODE
NO
NO
NO
NO
NO
NO
NO
NO
+1.05VALW
VCCST
{16,49} EC_RSMRST#
NO
NO
NO
NO
NO
NO
NO
NO
Mount RC176 to enable
DCI function
R169
51_0402_1%
@
XDP_TMS
PCH_TDI
TABLE : PCH ITP DEBUG REPORT
R93
JXDP1
R9917
R101
R9908
R9911
R9913
R9915
1
DCI@
R168
51_0402_1%
@
LOGIC
Individual
Port
2
Delete R93
NO ASM
NO ASM
ASM
NO ASM
NO ASM
NO ASM
NO ASM
ASM
ASM
ASM
ASM
ASM
ASM
ASM
ASM
ASM
ASM
{6}
{6}
{6}
{6}
No use
Reference Intel document 546884 SKL PHG
1
JXDP1
C70
R96
R101
R9909
R9910
R9916
R99
R9912
R9934
R9930
R9931
R9932
R9933
ASM
ASM
ASM
ASM
ASM
ASM
ASM
ASM
ASM
ASM
ASM
ASM
ASM
ASM
ASM
ASM
ASM
1
R596 1
PCH_PRDY#
ASM
ASM
ASM
ASM
ASM
ASM
ASM
2
ASM
ASM
ASM
ASM
ASM
ASM
ASM
ASM
ASM
ASM
ASM
ASM
ASM
ASM
ASM
ASM
ASM
ASM
ASM
ASM
ASM
ASM
ASM
ASM
2
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
1
ASM
ASM
ASM
ASM
ASM
ASM
ASM
R102
R597
R9907
C
NO
NO
NO
NO
NO
NO
NO
D
R597
1K_0402_1%
@
XDP_TDO
2
PCH_TDO
{16} PCH_TDO
R591
R593
R594
R595
R596
R657
R658
{18} SPI_WP#
1
No use
XDP_TCK
{16} PCH_TMS
D
Individual
Port
2 0_0402_5%
PCH_TDI
TABLE : CPU ITP DEBUG REPORT
R591 1
PCH_TMS
{16} JTAGX
1
2
5
1
@
IT15
IT17
GPP_B18_NO_REBOOT {20}
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/08/20
Deciphered Date
https://Dr-Bios.com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
5
4
3
2
Blank
2018/09/20
Size
C
Date:
Document Number
Rev
0.1
FG541/FG741
Thursday, January 03, 2019
1
Sheet
41
of
69
5
4
3
2
1
+3VALW TO +3VALW_LAN
JL1
1
1
+3VALW_LAN rising t i m ( 10 %
e
~90 %
):
0.5ms＜ pec 10 0m s
s ＜
+3VALW_LAN
2 @
2
+3VALW_LAN
+LAN_VDDREG
width : 40 mils
RL1
1
JUMP_43X79
CL9
1
2
2
@
@
1/20W_47K_5%_0201
2
@
1
2
@
CL6
1
2
CL7
1
2
Close to Pin11 Close to Pin32 Close to Pin11
0.1u_0201_10V6K
1 CL8
1
CL5
0.1u_0201_10V6K
1
1 @
2
0.1u_0201_10V6K
1
2
@
2
3
G
RL3
1
{20,49} LAN_PWR_ON#
CL4
D
@
RL2
100K_0201_5%
S
Q14
4.7U_0402_6.3V6M
LP2301ALT1G_SOT23-3
4.7U_0402_6.3V6M
+3VALW
2
0_0603_5%
0.01U_0201_10V6K
D
@
CL1
4.7U_0402_6.3V6M
2
1
D
CL2
0.1u_0201_10V6K
2
Close to Pin32
+3VALW_LAN
+3VS
2
+3VALW_LAN
UL1
LAN_CLKREQ#_R
2
G
QL1
1
3
1
D
RL5
10K_0201_5%
1
2
@
RL4
10K_0201_5%
manual change the Codec PN to RTL8111H-CG_QFN32_4X4
@
{16,45,49} PCIE_WAKE#
{45,49} LAN_WAKE#
@
1
1
RL7
RL6
2 0_0201_5%
2 0_0201_5%
RL8
+3VS
1
LAN_PWR_ON# RL12 1
@
TL3 @ 1
2 0_0201_5%
TL4 @ 1
2
@
2 0_0201_5%
{18,28,37,41,45,49} PLT_RST#
{14} PCIE_PRX_DTX_N14
{14} PCIE_PRX_DTX_P14
LAN_PWR_ON#
CL10 1
CL11 1
33
32
31
30
29
28
27
LAN_DISABLE#
26
25
+LAN_REGOUT
24
+LAN_VDDREG
23
+LAN_VDD10
22
PCIE_WAKE#_R
21
20
ISOLATE#
PLT_RST#
19
PCIE_PRX_C_DTX_N14 18
PCIE_PRX_C_DTX_P14 17
+3VALW_LAN
RSET
+LAN_VDD10
LAN_XTALO
LAN_XTALI
1
2
2.49K_0402_1%
RL9
1K_0402_1%
1
LAN_CLKREQ#
{17}
2N7002KW_SOT323-3
PCIE_WAKE#_R
C
ISOLATE# RL10
@
S
Need short
+3VALW
2 0.1u_0201_10V6K
2 0.1u_0201_10V6K
GND
AVDD33_2
RSET
AVDD10
CKXTAL2
CKXTAL1
LED0
LED1/GPIO
LED2
REGOUT
VDDREG
DVDD10
LANWAKEB
ISOLATEB
PERSTB
HSON
HSOP
REFCLK_N
REFCLK_P
HSIN
HSIP
CLKREQB
AVDD33_1
MDIN3
MDIP3
AVDD10_2
MDIN2
MDIP2
MDIN1
MDIP1
AVDD10_1
MDIN0
MDIP0
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
RL18 1
CLK_PCIE_LAN#
CLK_PCIE_LAN
PCIE_PTX_C_DRX_N14
PCIE_PTX_C_DRX_P14
LAN_CLKREQ#_R
+3VALW_LAN
LAN_MDI3LAN_MDI3+
+LAN_VDD10
LAN_MDI2LAN_MDI2+
LAN_MDI1LAN_MDI1+
+LAN_VDD10
LAN_MDI0LAN_MDI0+
CLK_PCIE_LAN# {17}
CLK_PCIE_LAN {17}
PCIE_PTX_C_DRX_N14
PCIE_PTX_C_DRX_P14
@
2 0_0201_5%
C
{14}
{14}
LAN_MDI3- {43}
LAN_MDI3+ {43}
LAN_MDI2LAN_MDI2+
LAN_MDI1LAN_MDI1+
{43}
{43}
{43}
{43}
LAN_MDI0- {43}
LAN_MDI0+ {43}
1
CL10 close to Pin18
CL11 close to Pin17
2
RL11
15K_0201_1%
@
RTL8111GUL-CG QFN 32P
@
B
B
LAN_XTALI
LAN_XTALO_R
1
2
RL21 1K_0402_5%
For RTL8111GUL(SWR mode, reserved)
For RTL8111H (LDO mode)
LAN_XTALO
+LAN_VDD10
YL1
1
2
1
CL12
15P_0402_50V8J
2
LL1
OSC1
GND2
GND1
OSC2
4
+LAN_REGOUT
1
2 8111GUL@
2.2UH_NLC252018T-2R2J-N_5%
RL20
3
25MHZ_10PF_7V25000014
1
1
2
0_0805_5%
8111H@
1 8111H@
CL13
15P_0402_50V8J
1124SF Add CL33
close to pin
2
2
CL33
0.1u_0201_10V6K
1
CL15
4.7U_0402_6.3V6M
2
1
2
1
CL16
0.1u_0201_10V6K
2
1
CL17
0.1u_0201_10V6K
2
1
CL18
0.1u_0201_10V6K
1
1
CL19
CL20
0.1u_0201_10V6K 0.1u_0201_10V6K
2
2
2
Close to Pin3, 8, 22, 30
21180125SF Add D65 For EMC
Need change to AZ5815/
EMC_8111H@
D65
SC40000BM00, S DIO_ESD
AZ5825-01F.R7GR DFN1006P2E
AZ5815-01F.R7GR DFN1006P2E, A.2,EG531
1
1
+LAN_VDD10
2
CL22
0.1u_0201_10V6K
Close to Pin22(Reserved)
Layout Note: LL1 must be
within 200mil to Pin24,
CL15,CL16 must be within
200mil to LL1
+LAN_REGOUT: Width =60mil
A
2
2
A
1
CL21
1U_0402_6.3V6K
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/08/20
LAN_RTL8111H_CG
2018/09/20
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Size Document Number
Custom
Date:
5
4
https://Dr-Bios.com
3
2
R ev
0.1
FG541/FG741
Wednesday, February 27, 2019
1
Sheet
42
of
69
3
{42} LAN_MDI0-
LAN_MDI0-
22
21
{42} LAN_MDI1+
{42} LAN_MDI1-
LAN_MDI1+
20
LAN_MDI1-
19
18
{42} LAN_MDI2+
DL1
LAN_MDI3+
4
5
{42} LAN_MDI2-
LAN_MDI2-
3
{42} LAN_MDI3+
2
6
LAN_MDI2+
1
2
AZ1513-04S.R7G SOT23
EMC_8111H@
C
17
LAN_MDI2-
16
15
1
LAN_MDI3-
LAN_MDI2+
{42} LAN_MDI3-
LAN_MDI3+
14
LAN_MDI3-
13
CL24
0.01U_0201_25V6-K
EMC_GST@
@
MCT1
TCT1
MX1+
TD1+
MX1-
TD1-
MCT2
TCT2
MX2+
TD2+
MX2-
TD2-
MCT3
TCT3
MX3+
TD3+
MX3-
TD3-
MCT4
TCT4
MX4+
TD4+
MX4-
TD4-
1
MCT
2
LAN_MDO0+
3
LAN_MDO0-
4
MCT
5
LAN_MDO1+
6
LAN_MDO1-
7
MCT
8
LAN_MDO2+
9
LAN_MDO2-
10
MCT
11
LAN_MDO3+
12
LAN_MDO3-
EMC_GST@
RL17
20_0603_5%
D
1
20180125SF:For EMC debug DL1 & DL2
Need change to SC300006100,
S DIO(BR) AZ1135-04S.R7G SOT23, A.1,EG531
23
1
{42} LAN_MDI0+
LAN_MDI0+
2
D
TL1
24
TCT
1
DL3
PDT5061_DO-214AA
EMC_GST@
EMC
2
0907SF change DL1/DL2 to
S DIO(BR) AZ1215-04S.R7G SOT23-6L
PN:SC300005900 for 8111H
2
1
4
2
5
CL32
0.022U_0603_50V7K
EMC_GST@
1
1
2
2
CL25
1000P_1206_2KV7-K
EMC_GST@
EMC
BOTH_GST5009 LF
C
EMC
CHASSIS1_GND
DL2
LAN_MDI1+
4
5
Add TL2 co-lay TL1 1009SF
LAN_MDI0-
3
2
TL2
24
TCT
LAN_MDI0+
LAN_MDI1-
6
LAN_MDI0-
LAN_MDI0+
1
23
22
21
AZ1513-04S.R7G SOT23
LAN_MDI1+
20
LAN_MDI1-
EMC_8111H@
19
18
B
LAN_MDI2+
Place Close to TL1
17
LAN_MDI2-
EMC
16
15
LAN_MDI3+
1204SF update,
4 R-Short place on DC-IN CONN & LAN CONN,
2 R-Short place on LAN CONN & HDMI CONN
RL14 1
RL15 1
RL16 1
RL22 1
A
RL23 1
RL24 1
14
LAN_MDI3-
13
@
TCT1
GND
TD1+
MX1+
TD1-
MX1-
TCT2
NC1
TD2+
MX2+
TD2-
MX2-
TCT3
NC2
TD3+
MX3+
TD3-
MX3-
TCT4
NC3
TD4+
MX4+
TD4-
MX4-
1
MCT
2
LAN_MDO0+
3
LAN_MDO0-
JRJ1
4
GND_3
5
LAN_MDO1+
6
LAN_MDO1-
LAN_MDO0+
1
LAN_MDO0-
2
LAN_MDO1+
3
LAN_MDO2+
4
LAN_MDO2-
5
LAN_MDO1-
6
LAN_MDO3+
7
LAN_MDO3-
7
8
LAN_MDO2+
8
LAN_MDO2-
9
10
11
LAN_MDO3+
12
LAN_MDO3-
GND_2
TX_DA+
GND_1
12
11
10
9
TX_DAB
RX_DB+
CHASSIS1_GND
BI_DC+
BI_DCRX_DBBI_DD+
BI_DD-
AJOHO_N-8660GR
ALLTO_C10235-10839-L
@
2 0_0603_5%
@
2 0_0603_5%
@
2 0_0603_5%
@
2 0_0603_5%
Don't short
J13
1
MCT
@
1
2
8/16 Update RJ45 P/N DC021608091 wei
2
JUMP_43X79
@
2 0_0603_5%
@
2 0_0603_5%
CHASSIS1_GND
Issued Date
A
Title
LC Future Center Secret Data
Security Classification
EMC
2015/08/20
Deciphered Date
CHASSIS1_GND
LAN_Transformer
2018/09/20
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Size
B
Date:
5
ME@
GND_4
4
3
https://Dr-Bios.com
2
Document Number
Re v
0.1
FG541/FG741
Saturday, February 02, 2019
Sheet
1
43
of
69
4
3
R177 1
REMOTE-_R
R178 1
@
@
2 0_0402_5%
C45
100P_0201_25V8J
@
REMOTE2-
2 0_0402_5%
REMOTE1-
1
2
B
2
E
REMOTE1-
C46
100P_0201_25V8J
@
C
Q15
MMBT3904WH_SOT323-3
@
3
2
1
@
10K_0402_5%
D+
4
SDA
D-
ALERT#
T_CRIT#
GND
1
1
1
EC_SMB_CK2
7
EC_SMB_DA2
R288
100K_0402_1%_NCP15WF104F03RC
EC_SMB_CK2 {16,28,49}
2
C47
0.1u_0201_10V6K
@
2
R51
+3VS
8
R287
100K_0402_1%_NCP15WF104F03RC
2
REMOTE-_R
1
SCL
R25
13.7K_0402_1%
NTC_V2
@
VDD
D
Near CPU
EC_SMB_DA2 {16,28,49}
6
2
U1
E
2
NTC_V1
+3VS
2
Q16
MMBT3904WH_SOT323-3
@
B
2
REMOTE2-
R36
13.7K_0402_1%
1
C
2
+3VALW
SMSC thermal sensor
placed near DIMM
REMOTE+_R
Near CPU core
1
+3VALW
REMOTE+/-_R, REMOTE1+/-, REMOTE2+/-:
Trace width/space:10/10 mil
Trace length: & lt; 8 "
D
REMOTE2+
Near GPU & VRAM
REMOTE1+
1
REMOTE2+
3
REMOTE-_R
2
2 0_0402_5%
1
1
C44
2200P_0201_25V7-K
@
@
2
REMOTE1+
R176 1
REMOTE+_R
REMOTE+_R
1
2 0_0402_5%
2
Close to U1
@
1
R175 1
3
5
5
@
R184
0_0402_5%
1
NCT7718W_MSOP8
Address 1001_101xb
for layout optimized, change the EC_AGND to
GND
C
+5VLP
C
+5VLP
3
{49,60,61} EC_ON
4
1
@
VCC TMSNS1
GND RHYST1
OT1 TMSNS2
OT2 RHYST2
8
PHYST1
6
PHYST2
R6
R7
1
1
@
@
@
2 0_0402_5%
NTC_V1
R197 1
TMSNS2
5
R196 1
TMSNS1
7
@
2 0_0402_5%
NTC_V2
R10530
13.7K_0402_1%
NTC_V1 {49}
2 10K_0402_5%
2
2
NTC_V2 {49}
NTC_V3
NTC_V3 {49}
1
U4
1
+3VALW
R253
21.5K_0402_1%
@
1
R252
21.5K_0402_1%
@
C7
0.1u_0201_10V6K
@
1
2
2
HW thermal sensor
1
2
+5VLP
2 10K_0402_5%
R10529
100K_0402_1%_NCP15WF104F03RC
2
@
R10528
0_0402_5%
B
1
B
2
G718TM1U_SOT23-8
over temperature threshold:
RSET=3*RTMH
92+/-30C
Hysteresis temperature threshold.
RHYST=(RSET*RTML)/(3*RTML-RSET)
56+/-30C
FAN Conn
need check ME SDV CONN list
Change to SP011411114 ref ME conn list,20181017SF update
0.5A
ME@ JFAN1
ACES_50228-00871-001
+5VS
R52
1
C49
10U_0805_10V6K
0.5A
1
@
C50
.1U_0402_10V6-K
@
2
+5VS_FAN1
2 0_0603_5%
1
2
8
7
6
5
4
3
2
1
{49} EC_FAN1_SPEED
{49} EC_FAN1_PWM
{49} EC_FAN2_PWM
{49} EC_FAN2_SPEED
+5VS
A
R75
1
C81
10U_0805_10V6K
1
@
GND2
GND1
10
9
A
+5VS_FAN2
2 0_0603_5%
C60
.1U_0402_10V6-K
@
2
8
7
6
5
4
3
2
1
1
Title
LC Future Center Secret Data
Security Classification
2
Issued Date
2016/08/16
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
5
4
https://Dr-Bios.com
3
Thermal sensor/FAN CONN
2018/09/20
2
Size Document Number
Custom
Date:
Rev
0.1
FG541/FG741
Tuesday, February 26, 2019
Sheet
1
44
of
69
A
B
C
D
E
+3VS_WLAN
1
1
RC832
RC833
+3VS +3VALW
for wlan
+3VS_WLAN
2 10K_0402_5%
2 10K_0402_5%
PCH_WLAN_OFF#
PCH_BT_OFF#
1
Mini-Express Card(WLAN/WiMAX)
1
1
2
{19} USB20_P14
{19} USB20_N14
CNVI_WR_D1_N
CNVI_WR_D1_P
1
{19} CNVI_WR_D1_N
{19} CNVI_WR_D1_P
WLAN_PWR_EN
OCB
3
S
2
1
1
G
R2226
75K_0402_5%
@
R2229
200K_0402_5%
@
R2234
@
@
2 0_0402_5%
2 0_0402_5%
R10373 1
R10374 1
CNVI_WR_CLK_N
CNVI_WR_CLK_P
{19} CNVI_WR_CLK_N
{19} CNVI_WR_CLK_P
1
R10371 1
R10372 1
CNVI_WR_D0_N
CNVI_WR_D0_P
{19} CNVI_WR_D0_N
{19} CNVI_WR_D0_P
2
0.01_0603_1%
@
3
SY6288C20AAC_SOT23-5
@
1
0.1u_0201_10V6K
EN
2
1
4
1
2 0_0402_5%
2 0_0402_5%
@
@
2 0_0402_5%
2 0_0402_5%
+3VS
+3VS_WLAN
WLAN
R2072
10K_0402_5%
2
@
Q165
{14} PCIE_PTX_C_DRX_P13
{14} PCIE_PTX_C_DRX_N13
1
2 0_0402_5%
R2233
1
@
WLAN
1
{14} PCIE_PRX_DTX_P13
{14} PCIE_PRX_DTX_N13
2 0_0402_5%
L2N7002KWT1G_SOT323-3
{17} CLK_PCIE_WLAN
{17} CLK_PCIE_WLAN#
R61
{17} WLAN_CLKREQ#
1
WLAN_CLKREQ_Q#
2 0_0402_5%
{16,42,49} PCIE_WAKE#
change WLAN CLKREQ# PH power source 0329SF
If support AOAC, NC R61;
if not support AOAC, stuff R61.
{19} CNVI_WT_D1_N
{19} CNVI_WT_D1_P
{19} CNVI_WT_D0_N
{19} CNVI_WT_D0_P
{19} CNVI_WT_CLK_N
{19} CNVI_WT_CLK_P
KEY E
PIN24~PIN31 NC PIN
25
27
29
31
D
@
3.3VAUX1
3.3VAUX2
LED1#
PCM_CLK/I2S_SCK
PCM_SYNC/I2S_WS
PCM_IN/I2S_SD_IN
PCM_OUT/I2S_SD_OUT
LED#2
GND11
UART_WAKE#
UART_RXD
1
@
R258
49.9K_0402_1%
T2
1
R10381
@
@
1
R10392
1
@
2 0_0402_5%
2 0_0402_5%
CNVI_RF_RESET#
CNVI_MODEM_CLKREQ
T3
UART_RX_DEBUG_R
@
R256 1
{42,49} LAN_WAKE#
CNVI_WT_D1_N
CNVI_WT_D1_P
R262 1 AOAC@ 2 0_0402_5%
R57
1
@
PCIE_WAKE#_WLAN
33
35
37
39
41
43
45
47
49
51
53
55
57
2 0_0402_5%
CNVI_WT_D1_R_N
CNVI_WT_D1_R_P
R10380 1
R10379 1
@
@
2 0_0402_5%
2 0_0402_5%
CNVI_WT_D0_N
CNVI_WT_D0_P
R10378 1
R10377 1
@
@
2 0_0402_5%
2 0_0402_5%
CNVI_WT_D0_R_N
CNVI_WT_D0_R_P
CNVI_WT_CLK_N
CNVI_WT_CLK_P
R10376 1
R10375 1
@
@
2 0_0402_5%
2 0_0402_5%
CNVI_WT_CLK_R_N
CNVI_WT_CLK_R_P
59
61
63
65
67
69
71
73
75
77
GND3
PETP0
PETN0
GND4
PERP0
PERN0
GND5
REFCLKP0
REFCLKN0
GND6
CLKREQ0#
PEWAKE0#
GND7
RSRVD/PETP1
RSRVD/PETN1
GND8
RSRVD/PERP1
RERVD/PERN1
GND9
RSRVD/REFCLKP1
RSRVD/REFCLKN1
GND10
24
26
28
30
UART_TXD
UART_CTS
UART_RTS
VENDOR_DEFINED1
VENDOR_DEFINED2
VENDOR_DEFINED3
COEX3
COEX2
COEX1
SUSCLK
PERST0#
W_DISABLE2#
W_DISABLE1#
I2C_DATA
I2C_CLK
ALERT#
RSRVD
UIM_SWP/PERST1#
UIM_POWER_SNK/CLKREQ1#
UIM_POWER_SRC/GPIO1/PEWAKE1#
3.3VAUX3
3.3VAUX4
GND15
GND14
1
R10383
{16}
PCH_UART2_RXD {20}
CNVI_BRI_RSP
CNVI_RGI_DT
@
2 0_0402_5%
R257 1
R10385 1 CNVI@ 2 22_0402_5%
{19}
{19}
UART_TX_DEBUG_R
32
34
36
38
40
42
44
46
48
50
52
54
56
EC_TX_RSVD
EC_RX_RSVD
R62
R63
@
2 0_0402_5%
1
1
@
2 1K_0402_5%
2 0_0402_5%
R58
R59
1
1
@
@
2 0_0402_5%
2 0_0402_5%
R89
58
60
62
64
66
68
70
72
74
1
1
@
PCH_UART2_TXD {20}
2 0_0402_5%
2 0_0402_5%
R53
R56
WLAN_SMB_DATA
WLAN_SMB_CLK
@
@
R55
SUSCLK_R
PLT_RST#
BT_OFF#
WLAN_OFF#
1
1
CNVI_RGI_RSP {19}
CNVI_BRI_DT {19}
2 0_0402_5%
SUSCLK {16}
PLT_RST# {18,28,37,41,42,49}
PCH_BT_OFF# {20}
PCH_WLAN_OFF# {20}
EC_RX {46,49}
EC_TX {46,49}
CLKIN_XTAL_LCP {17}
R186
100K_0402_5%
76
PLT_RST#
ARGOS_NASE0-S6701-TS40
2
R259
49.9K_0402_1%
2 0_0402_5%
2 0_0402_5%
@
{16}
1
1
1
2
4
6
8
10
12
14
16
18
20
22
R10382 1 CNVI@ 2 22_0402_5%
S
1
CNVI_WGR_CLK_R_N
CNVI_WGR_CLK_R_P
ME@
GND1
USB_D+
USB_DGND2
SDIO_CLK
SDIO_CMD
SDIO_DATA0
SDIO_DATA1
SDIO_DATA2
SDIO_DATA3
SDIO_WAKE#
SDIO_RESET#
C53
G
{49,51,60} SUSP#
R2223
CNVI_WGR_D0_R_N
CNVI_WGR_D0_R_P
1
3
5
7
9
11
13
15
17
19
21
23
@
2
3
{16} PM_SLP_WLAN#
CNVI_WGR_D1_R_N
CNVI_WGR_D1_R_P
1
OUT
GND
@
@
2
IN
2
5
2
U4403
R2225
75K_0402_5%
@
R10369 1
R10370 1
2
2
@
2
R10506
0.01_0603_1%
2
JWLAN1
1
+3VALW
{15} CNVI_EN#
@
2 C10128
10U 6.3V M X5R 0402
JUMP_43X79
+3VALW
Q2202
2N7002KW_SOT323-3
@
1
@
@
2 C10137
2 C10127
0.1u_0201_10V6K 1U_0402_6.3V6K
@
2
1
D
1
+3VS
J15
change WLAN common design SCH_SF20180719
2
+3VS_WLAN
same power source issue 0719SF
1
+3VS_WLAN
8/16 Update Conn. P/N SP070013200 wei
2
C381
1000P_0402_50V7K
2
@
1
1
2
C10135
10U 6.3V M X5R 0402
2
C10136
C10134
0.1u_0201_10V6K
2
1U_0402_6.3V6K
1
M.2 SSD(SATA/PCIE)
NEW
HLZ SDV 0601
{14} PCIE_SATA_PRX_DTX_P12
{14} PCIE_SATA_PRX_DTX_N12
PCIE_SATA_PTX_DRX_N12
PCIE_SATA_PTX_DRX_P12
0.22U_0402_10V6K
0.22U_0402_10V6K
PCIE_PTX_DRX_N9_C
PCIE_PTX_DRX_P9_C
PCIE_PRX_DTX_N10
PCIE_PRX_DTX_P10
CC166
CC1317
2
2
1
1
CC168
CC169
2
2
1 0.22U_0402_10V6K
1 0.22U_0402_10V6K
2
2
1
1
0.22U_0402_10V6K
0.22U_0402_10V6K
PCIE_PTX_DRX_N10_C
PCIE_PTX_DRX_P10_C
PCIE_PRX_DTX_N11
PCIE_PRX_DTX_P11
PCIE_PTX_DRX_N11_C
PCIE_PTX_DRX_P11_C
PCIE_SATA_PRX_DTX_P12
PCIE_SATA_PRX_DTX_N12
CC39
CC165
0.22U_0402_10V6K
0.22U_0402_10V6K
{17} CLK_PCIE_SSD#
{17} CLK_PCIE_SSD
PCIE_SATA_PTX_DRX_N12_C
PCIE_SATA_PTX_DRX_P12_C
CLK_PCIE_SSD#
CLK_PCIE_SSD
59
61
63
65
SSD_DET
67
69
71
73
75
77
NC
NC
NC
NC
NC
NC
NC
NC
N/C_1
PEDET
GND_12
GND_13
GND_14
PEG1
SUSCLK
3.3V_7
3.3V_8
3.3V_9
PEG2
2
1
3
C238
.1U_0402_10V6-K
+3.3V_NGFF
R4679
10K_0402_5%
@
DEVSLP0_R
DEVSLP0_R
1
2
R4678
0_0402_5%
@
DEVSLP0
R4680
10K_0402_5%
PLT_RST#
SSD_CLKREQ#
SSD_CLKREQ# {17}
1
TP76
@
60
62
64
66
+3.3V_NGFF
+3.3V_NGFF
68
70
72
74
76
R274
10K_0402_5%
1
ARGOS_NASM0-S6701-TS20
2
ME@
Add C927 due to signal waveform abnormal
HLZ SIV 0811
PLT_RST#
1
2
1
2
SSD_DET
2 0_0402_5% SSD_DET#
R249 1
For optane
SSD_DET# {14}
PEDET (PE_DTCT)
SATA Device
GND
PCIe Device
Open
R290
10K_0402_5%
@
SSD_DET#
0 - SATA
1 - PCIE
4
1
DEVSLP0 {15}
Ac coupling-Cap place near NGFF CONN within 500mil
1
{14} PCIE_SATA_PTX_DRX_N12
{14} PCIE_SATA_PTX_DRX_P12
{14} PCIE_PRX_DTX_N11
{14} PCIE_PRX_DTX_P11
PCIE_PTX_DRX_N11
PCIE_PTX_DRX_P11
1
1
2
{14} PCIE_PTX_DRX_N11
{14} PCIE_PTX_DRX_P11
{14} PCIE_PRX_DTX_N10
{14} PCIE_PRX_DTX_P10
PCIE_PTX_DRX_N10
PCIE_PTX_DRX_P10
2
2
CC170
CC171
1
{14} PCIE_PTX_DRX_N10
{14} PCIE_PTX_DRX_P10
{14} PCIE_PRX_DTX_N9
{14} PCIE_PRX_DTX_P9
PCIE_PTX_DRX_N9
PCIE_PTX_DRX_P9
2
{14} PCIE_PTX_DRX_N9
{14} PCIE_PTX_DRX_P9
+3.3V_NGFF
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
2
2
3.3V_1
3.3V_2
N/C_2
N/C_3
DAS/DSS#/LED1#
3.3V_3
3.3V_4
3.3V_5
3.3V_6
N/C_4
N/C_5
N/C_6
N/C_7
N/C_8
N/C_9
N/C_10
N/C_11
N/C_12
DEVSLP
N/C_13
N/C_14
N/C_15
N/C_16
N/C_17
PERST#
CLKREQ#
PEWAKE#
NC18
NC19
1
1
GND_1
GND_2
PERN3
PERP3
GND_3
PETN3
PETP3
GND_4
PERN2
PERP2
GND_5
PETN2
PETP2
GND_6
PERN1
PERP1
GND_7
PETN1
PETP1
GND_8
PERN0/SATA-B+
PERP0/SATA-BGND_9
PETN0/SATA-APETP0/SATA-A+
GND_10
REFCLKN
REFCLKP
GND_11
C107
22U_0603_6.3V6-M
2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
2
HLZ SDV 0616
PCIE_PRX_DTX_N9
PCIE_PRX_DTX_P9
1
2
Change 0805 to Jump
C241
3
1
.1U_0402_10V6-K
CD@
+3.3V_NGFF
1
C106
.1U_0402_10V6-K
2
C240
4.7U_0402_6.3V6M
CD@
2
JUMP_43X79
@
C239
22U_0603_6.3V6-M
1
JSSD1
2A
J8
1
C237
.1U_0402_10V6-K
+3VS
4
C927
1000P_0402_50V7K
2
Security Classification
Issued Date
T itle
LC Future Center Secret Data
2016/12/14
Deciphered Date
NGFF WLAN & SSD
2018/09/20
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Size
D
Document Number
B
C
https://Dr-Bios.com
D
Rev
0.1
FG541/FG741
Tuesday, February 26, 2019
Date:
A
E
Sheet
45
of
69
A
B
C
D
E
+USB_VCCA
C1117
@
1
2
IN
OUT
C128
1U_0402_6.3V6K
GND
4
{49} USB_ON#
ENB
OCB
2
47U_0805_6.3V6-M
1
2
1U_0402_10V6K
C127
@
+USB_VCCA
U2
1
C125
@
+5VALW
5
2
220U_6.3V_M
+
1
C55
LEFT SIDE USB3.0 PORT x2
1
2
1U_0402_10V6K
1
JUSB1
2
USB30_TX_P1
USB_OC1#
3
Low Active 2A
1
2
{15} USB30_TX_N1
{19} USB20_P1
C140
1000P_0201_50V7-K
EMC_NS@
USB30_TX_C_P1
USB30_RX_N1
{15} USB30_RX_N1
2 0_0402_5%
R96 1
R97 1
USB30_TX_C_N1
@
@
@
2 0_0402_5%
2 0_0402_5%
USB30_TX_R_N1
USB20_P1_R
@
@
2 0_0402_5%
2 0_0402_5%
USB20_N1_R
USB30_RX_R_P1
R98 1
2 0.1u_0201_10V6K
USB20_N1
USB30_RX_P1
{19} USB20_N1
{15} USB30_RX_P1
USB30_TX_R_P1
R95 1
R93 1
R94 1
2 0.1u_0201_10V6K
USB30_TX_N1
C124 1
USB20_P1
USB_OC1# {19}
SY6288D20AAC_SOT23-5
1
C126 1
{15} USB30_TX_P1
@
2 0_0402_5%
9
1
8
3
7
2
6
4
5
USB30_RX_R_N1
ME@
StdA_SSTX+
VBUS
StdA_SSTXD+
GND_DRAIN
DStdA_SSRX+
GND_1
StdA_SSRX-
1
GND_2
GND_3
GND_4
GND_5
10
11
12
13
ALLTO_C190AG-10939-L
09/05 Update USBConn. P/N DC021609011 wei
1
4
3
3
USB30_RX_R_N1
USB30_RX_R_N110
USB30_RX_R_P1
USB30_RX_R_P1
USB20_P1_R
USB30_TX_C_P1
4
USB20_P1
4
1
4
3
USB30_TX_R_N1
3
USB30_TX_R_P1
3
USB20_P1_R
EXC24CH900U_4P
EXC24CH900U_4P
USB20_N1
1
4
3
1
L8
2
EMC@
2
USB20_N1_R
D11
EMC@
NC1
Line-3
NC4
Line-4
USB30_RX_R_P1
2
USB30_TX_R_N1
4
USB30_TX_R_P1
5
3
GND1
D13
AZC199-02S.R7G_SOT23-3
EMC@
USB30_RX_R_N1
1
Line-2
NC3
7
Line-1
NC2
USB30_TX_R_P1 6
3
EMC_NS@
2
2
USB20_N1_R
D12
9
8
GND2
AZ1143-04F-R7G_DFN2510P10E10
EMC_NS@
1
1
AZ5725-01F.R7GR_DFN1006P2X2
L16
USB30_TX_C_N1
USB30_TX_R_N1
+USB_VCCA
2
EXC24CH900U_4P
1
4
1
1
USB30_RX_P1
2
USB30_RX_N1
EMC_NS@
2
2
2
L13
EMC
EMC
+USB_VCCA
2
2
1
C2059
@
USB30_TX_P3
C2058 1
2 0.1u_0201_10V6K
USB30_TX_C_P3 R3119
1
@
2 0_0402_5%
USB30_TX_N3
C2057 1
USB20_P3_S
2 0.1u_0201_10V6K
USB30_TX_C_N3 R3116 1
R3103 1
@
@
2 0_0402_5%
2 0_0402_5%
R942 1
R3117 1
@
@
2 0_0402_5%
2 0_0402_5%
R3114 1
@
2 0_0402_5%
{15} USB30_TX_P3
USB30_RX_P3
4
4
3
3
USB30_RX_R_P3
{15} USB30_TX_N3
EXC24CH900U_4P
USB30_TX_C_N3
L29
1
USB30_TX_C_P3
4
USB20_P3_S
4
1
USB20_N3_S
USB30_RX_P3
EMC_NS@
2
2
4
{15} USB30_RX_P3
USB30_TX_R_N3
USB20_P3_R
USB30_TX_R_P3
9
1
8
3
7
2
6
4
5
USB30_TX_R_N3
USB20_P3_R
USB20_N3_R
USB30_RX_R_P3
USB30_RX_R_N3
USB30_TX_R_P3
3
3
USB30_RX_N3
{15} USB30_RX_N3
3
6
10
11
12
13
1
D34
Line-1
NC2
Line-2
NC3
Line-3
NC4
Line-4
GND1
EMC_NS@
GND2
1
USB30_RX_R_N3
2
USB30_RX_R_P3
4
5
UARTA_P80_EN
USB30_TX_R_N3
EMC@
USB30_TX_R_P3
3
8
@
2
2
AZ1143-04F-R7G_DFN2510P10E10
D64
USB_NS@
R538
100K_0402_5%
1
USB30_TX_R_P3
7
EMC@
NC1
AZ5725-01F.R7GR_DFN1006P2X2
D43
AZC199-02S.R7G_SOT23-3
EMC@
D45
9
2
EMC@
AZ5725-01F.R7GR_DFN1006P2X2
USB20_N3_R
2
2
2
3
1
L17
1
1
USB30_TX_R_N3
1
USB30_RX_R_P3
1
USB30_RX_R_N3 10
+USB_VCCA
USB20_N3_R
USB20_N3_S
GND_2
GND_3
GND_4
GND_5
09/05 Update USBConn. P/N DC021609011 wei
Close to Connector
USB20_P3_R
2
3
R537
0_0402_5%
FOR ESD
4
ME@
StdA_SSTX+
VBUS
StdA_SSTXD+
GND_DRAIN
DStdA_SSRX+
GND_1
StdA_SSRX-
ALLTO_C190AG-10939-L
EXC24CH900U_4P
EXC24CH900U_4P
2
1U_0402_10V6K
JUSB3
USB30_RX_R_N3
1
EMC_NS@
2
2
2
1
1
L30
1
2
USB30_RX_N3
2
1U_0402_10V6K
1
C2060
@
09/20SF Update USB debug CONN GND pin follow TINY5
3
3
For USB Debug Function
09/20SF add USB debug follow TINY5
change from SA00007WL0D to SA00007WL00 SF1001
SVT non-staff0322SF
USB_UART_SEL
2
1
R531
1/16W_0_5%_0402
USB_NS@
USBDEBUG
1
+3VALW
USB_NS@
R547
1/16W_10K_5%_0402
U3
2
{45,49} EC_TX
USB_UART_SEL
{45,49} EC_RX
R533 2
USB_NS@
SOUTA_C 1
1 1/16W_0_5%_0402
SINA_C
USB_NS@
1 1/16W_0_5%_0402
R536 2
1
D
2
4
{19} USB20_N3
L2N7002KWT1G_SOT323-3
Q56
3
G
S
2
3
{19} USB20_P3
UARTA_P80_EN
5
11
USB_NS@
Kernel debug
Set input
{20} USBDEBUG
+3VALW
Set input
Set output Low
ENABLE
USB_NS@
1D+
VCC
1D-
S
2D+
NCY3958Y
2D-
D+
D-
GND1
OE#
10
9
USB_UART_SEL
8
UARTA_P80_EN
POST 80
USB20_P3_S
7
USB20_N3_S
Set input
DISABLE
Set output Low
ENABLE
6
GND2
4
4
NCT3958Y_DFN10_3X3
OE#
S
FUNCTION
H
2
R539
@
1
0_0402_5%
USB20_P3_S
USB20_N3
2
R541
@
1
L
L
D(+/-) to 1D(+/-)
L
USB20_P3
X
DISABLE
H
D(+/-) to 2D(+/-)
0_0402_5%
USB20_N3_S
Security Classification
Issued Date
T itle
LC Future Center Secret Data
2015/08/20
Deciphered Date
USB3.0 PORT (LEFT)
2018/09/20
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Size
D
Document Number
B
C
https://Dr-Bios.com
D
Rev
0.1
FG541/FG741
Friday, March 01, 2019
Date:
A
E
Sheet
46
of
69
A
B
C
D
E
F
G
H
SATA HDD Conn.
ME@
ELCO_006809610010846
1
SATA_PTX_DRX_P0
SATA_PTX_DRX_N0
{14} SATA_PRX_DTX_N0
{14} SATA_PRX_DTX_P0
1
2
C74
33P_0201_50V8-J
RF@
1
2
C76
33P_0201_50V8-J
RF@
1
C75
0.1u_0201_10V6K
2
1
2
C77
10U_0805_10V6K
1
2
C78
10U_0805_10V6K
@
1
1
2 0.01U_0201_10V6K
2 0.01U_0201_10V6K
SATA_PTX_C_DRX_P0
SATA_PTX_C_DRX_N0
SATA_PRX_DTX_N0
SATA_PRX_DTX_P0
{14} SATA_PTX_DRX_P0
{14} SATA_PTX_DRX_N0
+5VS_HDD
C66
C67
C68
C69
1
1
2 0.01U_0201_10V6K
2 0.01U_0201_10V6K
1
2
3
4
5
6
7
8
9
10
SATA_PRX_C_DTX_N0
SATA_PRX_C_DTX_P0
+5VS
Need short
+5VS_HDD
1
2
3
4
5
6
7
8
9
10
GND1
GND2
1
11
12
JHDD1
J3
1
1
2
2 @
JUMP_43X79
For EMC
2
2
Delete SATA ODD
8/14 Update SF
3
3
4
4
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/08/20
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
A
B
C
https://Dr-Bios.com
D
E
HDD/ODD CONN
2018/09/20
Deciphered Date
Size Document Number
Custom
F
G
R ev
0.1
FG541/FG741
Thursday, January 03, 2019
Date:
Sheet
47
H
of
69
5
4
3
2
1
VBUS_P0
+5VALW
1
EC_VBUS_EN 2
R118
@
{49} EC_VBUS_EN
+
1
0_0402_5%
3
8
2
R103
100K_0402_1%
10
13
IN1
IN2
OUT
FAULT
EN
CC2
CHG
CC1
REF
SINK
GND1
GND2
POL
12
5
FAULT#
11
SINK#
7
POL#
2
TYPE_C_OCP# {19}
R10527
SINK#
POL#
@
1 0_0402_5%
R10507
2
@
1 0_0402_5%
2
TYPE_C_DFP {49}
TYPE_C_ST {49}
R10508
1
TPS25820DSSR_WSON12_3X2
D
FAULT#
1 0_0402_5% TYPE_C_OCP#
CC1
6
2
CC2
9
@
2
2
4
2
2A_32V_ERBRD2R00X
1
1
2
2
1
2
@
150U_B2_6.3VM_R35M
C1333
1
2
C213
22U_0603_6.3V6-M
1.5A
C10122
@
22U_0603_6.3V6-M
1
2
1
2
1
2
1
1
1
2
@
2
2
@
0.47U_0402_25V6-K
C922
@
0.47U_0402_25V6-K
C921
2
@
0.47U_0402_25V6-K
C1334
2
1
0.47U_0402_25V6-K
C920
1
4.7U_0805_25V6-K
C919
D38
10U_0805_25V6K
C918
EMC_NS@
AZ5725-01F.R7GR_DFN1006P2X2
2
@ F10
1
U7
R108
100K_0402_1%
+5VALW
R105
100K_0402_1%
JUMP_43X39
R117
100K_0402_1%
+5VALW
1
@
1
R104
100K_0402_1%
VBUS_P0
D
2
1
1
J14 2
1
+5VALW
VBUS_P0
@
{19} USB20_N2
EMC@
1
2
4
3
2
C_DP
3
C_DM
EXC24CH900U_4P
R91
JP1
@
1
2 0_0402_5%
C
24
C_RX1_P_C
C_RX1_N_C
R944 2
USB30_RX_N2
USB30_RX_P2
C10131 1
C10130 1
C10125 1
C10126 1
C_TX2_N
C_TX2_P
2 0.1U_0201_6.3V6-K
2 0.1U_0201_6.3V6-K
C_RX2_N
C_RX2_P
2 0.33U 10V K X5R 0402
2 0.33U 10V K X5R 0402
EXC24CH900U_4P
C_TX2_N
2
C_TX2_P
3
1
1
3
L24
C_TX2_P_C
USB30_RX_N4 C10123 1
USB30_RX_P4 C10124 1
2 0.1U_0201_6.3V6-K
2 0.1U_0201_6.3V6-K
2 0.33U 10V K X5R 0402
2 0.33U 10V K X5R 0402
C_RX1_N
C_RX1_P
EMC_NS@
4
4
2
2
2 220K_0201_5%
1
1
16
CC1
CC2
C_TX2_N_C
D47
B
15
C_TX2_P_C
EMC_NS@
14
C_RX2_P_C
13
SSTXp1_A2
SSTXn1_A3
VBUS_B9
VBUS_A4
SBU2_B8
CC1_A5
Dn2_B7
Dp1_A6
Dp2_B6
Dn1_A7
CC2_B5
SBU1_A8
VBUS_B4
R101 2
@
R31352
Ref intel PDG(571391)Rev1.8 Type-C USB-IF update 0802SF
@
VBUS_A9
SSTXn2_B3
SSRXn2_A10
SSTXp2_B2
SSRXp2_A11
GND_B1
C_RX2_N_C
2 220K_0201_5%
C
SSRXn1_B10
EXC24CH900U_4P
GND_A12
1
2
C_TX1_P_C
3
C_TX1_N_C
4
5
CC1
6
C_DP
7
C_DM
8
9
10
C_RX2_N_C
11
C_RX2_P_C
12
HIGHS_UB11246-15A0C-1H
1 0_0402_5%
1
R10417 1
3
3
2 220K_0201_5%
R10416 1
17
CC2
1 0_0402_5%
2 220K_0201_5%
R10415 1
18
1 0_0402_5%
@
L25
C_RX2_P
C_RX2_N
R10414 1
@
19
C_DP
4
EMC_NS@
R100 2
C_TX1_N
C_TX1_P
C_DM
ME@
GND_A1
SSRXp1_B11
32
31
30
29
{15} USB30_RX_N4
{15} USB30_RX_P4
USB30_TX_N4 C10132 1
USB30_TX_P4 C10133 1
20
C_TX2_N_C
4
2
R31072
{15} USB30_TX_N4
{15} USB30_TX_P4
21
2
{15} USB30_RX_N2
{15} USB30_RX_P2
USB30_TX_N2
USB30_TX_P2
22
1 0_0402_5%
3
{15} USB30_TX_N2
{15} USB30_TX_P2
@
23
Power_GND_B12
25
26
27
28
4
GND5
GND6
GND7
GND8
L23
1
{19} USB20_P2
3A
2 0_0402_5%
GND12
GND11
GND10
GND9
R943 1
AZC199-02S.R7G_SOT23-3
1 0_0402_5%
B
EXC24CH900U_4P
2
4
4
L31
R31372
@
R3136 2
@
L32
C_TX1_P
4
C_TX1_N
1
4
1
2
3
3
EMC_NS@
1 0_0402_5%
C_RX1_N_C
C_DM
C_DP
D36
D48
EMC_NS@
10
C_RX1_N_C
9
C_TX2_N_C
C_RX1_P_C
C_RX1_P_C
2
1
3
C_RX1_P
1
7
C_TX2_P_C
6
1 0_0402_5%
EMC_NS@
3
3
2
NC1
Line-1
NC2
Line-2
NC3
Line-3
NC4
Line-4
GND2
C_TX1_P_C
2
EXC24CH900U_4P
@
R3138 2
1 0_0402_5%
EMC_NS@
GND1
1
C_RX1_N
AZC199-02S.R7G_SOT23-3
1
C_RX1_P_C
2
C_RX1_N_C
4
C_TX2_N_C
5
C_TX2_P_C
D20
C_TX1_P_C 10
C_TX1_N_C 9
C_RX2_N_C 7
C_RX2_P_C 6
EMC_NS@
NC1
Line-1
NC2
Line-2
NC3
Line-3
NC4
Line-4
3
GND1
8
GND2
AZ1143-04F-R7G_DFN2510P10E10
1
C_TX1_P_C
2
C_TX1_N_C
4
C_RX2_N_C
5
C_RX2_P_C
3
8
AZ1143-04F-R7G_DFN2510P10E10
For ESD
C_TX1_N_C
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/08/20
Deciphered Date
https://Dr-Bios.com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
5
4
3
2
3D Camera
2018/09/20
Size
C
Date:
Document Number
Rev
0.1
FG541/FG741
Friday, March 01, 2019
1
Sheet
48
of
69
5
4
2 0_0603_5%
+3VALW
CE2
22P_0402_50V8-J
EMC@
+3VL_EC_R
+3VL_EC
Close EC
1
1
LE1
2
2 0_0402_5%
2
2
2
1
2
@1
2
1
LE2
2 0_0603_5%
@
2
CE5
1000P_0201_50V7-K
EC_AGND
EC_AGND
+3VL_EC
D
+3VS
+3VL_EC
RPE2
2
1
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_DA1
EC_SMB_CK1
3
4
2.2K_0404_4P2R_5%
+3VS
RPE3
1
2
KSI7
KSI6
WRST#
EC_SMB_CK2
EC_SMB_DA2
4
3
PAD
PAD
PAD
PAD
PAD
1
1
1
1
1
@
IT1
@
IT2
@
IT3
@
IT4
@
IT5
PAD
PAD
PAD
1
1
1
@
IT6
@
IT7
@
IT8
For factory EC flash
2.2K_0404_4P2R_5%
EC_ON RE58 2
1 0_0402_5%
@
+3VL
110
111
115
116
117
118
94
95
ON/OFF
{50} ON/OFF
EC_SMB_CK1
EC_SMB_DA1
PECI_EC
{58,59,68} EC_SMB_CK1
{58,59,68} EC_SMB_DA1
2 33_0402_5%
RE24 1
{6,14} EC_PECI
58
59
60
61
62
63
64
65
36
37
38
39
40
41
42
43
44
45
46
51
52
53
54
55
56
57
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
{20,42} LAN_PWR_ON#
{16,28,44} EC_SMB_CK2
{16,28,44} EC_SMB_DA2
EC_SMB_CK2
EC_SMB_DA2
RE27 2
@
1 0_0402_5%
112
125
{16} DPWROK_EC
B
USB_ON#
33
35
93
{46} USB_ON#
{48} TYPE_C_ST
{16,41} EC_RSMRST#
PCIE_WAKE#
2
128
{16,42,45} PCIE_WAKE#
{16} AC_PRESENT
+3VL
@
2 10K_0402_5%
@
2 10K_0402_5%
1 100K_0402_5%
2 10K_0402_5%
2
74
AVCC
EXTERNAL SERIAL FLASH
NC1
NC2
NC3
NC4
AC_IN#
LID_SW#
UART
EGAD/GPE1
EGCS#/GPE2
EGCLK/GPE3
Bus
GPIO
GPJ1
SSCE0#/GPG2
SSCE1#/GPG0
DSR0#/GPG6
DTR1#/SBUSY/GPG1/ID7
CRX0/GPC0
CTX0/TMA0/GPB2
RI1#/GPD0
RI2#/GPD1
TACH2/GPJ0
TACH1A/TMA1/GPD7
TACH0A/GPD6
L80HLAT/BAO/GPE0
L80LLAT/GPE7
WAKE UP
GINT/CTS0#/GPD5
RTS1#/GPE5
CLKRUN#/GPH0/ID0
CK32KE/GPJ7
CK32K/GPJ6
GPH3/ID3
GPH4/ID4
GPH5/ID5
GPH6/ID6
SPI Flash ROM
PWRSW#
SM
XLP_OUT
SMCLK1/GPC1
SMDAT1/GPC2
SMCLK2/PECI/GPF6
SMDAT2/PECIRQT#/GPF7
CRX1/SIN1/SMCLK3/GPH1/ID1
CTX1/SOUT1/GPH2/SMDAT3/ID2
VSTBY0
GPE4
DAC2/TACH0B/GPJ2
DAC3/TACH1B/GPJ3
DAC4/DCD0#/GPJ4
DAC5/RIG0#/GPJ5
PS2CLK0/TMB0/CEC/GPF0
PS2DAT0/TMB1/GPF1
GPF2
PS2
GPF3
PS2CLK2/GPF4
PS2DAT2/GPF5
GPIO
EC_BKL_EN
EC_FAN2_PWM
EC_FAN1_PWM
2 10K_0402_5%
RE7
1
@
2 10K_0402_5%
RE9
1
@
EC_VBUS_EN
LAN_WAKE#
SUSP#
2 100K_0402_5%
EC_CMOS_ON#
RE275 1
@
2 10K_0402_5%
ADAPTER_ID_R
78
79
80
81
RE280 1
RE276 1
CPU_PWRGD
H_PROCHOT#_EC
PAD
1
@
IT37
CPU_PWRGD {63}
EC_ON_GPIO
RE57 1
2 0_0402_5%
@
C
EC_ON {44,60,61}
+5VALW
USB_ON#
RE15 1
SUSP#
RE18 1
CPUCORE_ON
RE270 1
2 100K_0402_5%
SUSP#
RE19 1
2 100K_0402_5%
SYSON_R
RE21 1
2 100K_0402_5%
EC_VCCIO_EN
RE268 1
96
97
98
99
+3VL_EC
CAPS_LED# {50}
PCH_PWR_EN {51,61}
SYS_PWROK {16,41}
PCH_PWROK {16,41}
101
102
103
105
EC_SPI_CS0#
EC_SPI_SI
EC_SPI_SO
EC_SPI_CLK
108
109
ACIN#
LID_SW#
EC_SPI_CS0# {18}
EC_SPI_SI {18}
EC_SPI_SO {18}
EC_SPI_CLK {18}
LID_SW# {50}
82
83
84
TYPE_C_DFP {48}
VDDQ_PGOOD {61}
EC_VPP_PWREN {61}
EC_VPP_PWREN
77
100
106
104
107
119
123
18
21
76
48
47
19
20
RE271 2
1 0_0402_5%
@
BKOFF#
BKOFF# {38}
RE34 2
{59} VR_HOT#
PM_SLP_S3#
EC_VCCIO_EN
1 0_0402_5%
@
H_PROCHOT#_EC
QE1
EMC Request
2
CE14
47P_0201_25V8-J
EMC_NS@
ON/OFF
@
CE18 1
1
D
2
CE48
0.01U_0201_10V6K
EMC_NS@
2
@
2015/08/20
Deciphered Date
4
https://Dr-Bios.com
3
2
A
ACIN {59}
2N7002KW_SOT323-3
@
Title
EC ITE8586LQFP
2018/09/20
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
5
1 0_0402_5%
G
S
LC Future Center Secret Data
Security Classification
Issued Date
RE262 2
QE2
2
CE19
0.1u_0201_10V6K
2
2 1U_0402_6.3V6K
1 10K_0402_5%
1
1
1
2 100P_0201_25V8J
1
3
EMC_NS@ CE17 1
ACIN#
2 47P_0201_25V8-J
2 100P_0201_25V8J
ACIN#
S 2N7002KW_SOT323-3
RE50
10K_0402_5%
2
3
S
RE42
100K_0402_5%
EMC_NS@ CE16 1
D
2
G
+3VS
EMC_NS@ CE15 1
QE3
EC_RTCRST#_ON
D
+3VL
1 10K_0402_5%
@
B
H_PROCHOT# {6,61,63}
1
2
2N7002KW_SOT323-3
ACIN#
RE46 2
2 EMC_NS@ 1000P_0201_50V7-K
VGA_AC_DET
EC_RTC_RST# {16}
1 10K_0402_5%
NOVO#
GPG2
2 EMC_NS@ 1000P_0201_50V7-K
CE13 1
0.01U_0201_10V6K
Reserve for VGA_AC_DET
RE267
100_0402_5%
BATT_TEMP
when mirror, GPG2 pull high
when no mirror, GPG2 pull low
CE21 1
EC_VCCIO_EN {62}
1 0_0402_5%
@
PECI_EC
+3VL_EC
@
2 EMC_NS@ 1000P_0201_50V7-K
VGA_AC_DET {28}
NUM_LED# {50}
+3VL
RE44 2
CE50 1
SYSON
RE55 2
2
PM_SLP_S4#
ME_FLASH {16}
SYSON {51,61}
SYSON
PM_SLP_S3# {16}
PM_SLP_S4# {16}
NOVO# {50}
EC_FAN2_SPEED {44}
EC_FAN1_SPEED {44}
EC_FAN2_SPEED
EC_FAN1_SPEED
2 100K_0402_5%
@
VDDQ_PGOOD CE51 1
EC_CMOS_ON# {38}
SYSON_R
2 100K_0402_5%
@
Add to fix Reset & PWRGD test fail issue
EC_MUTE# {35}
GPG2
G
RE43 2
2 100K_0402_5%
PM_SLP_SUS# {16}
for EC version update to EX, manual modify PN to FX
GPG2
4
3
EC_LID_OUT# {50}
BKOFF#
GPG2
1
2
2.2K_0404_4P2R_5%
EC_LID_OUT#
EC_AGND
A
RE274
@ 0_0402_5%
RPE4
EC_SMB_DA3
EC_SMB_CK3
RE65
100K_0402_5%
PBTN_OUT# {16,41}
EC_SMB_CK3 {61,63}
EC_SMB_DA3 {61,63}
EC_SMB_CK3
EC_SMB_DA3
2
1
RE273
0_0402_5%
@
ADAPTER_ID {58} +3VL_EC
PSYS {59,63}
ENBKL {38}
85
86
87
88
89
90
+3VALW +3VL_EC
For PMIC
1
SUSP# {45,51,60}
NTC_V1 {44}
NTC_V2 {44}
BATT_TEMP {58,59}
NTC_V3 {44}
CPUCORE_ON {6,63}
ADP_I {59}
2 0_0402_5%
@
2 0_0402_5%
@
BATT_TEMP
2
66
67
68
69
70
71
72
73
EC_VBUS_EN {48}
change for EC_VBUS_EN 20180910SF
Clock
IT8586E-AX_LQFP128_14X14
LID_SW#
RE40 1
26
50
92
114
121
127
11
DAC
BKOFF#
RE38 2
VSTBY1
VSTBY2
VSTBY3
VSTBY4
VSTBY5
VSTBY(PLL)
12
KSI0/STB#
KSI1/AFD#
KSI2/INIT#
KSI3/SLIN#
KSI4
KSI5
KSI6
KSI7
KSO0/PD0
Int. K/B
KSO1/PD1
Matrix
KSO2/PD2
KSO3/PD3
KSO4/PD4
KSO5/PD5
KSO6/PD6
KSO7/PD7
KSO8/ACK#
KSO9/BUSY
KSO10/PE
KSO11/ERR#
KSO12/SLCT
KSO13
KSO14
KSO15
KSO16/SMOSI/GPC3
KSO17/SMISO/GPC5
ON/OFF
RE36 1
ADC
IT8586E/AX
LQFP-128L
VSS1
RE35 1
ADC0/GPI0
ADC1/GPI1
ADC2/GPI2
ADC3/GPI3
ADC4/GPI4
ADC5/DCD1#/GPI5
ADC6/DSR1#/GPI6
ADC7/CTS1#/GPI7
@
ENBKL
PWR_LED# {50}
BATT_CHG_LED# {50}
BATT_LOW_LED# {50}
EC_BKL_EN {50}
EC_FAN2_PWM {44}
EC_FAN1_PWM {44}
EC_BEEP# {35}
1
KSO[0..17]
LPC
2 10K_0402_5%
RE11 1
LPC_FRAME#
PWR_LED#
24
25
28
29
30
31
32
34
120
124
3
KSI[0..7]
{50} KSI[0..7]
{50} KSO[0..17]
C
PW M
@
1
{15} EC_SMI#
{45,46} EC_RX
{45,46} EC_TX
{18,28,37,41,42,45} PLT_RST#
{14,20} EC_SCI#
CE12
1U_0402_6.3V6K
2
2 10K_0402_5%
RE279 1
2
100K_0402_5%
2 10K_0402_5%
1
1
RE10 1
EC_FAN1_PWM
PWM0/GPA0
PWM1/GPA1
PWM2/GPA2
PWM3/GPA3
PWM4/GPA4
PWM5/GPA5
PWM6/SSCK/GPA6
PWM7/RIG1#/GPA7
TMRI0/GPC4
TMRI1/GPC6
1 2
2
RE278 1
LAN_WAKE# {42,45}
EC_FAN2_PWM
AVSS
1
RE8
EC_FAN2_SPEED
EC_FAN1_SPEED
LAN_WAKE#
75
RB751V-40_SOD323-2
KBRST#/GPB6
SERIRQ/GPM6
LFRAME#/GPM5
LAD3/GPM3
LAD2/GPM2
LAD1/GPM1
LAD0/GPM0
LPCCLK/GPM4
WRST#
ECSMI#/GPD4
PWUREQ#/BBO/SMCLK2ALT/GPC7
LPCPD#/GPE6
LPCRST#/GPD2
ECSCI#/GPD3
GA20/GPB5
VSS2
VSS3
VSS4
VSS5
VSS6
@
1 0_0402_5%
4
1 0_0402_5%
5
2 0_0402_5% LPC_FRAME#_EC 6
LPC_AD3
7
LPC_AD2
8
LPC_AD1
9
LPC_AD0
10
CLK_PCI_EC
13
14
WRST#
15
EC_RX
16
EC_TX
17
PLT_RST#
22
23
EC_RTCRST#_ON
126
RE5
10K_0402_5%
minimum trace width 12 mil
27
49
91
113
122
2
@
@
@
1
+3VL_EC
DE1 1
RE56 2
RE59 2
RE60 1
{15} KBRST#
{15} SERIRQ
{15} LPC_FRAME#
{15} LPC_AD3
{15} LPC_AD2
{15} LPC_AD1
{15} LPC_AD0
{15} CLK_PCI_EC
VCC
VBAT
{25} WRST#
VCORE
UE1
3
1
@
@1
CE11
1
CE6
RE6
1
0.1u_0201_10V6K
2
Change RE6 to 0ohm jump
1
CE10
D
1
+3VL_EC_R
+3VS
0.1u_0201_10V6K
CD@
0.1u_0201_10V6K
1
2
All capacitors close to EC
+3VL_EC
1
CE4
0.1u_0201_10V6K
VCOREVCC
0.1u_0201_10V6K
1
CE9
CE3
2 0_0603_5%
@
+3VL_EC
2
0.1u_0201_10V6K
CE1
220P_0201_25V7-K
EMC@
2
@
1
+3VL
1
2 33_0402_5%
EMC@
CE8
1
0.1u_0201_10V6K
RE2
2 0_0603_5%
CE7
CLK_PCI_EC
1
@
RE3
For EMI
PLT_RST#
2
1
0.1u_0201_10V6K
For ESD
3
RE1
Size
C
Date:
Document Number
Rev
0.1
FG541/FG741
Wednesday, February 27, 2019
1
Sheet
49
of
69
5
4
2
NOVO_BTN#
2
2
SW2
4
R83
100K_0402_5%
@
D24
AZ5123-01F.R7GR_DFN1006P2X2
EMC@
5
R261 1
@
2 0_0402_5%
NOVO#
{49} NOVO#
NTC325-EKJ-A160T_3P
2
3
8/16 Del Power Button wei
2
D15
1
2
1
1
1
+3VALW
R82
100K_0402_5%
1
Novo button
2
+3VL
3
1
ON/OFF switch
NOVO_BTN#
1
ON/OFFBTN#
@
2
+3VL
2
+3VALW
R119 1
ON/OFFBTN#
2 0_0402_5%
@
R114
100K_0402_5%
D25
D
LID switch
EMC@
1
1
R111
100K_0402_5%
@
8/31 Update the P/N SN100008W00 wei
1
3
BAT54CW_SOT323-3
1
2 0_0402_5%
@
2
1
2
R85
AZ5123-01F.R7GR_DFN1006P2X2
ON/OFF
D
ON/OFF
1
ON/OFF {49}
C1104
100P_0201_25V8J
U14
J5 1
2
1
@
SHORT PADS
J6 1
2
C1105
0.01U_0201_10V6K
@
CAPS_LED#
NUM_LED#_R
C117
C118
ON/OFFBTN#
PWR_LED#
2 100P_0201_25V8J
R285 1
R279 1
1
KSO17 R281
1
KSO16 R280
{49} NUM_LED#
2 200_0402_1%
2 200_0402_1%
2 0_0402_5%
2 0_0402_5%
@
@
EMC@
1
2 100P_0201_25V8J
1
2 100P_0201_25V8J
8/23 PWR LED function under check
D23
AZ5123-01F.R7GR_DFN1006P2X2
EMC@
1
D22
AZ5123-01F.R7GR_DFN1006P2X2
EMC@
1
PWR_LED#
1
NUM_LED#_R
1
CAPS_LED#
D46
AZ5123-01F.R7GR_DFN1006P2X2
EMC@
{49} CAPS_LED#
CAPS_LED#
LID_SW# {49}
For EMC CPI fail need add R10418---1204SF
AH9247-W-7_SC59-3
KB Backlight Connector
ME@
@
KSI1
KSI7
KSI6
KSO9
KSI4
KSI5
KSO0
KSI2
KSI3
KSO5
KSO1
KSI0
KSO2
KSO4
KSO7
KSO8
KSO6
KSO3
KSO12
KSO13
KSO14
KSO11
KSO10
KSO15
2 200_0402_1% CAPS_LED#_R
PWR_CAPS_LED
2 0_0402_5%
2
R275 1
R84
1
NUM_LED#_R
KSO17_R
KSO16_R
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
update BL circuit and need too be confirm conn pin define
LED_KB_C
0925SF
1
D
EC_BKL_EN
2
{49} EC_BKL_EN
Q121
PJA138K_SOT23-3
BL@
G
S
3
R116
100K_0402_5%
BL@
+5VS
C
0.5A
JKBL1
1
2
3
4
LED_KB_C
R343 1
GND2
GND1
@
2 0_0603_5%
1
C1110
0.1u_0201_10V6K
@
34
33
1
2
3
4
ME@
GND2
GND1
6
5
CVILU_CF50041D0RN-10-NH
2
JKB1
2
2
2
2
+3VALW
2
VCC
2
1
LID_SW#
2
@
0_0402_5%
2
HIGHS_FC8AR321-3160-1H
EMC_NS@
EMC@
1
KSO[0..17] {49}
1
C
KBD symbol:
1.20180821SF update to SP011807040
KSI[0..7] {49}
2
R10418 1
3
1
KSI[0..7]
KSO[0..17]
C133
2 +VCC_LID
2
GND
OUTPUT
0_0402_5%
K/B Connector
PWR_CAPS_LED
@
R264 1
+3VL
SHORT PADS
1
For EMC
TP/B Connector
Finger Print Connector
+3VS
follow OD V1.5 delete finger print function
0927SF
TP_PWR
R141 1
@
TP_PWR
2 0_0402_5%
2.2K_0201_5%
@
@
2 0_0402_5%
2 0_0402_5%
2
C116
C115
EMC_NS@
1
2
100P_0201_25V8J
EMC_NS@
1
100P_0201_25V8J
EMC_NS@
2
3
ELCO_04-6809-606-110-846-+
EC_LID_OUT#_R
TP_INT#
6
5
4
3
2
1
TP_I2C_SDA0
TP_I2C_SCL0
DT1
1
TP_I2C_SCL0
2
R4675 1
R4676 1
{20} TP_I2C_SDA0
{20} TP_I2C_SCL0
TP_I2C_SCL0
TP_I2C_SDA0
TP_I2C_SDA0
2.2K_0201_5%
2
1
1
10K_0402_5%
{49} EC_LID_OUT#
{20} PCH_TP_INT#
B
2
1
RG50
10K_0402_5%
@
2
1
R10413
RG49
2
0.1u_0201_10V6K
C114
R10412
1
TP_PWR
6
5
4
3
2
1
JTP1
8
GND2
7
GND1
B
ME@
AZC199-02S.R7G_SOT23-3
For EMC
BATT_LOW_LED#
{49} BATT_LOW_LED#
1
2
R143 1
2 470_0402_5%
+3VALW
R144 1
2 1.5K_0402_5%
+5VALW
R4672 1
2 1.5K_0402_5%
+5VALW
1
L-C192JFCT-LCFC_SUPER_AMBER
2
2
1
LED2
D18
AZ5123-01F.R7GR_DFN1006P2X2
EMC_NS@
BATT_CHG_LED#
{49} BATT_CHG_LED#
LED3
1
2
2
2
1
1
L-C192WDT-LCFC_WHITE
D19
AZ5725-01F.R7GR_DFN1006P2X2
EMC_NS@
A
A
LED4 1
2
1
PWR_LED#
PWR_LED#
{49} PWR_LED#
08/17
D16
AZ5725-01F.R7GR_DFN1006P2X2
EMC_NS@
2
PWR_LED Change to M/B (310- & gt; 320)
2
1
L-C192WDT-LCFC
Security Classification
Issued Date
Title
LC Future Center Secret Data
Deciphered Date
2015/08/20
KBD/PWR/IO/LED/TP Conn.
2018/09/20
https://Dr-Bios.com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF
Size Document
Custom
LC FUTURE CENTER.
Date:
5
4
3
2
Number
Re v
0.1
FG541/FG741
Friday, March 01, 2019
1
Sheet
50
of
69
B
C
E
2
C2090
C2089
1
1
2
EMC_NS@
2
0.1u_0201_10V6K
C2088
1
EMC_NS@
2
EMC_NS@
1
0.1u_0201_10V6K
2
C2087
1
EMC_NS@
2
0.1u_0201_10V6K
C2092
C2091
1
EMC_NS@
EMC_NS@
2
0.1u_0201_10V6K
C2086
C2085
1
0.1u_0201_10V6K
2
EMC_NS@
1
0.1u_0201_10V6K
+3VS, C173 -- & gt; 2.74ms
+5VS, C176 -- & gt; 2.03ms
VIN 5V and 3.3V (VBIAS=5V), IMAX(per channel)=6A, Rds=16mohm
0.1u_0201_10V6K
Load Switch
+5VALW To +5VS
+3VALW To +3VS
D
+1.05VALW
EMC_NS@
+1.8VALW
0.1u_0201_10V6K
A
delete Load Switch 5VS and 3VS 20181101SF
1
1
EMC
1
2
2 0_0402_5%
CV456
1
0.22U_0402_25V6-K
1
1
G
2
1
CV453
0.01U_0402_25V7K
@
1@
CV455
10U_0603_6.3V6M
2
RV1116
OPT@
2
1
2
1
OPT@
1/10W_47_5%_0603
2
1
RV1121
210K_0402_1%
OPT@
+1.8VS_AON_EN#
D
2
QV23
L2N7002KWT1G_SOT323-3
OPT@
G
S
2
R278
200_0402_5%
@
2
R159
47_0603_5%
@
1
1
2
49.9K_0402_1%
LBAT54SWT1G_SOT323-3
1
2
3
D
SUSP
1
1
2
2
RV1117
100K_0402_5%
OPT@
2
RV1217
21
S
S1
S2
S3
D
3
31
+2.5V_DDR
6
G
1
+0.6VS
S
D
2
D
5
@
4
1
2
1 0_0402_5%
@
RV1216
4
RV1115 2
{19,28} PXS_PWREN
For DisCharge
{39} SUSP
QC25B
5
L2N7002KDW1T1G_SOT363-6
OPT@
QC25A
8/29 Add +1.8VS Circuit for Audio wei
R157
100K_0402_5%
@
RV1119
1
2
1K_0402_5%
OPT@
OPT@
+1.8VS_AON_EN#
G
+5VALW
R156
100K_0402_5%
RV1114
47K_0402_5%
OPT@
RV1113
47K_0402_5%
OPT@
@
DV12
+5VLP
Q5811
AON7400A_DFN8-5
V20B+
+5VALW
2
1
CV457
0.1U_0402_25V6
OPT@
C131
0.1u_0201_10V6K
@
2
CV454
0.1U_0402_25V6
2
1
2
@
2
2
1
@2
L2N7002KDW1T1G_SOT363-6
1
2
1
R87
100K_0402_5%
@
2
2
3
R202
470K_0402_5%
@
1
PCH_PWR_EN#_R
R162
100K_0402_5%
@
@
1
2
3
1
2
@
0.1u_0201_10V6K
C202
S 2N7002KW_SOT323-3
2 0_0402_5%
@
C130
0.01U_0201_10V6K
@
1
2
G
@
2
SUSP R201 1
1
2
Id=3.2A
@
2
1
0.1u_0201_10V6K
C205
3
D
G
0.1u_0201_10V6K
C204
Q29
D
1
@
LP2301ALT1G_SOT23-3
2
S
Q30
2
1
0.1u_0201_10V6K
C203
C1103
22U_0603_6.3V6-M
@
PCH_PWR_EN#
PCH_PWR_EN
+1.8VS_AON
1
LP2301ALT1G_SOT23-3
G
2 100K_0402_5%
1
+1.8VALW
D
@
0.6A
3
1
+1.8VALW to +1.8VS_AON
+1.8VS
Q35
S
R158 1
{49,61} PCH_PWR_EN
+1.8VALW
2
2
0.1u_0201_10V6K
C201
PCH_PWR_EN#_R
+3VALW_PCH
@
1
JUMP_43X79
1
1
J7
1
2
+3VALW
R155
100K_0402_5%
@
1
Need short
+5VALW
Q11
D
2
Q33
2
SUSP
G
1
3
3
S
@
D
SUSP
G
S 2N7002KW_SOT323-3
Q10
2N7002KW_SOT323-3
@
2
{45,49,60} SUSP#
3
G
S 2N7002KW_SOT323-3
08/29: Need double check enable signal and the resistance
+1.0VALW TO +1.0VGS
2
UC4
1
2
SUSP#
4
+5VALW
+1.05VALW
{49,61} SYSON
3
SYSON
5
6
7
IN1_1
IN1_2
OUT1_2
OUT1_1
EN1
CT1
VBIAS
GND
EN2
CT2
IN2_1
IN2_2
OUT2_2
OUT2_1
Thermal Pad
1
14
13
12
2
@
+3VALW
1
CC1316
1 RC3040
CC1293 1
CC1292 1
2 1000P_0201_50V7-K
RC3041
1
VCCST
15
1@
CC1392
10U_0603_6.3V6M
2
{28,30,67} 1V0_MAIN_EN
2 0_0402_5%
RC3042
UC8
2
VIN
5
VBIAS
6
1
@
@
9
8
+1.0VGS
2
1U_0201_6.3V6-M
@
VBIAS_R
2
2 1000P_0201_50V7-K
11
10
+1.05VALW
+5VALW
0_0402_5%
@
G2898KD1U_TDFN14P_2X3
CC1393
1U_0402_6.3V6K
1
1
CC1315
1U_0402_10V6K
2
ON
VOUT
NC
GND
4
3
1
EM5201BJ-45_SOT23-6
@
+1.0VGS_EN
2
1
CC72
1U_0402_6.3V6K
@
2
3
1
C1102
2
VCCSTG
1U_0402_6.3V6K
CC1250
1
CC71
22U_0603_6.3V6-M
VCCSTG & VCCST change to Dual Switch
+1.05VALW
0906SF
22U_0603_6.3V6-M
delete reserved for VCCSTG & VCCST 0928SF
3
2 0_0402_5%
@
1
@
CC1398
1U_0402_10V6K
2
4
4
Security Classification
Issued Date
T itle
LC Future Center Secret Data
2015/08/20
Deciphered Date
DC V TO VS INTERFACE
2018/09/20
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Size Document Number
Custom
B
C
https://Dr-Bios.com
D
E
Rev
0.1
FG541/FG741
Wednesday, February 27, 2019 Sheet
Date:
A
51
of
69
3
PU904
BATT
B5
3
+3VALW
1
DPWROK_EC
B1
4
PCH_RSMRST#
EC
5
EC_ON
A3
B4
PBTN_OUT#
V
PM_SLP_S3#
PM_SLP_S4#
PM_SLP_S5#
PM_SLP_SUS#
12
CPU_PLTRST#
SYS_PWROK
V
ON/OFF
PCH
6
PCH_PWROK
13
14
PM_DRAM_PWRGD
H_CPUPWRGD
C
B3
+3V_PCH
V
V
A4
B+
D
Q25,+3V_PCH
15
16
CPU
V V
BATT
MODE
A2
2
V
PU301
V
V V
VIN
PCH_PWR_EN#
1
V V
A1
V
AC
M ODE
A2
+3VLP
V V V
B2
D
2
V
4
V
5
C
V
NOVO
NVDD_PWR_EN
(DIS)
+1.35V
PU501
+VGA_CORE
PU801
V
7
SYSON
V
VR_REDY
V
Vb
11
DGPU_PWROK
V
8
V
+1.05VSP_VGA
PU702
+3VS_VGA
Q27
VGA
V
PU602
+1.5VS
B
PU502
+0.675V
PU701
+1.05VS
V
SUS_VCCP
Q32
+3VS
V
V
9
V
SUSP#,SUSP
+1.5VS_VGA
PU601
V
Q31
+5VS
V
V
B
V
Va (DIS)
VR_ON
V
10
PU901
+CPU_CORE
V
DGPU_PWR_EN
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/08/20
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
5
4
https://Dr-Bios.com
3
Power sequence block
2018/09/20
Deciphered Date
Size Document Number
Custom
Date:
2
Rev
0.1
FG541/FG741
Thursday, January 03, 2019
1
Sheet
52
of
69
5
4
3
GPU Thermal Holex2
2
Close to RJ45
DC-IN x2
CPU Thermal Holex3
H1
HOLEA
D
H2
HOLEA
1
WLAN Standoff
H10
HOLEA
H3
HOLEA
H11
HOLEA
D
PAD_D2P4
1
PAD_D2P4
1
PAD_C6P0D4P0
1
H12
HOLEA
PAD_C6P0D4P0
PAD_CT6P0B7P0D3P7
H14
HOLEA
PAD_C6P0D4P0
1
H13
HOLEA
PAD_C6P0D3P3
PAD_C6P0D3P3
H16
HOLEA
H15
HOLEA
1
H9
HOLEA
H8
HOLEA
H17
HOLEA
PAD_D3P4x2P7
H18
HOLEA
PAD_CT5P6B7P0D3P0
C
1
PAD_C6P0D4P0
PAD_C2P7D2P7N
H7
HOLEA
1
PAD_C6P0D4P0
C
H6
HOLEA
1
H5
HOLEA
1
H4
HOLEA
1
1
1
1
1
1
PAD_CT5P5B6P0D2P4 PAD_CT5P5B6P0D2P4
PAD_D2P4
1
1
FD6
1
FD5
1
FD4
1
FD3
1
FD2
1
FD1
1
1
PCB Fedical Mark PAD
PAD_CT5P6B7P0D3P0
CHASSIS1_GND
PAD_C7P0D3P0
Close to Audio jack
follow layout list update 20181010SF
SH7
B
1
SH8
ME@
1
1
SH10
SH11
1
1
SHIELDING_SUL-35A2M_9P2X3P3_1P
1
SHIELDING_SUL-35A2M_9P2X3P3_1P
ME@
SHIELDING_SUL-35A2M_9P2X3P3_1P
SH12
ME@
1
1
ME@
1
SHIELDING_SUL-35A2M_9P2X3P3_1P
USB3.0 Shielding
ME@
B
1
1
SHIELDING_SUL-35A2M_9P2X3P3_1P
1
SH9
ME@
SHIELDING_SUL-35A2M_9P2X3P3_1P
DDR4 Shielding
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/08/20
Deciphered Date
Hole
2018/09/20
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Size
B
Date:
5
4
3
https://Dr-Bios.com
2
Document Number
Re v
0.1
FG541/FG741
Thursday, January 03, 2019
Sheet
1
54
of
69
5
4
3
2
1
D
D
V20B+
+5VLP
@
PJ401
2.2UH_PCMB063T-2R2MS_8A_20%
+3VALW
1
2
PC3545
4.7U_0603_6.3V6K
14
+3/5VALW_EN
15
VIN2
BOOT2
LX2_1
LX2_2
LX2_3
EN2
@
PJ3505
PC3554
1
2
22
+5VALW_BS 1
23
24
36
10_0603_5% 0.1U_0603_25V7-M
+5VALW_LX
19
+5VALW_P
2
+5VALW_P
1.5UH_PCMB063T-1R5MS_10A_20%
PGOOD2
VBYP5
21
+5VLP
VCC2
1U_0402_6.3V6-K
LDO5
20
100mA
1
1
1
5VS_SS
2
PC3561
2200p_0402_25V7-K
1
2
Need Short
2
PC5978
0.1U_0201_25V6-K
+5VS
2
JUMP_43X79
1
@
+5VALW
8A
Vout=5V± 3%
Vset=5.1V± 1.5%
OCP=12A
OVP=(1.15~1.25)*Vout
UVP=(0.55~0.65)*Vout
Fsw=500Khz
PC5979
0.1U_0201_25V6-K
C
PR3509
2.2_0805_5%
EMC_NS@
1
1
1
PR3508
2.2_0805_5%
EMC_NS@
@
@
PJ3507
1
1
+3VS
2
JUMP_43X79
1
1
26
@
2
AGND_1
AGND_3
AGND_2
PGND_1
+5VS_SW
28
PC3532
1000P_0402_50V7K
EMC_NS@
PC3533
1000P_0402_50V7K
EMC_NS@
@
8
32
17
13
ENSW2
PGND_2
+5VS_EN
@
B
VOUTSW2
12
1
2
PC3565
22U_0603_6.3V6-M
2
1
2 0_0402_5%
VINSW2
PC3562
2200p_0402_25V7-K
1
2
ENSW1
SS2
27
2
PR5916 1
34
2
30
3VS_SS
2
SS1
+3VS_EN
@
31
+5VALW
PC3530
1U_0402_25V6-K
@
PJ3506
+3VS_SW
29
1
VOUTSW1
2
JUMP_43X79
@
2
VINSW1
PC3564
22U_0603_6.3V6-M
33
1
2
2 0_0402_5%
{45,49,51} SUSP#
2
PC3559
4.7U_0603_6.3V6K
PC3566
22U_0603_6.3V6-M
1
+3VALW
PJ3504
2
+3VALW_LX
18
PC3563
22U_0603_6.3V6-M
+3VALW_PG
ALW_PWRGD {16}
PR5915 1
2
16
PC3550
1
2
1
JUMP_43X39
+5VALW
@
1
2
2
2
1
PR3514
100K_0402_5%
2
1
PR3513
100K_0402_5%
@
PC3549
0.1U_0201_25V6-K
@
2
PL3502
1
1
VOUT2
+3VL
+3VLP
2
PR3512
+5VALW_LX
+3VLP
100mA
1
1
2
1
PC3548
10U_0805_25V6K
2 0_0402_5%
5
1
LDO3
1+5VALW_SN 2
VBYP3
VCC1
2
{44,49,60,61} EC_ON
PC3547
10U_0805_25V6K
2
PR5914 1
C
2
JUMP_43X79
+3VALW
0.1U_0201_25V6-K
1
1
1
PC3546
2
7
+5VALW_VIN
EMC@
2
2
1U_0402_25V6-K
PJ5506
8A
1
1
2
1
@
2.5A
1
V20B+
4
2
JUMP_43X79
@
+3VALW_SN 2
PGOOD1
PC3538
PJ3502
2
PC3542
22U_0603_6.3V6-M
3
PC3551
22U_0603_6.3V6-M
+3VALW_P
+3VALW_P
4
2
PC3544
22U_0603_6.3V6-M
2
1
6
1
PC3553
22U_0603_6.3V6-M
2
1
VOUT1
PL3501
0.1U_0603_25V7-M
+3VALW_LX
PC3543
22U_0603_6.3V6-M
2
1
EN1
1
2
35
1
LX1_1
LX1_2
LX1_3
PC3552
22U_0603_6.3V6-M
2
1
9
BOOT1
Vout=3.3V± 5%
Vset=3.37V± 1.5%
OCP=12A
OVP=(1.15~1.25)*Vout
UVP=(0.55~0.65)*Vout
Fsw=500Khz
+3VALW
PC3555
22U_0603_6.3V6-M
2
1
+3VALW_PG
VIN1
PC3541
1
2
2
@
PC3537
0.1U_0201_25V6-K
10
VDDSW
1
2
11
+3VALW_EN
PU401
LV5083AGQUF_UQFN36_5X4
PR3511
+3VALW_BS 1
3
2
10_0603_5%
PC3539
22U_0603_6.3V6-M
2
1
2
1
2 0_0402_5%
PC3536
10U_0805_25V6K
PR5913 1
{44,49,60,61} EC_ON
EMC@
2
JUMP_43X79
25
+3VALW_VIN
1
1
PC3534
10U_0805_25V6K
2
1
2
1
2
PC3535
0.1U_0201_25V6-K
1.5A
B
PC3531
1U_0402_25V6-K
VOUT=3.07V
TDC=6A
OCP=10A
Fsw=600Khz
VOUT=5.01V
TDC=8A
OCP=12A
Fsw=600Khz
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/08/20
Deciphered Date
https://Dr-Bios.com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
5
4
3
2
Cover Page
2018/09/20
Size
C
Date:
Document Number
Rev
1.0
FG541/FG741
Wednesday, February 27, 2019
1
Sheet
60
of
69
5
4
3
2
1
D
D
C
C
B
B
A
A
Security Classification
Issued Date
T itle
LC Future Center Secret Data
2015/08/20
Deciphered Date
Cover Page
2018/09/20
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Size
D
Document Number
4
3
https://Dr-Bios.com
2
Rev
0.1
FG541/FG741
Thursday, January 03, 2019
Date:
5
1
Sheet
55
of
69
5
4
3
2
1
D
D
C
C
B
B
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/08/20
Deciphered Date
Cover Page
2018/09/20
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Size
B
Date:
5
4
3
https://Dr-Bios.com
2
Document Number
Re v
0.1
FG541/FG741
Thursday, January 03, 2019
Sheet
1
56
of
69
5
4
3
B+
Adaptor
135W/20V
D
EC_ON_5V
EN1
Richtek
RT6585B
Switch Mode
FOR SYS
Page 60
EC_ON
PGOOD
2
1
+5VLP/ 100mA
+5VALW/10A
ALW_PWRGD
1V0_MAIN_EN
EN
Silergy
SY8032
Converter
Page 70
EN2
+3VLP/ 100mA
SYSON
EN
GMT
G9661
LDO
+2.5V/600mA
PGOOD
FOR DDR
Richtek
RT8231
Switch Mode
SYSON
S5
S3
+0.6VS/1A
FOR DDR
Page 61
Page 62
+1.2V/10A
PGOOD
EC_ON_1.8V
EN
Silergy
SY8033
Converter
C
EC_ON_1V
EN
Page 59
VRAM_VDDQ_ADJ
EN
Silergy
SY8286
Converter
FOR PCH
Page 63
AOS
RT8237E
Converter
FOR GPU
+1.8VALW/3.4A
PGOOD
FOR GPU
TI
BQ24780SRUYR
Battery Charger
Switch Mode
D
PGOOD
FOR GPU
+3VALW/ 8A
SM_PG_CTRL
+1.0VGS/2A
Page 70
+1.05VALW/ 6A
C
PGOOD
FBVDDQ/ 20A
PGOOD
VDDQPWROK
Page 69
SMBus
Silergy
SY8286
Converter
SUSP#
EN
FOR CPU
Page 64
VCCIO/ 6A
PGOOD
VCC_CORE/80A/124A
MPS
MP2949
Switch Mode
FOR CPU Core
B
CPUCORE_ON
EN
Battery
Li-ion
3S1P/52.5WH
Page 65-68
VCCGT/25A/32A
NVVDD_EN
EN
Page 71
PGOOD
EN
FOR GPU NVVDD
Page 71
CPU_PWRGD
NVVDD/60A/127A
PGOOD
Richtek
NCP81278
Switch Mode
NVVDDS_EN
B
VCCSA/10A
Richtek
RT8813D
Switch Mode
FOR GPU NVVDD
VCCIO_PG
NVVDD_PWRGD
NVVDDS/18A/30.7A
PGOOD
NVVDDS_PWRGD
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/02/26
Deciphered Date
2018/09/20
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
5
4
https://Dr-Bios.com
3
Power Diagram
Size Document Number
Custom
Rev
1.0
FG541/FG741
Date:
2
Wednesday, February 27, 2019 Sheet
1
57
of
69
5
4
3
1
1
2
PR103
1
1
2
GND1
GND2
1
2
3
4
BAT54CW_SOT323-3
3
VCCRTC_D
2
45.3K_0402_1%
@
JRTC1
PD101
2
PC104 EMC@
1000P_0402_50V7K
1
RTC_VCC
D
1
PR104
1
RTC_VCC_R
2
2
1K_0402_1%
1
HIGHS_PJSSS56-B5000-1H
ME@
2
5
1
ADAPTER_ID {49,58}
1
VCCRTC
PR101
0_0402_5%
PC103
EMC@
0.1U_0402_25V6
GND2
3
2
GND1
PC102
EMC@
0.1U_0402_25V6
DETECT
GND3
1
POWER2
+3VL
PL102 EMC@
HCB2012KF-121T50_0805
1
2
APDIN
4
2
6
D
GND4
2
PC101 EMC@
1000P_0402_50V7K
POWER1
7
1
VIN
PL101 EMC@
HCB2012KF-121T50_0805
1
2
JDCIN1
2
DC IN：
1.DC IN connect apply for PN HIGHS_PJSSS56-B5000-1H_5P-T ,need replace
connector rate current 7A
RTC：
1.
2
HIGHS_WS33020-S0351-HF
ME@
PC105
1U_0402_10V6K
@
0ohm delete
2.the max VCCRTC & lt; 3.2V specification
3.RTC cable 35mm
C
C
PL103 EMC@
HCB2012KF-121T50_0805
1
2
ME@
VMB
BATT+
1
2
1
1
2
+3VALW
EMC@
PR109
750_0603_1%
1
PD103
AZC199-02S.R7G_SOT23-3
EC_SMB_CK1 {49,59,68}
2
1
2
PC107
0.01U_0402_25V7K
PR105
100_0402_1%
EMC@
1
PC106
1000P_0402_50V7K
2
2
3
PL104 EMC@
HCB2012KF-121T50_0805
1
2
PR106
100_0402_1%
ALLTO_C51126-112Z9-C
JBATT1
1
1 2
2 3
3 4
4 5
EC_SMCA
5 6
EC_SMDA
6 7
7 8
8 9
9 10
10 11
11 12
12 13
GND1 14
GND2 15
GND3 16
GND4
EMC_NS@
BATT_TEMP_IN
1
2
BATT_TEMP {49,59}
A/D
PR108
10K_0402_1%
1
ADAPTER_ID {49,58}
1
@
@
PD102
AZ5123-01F.R7GR_DFN1006P2X2
+3VALW
2
2 100K_0402_1%
2
1
B
PC109
0.1U_0402_25V6
2
1
PR107
PC108
680P_0402_50V7K
2
1
EC_SMB_DA1 {49,59,68}
B
battery IN:
1.20180821SF update to SP011808066
2.battery connector 12pin per pin 4.5A
ADP_ID:1. cost down solution
2.EC initial ID function
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/08/20
Deciphered Date
https://Dr-Bios.com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
5
4
3
2
Cover Page
2018/09/20
Size
C
Date:
Document Number
Rev
1.0
FG541/FG741
Wednesday, February 27, 2019
1
Sheet
58
of
69
5
4
3
2
1
D
D
N2
PQ312
AONS32314_DFN8-5
PR301
0.01_1206_1%
1
2
0.01U_0402_25V7K
2
EMC@
2
2
1
2
1
2
3
9
PR341
1
PMON
0_0402_5%
2
10
{49} VR_HOT#
13
14
21
ILIM
3
2
1
DIS_CHG
PC314
10U_0805_25V6K
2
3
2
1
18
BQ24780_BATDRV
PC321
1000P_0402_50V7K
EMC@
BATSRC
SRP
17
20
PR338 2
1
10_0603_5%
2
1
10_0603_5%
2
1
10_0603_5%
B
2
1
2
2
SRP
SRN
SRP_R
PR328
PROCHOT#
0.1U_0402_25V7-K
2
PC327
2
1
EMC@
1
29
PR321
2.2_0805_5%
PC342
10U_0805_25V6K
PAD
BATDRV
4
PC320
10U_0805_25V6K
IDCHG
CMPIN
CMPOUT
ILIM
2
16
2
1
PC341
100P_0402_50V8J
1
20K_0402_1%
PR340
2
{49,63} Psys
IADP
DL_CHG
22
1
8
23
PC319
10U_0805_25V6K
7
GND
3
1
ADP_I_R
IDCHG
2 0_0402_5%
2 100P_0402_50V8J
@
LODRV
BATT+
4
2
PC340
10U_0805_25V6K
1
1
0.1U_0402_25V7-K
PC323
2
1
PC325 1
SCL
PR317
0.01_1206_1%
2
PC322
0.1U_0402_25V7-K
PC324
100P_0402_50V8J
1
2
SDA
TB_STAT#
PR323
{49} ADP_I
B
ACOK
1
1
12
2.2UH_PCMB063T-2R2MS_8A_20%
PL301
2
2 0_0402_5% EC_SMB_CK1_R
PH_CHG
1
11
1
{49,58,68} EC_SMB_CK1
27
1 2
1
PR322
{49,58,68} EC_SMB_DA1
DH_CHG
2
5
4
26
2.2_0603_5%
5
PR320
2 0_0402_5% EC_SMB_DA1_R
PHASE
BATPRES#
2 0_0402_5%
0.047U_0603_16V7K
PC318
2 2
1
PR316
SRN
19
SRN_R
PR329
15
ACIN_R
1
{49} ACIN
2
BST_CHG 1
ACDRV
PU301
4
HIDRV
BQ24780SRUYR_QFN28_4X4
ACDRV
CMSRC
25
PQ316
AON6380_DFN8-5
BTST
3
1
ACDET
PC309
0.01U_0402_25V7K
CMSRC
24
5
PC316
REGN
PQ317
AON6380_DFN8-5
6
ACDET
2.2U_10V_K_X5R_0603
VCC
3
2
1
2
28
ACN
780_VCC
ACP
1U_0603_25V6K
PC315
2
1
PC313
10U_0805_25V6K
1
2
2
ACN
1
1
ACP
2
BQ24780_VDD
1
EMC@ PC310
2200P_0402_50V7K
1
BAT54CW_SOT323-3
PD301
2
V20B+
2
1
2
1
PR325
PC308
0.01U_0402_25V7K
C
PR314
10_1206_5%
7.15K_0402_1%
1
PR303
499K_0402_1%
PR315
2
4
2
PC307
0.1U_0402_25V7-K
BATT+
VIN
PR313
43K_0402_1%
1
EMC@
PC305
1
1
2
PR311
4.02K_0603_1%
PR310
4.02K_0603_1%
1
PC7631
0.1U_0402_25V7-K
VIN
2
EMC@
PQ314
AONS32314_DFN8-5
1
PC7629
2200P_0402_50V7K
BQ24780_BATDRV
1
C
V20B+
PC7630
4700P_0402_50V7K
1
2
3
EMC@
1
PC304
0.01U_0402_25V7K
EMC@
2
1
2
PC303
0.01U_0402_25V7K
4
ACDRV_BG
1
PC302
0.022U_0402_25V7K
2
PR302
4.7_0603_5%
5
ACDRV_FG 4
1
1
2
4
2
PC301
470P_0402_50V7K
1
5
N2_J
5
1
1
2
3
2
1
2
3
VIN
PC306
0.1U_0402_25V7-K
N1
PQ311
AON6366E_DFN8-5
1
TB_STAT#
PR330
0_0402_5%
ILIM_R
2
1
1
2
BATT_TEMP {49,58}
PR332
32.4K_0402_1%
PR333
100K_0402_1%
2
1
2
1
PR331
143K_0402_1%
PC328
0.1U_0402_25V7-K
+3VALW
A
A
charge current：
1C 5A
charge voltage：
12.6V
charge frequency：
800K
ILIM pin：
charge7A, turbo-discharge-10A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/08/20
https://Dr-Bios.com
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
5
4
3
Cover Page
2018/09/20
Size Document Number
Custom
Date:
2
Rev
1.0
FG541/FG741
Wednesday, February 27, 2019
1
Sheet
59
of
69
A
PR501
1
B
2 0_0402_5%
C
D
VDDQ_EN
{49,51} SYSON
2
PC508 @
0.1U_0402_10V7K
1
2
PC503 @
0.1U_0402_10V7K
1
2
PC506 @
0.1U_0402_10V7K
1
1
VTT_EN
1
PC505 @
0.1U_0402_10V7K
1
{49} EC_VPP_PWREN
+2.5V_DDR_EN
PC502
1
2
PC504 @
0.1U_0402_10V7K
1
1U_0402_25V6-K
PR525
2
1 1M_0402_5%
+1.8VALW_L_EN
+2.5V_DDR_EN
29
+1.8VALW_L_EN
1
+1.05VALW_EN
11
+1.8VALW_B_EN
VDDQ_EN
VTT_EN
16
31
36
EN_LDO1
VSYS
28
2
2 0_0402_5%
EC_ON {44,49,60}
2
2.2U_10V_K_X5R_0603
PR505
1
2
10_0402_1%
VDDQ_VIN
2 0_0402_5%
1
SH00000PK0J, S COIL 0.47UH +-20% PCMB063T-R47MS 18A
+3VALW
SDA
EN_LDO2
SCL
EN_V1P0A
OT
EN_V1P8A
EN_VDDQ
EN_VTT
PG_V1P0A
PG_V1P8A
PG_VDDQ
25
PMIC_SMB_DAT1
26
PMIC_SMB_CLK1
24
PMIC_ALERT#
22
21
23
PR510
1
PR511
1
PR512
2 0_0402_5%
2
EC_SMB_DA3 {49,63}
2 0_0402_5%
EC_SMB_CK3 {49,63}
1 0_0402_5%
@
+1.05VALW_PG
H_PROCHOT# {6,49,63}
1
PAD PTC501
@
1
+1.8VALW_B_PG
PR513
R_0402
1
100K_0402_1%
2
1
PR521
PC500
PAD PTC502
@
2
1
+5VLP
+1.05VALW_EN
PMIC_EN
PR508
2 0_0402_5%
PR520
10_0603_5%
2
GND
1
PMIC_VCC
1
VSYS_PMIC
PR506
+1.8VALW_B_EN
41
2 0_0402_5%
9
1
27
PR507
1
VCC
{49,51} PCH_PWR_EN
2 0_0402_5%
PR503
PMIC_EN
{6} CPU_DRAMPG_CNTL
VDDQ_PGOOD
VDDQ_PGOOD {49}
PL503
VSNS_VDDQ
37
PC521
10U_0603_10V6K
4
LDO2
VIN_LDO2
FB_LDO2
3
2
PU501
LV5075BGQV_QFN40_5X5
PJ507
2
1
@
1
4
+2.5V_DDR
PC516
22U_0603_6.3V6-M
PC536
22U_0603_6.3V6-M
2
1
PC514
22U_0603_6.3V6-M
PC513
22U_0603_6.3V6-M
2
1
PC515
22U_0603_6.3V6-M
2
1
1
2
PC535
22U_0603_6.3V6-M
2
@
1
1
+1.8VALW
2
@
PJ5507
2
2
1
V20B+
1
JUMP_43X79
0.47UH_PCMB063T-R47MS_18A_20%
JUMP_43X39
PL501
LX_VDDQ
1
PJ509
+1.2V_P
2
2
+2.5V_P 2
6
2
1
JUMP_43X39
PC512
22U_0603_6.3V6-M
2
1
1
UG_VDDQ
LDO1
2
3
2
1
VIN_LDO1
5
5
4
3
2
1
LG_VDDQ
PQ502
AON7516_DFN8-5
1
1
2
1
2
+1.2V_P
PC520
22U_0603_6.3V6-M
2
+2.5V_DDR_VIN
2
+3VALW
@
1
+1.05VALW
JUMP_43X79
2.2_0805_5%
PR518
EMC_NS@
@
@
PC531
22U_0603_6.3V6-M
LGATE_VDDQ
CS_VDDQ
33K_0402_1%
PJ5510
1
1
PJ504
+1.8VALW_FB
VDDQ_VIN
PC518
2
JUMP_43X79
PC530
22U_0603_6.3V6-M
2
1
30
0.1U_0603_25V7-M
2
2
1
1
PR526
0_0603_5%
LG_VDDQ
@
PJ502
2
@
PC529
22U_0603_6.3V6-M
2
1
CS_VDDQ
LX_VDDQ
35
PC528
22U_0603_6.3V6-M
2
1
@
2
BST_VDDQ
34
1
VSNS_VTT
2
PR515
1
32
+1.05VALW_FB
PC526
10U_0805_25V6K
VTT
LX_VDDQ
40
2
39
1
VIN_VTT
BS_VDDQ
VTT
PC519
22U_0603_6.3V6-M
EMC_NS@
2
38
10U_0603_10V6K
@
1
EMC_NS@
PC527
22U_0603_6.3V6-M
2
1
1
1
2
JUMP_43X39
UG_VDDQ
@
10U_0805_25V6K
PC525
2
33
PL502
1
2
1UH_PH041H-1R0MS_3.8A_20%
PC538
22U_0603_6.3V6-M
PJ505
+0.6VS
UGATE_VDDQ
PR536
PC539
4.7_0603_5% 1200P_0402_50V7-K
1
2
1
2
+1.8VALW_FB
EMC@
2
1
2
+1.2V_P
LX_1P8
20
PC524
0.1U_0402_25V7-K
PC517
1
2
17
18
1
1
2
VO_V1P8A
EMC_NS@
PC511
22U_0603_6.3V6-M
2
1
LX_V1P8A1
LX_V1P8A2
EMC_NS@
2
VIN_V1P8A
+1.05VALW_FB
2
PC544
0.47UH_PCMB063T-R47MS_18A_20%
1200P_0402_50V7-K
1
2
1
19
10
1
PR535
4.7_0603_5%
1
2
2
+1.8VALW_B_VIN
PC534
22U_0603_6.3V6-M
LX_1P05
2
VO_V1P0A
12
13
14
15
1
@
1
LX_V1P0A1
LX_V1P0A2
LX_V1P0A3
LX_V1P0A4
1
1
1
2
JUMP_43X39
VIN_V1P0A1
VIN_V1P0A2
2
2
7
8
5
PJ5509
+5VALW
2
JUMP_43X39
+1.05VALW_B_VIN
PQ501
AON7380_DFN8-5
@
1
EMC_NS@
1
PC510
0.1U_0402_10V7K
+5VALW
2
22U_0603_6.3V6-M
PC509
2
1
PJ5508
2
2
2
@
1
1
+1.2V
JUMP_43X79
PC533
1000P_0402_50V7K
EMC_NS@
1.2V: setting 1.21V
TDC:8A
OCP:125mV/25A
OVP:120%
frequency:1Mhz
0.47UH_PCMC063T-R47MN_17.5A_20% DCR no limit
1.05V: setting 1.05V
TDC:6A
OCP:10A
OVP:120%
frequency:1Mhz
1.8V: setting 1.81V
TDC:3A
OCP:6A
OVP:120%
frequency:1Mhz
3
3
4
4
Security Classification
Issued Date
T itle
LC Future Center Secret Data
2015/08/20
Deciphered Date
Cover Page
2018/09/20
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Size
D
Date:
A
B
C
https://Dr-Bios.com
D
Document Number
Rev
1.0
FG541/FG741
Wednesday, February 27, 2019 Sheet
61
of
69
A
B
C
D
1
1
1
+3VS
@
PC716
22U_0603_6.3V6-M
2
1
PC715
22U_0603_6.3V6-M
2
1
2
PC712
220P_0402_50V7K
1
2
17
PC709
22U_0603_6.3V6-M
2
1
PC708
22U_0603_6.3V6-M
2
1
1
PR714
10_0402_1%
1
VCC
12
10
16
PR708
499_0402_1%
2
FB
NC3
NC1
NC2
+VCCIO_P
2
@
PJ2402
2
2
1
1
VCCIO
JUMP_43X79
2
1
2
1
EMC_NS@
1
@
2
BYP
+VCCIO_FB
2
2
0_0402_5%
PC677
0.1U_0402_10V7K
1
+VCCIO_EN
14
PL701
1UH_PCMB063T-1R0MS_12A_20%
+VCCIO_SW
EMC_NS@
15
PR701
ILMT
EN
1
2
PC702
0.1U_0603_25V7-M
6
19
20
1
13
11
@
+VCCIO_PG
+VCCIO_BS
PR711
4.7_0603_5%
1
LX1
LX2
LX3
9
1
1
PR712
2
0_0402_5%
{49} EC_VCCIO_EN
GND1
GND2
GND3
GND4
PG
BS
2
EMC@
1
2
PC704
2200P_0402_50V7K
2
PC703
10U_0805_25V6K
1
2
1
PC701
10U_0805_25V6K
2
7
8
18
21
IN1
IN2
IN3
IN4
PC718
680P_0402_50V7K
5
4
3
2
PR709
35.7K_0402_1%
2
PU702
+VCCIO_VIN
1
1
1
PC720
2.2U_0402_10V6-K
2
@ JUMP_43X79
SY8286RAC_QFN20_3X3
PJ701
2
V20B+
2
PR704
100K_0402_1%
PR713
1
2
VCC_IO_SEN {10}
1
0_0402_5%
PR710
2
60.4K_0402_1%
3
3
VCCIO:FB=0.6V/0.954V
TDC=6A
OCP:10A
OVP:120%
frequency:500Khz
remove sense pull high in power side
4
Title
LC Future Center Secret Data
Security Classification
Issued Date
4
Deciphered Date
2015/08/20
Cover Page
2018/09/20
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Size Document Number
Custom
Date:
A
B
C
https://Dr-Bios.com
Rev
1.0
FG541/FG741
Wednesday, February 27, 2019
D
Sheet
62
of
69
5
4
3
2
1
+3VALW
+3VL
1
1
L340 H82 PN:SA00009Q400
AGND_2949
PR5842
PR2905
4.7_0402_5% 4.7_0402_5%
+3VS
28
31
VDD18
1
{6,49,61} H_PROCHOT#
29
MP2949A_SDIO#
EN
133K_0402_1%
VIN_SEN
VRRDY
SCLK
SLP_S0#
ALT#
SDA_P
SDIO
SCL_P
VRHOT#
PE
47
2
PR2912
10K_0402_1%
1
MP2949A_SCLP
36
MP2949A_PE
PR2920 1
1
AGND_2949
+3VALW
VDIFFA
STB
MP2949A_VFBB
15
2
1
38
MP2949A_PWM6
39
MP2949A_PWM5
40
MP2949A_PWM4
41
MP2949A_PWM3
42
MP2949A_PWM2
43
MP2949A_PWM1
EC_SMB_DA3
{49,61} EC_SMB_DA3
PWM6_SA {66}
6
1
2.2K_0404_4P2R_5%
MP2949A_SDAP
D
VFBA
PWM5
QH4A
L2N7002KDW1T1G_SOT363-6
PWM5_GT {65}
C
VFBB
VFBC
PWM4
PWM4_VCORE {64}
EC_SMB_CK3
{49,61} EC_SMB_CK3
3
MP2949A_SCLP
4
D
11
MP2949A_VFBC
C
RPH9
3
4
VDIFFC
5
7
+3VALW
SYNC {64,65,66}
VDIFFB
PWM6
MP2949A_VFBA
34
2
1 PR2923 MP2949A_VDIFFC 14
G
6
1 PR2922 MP2949A_VDIFFB 10
8.25K_0402_1% 2
CPU_PWRGD {49}
G
1 PR2919 MP2949A_VDIFFA
2
2.15K_0402_1% 2
2 0_0402_5%
PMBUS PU at 3V_EC in EE page
PMBUS address: 20H
PR2918
2
10K_0402_1%
1.43K_0402_1%
D
MP2949A_SDAP
33
5
6
MP2949A_SLPS0#
32
GND1
GND2
CVILU_CI1804M2HR0-NH
AGND_2949 ME@
@
2M_0402_1%
MP2949A_VRRDY
35
1
MP2949A_VINSEN
30
2
1
2
3
4
S
27
MP2949A_ALT#
2 0_0402_5%
2 PR2909 1 10_0402_1%
{6} SVID_DATA
37
MP2949A_SCLK
MP2949A_VRHOT#
PR2906 1
{6} SVID_ALERT#
PSYS
2
MP2949A_EN
2 PR2904 1 49.9_0402_1%
{6} SVID_CLK
46
VDD33
MP2949A_PSYS
2 PR2907 1
AGND_2949
PR2908
1
2
3
4
S
@
1
2
PR2901
45.3_0402_1%
1
2
PR2902
75_0402_1%
1
2
PR2903
100_0402_1%
44
AGND_2949
PU2901
PC2901
0.1U_0402_25V7-K
0.01U_0402_25V7K
JP2
2
PR2911
10K_0402_1%
VCCST
V20B+
PC2904
1
2
2
PR2948
10K_0402_1%
D
PC2903
1U_0402_10V6K
1
4.7U_0603_6.3V6K
PC2902
2
1
2 0_0402_5%
MP2949A_VDD18
{6,49} CPUCORE_ON
MP2949A_VDD33
@
PR2915 1
1
2 0_0402_5%
AGND_2949
2
PR5841 1
1
0_0402_5%
2
26
{49,59} PSYS
2
2
@
PR5840
1
PWM3
{9} VCCCORE_SENSE
PR2925 1
2 0_0402_5% MP2949A_VOSENA
8
{9} VSSCORE_SENSE
PR2926 1
2 0_0402_5% MP2949A_VORTNA
9
VOSENA
PWM2
VORTNA
PWM1
1
PRPR2929
2 0_0402_5% MP2949A_VOSENB
12
{9} VSSGT_SENSE
PR2930 1
2 0_0402_5% MP2949A_VORTNB
13
{10} VCCSA_SENSE
PR2933 1
2 0_0402_5% MP2949A_VOSENC
16
{10} VSSSA_SENSE
PR2935 1
2 0_0402_5% MP2949A_VORTNC
17
{9} VCCGT_SENSE
18
{63} CSSUMA
19
{63} CSSUMB
20
{63} CSSUMC
AGND_2949
1 PR2941
MP2949A_IREF
24
PWM2_VCORE {64}
PWM1_VCORE {64}
CS1_VCORE {64}
CS2_VCORE {64}
VORTNB
CS3_VCORE {64}
CS4_VCORE {64}
VOSENC
VORTNC
CS1
CS2
5
MP2949A_CS1
PR2934 1
2 1.5K_0402_1%
4
MP2949A_CS2
PR2936 1
2 1.5K_0402_1%
3
MP2949A_CS3
PR2938 1
2 1.5K_0402_1%
2
MP2949A_CS4
PR2939 1
2 1.5K_0402_1%
1
MP2949A_CS5
PR2940 1
2 1.5K_0402_1%
CSSUMB {63}
48
MP2949A_CS6
PR2942 1
2 1.5K_0402_1%
CSSUMC {63}
CSSUMA {63}
CS_SUMA
CS_SUMB
CS3
CS_SUMC
CS5
2
L2N7002KDW1T1G_SOT363-6
VOSENB
CS4
61.9K_0402_1%
QH4B
PWM3_VCORE {64}
IREF
CS6
B
B
25
MP2949A_ADDRP
PR2943 1
2 0_0402_5%
AGND_2949
CS5_GT {65}
IMONB
TEMP
45
TEMP {64,65,66}
2
AGND
1
PJ2901 @
1
2
1
PR2947
49.9K_0402_1%
MP2949AGQKT-0247-Z_TQFN48_6X6
2
IMONC
49
1
2
PR2950
3.4K_0402_1%
1
2
PC2908
68P_0402_50V8J
332K_0402_1%
PR2946
2
1
1
2
MP2949A_IMONC 23
PR2949
1.37K_0402_1%
2
PC2907
220P_0402_50V7K
115K_0402_1%
PR2945
2
1
1
2
PR2951
499_0402_1%
2
CS6_SA {66}
IMONA
ADDR_P
MP2949A_IMONB 22
1
1
2
PR2944
26.1K_0402_1%
PC2906
560P_0402_50V7-K
1
MP2949A_IMONA 21
PC2909
1U_0402_10V6K
JUMPER
AGND_2949
AGND_2949
AGND_2949
AGND_2949
AGND_2949
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/08/20
Deciphered Date
https://Dr-Bios.com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
5
4
3
2
Cover Page
2018/09/20
Size
C
Date:
Document Number
Rev
0.3
FG541/FG741
Wednesday, February 27, 2019
1
Sheet
63
of
69
3
2
0_0603_5%
11
PC3004
22U_25V_M
PC3003
PL3001
0.15UH_PCME064T-R15MS0R667_36A_20%
SW_A1
9
LG_A1
1
2
2
1
7
EMC@
CPUCORE_SN1
PJ3001
JUMPER
1
1
1
PQ3004
3
2
1
2
AON6324_DFN8-5
1
EMC@
PR3012
1
PR3013
1
1
2
1
2
523_0402_1%
PR3016
1.5K_0402_1%
CPUCORE_VIN
PC3050
0.01U_0402_25V7K
PC3049
10U_0805_25V6K
2
1
1
2
2
PC3020
22U_0603_6.3V6-M
PC3019
22U_0603_6.3V6-M
1
2
PC3018
22U_0603_6.3V6-M
1
1
2
2
PC3017
22U_0603_6.3V6-M
1
2
PC3016
22U_0603_6.3V6-M
PC3015
22U_0603_6.3V6-M
1
1
2
2
PC3014
22U_0603_6.3V6-M
1
PC3013
22U_0603_6.3V6-M
1
2
1
2
PC3040
22U_0603_6.3V6-M
PC3039
22U_0603_6.3V6-M
1
2
PC3038
22U_0603_6.3V6-M
1
1
2
2
PC3037
22U_0603_6.3V6-M
1
2
PC3036
22U_0603_6.3V6-M
PC3035
22U_0603_6.3V6-M
1
2
1
1
2
PC3030
22U_0603_6.3V6-M
PC3029
22U_0603_6.3V6-M
1
1
2
2
PC3028
22U_0603_6.3V6-M
1
2
PC3027
22U_0603_6.3V6-M
PC3026
22U_0603_6.3V6-M
1
1
2
2
PC3025
22U_0603_6.3V6-M
PC3024
22U_0603_6.3V6-M
PL3003
0.15UH_PCME064T-R15MS0R667_36A_20%
SW_A3
1
PJ3005
JUMPER
EMC@
4
MP8693GDT-Z_TQFN12_2x3
2
3
2
1
PC3052
1U_0402_10V6K
B
1
LG_A3
6
PR3017
2.2_0805_5%
2
@
2
PQ3006
AON6324_DFN8-5
7
1
9
1
EMC@
PJ3006
JUMPER
PR3018
2.26K_0402_1%
PC3054
1
B
2
0.47U_0402_25V6K
PR3020
1
@
2
11
CPUCORE_SN3
1
VCCCPUCORE
2
0_0603_5%
1
GND
ISENN
2
1
2
ISENP
10
2
PC3053
2200P_0402_50V7K
LGATE
VCC
1
1
SW
EPAD
8
1
0.22U_0402_25V6-K
CS
13
+5VALW
1
PR3029
1
5
{63} CS3_VCORE
BST
TEMP
2
EMC@
4
PC3051
5
2
12
2
SYNC
4
{63,64} SYNC
{63,64,65,66} TEMP
HGATE
1
3
2
1
PWM
2
PC3048
10U_0805_25V6K
5
PU3003
3
2
2
110_0402_1%
PQ3005
AON6380_DFN8-5
2
Vboot=0V
Loadline=1.8mΩ
Ripple=+30mV/-10mV(0A-0.5A)
Ripple=± 10mV(0.5A-TDC)
Ripple=± 15mV(TDC-Iccmax)
TDC=80A (H42 =60A)
Iccmax=128A(H42 =86) OCP=155A(H42=96A)
OVP=VID+400mV
OVP=2V(during SS)
UVP=VID-300mV
Fsw=500Khz
4.7K +-1% TSM0A472F34D1RZ
PH3002
PR3014
2
511_0402_1%
2 0_0402_5% HG_A3
@
C
2
PR3015
PR5845 1
@
PC3047
1
0.47U_0402_25V6K
2
Phase3
@
PJ3004
JUMPER
PR3010
2.26K_0402_1%
1
{63} PWM3_VCORE
1
2
@
PJ3003
JUMPER
110_0402_1%
1
1
1
MP8693GDT-Z_TQFN12_2x3
CD@
@
2
2
EMC@
4
CD@
2
PC3043
0.01U_0402_25V7K
1
PC3042
10U_0805_25V6K
2
3
2
1
LG_A2
6
PC3045
1U_0402_10V6K
2
C
7
CPUCORE_SN2
ISENN
2
@
1
GND
1
PR3009
2.2_0805_5%
1 1
ISENP
10
PL3002
0.15UH_PCME064T-R15MS0R667_36A_20%
SW_A2
9
2
VCC
0_0603_5%
11
1
LGATE
2
EMC@
2
2
+5VALW
SW
EPAD
8
1
PC3046
2200P_0402_50V7K
CS
13
@
VCCCPUCORE
PR3028
2
0.22U_0402_25V6-K
TEMP
5
{63} CS2_VCORE
1
1
5
2
{63,64,65,66} TEMP
4
PC3044
1
2
1
PC3041
10U_0805_25V6K
5
CPUCORE_VIN
PU3002
12
2
1.5K_0402_1%
PQ3003
AON6380_DFN8-5
HG_A2
2 0_0402_5%
PR5844 1
CD@
2
1
2
110_0402_1%
BST
2
523_0402_1%
PR3007
HGATE
+
2
PC3034
22U_0603_6.3V6-M
511_0402_1%
PR3008
1
2
PC3011
22U_0603_6.3V6-M
2
PC3033
22U_0603_6.3V6-M
110_0402_1%
2
1
1
2
2
PC3012
22U_0603_6.3V6-M
2
4.7K +-1% TSM0A472F34D1RZ
PR3005
PH3001
PR3006
1
1
PC3022
1
0.47U_0402_25V6K
2
1
PR3004
SYNC
1
D
PR3002
2.26K_0402_1%
PC3032
22U_0603_6.3V6-M
2
3
2
1
EMC@
PWM
+
2
18pcs 22uf MLCC
PC3031
22U_0603_6.3V6-M
4
PQ3002
4
1
PJ3002
JUMPER
PC3023
22U_0603_6.3V6-M
GND
3
2
@
2
@
2
PR3001
2.2_0805_5%
AON6324_DFN8-5
{63,64} SYNC
+
@
PC3010
1U_0402_10V6K
Phase2 PWM2_VCORE
{63}
1
PC5860
1
+
6
ISENN
MP8693GDT-Z_TQFN12_2x3
2
1
2
330U_B2_2.5VM_R9M
1
1
ISENP
68A
VCCCPUCORE
PR3027
2
PC3008
330U_D2_2V_Y
1
1
VCC
10
VCCCPUCORE
1
LGATE
2
2
EPAD
8
+5VALW
1
D
SW
V20B+
@
4
PC3005
1
1
2
CS
13
12
0.22U_0402_25V6-K
TEMP
5
{63} CS1_VCORE
BST
+
PC3021
2200P_0402_50V7K
2
{63,64,65,66} TEMP
HGATE
SYNC
2
EMC@
1
3
2
1
PWM
4
5
3
{63} PWM1_VCORE
{63,64} SYNC
1
0.01U_0402_25V7K
2
PU3001
PC3002
10U_0805_25V6K
1
5
HG_A1
2 0_0402_5%
PR5843 1
Phase1
PQ3001
AON6380_DFN8-5
2
PC3001
10U_0805_25V6K
CPUCORE_VIN
8A
CPUCORE_VIN
PC3007
330U_D2_2V_Y
4
PC3006
330U_D2_2V_Y
5
PR3021
2
1
110_0402_1%
4.7K +-1% TSM0A472F34D1RZ
PH3003
PR3022
2
1
2
511_0402_1%
1
2
523_0402_1%
PR3025
1
PR3024
1
2
1.5K_0402_1%
2
110_0402_1%
CPUCORE_VIN
ISENP
PC5855
1
EMC@
2
@
2
PR5851
2.2_0805_5%
6
4
MP8693GDT-Z_TQFN12_2x3
PC5857
1U_0402_10V6K
PQ5810
2
3
2
1
2
1
ISENN
LG_A4
7
AON6324_DFN8-5
EMC@
1
A
PR5853
1
CPUCORE_SN4
GND
9
1
PJ5504
JUMPER
1
SW
LGATE
VCC
PL5804
0.15UH_PCME064T-R15MS0R667_36A_20%
SW_A4
2
EPAD
0_0603_5%
11
1
CS
VCCCPUCORE
2
@
PJ5505
JUMPER
1
8
10
0.22U_0402_25V6-K
TEMP
2
EMC@
PR5850
1
PR5852
2.26K_0402_1%
PC5858
2
13
+5VALW
BST
2
1
{63} CS4_VCORE
SYNC
1
2
5
PC5856
1
PC5859
2200P_0402_50V7K
2
HGATE
3
2
1
{63,64} SYNC
{63,64,65,66} TEMP
PWM
4
5
4
12
0.01U_0402_25V7K
PU5803
3
{63} PWM4_VCORE
2
2
PQ5809
AON6380_DFN8-5
HG_A4
2 0_0402_5%
PR5849 1
Phase4
PC5854
10U_0805_25V6K
5
1
PC5853
10U_0805_25V6K
8A
1
1
2
0.47U_0402_25V6K
A
4.7K +-1% TSM0A472F34D1RZ
PR5854
PH3202
PR5855
2
1
110_0402_1%
2
1
2
511_0402_1%
1
2
523_0402_1%
PR5856
1
PR5857
1
2
2
1.5K_0402_1%
110_0402_1%
Security Classification
Issued Date
Title
LC Future Center Secret Data
2015/08/20
Deciphered Date
Cover Page
2018/09/20
https://Dr-Bios.com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF
Size Document
Custom
LC FUTURE CENTER.
Date:
5
4
3
2
Number
Re v
0.3
FG541/FG741
Wednesday, February 27, 2019
1
Sheet
64
of
69
5
4
3
2
1
D
D
CPUCORE_VIN
PC3132
2
EMC@
0.01U_0402_25V7K
PC3131
10U_0805_25V6K
1
2
2 0_0402_5%
1
Vboot=0V
Loadline=2.7mΩ
Ripple=+30mV/-10mV(0A-0.5A)
Ripple=± 10mV(0.5A-TDC)
Ripple=± 15mV(TDC-Iccmax)
TDC=25A Iccmax=32A OCP=6548A
OVP=2V(during SS)
OVP=VID+400mV
UVP=VID-300mV
Fsw=500Khz
5
PR5847 1
C
PC3130
10U_0805_25V6K
2
1
6A
PQ3103
AON6380_DFN8-5
HG_B2
4
C
PU3102
+
2
PC3106
330U_D2_2V_Y
PC3105
330U_D2_2V_Y
2
1
@
PR3110
2.26K_0402_1%
PC3116
22U_0603_6.3V6-M
2
1
PC3118
22U_0603_6.3V6-M
2
1
PC3119
22U_0603_6.3V6-M
2
1
PC3117
22U_0603_6.3V6-M
2
1
PC3127
22U_0603_6.3V6-M
2
1
PC3128
22U_0603_6.3V6-M
2
1
PC3129
22U_0603_6.3V6-M
2
1
511_0402_1%
120_0402_1%
PC3115
22U_0603_6.3V6-M
2
1
4.7K +-1% TSM0A472F34D1RZ
PH3102
PR3114
1
2
1
2
2
PC3126
22U_0603_6.3V6-M
2
1
1
PC3125
22U_0603_6.3V6-M
2
1
PR3113
2
PC3114
22U_0603_6.3V6-M
2
1
1
PC3124
22U_0603_6.3V6-M
2
1
@
PR3112
B
PC3113
22U_0603_6.3V6-M
2
1
2 0.33U_10V_K_X5R_0402
PC3112
22U_0603_6.3V6-M
2
1
1
PC3123
22U_0603_6.3V6-M
2
1
PC3136
PC3122
22U_0603_6.3V6-M
2
1
2
1
EMC@
+
@
PJ3104
JUMPER
PC3111
22U_0603_6.3V6-M
2
1
MP8693GDT-Z_TQFN12_2x3
PC3134
1U_0402_10V6K
PJ3103
JUMPER
PC3121
22U_0603_6.3V6-M
2
1
4
1
@
2
EMC@
PC3110
22U_0603_6.3V6-M
2
1
LG_B2
6
PR3109
2.2_0805_5%
3
2
1
2
1
ISENN
PQ3104
AON6324_DFN8-5
7
GFXCORE_SN2
GND
9
PC3120
22U_0603_6.3V6-M
2
1
ISENP
32A
1
LGATE
VCC
VCCGFXCORE
PL3102
0.15UH_PCME064T-R15MS0R667_36A_20%
1
2
SW_B2
11
2
EPAD
SW
2
0_0603_5%
1
CS
1
1
0.22U_0402_25V6-K
2
8
10
1
TEMP
PR3118
PC3135
2200P_0402_50V7K
13
+5VALW
BST
PC3133
1
2
1
5
{63} CS5_GT
SYNC
12
2
2
HGATE
3
2
1
4
{63} SYNC
{63,64,66} TEMP
PWM
5
3
{63} PWM5_GT
@
@
@
@
B
523_0402_1%
PR3115
1
PR3116
1
2
1.5K_0402_1%
2
120_0402_1%
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/08/20
Deciphered Date
https://Dr-Bios.com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
5
4
3
2
Cover Page
2018/09/20
Size
C
Date:
Document Number
Rev
0.3
FG541/FG741
Wednesday, February 27, 2019
1
Sheet
65
of
69
4
3
2
D
D
PC3203
0.01U_0402_25V7K
PC3211
22U_0603_6.3V6-M
2
1
PC3221
22U_0603_6.3V6-M
PC3212
22U_0603_6.3V6-M
2
1
PC3210
22U_0603_6.3V6-M
2
1
PC3220
22U_0603_6.3V6-M
1
2
@
2
4.7K +-1% TSM0A472F34D1RZ
PR3206
PH3201
1
2
1
2
2
511_0402_1%
240_0402_1%
PR3207
2
1
PC3209
22U_0603_6.3V6-M
2
1
PC3208
22U_0603_6.3V6-M
2
1
PC3218
22U_0603_6.3V6-M
1
2
PR3205
1
PR3208
PC3219
22U_0603_6.3V6-M
1
2
PC3207
22U_0603_6.3V6-M
2
1
1
910_0402_1%
@
@
PC3215
0.22U_0402_25V6-K
2
PC3217
22U_0603_6.3V6-M
2
1
1
PR3202
1.5K_0402_1%
PR3204
1
@
PJ3202
JUMPER
PC3206
22U_0603_6.3V6-M
2
1
2
3
2
1
EMC@
@
PJ3201
JUMPER
PC3205
22U_0603_6.3V6-M
2
1
4
MP8693GDT-Z_TQFN12_2x3
PC3213
1U_0402_10V6K
EMC@
1
6
B
C
2
7
PR3201
2.2_0805_5%
2
1
2
LG_C1
VCCSA_SN
ISENN
2
1
ISENP
GND
1
2
VCC
9
VCCSA
10A
PL3201
SW_C1
1
SW
LGATE
11
0.47UH_PCMB063T-R47MS3R675_18A_20%
2
10
2
1
8
+5VALW
EPAD
PR3209
1
0.22U_0402_25V6-K 0_0603_5%
TEMP
CS
PC3204
2
Loadline=10.3mΩ
Vboot=1.05V
Ripple=+30mV/-10mV(0A-0.5A)
Ripple=± 10mV(0.5A-TDC)
Ripple=± 15mV(TDC-Iccmax)
TDC=10A Iccmax=11.1A OCP=18A
OVP=2V(during SS)
OVP=VID+400mV
UVP=VID-300mV
Fsw=500Khz
1
13
4
1
2
{63} CS6_SA
BST
1
PC3214
2200P_0402_50V7K
5
SYNC
12
PQ3202
AON7516_DFN8-5
2
HGATE
2
EMC@
3
2
1
{63} SYNC
{63,64,65} TEMP
PWM
5
4
1
PQ3201
AON7380_DFN8-5
5
PU3201
3
{63} PWM6_SA
PC3202
10U_0805_25V6K
1
2
HG_C1
2
0_0402_5%
PC3201
10U_0805_25V6K
2
1
CPUCORE_VIN
PR5848 1
C
1
PC3216
22U_0603_6.3V6-M
2
1
5
1
@
@
B
1.5K_0402_1%
2
910_0402_1%
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/08/20
Deciphered Date
Cover Page
2018/09/20
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Size
B
Date:
5
4
3
https://Dr-Bios.com
2
Document Number
Re v
1.0
FG541/FG741
Wednesday, February 27, 2019
Sheet
1
66
of
69
A
B
GPU_ALL_B+
C
D
V20B+
PR5553
0.005_1206_1%
3A
3
PFM
23
SS
PFM
SS
1
PGND_3
PGND_4
+3VS
PC5529
330U_D2_2V_Y
PC5519
22U_0603_6.3V6-M
2
PC5518
22U_0603_6.3V6-M
2
1
1
1
PC5517
22U_0603_6.3V6-M
2
1
@
15
19
{28} VRAM_VDDQ_ADJ
PR5514 1
2 0_0402_5%
PC5513
22U_0603_6.3V6-M
1
PR5509
0_0402_5%
PR5513
8.2K_0402_1%
@
CD@
@
@
{29} FBVDD_VCC_SENSE
2
D
2
PQ5501
LBSS139WT1G_SC70-3
G
S
PR5512 32.4k for Micron RAM 1.55V; PR5512 41.2k for 1.5V, EE use 76 bom control
PR5559
100K_0402_1%
2
FBVDD_VCC_SENSE_R
PC5512
22U_0603_6.3V6-M
2
1
VRAM_VDDQ_ADJ
L = 1.354V
H = 1.507V
14
4
PR5511
100K_0402_1%
PC5511
22U_0603_6.3V6-M
2
1
13
2
10.2K_0402_1%
2
12
PGOOD
2
1
1
1
+1.35VGS_FB
AGND
{28} VDDQPWROK
@
PC5510
22U_0603_6.3V6-M
2
1
PGND_2
5
2
PGND_1
PGND_5
2
PC5516
22U_0603_6.3V6-M
2
1
3
@
+
2
PR5508
FB
PC5508
22U_0603_6.3V6-M
2
1
1
2
100K_0402_1%
PC5522
0.01U_0402_25V7K
1
2
1500P_0402_50V7-K
+1.35VGS_FB_R3
PR5505=110K-FSW=550K
PR5558
@
PC5523
2 0_0402_5% 1
2
PR5560 1
EMC_NS@
18
PC5506
22U_0603_6.3V6-M
2
1
TON
.1U_0402_10V6-K
LX_5
1
6
TON
EN
PC5521
1000P_0402_50V9-J
1
GPU_ALL_B+
2
17
+1.35VGS
1
2
VCC
LX_4
PR5506
10_0402_1%
EMC_NS@
16
1
IN_4
LX_3
2
IN_3
PR5512
1/16W_39K_1%_0402
+1.35VGS_EN
PC5520
1
2
2
0.42UH_CMME064T-R42MS1R_24A_20%
2
LX_2
1 2
IN_2
4.7U_0603_6.3V6K
PR5505
110K_0402_1%
1
2
1
PR5503
2.2_0805_5%
1
21
1 PR5504 2
30K_0402_5%
+1.35VGS_LX
11
2
9
22
PC5505
2
1
{28,30} FBVDDQ_PWR_EN
10
PC5509
22U_0603_6.3V6-M
2
1
LX_1
1
IN_1
1
PL5501
PC5515
22U_0603_6.3V6-M
2
1
2
BST
8
PU5501
EMC_NS@
1
2
PC5503
0.1U_0402_25V6
1
2
7
AOZ2264QI-20_QFN23_4X4
+5VALW
PC5502
10U_0805_25V6K
1
2
PR5502
2.2_0603_5%
2
1
PC5501
10U_0805_25V6K
GPU_ALL_B+
GDDR5 Total 14A, 5A for VRAM;9A for GPU
PC5507
22U_0603_6.3V6-M
2
1
GPU_TGP_R- {69}
1
PC5514
22U_0603_6.3V6-M
2
1
20
1
GPU_TGP_R-
PR5501
0_0603_5%
+1.35VGS_BST 1
2
GPU_TGP_R+ {69}
3
4
2
GPU_TGP_R+
1
PC5504
0.1U_0603_25V7-M
GPU_ALL_B+
@
1
+3VS
+5VALW
PR540
1
PR5839
100K_0402_1%
2 0_0402_5%
2
PC545
1
2
1.0VGS_PG {28}
3
3
1U_0402_6.3V6K
PD5803
3
PR5922 1
2
2 0_0402_5%
1
PC548
0.1U_0402_25V6
@
POK
VOUT1
VOUT2
EN
EPAD
FB
PJ511
3
4
2
2
1
2 0_0402_5%
2
2
PR5923 1
LBAT54SWT1G_SOT323-3
@
2
@
1
1
+1.0VGS
JUMP_43X79
PC547
22U_0603_6.3V6-M
0_0402_5%
VCNTL
VIN
2
8
9
1
10U_0603_10V6K
PC546
2
1
1
1
PR538
26.1K_0402_1%
1
1 2
2
PR537 JUMP_43X79
2
7
PR539
100K_0402_1%
1
6
5
GND
2
+1.2V
{28,30,51} 1V0_MAIN_EN
@
1
PJ510
PU502 APL5930CKAI-TRG_SO8
1.35VGS
FB:0.6V/1.35V
TDC=11A
ICCMAX=20A
OCP=25A
FSW=550K
4
4
LDO-1.0VGS
TDC:1A
iccmax:1.1A
FB:0.8V/1.0V
https://Dr-Bios.com
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/08/20
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
A
B
C
Cover Page
2018/09/20
Size
C
Date:
Document Number
Rev
1.0
FG541/FG741
Friday, March 01, 2019
D
Sheet
67
of
69
5
4
3
2
1
D
D
PR7501 0_0402_5%
1
2
+5VALW
NVDD_SDA
NVDD_SDA {28}
@
NVVDD_B+
PR7502
0.005_1206_1%
2
1
1
2
PC7509
330U_D2_2V_Y
1
1 2
PC7576
22U_6.3V_M_X6S_0603
2
1
PC7577
22U_6.3V_M_X6S_0603
2
1
PC7578
22U_6.3V_M_X6S_0603
2
1
PC7579
22U_6.3V_M_X6S_0603
2
1
PC7519
22U_6.3V_M_X6S_0603
2
1
VIN1
VIN6
VIN5
VIN4
VIN2
VIN3
PC7510
330U_D2_2V_Y
2
1
2
25
3
2
2
PC7516
22U_6.3V_M_X6S_0603
2
1
1
@
@
+5VALW
NVVDD_B+
DISB#
IMON
REFIN
1
NCP303150MNTWG_PQFN41_5X6
1
1
2
2
2
2
PC7539
330U_D2_2V_Y
VIN1
1
PR7599
1/8W_2.2_5%_0805
EMC_NS@
PC7538
330U_D2_2V_Y
1
NVVDD_BOOT2
25
1
19
18
17
16
15
14
13
12
11
10
PC7599
2200P_0402_50V7K
EMC_NS@
CD@
@
@
@
2
PC7573
VIN6
VIN5
VIN4
VIN2
VIN3
2
PWM
2
39
SW10
SW9
SW8
SW7
SW6
SW5
SW4
SW3
SW2
SW1
+
PC7583
22U_6.3V_M_X6S_0603
2
1
38
NVVDD_REFIN2
NCP303150MNTWG
1
PC7582
22U_6.3V_M_X6S_0603
2
1
35
NVVDD_CSP2
GL2
GL1
ZCD_EN
FAULT
+
PC7581
22U_6.3V_M_X6S_0603
2
1
NVVDD_DRON
NVVDD_REFIN2
10_0402_5%
NC2
0.22UH_CMME104T-R22MS_50A_20%
PC7580
22U_6.3V_M_X6S_0603
2
1
34
B
1
PC7549
22U_6.3V_M_X6S_0603
2
1
100K_0402_1%
2
PR7559
41
6
37
36
33
NVVDD_PHASE2
32
2
PC7548
22U_6.3V_M_X6S_0603
2
1
1
PR7556
240_0402_1%
31
@
NVVDD_PWM2
BOOT
PHASE
PL7502
1
PC7547
22U_6.3V_M_X6S_0603
2
1
1
100P_0402_50V8J
2K_0402_5%
1
0_0402_5%
2 0_0402_5%
NVVDD_TMON_R
NVVDD_CSP2
PC7535
0.22U_0603_50V7-K
NVVDD_SW2
PC7546
22U_6.3V_M_X6S_0603
2
1
PR7591 1
2
1/10W_3.9_5%_0603
2
PC7545
22U_6.3V_M_X6S_0603
2
1
1
disable phase3/4
2
PR7577
PR7528 10_0402_5%
2
NC1
NVVDD
PR7545
1
1 2
NVVDD_REFIN1
1
PC7530
PC7531
10U_25V_K_X6S_0805_H1.25
10U_25V_K_X6S_0805_H1.25
2
100K_0402_1%
2
1
PU7503
UP9632_@
1
2.2U_25V_K_X5R_0402
PGND2
PGND3
PGND4
PGND5
PGND6
PGND7
PGND8
PGND9
PGND10
PGND1
AGND
1
PR7550
130_0402_1%
430_0402_1%
2
2
PC7542
PC7537
2.2U_25V_K_X5R_0402
PR7578
0_0402_5%
@
TC7502
PAD
@
NVVDD_CSP1
1
NVVDD
PR7539
0_0402_5%
differential
PR7547
1
2
1
2
2
+5VALW
NVVDD_VREF
100P_0402_50V8J
PC7529
0.1U_0402_25V6
EMC@
PR7548
2.2_0603_5%
PR7543
300K_0402_1%
NVVDD_VCC2
430_0402_1%
PC7534
4
2
PC7533
0.01U_50V_K_X7R_0402
1
1
2
@
1000P_0402_50V7K
Total OCP 166A
Perphase OCP 71A
2
PC7543
C
@
2
PR7552
2
2
20.5K_0402_1%
2
PR7549
1
+
91K_0402_1%
2
41
PR7546
1
PR7557
PC7508
2200P_0402_50V7K
EMC_NS@
PR7535
1
PR7537
NVVDD_CSREF
21
1
PC7527
1
2
2
NVVDD_CSSUM
22
PC7541
2200P_0402_50V7K
+5VALW
1
@
NCP303150MNTWG_PQFN41_5X6
2
NVVDD_CSCOMP
23
33.2K_0402_1%
2
FSW:400K
2 0_0402_5% 0_0402_5% PR7507 @ NVVDD_TMON_R
1
2
1
1
NVVDD_ILIM
24
PC7536
REFIN
+
2
2
NVVDD_TMON
PR7533 1
NVVDD_IOUT
25
1
1
2
PR7532
1
NVVDD_FSW
27
26
1
IMON
0.22UH_CMME104T-R22MS_50A_20%
PR7519
1/8W_2.2_5%_0805
EMC_NS@
NVVDD_DIFF
28
1
CSP1
CSP2
CSP3
NC4
29
2
PR7553
53.6K_0402_1%
39
PC7572
0.1U_0402_25V6
33
NVVDD_PHASE1
32
NVVDD_FB
2
GND
38
NVVDD_REFIN1
PWM
DISB#
1
19
18
17
16
15
14
13
12
11
10
SW10
SW9
SW8
SW7
SW6
SW5
SW4
SW3
SW2
SW1
2
1K_0402_1%
20
11
1
NVVDD_PWM1
CSP4
CSREF
49.9_0402_1%
2
2
NCP303150MNTWG
1
CSSUM
PR7531
2200P_25V_K_X7R_0402
30
PR7527
1
330P_0402_50V7K
1
PWM3/PHTH2
PWM2/PHTH3
PC7521
1
2
2
PR7530 1/16W_3.3K_1%_0402
1
2
1
2
CSCOMP
2
GL2
GL1
ZCD_EN
FAULT
NVVDD
PC7505
PL7501
0.22U_0603_50V7-K
NVVDD_SW1
1
2
31
33
34
32
VSP
SCL
VSN
VCC
SDA
35
36
38
39
40
37
EN
PSI
PGOOD
PWM4/PHTH1
NCP81611MNTXG_QFN40_5X5
2
2
2
ILIM
PR7542
39.2K_0402_1%
B
IOUT
LPC2
1
1
1
10
PR7540
20K_0402_1%
PR7538
6.65K_0402_1%
NCP81611MNTXG
18
NVVDD_PWM2
LPC1
19
9
TMON
17
NVVDD_PWM3
FSW
I2C
16
8
DIFF
SS
NVVDD_CSP1
7
FB
VRAMP
NVVDD_CSP2
NVVDD_LPC2
VREF
NVVDD_CSP4
NVVDD_PWM4
6
NC3
Cold Boot: 1phase
5
NVVDD_LPC1
15
Warm Boot: 1phase
3
4
NVVDD_I2C
NC2
2
NVVDD_SS
1
2
PR7572
26.1K_0402_1%
1
2
PR7573
100K_0402_1%
1
2
PR7534
78.7K_0402_1%
1
2
PR7536 54.9K_0402_1%
COMP
NC1
I2C ADD:0X40
1
33P_0402_50V8J
PC7524
1
REFIN
14
2 0.01U_50V_K_X7R_0402
NVVDD_VRAMP
Soft Start; 600us
1
13
1
NVVDD_VREF
DRON
PC7522
PWM1/PHTH4
NVVDD_REFIN
12
4700P_25V_K_X7R_0402
2
PWM_VID
VID_BUFF
PU7501
BOOT
PHASE
NC2
NVVDD_Vin_R+ {69}
1/10W_3.9_5%_0603
2
PC7515
22U_6.3V_M_X6S_0603
2
1
NVVDD_CSP1
PC7520
PR7524
20.5K_0402_1%
{69} NVVDD_Vin_RPR7510
1
PC7514
22U_6.3V_M_X6S_0603
2
1
35
30
29
28
26
27
NVVDD_VCC1
NVVDD_DRON
{30}
PC7501
0.1U_0402_25V6
EMC@
1
NVVDD_VDD_SENSE
34
NC1
PC7502
PC7503
10U_25V_K_X6S_0805_H1.25
10U_25V_K_X6S_0805_H1.25
PGND2
PGND3
PGND4
PGND5
PGND6
PGND7
PGND8
PGND9
PGND10
PGND1
AGND
@
NVVDD_PWM1
2 0_0402_5%
NVVDD_COMP
2
2
NVVDD_DRON
PR7529
1
& lt; 15A: 1 phase CCM
PR7522 1
2 0_0402_5%
NVVDD_TMON_R
41
6
37
36
NVVDD
100_0402_1%
PR7571
4.32K_0402_1%
PR7526
1
1
PC7523
& lt; 5A: 1 phase DCM
PR7593 1
2
31
3
2
1
PC7512
1000P_0402_50V7K
NVVDD_VSP
4
1
1
@
0_0402_5%
PR7579
3
7
8
9
20
21
22
23
24
40
5
2
PR7521
1
NVDD_VID_BUFF
{30}
PVCC
1
NVVDD_VSS_SENSE
1/16W_6.19K_1%_0402
1/16W_309_1%_0402
2
2
PR7525
1
1K_0402_5%
2
1
2 0_0402_5%
1
PR7518 1
1
1
2
PR7523
4700P_25V_K_X7R_0402
2
16.5K_0402_1%
1
TC7501
PAD
2
100_0402_1%
NVVDD_VSN
NVVDD_PWM_VID_R
2 0_0402_5%
@
1
PU7502
UP9632_@
2
NVVDD_B+
2
2
2
1
NVVDD_PWRGD_R
PC7513
1
PC7528
0.01U_50V_K_X7R_0402
@
PR7516
NVVDD_PSI_R
PR7580
0_0402_5%
VCC
2
2
PR7504
0_0402_5%
Place close to
GPU pins
100P_0402_50V8J
{28} NVVDD_PSI
2
2.2U_25V_K_X5R_0402
PVCC
PR7520 1
OPT18@
2 0_0402_5%
{28} NVVDD_PWM_VID
@
PR7586 stuff
PR7586 un-stuff
2 0_0402_5%
PR7517 1
N18: MID PSI
N17: HIG PSI
1
NVVDD_VCC
1
1
1
2
PR7515 1
{28} NVVDD_PWRGD
C
PR7586
10K_0402_5%
PC7511
2.2U_25V_K_X5R_0402
1
VCC
2
NVVDD
PC7506
PR7594
10K_0402_5%
1
2
4.32K_0402_1%
PR7514
10K_0402_5%
PC7507
2.2U_25V_K_X5R_0402
+5VALW
NVVDD_BOOT1
1
PR7505
2.2_0603_5%
2
PC7588
.1U_0402_10V6-K
2
+1.8VS_AON
GPU_ALL_B+
4
2
7
8
9
20
21
22
23
24
40
5
2
@
PR7585
2 1
2
1
PR7583
0_0402_5%
31
2
1
PD5801
25.5K_0402_1% NVVDD_EN_R
2
1
LBAT54SWT1G_SOT323-3
+1.8VS_AON
1
PR7513
2.2_0603_5%
@
PR7508
1
{28,29} NVVDD_EN
PC7518
22U_6.3V_M_X6S_0603
2
1
NVDD_SCL {28}
+5VALW
PC7517
22U_6.3V_M_X6S_0603
2
1
0_0402_5% NVDD_SCL
2
30
29
28
26
27
PR7503
1
{49,58,59} EC_SMB_CK1
PC7544
22U_6.3V_M_X6S_0603
2
1
{49,58,59} EC_SMB_DA1
0.1U_0402_25V6
A
A
Issued Date
Title
LC Future Center Secret Data
Security Classification
2015/08/20
Deciphered Date
Cover Page
2018/09/20
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Size
Document Number
Custom
Date:
5
4
3
https://Dr-Bios.com
2
1
Re v
0.1
FG541/FG741
Friday, March 01, 2019
Sheet
68
of
69
5
4
3
2
1
D
D
+3VALW
+3VS
+3VS
1
1
+3VALW
2
0_0402_5%
1
2
1
@
0_0402_5%
PR7653
@
0_0402_5%
2
PR7654
2
PR7619
2
PR7655
0_0402_5%
1
2
OVRM_SKIP
GND_FET
1
PR7614
2
ADC_IN_P {28}
ADC_IN_N {28}
47P_0402_50V8J
@
PR7611
0_0402_5%
1
PC7607
0.015U_25V_K_X7R_0402
@
2
+3VS
PR7617 1
CM_REF: 0.845V
1000P_0402_50V7K
PC7611
1
2
SH_O1
BS_OK
MUX_SEL
2 0_0402_5%
2
@
1
@
PR7612
0_0402_5%
2
2
PC7609
47P_0402_50V8J
@
1
PC7610
47P_0402_50V8J
TC7601
1
UPI---US5650
PR7605=487
PR7613=487
PR7610=357ohm for Lower 70W 215 for 75W to 90W 165 for 100W to 110W
PR7614=357ohm for Lower 70W 215 for 75W to 90W 165 for 100W to 110W
PR7603=324K
PR7602=75K
PR7609=75K
PC7604=1nF
PC7608=1nF
B
2
ADC_IN_P
ADC_IN_N
1
{28} ADC_MUX_SEL
2 1
PC7605
US5650QQKI_WQFN32_4X4
PR7677
0_0402_5%
C
365K_0402_1% PR7607 1/16W_680K_1%_0402
1
PR7630 1
BG_REF_OUT
=1.3V
BS_REF: 0.05V
1000P_0402_50V7K
2
1
PC7628
0.015U_25V_K_X7R_0402
PR7620 10K_0402_1%
1
2
BS_REF
BG_REF_OUT
CM_REF_IN
2
PR7615
10K_0402_1%
2
GND_FET
2
2
2
PC7608
1000P_0402_50V7K
1_/16W_357_1%_0402
1
2
1 2
PR7613
1/16W_487_+-1%_0402
1
OVRM_EN
PR7606
1
1
1
PR7610
PR7609
75K_0402_1%
BS_OK_Threshold: 6V
PR7652 1
SH_IN_Nx
1
PR7608 100_0402_1%
1
2
1
2 SH_IN_N1
3 SH_IN_P1
4 BS_IN1
5 SH_IN_N2
6 SH_IN_P2
7 BS_IN2
8 SH_O2
10 CUSTOM8
2 0_0402_5%
11 SH_O3
12 BS_IN3
13 SH_IN_P3
2 0_0402_5%
14 SH_IN_N3
15 BS_IN4
16 SH_IN_P4
9 SH_IN_N4
GND_FET
25
26
28
31
24
23
22
21
20
19
18
17
32
30
29
2
2
SKIP
MODE
ENABLE
CUSTOM31
BS_REF
BG_REF_OUT
CM_REF_IN
CUSTOM21
DIFF_OUT_P
DIFF_OUT_N
CUSTOM18
SH_O4
SH_O1
BS_OK
MUX_SEL
1_/16W_357_1%_0402
1
SH_IN_N1
SH_IN_P1
BS_IN1
SH_IN_N2
SH_IN_P2
BS_IN2
SH_O2
VCC
2
PC7604
1000P_0402_50V7K
PR7698 0_0402_5%
{68} NVVDD_Vin_R+
PC7603
1K_0402_1%
10K_0402_1%
2
1
GND
{68} NVVDD_Vin_R-
1
2
1
1/16W_324K_1%_0402
@
PU7601
33
2
GND_FET
1
PR7605
1/16W_487_+-1%_0402
PR7645
27
@
1 2
BS_OK_Threshold: 6V
C
1000P_0402_50V7K
2
PR7604
1
0_0402_5%
2
PR7603
PR7641
10K_0402_1%
1
PR7618
1
PC7602
1
2
1
PR7602
75K_0402_1%
@
2
PR7601 100_0402_1%
1
2
{67} GPU_TGP_R+
PR7640
10K_0402_1%
1
1
2
PC7601
1U_0402_16V6K
PR7699 0_0402_5%
1
2
{67} GPU_TGP_R-
PAD
@
B
ON---NCP45491
PR7605=649
PR7613=649
PR7610=475ohm for lower 70W 287 for 75W to 90W 221 for 100W to 110W
PR7614=475ohm for lower 70W 287 for 75W to 90W 221 for 100W to 110W
PR7603=243K
PR7602=75K
PR7609=75K
PC7604=1nF
PC7608=1nF
A
Title
LC Future Center Secret Data
Security Classification
Issued Date
A
2015/08/20
Deciphered Date
https://Dr-Bios.com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R & D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
5
4
3
2
Cover Page
2018/09/20
Size
C
Date:
Document Number
Rev
0.1
FG541/FG741
Wednesday, February 27, 2019
1
Sheet
69
of
69